add XiUOS/stm32f103-nano board support, task create function has some bugs

Ubiquitous/XiUOS/Makefile

@@ -5,7 +5,7 @@ MAKEFLAGS += --no-print-directory
 .PHONY:COMPILE_APP COMPILE_KERNEL
 
 
-support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator cortex-m4-emulator ok1052-c gapuino
+support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator cortex-m4-emulator ok1052-c gapuino stm32f103-nano
 SRC_DIR:=
 
 export BOARD ?=kd233

Ubiquitous/XiUOS/arch/arm/Makefile

@@ -5,6 +5,10 @@ ifeq ($(CONFIG_BOARD_CORTEX_M3_EVB),y)
 SRC_DIR +=cortex-m3
 endif
 
+ifeq ($(CONFIG_BOARD_STM32F103_NANO),y)
+SRC_DIR +=cortex-m3
+endif
+
 ifeq ($(CONFIG_BOARD_STM32F407_EVB),y)
 SRC_DIR +=cortex-m4
 endif

Ubiquitous/XiUOS/arch/arm/cortex-m3/Makefile

@@ -1,3 +1,11 @@
-SRC_FILES := boot.c  interrupt.c interrupt_vector.S
+ifeq ($(CONFIG_BOARD_CORTEX_M3_EVB),y)
+SRC_FILES := boot.c
+endif
+
+ifeq ($(CONFIG_BOARD_STM32F103_NANO),y)
+SRC_FILES := boot.S
+endif
+
+SRC_FILES += interrupt.c interrupt_vector.S
 
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiUOS/arch/arm/cortex-m3/boot.S

@@ -0,0 +1,114 @@
+/**
+  *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
+  * @file      startup_stm32f103xb.s
+  * @author    MCD Application Team
+  * @brief     STM32F103xB Devices vector table for Atollic toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system   
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/**
+* @file boot.S
+* @brief derived from ST standard peripheral library
+* @version 1.1 
+* @author AIIT XUOS Lab
+* @date 2021-11-30
+*/
+
+/*************************************************
+File name: boot.S
+Description: Reset and init function
+Others: 
+History: 
+1. Date: 2021-11-30
+Author: AIIT XUOS Lab
+Modification: 
+1. take startup_stm32f103xb.s for XiUOS
+*************************************************/
+
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ  BootRAM, 0xF108F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r3, =_sidata
+  ldr r3, [r3, r1]
+  str r3, [r0, r1]
+  adds r1, r1, #4
+
+LoopCopyDataInit:
+  ldr r0, =_sdata
+  ldr r3, =_edata
+  adds r2, r0, r1
+  cmp r2, r3
+  bcc CopyDataInit
+  ldr r2, =_sbss
+  b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs r3, #0
+  str r3, [r2], #4
+
+LoopFillZerobss:
+  ldr r3, = _ebss
+  cmp r2, r3
+  bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+    bl  SystemInit
+
+/* Call the application's entry point.*/
+  bl entry
+  bx lr
+.size Reset_Handler, .-Reset_Handler

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210730193816

@@ -1,59 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_STM32F407_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "stm32f407-st-discovery feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "/XiUOS_stm32f407-st-discovery_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134238

@@ -1,59 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "stm32f407-st-discovery feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "/XiUOS_stm32f407-st-discovery_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134239

@@ -1,59 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "stm32f407-st-discovery feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "/XiUOS_stm32f407-st-discovery_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134303

@@ -1,59 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "cortex-m4 emulator feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "/XiUOS_stm32f407-st-discovery_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134546

@@ -1,63 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "cortex-m4 emulator feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "//XiUOS_cortex-m4-emulator_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-    config __STACKSIZE__
-        int "stack size for interrupt"
-        default 4096
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134553

@@ -1,63 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "cortex-m4 emulator feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "//XiUOS_cortex-m4-emulator_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-    config __STACKSIZE__
-        int "stack size for interrupt"
-        default 4096
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134554

@@ -1,63 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "cortex-m4 emulator feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "//XiUOS_cortex-m4-emulator_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-    config __STACKSIZE__
-        int "stack size for interrupt"
-        default 4096
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134556

@@ -1,63 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "cortex-m4 emulator feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "//XiUOS_cortex-m4-emulator_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-    config __STACKSIZE__
-        int "stack size for interrupt"
-        default 4096
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134557

@@ -1,63 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "cortex-m4 emulator feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "//XiUOS_cortex-m4-emulator_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-    config __STACKSIZE__
-        int "stack size for interrupt"
-        default 4096
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134558

@@ -1,63 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "cortex-m4 emulator feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "//XiUOS_cortex-m4-emulator_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-    config __STACKSIZE__
-        int "stack size for interrupt"
-        default 4096
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134605

@@ -1,63 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "cortex-m4 emulator feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "//XiUOS_cortex-m4-emulator_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-    config __STACKSIZE__
-        int "stack size for interrupt"
-        default 4096
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134606

@@ -1,63 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "cortex-m4 emulator feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "//XiUOS_cortex-m4-emulator_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-    config __STACKSIZE__
-        int "stack size for interrupt"
-        default 4096
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134607

@@ -1,63 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "cortex-m4 emulator feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "//XiUOS_cortex-m4-emulator_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-    config __STACKSIZE__
-        int "stack size for interrupt"
-        default 4096
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825134608

@@ -1,63 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "cortex-m4 emulator feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "//XiUOS_cortex-m4-emulator_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-    config __STACKSIZE__
-        int "stack size for interrupt"
-        default 4096
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825135732

@@ -1,63 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "cortex-m4 emulator feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "//XiUOS_cortex-m4-emulator_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-    config __STACKSIZE__
-        int "stack size for interrupt"
-        default 4096
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825140237

@@ -1,59 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "cortex-m4 emulator feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "//XiUOS_cortex-m4-emulator_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825140238

@@ -1,59 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "cortex-m4 emulator feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "//XiUOS_cortex-m4-emulator_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825140304

@@ -1,63 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "cortex-m4 emulator feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "//XiUOS_cortex-m4-emulator_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-    config __STACKSIZE__
-        int "stack size for interrupt"
-        default 4096
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825140305

@@ -1,63 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "cortex-m4 emulator feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "//XiUOS_cortex-m4-emulator_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-    config __STACKSIZE__
-        int "stack size for interrupt"
-        default 4096
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/Kconfig_20210825140911

@@ -1,63 +0,0 @@
-mainmenu "XiUOS Project Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config KERNEL_DIR
-    string
-    option env="KERNEL_ROOT"
-    default "../.."
-
-config BOARD_CORTEX_M4_EVB
-    bool
-    select  ARCH_ARM
-    default y
-
-source "$KERNEL_DIR/arch/Kconfig"
-
-menu "cortex-m4 emulator feature"
-    source "$BSP_DIR/third_party_driver/Kconfig"
-    
-    menu "config default board resources"
-        menu "config board app name"
-            config BOARD_APP_NAME
-                string "config board app name"
-                default "/XiUOS_cortex-m4-emulator_app.bin"
-        endmenu
-
-        menu "config board service table"
-            config SERVICE_TABLE_ADDRESS
-                hex "board service table address"
-                default 0x20000000
-        endmenu
-
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
-    endmenu
-
-    config __STACKSIZE__
-        int "stack size for interrupt"
-        default 4096
-
-endmenu
-
-
-menu "Hardware feature"
-source "$KERNEL_DIR/resources/Kconfig"
-endmenu
-
-source "$KERNEL_DIR/Kconfig"

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210825111355.c

@@ -1,125 +0,0 @@
-/*
-* Copyright (c) 2020 AIIT XUOS Lab
-* XiUOS is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*        http://license.coscl.org.cn/MulanPSL2
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-* See the Mulan PSL v2 for more details.
-*/
-
-/**
-* @file board.c
-* @brief support stm32f407-st-discovery-board init configure and start-up
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2021-04-25
-*/
-
-/*************************************************
-File name: board.c
-Description: support stm32f407-st-discovery-board init configure and driver/task/... init
-Others: 
-History: 
-1. Date: 2021-04-25
-Author: AIIT XUOS Lab
-Modification: 
-1. support stm32f407-st-discovery-board InitBoardHardware
-*************************************************/
-
-#include <xiuos.h>
-#include "hardware_rcc.h"
-#include "board.h"
-#include "connect_usart.h"
-#include "misc.h"
-#include <xs_service.h>
-
-
-
-static void ClockConfiguration()
-{
-    int cr,cfgr,pllcfgr;
-    int cr1,cfgr1,pllcfgr1;
-    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-    PWR->CR |= PWR_CR_VOS;
-    RCC_HSEConfig(RCC_HSE_ON);
-    if (RCC_WaitForHSEStartUp() == SUCCESS)
-    {
-        RCC_HCLKConfig(RCC_SYSCLK_Div1);
-        RCC_PCLK2Config(RCC_HCLK_Div2);
-        RCC_PCLK1Config(RCC_HCLK_Div4);
-        RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
-
-        RCC_PLLCmd(ENABLE);
-        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
-
-        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
-        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
-        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
-    }
-    SystemCoreClockUpdate();
-}
-
-void NVIC_Configuration(void)
-{
-#ifdef  VECT_TAB_RAM
-    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
-#else
-    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
-#endif
-
-    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
-}
-
-void  SysTickConfiguration(void)
-{
-    RCC_ClocksTypeDef  rcc_clocks;
-    uint32         cnts;
-
-    RCC_GetClocksFreq(&rcc_clocks);
-
-    cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
-    cnts = cnts / 8;
-
-    SysTick_Config(cnts);
-    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
-}
-
-void SysTick_Handler(int irqn, void *arg)
-{
-
-    TickAndTaskTimesliceUpdate();
-
-}
-DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
-
-
-void InitBoardHardware()
-{
-	int i = 0;
-	int ret = 0;
-    ClockConfiguration();
-
-    NVIC_Configuration();
-
-    SysTickConfiguration();
-#ifdef BSP_USING_UART
-	Stm32HwUsartInit();
-#endif
-#ifdef KERNEL_CONSOLE
-    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
-
-    RCC_ClocksTypeDef  rcc_clocks;
-    RCC_GetClocksFreq(&rcc_clocks);
-    KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
-
-    KPrintf("\nconsole init completed.\n");
-    KPrintf("board initialization......\n");
-#endif
-    
-    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
-	
-}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210825132137.h

@@ -1,78 +0,0 @@
-/*
-* Copyright (c) 2020 AIIT XUOS Lab
-* XiUOS is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*        http://license.coscl.org.cn/MulanPSL2
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-* See the Mulan PSL v2 for more details.
-*/
-
-/**
-* @file board.h
-* @brief define stm32f407-st-discovery-board init configure and start-up function
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2021-04-25
-*/
-
-/*************************************************
-File name: board.h
-Description: define stm32f407-st-discovery-board board init function and struct
-Others: 
-History: 
-1. Date: 2021-04-25
-Author: AIIT XUOS Lab
-Modification: 
-1. define stm32f407-st-discovery-board InitBoardHardware
-2. define stm32f407-st-discovery-board data and bss struct
-*************************************************/
-
-#ifndef BOARD_H
-#define BOARD_H
-
-#include <stdint.h>
-
-extern int __stack_end__;
-extern unsigned int g_service_table_start;
-extern unsigned int g_service_table_end;
-
-#define SURPORT_MPU
-
-#define MEMORY_START_ADDRESS (&__stack_end__)
-#define MEM_OFFSET         128
-#define MEMORY_END_ADDRESS      (0x20000000 + MEM_OFFSET * 1024)
-
-
-#ifdef SEPARATE_COMPILE
-typedef int (*main_t)(int argc, char *argv[]);
-typedef void (*exit_t)(void);
-struct userspace_s
-{
-  main_t    us_entrypoint;
-  exit_t    us_taskquit;
-  uintptr_t us_textstart;
-  uintptr_t us_textend;
-  uintptr_t us_datasource;
-  uintptr_t us_datastart;
-  uintptr_t us_dataend;
-  uintptr_t us_bssstart;
-  uintptr_t us_bssend;
-  uintptr_t us_heapend;
-};
-#define USERSPACE (( struct userspace_s *)(0x08080000))
-
-#ifndef SERVICE_TABLE_ADDRESS
-#define SERVICE_TABLE_ADDRESS    (0x20000000)
-#endif
-
-#define USER_SRAM_SIZE         64
-#define USER_MEMORY_START_ADDRESS (USERSPACE->us_bssend)
-#define USER_MEMORY_END_ADDRESS   (0x10000000 + USER_SRAM_SIZE * 1024)
-#endif
-
-void InitBoardHardware(void);
-
-#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210825135326.c

@@ -1,125 +0,0 @@
-/*
-* Copyright (c) 2020 AIIT XUOS Lab
-* XiUOS is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*        http://license.coscl.org.cn/MulanPSL2
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-* See the Mulan PSL v2 for more details.
-*/
-
-/**
-* @file board.c
-* @brief support stm32f407-st-discovery-board init configure and start-up
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2021-04-25
-*/
-
-/*************************************************
-File name: board.c
-Description: support stm32f407-st-discovery-board init configure and driver/task/... init
-Others: 
-History: 
-1. Date: 2021-04-25
-Author: AIIT XUOS Lab
-Modification: 
-1. support stm32f407-st-discovery-board InitBoardHardware
-*************************************************/
-
-#include <xiuos.h>
-#include "hardware_rcc.h"
-#include "board.h"
-#include "connect_usart.h"
-#include "misc.h"
-#include <xs_service.h>
-
-
-
-static void ClockConfiguration()
-{
-    int cr,cfgr,pllcfgr;
-    int cr1,cfgr1,pllcfgr1;
-    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-    PWR->CR |= PWR_CR_VOS;
-    RCC_HSEConfig(RCC_HSE_ON);
-    if (RCC_WaitForHSEStartUp() == SUCCESS)
-    {
-        RCC_HCLKConfig(RCC_SYSCLK_Div1);
-        RCC_PCLK2Config(RCC_HCLK_Div2);
-        RCC_PCLK1Config(RCC_HCLK_Div4);
-        RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
-
-        RCC_PLLCmd(ENABLE);
-        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
-
-        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
-        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
-        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
-    }
-    SystemCoreClockUpdate();
-}
-
-void NVIC_Configuration(void)
-{
-#ifdef  VECT_TAB_RAM
-    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
-#else
-    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
-#endif
-
-    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
-}
-
-void  SysTickConfiguration(void)
-{
-    RCC_ClocksTypeDef  rcc_clocks;
-    uint32         cnts;
-
-    RCC_GetClocksFreq(&rcc_clocks);
-
-    cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
-    cnts = cnts / 8;
-
-    SysTick_Config(cnts);
-    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
-}
-
-void SysTick_Handler(int irqn, void *arg)
-{
-
-    TickAndTaskTimesliceUpdate();
-
-}
-DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
-
-
-void InitBoardHardware()
-{
-	int i = 0;
-	int ret = 0;
-    ClockConfiguration();
-
-    NVIC_Configuration();
-
-    SysTickConfiguration();
-#ifdef BSP_USING_UART
-	InitHwUsart();
-#endif
-#ifdef KERNEL_CONSOLE
-    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
-
-    RCC_ClocksTypeDef  rcc_clocks;
-    RCC_GetClocksFreq(&rcc_clocks);
-    KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
-
-    KPrintf("\nconsole init completed.\n");
-    KPrintf("board initialization......\n");
-#endif
-    
-    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
-	
-}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210825135622.c

@@ -1,125 +0,0 @@
-/*
-* Copyright (c) 2020 AIIT XUOS Lab
-* XiUOS is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*        http://license.coscl.org.cn/MulanPSL2
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-* See the Mulan PSL v2 for more details.
-*/
-
-/**
-* @file board.c
-* @brief support stm32f407-st-discovery-board init configure and start-up
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2021-04-25
-*/
-
-/*************************************************
-File name: board.c
-Description: support stm32f407-st-discovery-board init configure and driver/task/... init
-Others: 
-History: 
-1. Date: 2021-04-25
-Author: AIIT XUOS Lab
-Modification: 
-1. support stm32f407-st-discovery-board InitBoardHardware
-*************************************************/
-
-#include <xiuos.h>
-#include "hardware_rcc.h"
-#include "board.h"
-#include "connect_usart.h"
-#include "misc.h"
-#include <xs_service.h>
-
-
-
-static void ClockConfiguration()
-{
-    int cr,cfgr,pllcfgr;
-    int cr1,cfgr1,pllcfgr1;
-    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-    PWR->CR |= PWR_CR_VOS;
-    RCC_HSEConfig(RCC_HSE_ON);
-    if (RCC_WaitForHSEStartUp() == SUCCESS)
-    {
-        RCC_HCLKConfig(RCC_SYSCLK_Div1);
-        RCC_PCLK2Config(RCC_HCLK_Div2);
-        RCC_PCLK1Config(RCC_HCLK_Div4);
-        RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
-
-        RCC_PLLCmd(ENABLE);
-        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
-
-        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
-        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
-        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
-    }
-    SystemCoreClockUpdate();
-}
-
-void NVIC_Configuration(void)
-{
-#ifdef  VECT_TAB_RAM
-    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
-#else
-    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
-#endif
-
-    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
-}
-
-void  SysTickConfiguration(void)
-{
-    RCC_ClocksTypeDef  rcc_clocks;
-    uint32         cnts;
-
-    RCC_GetClocksFreq(&rcc_clocks);
-
-    cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
-    cnts = cnts / 8;
-
-    SysTick_Config(cnts);
-    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
-}
-
-void SysTick_Handler(int irqn, void *arg)
-{
-
-    TickAndTaskTimesliceUpdate();
-
-}
-DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
-
-
-void InitBoardHardware()
-{
-	int i = 0;
-	int ret = 0;
-    ClockConfiguration();
-
-    NVIC_Configuration();
-
-    SysTickConfiguration();
-#ifdef BSP_USING_UART
-	InitHwUsart();
-#endif
-#ifdef KERNEL_CONSOLE
-    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
-
-    RCC_ClocksTypeDef  rcc_clocks;
-    RCC_GetClocksFreq(&rcc_clocks);
-    KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
-
-    KPrintf("\nconsole init completed.\n");
-    KPrintf("board initialization......\n");
-#endif
-    
-    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
-	
-}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210825135623.c

@@ -1,125 +0,0 @@
-/*
-* Copyright (c) 2020 AIIT XUOS Lab
-* XiUOS is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*        http://license.coscl.org.cn/MulanPSL2
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-* See the Mulan PSL v2 for more details.
-*/
-
-/**
-* @file board.c
-* @brief support stm32f407-st-discovery-board init configure and start-up
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2021-04-25
-*/
-
-/*************************************************
-File name: board.c
-Description: support stm32f407-st-discovery-board init configure and driver/task/... init
-Others: 
-History: 
-1. Date: 2021-04-25
-Author: AIIT XUOS Lab
-Modification: 
-1. support stm32f407-st-discovery-board InitBoardHardware
-*************************************************/
-
-#include <xiuos.h>
-#include "hardware_rcc.h"
-#include "board.h"
-#include "connect_usart.h"
-#include "misc.h"
-#include <xs_service.h>
-
-
-
-static void ClockConfiguration()
-{
-    int cr,cfgr,pllcfgr;
-    int cr1,cfgr1,pllcfgr1;
-    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-    PWR->CR |= PWR_CR_VOS;
-    RCC_HSEConfig(RCC_HSE_ON);
-    if (RCC_WaitForHSEStartUp() == SUCCESS)
-    {
-        RCC_HCLKConfig(RCC_SYSCLK_Div1);
-        RCC_PCLK2Config(RCC_HCLK_Div2);
-        RCC_PCLK1Config(RCC_HCLK_Div4);
-        RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
-
-        RCC_PLLCmd(ENABLE);
-        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
-
-        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
-        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
-        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
-    }
-    SystemCoreClockUpdate();
-}
-
-void NVIC_Configuration(void)
-{
-#ifdef  VECT_TAB_RAM
-    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
-#else
-    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
-#endif
-
-    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
-}
-
-void  SysTickConfiguration(void)
-{
-    RCC_ClocksTypeDef  rcc_clocks;
-    uint32         cnts;
-
-    RCC_GetClocksFreq(&rcc_clocks);
-
-    cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
-    cnts = cnts / 8;
-
-    SysTick_Config(cnts);
-    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
-}
-
-void SysTick_Handler(int irqn, void *arg)
-{
-
-    TickAndTaskTimesliceUpdate();
-
-}
-DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
-
-
-void InitBoardHardware()
-{
-	int i = 0;
-	int ret = 0;
-    ClockConfiguration();
-
-    NVIC_Configuration();
-
-    SysTickConfiguration();
-#ifdef BSP_USING_UART
-	InitHwUsart();
-#endif
-#ifdef KERNEL_CONSOLE
-    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
-
-    RCC_ClocksTypeDef  rcc_clocks;
-    RCC_GetClocksFreq(&rcc_clocks);
-    KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
-
-    KPrintf("\nconsole init completed.\n");
-    KPrintf("board initialization......\n");
-#endif
-    
-    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
-	
-}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210825140908.c

@@ -1,125 +0,0 @@
-/*
-* Copyright (c) 2020 AIIT XUOS Lab
-* XiUOS is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*        http://license.coscl.org.cn/MulanPSL2
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-* See the Mulan PSL v2 for more details.
-*/
-
-/**
-* @file board.c
-* @brief support stm32f407-st-discovery-board init configure and start-up
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2021-04-25
-*/
-
-/*************************************************
-File name: board.c
-Description: support stm32f407-st-discovery-board init configure and driver/task/... init
-Others: 
-History: 
-1. Date: 2021-04-25
-Author: AIIT XUOS Lab
-Modification: 
-1. support stm32f407-st-discovery-board InitBoardHardware
-*************************************************/
-
-#include <xiuos.h>
-#include "hardware_rcc.h"
-#include "board.h"
-#include "connect_usart.h"
-#include "misc.h"
-#include <xs_service.h>
-
-
-
-static void ClockConfiguration()
-{
-    int cr,cfgr,pllcfgr;
-    int cr1,cfgr1,pllcfgr1;
-    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-    PWR->CR |= PWR_CR_VOS;
-    RCC_HSEConfig(RCC_HSE_ON);
-    if (RCC_WaitForHSEStartUp() == SUCCESS)
-    {
-        RCC_HCLKConfig(RCC_SYSCLK_Div1);
-        RCC_PCLK2Config(RCC_HCLK_Div2);
-        RCC_PCLK1Config(RCC_HCLK_Div4);
-        RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
-
-        RCC_PLLCmd(ENABLE);
-        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
-
-        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
-        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
-        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
-    }
-    SystemCoreClockUpdate();
-}
-
-void NVIC_Configuration(void)
-{
-#ifdef  VECT_TAB_RAM
-    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
-#else
-    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
-#endif
-
-    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
-}
-
-void  SysTickConfiguration(void)
-{
-    RCC_ClocksTypeDef  rcc_clocks;
-    uint32         cnts;
-
-    RCC_GetClocksFreq(&rcc_clocks);
-
-    cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
-    cnts = cnts / 8;
-
-    SysTick_Config(cnts);
-    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
-}
-
-void SysTick_Handler(int irqn, void *arg)
-{
-
-    TickAndTaskTimesliceUpdate();
-
-}
-DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
-
-
-void InitBoardHardware()
-{
-	int i = 0;
-	int ret = 0;
-    ClockConfiguration();
-
-    NVIC_Configuration();
-
-    SysTickConfiguration();
-#ifdef BSP_USING_UART
-	InitHwUsart();
-#endif
-#ifdef KERNEL_CONSOLE
-    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
-
-    RCC_ClocksTypeDef  rcc_clocks;
-    RCC_GetClocksFreq(&rcc_clocks);
-    KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
-
-    KPrintf("\nconsole init completed.\n");
-    KPrintf("board initialization......\n");
-#endif
-    
-    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
-	
-}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210825210606.h

@@ -1,78 +0,0 @@
-/*
-* Copyright (c) 2020 AIIT XUOS Lab
-* XiUOS is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*        http://license.coscl.org.cn/MulanPSL2
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-* See the Mulan PSL v2 for more details.
-*/
-
-/**
-* @file board.h
-* @brief define stm32f407-st-discovery-board init configure and start-up function
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2021-04-25
-*/
-
-/*************************************************
-File name: board.h
-Description: define stm32f407-st-discovery-board board init function and struct
-Others: 
-History: 
-1. Date: 2021-04-25
-Author: AIIT XUOS Lab
-Modification: 
-1. define stm32f407-st-discovery-board InitBoardHardware
-2. define stm32f407-st-discovery-board data and bss struct
-*************************************************/
-
-#ifndef BOARD_H
-#define BOARD_H
-
-#include <stdint.h>
-
-extern int __stack_end__;
-extern unsigned int g_service_table_start;
-extern unsigned int g_service_table_end;
-
-#define SURPORT_MPU
-
-#define MEMORY_START_ADDRESS (&__stack_end__)
-#define MEM_OFFSET         128
-#define MEMORY_END_ADDRESS      (0x20000000 + MEM_OFFSET * 1024)
-
-
-#ifdef SEPARATE_COMPILE
-typedef int (*main_t)(int argc, char *argv[]);
-typedef void (*exit_t)(void);
-struct userspace_s
-{
-  main_t    us_entrypoint;
-  exit_t    us_taskquit;
-  uintptr_t us_textstart;
-  uintptr_t us_textend;
-  uintptr_t us_datasource;
-  uintptr_t us_datastart;
-  uintptr_t us_dataend;
-  uintptr_t us_bssstart;
-  uintptr_t us_bssend;
-  uintptr_t us_heapend;
-};
-#define USERSPACE (( struct userspace_s *)(0x08080000))
-
-#ifndef SERVICE_TABLE_ADDRESS
-#define SERVICE_TABLE_ADDRESS    (0x20000000)
-#endif
-
-#define USER_SRAM_SIZE         64
-#define USER_MEMORY_START_ADDRESS (USERSPACE->us_bssend)
-#define USER_MEMORY_END_ADDRESS   (0x10000000 + USER_SRAM_SIZE * 1024)
-#endif
-
-void InitBoardHardware(void);
-
-#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210826182559.c

@@ -1,125 +0,0 @@
-/*
-* Copyright (c) 2020 AIIT XUOS Lab
-* XiUOS is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*        http://license.coscl.org.cn/MulanPSL2
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-* See the Mulan PSL v2 for more details.
-*/
-
-/**
-* @file board.c
-* @brief support stm32f407-st-discovery-board init configure and start-up
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2021-04-25
-*/
-
-/*************************************************
-File name: board.c
-Description: support stm32f407-st-discovery-board init configure and driver/task/... init
-Others: 
-History: 
-1. Date: 2021-04-25
-Author: AIIT XUOS Lab
-Modification: 
-1. support stm32f407-st-discovery-board InitBoardHardware
-*************************************************/
-
-#include <xiuos.h>
-#include "hardware_rcc.h"
-#include "board.h"
-#include "connect_usart.h"
-#include "misc.h"
-#include <xs_service.h>
-
-
-
-static void ClockConfiguration()
-{
-    int cr,cfgr,pllcfgr;
-    int cr1,cfgr1,pllcfgr1;
-    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-    PWR->CR |= PWR_CR_VOS;
-    RCC_HSEConfig(RCC_HSE_ON);
-    if (RCC_WaitForHSEStartUp() == SUCCESS)
-    {
-        RCC_HCLKConfig(RCC_SYSCLK_Div1);
-        RCC_PCLK2Config(RCC_HCLK_Div2);
-        RCC_PCLK1Config(RCC_HCLK_Div4);
-        RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
-
-        RCC_PLLCmd(ENABLE);
-        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
-
-        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
-        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
-        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
-    }
-    SystemCoreClockUpdate();
-}
-
-void NVIC_Configuration(void)
-{
-#ifdef  VECT_TAB_RAM
-    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
-#else
-    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
-#endif
-
-    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
-}
-
-void  SysTickConfiguration(void)
-{
-    RCC_ClocksTypeDef  rcc_clocks;
-    uint32         cnts;
-
-    RCC_GetClocksFreq(&rcc_clocks);
-
-    cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
-    cnts = cnts / 8;
-
-    SysTick_Config(cnts);
-    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
-}
-
-void SysTick_Handler(int irqn, void *arg)
-{
-
-    TickAndTaskTimesliceUpdate();
-
-}
-DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
-
-
-void InitBoardHardware()
-{
-	int i = 0;
-	int ret = 0;
-    ClockConfiguration();
-
-    NVIC_Configuration();
-
-    SysTickConfiguration();
-#ifdef BSP_USING_UART
-	Stm32HwUsartInit();
-#endif
-#ifdef KERNEL_CONSOLE
-    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
-
-    RCC_ClocksTypeDef  rcc_clocks;
-    RCC_GetClocksFreq(&rcc_clocks);
-    KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
-
-    KPrintf("\nconsole init completed.\n");
-    KPrintf("board initialization......\n");
-#endif
-    
-    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
-	
-}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210826182600.c

@@ -1,125 +0,0 @@
-/*
-* Copyright (c) 2020 AIIT XUOS Lab
-* XiUOS is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*        http://license.coscl.org.cn/MulanPSL2
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-* See the Mulan PSL v2 for more details.
-*/
-
-/**
-* @file board.c
-* @brief support stm32f407-st-discovery-board init configure and start-up
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2021-04-25
-*/
-
-/*************************************************
-File name: board.c
-Description: support stm32f407-st-discovery-board init configure and driver/task/... init
-Others: 
-History: 
-1. Date: 2021-04-25
-Author: AIIT XUOS Lab
-Modification: 
-1. support stm32f407-st-discovery-board InitBoardHardware
-*************************************************/
-
-#include <xiuos.h>
-#include "hardware_rcc.h"
-#include "board.h"
-#include "connect_usart.h"
-#include "misc.h"
-#include <xs_service.h>
-
-
-
-static void ClockConfiguration()
-{
-    int cr,cfgr,pllcfgr;
-    int cr1,cfgr1,pllcfgr1;
-    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-    PWR->CR |= PWR_CR_VOS;
-    RCC_HSEConfig(RCC_HSE_ON);
-    if (RCC_WaitForHSEStartUp() == SUCCESS)
-    {
-        RCC_HCLKConfig(RCC_SYSCLK_Div1);
-        RCC_PCLK2Config(RCC_HCLK_Div2);
-        RCC_PCLK1Config(RCC_HCLK_Div4);
-        RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
-
-        RCC_PLLCmd(ENABLE);
-        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
-
-        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
-        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
-        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
-    }
-    SystemCoreClockUpdate();
-}
-
-void NVIC_Configuration(void)
-{
-#ifdef  VECT_TAB_RAM
-    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
-#else
-    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
-#endif
-
-    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
-}
-
-void  SysTickConfiguration(void)
-{
-    RCC_ClocksTypeDef  rcc_clocks;
-    uint32         cnts;
-
-    RCC_GetClocksFreq(&rcc_clocks);
-
-    cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
-    cnts = cnts / 8;
-
-    SysTick_Config(cnts);
-    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
-}
-
-void SysTick_Handler(int irqn, void *arg)
-{
-
-    TickAndTaskTimesliceUpdate();
-
-}
-DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
-
-
-void InitBoardHardware()
-{
-	int i = 0;
-	int ret = 0;
-    ClockConfiguration();
-
-    NVIC_Configuration();
-
-    SysTickConfiguration();
-#ifdef BSP_USING_UART
-	Stm32HwUsartInit();
-#endif
-#ifdef KERNEL_CONSOLE
-    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
-
-    RCC_ClocksTypeDef  rcc_clocks;
-    RCC_GetClocksFreq(&rcc_clocks);
-    KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
-
-    KPrintf("\nconsole init completed.\n");
-    KPrintf("board initialization......\n");
-#endif
-    
-    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
-	
-}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/board_20210826182601.c

@@ -1,125 +0,0 @@
-/*
-* Copyright (c) 2020 AIIT XUOS Lab
-* XiUOS is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*        http://license.coscl.org.cn/MulanPSL2
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-* See the Mulan PSL v2 for more details.
-*/
-
-/**
-* @file board.c
-* @brief support stm32f407-st-discovery-board init configure and start-up
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2021-04-25
-*/
-
-/*************************************************
-File name: board.c
-Description: support stm32f407-st-discovery-board init configure and driver/task/... init
-Others: 
-History: 
-1. Date: 2021-04-25
-Author: AIIT XUOS Lab
-Modification: 
-1. support stm32f407-st-discovery-board InitBoardHardware
-*************************************************/
-
-#include <xiuos.h>
-#include "hardware_rcc.h"
-#include "board.h"
-#include "connect_usart.h"
-#include "misc.h"
-#include <xs_service.h>
-
-
-
-static void ClockConfiguration()
-{
-    int cr,cfgr,pllcfgr;
-    int cr1,cfgr1,pllcfgr1;
-    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-    PWR->CR |= PWR_CR_VOS;
-    RCC_HSEConfig(RCC_HSE_ON);
-    if (RCC_WaitForHSEStartUp() == SUCCESS)
-    {
-        RCC_HCLKConfig(RCC_SYSCLK_Div1);
-        RCC_PCLK2Config(RCC_HCLK_Div2);
-        RCC_PCLK1Config(RCC_HCLK_Div4);
-        RCC_PLLConfig(RCC_PLLSource_HSE, 8, 336, 2, 7);
-
-        RCC_PLLCmd(ENABLE);
-        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
-
-        FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
-        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
-        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
-    }
-    SystemCoreClockUpdate();
-}
-
-void NVIC_Configuration(void)
-{
-#ifdef  VECT_TAB_RAM
-    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
-#else
-    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
-#endif
-
-    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
-}
-
-void  SysTickConfiguration(void)
-{
-    RCC_ClocksTypeDef  rcc_clocks;
-    uint32         cnts;
-
-    RCC_GetClocksFreq(&rcc_clocks);
-
-    cnts = (uint32)rcc_clocks.HCLK_Frequency / TICK_PER_SECOND;
-    cnts = cnts / 8;
-
-    SysTick_Config(cnts);
-    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
-}
-
-void SysTick_Handler(int irqn, void *arg)
-{
-
-    TickAndTaskTimesliceUpdate();
-
-}
-DECLARE_HW_IRQ(SysTick_IRQn, SysTick_Handler, NONE);
-
-
-void InitBoardHardware()
-{
-	int i = 0;
-	int ret = 0;
-    ClockConfiguration();
-
-    NVIC_Configuration();
-
-    SysTickConfiguration();
-#ifdef BSP_USING_UART
-	Stm32HwUsartInit();
-#endif
-#ifdef KERNEL_CONSOLE
-    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
-
-    RCC_ClocksTypeDef  rcc_clocks;
-    RCC_GetClocksFreq(&rcc_clocks);
-    KPrintf("HCLK_Frequency %d, PCLK1_Frequency %d, PCLK2_Frequency %d, SYSCLK_Frequency %d\n", rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency, rcc_clocks.SYSCLK_Frequency);
-
-    KPrintf("\nconsole init completed.\n");
-    KPrintf("board initialization......\n");
-#endif
-    
-    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
-	
-}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/config_20210824125750.mk

@@ -1,17 +0,0 @@
-export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
-
-export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
-export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb  -gdwarf-2
-export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
-export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
-
-export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
-
-
-export DEFINES := -DHAVE_CCONFIG_H  -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO
-
-export USING_NEWLIB =1
-export USING_VFS = 1
-export USING_SPI = 1
-export ARCH = arm
-export USING_LORA = 1

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/config_20210825140049.mk

@@ -1,14 +0,0 @@
-export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
-
-export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
-export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb  -gdwarf-2
-export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
-export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
-
-export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
-
-
-export DEFINES := -DHAVE_CCONFIG_H  -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO
-
-export ARCH = arm
-export USING_LORA = 1

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/config_20210825140050.mk

@@ -1,14 +0,0 @@
-export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
-
-export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
-export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb  -gdwarf-2
-export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
-export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
-
-export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
-
-
-export DEFINES := -DHAVE_CCONFIG_H  -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO
-
-export ARCH = arm
-export USING_LORA = 1

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/config_20210825140057.mk

@@ -1,14 +0,0 @@
-export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
-
-export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
-export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb  -gdwarf-2
-export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
-export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
-
-export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
-
-
-export DEFINES := -DHAVE_CCONFIG_H  
-
-export ARCH = arm
-export USING_LORA = 1

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/config_20210825140058.mk

@@ -1,14 +0,0 @@
-export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
-
-export CFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror
-export AFLAGS := -c -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb  -gdwarf-2
-export LFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f407-st-discovery.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
-export CXXFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror
-
-export APPLFLAGS := -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
-
-
-export DEFINES := -DHAVE_CCONFIG_H  
-
-export ARCH = arm
-export USING_LORA = 1

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/third_party_driver/include/connect_usart_20210730193816.h

@@ -1,63 +0,0 @@
-/*
-* Copyright (c) 2020 AIIT XUOS Lab
-* XiUOS is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*        http://license.coscl.org.cn/MulanPSL2
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-* See the Mulan PSL v2 for more details.
-*/
- 
-/**
-* @file connect_usart.h
-* @brief define stm32f407-st-discovery-board usart function and struct
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2021-04-25
-*/
-
-#ifndef CONNECT_USART_H
-#define CONNECT_USART_H
-
-#include <device.h>
-#include "hardware_usart.h"
-#include "hardware_dma.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define KERNEL_CONSOLE_BUS_NAME       SERIAL_BUS_NAME_1
-#define KERNEL_CONSOLE_DRV_NAME       SERIAL_DRV_NAME_1
-#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
-
-struct UsartHwCfg
-{
-    USART_TypeDef *uart_device;
-    IRQn_Type irq;
-};
-
-struct Stm32Usart
-{
-    struct Stm32UsartDma
-    {
-        DMA_Stream_TypeDef *RxStream;
-        uint32 RxCh;
-        uint32 RxFlag;
-        uint8 RxIrqCh;
-        x_size_t SettingRecvLen;
-        x_size_t LastRecvIndex;
-    } dma;
-
-    struct SerialBus serial_bus;
-};
-
-int Stm32HwUsartInit(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/third_party_driver/uart/connect_usart_20210730193816.c

@@ -1,858 +0,0 @@
-/*
- * Copyright (c) 2020 RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- */
-
-/**
-* @file connect_usart.c
-* @brief support stm32f407-st-discovery-board usart function and register to bus framework
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2021-04-25
-*/
-
-/*************************************************
-File name: connect_uart.c
-Description: support stm32f407-st-discovery-board usart configure and uart bus register function
-Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_usart.c for references
-                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
-History: 
-1. Date: 2021-04-25
-Author: AIIT XUOS Lab
-Modification: 
-1. support stm32f407-st-discovery-board usart configure, write and read
-2. support stm32f407-st-discovery-board usart bus device and driver register
-*************************************************/
-
-#include "stm32f4xx.h"
-#include "board.h"
-#include "misc.h"
-#include "connect_usart.h"
-#include "hardware_gpio.h"
-#include "hardware_rcc.h"
-
-/* UART GPIO define. */
-#define UART1_GPIO_TX       GPIO_Pin_6
-#define UART1_TX_PIN_SOURCE GPIO_PinSource6
-#define UART1_GPIO_RX       GPIO_Pin_7
-#define UART1_RX_PIN_SOURCE GPIO_PinSource7
-#define UART1_GPIO          GPIOB
-#define UART1_GPIO_RCC      RCC_AHB1Periph_GPIOB
-#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
-
-#define UART2_GPIO_TX       GPIO_Pin_2
-#define UART2_TX_PIN_SOURCE GPIO_PinSource2
-#define UART2_GPIO_RX       GPIO_Pin_3
-#define UART2_RX_PIN_SOURCE GPIO_PinSource3
-#define UART2_GPIO          GPIOA
-#define UART2_GPIO_RCC      RCC_AHB1Periph_GPIOA
-#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
-
-#define UART3_GPIO_TX       GPIO_Pin_8
-#define UART3_TX_PIN_SOURCE GPIO_PinSource8
-#define UART3_GPIO_RX       GPIO_Pin_9
-#define UART3_RX_PIN_SOURCE GPIO_PinSource9
-#define UART3_GPIO          GPIOD
-#define UART3_GPIO_RCC      RCC_AHB1Periph_GPIOD
-#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
-
-#define UART4_GPIO_TX       GPIO_Pin_10
-#define UART4_TX_PIN_SOURCE GPIO_PinSource10
-#define UART4_GPIO_RX       GPIO_Pin_11
-#define UART4_RX_PIN_SOURCE GPIO_PinSource11
-#define UART4_GPIO          GPIOC
-#define UART4_GPIO_RCC      RCC_AHB1Periph_GPIOC
-#define RCC_APBPeriph_UART4 RCC_APB1Periph_UART4
-
-#define UART5_GPIO_TX       GPIO_Pin_12
-#define UART5_TX_PIN_SOURCE GPIO_PinSource12
-#define UART5_GPIO_RX       GPIO_Pin_2
-#define UART5_RX_PIN_SOURCE GPIO_PinSource2
-#define UART5_TX            GPIOC
-#define UART5_RX            GPIOD
-#define UART5_GPIO_RCC_TX   RCC_AHB1Periph_GPIOC
-#define UART5_GPIO_RCC_RX   RCC_AHB1Periph_GPIOD
-#define RCC_APBPeriph_UART5 RCC_APB1Periph_UART5
-
-#define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
-#define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
-
-static void RCCConfiguration(void)
-{
-#ifdef BSP_USING_USART1
-    RCC_AHB1PeriphClockCmd(UART1_GPIO_RCC, ENABLE);
-    RCC_APB2PeriphClockCmd(RCC_APBPeriph_UART1, ENABLE);
-#endif
-
-#ifdef BSP_USING_USART2
-    RCC_AHB1PeriphClockCmd(UART2_GPIO_RCC, ENABLE);
-    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART2, ENABLE);
-#endif
-
-#ifdef BSP_USING_USART3
-    RCC_AHB1PeriphClockCmd(UART3_GPIO_RCC, ENABLE);
-    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART3, ENABLE);
-#endif
-
-#ifdef BSP_USING_UART4
-    RCC_AHB1PeriphClockCmd(UART4_GPIO_RCC, ENABLE);
-    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART4, ENABLE);
-#endif
-
-#ifdef BSP_USING_UART5
-    RCC_AHB1PeriphClockCmd(UART5_GPIO_RCC_TX | UART5_GPIO_RCC_RX, ENABLE);
-    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART5, ENABLE);
-#endif
-}
-
-static void GPIOConfiguration(void)
-{
-    GPIO_InitTypeDef gpio_initstructure;
-
-    gpio_initstructure.GPIO_Mode  = GPIO_Mode_AF;
-    gpio_initstructure.GPIO_OType = GPIO_OType_PP;
-    gpio_initstructure.GPIO_PuPd  = GPIO_PuPd_UP;
-    gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz;
-
-#ifdef BSP_USING_USART1
-    gpio_initstructure.GPIO_Pin = UART1_GPIO_RX | UART1_GPIO_TX;
-    GPIO_PinAFConfig(UART1_GPIO, UART1_TX_PIN_SOURCE, GPIO_AF_USART1);
-    GPIO_PinAFConfig(UART1_GPIO, UART1_RX_PIN_SOURCE, GPIO_AF_USART1);    
-    
-    GPIO_Init(UART1_GPIO, &gpio_initstructure);
-#endif
-
-#ifdef BSP_USING_USART2
-    gpio_initstructure.GPIO_Pin = UART2_GPIO_RX | UART2_GPIO_TX;
-    GPIO_PinAFConfig(UART2_GPIO, UART2_TX_PIN_SOURCE, GPIO_AF_USART2);
-    GPIO_PinAFConfig(UART2_GPIO, UART2_RX_PIN_SOURCE, GPIO_AF_USART2);
-    
-    GPIO_Init(UART2_GPIO, &gpio_initstructure);
-#endif
-
-#ifdef BSP_USING_USART3
-    gpio_initstructure.GPIO_Pin = UART3_GPIO_TX | UART3_GPIO_RX;
-    GPIO_PinAFConfig(UART3_GPIO, UART3_TX_PIN_SOURCE, GPIO_AF_USART3);
-    GPIO_PinAFConfig(UART3_GPIO, UART3_RX_PIN_SOURCE, GPIO_AF_USART3);
-    
-    GPIO_Init(UART3_GPIO, &gpio_initstructure);
-#endif
-
-#ifdef BSP_USING_UART4
-    gpio_initstructure.GPIO_Pin = UART4_GPIO_TX | UART4_GPIO_RX;
-    GPIO_PinAFConfig(UART4_GPIO, UART4_TX_PIN_SOURCE, GPIO_AF_UART4);
-    GPIO_PinAFConfig(UART4_GPIO, UART4_RX_PIN_SOURCE, GPIO_AF_UART4);
-    
-    GPIO_Init(UART4_GPIO, &gpio_initstructure);
-#endif
-
-#ifdef BSP_USING_UART5
-    gpio_initstructure.GPIO_Pin = UART5_GPIO_TX;
-    GPIO_PinAFConfig(UART5_TX, UART5_TX_PIN_SOURCE, GPIO_AF_UART5); 
-    GPIO_Init(UART5_TX, &gpio_initstructure);
-    
-    gpio_initstructure.GPIO_Pin = UART5_GPIO_RX;
-    GPIO_PinAFConfig(UART5_RX, UART5_RX_PIN_SOURCE, GPIO_AF_UART5);
-    GPIO_Init(UART5_RX, &gpio_initstructure);
-#endif
-}
-
-static void NVIC_Configuration(IRQn_Type irq)
-{
-    NVIC_InitTypeDef NVIC_InitStructure;
-
-    NVIC_InitStructure.NVIC_IRQChannel = irq;
-    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
-    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-    NVIC_Init(&NVIC_InitStructure);
-}
-
-static void DmaUartConfig(struct Stm32UsartDma *dma, USART_TypeDef *uart_device, uint32_t SettingRecvLen, void *mem_base_addr)
-{   
-    DMA_InitTypeDef DMA_InitStructure;
-
-    dma->SettingRecvLen = SettingRecvLen;
-    DMA_DeInit(dma->RxStream);
-    while (DMA_GetCmdStatus(dma->RxStream) != DISABLE);
-    DMA_InitStructure.DMA_Channel = dma->RxCh;
-    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(uart_device->DR);
-    DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)mem_base_addr;
-    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
-    DMA_InitStructure.DMA_BufferSize = dma->SettingRecvLen;
-    DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-    DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-    DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
-    DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
-    DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-    DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
-    DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
-    DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
-    DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
-    DMA_Init(dma->RxStream, &DMA_InitStructure);
-}
-
-static void DMAConfiguration(struct SerialHardwareDevice *serial_dev, USART_TypeDef *uart_device)
-{
-    struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, serial_bus);
-    struct Stm32UsartDma *dma = &serial->dma; 
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
-
-    NVIC_InitTypeDef NVIC_InitStructure;
-
-    USART_ITConfig(uart_device, USART_IT_IDLE , ENABLE);
-
-    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
-    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
-
-    DmaUartConfig(dma, uart_device, serial_cfg->data_cfg.serial_buffer_size, serial_dev->serial_fifo.serial_rx->serial_rx_buffer);
-
-    DMA_ClearFlag(dma->RxStream, dma->RxFlag);
-    DMA_ITConfig(dma->RxStream, DMA_IT_TC, ENABLE);
-    USART_DMACmd(uart_device, USART_DMAReq_Rx, ENABLE);
-    DMA_Cmd(dma->RxStream, ENABLE);
-
-    NVIC_InitStructure.NVIC_IRQChannel = dma->RxIrqCh;
-    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-    NVIC_Init(&NVIC_InitStructure);
-}
-
-static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
-{
-    struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
-    struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
-
-    if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
-        data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
-    }
-
-    if((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
-        data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
-    }
-
-    if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
-        data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
-    }
-
-    if((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
-        data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
-    }
-
-    if((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
-        data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
-    }
-
-    if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
-        data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
-    }
-
-    if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
-        data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
-    }
-}
-
-static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
-{
-    NULL_PARAM_CHECK(serial_drv);
-
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-
-    if (configure_info->private_data) {
-        struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
-        SerialCfgParamCheck(serial_cfg, serial_cfg_new);
-    }
-
-    USART_InitTypeDef USART_InitStructure;
-
-    USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate;
-
-    if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_8) {
-        USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-    } else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) {
-        USART_InitStructure.USART_WordLength = USART_WordLength_9b;
-    }
-
-    if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1){
-        USART_InitStructure.USART_StopBits = USART_StopBits_1;
-    } else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) {
-        USART_InitStructure.USART_StopBits = USART_StopBits_2;
-    }
-
-    if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE) {
-        USART_InitStructure.USART_Parity = USART_Parity_No;
-    } else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD) {
-        USART_InitStructure.USART_Parity = USART_Parity_Odd;
-    } else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) {
-        USART_InitStructure.USART_Parity = USART_Parity_Even;
-    }
-
-    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-    USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-    USART_Init(serial_hw_cfg->uart_device, &USART_InitStructure);
-
-    USART_Cmd(serial_hw_cfg->uart_device, ENABLE);
-
-    return EOK;
-}
-
-static uint32 Stm32SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
-{
-    NULL_PARAM_CHECK(serial_drv);
-
-    struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-    struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
-
-    switch (serial_operation_cmd)
-    {
-        case OPER_CLR_INT:
-            UART_DISABLE_IRQ(serial_hw_cfg->irq);
-            USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, DISABLE);
-            break;
-        case OPER_SET_INT:
-            UART_ENABLE_IRQ(serial_hw_cfg->irq);
-            USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, ENABLE);
-            break;
-        case OPER_CONFIG :
-            if (SIGN_OPER_DMA_RX == serial_dev_param->serial_set_mode){
-                DMAConfiguration(serial_dev, serial_hw_cfg->uart_device);
-            }
-    }
-
-    return EOK;
-}
-
-static int Stm32SerialPutchar(struct SerialHardwareDevice *serial_dev, char c)
-{
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-
-    while (!(serial_hw_cfg->uart_device->SR & USART_FLAG_TXE));
-    serial_hw_cfg->uart_device->DR = c;
-
-    return EOK;
-}
-
-static int Stm32SerialGetchar(struct SerialHardwareDevice *serial_dev)
-{
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-
-    int ch = -1;
-    if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) {
-        ch = serial_hw_cfg->uart_device->DR & 0xff;
-    }
-
-    return ch;
-}
-
-static void DmaUartRxIdleIsr(struct SerialHardwareDevice *serial_dev, struct Stm32UsartDma *dma, USART_TypeDef *uart_device)
-{
-    x_base level = CriticalAreaLock();
-
-    x_size_t recv_total_index = dma->SettingRecvLen - DMA_GetCurrDataCounter(dma->RxStream);
-    x_size_t recv_len = recv_total_index - dma->LastRecvIndex;
-    dma->LastRecvIndex = recv_total_index;
-    CriticalAreaUnLock(level);
-
-    if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
-
-    USART_ReceiveData(uart_device);
-}
-
-static void DmaRxDoneIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
-{
-    struct Stm32UsartDma *dma = &serial->dma; 
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-
-    if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET) {
-        x_base level = CriticalAreaLock();
-
-        x_size_t recv_len = dma->SettingRecvLen - dma->LastRecvIndex;
-        dma->LastRecvIndex = 0;
-        CriticalAreaUnLock(level);
-
-        if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
-
-        DMA_ClearFlag(dma->RxStream, dma->RxFlag);
-    }
-}
-
-static void UartIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
-{
-    struct Stm32UsartDma *dma = &serial->dma; 
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-
-    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) {
-        SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
-        USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_RXNE);
-    }
-    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET) {
-        DmaUartRxIdleIsr(serial_dev, dma, serial_hw_cfg->uart_device);
-    }
-    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET) {
-        USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_TC);
-    }
-    if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET) {
-        USART_ReceiveData(serial_hw_cfg->uart_device);
-    }
-}
-
-#ifdef BSP_USING_USART1
-struct Stm32Usart serial_1;
-struct SerialDriver serial_driver_1;
-struct SerialHardwareDevice serial_device_1;
-
-static const struct Stm32UsartDma usart_dma_1 =
-{
-    DMA2_Stream5,
-    DMA_Channel_4,
-    DMA_FLAG_TCIF5,
-    DMA2_Stream5_IRQn,
-    0,
-    0,
-};
-
-void USART1_IRQHandler(int irq_num, void *arg)
-{
-    UartIsr(&serial_1, &serial_driver_1, &serial_device_1);
-}
-DECLARE_HW_IRQ(USART1_IRQn, USART1_IRQHandler, NONE);
-
-void DMA2_Stream5_IRQHandler(int irq_num, void *arg) {
-    DmaRxDoneIsr(&serial_1, &serial_driver_1, &serial_device_1);
-}
-DECLARE_HW_IRQ(DMA2_Stream5_IRQn, DMA2_Stream5_IRQHandler, NONE);
-#endif
-
-#ifdef BSP_USING_USART2
-struct Stm32Usart serial_2;
-struct SerialDriver serial_driver_2;
-struct SerialHardwareDevice serial_device_2;
-
-static const struct Stm32UsartDma usart_dma_2 =
-{
-    DMA1_Stream5,
-    DMA_Channel_4,
-    DMA_FLAG_TCIF5,
-    DMA1_Stream5_IRQn,
-    0,
-    0,
-};
-
-void USART2_IRQHandler(int irq_num, void *arg)
-{
-    UartIsr(&serial_2, &serial_driver_2, &serial_device_2);
-}
-DECLARE_HW_IRQ(USART2_IRQn, USART2_IRQHandler, NONE);
-
-void DMA1_Stream5_IRQHandler(int irq_num, void *arg) {
-    DmaRxDoneIsr(&serial_2, &serial_driver_2, &serial_device_2);
-}
-DECLARE_HW_IRQ(DMA1_Stream5_IRQn, DMA1_Stream5_IRQHandler, NONE);
-#endif
-
-#ifdef BSP_USING_USART3
-struct Stm32Usart serial_3;
-struct SerialDriver serial_driver_3;
-struct SerialHardwareDevice serial_device_3;
-
-static const struct Stm32UsartDma usart_dma_3 =
-{
-    DMA1_Stream1,
-    DMA_Channel_4,
-    DMA_FLAG_TCIF1,
-    DMA1_Stream1_IRQn,
-    0,
-    0,
-};
-
-void USART3_IRQHandler(int irq_num, void *arg)
-{
-    UartIsr(&serial_3, &serial_driver_3, &serial_device_3);
-}
-DECLARE_HW_IRQ(USART3_IRQn, USART3_IRQHandler, NONE);
-
-void DMA1_Stream1_IRQHandler(int irq_num, void *arg) {
-    DmaRxDoneIsr(&serial_3, &serial_driver_3, &serial_device_3);
-}
-DECLARE_HW_IRQ(DMA1_Stream1_IRQn, DMA1_Stream1_IRQHandler, NONE);
-#endif
-
-#ifdef BSP_USING_UART4
-struct Stm32Usart serial_4;
-struct SerialDriver serial_driver_4;
-struct SerialHardwareDevice serial_device_4;
-
-static const struct Stm32UsartDma uart_dma_4 =
-{
-    DMA1_Stream2,
-    DMA_Channel_4,
-    DMA_FLAG_TCIF2,
-    DMA1_Stream2_IRQn,
-    0,
-    0,
-};
-
-void UART4_IRQHandler(int irq_num, void *arg)
-{
-    UartIsr(&serial_4, &serial_driver_4, &serial_device_4);
-}
-DECLARE_HW_IRQ(UART4_IRQn, UART4_IRQHandler, NONE);
-
-void DMA1_Stream2_IRQHandler(int irq_num, void *arg) {
-    DmaRxDoneIsr(&serial_4, &serial_driver_4, &serial_device_4);
-}
-DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE);
-#endif
-
-#ifdef BSP_USING_UART5
-struct Stm32Usart serial_5;
-struct SerialDriver serial_driver_5;
-struct SerialHardwareDevice serial_device_5;
-
-static const struct Stm32UsartDma uart_dma_5 =
-{
-    DMA1_Stream0,
-    DMA_Channel_4,
-    DMA_FLAG_TCIF0,
-    DMA1_Stream0_IRQn,
-    0,
-    0,
-};
-
-void UART5_IRQHandler(int irq_num, void *arg)
-{
-    UartIsr(&serial_5, &serial_driver_5, &serial_device_5);
-}
-DECLARE_HW_IRQ(UART5_IRQn, UART5_IRQHandler, NONE);
-
-void DMA1_Stream0_IRQHandler(int irq_num, void *arg) {
-    DmaRxDoneIsr(&serial_5, &serial_driver_5, &serial_device_5);
-}
-DECLARE_HW_IRQ(DMA1_Stream0_IRQn, DMA1_Stream0_IRQHandler, NONE);
-#endif
-
-static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
-{
-    NULL_PARAM_CHECK(drv);
-    NULL_PARAM_CHECK(configure_info);
-
-    x_err_t ret = EOK;
-    int serial_operation_cmd;
-    struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
-
-    switch (configure_info->configure_cmd)
-    {
-        case OPE_INT:
-            ret = Stm32SerialInit(serial_drv, configure_info);
-            break;
-        case OPE_CFG:
-            serial_operation_cmd = *(int *)configure_info->private_data;
-            ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
-            break;
-        default:
-            break;
-    }
-
-    return ret;
-}
-
-static const struct SerialDataCfg data_cfg_init = 
-{
-    .serial_baud_rate = BAUD_RATE_115200,
-    .serial_data_bits = DATA_BITS_8,
-    .serial_stop_bits = STOP_BITS_1,
-    .serial_parity_mode = PARITY_NONE,
-    .serial_bit_order = BIT_ORDER_LSB,
-    .serial_invert_mode = NRZ_NORMAL,
-    .serial_buffer_size = SERIAL_RB_BUFSZ,
-};
-
-/*manage the serial device operations*/
-static const struct SerialDrvDone drv_done =
-{
-    .init = Stm32SerialInit,
-    .configure = Stm32SerialConfigure,
-};
-
-/*manage the serial device hal operations*/
-static struct SerialHwDevDone hwdev_done =
-{
-    .put_char = Stm32SerialPutchar,
-    .get_char = Stm32SerialGetchar,
-};
-
-static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
-{
-    x_err_t ret = EOK;
-
-    /*Init the serial bus */
-    ret = SerialBusInit(serial_bus, bus_name);
-    if (EOK != ret) {
-        KPrintf("hw_serial_init SerialBusInit error %d\n", ret);
-        return ERROR;
-    }
-
-    /*Init the serial driver*/
-    ret = SerialDriverInit(serial_driver, drv_name);
-    if (EOK != ret) {
-        KPrintf("hw_serial_init SerialDriverInit error %d\n", ret);
-        return ERROR;
-    }
-
-    /*Attach the serial driver to the serial bus*/
-    ret = SerialDriverAttachToBus(drv_name, bus_name);
-    if (EOK != ret) {
-        KPrintf("hw_serial_init SerialDriverAttachToBus error %d\n", ret);
-        return ERROR;
-    } 
-
-    return ret;
-}
-
-/*Attach the serial device to the serial bus*/
-static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
-{
-    x_err_t ret = EOK;
-
-    ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
-    if (EOK != ret) {
-        KPrintf("hw_serial_init SerialDeviceInit device %s error %d\n", dev_name, ret);
-        return ERROR;
-    }  
-
-    ret = SerialDeviceAttachToBus(dev_name, bus_name);
-    if (EOK != ret) {
-        KPrintf("hw_serial_init SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
-        return ERROR;
-    }  
-
-    return  ret;
-}
-
-int InitHwUsart(void)
-{
-    x_err_t ret = EOK;
-
-    RCCConfiguration();
-    GPIOConfiguration();
-
-#ifdef BSP_USING_USART1
-    static struct SerialCfgParam serial_cfg_1;
-    memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam));
-
-    static struct UsartHwCfg serial_hw_cfg_1;
-    memset(&serial_hw_cfg_1, 0, sizeof(struct UsartHwCfg));
-
-    static struct SerialDevParam serial_dev_param_1;
-    memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
-
-    serial_1.dma = usart_dma_1;
-    
-    serial_driver_1.drv_done = &drv_done;
-    serial_driver_1.configure = &Stm32SerialDrvConfigure;
-    serial_device_1.hwdev_done = &hwdev_done;
-
-    serial_cfg_1.data_cfg = data_cfg_init;
-
-    serial_hw_cfg_1.uart_device = USART1;
-    serial_hw_cfg_1.irq = USART1_IRQn;
-    serial_cfg_1.hw_cfg.private_data = (void *)&serial_hw_cfg_1;
-    serial_driver_1.private_data = (void *)&serial_cfg_1;
-
-    serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX;
-    serial_device_1.haldev.private_data = (void *)&serial_dev_param_1;
-
-    NVIC_Configuration(serial_hw_cfg_1.irq);
-
-    ret = BoardSerialBusInit(&serial_1.serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart1 error ret %u\n", ret);
-        return ERROR;
-    }
-
-    ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart1 error ret %u\n", ret);
-        return ERROR;
-    }    
-#endif
-
-#ifdef BSP_USING_USART2
-    static struct SerialCfgParam serial_cfg_2;
-    memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam));
-
-    static struct UsartHwCfg serial_hw_cfg_2;
-    memset(&serial_hw_cfg_2, 0, sizeof(struct UsartHwCfg));
-
-    static struct SerialDevParam serial_dev_param_2;
-    memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
-
-    serial_2.dma = usart_dma_2;
-    
-    serial_driver_2.drv_done = &drv_done;
-    serial_driver_2.configure = &Stm32SerialDrvConfigure;
-    serial_device_2.hwdev_done = &hwdev_done;
-
-    serial_cfg_2.data_cfg = data_cfg_init;
-
-    serial_hw_cfg_2.uart_device = USART2;
-    serial_hw_cfg_2.irq = USART2_IRQn;
-    serial_cfg_2.hw_cfg.private_data = (void *)&serial_hw_cfg_2;
-    serial_driver_2.private_data = (void *)&serial_cfg_2;
-
-    serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX;
-    serial_device_2.haldev.private_data = (void *)&serial_dev_param_2;
-
-    NVIC_Configuration(serial_hw_cfg_2.irq);
-
-    ret = BoardSerialBusInit(&serial_2.serial_bus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart2 error ret %u\n", ret);
-        return ERROR;
-    }
-
-    ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart2 error ret %u\n", ret);
-        return ERROR;
-    }    
-#endif
-
-#ifdef BSP_USING_USART3
-    static struct SerialCfgParam serial_cfg_3;
-    memset(&serial_cfg_3, 0, sizeof(struct SerialCfgParam));
-
-    static struct UsartHwCfg serial_hw_cfg_3;
-    memset(&serial_hw_cfg_3, 0, sizeof(struct UsartHwCfg));
-
-    static struct SerialDevParam serial_dev_param_3;
-    memset(&serial_dev_param_3, 0, sizeof(struct SerialDevParam));
-
-    serial_3.dma = usart_dma_3;
-    
-    serial_driver_3.drv_done = &drv_done;
-    serial_driver_3.configure = &Stm32SerialDrvConfigure;
-    serial_device_3.hwdev_done = &hwdev_done;
-
-    serial_cfg_3.data_cfg = data_cfg_init;
-
-    serial_hw_cfg_3.uart_device = USART3;
-    serial_hw_cfg_3.irq = USART3_IRQn;
-    serial_cfg_3.hw_cfg.private_data = (void *)&serial_hw_cfg_3;
-    serial_driver_3.private_data = (void *)&serial_cfg_3;
-
-    serial_dev_param_3.serial_work_mode = SIGN_OPER_INT_RX;
-    serial_device_3.haldev.private_data = (void *)&serial_dev_param_3;
-
-    NVIC_Configuration(serial_hw_cfg_3.irq);
-
-    ret = BoardSerialBusInit(&serial_3.serial_bus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart3 error ret %u\n", ret);
-        return ERROR;
-    }
-
-    ret = BoardSerialDevBend(&serial_device_3, (void *)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart3 error ret %u\n", ret);
-        return ERROR;
-    }    
-#endif
-
-#ifdef BSP_USING_UART4
-    static struct SerialCfgParam serial_cfg_4;
-    memset(&serial_cfg_4, 0, sizeof(struct SerialCfgParam));
-
-    static struct UsartHwCfg serial_hw_cfg_4;
-    memset(&serial_hw_cfg_4, 0, sizeof(struct UsartHwCfg));
-
-    static struct SerialDevParam serial_dev_param_4;
-    memset(&serial_dev_param_4, 0, sizeof(struct SerialDevParam));
-
-    serial_4.dma = uart_dma_4;
-    
-    serial_driver_4.drv_done = &drv_done;
-    serial_driver_4.configure = &Stm32SerialDrvConfigure;
-    serial_device_4.hwdev_done = &hwdev_done;
-
-    serial_cfg_4.data_cfg = data_cfg_init;
-
-    serial_hw_cfg_4.uart_device = UART4;
-    serial_hw_cfg_4.irq = UART4_IRQn;
-    serial_cfg_4.hw_cfg.private_data = (void *)&serial_hw_cfg_4;
-    serial_driver_4.private_data = (void *)&serial_cfg_4;
-
-    serial_dev_param_4.serial_work_mode = SIGN_OPER_INT_RX;
-    serial_device_4.haldev.private_data = (void *)&serial_dev_param_4;
-
-    NVIC_Configuration(serial_hw_cfg_4.irq);
-
-    ret = BoardSerialBusInit(&serial_4.serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart4 error ret %u\n", ret);
-        return ERROR;
-    }
-
-    ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart4 error ret %u\n", ret);
-        return ERROR;
-    }    
-#endif
-
-#ifdef BSP_USING_UART5
-    static struct SerialCfgParam serial_cfg_5;
-    memset(&serial_cfg_5, 0, sizeof(struct SerialCfgParam));
-
-    static struct UsartHwCfg serial_hw_cfg_5;
-    memset(&serial_hw_cfg_5, 0, sizeof(struct UsartHwCfg));
-
-    static struct SerialDevParam serial_dev_param_5;
-    memset(&serial_dev_param_5, 0, sizeof(struct SerialDevParam));
-
-    serial_5.dma = uart_dma_5;
-    
-    serial_driver_5.drv_done = &drv_done;
-    serial_driver_5.configure = &Stm32SerialDrvConfigure;
-    serial_device_5.hwdev_done = &hwdev_done;
-
-    serial_cfg_5.data_cfg = data_cfg_init;
-
-    serial_hw_cfg_5.uart_device = UART5;
-    serial_hw_cfg_5.irq = UART5_IRQn;
-    serial_cfg_5.hw_cfg.private_data = (void *)&serial_hw_cfg_5;
-    serial_driver_5.private_data = (void *)&serial_cfg_5;
-
-    serial_dev_param_5.serial_work_mode = SIGN_OPER_INT_RX;
-    serial_device_5.haldev.private_data = (void *)&serial_dev_param_5;
-
-    NVIC_Configuration(serial_hw_cfg_5.irq);
-
-    ret = BoardSerialBusInit(&serial_5.serial_bus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart5 error ret %u\n", ret);
-        return ERROR;
-    }
-
-    ret = BoardSerialDevBend(&serial_device_5, (void *)&serial_cfg_5, SERIAL_BUS_NAME_5, SERIAL_5_DEVICE_NAME_0);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart5 error ret %u\n", ret);
-        return ERROR;
-    }    
-#endif
-
-    return ret;
-}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/third_party_driver/uart/connect_usart_20210825135244.c

@@ -1,858 +0,0 @@
-/*
- * Copyright (c) 2020 RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- */
-
-/**
-* @file connect_usart.c
-* @brief support stm32f407-st-discovery-board usart function and register to bus framework
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2021-04-25
-*/
-
-/*************************************************
-File name: connect_uart.c
-Description: support stm32f407-st-discovery-board usart configure and uart bus register function
-Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_usart.c for references
-                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
-History: 
-1. Date: 2021-04-25
-Author: AIIT XUOS Lab
-Modification: 
-1. support stm32f407-st-discovery-board usart configure, write and read
-2. support stm32f407-st-discovery-board usart bus device and driver register
-*************************************************/
-
-#include "stm32f4xx.h"
-#include "board.h"
-#include "misc.h"
-#include "connect_usart.h"
-#include "hardware_gpio.h"
-#include "hardware_rcc.h"
-
-/* UART GPIO define. */
-#define UART1_GPIO_TX       GPIO_Pin_6
-#define UART1_TX_PIN_SOURCE GPIO_PinSource6
-#define UART1_GPIO_RX       GPIO_Pin_7
-#define UART1_RX_PIN_SOURCE GPIO_PinSource7
-#define UART1_GPIO          GPIOB
-#define UART1_GPIO_RCC      RCC_AHB1Periph_GPIOB
-#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
-
-#define UART2_GPIO_TX       GPIO_Pin_2
-#define UART2_TX_PIN_SOURCE GPIO_PinSource2
-#define UART2_GPIO_RX       GPIO_Pin_3
-#define UART2_RX_PIN_SOURCE GPIO_PinSource3
-#define UART2_GPIO          GPIOA
-#define UART2_GPIO_RCC      RCC_AHB1Periph_GPIOA
-#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
-
-#define UART3_GPIO_TX       GPIO_Pin_8
-#define UART3_TX_PIN_SOURCE GPIO_PinSource8
-#define UART3_GPIO_RX       GPIO_Pin_9
-#define UART3_RX_PIN_SOURCE GPIO_PinSource9
-#define UART3_GPIO          GPIOD
-#define UART3_GPIO_RCC      RCC_AHB1Periph_GPIOD
-#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
-
-#define UART4_GPIO_TX       GPIO_Pin_10
-#define UART4_TX_PIN_SOURCE GPIO_PinSource10
-#define UART4_GPIO_RX       GPIO_Pin_11
-#define UART4_RX_PIN_SOURCE GPIO_PinSource11
-#define UART4_GPIO          GPIOC
-#define UART4_GPIO_RCC      RCC_AHB1Periph_GPIOC
-#define RCC_APBPeriph_UART4 RCC_APB1Periph_UART4
-
-#define UART5_GPIO_TX       GPIO_Pin_12
-#define UART5_TX_PIN_SOURCE GPIO_PinSource12
-#define UART5_GPIO_RX       GPIO_Pin_2
-#define UART5_RX_PIN_SOURCE GPIO_PinSource2
-#define UART5_TX            GPIOC
-#define UART5_RX            GPIOD
-#define UART5_GPIO_RCC_TX   RCC_AHB1Periph_GPIOC
-#define UART5_GPIO_RCC_RX   RCC_AHB1Periph_GPIOD
-#define RCC_APBPeriph_UART5 RCC_APB1Periph_UART5
-
-#define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
-#define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
-
-static void RCCConfiguration(void)
-{
-#ifdef BSP_USING_USART1
-    RCC_AHB1PeriphClockCmd(UART1_GPIO_RCC, ENABLE);
-    RCC_APB2PeriphClockCmd(RCC_APBPeriph_UART1, ENABLE);
-#endif
-
-#ifdef BSP_USING_USART2
-    RCC_AHB1PeriphClockCmd(UART2_GPIO_RCC, ENABLE);
-    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART2, ENABLE);
-#endif
-
-#ifdef BSP_USING_USART3
-    RCC_AHB1PeriphClockCmd(UART3_GPIO_RCC, ENABLE);
-    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART3, ENABLE);
-#endif
-
-#ifdef BSP_USING_UART4
-    RCC_AHB1PeriphClockCmd(UART4_GPIO_RCC, ENABLE);
-    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART4, ENABLE);
-#endif
-
-#ifdef BSP_USING_UART5
-    RCC_AHB1PeriphClockCmd(UART5_GPIO_RCC_TX | UART5_GPIO_RCC_RX, ENABLE);
-    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART5, ENABLE);
-#endif
-}
-
-static void GPIOConfiguration(void)
-{
-    GPIO_InitTypeDef gpio_initstructure;
-
-    gpio_initstructure.GPIO_Mode  = GPIO_Mode_AF;
-    gpio_initstructure.GPIO_OType = GPIO_OType_PP;
-    gpio_initstructure.GPIO_PuPd  = GPIO_PuPd_UP;
-    gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz;
-
-#ifdef BSP_USING_USART1
-    gpio_initstructure.GPIO_Pin = UART1_GPIO_RX | UART1_GPIO_TX;
-    GPIO_PinAFConfig(UART1_GPIO, UART1_TX_PIN_SOURCE, GPIO_AF_USART1);
-    GPIO_PinAFConfig(UART1_GPIO, UART1_RX_PIN_SOURCE, GPIO_AF_USART1);    
-    
-    GPIO_Init(UART1_GPIO, &gpio_initstructure);
-#endif
-
-#ifdef BSP_USING_USART2
-    gpio_initstructure.GPIO_Pin = UART2_GPIO_RX | UART2_GPIO_TX;
-    GPIO_PinAFConfig(UART2_GPIO, UART2_TX_PIN_SOURCE, GPIO_AF_USART2);
-    GPIO_PinAFConfig(UART2_GPIO, UART2_RX_PIN_SOURCE, GPIO_AF_USART2);
-    
-    GPIO_Init(UART2_GPIO, &gpio_initstructure);
-#endif
-
-#ifdef BSP_USING_USART3
-    gpio_initstructure.GPIO_Pin = UART3_GPIO_TX | UART3_GPIO_RX;
-    GPIO_PinAFConfig(UART3_GPIO, UART3_TX_PIN_SOURCE, GPIO_AF_USART3);
-    GPIO_PinAFConfig(UART3_GPIO, UART3_RX_PIN_SOURCE, GPIO_AF_USART3);
-    
-    GPIO_Init(UART3_GPIO, &gpio_initstructure);
-#endif
-
-#ifdef BSP_USING_UART4
-    gpio_initstructure.GPIO_Pin = UART4_GPIO_TX | UART4_GPIO_RX;
-    GPIO_PinAFConfig(UART4_GPIO, UART4_TX_PIN_SOURCE, GPIO_AF_UART4);
-    GPIO_PinAFConfig(UART4_GPIO, UART4_RX_PIN_SOURCE, GPIO_AF_UART4);
-    
-    GPIO_Init(UART4_GPIO, &gpio_initstructure);
-#endif
-
-#ifdef BSP_USING_UART5
-    gpio_initstructure.GPIO_Pin = UART5_GPIO_TX;
-    GPIO_PinAFConfig(UART5_TX, UART5_TX_PIN_SOURCE, GPIO_AF_UART5); 
-    GPIO_Init(UART5_TX, &gpio_initstructure);
-    
-    gpio_initstructure.GPIO_Pin = UART5_GPIO_RX;
-    GPIO_PinAFConfig(UART5_RX, UART5_RX_PIN_SOURCE, GPIO_AF_UART5);
-    GPIO_Init(UART5_RX, &gpio_initstructure);
-#endif
-}
-
-static void NVIC_Configuration(IRQn_Type irq)
-{
-    NVIC_InitTypeDef NVIC_InitStructure;
-
-    NVIC_InitStructure.NVIC_IRQChannel = irq;
-    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
-    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-    NVIC_Init(&NVIC_InitStructure);
-}
-
-static void DmaUartConfig(struct Stm32UsartDma *dma, USART_TypeDef *uart_device, uint32_t SettingRecvLen, void *mem_base_addr)
-{   
-    DMA_InitTypeDef DMA_InitStructure;
-
-    dma->SettingRecvLen = SettingRecvLen;
-    DMA_DeInit(dma->RxStream);
-    while (DMA_GetCmdStatus(dma->RxStream) != DISABLE);
-    DMA_InitStructure.DMA_Channel = dma->RxCh;
-    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(uart_device->DR);
-    DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)mem_base_addr;
-    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
-    DMA_InitStructure.DMA_BufferSize = dma->SettingRecvLen;
-    DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-    DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-    DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
-    DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
-    DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-    DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
-    DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
-    DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
-    DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
-    DMA_Init(dma->RxStream, &DMA_InitStructure);
-}
-
-static void DMAConfiguration(struct SerialHardwareDevice *serial_dev, USART_TypeDef *uart_device)
-{
-    struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, serial_bus);
-    struct Stm32UsartDma *dma = &serial->dma; 
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
-
-    NVIC_InitTypeDef NVIC_InitStructure;
-
-    USART_ITConfig(uart_device, USART_IT_IDLE , ENABLE);
-
-    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
-    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
-
-    DmaUartConfig(dma, uart_device, serial_cfg->data_cfg.serial_buffer_size, serial_dev->serial_fifo.serial_rx->serial_rx_buffer);
-
-    DMA_ClearFlag(dma->RxStream, dma->RxFlag);
-    DMA_ITConfig(dma->RxStream, DMA_IT_TC, ENABLE);
-    USART_DMACmd(uart_device, USART_DMAReq_Rx, ENABLE);
-    DMA_Cmd(dma->RxStream, ENABLE);
-
-    NVIC_InitStructure.NVIC_IRQChannel = dma->RxIrqCh;
-    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-    NVIC_Init(&NVIC_InitStructure);
-}
-
-static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
-{
-    struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
-    struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
-
-    if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
-        data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
-    }
-
-    if((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
-        data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
-    }
-
-    if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
-        data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
-    }
-
-    if((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
-        data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
-    }
-
-    if((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
-        data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
-    }
-
-    if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
-        data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
-    }
-
-    if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
-        data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
-    }
-}
-
-static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
-{
-    NULL_PARAM_CHECK(serial_drv);
-
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-
-    if (configure_info->private_data) {
-        struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
-        SerialCfgParamCheck(serial_cfg, serial_cfg_new);
-    }
-
-    USART_InitTypeDef USART_InitStructure;
-
-    USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate;
-
-    if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_8) {
-        USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-    } else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) {
-        USART_InitStructure.USART_WordLength = USART_WordLength_9b;
-    }
-
-    if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1){
-        USART_InitStructure.USART_StopBits = USART_StopBits_1;
-    } else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) {
-        USART_InitStructure.USART_StopBits = USART_StopBits_2;
-    }
-
-    if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE) {
-        USART_InitStructure.USART_Parity = USART_Parity_No;
-    } else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD) {
-        USART_InitStructure.USART_Parity = USART_Parity_Odd;
-    } else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) {
-        USART_InitStructure.USART_Parity = USART_Parity_Even;
-    }
-
-    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-    USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-    USART_Init(serial_hw_cfg->uart_device, &USART_InitStructure);
-
-    USART_Cmd(serial_hw_cfg->uart_device, ENABLE);
-
-    return EOK;
-}
-
-static uint32 Stm32SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
-{
-    NULL_PARAM_CHECK(serial_drv);
-
-    struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-    struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
-
-    switch (serial_operation_cmd)
-    {
-        case OPER_CLR_INT:
-            UART_DISABLE_IRQ(serial_hw_cfg->irq);
-            USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, DISABLE);
-            break;
-        case OPER_SET_INT:
-            UART_ENABLE_IRQ(serial_hw_cfg->irq);
-            USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, ENABLE);
-            break;
-        case OPER_CONFIG :
-            if (SIGN_OPER_DMA_RX == serial_dev_param->serial_set_mode){
-                DMAConfiguration(serial_dev, serial_hw_cfg->uart_device);
-            }
-    }
-
-    return EOK;
-}
-
-static int Stm32SerialPutchar(struct SerialHardwareDevice *serial_dev, char c)
-{
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-
-    while (!(serial_hw_cfg->uart_device->SR & USART_FLAG_TXE));
-    serial_hw_cfg->uart_device->DR = c;
-
-    return EOK;
-}
-
-static int Stm32SerialGetchar(struct SerialHardwareDevice *serial_dev)
-{
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-
-    int ch = -1;
-    if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) {
-        ch = serial_hw_cfg->uart_device->DR & 0xff;
-    }
-
-    return ch;
-}
-
-static void DmaUartRxIdleIsr(struct SerialHardwareDevice *serial_dev, struct Stm32UsartDma *dma, USART_TypeDef *uart_device)
-{
-    x_base level = CriticalAreaLock();
-
-    x_size_t recv_total_index = dma->SettingRecvLen - DMA_GetCurrDataCounter(dma->RxStream);
-    x_size_t recv_len = recv_total_index - dma->LastRecvIndex;
-    dma->LastRecvIndex = recv_total_index;
-    CriticalAreaUnLock(level);
-
-    if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
-
-    USART_ReceiveData(uart_device);
-}
-
-static void DmaRxDoneIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
-{
-    struct Stm32UsartDma *dma = &serial->dma; 
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-
-    if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET) {
-        x_base level = CriticalAreaLock();
-
-        x_size_t recv_len = dma->SettingRecvLen - dma->LastRecvIndex;
-        dma->LastRecvIndex = 0;
-        CriticalAreaUnLock(level);
-
-        if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
-
-        DMA_ClearFlag(dma->RxStream, dma->RxFlag);
-    }
-}
-
-static void UartIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
-{
-    struct Stm32UsartDma *dma = &serial->dma; 
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-
-    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) {
-        SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
-        USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_RXNE);
-    }
-    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET) {
-        DmaUartRxIdleIsr(serial_dev, dma, serial_hw_cfg->uart_device);
-    }
-    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET) {
-        USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_TC);
-    }
-    if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET) {
-        USART_ReceiveData(serial_hw_cfg->uart_device);
-    }
-}
-
-#ifdef BSP_USING_USART1
-struct Stm32Usart serial_1;
-struct SerialDriver serial_driver_1;
-struct SerialHardwareDevice serial_device_1;
-
-static const struct Stm32UsartDma usart_dma_1 =
-{
-    DMA2_Stream5,
-    DMA_Channel_4,
-    DMA_FLAG_TCIF5,
-    DMA2_Stream5_IRQn,
-    0,
-    0,
-};
-
-void USART1_IRQHandler(int irq_num, void *arg)
-{
-    UartIsr(&serial_1, &serial_driver_1, &serial_device_1);
-}
-DECLARE_HW_IRQ(USART1_IRQn, USART1_IRQHandler, NONE);
-
-void DMA2_Stream5_IRQHandler(int irq_num, void *arg) {
-    DmaRxDoneIsr(&serial_1, &serial_driver_1, &serial_device_1);
-}
-DECLARE_HW_IRQ(DMA2_Stream5_IRQn, DMA2_Stream5_IRQHandler, NONE);
-#endif
-
-#ifdef BSP_USING_USART2
-struct Stm32Usart serial_2;
-struct SerialDriver serial_driver_2;
-struct SerialHardwareDevice serial_device_2;
-
-static const struct Stm32UsartDma usart_dma_2 =
-{
-    DMA1_Stream5,
-    DMA_Channel_4,
-    DMA_FLAG_TCIF5,
-    DMA1_Stream5_IRQn,
-    0,
-    0,
-};
-
-void USART2_IRQHandler(int irq_num, void *arg)
-{
-    UartIsr(&serial_2, &serial_driver_2, &serial_device_2);
-}
-DECLARE_HW_IRQ(USART2_IRQn, USART2_IRQHandler, NONE);
-
-void DMA1_Stream5_IRQHandler(int irq_num, void *arg) {
-    DmaRxDoneIsr(&serial_2, &serial_driver_2, &serial_device_2);
-}
-DECLARE_HW_IRQ(DMA1_Stream5_IRQn, DMA1_Stream5_IRQHandler, NONE);
-#endif
-
-#ifdef BSP_USING_USART3
-struct Stm32Usart serial_3;
-struct SerialDriver serial_driver_3;
-struct SerialHardwareDevice serial_device_3;
-
-static const struct Stm32UsartDma usart_dma_3 =
-{
-    DMA1_Stream1,
-    DMA_Channel_4,
-    DMA_FLAG_TCIF1,
-    DMA1_Stream1_IRQn,
-    0,
-    0,
-};
-
-void USART3_IRQHandler(int irq_num, void *arg)
-{
-    UartIsr(&serial_3, &serial_driver_3, &serial_device_3);
-}
-DECLARE_HW_IRQ(USART3_IRQn, USART3_IRQHandler, NONE);
-
-void DMA1_Stream1_IRQHandler(int irq_num, void *arg) {
-    DmaRxDoneIsr(&serial_3, &serial_driver_3, &serial_device_3);
-}
-DECLARE_HW_IRQ(DMA1_Stream1_IRQn, DMA1_Stream1_IRQHandler, NONE);
-#endif
-
-#ifdef BSP_USING_UART4
-struct Stm32Usart serial_4;
-struct SerialDriver serial_driver_4;
-struct SerialHardwareDevice serial_device_4;
-
-static const struct Stm32UsartDma uart_dma_4 =
-{
-    DMA1_Stream2,
-    DMA_Channel_4,
-    DMA_FLAG_TCIF2,
-    DMA1_Stream2_IRQn,
-    0,
-    0,
-};
-
-void UART4_IRQHandler(int irq_num, void *arg)
-{
-    UartIsr(&serial_4, &serial_driver_4, &serial_device_4);
-}
-DECLARE_HW_IRQ(UART4_IRQn, UART4_IRQHandler, NONE);
-
-void DMA1_Stream2_IRQHandler(int irq_num, void *arg) {
-    DmaRxDoneIsr(&serial_4, &serial_driver_4, &serial_device_4);
-}
-DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE);
-#endif
-
-#ifdef BSP_USING_UART5
-struct Stm32Usart serial_5;
-struct SerialDriver serial_driver_5;
-struct SerialHardwareDevice serial_device_5;
-
-static const struct Stm32UsartDma uart_dma_5 =
-{
-    DMA1_Stream0,
-    DMA_Channel_4,
-    DMA_FLAG_TCIF0,
-    DMA1_Stream0_IRQn,
-    0,
-    0,
-};
-
-void UART5_IRQHandler(int irq_num, void *arg)
-{
-    UartIsr(&serial_5, &serial_driver_5, &serial_device_5);
-}
-DECLARE_HW_IRQ(UART5_IRQn, UART5_IRQHandler, NONE);
-
-void DMA1_Stream0_IRQHandler(int irq_num, void *arg) {
-    DmaRxDoneIsr(&serial_5, &serial_driver_5, &serial_device_5);
-}
-DECLARE_HW_IRQ(DMA1_Stream0_IRQn, DMA1_Stream0_IRQHandler, NONE);
-#endif
-
-static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
-{
-    NULL_PARAM_CHECK(drv);
-    NULL_PARAM_CHECK(configure_info);
-
-    x_err_t ret = EOK;
-    int serial_operation_cmd;
-    struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
-
-    switch (configure_info->configure_cmd)
-    {
-        case OPE_INT:
-            ret = Stm32SerialInit(serial_drv, configure_info);
-            break;
-        case OPE_CFG:
-            serial_operation_cmd = *(int *)configure_info->private_data;
-            ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
-            break;
-        default:
-            break;
-    }
-
-    return ret;
-}
-
-static const struct SerialDataCfg data_cfg_init = 
-{
-    .serial_baud_rate = BAUD_RATE_115200,
-    .serial_data_bits = DATA_BITS_8,
-    .serial_stop_bits = STOP_BITS_1,
-    .serial_parity_mode = PARITY_NONE,
-    .serial_bit_order = BIT_ORDER_LSB,
-    .serial_invert_mode = NRZ_NORMAL,
-    .serial_buffer_size = SERIAL_RB_BUFSZ,
-};
-
-/*manage the serial device operations*/
-static const struct SerialDrvDone drv_done =
-{
-    .init = Stm32SerialInit,
-    .configure = Stm32SerialConfigure,
-};
-
-/*manage the serial device hal operations*/
-static struct SerialHwDevDone hwdev_done =
-{
-    .put_char = Stm32SerialPutchar,
-    .get_char = Stm32SerialGetchar,
-};
-
-static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
-{
-    x_err_t ret = EOK;
-
-    /*Init the serial bus */
-    ret = SerialBusInit(serial_bus, bus_name);
-    if (EOK != ret) {
-        KPrintf("hw_serial_init SerialBusInit error %d\n", ret);
-        return ERROR;
-    }
-
-    /*Init the serial driver*/
-    ret = SerialDriverInit(serial_driver, drv_name);
-    if (EOK != ret) {
-        KPrintf("hw_serial_init SerialDriverInit error %d\n", ret);
-        return ERROR;
-    }
-
-    /*Attach the serial driver to the serial bus*/
-    ret = SerialDriverAttachToBus(drv_name, bus_name);
-    if (EOK != ret) {
-        KPrintf("hw_serial_init SerialDriverAttachToBus error %d\n", ret);
-        return ERROR;
-    } 
-
-    return ret;
-}
-
-/*Attach the serial device to the serial bus*/
-static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
-{
-    x_err_t ret = EOK;
-
-    ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
-    if (EOK != ret) {
-        KPrintf("hw_serial_init SerialDeviceInit device %s error %d\n", dev_name, ret);
-        return ERROR;
-    }  
-
-    ret = SerialDeviceAttachToBus(dev_name, bus_name);
-    if (EOK != ret) {
-        KPrintf("hw_serial_init SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
-        return ERROR;
-    }  
-
-    return  ret;
-}
-
-int InitHwUsart(void)
-{
-    x_err_t ret = EOK;
-
-    RCCConfiguration();
-    GPIOConfiguration();
-
-#ifdef BSP_USING_USART1
-    static struct SerialCfgParam serial_cfg_1;
-    memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam));
-
-    static struct UsartHwCfg serial_hw_cfg_1;
-    memset(&serial_hw_cfg_1, 0, sizeof(struct UsartHwCfg));
-
-    static struct SerialDevParam serial_dev_param_1;
-    memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
-
-    serial_1.dma = usart_dma_1;
-    
-    serial_driver_1.drv_done = &drv_done;
-    serial_driver_1.configure = &Stm32SerialDrvConfigure;
-    serial_device_1.hwdev_done = &hwdev_done;
-
-    serial_cfg_1.data_cfg = data_cfg_init;
-
-    serial_hw_cfg_1.uart_device = USART1;
-    serial_hw_cfg_1.irq = USART1_IRQn;
-    serial_cfg_1.hw_cfg.private_data = (void *)&serial_hw_cfg_1;
-    serial_driver_1.private_data = (void *)&serial_cfg_1;
-
-    serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX;
-    serial_device_1.haldev.private_data = (void *)&serial_dev_param_1;
-
-    NVIC_Configuration(serial_hw_cfg_1.irq);
-
-    ret = BoardSerialBusInit(&serial_1.serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart1 error ret %u\n", ret);
-        return ERROR;
-    }
-
-    ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart1 error ret %u\n", ret);
-        return ERROR;
-    }    
-#endif
-
-#ifdef BSP_USING_USART2
-    static struct SerialCfgParam serial_cfg_2;
-    memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam));
-
-    static struct UsartHwCfg serial_hw_cfg_2;
-    memset(&serial_hw_cfg_2, 0, sizeof(struct UsartHwCfg));
-
-    static struct SerialDevParam serial_dev_param_2;
-    memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
-
-    serial_2.dma = usart_dma_2;
-    
-    serial_driver_2.drv_done = &drv_done;
-    serial_driver_2.configure = &Stm32SerialDrvConfigure;
-    serial_device_2.hwdev_done = &hwdev_done;
-
-    serial_cfg_2.data_cfg = data_cfg_init;
-
-    serial_hw_cfg_2.uart_device = USART2;
-    serial_hw_cfg_2.irq = USART2_IRQn;
-    serial_cfg_2.hw_cfg.private_data = (void *)&serial_hw_cfg_2;
-    serial_driver_2.private_data = (void *)&serial_cfg_2;
-
-    serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX;
-    serial_device_2.haldev.private_data = (void *)&serial_dev_param_2;
-
-    NVIC_Configuration(serial_hw_cfg_2.irq);
-
-    ret = BoardSerialBusInit(&serial_2.serial_bus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart2 error ret %u\n", ret);
-        return ERROR;
-    }
-
-    ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart2 error ret %u\n", ret);
-        return ERROR;
-    }    
-#endif
-
-#ifdef BSP_USING_USART3
-    static struct SerialCfgParam serial_cfg_3;
-    memset(&serial_cfg_3, 0, sizeof(struct SerialCfgParam));
-
-    static struct UsartHwCfg serial_hw_cfg_3;
-    memset(&serial_hw_cfg_3, 0, sizeof(struct UsartHwCfg));
-
-    static struct SerialDevParam serial_dev_param_3;
-    memset(&serial_dev_param_3, 0, sizeof(struct SerialDevParam));
-
-    serial_3.dma = usart_dma_3;
-    
-    serial_driver_3.drv_done = &drv_done;
-    serial_driver_3.configure = &Stm32SerialDrvConfigure;
-    serial_device_3.hwdev_done = &hwdev_done;
-
-    serial_cfg_3.data_cfg = data_cfg_init;
-
-    serial_hw_cfg_3.uart_device = USART3;
-    serial_hw_cfg_3.irq = USART3_IRQn;
-    serial_cfg_3.hw_cfg.private_data = (void *)&serial_hw_cfg_3;
-    serial_driver_3.private_data = (void *)&serial_cfg_3;
-
-    serial_dev_param_3.serial_work_mode = SIGN_OPER_INT_RX;
-    serial_device_3.haldev.private_data = (void *)&serial_dev_param_3;
-
-    NVIC_Configuration(serial_hw_cfg_3.irq);
-
-    ret = BoardSerialBusInit(&serial_3.serial_bus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart3 error ret %u\n", ret);
-        return ERROR;
-    }
-
-    ret = BoardSerialDevBend(&serial_device_3, (void *)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart3 error ret %u\n", ret);
-        return ERROR;
-    }    
-#endif
-
-#ifdef BSP_USING_UART4
-    static struct SerialCfgParam serial_cfg_4;
-    memset(&serial_cfg_4, 0, sizeof(struct SerialCfgParam));
-
-    static struct UsartHwCfg serial_hw_cfg_4;
-    memset(&serial_hw_cfg_4, 0, sizeof(struct UsartHwCfg));
-
-    static struct SerialDevParam serial_dev_param_4;
-    memset(&serial_dev_param_4, 0, sizeof(struct SerialDevParam));
-
-    serial_4.dma = uart_dma_4;
-    
-    serial_driver_4.drv_done = &drv_done;
-    serial_driver_4.configure = &Stm32SerialDrvConfigure;
-    serial_device_4.hwdev_done = &hwdev_done;
-
-    serial_cfg_4.data_cfg = data_cfg_init;
-
-    serial_hw_cfg_4.uart_device = UART4;
-    serial_hw_cfg_4.irq = UART4_IRQn;
-    serial_cfg_4.hw_cfg.private_data = (void *)&serial_hw_cfg_4;
-    serial_driver_4.private_data = (void *)&serial_cfg_4;
-
-    serial_dev_param_4.serial_work_mode = SIGN_OPER_INT_RX;
-    serial_device_4.haldev.private_data = (void *)&serial_dev_param_4;
-
-    NVIC_Configuration(serial_hw_cfg_4.irq);
-
-    ret = BoardSerialBusInit(&serial_4.serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart4 error ret %u\n", ret);
-        return ERROR;
-    }
-
-    ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart4 error ret %u\n", ret);
-        return ERROR;
-    }    
-#endif
-
-#ifdef BSP_USING_UART5
-    static struct SerialCfgParam serial_cfg_5;
-    memset(&serial_cfg_5, 0, sizeof(struct SerialCfgParam));
-
-    static struct UsartHwCfg serial_hw_cfg_5;
-    memset(&serial_hw_cfg_5, 0, sizeof(struct UsartHwCfg));
-
-    static struct SerialDevParam serial_dev_param_5;
-    memset(&serial_dev_param_5, 0, sizeof(struct SerialDevParam));
-
-    serial_5.dma = uart_dma_5;
-    
-    serial_driver_5.drv_done = &drv_done;
-    serial_driver_5.configure = &Stm32SerialDrvConfigure;
-    serial_device_5.hwdev_done = &hwdev_done;
-
-    serial_cfg_5.data_cfg = data_cfg_init;
-
-    serial_hw_cfg_5.uart_device = UART5;
-    serial_hw_cfg_5.irq = UART5_IRQn;
-    serial_cfg_5.hw_cfg.private_data = (void *)&serial_hw_cfg_5;
-    serial_driver_5.private_data = (void *)&serial_cfg_5;
-
-    serial_dev_param_5.serial_work_mode = SIGN_OPER_INT_RX;
-    serial_device_5.haldev.private_data = (void *)&serial_dev_param_5;
-
-    NVIC_Configuration(serial_hw_cfg_5.irq);
-
-    ret = BoardSerialBusInit(&serial_5.serial_bus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart5 error ret %u\n", ret);
-        return ERROR;
-    }
-
-    ret = BoardSerialDevBend(&serial_device_5, (void *)&serial_cfg_5, SERIAL_BUS_NAME_5, SERIAL_5_DEVICE_NAME_0);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart5 error ret %u\n", ret);
-        return ERROR;
-    }    
-#endif
-
-    return ret;
-}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/third_party_driver/uart/connect_usart_20210825135326.c

@@ -1,858 +0,0 @@
-/*
- * Copyright (c) 2020 RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- */
-
-/**
-* @file connect_usart.c
-* @brief support stm32f407-st-discovery-board usart function and register to bus framework
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2021-04-25
-*/
-
-/*************************************************
-File name: connect_uart.c
-Description: support stm32f407-st-discovery-board usart configure and uart bus register function
-Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_usart.c for references
-                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
-History: 
-1. Date: 2021-04-25
-Author: AIIT XUOS Lab
-Modification: 
-1. support stm32f407-st-discovery-board usart configure, write and read
-2. support stm32f407-st-discovery-board usart bus device and driver register
-*************************************************/
-
-#include "stm32f4xx.h"
-#include "board.h"
-#include "misc.h"
-#include "connect_usart.h"
-#include "hardware_gpio.h"
-#include "hardware_rcc.h"
-
-/* UART GPIO define. */
-#define UART1_GPIO_TX       GPIO_Pin_6
-#define UART1_TX_PIN_SOURCE GPIO_PinSource6
-#define UART1_GPIO_RX       GPIO_Pin_7
-#define UART1_RX_PIN_SOURCE GPIO_PinSource7
-#define UART1_GPIO          GPIOB
-#define UART1_GPIO_RCC      RCC_AHB1Periph_GPIOB
-#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
-
-#define UART2_GPIO_TX       GPIO_Pin_2
-#define UART2_TX_PIN_SOURCE GPIO_PinSource2
-#define UART2_GPIO_RX       GPIO_Pin_3
-#define UART2_RX_PIN_SOURCE GPIO_PinSource3
-#define UART2_GPIO          GPIOA
-#define UART2_GPIO_RCC      RCC_AHB1Periph_GPIOA
-#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
-
-#define UART3_GPIO_TX       GPIO_Pin_8
-#define UART3_TX_PIN_SOURCE GPIO_PinSource8
-#define UART3_GPIO_RX       GPIO_Pin_9
-#define UART3_RX_PIN_SOURCE GPIO_PinSource9
-#define UART3_GPIO          GPIOD
-#define UART3_GPIO_RCC      RCC_AHB1Periph_GPIOD
-#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
-
-#define UART4_GPIO_TX       GPIO_Pin_10
-#define UART4_TX_PIN_SOURCE GPIO_PinSource10
-#define UART4_GPIO_RX       GPIO_Pin_11
-#define UART4_RX_PIN_SOURCE GPIO_PinSource11
-#define UART4_GPIO          GPIOC
-#define UART4_GPIO_RCC      RCC_AHB1Periph_GPIOC
-#define RCC_APBPeriph_UART4 RCC_APB1Periph_UART4
-
-#define UART5_GPIO_TX       GPIO_Pin_12
-#define UART5_TX_PIN_SOURCE GPIO_PinSource12
-#define UART5_GPIO_RX       GPIO_Pin_2
-#define UART5_RX_PIN_SOURCE GPIO_PinSource2
-#define UART5_TX            GPIOC
-#define UART5_RX            GPIOD
-#define UART5_GPIO_RCC_TX   RCC_AHB1Periph_GPIOC
-#define UART5_GPIO_RCC_RX   RCC_AHB1Periph_GPIOD
-#define RCC_APBPeriph_UART5 RCC_APB1Periph_UART5
-
-#define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
-#define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
-
-static void RCCConfiguration(void)
-{
-#ifdef BSP_USING_USART1
-    RCC_AHB1PeriphClockCmd(UART1_GPIO_RCC, ENABLE);
-    RCC_APB2PeriphClockCmd(RCC_APBPeriph_UART1, ENABLE);
-#endif
-
-#ifdef BSP_USING_USART2
-    RCC_AHB1PeriphClockCmd(UART2_GPIO_RCC, ENABLE);
-    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART2, ENABLE);
-#endif
-
-#ifdef BSP_USING_USART3
-    RCC_AHB1PeriphClockCmd(UART3_GPIO_RCC, ENABLE);
-    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART3, ENABLE);
-#endif
-
-#ifdef BSP_USING_UART4
-    RCC_AHB1PeriphClockCmd(UART4_GPIO_RCC, ENABLE);
-    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART4, ENABLE);
-#endif
-
-#ifdef BSP_USING_UART5
-    RCC_AHB1PeriphClockCmd(UART5_GPIO_RCC_TX | UART5_GPIO_RCC_RX, ENABLE);
-    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART5, ENABLE);
-#endif
-}
-
-static void GPIOConfiguration(void)
-{
-    GPIO_InitTypeDef gpio_initstructure;
-
-    gpio_initstructure.GPIO_Mode  = GPIO_Mode_AF;
-    gpio_initstructure.GPIO_OType = GPIO_OType_PP;
-    gpio_initstructure.GPIO_PuPd  = GPIO_PuPd_UP;
-    gpio_initstructure.GPIO_Speed = GPIO_Speed_2MHz;
-
-#ifdef BSP_USING_USART1
-    gpio_initstructure.GPIO_Pin = UART1_GPIO_RX | UART1_GPIO_TX;
-    GPIO_PinAFConfig(UART1_GPIO, UART1_TX_PIN_SOURCE, GPIO_AF_USART1);
-    GPIO_PinAFConfig(UART1_GPIO, UART1_RX_PIN_SOURCE, GPIO_AF_USART1);    
-    
-    GPIO_Init(UART1_GPIO, &gpio_initstructure);
-#endif
-
-#ifdef BSP_USING_USART2
-    gpio_initstructure.GPIO_Pin = UART2_GPIO_RX | UART2_GPIO_TX;
-    GPIO_PinAFConfig(UART2_GPIO, UART2_TX_PIN_SOURCE, GPIO_AF_USART2);
-    GPIO_PinAFConfig(UART2_GPIO, UART2_RX_PIN_SOURCE, GPIO_AF_USART2);
-    
-    GPIO_Init(UART2_GPIO, &gpio_initstructure);
-#endif
-
-#ifdef BSP_USING_USART3
-    gpio_initstructure.GPIO_Pin = UART3_GPIO_TX | UART3_GPIO_RX;
-    GPIO_PinAFConfig(UART3_GPIO, UART3_TX_PIN_SOURCE, GPIO_AF_USART3);
-    GPIO_PinAFConfig(UART3_GPIO, UART3_RX_PIN_SOURCE, GPIO_AF_USART3);
-    
-    GPIO_Init(UART3_GPIO, &gpio_initstructure);
-#endif
-
-#ifdef BSP_USING_UART4
-    gpio_initstructure.GPIO_Pin = UART4_GPIO_TX | UART4_GPIO_RX;
-    GPIO_PinAFConfig(UART4_GPIO, UART4_TX_PIN_SOURCE, GPIO_AF_UART4);
-    GPIO_PinAFConfig(UART4_GPIO, UART4_RX_PIN_SOURCE, GPIO_AF_UART4);
-    
-    GPIO_Init(UART4_GPIO, &gpio_initstructure);
-#endif
-
-#ifdef BSP_USING_UART5
-    gpio_initstructure.GPIO_Pin = UART5_GPIO_TX;
-    GPIO_PinAFConfig(UART5_TX, UART5_TX_PIN_SOURCE, GPIO_AF_UART5); 
-    GPIO_Init(UART5_TX, &gpio_initstructure);
-    
-    gpio_initstructure.GPIO_Pin = UART5_GPIO_RX;
-    GPIO_PinAFConfig(UART5_RX, UART5_RX_PIN_SOURCE, GPIO_AF_UART5);
-    GPIO_Init(UART5_RX, &gpio_initstructure);
-#endif
-}
-
-static void NVIC_Configuration(IRQn_Type irq)
-{
-    NVIC_InitTypeDef NVIC_InitStructure;
-
-    NVIC_InitStructure.NVIC_IRQChannel = irq;
-    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
-    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-    NVIC_Init(&NVIC_InitStructure);
-}
-
-static void DmaUartConfig(struct Stm32UsartDma *dma, USART_TypeDef *uart_device, uint32_t SettingRecvLen, void *mem_base_addr)
-{   
-    DMA_InitTypeDef DMA_InitStructure;
-
-    dma->SettingRecvLen = SettingRecvLen;
-    DMA_DeInit(dma->RxStream);
-    while (DMA_GetCmdStatus(dma->RxStream) != DISABLE);
-    DMA_InitStructure.DMA_Channel = dma->RxCh;
-    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(uart_device->DR);
-    DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)mem_base_addr;
-    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
-    DMA_InitStructure.DMA_BufferSize = dma->SettingRecvLen;
-    DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-    DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
-    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-    DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
-    DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
-    DMA_InitStructure.DMA_Priority = DMA_Priority_High;
-    DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
-    DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
-    DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
-    DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
-    DMA_Init(dma->RxStream, &DMA_InitStructure);
-}
-
-static void DMAConfiguration(struct SerialHardwareDevice *serial_dev, USART_TypeDef *uart_device)
-{
-    struct Stm32Usart *serial = CONTAINER_OF(serial_dev->haldev.owner_bus, struct Stm32Usart, serial_bus);
-    struct Stm32UsartDma *dma = &serial->dma; 
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
-
-    NVIC_InitTypeDef NVIC_InitStructure;
-
-    USART_ITConfig(uart_device, USART_IT_IDLE , ENABLE);
-
-    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
-    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
-
-    DmaUartConfig(dma, uart_device, serial_cfg->data_cfg.serial_buffer_size, serial_dev->serial_fifo.serial_rx->serial_rx_buffer);
-
-    DMA_ClearFlag(dma->RxStream, dma->RxFlag);
-    DMA_ITConfig(dma->RxStream, DMA_IT_TC, ENABLE);
-    USART_DMACmd(uart_device, USART_DMAReq_Rx, ENABLE);
-    DMA_Cmd(dma->RxStream, ENABLE);
-
-    NVIC_InitStructure.NVIC_IRQChannel = dma->RxIrqCh;
-    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-    NVIC_Init(&NVIC_InitStructure);
-}
-
-static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
-{
-    struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
-    struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
-
-    if((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
-        data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
-    }
-
-    if((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
-        data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
-    }
-
-    if((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
-        data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
-    }
-
-    if((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
-        data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
-    }
-
-    if((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
-        data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
-    }
-
-    if((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
-        data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
-    }
-
-    if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
-        data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
-    }
-}
-
-static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
-{
-    NULL_PARAM_CHECK(serial_drv);
-
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-
-    if (configure_info->private_data) {
-        struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
-        SerialCfgParamCheck(serial_cfg, serial_cfg_new);
-    }
-
-    USART_InitTypeDef USART_InitStructure;
-
-    USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate;
-
-    if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_8) {
-        USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-    } else if (serial_cfg->data_cfg.serial_data_bits == DATA_BITS_9) {
-        USART_InitStructure.USART_WordLength = USART_WordLength_9b;
-    }
-
-    if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_1){
-        USART_InitStructure.USART_StopBits = USART_StopBits_1;
-    } else if (serial_cfg->data_cfg.serial_stop_bits == STOP_BITS_2) {
-        USART_InitStructure.USART_StopBits = USART_StopBits_2;
-    }
-
-    if (serial_cfg->data_cfg.serial_parity_mode == PARITY_NONE) {
-        USART_InitStructure.USART_Parity = USART_Parity_No;
-    } else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_ODD) {
-        USART_InitStructure.USART_Parity = USART_Parity_Odd;
-    } else if (serial_cfg->data_cfg.serial_parity_mode == PARITY_EVEN) {
-        USART_InitStructure.USART_Parity = USART_Parity_Even;
-    }
-
-    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-    USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-    USART_Init(serial_hw_cfg->uart_device, &USART_InitStructure);
-
-    USART_Cmd(serial_hw_cfg->uart_device, ENABLE);
-
-    return EOK;
-}
-
-static uint32 Stm32SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
-{
-    NULL_PARAM_CHECK(serial_drv);
-
-    struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-    struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
-
-    switch (serial_operation_cmd)
-    {
-        case OPER_CLR_INT:
-            UART_DISABLE_IRQ(serial_hw_cfg->irq);
-            USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, DISABLE);
-            break;
-        case OPER_SET_INT:
-            UART_ENABLE_IRQ(serial_hw_cfg->irq);
-            USART_ITConfig(serial_hw_cfg->uart_device, USART_IT_RXNE, ENABLE);
-            break;
-        case OPER_CONFIG :
-            if (SIGN_OPER_DMA_RX == serial_dev_param->serial_set_mode){
-                DMAConfiguration(serial_dev, serial_hw_cfg->uart_device);
-            }
-    }
-
-    return EOK;
-}
-
-static int Stm32SerialPutchar(struct SerialHardwareDevice *serial_dev, char c)
-{
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-
-    while (!(serial_hw_cfg->uart_device->SR & USART_FLAG_TXE));
-    serial_hw_cfg->uart_device->DR = c;
-
-    return EOK;
-}
-
-static int Stm32SerialGetchar(struct SerialHardwareDevice *serial_dev)
-{
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-
-    int ch = -1;
-    if (serial_hw_cfg->uart_device->SR & USART_FLAG_RXNE) {
-        ch = serial_hw_cfg->uart_device->DR & 0xff;
-    }
-
-    return ch;
-}
-
-static void DmaUartRxIdleIsr(struct SerialHardwareDevice *serial_dev, struct Stm32UsartDma *dma, USART_TypeDef *uart_device)
-{
-    x_base level = CriticalAreaLock();
-
-    x_size_t recv_total_index = dma->SettingRecvLen - DMA_GetCurrDataCounter(dma->RxStream);
-    x_size_t recv_len = recv_total_index - dma->LastRecvIndex;
-    dma->LastRecvIndex = recv_total_index;
-    CriticalAreaUnLock(level);
-
-    if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
-
-    USART_ReceiveData(uart_device);
-}
-
-static void DmaRxDoneIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
-{
-    struct Stm32UsartDma *dma = &serial->dma; 
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-
-    if (DMA_GetFlagStatus(dma->RxStream, dma->RxFlag) != RESET) {
-        x_base level = CriticalAreaLock();
-
-        x_size_t recv_len = dma->SettingRecvLen - dma->LastRecvIndex;
-        dma->LastRecvIndex = 0;
-        CriticalAreaUnLock(level);
-
-        if (recv_len) SerialSetIsr(serial_dev, SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
-
-        DMA_ClearFlag(dma->RxStream, dma->RxFlag);
-    }
-}
-
-static void UartIsr(struct Stm32Usart *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
-{
-    struct Stm32UsartDma *dma = &serial->dma; 
-    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
-    struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
-
-    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_RXNE) != RESET) {
-        SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
-        USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_RXNE);
-    }
-    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_IDLE) != RESET) {
-        DmaUartRxIdleIsr(serial_dev, dma, serial_hw_cfg->uart_device);
-    }
-    if (USART_GetITStatus(serial_hw_cfg->uart_device, USART_IT_TC) != RESET) {
-        USART_ClearITPendingBit(serial_hw_cfg->uart_device, USART_IT_TC);
-    }
-    if (USART_GetFlagStatus(serial_hw_cfg->uart_device, USART_FLAG_ORE) == SET) {
-        USART_ReceiveData(serial_hw_cfg->uart_device);
-    }
-}
-
-#ifdef BSP_USING_USART1
-struct Stm32Usart serial_1;
-struct SerialDriver serial_driver_1;
-struct SerialHardwareDevice serial_device_1;
-
-static const struct Stm32UsartDma usart_dma_1 =
-{
-    DMA2_Stream5,
-    DMA_Channel_4,
-    DMA_FLAG_TCIF5,
-    DMA2_Stream5_IRQn,
-    0,
-    0,
-};
-
-void USART1_IRQHandler(int irq_num, void *arg)
-{
-    UartIsr(&serial_1, &serial_driver_1, &serial_device_1);
-}
-DECLARE_HW_IRQ(USART1_IRQn, USART1_IRQHandler, NONE);
-
-void DMA2_Stream5_IRQHandler(int irq_num, void *arg) {
-    DmaRxDoneIsr(&serial_1, &serial_driver_1, &serial_device_1);
-}
-DECLARE_HW_IRQ(DMA2_Stream5_IRQn, DMA2_Stream5_IRQHandler, NONE);
-#endif
-
-#ifdef BSP_USING_USART2
-struct Stm32Usart serial_2;
-struct SerialDriver serial_driver_2;
-struct SerialHardwareDevice serial_device_2;
-
-static const struct Stm32UsartDma usart_dma_2 =
-{
-    DMA1_Stream5,
-    DMA_Channel_4,
-    DMA_FLAG_TCIF5,
-    DMA1_Stream5_IRQn,
-    0,
-    0,
-};
-
-void USART2_IRQHandler(int irq_num, void *arg)
-{
-    UartIsr(&serial_2, &serial_driver_2, &serial_device_2);
-}
-DECLARE_HW_IRQ(USART2_IRQn, USART2_IRQHandler, NONE);
-
-void DMA1_Stream5_IRQHandler(int irq_num, void *arg) {
-    DmaRxDoneIsr(&serial_2, &serial_driver_2, &serial_device_2);
-}
-DECLARE_HW_IRQ(DMA1_Stream5_IRQn, DMA1_Stream5_IRQHandler, NONE);
-#endif
-
-#ifdef BSP_USING_USART3
-struct Stm32Usart serial_3;
-struct SerialDriver serial_driver_3;
-struct SerialHardwareDevice serial_device_3;
-
-static const struct Stm32UsartDma usart_dma_3 =
-{
-    DMA1_Stream1,
-    DMA_Channel_4,
-    DMA_FLAG_TCIF1,
-    DMA1_Stream1_IRQn,
-    0,
-    0,
-};
-
-void USART3_IRQHandler(int irq_num, void *arg)
-{
-    UartIsr(&serial_3, &serial_driver_3, &serial_device_3);
-}
-DECLARE_HW_IRQ(USART3_IRQn, USART3_IRQHandler, NONE);
-
-void DMA1_Stream1_IRQHandler(int irq_num, void *arg) {
-    DmaRxDoneIsr(&serial_3, &serial_driver_3, &serial_device_3);
-}
-DECLARE_HW_IRQ(DMA1_Stream1_IRQn, DMA1_Stream1_IRQHandler, NONE);
-#endif
-
-#ifdef BSP_USING_UART4
-struct Stm32Usart serial_4;
-struct SerialDriver serial_driver_4;
-struct SerialHardwareDevice serial_device_4;
-
-static const struct Stm32UsartDma uart_dma_4 =
-{
-    DMA1_Stream2,
-    DMA_Channel_4,
-    DMA_FLAG_TCIF2,
-    DMA1_Stream2_IRQn,
-    0,
-    0,
-};
-
-void UART4_IRQHandler(int irq_num, void *arg)
-{
-    UartIsr(&serial_4, &serial_driver_4, &serial_device_4);
-}
-DECLARE_HW_IRQ(UART4_IRQn, UART4_IRQHandler, NONE);
-
-void DMA1_Stream2_IRQHandler(int irq_num, void *arg) {
-    DmaRxDoneIsr(&serial_4, &serial_driver_4, &serial_device_4);
-}
-DECLARE_HW_IRQ(DMA1_Stream2_IRQn, DMA1_Stream2_IRQHandler, NONE);
-#endif
-
-#ifdef BSP_USING_UART5
-struct Stm32Usart serial_5;
-struct SerialDriver serial_driver_5;
-struct SerialHardwareDevice serial_device_5;
-
-static const struct Stm32UsartDma uart_dma_5 =
-{
-    DMA1_Stream0,
-    DMA_Channel_4,
-    DMA_FLAG_TCIF0,
-    DMA1_Stream0_IRQn,
-    0,
-    0,
-};
-
-void UART5_IRQHandler(int irq_num, void *arg)
-{
-    UartIsr(&serial_5, &serial_driver_5, &serial_device_5);
-}
-DECLARE_HW_IRQ(UART5_IRQn, UART5_IRQHandler, NONE);
-
-void DMA1_Stream0_IRQHandler(int irq_num, void *arg) {
-    DmaRxDoneIsr(&serial_5, &serial_driver_5, &serial_device_5);
-}
-DECLARE_HW_IRQ(DMA1_Stream0_IRQn, DMA1_Stream0_IRQHandler, NONE);
-#endif
-
-static uint32 Stm32SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
-{
-    NULL_PARAM_CHECK(drv);
-    NULL_PARAM_CHECK(configure_info);
-
-    x_err_t ret = EOK;
-    int serial_operation_cmd;
-    struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
-
-    switch (configure_info->configure_cmd)
-    {
-        case OPE_INT:
-            ret = Stm32SerialInit(serial_drv, configure_info);
-            break;
-        case OPE_CFG:
-            serial_operation_cmd = *(int *)configure_info->private_data;
-            ret = Stm32SerialConfigure(serial_drv, serial_operation_cmd);
-            break;
-        default:
-            break;
-    }
-
-    return ret;
-}
-
-static const struct SerialDataCfg data_cfg_init = 
-{
-    .serial_baud_rate = BAUD_RATE_115200,
-    .serial_data_bits = DATA_BITS_8,
-    .serial_stop_bits = STOP_BITS_1,
-    .serial_parity_mode = PARITY_NONE,
-    .serial_bit_order = BIT_ORDER_LSB,
-    .serial_invert_mode = NRZ_NORMAL,
-    .serial_buffer_size = SERIAL_RB_BUFSZ,
-};
-
-/*manage the serial device operations*/
-static const struct SerialDrvDone drv_done =
-{
-    .init = Stm32SerialInit,
-    .configure = Stm32SerialConfigure,
-};
-
-/*manage the serial device hal operations*/
-static struct SerialHwDevDone hwdev_done =
-{
-    .put_char = Stm32SerialPutchar,
-    .get_char = Stm32SerialGetchar,
-};
-
-static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
-{
-    x_err_t ret = EOK;
-
-    /*Init the serial bus */
-    ret = SerialBusInit(serial_bus, bus_name);
-    if (EOK != ret) {
-        KPrintf("hw_serial_init SerialBusInit error %d\n", ret);
-        return ERROR;
-    }
-
-    /*Init the serial driver*/
-    ret = SerialDriverInit(serial_driver, drv_name);
-    if (EOK != ret) {
-        KPrintf("hw_serial_init SerialDriverInit error %d\n", ret);
-        return ERROR;
-    }
-
-    /*Attach the serial driver to the serial bus*/
-    ret = SerialDriverAttachToBus(drv_name, bus_name);
-    if (EOK != ret) {
-        KPrintf("hw_serial_init SerialDriverAttachToBus error %d\n", ret);
-        return ERROR;
-    } 
-
-    return ret;
-}
-
-/*Attach the serial device to the serial bus*/
-static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
-{
-    x_err_t ret = EOK;
-
-    ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
-    if (EOK != ret) {
-        KPrintf("hw_serial_init SerialDeviceInit device %s error %d\n", dev_name, ret);
-        return ERROR;
-    }  
-
-    ret = SerialDeviceAttachToBus(dev_name, bus_name);
-    if (EOK != ret) {
-        KPrintf("hw_serial_init SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
-        return ERROR;
-    }  
-
-    return  ret;
-}
-
-int InitHwUsart(void)
-{
-    x_err_t ret = EOK;
-
-    RCCConfiguration();
-    GPIOConfiguration();
-
-#ifdef BSP_USING_USART1
-    static struct SerialCfgParam serial_cfg_1;
-    memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam));
-
-    static struct UsartHwCfg serial_hw_cfg_1;
-    memset(&serial_hw_cfg_1, 0, sizeof(struct UsartHwCfg));
-
-    static struct SerialDevParam serial_dev_param_1;
-    memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
-
-    serial_1.dma = usart_dma_1;
-    
-    serial_driver_1.drv_done = &drv_done;
-    serial_driver_1.configure = &Stm32SerialDrvConfigure;
-    serial_device_1.hwdev_done = &hwdev_done;
-
-    serial_cfg_1.data_cfg = data_cfg_init;
-
-    serial_hw_cfg_1.uart_device = USART1;
-    serial_hw_cfg_1.irq = USART1_IRQn;
-    serial_cfg_1.hw_cfg.private_data = (void *)&serial_hw_cfg_1;
-    serial_driver_1.private_data = (void *)&serial_cfg_1;
-
-    serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX;
-    serial_device_1.haldev.private_data = (void *)&serial_dev_param_1;
-
-    NVIC_Configuration(serial_hw_cfg_1.irq);
-
-    ret = BoardSerialBusInit(&serial_1.serial_bus, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart1 error ret %u\n", ret);
-        return ERROR;
-    }
-
-    ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart1 error ret %u\n", ret);
-        return ERROR;
-    }    
-#endif
-
-#ifdef BSP_USING_USART2
-    static struct SerialCfgParam serial_cfg_2;
-    memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam));
-
-    static struct UsartHwCfg serial_hw_cfg_2;
-    memset(&serial_hw_cfg_2, 0, sizeof(struct UsartHwCfg));
-
-    static struct SerialDevParam serial_dev_param_2;
-    memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
-
-    serial_2.dma = usart_dma_2;
-    
-    serial_driver_2.drv_done = &drv_done;
-    serial_driver_2.configure = &Stm32SerialDrvConfigure;
-    serial_device_2.hwdev_done = &hwdev_done;
-
-    serial_cfg_2.data_cfg = data_cfg_init;
-
-    serial_hw_cfg_2.uart_device = USART2;
-    serial_hw_cfg_2.irq = USART2_IRQn;
-    serial_cfg_2.hw_cfg.private_data = (void *)&serial_hw_cfg_2;
-    serial_driver_2.private_data = (void *)&serial_cfg_2;
-
-    serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX;
-    serial_device_2.haldev.private_data = (void *)&serial_dev_param_2;
-
-    NVIC_Configuration(serial_hw_cfg_2.irq);
-
-    ret = BoardSerialBusInit(&serial_2.serial_bus, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart2 error ret %u\n", ret);
-        return ERROR;
-    }
-
-    ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_2_DEVICE_NAME_0);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart2 error ret %u\n", ret);
-        return ERROR;
-    }    
-#endif
-
-#ifdef BSP_USING_USART3
-    static struct SerialCfgParam serial_cfg_3;
-    memset(&serial_cfg_3, 0, sizeof(struct SerialCfgParam));
-
-    static struct UsartHwCfg serial_hw_cfg_3;
-    memset(&serial_hw_cfg_3, 0, sizeof(struct UsartHwCfg));
-
-    static struct SerialDevParam serial_dev_param_3;
-    memset(&serial_dev_param_3, 0, sizeof(struct SerialDevParam));
-
-    serial_3.dma = usart_dma_3;
-    
-    serial_driver_3.drv_done = &drv_done;
-    serial_driver_3.configure = &Stm32SerialDrvConfigure;
-    serial_device_3.hwdev_done = &hwdev_done;
-
-    serial_cfg_3.data_cfg = data_cfg_init;
-
-    serial_hw_cfg_3.uart_device = USART3;
-    serial_hw_cfg_3.irq = USART3_IRQn;
-    serial_cfg_3.hw_cfg.private_data = (void *)&serial_hw_cfg_3;
-    serial_driver_3.private_data = (void *)&serial_cfg_3;
-
-    serial_dev_param_3.serial_work_mode = SIGN_OPER_INT_RX;
-    serial_device_3.haldev.private_data = (void *)&serial_dev_param_3;
-
-    NVIC_Configuration(serial_hw_cfg_3.irq);
-
-    ret = BoardSerialBusInit(&serial_3.serial_bus, &serial_driver_3, SERIAL_BUS_NAME_3, SERIAL_DRV_NAME_3);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart3 error ret %u\n", ret);
-        return ERROR;
-    }
-
-    ret = BoardSerialDevBend(&serial_device_3, (void *)&serial_cfg_3, SERIAL_BUS_NAME_3, SERIAL_3_DEVICE_NAME_0);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart3 error ret %u\n", ret);
-        return ERROR;
-    }    
-#endif
-
-#ifdef BSP_USING_UART4
-    static struct SerialCfgParam serial_cfg_4;
-    memset(&serial_cfg_4, 0, sizeof(struct SerialCfgParam));
-
-    static struct UsartHwCfg serial_hw_cfg_4;
-    memset(&serial_hw_cfg_4, 0, sizeof(struct UsartHwCfg));
-
-    static struct SerialDevParam serial_dev_param_4;
-    memset(&serial_dev_param_4, 0, sizeof(struct SerialDevParam));
-
-    serial_4.dma = uart_dma_4;
-    
-    serial_driver_4.drv_done = &drv_done;
-    serial_driver_4.configure = &Stm32SerialDrvConfigure;
-    serial_device_4.hwdev_done = &hwdev_done;
-
-    serial_cfg_4.data_cfg = data_cfg_init;
-
-    serial_hw_cfg_4.uart_device = UART4;
-    serial_hw_cfg_4.irq = UART4_IRQn;
-    serial_cfg_4.hw_cfg.private_data = (void *)&serial_hw_cfg_4;
-    serial_driver_4.private_data = (void *)&serial_cfg_4;
-
-    serial_dev_param_4.serial_work_mode = SIGN_OPER_INT_RX;
-    serial_device_4.haldev.private_data = (void *)&serial_dev_param_4;
-
-    NVIC_Configuration(serial_hw_cfg_4.irq);
-
-    ret = BoardSerialBusInit(&serial_4.serial_bus, &serial_driver_4, SERIAL_BUS_NAME_4, SERIAL_DRV_NAME_4);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart4 error ret %u\n", ret);
-        return ERROR;
-    }
-
-    ret = BoardSerialDevBend(&serial_device_4, (void *)&serial_cfg_4, SERIAL_BUS_NAME_4, SERIAL_4_DEVICE_NAME_0);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart4 error ret %u\n", ret);
-        return ERROR;
-    }    
-#endif
-
-#ifdef BSP_USING_UART5
-    static struct SerialCfgParam serial_cfg_5;
-    memset(&serial_cfg_5, 0, sizeof(struct SerialCfgParam));
-
-    static struct UsartHwCfg serial_hw_cfg_5;
-    memset(&serial_hw_cfg_5, 0, sizeof(struct UsartHwCfg));
-
-    static struct SerialDevParam serial_dev_param_5;
-    memset(&serial_dev_param_5, 0, sizeof(struct SerialDevParam));
-
-    serial_5.dma = uart_dma_5;
-    
-    serial_driver_5.drv_done = &drv_done;
-    serial_driver_5.configure = &Stm32SerialDrvConfigure;
-    serial_device_5.hwdev_done = &hwdev_done;
-
-    serial_cfg_5.data_cfg = data_cfg_init;
-
-    serial_hw_cfg_5.uart_device = UART5;
-    serial_hw_cfg_5.irq = UART5_IRQn;
-    serial_cfg_5.hw_cfg.private_data = (void *)&serial_hw_cfg_5;
-    serial_driver_5.private_data = (void *)&serial_cfg_5;
-
-    serial_dev_param_5.serial_work_mode = SIGN_OPER_INT_RX;
-    serial_device_5.haldev.private_data = (void *)&serial_dev_param_5;
-
-    NVIC_Configuration(serial_hw_cfg_5.irq);
-
-    ret = BoardSerialBusInit(&serial_5.serial_bus, &serial_driver_5, SERIAL_BUS_NAME_5, SERIAL_DRV_NAME_5);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart5 error ret %u\n", ret);
-        return ERROR;
-    }
-
-    ret = BoardSerialDevBend(&serial_device_5, (void *)&serial_cfg_5, SERIAL_BUS_NAME_5, SERIAL_5_DEVICE_NAME_0);
-    if (EOK != ret) {
-        KPrintf("InitHwUsart usart5 error ret %u\n", ret);
-        return ERROR;
-    }    
-#endif
-
-    return ret;
-}

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825132156.h

@@ -1,185 +0,0 @@
-#ifndef XS_CONFIG_H__
-#define XS_CONFIG_H__
-
-/*  Automatically generated file; DO NOT EDIT. */
-/*  XiUOS Project Configuration */
-
-#define BOARD_STM32F407_EVB
-#define ARCH_ARM
-
-/*  stm32f407-st-discovery feature */
-
-#define BSP_USING_DMA
-#define BSP_USING_GPIO
-#define PIN_BUS_NAME "pin"
-#define PIN_DRIVER_NAME "pin_drv"
-#define PIN_DEVICE_NAME "pin_dev"
-#define BSP_USING_UART
-#define BSP_USING_USART1
-#define SERIAL_BUS_NAME_1 "usart1"
-#define SERIAL_DRV_NAME_1 "usart1_drv"
-#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
-#define BSP_USING_USART2
-#define SERIAL_BUS_NAME_2 "usart2"
-#define SERIAL_DRV_NAME_2 "usart2_drv"
-#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
-#define BSP_USING_USART3
-#define SERIAL_BUS_NAME_3 "usart3"
-#define SERIAL_DRV_NAME_3 "usart3_drv"
-#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
-#define BSP_USING_WDT
-#define WDT_BUS_NAME "wdt"
-#define WDT_DRIVER_NAME "wdt_drv"
-#define WDT_DEVICE_NAME "wdt_dev"
-
-/*  config default board resources */
-
-/*  config board app name */
-
-#define BOARD_APP_NAME "/XiUOS_stm32f407-st-discovery_app.bin"
-
-/*  config board service table */
-
-#define SERVICE_TABLE_ADDRESS 0x20000000
-
-/*  config hardware resources for connection */
-
-/*  Hardware feature */
-
-#define RESOURCES_SERIAL
-#define SERIAL_USING_DMA
-#define SERIAL_RB_BUFSZ 128
-#define RESOURCES_PIN
-#define RESOURCES_WDT
-
-/*  Kernel feature */
-
-/*  separate compile(choose none for compile once) */
-
-#define APP_STARTUP_FROM_FLASH
-
-/*  Memory Management */
-
-#define MEM_ALIGN_SIZE 8
-#define MM_PAGE_SIZE 4096
-
-/*  Using small memory allocator */
-
-#define KERNEL_SMALL_MEM_ALLOC
-#define SMALL_NUMBER_32B 64
-#define SMALL_NUMBER_64B 32
-
-/*  Task feature */
-
-#define USER_APPLICATION
-
-/*  Inter-Task communication */
-
-#define KERNEL_SEMAPHORE
-#define KERNEL_MUTEX
-#define KERNEL_EVENT
-#define KERNEL_MESSAGEQUEUE
-#define KERNEL_SOFTTIMER
-#define SCHED_POLICY_RR_REMAINSLICE
-#define KTASK_PRIORITY_32
-#define KTASK_PRIORITY_MAX 32
-#define TICK_PER_SECOND 1000
-#define KERNEL_STACK_OVERFLOW_CHECK
-#define IDLE_KTASK_STACKSIZE 256
-#define ZOMBIE_KTASK_STACKSIZE 2048
-
-/*  Kernel Console */
-
-#define KERNEL_CONSOLE
-#define KERNEL_BANNER
-#define KERNEL_CONSOLEBUF_SIZE 128
-
-/*  Kernel Hook */
-
-
-/*  Command shell */
-
-#define TOOL_SHELL
-#define SHELL_ENTER_CR
-#define SHELL_ENTER_LF
-#define SHELL_ENTER_CR_AND_LF
-
-/*  Set shell user control */
-
-#define SHELL_DEFAULT_USER "letter"
-#define SHELL_DEFAULT_USER_PASSWORD ""
-#define SHELL_LOCK_TIMEOUT 10000
-
-/*  Set shell config param */
-
-#define SHELL_TASK_STACK_SIZE 4096
-#define SHELL_TASK_PRIORITY 20
-#define SHELL_MAX_NUMBER 5
-#define SHELL_PARAMETER_MAX_NUMBER 8
-#define SHELL_HISTORY_MAX_NUMBER 5
-#define SHELL_PRINT_BUFFER 128
-#define SHELL_HELP_SHOW_PERMISSION
-
-/*  Kernel data structure Manage */
-
-#define KERNEL_QUEUEMANAGE
-#define KERNEL_WORKQUEUE
-#define WORKQUEUE_KTASK_STACKSIZE 512
-#define WORKQUEUE_KTASK_PRIORITY 23
-#define QUEUE_MAX 16
-#define KERNEL_WAITQUEUE
-#define KERNEL_DATAQUEUE
-
-/*  Kernel components init */
-
-#define KERNEL_COMPONENTS_INIT
-#define ENV_INIT_KTASK_STACK_SIZE 8192
-#define KERNEL_USER_MAIN
-#define NAME_NUM_MAX 32
-
-/*  hash table config */
-
-#define ID_HTABLE_SIZE 16
-#define ID_NUM_MAX 128
-
-/*  File system */
-
-#define FS_VFS
-#define VFS_USING_WORKDIR
-#define FS_VFS_DEVFS
-#define FS_VFS_FATFS
-
-/*  APP Framework */
-
-/*  Perception */
-
-
-/*  connection */
-
-
-/*  Intelligence */
-
-
-/*  Control */
-
-/*  Lib */
-
-#define LIB
-#define LIB_POSIX
-
-/*  C++ features */
-
-#define LIB_NEWLIB
-
-/*  Security */
-
-
-/*  Applications */
-
-
-/*  config stack size and priority of main task */
-
-#define MAIN_KTASK_STACK_SIZE 2048
-#define MAIN_KTASK_PRIORITY 10
-
-#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140658.h

@@ -1,185 +0,0 @@
-#ifndef XS_CONFIG_H__
-#define XS_CONFIG_H__
-
-/*  Automatically generated file; DO NOT EDIT. */
-/*  XiUOS Project Configuration */
-
-#define BOARD_CORTEX_M4_EVB
-#define ARCH_ARM
-
-/*  stm32f407-st-discovery feature */
-
-#define BSP_USING_DMA
-#define BSP_USING_GPIO
-#define PIN_BUS_NAME "pin"
-#define PIN_DRIVER_NAME "pin_drv"
-#define PIN_DEVICE_NAME "pin_dev"
-#define BSP_USING_UART
-#define BSP_USING_USART1
-#define SERIAL_BUS_NAME_1 "usart1"
-#define SERIAL_DRV_NAME_1 "usart1_drv"
-#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
-#define BSP_USING_USART2
-#define SERIAL_BUS_NAME_2 "usart2"
-#define SERIAL_DRV_NAME_2 "usart2_drv"
-#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
-#define BSP_USING_USART3
-#define SERIAL_BUS_NAME_3 "usart3"
-#define SERIAL_DRV_NAME_3 "usart3_drv"
-#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
-#define BSP_USING_WDT
-#define WDT_BUS_NAME "wdt"
-#define WDT_DRIVER_NAME "wdt_drv"
-#define WDT_DEVICE_NAME "wdt_dev"
-
-/*  config default board resources */
-
-/*  config board app name */
-
-#define BOARD_APP_NAME "/XiUOS_stm32f407-st-discovery_app.bin"
-
-/*  config board service table */
-
-#define SERVICE_TABLE_ADDRESS 0x20000000
-
-/*  config hardware resources for connection */
-
-/*  Hardware feature */
-
-#define RESOURCES_SERIAL
-#define SERIAL_USING_DMA
-#define SERIAL_RB_BUFSZ 128
-#define RESOURCES_PIN
-#define RESOURCES_WDT
-
-/*  Kernel feature */
-
-/*  separate compile(choose none for compile once) */
-
-#define APP_STARTUP_FROM_FLASH
-
-/*  Memory Management */
-
-#define MEM_ALIGN_SIZE 8
-#define MM_PAGE_SIZE 4096
-
-/*  Using small memory allocator */
-
-#define KERNEL_SMALL_MEM_ALLOC
-#define SMALL_NUMBER_32B 64
-#define SMALL_NUMBER_64B 32
-
-/*  Task feature */
-
-#define USER_APPLICATION
-
-/*  Inter-Task communication */
-
-#define KERNEL_SEMAPHORE
-#define KERNEL_MUTEX
-#define KERNEL_EVENT
-#define KERNEL_MESSAGEQUEUE
-#define KERNEL_SOFTTIMER
-#define SCHED_POLICY_RR_REMAINSLICE
-#define KTASK_PRIORITY_32
-#define KTASK_PRIORITY_MAX 32
-#define TICK_PER_SECOND 1000
-#define KERNEL_STACK_OVERFLOW_CHECK
-#define IDLE_KTASK_STACKSIZE 256
-#define ZOMBIE_KTASK_STACKSIZE 2048
-
-/*  Kernel Console */
-
-#define KERNEL_CONSOLE
-#define KERNEL_BANNER
-#define KERNEL_CONSOLEBUF_SIZE 128
-
-/*  Kernel Hook */
-
-
-/*  Command shell */
-
-#define TOOL_SHELL
-#define SHELL_ENTER_CR
-#define SHELL_ENTER_LF
-#define SHELL_ENTER_CR_AND_LF
-
-/*  Set shell user control */
-
-#define SHELL_DEFAULT_USER "letter"
-#define SHELL_DEFAULT_USER_PASSWORD ""
-#define SHELL_LOCK_TIMEOUT 10000
-
-/*  Set shell config param */
-
-#define SHELL_TASK_STACK_SIZE 4096
-#define SHELL_TASK_PRIORITY 20
-#define SHELL_MAX_NUMBER 5
-#define SHELL_PARAMETER_MAX_NUMBER 8
-#define SHELL_HISTORY_MAX_NUMBER 5
-#define SHELL_PRINT_BUFFER 128
-#define SHELL_HELP_SHOW_PERMISSION
-
-/*  Kernel data structure Manage */
-
-#define KERNEL_QUEUEMANAGE
-#define KERNEL_WORKQUEUE
-#define WORKQUEUE_KTASK_STACKSIZE 512
-#define WORKQUEUE_KTASK_PRIORITY 23
-#define QUEUE_MAX 16
-#define KERNEL_WAITQUEUE
-#define KERNEL_DATAQUEUE
-
-/*  Kernel components init */
-
-#define KERNEL_COMPONENTS_INIT
-#define ENV_INIT_KTASK_STACK_SIZE 8192
-#define KERNEL_USER_MAIN
-#define NAME_NUM_MAX 32
-
-/*  hash table config */
-
-#define ID_HTABLE_SIZE 16
-#define ID_NUM_MAX 128
-
-/*  File system */
-
-#define FS_VFS
-#define VFS_USING_WORKDIR
-#define FS_VFS_DEVFS
-#define FS_VFS_FATFS
-
-/*  APP Framework */
-
-/*  Perception */
-
-
-/*  connection */
-
-
-/*  Intelligence */
-
-
-/*  Control */
-
-/*  Lib */
-
-#define LIB
-#define LIB_POSIX
-
-/*  C++ features */
-
-#define LIB_NEWLIB
-
-/*  Security */
-
-
-/*  Applications */
-
-
-/*  config stack size and priority of main task */
-
-#define MAIN_KTASK_STACK_SIZE 2048
-#define MAIN_KTASK_PRIORITY 10
-
-#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140659.h

@@ -1,185 +0,0 @@
-#ifndef XS_CONFIG_H__
-#define XS_CONFIG_H__
-
-/*  Automatically generated file; DO NOT EDIT. */
-/*  XiUOS Project Configuration */
-
-#define BOARD_CORTEX_M4_EVB
-#define ARCH_ARM
-
-/*  stm32f407-st-discovery feature */
-
-#define BSP_USING_DMA
-#define BSP_USING_GPIO
-#define PIN_BUS_NAME "pin"
-#define PIN_DRIVER_NAME "pin_drv"
-#define PIN_DEVICE_NAME "pin_dev"
-#define BSP_USING_UART
-#define BSP_USING_USART1
-#define SERIAL_BUS_NAME_1 "usart1"
-#define SERIAL_DRV_NAME_1 "usart1_drv"
-#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
-#define BSP_USING_USART2
-#define SERIAL_BUS_NAME_2 "usart2"
-#define SERIAL_DRV_NAME_2 "usart2_drv"
-#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
-#define BSP_USING_USART3
-#define SERIAL_BUS_NAME_3 "usart3"
-#define SERIAL_DRV_NAME_3 "usart3_drv"
-#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
-#define BSP_USING_WDT
-#define WDT_BUS_NAME "wdt"
-#define WDT_DRIVER_NAME "wdt_drv"
-#define WDT_DEVICE_NAME "wdt_dev"
-
-/*  config default board resources */
-
-/*  config board app name */
-
-#define BOARD_APP_NAME "/XiUOS_stm32f407-st-discovery_app.bin"
-
-/*  config board service table */
-
-#define SERVICE_TABLE_ADDRESS 0x20000000
-
-/*  config hardware resources for connection */
-
-/*  Hardware feature */
-
-#define RESOURCES_SERIAL
-#define SERIAL_USING_DMA
-#define SERIAL_RB_BUFSZ 128
-#define RESOURCES_PIN
-#define RESOURCES_WDT
-
-/*  Kernel feature */
-
-/*  separate compile(choose none for compile once) */
-
-#define APP_STARTUP_FROM_FLASH
-
-/*  Memory Management */
-
-#define MEM_ALIGN_SIZE 8
-#define MM_PAGE_SIZE 4096
-
-/*  Using small memory allocator */
-
-#define KERNEL_SMALL_MEM_ALLOC
-#define SMALL_NUMBER_32B 64
-#define SMALL_NUMBER_64B 32
-
-/*  Task feature */
-
-#define USER_APPLICATION
-
-/*  Inter-Task communication */
-
-#define KERNEL_SEMAPHORE
-#define KERNEL_MUTEX
-#define KERNEL_EVENT
-#define KERNEL_MESSAGEQUEUE
-#define KERNEL_SOFTTIMER
-#define SCHED_POLICY_RR_REMAINSLICE
-#define KTASK_PRIORITY_32
-#define KTASK_PRIORITY_MAX 32
-#define TICK_PER_SECOND 1000
-#define KERNEL_STACK_OVERFLOW_CHECK
-#define IDLE_KTASK_STACKSIZE 256
-#define ZOMBIE_KTASK_STACKSIZE 2048
-
-/*  Kernel Console */
-
-#define KERNEL_CONSOLE
-#define KERNEL_BANNER
-#define KERNEL_CONSOLEBUF_SIZE 128
-
-/*  Kernel Hook */
-
-
-/*  Command shell */
-
-#define TOOL_SHELL
-#define SHELL_ENTER_CR
-#define SHELL_ENTER_LF
-#define SHELL_ENTER_CR_AND_LF
-
-/*  Set shell user control */
-
-#define SHELL_DEFAULT_USER "letter"
-#define SHELL_DEFAULT_USER_PASSWORD ""
-#define SHELL_LOCK_TIMEOUT 10000
-
-/*  Set shell config param */
-
-#define SHELL_TASK_STACK_SIZE 4096
-#define SHELL_TASK_PRIORITY 20
-#define SHELL_MAX_NUMBER 5
-#define SHELL_PARAMETER_MAX_NUMBER 8
-#define SHELL_HISTORY_MAX_NUMBER 5
-#define SHELL_PRINT_BUFFER 128
-#define SHELL_HELP_SHOW_PERMISSION
-
-/*  Kernel data structure Manage */
-
-#define KERNEL_QUEUEMANAGE
-#define KERNEL_WORKQUEUE
-#define WORKQUEUE_KTASK_STACKSIZE 512
-#define WORKQUEUE_KTASK_PRIORITY 23
-#define QUEUE_MAX 16
-#define KERNEL_WAITQUEUE
-#define KERNEL_DATAQUEUE
-
-/*  Kernel components init */
-
-#define KERNEL_COMPONENTS_INIT
-#define ENV_INIT_KTASK_STACK_SIZE 8192
-#define KERNEL_USER_MAIN
-#define NAME_NUM_MAX 32
-
-/*  hash table config */
-
-#define ID_HTABLE_SIZE 16
-#define ID_NUM_MAX 128
-
-/*  File system */
-
-#define FS_VFS
-#define VFS_USING_WORKDIR
-#define FS_VFS_DEVFS
-#define FS_VFS_FATFS
-
-/*  APP Framework */
-
-/*  Perception */
-
-
-/*  connection */
-
-
-/*  Intelligence */
-
-
-/*  Control */
-
-/*  Lib */
-
-#define LIB
-#define LIB_POSIX
-
-/*  C++ features */
-
-#define LIB_NEWLIB
-
-/*  Security */
-
-
-/*  Applications */
-
-
-/*  config stack size and priority of main task */
-
-#define MAIN_KTASK_STACK_SIZE 2048
-#define MAIN_KTASK_PRIORITY 10
-
-#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140738.h

@@ -1,185 +0,0 @@
-#ifndef XS_CONFIG_H__
-#define XS_CONFIG_H__
-
-/*  Automatically generated file; DO NOT EDIT. */
-/*  XiUOS Project Configuration */
-
-#define BOARD_CORTEX_M4_EVB
-#define ARCH_ARM
-
-/*  stm32f407-st-discovery feature */
-
-#define BSP_USING_DMA
-#define BSP_USING_GPIO
-#define PIN_BUS_NAME "pin"
-#define PIN_DRIVER_NAME "pin_drv"
-#define PIN_DEVICE_NAME "pin_dev"
-#define BSP_USING_UART
-#define BSP_USING_USART1
-#define SERIAL_BUS_NAME_1 "usart1"
-#define SERIAL_DRV_NAME_1 "usart1_drv"
-#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
-#define BSP_USING_USART2
-#define SERIAL_BUS_NAME_2 "usart2"
-#define SERIAL_DRV_NAME_2 "usart2_drv"
-#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
-#define BSP_USING_USART3
-#define SERIAL_BUS_NAME_3 "usart3"
-#define SERIAL_DRV_NAME_3 "usart3_drv"
-#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
-#define BSP_USING_WDT
-#define WDT_BUS_NAME "wdt"
-#define WDT_DRIVER_NAME "wdt_drv"
-#define WDT_DEVICE_NAME "wdt_dev"
-
-/*  config default board resources */
-
-/*  config board app name */
-
-#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
-
-/*  config board service table */
-
-#define SERVICE_TABLE_ADDRESS 0x20000000
-
-/*  config hardware resources for connection */
-
-/*  Hardware feature */
-
-#define RESOURCES_SERIAL
-#define SERIAL_USING_DMA
-#define SERIAL_RB_BUFSZ 128
-#define RESOURCES_PIN
-#define RESOURCES_WDT
-
-/*  Kernel feature */
-
-/*  separate compile(choose none for compile once) */
-
-#define APP_STARTUP_FROM_FLASH
-
-/*  Memory Management */
-
-#define MEM_ALIGN_SIZE 8
-#define MM_PAGE_SIZE 4096
-
-/*  Using small memory allocator */
-
-#define KERNEL_SMALL_MEM_ALLOC
-#define SMALL_NUMBER_32B 64
-#define SMALL_NUMBER_64B 32
-
-/*  Task feature */
-
-#define USER_APPLICATION
-
-/*  Inter-Task communication */
-
-#define KERNEL_SEMAPHORE
-#define KERNEL_MUTEX
-#define KERNEL_EVENT
-#define KERNEL_MESSAGEQUEUE
-#define KERNEL_SOFTTIMER
-#define SCHED_POLICY_RR_REMAINSLICE
-#define KTASK_PRIORITY_32
-#define KTASK_PRIORITY_MAX 32
-#define TICK_PER_SECOND 1000
-#define KERNEL_STACK_OVERFLOW_CHECK
-#define IDLE_KTASK_STACKSIZE 256
-#define ZOMBIE_KTASK_STACKSIZE 2048
-
-/*  Kernel Console */
-
-#define KERNEL_CONSOLE
-#define KERNEL_BANNER
-#define KERNEL_CONSOLEBUF_SIZE 128
-
-/*  Kernel Hook */
-
-
-/*  Command shell */
-
-#define TOOL_SHELL
-#define SHELL_ENTER_CR
-#define SHELL_ENTER_LF
-#define SHELL_ENTER_CR_AND_LF
-
-/*  Set shell user control */
-
-#define SHELL_DEFAULT_USER "letter"
-#define SHELL_DEFAULT_USER_PASSWORD ""
-#define SHELL_LOCK_TIMEOUT 10000
-
-/*  Set shell config param */
-
-#define SHELL_TASK_STACK_SIZE 4096
-#define SHELL_TASK_PRIORITY 20
-#define SHELL_MAX_NUMBER 5
-#define SHELL_PARAMETER_MAX_NUMBER 8
-#define SHELL_HISTORY_MAX_NUMBER 5
-#define SHELL_PRINT_BUFFER 128
-#define SHELL_HELP_SHOW_PERMISSION
-
-/*  Kernel data structure Manage */
-
-#define KERNEL_QUEUEMANAGE
-#define KERNEL_WORKQUEUE
-#define WORKQUEUE_KTASK_STACKSIZE 512
-#define WORKQUEUE_KTASK_PRIORITY 23
-#define QUEUE_MAX 16
-#define KERNEL_WAITQUEUE
-#define KERNEL_DATAQUEUE
-
-/*  Kernel components init */
-
-#define KERNEL_COMPONENTS_INIT
-#define ENV_INIT_KTASK_STACK_SIZE 8192
-#define KERNEL_USER_MAIN
-#define NAME_NUM_MAX 32
-
-/*  hash table config */
-
-#define ID_HTABLE_SIZE 16
-#define ID_NUM_MAX 128
-
-/*  File system */
-
-#define FS_VFS
-#define VFS_USING_WORKDIR
-#define FS_VFS_DEVFS
-#define FS_VFS_FATFS
-
-/*  APP Framework */
-
-/*  Perception */
-
-
-/*  connection */
-
-
-/*  Intelligence */
-
-
-/*  Control */
-
-/*  Lib */
-
-#define LIB
-#define LIB_POSIX
-
-/*  C++ features */
-
-#define LIB_NEWLIB
-
-/*  Security */
-
-
-/*  Applications */
-
-
-/*  config stack size and priority of main task */
-
-#define MAIN_KTASK_STACK_SIZE 2048
-#define MAIN_KTASK_PRIORITY 10
-
-#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140837.h

@@ -1,185 +0,0 @@
-#ifndef XS_CONFIG_H__
-#define XS_CONFIG_H__
-
-/*  Automatically generated file; DO NOT EDIT. */
-/*  XiUOS Project Configuration */
-
-#define BOARD_CORTEX_M4_EVB
-#define ARCH_ARM
-
-/*  stm32f407-st-discovery feature */
-
-#define BSP_USING_DMA
-#define BSP_USING_GPIO
-#define PIN_BUS_NAME "pin"
-#define PIN_DRIVER_NAME "pin_drv"
-#define PIN_DEVICE_NAME "pin_dev"
-#define BSP_USING_UART
-#define BSP_USING_USART1
-#define SERIAL_BUS_NAME_1 "usart1"
-#define SERIAL_DRV_NAME_1 "usart1_drv"
-#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
-#define BSP_USING_USART2
-#define SERIAL_BUS_NAME_2 "usart2"
-#define SERIAL_DRV_NAME_2 "usart2_drv"
-#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
-#define BSP_USING_USART3
-#define SERIAL_BUS_NAME_3 "usart3"
-#define SERIAL_DRV_NAME_3 "usart3_drv"
-#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
-#define BSP_USING_WDT
-#define WDT_BUS_NAME "wdt"
-#define WDT_DRIVER_NAME "wdt_drv"
-#define WDT_DEVICE_NAME "wdt_dev"
-
-/*  config default board resources */
-
-/*  config board app name */
-
-#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
-
-/*  config board service table */
-
-#define SERVICE_TABLE_ADDRESS 0x20000000
-
-/*  config hardware resources for connection */
-
-/*  Hardware feature */
-
-#define RESOURCES_SERIAL
-#define SERIAL_USING_DMA
-#define SERIAL_RB_BUFSZ 128
-#define RESOURCES_PIN
-#define RESOURCES_WDT
-
-/*  Kernel feature */
-
-/*  separate compile(choose none for compile once) */
-
-#define APP_STARTUP_FROM_FLASH
-
-/*  Memory Management */
-
-#define MEM_ALIGN_SIZE 8
-#define MM_PAGE_SIZE 4096
-
-/*  Using small memory allocator */
-
-#define KERNEL_SMALL_MEM_ALLOC
-#define SMALL_NUMBER_32B 64
-#define SMALL_NUMBER_64B 32
-
-/*  Task feature */
-
-#define USER_APPLICATION
-
-/*  Inter-Task communication */
-
-#define KERNEL_SEMAPHORE
-#define KERNEL_MUTEX
-#define KERNEL_EVENT
-#define KERNEL_MESSAGEQUEUE
-#define KERNEL_SOFTTIMER
-#define SCHED_POLICY_RR_REMAINSLICE
-#define KTASK_PRIORITY_32
-#define KTASK_PRIORITY_MAX 32
-#define TICK_PER_SECOND 1000
-#define KERNEL_STACK_OVERFLOW_CHECK
-#define IDLE_KTASK_STACKSIZE 256
-#define ZOMBIE_KTASK_STACKSIZE 2048
-
-/*  Kernel Console */
-
-#define KERNEL_CONSOLE
-#define KERNEL_BANNER
-#define KERNEL_CONSOLEBUF_SIZE 128
-
-/*  Kernel Hook */
-
-
-/*  Command shell */
-
-#define TOOL_SHELL
-#define SHELL_ENTER_CR
-#define SHELL_ENTER_LF
-#define SHELL_ENTER_CR_AND_LF
-
-/*  Set shell user control */
-
-#define SHELL_DEFAULT_USER "letter"
-#define SHELL_DEFAULT_USER_PASSWORD ""
-#define SHELL_LOCK_TIMEOUT 10000
-
-/*  Set shell config param */
-
-#define SHELL_TASK_STACK_SIZE 4096
-#define SHELL_TASK_PRIORITY 20
-#define SHELL_MAX_NUMBER 5
-#define SHELL_PARAMETER_MAX_NUMBER 8
-#define SHELL_HISTORY_MAX_NUMBER 5
-#define SHELL_PRINT_BUFFER 128
-#define SHELL_HELP_SHOW_PERMISSION
-
-/*  Kernel data structure Manage */
-
-#define KERNEL_QUEUEMANAGE
-#define KERNEL_WORKQUEUE
-#define WORKQUEUE_KTASK_STACKSIZE 512
-#define WORKQUEUE_KTASK_PRIORITY 23
-#define QUEUE_MAX 16
-#define KERNEL_WAITQUEUE
-#define KERNEL_DATAQUEUE
-
-/*  Kernel components init */
-
-#define KERNEL_COMPONENTS_INIT
-#define ENV_INIT_KTASK_STACK_SIZE 8192
-#define KERNEL_USER_MAIN
-#define NAME_NUM_MAX 32
-
-/*  hash table config */
-
-#define ID_HTABLE_SIZE 16
-#define ID_NUM_MAX 128
-
-/*  File system */
-
-#define FS_VFS
-#define VFS_USING_WORKDIR
-#define FS_VFS_DEVFS
-#define FS_VFS_FATFS
-
-/*  APP Framework */
-
-/*  Perception */
-
-
-/*  connection */
-
-
-/*  Intelligence */
-
-
-/*  Control */
-
-/*  Lib */
-
-#define LIB
-#define LIB_POSIX
-
-/*  C++ features */
-
-#define LIB_NEWLIB
-
-/*  Security */
-
-
-/*  Applications */
-
-
-/*  config stack size and priority of main task */
-
-#define MAIN_KTASK_STACK_SIZE 2048
-#define MAIN_KTASK_PRIORITY 10
-
-#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140856.h

@@ -1,185 +0,0 @@
-#ifndef XS_CONFIG_H__
-#define XS_CONFIG_H__
-
-/*  Automatically generated file; DO NOT EDIT. */
-/*  XiUOS Project Configuration */
-
-#define BOARD_CORTEX_M4_EVB
-#define ARCH_ARM
-
-/*  BOARD_CORTEX_M4_EVB feature */
-
-#define BSP_USING_DMA
-#define BSP_USING_GPIO
-#define PIN_BUS_NAME "pin"
-#define PIN_DRIVER_NAME "pin_drv"
-#define PIN_DEVICE_NAME "pin_dev"
-#define BSP_USING_UART
-#define BSP_USING_USART1
-#define SERIAL_BUS_NAME_1 "usart1"
-#define SERIAL_DRV_NAME_1 "usart1_drv"
-#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
-#define BSP_USING_USART2
-#define SERIAL_BUS_NAME_2 "usart2"
-#define SERIAL_DRV_NAME_2 "usart2_drv"
-#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
-#define BSP_USING_USART3
-#define SERIAL_BUS_NAME_3 "usart3"
-#define SERIAL_DRV_NAME_3 "usart3_drv"
-#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
-#define BSP_USING_WDT
-#define WDT_BUS_NAME "wdt"
-#define WDT_DRIVER_NAME "wdt_drv"
-#define WDT_DEVICE_NAME "wdt_dev"
-
-/*  config default board resources */
-
-/*  config board app name */
-
-#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
-
-/*  config board service table */
-
-#define SERVICE_TABLE_ADDRESS 0x20000000
-
-/*  config hardware resources for connection */
-
-/*  Hardware feature */
-
-#define RESOURCES_SERIAL
-#define SERIAL_USING_DMA
-#define SERIAL_RB_BUFSZ 128
-#define RESOURCES_PIN
-#define RESOURCES_WDT
-
-/*  Kernel feature */
-
-/*  separate compile(choose none for compile once) */
-
-#define APP_STARTUP_FROM_FLASH
-
-/*  Memory Management */
-
-#define MEM_ALIGN_SIZE 8
-#define MM_PAGE_SIZE 4096
-
-/*  Using small memory allocator */
-
-#define KERNEL_SMALL_MEM_ALLOC
-#define SMALL_NUMBER_32B 64
-#define SMALL_NUMBER_64B 32
-
-/*  Task feature */
-
-#define USER_APPLICATION
-
-/*  Inter-Task communication */
-
-#define KERNEL_SEMAPHORE
-#define KERNEL_MUTEX
-#define KERNEL_EVENT
-#define KERNEL_MESSAGEQUEUE
-#define KERNEL_SOFTTIMER
-#define SCHED_POLICY_RR_REMAINSLICE
-#define KTASK_PRIORITY_32
-#define KTASK_PRIORITY_MAX 32
-#define TICK_PER_SECOND 1000
-#define KERNEL_STACK_OVERFLOW_CHECK
-#define IDLE_KTASK_STACKSIZE 256
-#define ZOMBIE_KTASK_STACKSIZE 2048
-
-/*  Kernel Console */
-
-#define KERNEL_CONSOLE
-#define KERNEL_BANNER
-#define KERNEL_CONSOLEBUF_SIZE 128
-
-/*  Kernel Hook */
-
-
-/*  Command shell */
-
-#define TOOL_SHELL
-#define SHELL_ENTER_CR
-#define SHELL_ENTER_LF
-#define SHELL_ENTER_CR_AND_LF
-
-/*  Set shell user control */
-
-#define SHELL_DEFAULT_USER "letter"
-#define SHELL_DEFAULT_USER_PASSWORD ""
-#define SHELL_LOCK_TIMEOUT 10000
-
-/*  Set shell config param */
-
-#define SHELL_TASK_STACK_SIZE 4096
-#define SHELL_TASK_PRIORITY 20
-#define SHELL_MAX_NUMBER 5
-#define SHELL_PARAMETER_MAX_NUMBER 8
-#define SHELL_HISTORY_MAX_NUMBER 5
-#define SHELL_PRINT_BUFFER 128
-#define SHELL_HELP_SHOW_PERMISSION
-
-/*  Kernel data structure Manage */
-
-#define KERNEL_QUEUEMANAGE
-#define KERNEL_WORKQUEUE
-#define WORKQUEUE_KTASK_STACKSIZE 512
-#define WORKQUEUE_KTASK_PRIORITY 23
-#define QUEUE_MAX 16
-#define KERNEL_WAITQUEUE
-#define KERNEL_DATAQUEUE
-
-/*  Kernel components init */
-
-#define KERNEL_COMPONENTS_INIT
-#define ENV_INIT_KTASK_STACK_SIZE 8192
-#define KERNEL_USER_MAIN
-#define NAME_NUM_MAX 32
-
-/*  hash table config */
-
-#define ID_HTABLE_SIZE 16
-#define ID_NUM_MAX 128
-
-/*  File system */
-
-#define FS_VFS
-#define VFS_USING_WORKDIR
-#define FS_VFS_DEVFS
-#define FS_VFS_FATFS
-
-/*  APP Framework */
-
-/*  Perception */
-
-
-/*  connection */
-
-
-/*  Intelligence */
-
-
-/*  Control */
-
-/*  Lib */
-
-#define LIB
-#define LIB_POSIX
-
-/*  C++ features */
-
-#define LIB_NEWLIB
-
-/*  Security */
-
-
-/*  Applications */
-
-
-/*  config stack size and priority of main task */
-
-#define MAIN_KTASK_STACK_SIZE 2048
-#define MAIN_KTASK_PRIORITY 10
-
-#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140900.h

@@ -1,185 +0,0 @@
-#ifndef XS_CONFIG_H__
-#define XS_CONFIG_H__
-
-/*  Automatically generated file; DO NOT EDIT. */
-/*  XiUOS Project Configuration */
-
-#define BOARD_CORTEX_M4_EVB
-#define ARCH_ARM
-
-/*  BOARD_CORTEX_M4_EVB feature */
-
-#define BSP_USING_DMA
-#define BSP_USING_GPIO
-#define PIN_BUS_NAME "pin"
-#define PIN_DRIVER_NAME "pin_drv"
-#define PIN_DEVICE_NAME "pin_dev"
-#define BSP_USING_UART
-#define BSP_USING_USART1
-#define SERIAL_BUS_NAME_1 "usart1"
-#define SERIAL_DRV_NAME_1 "usart1_drv"
-#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
-#define BSP_USING_USART2
-#define SERIAL_BUS_NAME_2 "usart2"
-#define SERIAL_DRV_NAME_2 "usart2_drv"
-#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
-#define BSP_USING_USART3
-#define SERIAL_BUS_NAME_3 "usart3"
-#define SERIAL_DRV_NAME_3 "usart3_drv"
-#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
-#define BSP_USING_WDT
-#define WDT_BUS_NAME "wdt"
-#define WDT_DRIVER_NAME "wdt_drv"
-#define WDT_DEVICE_NAME "wdt_dev"
-
-/*  config default board resources */
-
-/*  config board app name */
-
-#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
-
-/*  config board service table */
-
-#define SERVICE_TABLE_ADDRESS 0x20000000
-
-/*  config hardware resources for connection */
-
-/*  Hardware feature */
-
-#define RESOURCES_SERIAL
-#define SERIAL_USING_DMA
-#define SERIAL_RB_BUFSZ 128
-#define RESOURCES_PIN
-#define RESOURCES_WDT
-
-/*  Kernel feature */
-
-/*  separate compile(choose none for compile once) */
-
-#define APP_STARTUP_FROM_FLASH
-
-/*  Memory Management */
-
-#define MEM_ALIGN_SIZE 8
-#define MM_PAGE_SIZE 4096
-
-/*  Using small memory allocator */
-
-#define KERNEL_SMALL_MEM_ALLOC
-#define SMALL_NUMBER_32B 64
-#define SMALL_NUMBER_64B 32
-
-/*  Task feature */
-
-#define USER_APPLICATION
-
-/*  Inter-Task communication */
-
-#define KERNEL_SEMAPHORE
-#define KERNEL_MUTEX
-#define KERNEL_EVENT
-#define KERNEL_MESSAGEQUEUE
-#define KERNEL_SOFTTIMER
-#define SCHED_POLICY_RR_REMAINSLICE
-#define KTASK_PRIORITY_32
-#define KTASK_PRIORITY_MAX 32
-#define TICK_PER_SECOND 1000
-#define KERNEL_STACK_OVERFLOW_CHECK
-#define IDLE_KTASK_STACKSIZE 256
-#define ZOMBIE_KTASK_STACKSIZE 2048
-
-/*  Kernel Console */
-
-#define KERNEL_CONSOLE
-#define KERNEL_BANNER
-#define KERNEL_CONSOLEBUF_SIZE 128
-
-/*  Kernel Hook */
-
-
-/*  Command shell */
-
-#define TOOL_SHELL
-#define SHELL_ENTER_CR
-#define SHELL_ENTER_LF
-#define SHELL_ENTER_CR_AND_LF
-
-/*  Set shell user control */
-
-#define SHELL_DEFAULT_USER "letter"
-#define SHELL_DEFAULT_USER_PASSWORD ""
-#define SHELL_LOCK_TIMEOUT 10000
-
-/*  Set shell config param */
-
-#define SHELL_TASK_STACK_SIZE 4096
-#define SHELL_TASK_PRIORITY 20
-#define SHELL_MAX_NUMBER 5
-#define SHELL_PARAMETER_MAX_NUMBER 8
-#define SHELL_HISTORY_MAX_NUMBER 5
-#define SHELL_PRINT_BUFFER 128
-#define SHELL_HELP_SHOW_PERMISSION
-
-/*  Kernel data structure Manage */
-
-#define KERNEL_QUEUEMANAGE
-#define KERNEL_WORKQUEUE
-#define WORKQUEUE_KTASK_STACKSIZE 512
-#define WORKQUEUE_KTASK_PRIORITY 23
-#define QUEUE_MAX 16
-#define KERNEL_WAITQUEUE
-#define KERNEL_DATAQUEUE
-
-/*  Kernel components init */
-
-#define KERNEL_COMPONENTS_INIT
-#define ENV_INIT_KTASK_STACK_SIZE 8192
-#define KERNEL_USER_MAIN
-#define NAME_NUM_MAX 32
-
-/*  hash table config */
-
-#define ID_HTABLE_SIZE 16
-#define ID_NUM_MAX 128
-
-/*  File system */
-
-#define FS_VFS
-#define VFS_USING_WORKDIR
-#define FS_VFS_DEVFS
-#define FS_VFS_FATFS
-
-/*  APP Framework */
-
-/*  Perception */
-
-
-/*  connection */
-
-
-/*  Intelligence */
-
-
-/*  Control */
-
-/*  Lib */
-
-#define LIB
-#define LIB_POSIX
-
-/*  C++ features */
-
-#define LIB_NEWLIB
-
-/*  Security */
-
-
-/*  Applications */
-
-
-/*  config stack size and priority of main task */
-
-#define MAIN_KTASK_STACK_SIZE 2048
-#define MAIN_KTASK_PRIORITY 10
-
-#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140901.h

@@ -1,185 +0,0 @@
-#ifndef XS_CONFIG_H__
-#define XS_CONFIG_H__
-
-/*  Automatically generated file; DO NOT EDIT. */
-/*  XiUOS Project Configuration */
-
-#define BOARD_CORTEX_M4_EVB
-#define ARCH_ARM
-
-/*  BOARD_CORTEX_M4_EVB feature */
-
-#define BSP_USING_DMA
-#define BSP_USING_GPIO
-#define PIN_BUS_NAME "pin"
-#define PIN_DRIVER_NAME "pin_drv"
-#define PIN_DEVICE_NAME "pin_dev"
-#define BSP_USING_UART
-#define BSP_USING_USART1
-#define SERIAL_BUS_NAME_1 "usart1"
-#define SERIAL_DRV_NAME_1 "usart1_drv"
-#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
-#define BSP_USING_USART2
-#define SERIAL_BUS_NAME_2 "usart2"
-#define SERIAL_DRV_NAME_2 "usart2_drv"
-#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
-#define BSP_USING_USART3
-#define SERIAL_BUS_NAME_3 "usart3"
-#define SERIAL_DRV_NAME_3 "usart3_drv"
-#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
-#define BSP_USING_WDT
-#define WDT_BUS_NAME "wdt"
-#define WDT_DRIVER_NAME "wdt_drv"
-#define WDT_DEVICE_NAME "wdt_dev"
-
-/*  config default board resources */
-
-/*  config board app name */
-
-#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
-
-/*  config board service table */
-
-#define SERVICE_TABLE_ADDRESS 0x20000000
-
-/*  config hardware resources for connection */
-
-/*  Hardware feature */
-
-#define RESOURCES_SERIAL
-#define SERIAL_USING_DMA
-#define SERIAL_RB_BUFSZ 128
-#define RESOURCES_PIN
-#define RESOURCES_WDT
-
-/*  Kernel feature */
-
-/*  separate compile(choose none for compile once) */
-
-#define APP_STARTUP_FROM_FLASH
-
-/*  Memory Management */
-
-#define MEM_ALIGN_SIZE 8
-#define MM_PAGE_SIZE 4096
-
-/*  Using small memory allocator */
-
-#define KERNEL_SMALL_MEM_ALLOC
-#define SMALL_NUMBER_32B 64
-#define SMALL_NUMBER_64B 32
-
-/*  Task feature */
-
-#define USER_APPLICATION
-
-/*  Inter-Task communication */
-
-#define KERNEL_SEMAPHORE
-#define KERNEL_MUTEX
-#define KERNEL_EVENT
-#define KERNEL_MESSAGEQUEUE
-#define KERNEL_SOFTTIMER
-#define SCHED_POLICY_RR_REMAINSLICE
-#define KTASK_PRIORITY_32
-#define KTASK_PRIORITY_MAX 32
-#define TICK_PER_SECOND 1000
-#define KERNEL_STACK_OVERFLOW_CHECK
-#define IDLE_KTASK_STACKSIZE 256
-#define ZOMBIE_KTASK_STACKSIZE 2048
-
-/*  Kernel Console */
-
-#define KERNEL_CONSOLE
-#define KERNEL_BANNER
-#define KERNEL_CONSOLEBUF_SIZE 128
-
-/*  Kernel Hook */
-
-
-/*  Command shell */
-
-#define TOOL_SHELL
-#define SHELL_ENTER_CR
-#define SHELL_ENTER_LF
-#define SHELL_ENTER_CR_AND_LF
-
-/*  Set shell user control */
-
-#define SHELL_DEFAULT_USER "letter"
-#define SHELL_DEFAULT_USER_PASSWORD ""
-#define SHELL_LOCK_TIMEOUT 10000
-
-/*  Set shell config param */
-
-#define SHELL_TASK_STACK_SIZE 4096
-#define SHELL_TASK_PRIORITY 20
-#define SHELL_MAX_NUMBER 5
-#define SHELL_PARAMETER_MAX_NUMBER 8
-#define SHELL_HISTORY_MAX_NUMBER 5
-#define SHELL_PRINT_BUFFER 128
-#define SHELL_HELP_SHOW_PERMISSION
-
-/*  Kernel data structure Manage */
-
-#define KERNEL_QUEUEMANAGE
-#define KERNEL_WORKQUEUE
-#define WORKQUEUE_KTASK_STACKSIZE 512
-#define WORKQUEUE_KTASK_PRIORITY 23
-#define QUEUE_MAX 16
-#define KERNEL_WAITQUEUE
-#define KERNEL_DATAQUEUE
-
-/*  Kernel components init */
-
-#define KERNEL_COMPONENTS_INIT
-#define ENV_INIT_KTASK_STACK_SIZE 8192
-#define KERNEL_USER_MAIN
-#define NAME_NUM_MAX 32
-
-/*  hash table config */
-
-#define ID_HTABLE_SIZE 16
-#define ID_NUM_MAX 128
-
-/*  File system */
-
-#define FS_VFS
-#define VFS_USING_WORKDIR
-#define FS_VFS_DEVFS
-#define FS_VFS_FATFS
-
-/*  APP Framework */
-
-/*  Perception */
-
-
-/*  connection */
-
-
-/*  Intelligence */
-
-
-/*  Control */
-
-/*  Lib */
-
-#define LIB
-#define LIB_POSIX
-
-/*  C++ features */
-
-#define LIB_NEWLIB
-
-/*  Security */
-
-
-/*  Applications */
-
-
-/*  config stack size and priority of main task */
-
-#define MAIN_KTASK_STACK_SIZE 2048
-#define MAIN_KTASK_PRIORITY 10
-
-#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140902.h

@@ -1,185 +0,0 @@
-#ifndef XS_CONFIG_H__
-#define XS_CONFIG_H__
-
-/*  Automatically generated file; DO NOT EDIT. */
-/*  XiUOS Project Configuration */
-
-#define BOARD_CORTEX_M4_EVB
-#define ARCH_ARM
-
-/*  BOARD_CORTEX_M4_EVB feature */
-
-#define BSP_USING_DMA
-#define BSP_USING_GPIO
-#define PIN_BUS_NAME "pin"
-#define PIN_DRIVER_NAME "pin_drv"
-#define PIN_DEVICE_NAME "pin_dev"
-#define BSP_USING_UART
-#define BSP_USING_USART1
-#define SERIAL_BUS_NAME_1 "usart1"
-#define SERIAL_DRV_NAME_1 "usart1_drv"
-#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
-#define BSP_USING_USART2
-#define SERIAL_BUS_NAME_2 "usart2"
-#define SERIAL_DRV_NAME_2 "usart2_drv"
-#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
-#define BSP_USING_USART3
-#define SERIAL_BUS_NAME_3 "usart3"
-#define SERIAL_DRV_NAME_3 "usart3_drv"
-#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
-#define BSP_USING_WDT
-#define WDT_BUS_NAME "wdt"
-#define WDT_DRIVER_NAME "wdt_drv"
-#define WDT_DEVICE_NAME "wdt_dev"
-
-/*  config default board resources */
-
-/*  config board app name */
-
-#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
-
-/*  config board service table */
-
-#define SERVICE_TABLE_ADDRESS 0x20000000
-
-/*  config hardware resources for connection */
-
-/*  Hardware feature */
-
-#define RESOURCES_SERIAL
-#define SERIAL_USING_DMA
-#define SERIAL_RB_BUFSZ 128
-#define RESOURCES_PIN
-#define RESOURCES_WDT
-
-/*  Kernel feature */
-
-/*  separate compile(choose none for compile once) */
-
-#define APP_STARTUP_FROM_FLASH
-
-/*  Memory Management */
-
-#define MEM_ALIGN_SIZE 8
-#define MM_PAGE_SIZE 4096
-
-/*  Using small memory allocator */
-
-#define KERNEL_SMALL_MEM_ALLOC
-#define SMALL_NUMBER_32B 64
-#define SMALL_NUMBER_64B 32
-
-/*  Task feature */
-
-#define USER_APPLICATION
-
-/*  Inter-Task communication */
-
-#define KERNEL_SEMAPHORE
-#define KERNEL_MUTEX
-#define KERNEL_EVENT
-#define KERNEL_MESSAGEQUEUE
-#define KERNEL_SOFTTIMER
-#define SCHED_POLICY_RR_REMAINSLICE
-#define KTASK_PRIORITY_32
-#define KTASK_PRIORITY_MAX 32
-#define TICK_PER_SECOND 1000
-#define KERNEL_STACK_OVERFLOW_CHECK
-#define IDLE_KTASK_STACKSIZE 256
-#define ZOMBIE_KTASK_STACKSIZE 2048
-
-/*  Kernel Console */
-
-#define KERNEL_CONSOLE
-#define KERNEL_BANNER
-#define KERNEL_CONSOLEBUF_SIZE 128
-
-/*  Kernel Hook */
-
-
-/*  Command shell */
-
-#define TOOL_SHELL
-#define SHELL_ENTER_CR
-#define SHELL_ENTER_LF
-#define SHELL_ENTER_CR_AND_LF
-
-/*  Set shell user control */
-
-#define SHELL_DEFAULT_USER "letter"
-#define SHELL_DEFAULT_USER_PASSWORD ""
-#define SHELL_LOCK_TIMEOUT 10000
-
-/*  Set shell config param */
-
-#define SHELL_TASK_STACK_SIZE 4096
-#define SHELL_TASK_PRIORITY 20
-#define SHELL_MAX_NUMBER 5
-#define SHELL_PARAMETER_MAX_NUMBER 8
-#define SHELL_HISTORY_MAX_NUMBER 5
-#define SHELL_PRINT_BUFFER 128
-#define SHELL_HELP_SHOW_PERMISSION
-
-/*  Kernel data structure Manage */
-
-#define KERNEL_QUEUEMANAGE
-#define KERNEL_WORKQUEUE
-#define WORKQUEUE_KTASK_STACKSIZE 512
-#define WORKQUEUE_KTASK_PRIORITY 23
-#define QUEUE_MAX 16
-#define KERNEL_WAITQUEUE
-#define KERNEL_DATAQUEUE
-
-/*  Kernel components init */
-
-#define KERNEL_COMPONENTS_INIT
-#define ENV_INIT_KTASK_STACK_SIZE 8192
-#define KERNEL_USER_MAIN
-#define NAME_NUM_MAX 32
-
-/*  hash table config */
-
-#define ID_HTABLE_SIZE 16
-#define ID_NUM_MAX 128
-
-/*  File system */
-
-#define FS_VFS
-#define VFS_USING_WORKDIR
-#define FS_VFS_DEVFS
-#define FS_VFS_FATFS
-
-/*  APP Framework */
-
-/*  Perception */
-
-
-/*  connection */
-
-
-/*  Intelligence */
-
-
-/*  Control */
-
-/*  Lib */
-
-#define LIB
-#define LIB_POSIX
-
-/*  C++ features */
-
-#define LIB_NEWLIB
-
-/*  Security */
-
-
-/*  Applications */
-
-
-/*  config stack size and priority of main task */
-
-#define MAIN_KTASK_STACK_SIZE 2048
-#define MAIN_KTASK_PRIORITY 10
-
-#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140903.h

@@ -1,185 +0,0 @@
-#ifndef XS_CONFIG_H__
-#define XS_CONFIG_H__
-
-/*  Automatically generated file; DO NOT EDIT. */
-/*  XiUOS Project Configuration */
-
-#define BOARD_CORTEX_M4_EVB
-#define ARCH_ARM
-
-/*  BOARD_CORTEX_M4_EVB feature */
-
-#define BSP_USING_DMA
-#define BSP_USING_GPIO
-#define PIN_BUS_NAME "pin"
-#define PIN_DRIVER_NAME "pin_drv"
-#define PIN_DEVICE_NAME "pin_dev"
-#define BSP_USING_UART
-#define BSP_USING_USART1
-#define SERIAL_BUS_NAME_1 "usart1"
-#define SERIAL_DRV_NAME_1 "usart1_drv"
-#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
-#define BSP_USING_USART2
-#define SERIAL_BUS_NAME_2 "usart2"
-#define SERIAL_DRV_NAME_2 "usart2_drv"
-#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
-#define BSP_USING_USART3
-#define SERIAL_BUS_NAME_3 "usart3"
-#define SERIAL_DRV_NAME_3 "usart3_drv"
-#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
-#define BSP_USING_WDT
-#define WDT_BUS_NAME "wdt"
-#define WDT_DRIVER_NAME "wdt_drv"
-#define WDT_DEVICE_NAME "wdt_dev"
-
-/*  config default board resources */
-
-/*  config board app name */
-
-#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
-
-/*  config board service table */
-
-#define SERVICE_TABLE_ADDRESS 0x20000000
-
-/*  config hardware resources for connection */
-
-/*  Hardware feature */
-
-#define RESOURCES_SERIAL
-#define SERIAL_USING_DMA
-#define SERIAL_RB_BUFSZ 128
-#define RESOURCES_PIN
-#define RESOURCES_WDT
-
-/*  Kernel feature */
-
-/*  separate compile(choose none for compile once) */
-
-#define APP_STARTUP_FROM_FLASH
-
-/*  Memory Management */
-
-#define MEM_ALIGN_SIZE 8
-#define MM_PAGE_SIZE 4096
-
-/*  Using small memory allocator */
-
-#define KERNEL_SMALL_MEM_ALLOC
-#define SMALL_NUMBER_32B 64
-#define SMALL_NUMBER_64B 32
-
-/*  Task feature */
-
-#define USER_APPLICATION
-
-/*  Inter-Task communication */
-
-#define KERNEL_SEMAPHORE
-#define KERNEL_MUTEX
-#define KERNEL_EVENT
-#define KERNEL_MESSAGEQUEUE
-#define KERNEL_SOFTTIMER
-#define SCHED_POLICY_RR_REMAINSLICE
-#define KTASK_PRIORITY_32
-#define KTASK_PRIORITY_MAX 32
-#define TICK_PER_SECOND 1000
-#define KERNEL_STACK_OVERFLOW_CHECK
-#define IDLE_KTASK_STACKSIZE 256
-#define ZOMBIE_KTASK_STACKSIZE 2048
-
-/*  Kernel Console */
-
-#define KERNEL_CONSOLE
-#define KERNEL_BANNER
-#define KERNEL_CONSOLEBUF_SIZE 128
-
-/*  Kernel Hook */
-
-
-/*  Command shell */
-
-#define TOOL_SHELL
-#define SHELL_ENTER_CR
-#define SHELL_ENTER_LF
-#define SHELL_ENTER_CR_AND_LF
-
-/*  Set shell user control */
-
-#define SHELL_DEFAULT_USER "letter"
-#define SHELL_DEFAULT_USER_PASSWORD ""
-#define SHELL_LOCK_TIMEOUT 10000
-
-/*  Set shell config param */
-
-#define SHELL_TASK_STACK_SIZE 4096
-#define SHELL_TASK_PRIORITY 20
-#define SHELL_MAX_NUMBER 5
-#define SHELL_PARAMETER_MAX_NUMBER 8
-#define SHELL_HISTORY_MAX_NUMBER 5
-#define SHELL_PRINT_BUFFER 128
-#define SHELL_HELP_SHOW_PERMISSION
-
-/*  Kernel data structure Manage */
-
-#define KERNEL_QUEUEMANAGE
-#define KERNEL_WORKQUEUE
-#define WORKQUEUE_KTASK_STACKSIZE 512
-#define WORKQUEUE_KTASK_PRIORITY 23
-#define QUEUE_MAX 16
-#define KERNEL_WAITQUEUE
-#define KERNEL_DATAQUEUE
-
-/*  Kernel components init */
-
-#define KERNEL_COMPONENTS_INIT
-#define ENV_INIT_KTASK_STACK_SIZE 8192
-#define KERNEL_USER_MAIN
-#define NAME_NUM_MAX 32
-
-/*  hash table config */
-
-#define ID_HTABLE_SIZE 16
-#define ID_NUM_MAX 128
-
-/*  File system */
-
-#define FS_VFS
-#define VFS_USING_WORKDIR
-#define FS_VFS_DEVFS
-#define FS_VFS_FATFS
-
-/*  APP Framework */
-
-/*  Perception */
-
-
-/*  connection */
-
-
-/*  Intelligence */
-
-
-/*  Control */
-
-/*  Lib */
-
-#define LIB
-#define LIB_POSIX
-
-/*  C++ features */
-
-#define LIB_NEWLIB
-
-/*  Security */
-
-
-/*  Applications */
-
-
-/*  config stack size and priority of main task */
-
-#define MAIN_KTASK_STACK_SIZE 2048
-#define MAIN_KTASK_PRIORITY 10
-
-#endif

Ubiquitous/XiUOS/board/cortex-m4-emulator/.history/xsconfig_20210825140904.h

@@ -1,185 +0,0 @@
-#ifndef XS_CONFIG_H__
-#define XS_CONFIG_H__
-
-/*  Automatically generated file; DO NOT EDIT. */
-/*  XiUOS Project Configuration */
-
-#define BOARD_CORTEX_M4_EVB
-#define ARCH_ARM
-
-/*  BOARD_CORTEX_M4_EVB feature */
-
-#define BSP_USING_DMA
-#define BSP_USING_GPIO
-#define PIN_BUS_NAME "pin"
-#define PIN_DRIVER_NAME "pin_drv"
-#define PIN_DEVICE_NAME "pin_dev"
-#define BSP_USING_UART
-#define BSP_USING_USART1
-#define SERIAL_BUS_NAME_1 "usart1"
-#define SERIAL_DRV_NAME_1 "usart1_drv"
-#define SERIAL_1_DEVICE_NAME_0 "usart1_dev1"
-#define BSP_USING_USART2
-#define SERIAL_BUS_NAME_2 "usart2"
-#define SERIAL_DRV_NAME_2 "usart2_drv"
-#define SERIAL_2_DEVICE_NAME_0 "usart2_dev2"
-#define BSP_USING_USART3
-#define SERIAL_BUS_NAME_3 "usart3"
-#define SERIAL_DRV_NAME_3 "usart3_drv"
-#define SERIAL_3_DEVICE_NAME_0 "usart3_dev3"
-#define BSP_USING_WDT
-#define WDT_BUS_NAME "wdt"
-#define WDT_DRIVER_NAME "wdt_drv"
-#define WDT_DEVICE_NAME "wdt_dev"
-
-/*  config default board resources */
-
-/*  config board app name */
-
-#define BOARD_APP_NAME "/XiUOS_cortex-m4-emulator_app.bin"
-
-/*  config board service table */
-
-#define SERVICE_TABLE_ADDRESS 0x20000000
-
-/*  config hardware resources for connection */
-
-/*  Hardware feature */
-
-#define RESOURCES_SERIAL
-#define SERIAL_USING_DMA
-#define SERIAL_RB_BUFSZ 128
-#define RESOURCES_PIN
-#define RESOURCES_WDT
-
-/*  Kernel feature */
-
-/*  separate compile(choose none for compile once) */
-
-#define APP_STARTUP_FROM_FLASH
-
-/*  Memory Management */
-
-#define MEM_ALIGN_SIZE 8
-#define MM_PAGE_SIZE 4096
-
-/*  Using small memory allocator */
-
-#define KERNEL_SMALL_MEM_ALLOC
-#define SMALL_NUMBER_32B 64
-#define SMALL_NUMBER_64B 32
-
-/*  Task feature */
-
-#define USER_APPLICATION
-
-/*  Inter-Task communication */
-
-#define KERNEL_SEMAPHORE
-#define KERNEL_MUTEX
-#define KERNEL_EVENT
-#define KERNEL_MESSAGEQUEUE
-#define KERNEL_SOFTTIMER
-#define SCHED_POLICY_RR_REMAINSLICE
-#define KTASK_PRIORITY_32
-#define KTASK_PRIORITY_MAX 32
-#define TICK_PER_SECOND 1000
-#define KERNEL_STACK_OVERFLOW_CHECK
-#define IDLE_KTASK_STACKSIZE 256
-#define ZOMBIE_KTASK_STACKSIZE 2048
-
-/*  Kernel Console */
-
-#define KERNEL_CONSOLE
-#define KERNEL_BANNER
-#define KERNEL_CONSOLEBUF_SIZE 128
-
-/*  Kernel Hook */
-
-
-/*  Command shell */
-
-#define TOOL_SHELL
-#define SHELL_ENTER_CR
-#define SHELL_ENTER_LF
-#define SHELL_ENTER_CR_AND_LF
-
-/*  Set shell user control */
-
-#define SHELL_DEFAULT_USER "letter"
-#define SHELL_DEFAULT_USER_PASSWORD ""
-#define SHELL_LOCK_TIMEOUT 10000
-
-/*  Set shell config param */
-
-#define SHELL_TASK_STACK_SIZE 4096
-#define SHELL_TASK_PRIORITY 20
-#define SHELL_MAX_NUMBER 5
-#define SHELL_PARAMETER_MAX_NUMBER 8
-#define SHELL_HISTORY_MAX_NUMBER 5
-#define SHELL_PRINT_BUFFER 128
-#define SHELL_HELP_SHOW_PERMISSION
-
-/*  Kernel data structure Manage */
-
-#define KERNEL_QUEUEMANAGE
-#define KERNEL_WORKQUEUE
-#define WORKQUEUE_KTASK_STACKSIZE 512
-#define WORKQUEUE_KTASK_PRIORITY 23
-#define QUEUE_MAX 16
-#define KERNEL_WAITQUEUE
-#define KERNEL_DATAQUEUE
-
-/*  Kernel components init */
-
-#define KERNEL_COMPONENTS_INIT
-#define ENV_INIT_KTASK_STACK_SIZE 8192
-#define KERNEL_USER_MAIN
-#define NAME_NUM_MAX 32
-
-/*  hash table config */
-
-#define ID_HTABLE_SIZE 16
-#define ID_NUM_MAX 128
-
-/*  File system */
-
-#define FS_VFS
-#define VFS_USING_WORKDIR
-#define FS_VFS_DEVFS
-#define FS_VFS_FATFS
-
-/*  APP Framework */
-
-/*  Perception */
-
-
-/*  connection */
-
-
-/*  Intelligence */
-
-
-/*  Control */
-
-/*  Lib */
-
-#define LIB
-#define LIB_POSIX
-
-/*  C++ features */
-
-#define LIB_NEWLIB
-
-/*  Security */
-
-
-/*  Applications */
-
-
-/*  config stack size and priority of main task */
-
-#define MAIN_KTASK_STACK_SIZE 2048
-#define MAIN_KTASK_PRIORITY 10
-
-#endif

Ubiquitous/XiUOS/board/stm32f103-nano/.defconfig

@@ -0,0 +1,218 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# XiUOS Project Configuration
+#
+CONFIG_BOARD_STM32F103_NANO=y
+CONFIG_KERNEL_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_ARCH_ARM=y
+
+#
+# stm32f103-nano feature
+#
+# CONFIG_BSP_USING_DMA is not set
+# CONFIG_BSP_USING_GPIO is not set
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_LCD is not set
+# CONFIG_BSP_USING_EXTMEM is not set
+# CONFIG_BSP_USING_SDIO is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_HWTIMER is not set
+# CONFIG_BSP_USING_WDT is not set
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+# CONFIG_BSP_USING_UART4 is not set
+# CONFIG_BSP_USING_UART5 is not set
+# CONFIG_BSP_USING_USB is not set
+# CONFIG_BSP_USING_USBH is not set
+
+#
+# Hardware feature
+#
+CONFIG_RESOURCES_SERIAL=y
+# CONFIG_SERIAL_USING_DMA is not set
+# CONFIG_SERIAL_RB_BUFSZ is not set
+# CONFIG_RESOURCES_CAN is not set
+# CONFIG_RESOURCES_HWTIMER is not set
+# CONFIG_RESOURCES_I2C is not set
+# CONFIG_RESOURCES_LCD is not set
+# CONFIG_RESOURCES_SDIO is not set
+# CONFIG_RESOURCES_TOUCH is not set
+CONFIG_RESOURCES_PIN=y
+# CONFIG_RESOURCES_RTC is not set
+# CONFIG_RESOURCES_SPI is not set
+# CONFIG_RESOURCES_SPI_SD is not set
+# CONFIG_RESOURCES_SPI_SFUD is not set
+# SFUD_USING_SFDP is not set
+# SFUD_USING_FLASH_INFO_TABLE is not set
+# SFUD_DEBUG_LOG is not set
+# CONFIG_RESOURCES_WDT is not set
+# CONFIG_RESOURCES_USB is not set
+# CONFIG_RESOURCES_USB_HOST is not set
+# CONFIG_UDISK_MOUNTPOINT is not set
+# CONFIG_USBH_MSTORAGE is not set
+# CONFIG_RESOURCES_USB_DEVICE is not set
+# CONFIG_USBD_THREAD_STACK_SZ is not set
+
+#
+# Kernel feature
+#
+# CONFIG_SEPARATE_COMPILE is not set
+# CONFIG_COMPILER_APP is not set
+# CONFIG_COMPILER_KERNEL is not set
+#
+# Kernel Device Object
+#
+CONFIG_KERNEL_DEVICE=y
+CONFIG_KERNEL_CONSOLE=y
+CONFIG_KERNEL_CONSOLEBUF_SIZE=128
+
+#
+# Task feature
+#
+CONFIG_SCHED_POLICY_RR_REMAINSLICE=y
+# CONFIG_SCHED_POLICY_RR is not set
+# CONFIG_SCHED_POLICY_FIFO is not set
+
+#
+# Inter-Task communication
+#
+CONFIG_KERNEL_SEMAPHORE=y
+CONFIG_KERNEL_MUTEX=y
+CONFIG_KERNEL_EVENT=y
+CONFIG_KERNEL_MESSAGEQUEUE=y
+# CONFIG_KTASK_PRIORITY_8 is not set
+CONFIG_KTASK_PRIORITY_32=y
+# CONFIG_KTASK_PRIORITY_256 is not set
+CONFIG_KTASK_PRIORITY_MAX=32
+CONFIG_TICK_PER_SECOND=1000
+CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y
+CONFIG_KERNEL_BANNER=y
+# CONFIG_KERNEL_HOOK is not set
+CONFIG_KERNEL_SOFTTIMER=y
+CONFIG_KERNEL_IDLE_HOOK=y
+CONFIG_IDEL_HOOK_LIST_SIZE=4
+CONFIG_IDLE_KTASK_STACKSIZE=256
+CONFIG_USER_APPLICATION=y
+# CONFIG_TASK_ISOLATION is not set
+
+#
+# Memory Management
+#
+# CONFIG_KERNEL_MEMBLOCK is not set
+
+#
+# Command shell
+#
+CONFIG_TOOL_SHELL=y
+CONFIG_SHELL_ENTER_CR=y
+CONFIG_SHELL_ENTER_LF=y
+CONFIG_SHELL_ENTER_CR_AND_LF=y
+# CONFIG_SHELL_ENTER_CRLF is not set
+
+#
+# User Control
+#
+CONFIG_SHELL_DEFAULT_USER="letter"
+CONFIG_SHELL_DEFAULT_USER_PASSWORD=""
+CONFIG_SHELL_LOCK_TIMEOUT=10000
+CONFIG_SHELL_TASK_STACK_SIZE=4096
+CONFIG_SHELL_TASK_PRIORITY=20
+CONFIG_SHELL_MAX_NUMBER=5
+CONFIG_SHELL_PARAMETER_MAX_NUMBER=8
+CONFIG_SHELL_HISTORY_MAX_NUMBER=5
+CONFIG_SHELL_PRINT_BUFFER=128
+CONFIG_SHELL_USING_CMD_EXPORT=y
+CONFIG_SHELL_HELP_SHOW_PERMISSION=y
+# CONFIG_SHELL_HELP_LIST_USER is not set
+# CONFIG_SHELL_HELP_LIST_VAR is not set
+# CONFIG_SHELL_HELP_LIST_KEY is not set
+CONFIG_KERNEL_QUEUEMANAGE=y
+CONFIG_KERNEL_WORKQUEUE=y
+CONFIG_WORKQUEUE_KTASK_STACKSIZE=512
+CONFIG_WORKQUEUE_KTASK_PRIORITY=23
+CONFIG_KERNEL_WAITQUEUE=y
+CONFIG_KERNEL_DATAQUEUE=y
+# CONFIG_KERNEL_CIRCULAR_AREA is not set
+# CONFIG_KERNEL_AVL_TREE is not set
+CONFIG_NAME_MAX=8
+CONFIG_ALIGN_SIZE=4
+CONFIG_KERNEL_COMPONENTS_INIT=y
+CONFIG_KERNEL_USER_MAIN=y
+CONFIG_MAIN_KTASK_STACK_SIZE=2048
+CONFIG_ENV_INIT_KTASK_STACK_SIZE=8192
+CONFIG_MAIN_KTASK_PRIORITY=10
+# CONFIG_USER_TEST is not set
+# CONFIG_TOOL_TEST_SEM is not set
+# CONFIG_TOOL_TEST_MUTEX is not set
+# CONFIG_TOOL_TEST_EVENT is not set
+# CONFIG_TOOL_TEST_MSG is not set
+# CONFIG_TOOL_TEST_AVLTREE is not set
+# CONFIG_TEST_CRICULAR_AREA is not set
+# CONFIG_TOOL_TEST_MEM is not set
+# CONFIG_TOOL_TEST_TIMER is not set
+# CONFIG_TOOL_TEST_IWG is not set
+# CONFIG_TOOL_TEST_REALTIME is not set
+# CONFIG_TOOL_TEST_DBG is not set
+# CONFIG_TOOL_TEST_SCHED is not set
+# CONFIG_KERNEL_DEBUG is not set
+CONFIG_DEBUG_INIT_CONFIG=y
+CONFIG_DBG_INIT=1
+# CONFIG_ARCH_SMP is not set
+
+#
+# File system
+#
+# CONFIG_FS_VFS is not set
+# CONFIG_VFS_USING_WORKDIR is not set
+# CONFIG_FS_VFS_DEVFS is not set
+
+#
+# Fat filesystem 
+#
+
+#
+# IOT-Device File system
+#
+
+#
+# Lwext4 filesystem 
+#
+
+#
+# APP Framework
+#
+
+#
+# connection
+#
+# CONFIG_CONNECTION_AT is not set
+# CONFIG_CONNECTION_MQTT is not set
+
+#
+# medium communication 
+#
+
+
+#
+# Intelligence
+#
+
+#
+# Control
+#
+
+#
+# Lib
+#
+CONFIG_LIB=y
+CONFIG_LIB_POSIX=y
+CONFIG_LIB_NEWLIB=y
+
+CONFIG_LITTLEVGL2RTT_USING_DEMO=y
+
+#
+# Security
+#

Ubiquitous/XiUOS/board/stm32f103-nano/Kconfig

@@ -10,21 +10,21 @@ config KERNEL_DIR
     option env="KERNEL_ROOT"
     default "../.."
 
-config BOARD_CORTEX_M4_EVB
+config BOARD_STM32F103_NANO
     bool
     select  ARCH_ARM
     default y
 
 source "$KERNEL_DIR/arch/Kconfig"
 
-menu "cortex-m4 emulator feature"
+menu "stm32f103-nano feature"
     source "$BSP_DIR/third_party_driver/Kconfig"
     
     menu "config default board resources"
         menu "config board app name"
             config BOARD_APP_NAME
                 string "config board app name"
-                default "//XiUOS_cortex-m4-emulator_app.bin"
+                default "/XiUOS_stm32f103nano_app.bin"
         endmenu
 
         menu "config board service table"
@@ -33,20 +33,6 @@ menu "cortex-m4 emulator feature"
                 default 0x20000000
         endmenu
 
-        menu "config hardware resources for connection"
-            if CONNECTION_COMMUNICATION_ETHERNET
-                config ETHERNET_UART_NAME
-                    string "ethernet uart name"
-                    default "/dev/usart3_dev3"
-            endif
-            if CONNECTION_COMMUNICATION_WIFI
-                config WIFI_UART_NAME
-                    string "wifi uart name"
-                    default "/dev/usart3_dev3"
-            endif
-
-        endmenu
-
     endmenu
 
 endmenu

Ubiquitous/XiUOS/board/stm32f103-nano/Makefile

@@ -0,0 +1,8 @@
+SRC_FILES := board.c
+
+SRC_DIR := third_party_driver
+
+
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiUOS/board/stm32f103-nano/README.md

@@ -0,0 +1,212 @@
+# 从零开始构建矽璓工业物联操作系统：使用ARM架构的STM32F103-nano开发板
+
+[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓工业物联操作系统是一款面向工业物联场景的泛在操作系统，来自泛在操作系统研究计划。所谓泛在操作系统(UOS: Ubiquitous Operating Systems)，是支持互联网时代人机物融合泛在计算应用模式的新型操作系统，是传统操作系统概念的泛化与延伸。在泛在操作系统技术体系中，不同的泛在计算设备和泛在应用场景需要符合各自特性的不同UOS，XiUOS即是面向工业物联场景的一种UOS，主要由一个极简的微型实时操作系统(RTOS)内核和其上的智能工业物联框架构成，支持工业物联网(IIoT: Industrial Internet of Things)应用。
+
+## 开发环境搭建
+
+### 推荐使用：
+
+**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop)
+
+更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改）
+
+第一步:打开sources.list文件
+
+```c
+sudo vim /etc/apt/sources.list
+```
+
+第二步:将以下内容复制到sources.list文件
+
+```c
+deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
+deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
+deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
+deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
+deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
+```
+
+第三步:更新源和系统软件
+
+```c
+sudo apt-get update
+sudo apt-get upgrade
+```
+
+**开发工具推荐使用 VSCode   ，VScode下载地址为：** VSCode  [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb)
+
+### 依赖包安装：
+
+```
+$ sudo apt install build-essential pkg-config  git
+$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
+```
+
+**XiUOS操作系统源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
+
+新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：
+
+```c
+mkdir test  &&  cd test
+git clone https://git.trustie.net/xuos/xiuos.git
+```
+
+打开源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| application | 应用代码 |
+| board | 板级支持包 |
+| framework | 应用框架 |
+| fs | 文件系统 |
+| kernel | 内核源码 |
+| resources | 驱动文件 |
+| tool | 系统工具 |
+
+使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示：
+
+<div align= "center"> 
+<img src = img/vscode.jpg  width =1000>
+  </div>
+
+### 裁减配置工具的下载
+
+裁减配置工具：
+
+**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)，下载与安装的具体命令如下：
+
+```c
+mkdir kfrontends  && cd kfrontends
+git  clone https://git.trustie.net/xuos/kconfig-frontends.git
+```
+
+下载源码后按以下步骤执行软件安装：
+
+```c
+cd kconfig-frontends
+ ./xs_build.sh
+```
+
+### 编译工具链：
+
+ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。
+
+```shell
+$ sudo apt install gcc-arm-none-eabi
+```
+
+# 在STM32F103-nano上创建第一个应用 --helloworld
+
+## 1. 简介
+
+| 硬件 | 描述 |
+| -- | -- |
+|芯片型号| Stm32F103RBT6|
+|CPU|arm cortex-m3|
+|主频| 72MHz |
+|片内SRAM| 20KB |
+|片上FLASH| 128KB |
+| 外设 | -- |
+| | ADC、DAC、USB、GPIO、UART、SPI、SDIO、RTC、CAN、DMA、MAC、I²C、WDT、Timer等 |
+
+XiUOS板级驱动当前支持使用GPIO、UART。
+
+## 2. 编译说明
+
+### 编辑环境：`Ubuntu18.04`
+
+### 编译工具链：`arm-none-eabi-gcc`
+使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目
+
+修改`applications`文件夹下`main.c`
+在输出函数中写入 `Hello, world!!! \n   Running on stm32f103-nano`完成代码编辑。
+
+![main](img/main.png)
+
+编译步骤：
+
+1.在VScode命令终端中执行以下命令，生成配置文件
+
+```c
+   make BOARD=stm32f103-nano distclean
+   make BOARD=stm32f103-nano menuconfig
+```
+
+2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
+
+![menuconfig1](img/menuconfig1.png)
+
+退出时选择`yes`保存上面所配置的内容，如下图所示：
+
+![menuconfig2](img/menuconfig2.jpg)
+
+3.继续执行以下命令，进行编译
+
+```c
+make BOARD=stm32f103-nano
+```
+
+4.如果编译正确无误，会产生XiUOS_stm32f103-nano.elf、XiUOS_stm32f103-nano.bin文件。其中XiUOS_stm32f103-nano.bin需要烧写到设备中进行运行。
+
+## 3. 烧写及执行
+
+stm32f103-nano开发板内置板载st-link SWD下载接口，连接USB后便可使用st-flash工具进行烧写bin文件。
+
+![stm32f103-nano](img/stm32f103-nano.png)
+
+### 烧写工具
+
+ARM：ST-LINK（ST-LINK V2实物如图，可在购物网站搜索关键字购买）
+
+![st-link](img/st-link.png)
+
+下载并以下执行命令以下命令安装st-link工具(本文使用v1.5.1版本)。
+
+```
+sudo apt install libusb-dev
+sudo apt install libusb-1.0-0-dev
+sudo apt  install cmake
+cd stlink
+make
+cd build/Release && make install DESTDIR=_install
+```
+
+将生成的st-flash（在stlink/build/Release/bin文件夹下）复制到/usr/bin下就可使用了
+
+代码根目录下执行st-flash工具烧录
+
+```
+sudo st-flash  write  build/XiUOS_stm32f103-nano.bin 0x8000000
+```
+
+此外，推荐用户使用putty作为终端工具，安装命令如下：
+
+```c
+sudo apt install  putty
+```
+
+打开putty配置串口信息
+
+```c
+sudo puty
+```
+
+选择ttyUSB0（这个端口号根据具体情况而定），配置波特率为115200。
+
+![putty](img/putty.png)
+
+注意：选择正确的终端端口号，最后可以执行以下命令，清除配置文件和编译生成的文件
+
+```c
+make  BOARD=stm32f103-nano distclean
+```
+
+### 3.1 运行结果
+
+如果编译 & 烧写无误，将会在串口终端上看到信息打印输出。
+
+![terminal](img/terminal.png)

Ubiquitous/XiUOS/board/stm32f103-nano/board.c

@@ -0,0 +1,94 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.c
+* @brief support stm32f103-nano-board init configure and start-up
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-11-25
+*/
+
+#include <board.h>
+#include <xiuos.h>
+#include <device.h>
+#include <arch_interrupt.h>
+#include <stm32f1xx_hal_rcc.h>
+#include <stm32f1xx_hal_rcc_ex.h>
+
+extern int InitHwUart(void);
+
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+  /**Initializes the CPU, AHB and APB busses clocks
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
+                              |RCC_OSCILLATORTYPE_LSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    //Error_Handler();
+  }
+  /**Initializes the CPU, AHB and APB busses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+  {
+    //Error_Handler();
+  }
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC;
+  PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  {
+    //Error_Handler();
+  }
+}
+
+void SysTick_Handler(int irqn, void *arg)
+{
+    TickAndTaskTimesliceUpdate();
+}
+DECLARE_HW_IRQ(SYSTICK_IRQN, SysTick_Handler, NONE);
+
+void InitBoardHardware()
+{
+  HAL_Init();
+
+  /* enable interrupt */
+  __set_PRIMASK(0);
+  /* System clock initialization */
+  SystemClock_Config();
+  /* disable interrupt */
+  __set_PRIMASK(1);
+  
+  InitHwUart();
+	InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
+	InitBoardMemory((void*)HEAP_START, (void*)HEAP_END);
+}

Ubiquitous/XiUOS/board/stm32f103-nano/board.h

@@ -0,0 +1,35 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.h
+* @brief define stm32f103-nano init configure and start-up function
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-11-25
+*/
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <stm32f1xx.h>
+#include <connect_uart.h>
+
+extern void *__bss_end;
+extern void *_heap_end;
+
+#define HEAP_START  ((void *)&__bss_end)
+#define HEAP_END    ((void *)&_heap_end)
+
+void SystemClock_Config(void);
+
+#endif

Ubiquitous/XiUOS/board/stm32f103-nano/config.mk

@@ -0,0 +1,14 @@
+export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
+
+export CFLAGS := -mcpu=cortex-m3 -mthumb  -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb 
+export AFLAGS := -c -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb  -gdwarf-2
+export LFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_stm32f103-nano.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
+export CXXFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g 
+
+export APPLFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
+
+
+export DEFINES := -DHAVE_CCONFIG_H  
+
+export ARCH = arm
+export MCU = cortex-m3

Ubiquitous/XiUOS/board/stm32f103-nano/include/arm_common_tables.h

@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. October 2015
+* $Revision: 	V.1.4.5 a
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+/* extern const q31_t realCoefAQ31[1024]; */
+/* extern const q31_t realCoefBQ31[1024]; */
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */

Ubiquitous/XiUOS/board/stm32f103-nano/include/arm_const_structs.h

@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif

Ubiquitous/XiUOS/board/stm32f103-nano/include/cmsis_armcc.h

@@ -0,0 +1,865 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

Ubiquitous/XiUOS/board/stm32f103-nano/include/cmsis_compiler.h

@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

Ubiquitous/XiUOS/board/stm32f103-nano/include/cmsis_iccarm.h

@@ -0,0 +1,935 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.7
+ * @date     19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT            __restrict
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */

Ubiquitous/XiUOS/board/stm32f103-nano/include/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

Ubiquitous/XiUOS/board/stm32f103-nano/include/core_cmFunc.h

@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */

Ubiquitous/XiUOS/board/stm32f103-nano/include/core_cmInstr.h

@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

Ubiquitous/XiUOS/board/stm32f103-nano/include/core_cmSimd.h

@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */

Ubiquitous/XiUOS/board/stm32f103-nano/include/stm32f1xx.h

@@ -0,0 +1,225 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32F1xx Device Peripheral Access Layer Header File. 
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *            - Configuration section that allows to select:
+  *              - The STM32F1xx device used in the target application
+  *              - To use or not the peripheral<EFBFBD>s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral<EFBFBD>s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f1xx
+  * @{
+  */
+    
+#ifndef __STM32F1XX_H
+#define __STM32F1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32F1)
+#define STM32F1
+#endif /* STM32F1 */
+
+#if !defined (STM32F103xB)
+#define STM32F103xB
+#define USE_HAL_DRIVER
+#endif
+
+/* Uncomment the line below according to the target STM32L device used in your 
+   application 
+  */
+
+#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
+    !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
+    !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
+  /* #define STM32F100xB  */   /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
+  /* #define STM32F100xE */    /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
+  /* #define STM32F101x6  */   /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
+  /* #define STM32F101xB  */   /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
+  /* #define STM32F101xE */    /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ 
+  /* #define STM32F101xG  */   /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
+  /* #define STM32F102x6 */    /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
+  /* #define STM32F102xB  */   /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
+  /* #define STM32F103x6  */   /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
+  /* #define STM32F103xB  */   /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
+  /* #define STM32F103xE */    /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
+  /* #define STM32F103xG  */   /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
+  /* #define STM32F105xC */    /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
+  /* #define STM32F107xC  */   /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */  
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+  
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V4.3.1
+  */
+#define __STM32F1_CMSIS_VERSION_MAIN   (0x04) /*!< [31:24] main version */
+#define __STM32F1_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
+#define __STM32F1_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F1_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F1_CMSIS_VERSION        ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
+                                       |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
+                                       |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
+                                       |(__STM32F1_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32F100xB)
+  #include "stm32f100xb.h"
+#elif defined(STM32F100xE)
+  #include "stm32f100xe.h"
+#elif defined(STM32F101x6)
+  #include "stm32f101x6.h"
+#elif defined(STM32F101xB)
+  #include "stm32f101xb.h"
+#elif defined(STM32F101xE)
+  #include "stm32f101xe.h"
+#elif defined(STM32F101xG)
+  #include "stm32f101xg.h"
+#elif defined(STM32F102x6)
+  #include "stm32f102x6.h"
+#elif defined(STM32F102xB)
+  #include "stm32f102xb.h"
+#elif defined(STM32F103x6)
+  #include "stm32f103x6.h"
+#elif defined(STM32F103xB)
+  #include "stm32f103xb.h"
+#elif defined(STM32F103xE)
+  #include "stm32f103xe.h"
+#elif defined(STM32F103xG)
+  #include "stm32f103xg.h"
+#elif defined(STM32F105xC)
+  #include "stm32f105xc.h"
+#elif defined(STM32F107xC)
+  #include "stm32f107xc.h"
+#else
+ #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */  
+typedef enum 
+{
+  RESET = 0, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum 
+{
+  DISABLE = 0, 
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  SUCCESS = 0U,
+  ST_ERROR = !SUCCESS
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include <stm32f1xx_hal.h>
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F1xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/stm32f103-nano/include/stm32f1xx_it.h

@@ -0,0 +1,85 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  *
+  * COPYRIGHT(c) 2018 STMicroelectronics
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_IT_H
+#define __STM32F1xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void USART1_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/stm32f103-nano/include/system_stm32f1xx.h

@@ -0,0 +1,98 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f10x.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f10x_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F10x_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F10x_System_Exported_types
+  * @{
+  */
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+extern const uint8_t  AHBPrescTable[16U];  /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8U];   /*!< APB prescalers table values */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F10x_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F10X_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/stm32f103-nano/link.lds

@@ -0,0 +1,107 @@
+/*
+ * linker script for STM32F10x with GNU ld
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    flash (rx) : ORIGIN = 0x08000000, LENGTH = 128k /* 128KB flash */
+    sram (rw) : ORIGIN = 0x20000000, LENGTH =  20k /* 20K sram */
+}
+OUTPUT_ARCH(arm)
+
+ENTRY(Reset_Handler)
+_system_stack_size = 0x1000;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        KEEP(*(.isr_vector))            /* Startup code */
+
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+
+        /* section information for shell */
+        . = ALIGN(4);
+        _shell_command_start = .;
+        KEEP (*(shellCommand))
+        _shell_command_end = .;
+        . = ALIGN(4);
+      
+        __isrtbl_idx_start = .;
+        KEEP(*(.isrtbl.idx))
+        __isrtbl_start = .;
+        KEEP(*(.isrtbl))
+        __isrtbl_end = .;
+        . = ALIGN(4);
+
+        PROVIDE(g_service_table_start = ABSOLUTE(.));
+        KEEP(*(.g_service_table))
+        PROVIDE(g_service_table_end = ABSOLUTE(.));
+
+        PROVIDE(_etext =  ABSOLUTE(.));
+
+        _etext = .;
+    } > flash = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > flash
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >sram
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+    } > sram
+    __bss_end = .;
+
+    _end = .;
+
+   .stack ORIGIN(sram) + LENGTH(sram) - _system_stack_size :
+    {
+    PROVIDE( _heap_end = . );
+    . = _system_stack_size;
+    PROVIDE( _sp = . );
+    } >sram 
+
+}

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/Kconfig

@@ -0,0 +1,7 @@
+menuconfig BSP_USING_UART
+bool "Using UART device"
+default y
+select RESOURCES_SERIAL
+if BSP_USING_UART
+source "$BSP_DIR/third_party_driver/uart/Kconfig"
+endif

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/Makefile

@@ -0,0 +1,7 @@
+SRC_DIR := libraries 
+
+ifeq ($(CONFIG_BSP_USING_UART),y)
+  SRC_DIR += uart
+endif
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/include/connect_uart.h

@@ -11,50 +11,38 @@
 */
  
 /**
-* @file connect_usart.h
+* @file connect_uart.h
-* @brief define stm32f407-st-discovery-board usart function and struct
+* @brief define stm32f103-nano-board uart function and struct
 * @version 1.0 
 * @author AIIT XUOS Lab
-* @date 2021-04-25
+* @date 2021-11-25
 */
 
-#ifndef CONNECT_USART_H
+#ifndef CONNECT_UART_H
-#define CONNECT_USART_H
+#define CONNECT_UART_H
 
 #include <device.h>
-#include "hardware_usart.h"
+#include <stm32f1xx_hal_uart.h>
-#include "hardware_dma.h"
+#include <stm32f103xb.h>
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#define UART_INSTANCE_CLEAR_FUNCTION    __HAL_UART_CLEAR_FLAG
+
+struct Stm32UartHwCfg
+{
+    UART_HandleTypeDef uart_handle;
+    USART_TypeDef *uart_device;
+    IRQn_Type irq_type;
+};
+
 #define KERNEL_CONSOLE_BUS_NAME       SERIAL_BUS_NAME_1
 #define KERNEL_CONSOLE_DRV_NAME       SERIAL_DRV_NAME_1
-#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
+#define KERNEL_CONSOLE_DEVICE_NAME    SERIAL_1_DEVICE_NAME_0
 
-struct UsartHwCfg
+int InitHwUart(void);
-{
-    USART_TypeDef *uart_device;
-    IRQn_Type irq;
-};
-
-struct Stm32Usart
-{
-    struct Stm32UsartDma
-    {
-        DMA_Stream_TypeDef *RxStream;
-        uint32 RxCh;
-        uint32 RxFlag;
-        uint8 RxIrqCh;
-        x_size_t SettingRecvLen;
-        x_size_t LastRecvIndex;
-    } dma;
-
-    struct SerialBus serial_bus;
-};
-
-int InitHwUsart(void);
 
 #ifdef __cplusplus
 }

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/CMSIS/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := system_stm32f1xx.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/CMSIS/system_stm32f1xx.c

@@ -0,0 +1,430 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f1xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f1xx_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
+  *    the product used), refer to "HSE_VALUE". 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f1xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F1xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f1xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_Defines
+  * @{
+  */
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE               8000000U /*!< Default value of the External oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE               8000000U /*!< Default value of the Internal oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+/*!< Uncomment the following line if you need to use external SRAM  */ 
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00000000U /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_Variables
+  * @{
+  */
+
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+uint32_t SystemCoreClock = 16000000;
+const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8U] =  {0, 0, 0, 0, 1, 2, 3, 4};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= 0x00000001U;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+  RCC->CFGR &= 0xF8FF0000U;
+#else
+  RCC->CFGR &= 0xF0FF0000U;
+#endif /* STM32F105xC */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= 0xFEF6FFFFU;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= 0xFF80FFFFU;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= 0xEBFFFFFFU;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000U;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000U;
+#elif defined(STM32F100xB) || defined(STM32F100xE)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000U;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000U;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000U;
+#endif /* STM32F105xC */
+    
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depending on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+  uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xB) || defined(STM32F100xE)
+  uint32_t prediv1factor = 0U;
+#endif /* STM32F100xB or STM32F100xE */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00U:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04U:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08U:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#if !defined(STM32F105xC) && !defined(STM32F107xC)      
+      pllmull = ( pllmull >> 18U) + 2U;
+      
+      if (pllsource == 0x00U)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
+      }
+      else
+      {
+ #if defined(STM32F100xB) || defined(STM32F100xE)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18U;
+      
+      if (pllmull != 0x0DU)
+      {
+         pllmull += 2U;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13U / 2U; 
+      }
+            
+      if (pllsource == 0x00U)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
+        
+        if (prediv1source == 0U)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F105xC */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f1xx.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f1xx_xx.s/.c before jump to main.
+  *         This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+  __IO uint32_t tmpreg;
+  /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+    required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114U;
+
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+  RCC->APB2ENR = 0x000001E0U;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
+
+  (void)(tmpreg);
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BBU;  
+  GPIOD->CRH = 0xBBBBBBBBU;
+
+  GPIOE->CRL = 0xB44444BBU;  
+  GPIOE->CRH = 0xBBBBBBBBU;
+
+  GPIOF->CRL = 0x44BBBBBBU;  
+  GPIOF->CRH = 0xBBBB4444U;
+
+  GPIOG->CRL = 0x44BBBBBBU;  
+  GPIOG->CRH = 0x444B4B44U;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4U] = 0x00001091U;
+  FSMC_Bank1->BTCR[5U] = 0x00110212U;
+}
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/Makefile

@@ -0,0 +1,3 @@
+SRC_DIR := CMSIS STM32F1xx_HAL
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/STM32F1xx_HAL/Makefile

@@ -0,0 +1,3 @@
+SRC_DIR := src
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/STM32F1xx_HAL/inc/stm32f1xx_hal.h

@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the HAL
+  *          module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_H
+#define __STM32F1xx_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_conf.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HAL
+  * @{
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+  * @{
+  */
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+  * @{
+  */
+typedef enum
+{
+  HAL_TICK_FREQ_10HZ         = 100U,
+  HAL_TICK_FREQ_100HZ        = 10U,
+  HAL_TICK_FREQ_1KHZ         = 1U,
+  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+  * @}
+  */
+/* Exported types ------------------------------------------------------------*/
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+
+/**
+  * @}
+  */
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+  * @{
+  */
+
+/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
+  * @brief   Freeze/Unfreeze Peripherals in Debug mode
+  * Note: On devices STM32F10xx8 and STM32F10xxB,
+  *                  STM32F101xC/D/E and STM32F103xC/D/E,
+  *                  STM32F101xF/G and STM32F103xF/G
+  *                  STM32F10xx4 and STM32F10xx6
+  *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
+  *       debug mode (not accessible by the user software in normal mode).
+  *       Refer to errata sheet of these devices for more details.
+  * @{
+  */
+
+/* Peripherals on APB1 */
+/**
+  * @brief  TIM2 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM2()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM2()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
+
+/**
+  * @brief  TIM3 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM3()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
+
+#if defined (DBGMCU_CR_DBG_TIM4_STOP)
+/**
+  * @brief  TIM4 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM4()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM4()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM5_STOP)
+/**
+  * @brief  TIM5 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM5()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM5()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM6_STOP)
+/**
+  * @brief  TIM6 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM6()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM6()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM7_STOP)
+/**
+  * @brief  TIM7 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM7()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM7()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM12_STOP)
+/**
+  * @brief  TIM12 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM12()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM12()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM13_STOP)
+/**
+  * @brief  TIM13 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM13()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM13()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM14_STOP)
+/**
+  * @brief  TIM14 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM14()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM14()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
+#endif
+
+/**
+  * @brief  WWDG Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_WWDG()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
+
+/**
+  * @brief  IWDG Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_IWDG()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
+
+/**
+  * @brief  I2C1 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()    SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
+
+#if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
+/**
+  * @brief  I2C2 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()    SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
+#endif
+
+#if defined (DBGMCU_CR_DBG_CAN1_STOP)
+/**
+  * @brief  CAN1 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_CAN1()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_CAN1()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_CAN2_STOP)
+/**
+  * @brief  CAN2 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_CAN2()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_CAN2()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
+#endif
+
+/* Peripherals on APB2 */
+#if defined (DBGMCU_CR_DBG_TIM1_STOP)
+/**
+  * @brief  TIM1 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM1()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM1()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM8_STOP)
+/**
+  * @brief  TIM8 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM8()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM8()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM9_STOP)
+/**
+  * @brief  TIM9 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM9()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM9()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM10_STOP)
+/**
+  * @brief  TIM10 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM10()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM10()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM11_STOP)
+/**
+  * @brief  TIM11 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM11()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM11()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
+#endif
+
+
+#if defined (DBGMCU_CR_DBG_TIM15_STOP)
+/**
+  * @brief  TIM15 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM15()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM15()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM16_STOP)
+/**
+  * @brief  TIM16 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM16()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM16()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
+#endif
+
+#if defined (DBGMCU_CR_DBG_TIM17_STOP)
+/**
+  * @brief  TIM17 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM17()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM17()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+  * @{
+  */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
+                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Functions
+  * @{
+  */
+/** @addtogroup HAL_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Variables HAL Private Variables
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Constants HAL Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/STM32F1xx_HAL/inc/stm32f1xx_hal_cec.h

@@ -0,0 +1,552 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_cec.h
+  * @author  MCD Application Team
+  * @brief   Header file of CEC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************  
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_CEC_H
+#define __STM32F1xx_HAL_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+#if defined (CEC)
+
+/** @addtogroup STM32F1xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CEC
+  * @{
+  */
+ 
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup CEC_Exported_Types CEC Exported Types
+  * @{
+  */
+/** 
+  * @brief CEC Init Structure definition  
+  */ 
+typedef struct
+{
+  uint32_t TimingErrorFree; /*!< Configures the CEC Bit Timing Error Mode. 
+                                 This parameter can be a value of @ref CEC_BitTimingErrorMode */
+  uint32_t PeriodErrorFree; /*!< Configures the CEC Bit Period Error Mode. 
+                                 This parameter can be a value of @ref CEC_BitPeriodErrorMode */
+  uint16_t  OwnAddress;     /*!< Own addresses configuration
+                                 This parameter can be a value of @ref CEC_OWN_ADDRESS */
+  uint8_t  *RxBuffer;       /*!< CEC Rx buffer pointeur */
+}CEC_InitTypeDef;
+
+/** 
+  * @brief HAL CEC State structures definition 
+  * @note  HAL CEC State value is a combination of 2 different substates: gState and RxState.
+  *        - gState contains CEC state information related to global Handle management 
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7 (not used)
+  *             x  : Should be set to 0
+  *          b6  Error information 
+  *             0  : No Error
+  *             1  : Error
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP initialized. HAL CEC Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (IP busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.  
+  */ 
+typedef enum
+{
+  HAL_CEC_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized 
+                                                   Value is allowed for gState and RxState             */
+  HAL_CEC_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
+                                                   Value is allowed for gState and RxState             */
+  HAL_CEC_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
+                                                   Value is allowed for gState only                    */
+  HAL_CEC_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
+                                                   Value is allowed for RxState only                   */
+  HAL_CEC_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing 
+                                                   Value is allowed for gState only                    */
+  HAL_CEC_STATE_BUSY_RX_TX        = 0x23U,    /*!< an internal process is ongoing
+                                                   Value is allowed for gState only                    */
+  HAL_CEC_STATE_ERROR             = 0x60U     /*!< Error Value is allowed for gState only              */
+}HAL_CEC_StateTypeDef;
+
+/** 
+  * @brief  CEC handle Structure definition  
+  */  
+typedef struct __CEC_HandleTypeDef
+{
+  CEC_TypeDef             *Instance;      /*!< CEC registers base address */
+  
+  CEC_InitTypeDef         Init;           /*!< CEC communication parameters */
+  
+  uint8_t                 *pTxBuffPtr;    /*!< Pointer to CEC Tx transfer Buffer */
+  
+  uint16_t                TxXferCount;    /*!< CEC Tx Transfer Counter */
+  
+  uint16_t                RxXferSize;     /*!< CEC Rx Transfer size, 0: header received only */
+  
+  HAL_LockTypeDef         Lock;           /*!< Locking object */
+
+  HAL_CEC_StateTypeDef    gState;         /*!< CEC state information related to global Handle management 
+                                               and also related to Tx operations.
+                                               This parameter can be a value of @ref HAL_CEC_StateTypeDef */
+  
+  HAL_CEC_StateTypeDef    RxState;        /*!< CEC state information related to Rx operations.
+                                               This parameter can be a value of @ref HAL_CEC_StateTypeDef */
+  
+  uint32_t                ErrorCode;      /*!< For errors handling purposes, copy of ISR register 
+                                               in case error is reported */  
+
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+  void  (* TxCpltCallback) ( struct __CEC_HandleTypeDef * hcec);                            /*!< CEC Tx Transfer completed callback */
+  void  (* RxCpltCallback) ( struct __CEC_HandleTypeDef * hcec, uint32_t RxFrameSize);      /*!< CEC Rx Transfer completed callback */
+  void  (* ErrorCallback)  ( struct __CEC_HandleTypeDef * hcec);                            /*!< CEC error callback */
+
+  void  (* MspInitCallback)        ( struct __CEC_HandleTypeDef * hcec);    /*!< CEC Msp Init callback              */
+  void  (* MspDeInitCallback)      ( struct __CEC_HandleTypeDef * hcec);    /*!< CEC Msp DeInit callback            */
+
+#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */											   
+}CEC_HandleTypeDef;
+
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL CEC Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_CEC_TX_CPLT_CB_ID      = 0x00U,    /*!< CEC Tx Transfer completed callback ID  */
+  HAL_CEC_RX_CPLT_CB_ID      = 0x01U,    /*!< CEC Rx Transfer completed callback ID  */
+  HAL_CEC_ERROR_CB_ID        = 0x02U,    /*!< CEC error callback  ID                 */
+  HAL_CEC_MSPINIT_CB_ID      = 0x03U,    /*!< CEC Msp Init callback ID               */
+  HAL_CEC_MSPDEINIT_CB_ID    = 0x04U     /*!< CEC Msp DeInit callback ID             */
+}HAL_CEC_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL CEC Callback pointer definition
+  */
+typedef  void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef * hcec); /*!< pointer to an CEC callback function */
+typedef  void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef * hcec, uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CEC_Exported_Constants CEC Exported Constants
+  * @{
+  */
+
+/** @defgroup CEC_Error_Code CEC Error Code
+  * @{
+  */
+#define HAL_CEC_ERROR_NONE   0x00000000U    /*!< no error */
+#define HAL_CEC_ERROR_BTE    CEC_ESR_BTE    /*!< Bit Timing Error */
+#define HAL_CEC_ERROR_BPE    CEC_ESR_BPE    /*!< Bit Period Error */
+#define HAL_CEC_ERROR_RBTFE  CEC_ESR_RBTFE  /*!< Rx Block Transfer Finished Error */
+#define HAL_CEC_ERROR_SBE    CEC_ESR_SBE    /*!< Start Bit Error */
+#define HAL_CEC_ERROR_ACKE   CEC_ESR_ACKE   /*!< Block Acknowledge Error */
+#define HAL_CEC_ERROR_LINE   CEC_ESR_LINE   /*!< Line Error */
+#define HAL_CEC_ERROR_TBTFE  CEC_ESR_TBTFE  /*!< Tx Block Transfer Finished Error */
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+#define  HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback Error  */
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup CEC_BitTimingErrorMode Bit Timing Error Mode
+  * @{
+  */ 
+#define CEC_BIT_TIMING_ERROR_MODE_STANDARD  0x00000000U      /*!< Bit timing error Standard Mode */
+#define CEC_BIT_TIMING_ERROR_MODE_ERRORFREE CEC_CFGR_BTEM    /*!< Bit timing error Free Mode */
+/**
+  * @}
+  */
+
+/** @defgroup CEC_BitPeriodErrorMode Bit Period Error Mode
+  * @{
+  */ 
+#define CEC_BIT_PERIOD_ERROR_MODE_STANDARD 0x00000000U      /*!< Bit period error Standard Mode */
+#define CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE CEC_CFGR_BPEM    /*!< Bit period error Flexible Mode */
+/**
+  * @}
+  */ 
+  
+/** @defgroup CEC_Initiator_Position   CEC Initiator logical address position in message header     
+  * @{
+  */
+#define CEC_INITIATOR_LSB_POS                  4U
+/**
+  * @}
+  */
+
+/** @defgroup CEC_OWN_ADDRESS   CEC Own Address    
+  * @{
+  */
+#define CEC_OWN_ADDRESS_NONE            CEC_OWN_ADDRESS_0    /* Reset value */
+#define CEC_OWN_ADDRESS_0              ((uint16_t)0x0000U)   /* Logical Address 0 */
+#define CEC_OWN_ADDRESS_1              ((uint16_t)0x0001U)   /* Logical Address 1 */
+#define CEC_OWN_ADDRESS_2              ((uint16_t)0x0002U)   /* Logical Address 2 */
+#define CEC_OWN_ADDRESS_3              ((uint16_t)0x0003U)   /* Logical Address 3 */
+#define CEC_OWN_ADDRESS_4              ((uint16_t)0x0004U)   /* Logical Address 4 */
+#define CEC_OWN_ADDRESS_5              ((uint16_t)0x0005U)   /* Logical Address 5 */
+#define CEC_OWN_ADDRESS_6              ((uint16_t)0x0006U)   /* Logical Address 6 */
+#define CEC_OWN_ADDRESS_7              ((uint16_t)0x0007U)   /* Logical Address 7 */
+#define CEC_OWN_ADDRESS_8              ((uint16_t)0x0008U)   /* Logical Address 8 */
+#define CEC_OWN_ADDRESS_9              ((uint16_t)0x0009U)   /* Logical Address 9 */
+#define CEC_OWN_ADDRESS_10             ((uint16_t)0x000AU)   /* Logical Address 10 */
+#define CEC_OWN_ADDRESS_11             ((uint16_t)0x000BU)   /* Logical Address 11 */
+#define CEC_OWN_ADDRESS_12             ((uint16_t)0x000CU)   /* Logical Address 12 */
+#define CEC_OWN_ADDRESS_13             ((uint16_t)0x000DU)   /* Logical Address 13 */
+#define CEC_OWN_ADDRESS_14             ((uint16_t)0x000EU)   /* Logical Address 14 */
+#define CEC_OWN_ADDRESS_15             ((uint16_t)0x000FU)   /* Logical Address 15 */
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Interrupts_Definitions  Interrupts definition
+  * @{
+  */
+#define CEC_IT_IE CEC_CFGR_IE
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Flags_Definitions  Flags definition
+  * @{
+  */
+#define CEC_FLAG_TSOM  CEC_CSR_TSOM
+#define CEC_FLAG_TEOM  CEC_CSR_TEOM
+#define CEC_FLAG_TERR  CEC_CSR_TERR
+#define CEC_FLAG_TBTRF CEC_CSR_TBTRF
+#define CEC_FLAG_RSOM  CEC_CSR_RSOM
+#define CEC_FLAG_REOM  CEC_CSR_REOM
+#define CEC_FLAG_RERR  CEC_CSR_RERR
+#define CEC_FLAG_RBTF  CEC_CSR_RBTF
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+  
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CEC_Exported_Macros CEC Exported Macros
+  * @{
+  */
+
+/** @brief  Reset CEC handle gstate & RxState
+  * @param  __HANDLE__: CEC handle.
+  * @retval None
+  */
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \
+                                                       (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \
+                                                       (__HANDLE__)->MspInitCallback = NULL;           \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;         \
+                                                     } while(0)
+#else  
+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \
+                                                       (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \
+                                                     } while(0)
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+
+/** @brief  Checks whether or not the specified CEC interrupt flag is set.
+  * @param  __HANDLE__: specifies the CEC Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *     @arg CEC_FLAG_TERR: Tx Error
+  *     @arg CEC_FLAG_TBTRF:Tx Block Transfer Finished
+  *     @arg CEC_FLAG_RERR: Rx Error
+  *     @arg CEC_FLAG_RBTF: Rx Block Transfer Finished
+  * @retval ITStatus
+  */
+#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) READ_BIT((__HANDLE__)->Instance->CSR,(__FLAG__)) 
+
+/** @brief  Clears the CEC's pending flags.
+  * @param  __HANDLE__: specifies the CEC Handle.
+  * @param  __FLAG__: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg CEC_CSR_TERR: Tx Error
+  *     @arg CEC_FLAG_TBTRF: Tx Block Transfer Finished
+  *     @arg CEC_CSR_RERR: Rx Error
+  *     @arg CEC_CSR_RBTF: Rx Block Transfer Finished
+  * @retval none  
+  */
+#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)                                                                   \
+                          do {                                                                                       \
+                            uint32_t tmp = 0x0U;                                                                     \
+                            tmp = (__HANDLE__)->Instance->CSR & 0x00000002U;                                         \
+                            (__HANDLE__)->Instance->CSR &= (uint32_t)(((~(uint32_t)(__FLAG__)) & 0xFFFFFFFCU) | tmp);\
+                          } while(0U)
+
+/** @brief  Enables the specified CEC interrupt.
+  * @param  __HANDLE__: specifies the CEC Handle.
+  * @param  __INTERRUPT__: specifies the CEC interrupt to enable.
+  *          This parameter can be:
+  *            @arg CEC_IT_IE         : Interrupt Enable.
+  * @retval none
+  */
+#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
+
+/** @brief  Disables the specified CEC interrupt.
+  * @param  __HANDLE__: specifies the CEC Handle.
+  * @param  __INTERRUPT__: specifies the CEC interrupt to disable.
+  *          This parameter can be:
+  *            @arg CEC_IT_IE         : Interrupt Enable
+  * @retval none
+  */   
+#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
+
+/** @brief  Checks whether or not the specified CEC interrupt is enabled.
+  * @param  __HANDLE__: specifies the CEC Handle.
+  * @param  __INTERRUPT__: specifies the CEC interrupt to check.
+  *          This parameter can be:
+  *            @arg CEC_IT_IE         : Interrupt Enable
+  * @retval FlagStatus  
+  */
+#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
+
+/** @brief  Enables the CEC device
+  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @retval none 
+  */
+#define __HAL_CEC_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
+
+/** @brief  Disables the CEC device
+  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @retval none 
+  */
+#define __HAL_CEC_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
+
+/** @brief  Set Transmission Start flag
+  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @retval none 
+  */
+#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
+
+/** @brief  Set Transmission End flag
+  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @retval none
+  */
+#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
+
+/** @brief  Get Transmission Start flag
+  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @retval FlagStatus 
+  */
+#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
+
+/** @brief  Get Transmission End flag
+  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @retval FlagStatus 
+  */
+#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
+
+/** @brief  Clear OAR register
+  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @retval none 
+  */
+#define __HAL_CEC_CLEAR_OAR(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->OAR, CEC_OAR_OA)
+
+/** @brief  Set OAR register
+  * @param  __HANDLE__: specifies the CEC Handle. 
+  * @param  __ADDRESS__: Own Address value.
+  * @retval none 
+  */
+#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) MODIFY_REG((__HANDLE__)->Instance->OAR, CEC_OAR_OA, (__ADDRESS__));
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CEC_Exported_Functions CEC Exported Functions
+  * @{
+  */
+
+/** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions 
+  * @{
+  */
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
+HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
+void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
+void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, pCEC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup CEC_Exported_Functions_Group2 Input and Output operation functions 
+  *  @brief CEC Transmit/Receive functions 
+  * @{
+  */
+/* I/O operation functions  ***************************************************/
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
+uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
+void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
+void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions 
+  *  @brief   CEC control functions 
+  * @{
+  */
+/* Peripheral State and Error functions ***************************************/
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CEC_Private_Types CEC Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Variables CEC Private Variables
+  * @{
+  */
+  
+/**
+  * @}
+  */ 
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Constants CEC Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CEC_Private_Macros CEC Private Macros
+  * @{
+  */
+#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BIT_TIMING_ERROR_MODE_STANDARD) || \
+                                            ((MODE) == CEC_BIT_TIMING_ERROR_MODE_ERRORFREE))
+
+#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BIT_PERIOD_ERROR_MODE_STANDARD) || \
+                                            ((MODE) == CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE))
+
+/** @brief Check CEC message size.
+  *       The message size is the payload size: without counting the header, 
+  *       it varies from 0 byte (ping operation, one header only, no payload) to 
+  *       15 bytes (1 opcode and up to 14 operands following the header). 
+  * @param  __SIZE__: CEC message size.               
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
+/** @brief Check CEC device Own Address Register (OAR) setting.
+  * @param  __ADDRESS__: CEC own address.               
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
+
+/** @brief Check CEC initiator or destination logical address setting.
+  *        Initiator and destination addresses are coded over 4 bits. 
+  * @param  __ADDRESS__: CEC initiator or logical address.               
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
+
+
+
+/**
+  * @}
+  */
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Functions CEC Private Functions
+  * @{
+  */
+  
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#endif /* CEC */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_CEC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/STM32F1xx_HAL/inc/stm32f1xx_hal_conf.h

@@ -0,0 +1,370 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_conf.h
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_CONF_H
+#define __STM32F1xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+  
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_CAN_MODULE_ENABLED   */
+/*#define HAL_CEC_MODULE_ENABLED   */
+/*#define HAL_CORTEX_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_DAC_MODULE_ENABLED   */
+/*#define HAL_DMA_MODULE_ENABLED   */
+/*#define HAL_ETH_MODULE_ENABLED   */
+/*#define HAL_FLASH_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_NOR_MODULE_ENABLED   */
+/*#define HAL_NAND_MODULE_ENABLED   */
+/*#define HAL_PCCARD_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_HCD_MODULE_ENABLED   */
+/*#define HAL_PWR_MODULE_ENABLED   */
+/*#define HAL_RCC_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SD_MODULE_ENABLED   */
+/*#define HAL_MMC_MODULE_ENABLED   */
+/*#define HAL_SDRAM_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_SRAM_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+/*#define HAL_EXTI_MODULE_ENABLED   */
+
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE               40000U    /*!< LSI Typical Value in Hz */
+#endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
+                                                The real value may vary depending on the variations
+                                                in voltage and temperature. */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            ((uint32_t)0)    /*!< tick interrupt priority (lowest by default)  */            
+#define  USE_RTOS                     0
+#define  PREFETCH_ENABLE              1
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2
+#define MAC_ADDR1   0
+#define MAC_ADDR2   0
+#define MAC_ADDR3   0
+#define MAC_ADDR4   0
+#define MAC_ADDR5   0
+
+/* Definition of the Ethernet driver buffers size and count */   
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    ((uint32_t)8)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848_PHY_ADDRESS Address*/ 
+#define DP83848_PHY_ADDRESS           0x01U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
+ 
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+  
+/* Section 4: Extended PHY Registers */
+#define PHY_SR                          ((uint16_t)0x10U)    /*!< PHY status register Offset                      */
+
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f1xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+ #include "stm32f1xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f1xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+   
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f1xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+   
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f1xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */  
+   
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f1xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f1xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f1xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f1xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f1xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f1xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f1xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f1xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f1xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f1xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f1xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f1xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f1xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f1xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f1xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */ 
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f1xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */  
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f1xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f1xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */     
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f1xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f1xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f1xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f1xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f1xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f1xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f1xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f1xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f1xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */   
+   
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/STM32F1xx_HAL/inc/stm32f1xx_hal_cortex.h

@@ -0,0 +1,410 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_CORTEX_H
+#define __STM32F1xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CORTEX
+  * @{
+  */ 
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1U)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+  * @brief  MPU Region initialization structure 
+  * @{
+  */
+typedef struct
+{
+  uint8_t                Enable;                /*!< Specifies the status of the region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
+  uint8_t                Number;                /*!< Specifies the number of the region to protect. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
+  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
+  uint8_t                Size;                  /*!< Specifies the size of the region to protect. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
+  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. 
+                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */         
+  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
+                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */                 
+  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
+  uint8_t                DisableExec;           /*!< Specifies the instruction access status. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
+  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
+  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
+  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
+}MPU_Region_InitTypeDef;
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+  * @{
+  */
+#define NVIC_PRIORITYGROUP_0         0x00000007U /*!< 0 bits for pre-emption priority
+                                                      4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         0x00000006U /*!< 1 bits for pre-emption priority
+                                                      3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         0x00000005U /*!< 2 bits for pre-emption priority
+                                                      2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         0x00000004U /*!< 3 bits for pre-emption priority
+                                                      1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4         0x00000003U /*!< 4 bits for pre-emption priority
+                                                      0 bits for subpriority */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source 
+  * @{
+  */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8    0x00000000U
+#define SYSTICK_CLKSOURCE_HCLK         0x00000004U
+
+/**
+  * @}
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+  * @{
+  */
+#define  MPU_HFNMI_PRIVDEF_NONE           0x00000000U
+#define  MPU_HARDFAULT_NMI                MPU_CTRL_HFNMIENA_Msk
+#define  MPU_PRIVILEGED_DEFAULT           MPU_CTRL_PRIVDEFENA_Msk
+#define  MPU_HFNMI_PRIVDEF               (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+  * @{
+  */
+#define  MPU_REGION_ENABLE     ((uint8_t)0x01)
+#define  MPU_REGION_DISABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+  * @{
+  */
+#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
+#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+  * @{
+  */
+#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+  * @{
+  */
+#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+  * @{
+  */
+#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
+  * @{
+  */
+#define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
+#define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
+#define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+  * @{
+  */
+#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
+#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
+#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
+#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
+#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
+#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)
+#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
+#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
+#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
+#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
+#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
+#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
+#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
+#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
+#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
+#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
+#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
+#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
+#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
+#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
+#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
+#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
+#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
+#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
+#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
+#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
+#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
+#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
+/**
+  * @}
+  */
+   
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
+  * @{
+  */
+#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)
+#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
+#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)
+#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)
+#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
+#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+  * @{
+  */
+#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)
+#define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
+#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)
+#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)
+#define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
+#define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
+#define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
+#define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+
+/* Exported Macros -----------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_Exported_Functions
+  * @{
+  */
+  
+/** @addtogroup CORTEX_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+  * @}
+  */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+
+#if (__MPU_PRESENT == 1U)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+  * @{
+  */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= (IRQn_Type)0x00U)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1U)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+                                     ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
+                                ((TYPE) == MPU_TEX_LEVEL1)  || \
+                                ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**                                                                          
+  * @}                                                                  
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_CORTEX_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/STM32F1xx_HAL/inc/stm32f1xx_hal_crc.h

@@ -0,0 +1,184 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_crc.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F1xx_HAL_CRC_H
+#define STM32F1xx_HAL_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRC_Exported_Types CRC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  CRC HAL State Structure definition
+  */
+typedef enum
+{
+  HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
+  HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
+  HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
+  HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
+  HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */
+} HAL_CRC_StateTypeDef;
+
+
+/**
+  * @brief  CRC Handle Structure definition
+  */
+typedef struct
+{
+  CRC_TypeDef                 *Instance;   /*!< Register base address        */
+
+  HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
+
+  __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
+
+} CRC_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Constants CRC Exported Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
+  * @{
+  */
+
+/** @brief Reset CRC handle state.
+  * @param  __HANDLE__ CRC handle.
+  * @retval None
+  */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
+
+/**
+  * @brief  Reset CRC Data Register.
+  * @param  __HANDLE__ CRC handle
+  * @retval None
+  */
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+
+/**
+  * @brief Store data in the Independent Data (ID) register.
+  * @param __HANDLE__ CRC handle
+  * @param __VALUE__  Value to be stored in the ID register
+  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
+  * @retval None
+  */
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
+
+/**
+  * @brief Return the data stored in the Independent Data (ID) register.
+  * @param __HANDLE__ CRC handle
+  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
+  * @retval Value of the ID register
+  */
+#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
+/**
+  * @}
+  */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup  CRC_Private_Macros CRC Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions ***********************************************/
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+/**
+  * @}
+  */
+
+/* Peripheral State and Error functions ***************************************/
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+  * @{
+  */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F1xx_HAL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/STM32F1xx_HAL/inc/stm32f1xx_hal_def.h

@@ -0,0 +1,198 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_def.h
+  * @author  MCD Application Team
+  * @brief   This file contains HAL common defines, enumeration, macros and
+  *          structures definitions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_DEF
+#define __STM32F1xx_HAL_DEF
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f1xx.h>
+#if defined(USE_HAL_LEGACY)
+#include "Legacy/stm32_hal_legacy.h"
+#endif
+#include <stddef.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  HAL Status structures definition
+  */
+typedef enum
+{
+  HAL_OK       = 0x00U,
+  HAL_ERROR    = 0x01U,
+  HAL_BUSY     = 0x02U,
+  HAL_TIMEOUT  = 0x03U
+} HAL_StatusTypeDef;
+
+/**
+  * @brief  HAL Lock structures definition
+  */
+typedef enum
+{
+  HAL_UNLOCKED = 0x00U,
+  HAL_LOCKED   = 0x01U
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+#define HAL_MAX_DELAY      0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) != 0U)
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \
+                        do{                                                      \
+                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \
+                          } while(0U)
+
+#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */
+
+/** @brief Reset the Handle's State field.
+  * @param __HANDLE__ specifies the Peripheral Handle.
+  * @note  This macro can be used for the following purpose:
+  *          - When the Handle is declared as local variable; before passing it as parameter
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+  *            to set to 0 the Handle's "State" field.
+  *            Otherwise, "State" field may have any random value and the first time the function
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+  *            (i.e. HAL_PPP_MspInit() will not be executed).
+  *          - When there is a need to reconfigure the low level hardware: instead of calling
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+  * @retval None
+  */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
+
+#if (USE_RTOS == 1U)
+/* Reserved for future use */
+#error "USE_RTOS should be 0 in the current HAL release"
+#else
+#define __HAL_LOCK(__HANDLE__)                                           \
+                                do{                                        \
+                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
+                                    {                                      \
+                                       return HAL_BUSY;                    \
+                                    }                                      \
+                                    else                                   \
+                                    {                                      \
+                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
+                                    }                                      \
+                                  }while (0U)
+
+#define __HAL_UNLOCK(__HANDLE__)                                          \
+                                  do{                                       \
+                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
+                                    }while (0U)
+#endif /* USE_RTOS */
+
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#ifndef __weak
+#define __weak   __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#ifndef __ALIGN_END
+#define __ALIGN_END    __attribute__ ((aligned (4)))
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif /* __ALIGN_BEGIN */
+#else
+#ifndef __ALIGN_END
+#define __ALIGN_END
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#if defined   (__CC_ARM)      /* ARM Compiler */
+#define __ALIGN_BEGIN    __align(4)
+#elif defined (__ICCARM__)    /* IAR Compiler */
+#define __ALIGN_BEGIN
+#endif /* __CC_ARM */
+#endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+
+/**
+  * @brief  __RAM_FUNC definition
+  */
+#if defined ( __CC_ARM   )
+/* ARM Compiler
+   ------------
+   RAM functions are defined using the toolchain options.
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog.
+*/
+#define __RAM_FUNC
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC __attribute__((section(".RamFunc")))
+
+#endif
+
+/**
+  * @brief  __NOINLINE definition
+  */
+#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )
+/* ARM & GNUCompiler
+   ----------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32F1xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/STM32F1xx_HAL/inc/stm32f1xx_hal_dma.h

@@ -0,0 +1,457 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_DMA_H
+#define __STM32F1xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+  * @{
+  */
+
+/**
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral, 
+                                           from memory to memory or from peripheral to memory.
+                                           This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+  uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                           This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+  uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
+                                           This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+  uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
+                                           This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+  uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
+                                           This parameter can be a value of @ref DMA_Memory_data_size */
+
+  uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
+                                           This parameter can be a value of @ref DMA_mode
+                                           @note The circular buffer mode cannot be used if the memory-to-memory
+                                                 data transfer is configured on the selected Channel */
+
+  uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
+                                           This parameter can be a value of @ref DMA_Priority_level */
+} DMA_InitTypeDef;
+
+/**
+  * @brief  HAL DMA State structures definition
+  */
+typedef enum
+{
+  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled    */
+  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use      */
+  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing                 */
+  HAL_DMA_STATE_TIMEOUT           = 0x03U   /*!< DMA timeout state                      */
+}HAL_DMA_StateTypeDef;
+
+/**
+  * @brief  HAL DMA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_DMA_FULL_TRANSFER           = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER           = 0x01U     /*!< Half Transfer     */
+}HAL_DMA_LevelCompleteTypeDef;
+
+/** 
+  * @brief  HAL DMA Callback ID structure definition
+  */
+typedef enum
+{
+  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half transfer     */
+  HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,    /*!< Error             */ 
+  HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,    /*!< Abort             */ 
+  HAL_DMA_XFER_ALL_CB_ID           = 0x04U     /*!< All               */ 
+    
+}HAL_DMA_CallbackIDTypeDef;
+
+/** 
+  * @brief  DMA handle Structure definition
+  */
+typedef struct __DMA_HandleTypeDef
+{
+  DMA_Channel_TypeDef   *Instance;                       /*!< Register base address                  */
+  
+  DMA_InitTypeDef       Init;                            /*!< DMA communication parameters           */ 
+  
+  HAL_LockTypeDef       Lock;                            /*!< DMA locking object                     */  
+  
+  HAL_DMA_StateTypeDef  State;                           /*!< DMA transfer state                     */
+  
+  void                  *Parent;                                                      /*!< Parent object state                    */  
+  
+  void                  (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
+  
+  void                  (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
+  
+  void                  (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
+
+  void                  (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer abort callback            */  
+  
+  __IO uint32_t         ErrorCode;                                                    /*!< DMA Error code                         */
+
+  DMA_TypeDef            *DmaBaseAddress;                                             /*!< DMA Channel Base Address               */
+  
+  uint32_t               ChannelIndex;                                                /*!< DMA Channel Index                      */  
+
+} DMA_HandleTypeDef;    
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+  * @{
+  */
+#define HAL_DMA_ERROR_NONE                     0x00000000U    /*!< No error             */
+#define HAL_DMA_ERROR_TE                       0x00000001U    /*!< Transfer error       */
+#define HAL_DMA_ERROR_NO_XFER                  0x00000004U    /*!< no ongoing transfer  */
+#define HAL_DMA_ERROR_TIMEOUT                  0x00000020U    /*!< Timeout error        */
+#define HAL_DMA_ERROR_NOT_SUPPORTED            0x00000100U    /*!< Not supported mode                    */ 
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+  * @{
+  */
+#define DMA_PERIPH_TO_MEMORY         0x00000000U                 /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)     /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction     */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+  * @{
+  */
+#define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)  /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE       0x00000000U               /*!< Peripheral increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+  * @{
+  */
+#define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */
+#define DMA_MINC_DISABLE        0x00000000U               /*!< Memory increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+  * @{
+  */
+#define DMA_PDATAALIGN_BYTE          0x00000000U                  /*!< Peripheral data alignment: Byte     */
+#define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord */
+#define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment: Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+  * @{
+  */
+#define DMA_MDATAALIGN_BYTE          0x00000000U                  /*!< Memory data alignment: Byte     */
+#define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)  /*!< Memory data alignment: Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_mode DMA mode
+  * @{
+  */
+#define DMA_NORMAL         0x00000000U                  /*!< Normal mode                  */
+#define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)     /*!< Circular mode                */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+  * @{
+  */
+#define DMA_PRIORITY_LOW             0x00000000U               /*!< Priority level : Low       */
+#define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)  /*!< Priority level : Medium    */
+#define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)  /*!< Priority level : High      */
+#define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+  * @{
+  */
+#define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
+#define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
+#define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+  * @{
+  */
+#define DMA_FLAG_GL1                      0x00000001U
+#define DMA_FLAG_TC1                      0x00000002U
+#define DMA_FLAG_HT1                      0x00000004U
+#define DMA_FLAG_TE1                      0x00000008U
+#define DMA_FLAG_GL2                      0x00000010U
+#define DMA_FLAG_TC2                      0x00000020U
+#define DMA_FLAG_HT2                      0x00000040U
+#define DMA_FLAG_TE2                      0x00000080U
+#define DMA_FLAG_GL3                      0x00000100U
+#define DMA_FLAG_TC3                      0x00000200U
+#define DMA_FLAG_HT3                      0x00000400U
+#define DMA_FLAG_TE3                      0x00000800U
+#define DMA_FLAG_GL4                      0x00001000U
+#define DMA_FLAG_TC4                      0x00002000U
+#define DMA_FLAG_HT4                      0x00004000U
+#define DMA_FLAG_TE4                      0x00008000U
+#define DMA_FLAG_GL5                      0x00010000U
+#define DMA_FLAG_TC5                      0x00020000U
+#define DMA_FLAG_HT5                      0x00040000U
+#define DMA_FLAG_TE5                      0x00080000U
+#define DMA_FLAG_GL6                      0x00100000U
+#define DMA_FLAG_TC6                      0x00200000U
+#define DMA_FLAG_HT6                      0x00400000U
+#define DMA_FLAG_TE6                      0x00800000U
+#define DMA_FLAG_GL7                      0x01000000U
+#define DMA_FLAG_TC7                      0x02000000U
+#define DMA_FLAG_HT7                      0x04000000U
+#define DMA_FLAG_TE7                      0x08000000U
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @brief  Reset DMA handle state.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+  * @brief  Enable the specified DMA Channel.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE(__HANDLE__)        (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+
+/**
+  * @brief  Disable the specified DMA Channel.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE(__HANDLE__)       (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+
+
+/* Interrupt & Flag management */
+
+/**
+  * @brief  Enables the specified DMA Channel interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
+
+/**
+  * @brief  Disable the specified DMA Channel interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
+
+/**
+  * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval The state of DMA_IT (SET or RESET).
+  */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+  * @brief  Return the number of remaining data units in the current DMA Channel transfer.
+  * @param  __HANDLE__: DMA handle
+  * @retval The number of remaining data units in the current DMA Channel transfer.
+  */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
+
+/**
+  * @}
+  */
+
+/* Include DMA HAL Extension module */
+#include "stm32f1xx_hal_dma_ex.h"   
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+  * @{
+  */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+                                            ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
+                                        ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
+                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+                                           ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
+                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
+                           ((MODE) == DMA_CIRCULAR))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
+                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+/**
+  * @}
+  */ 
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/STM32F1xx_HAL/inc/stm32f1xx_hal_dma_ex.h

@@ -0,0 +1,277 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_dma_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_DMA_EX_H
+#define __STM32F1xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMAEx DMAEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
+  * @{
+  */
+/* Interrupt & Flag management */
+#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \
+    defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
+  * @{
+  */
+
+/**
+  * @brief  Returns the current DMA Channel transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer complete flag index.
+  */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
+   DMA_FLAG_TC5)
+
+/**
+  * @brief  Returns the current DMA Channel half transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified half transfer complete flag index.
+  */      
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
+   DMA_FLAG_HT5)
+
+/**
+  * @brief  Returns the current DMA Channel transfer error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
+   DMA_FLAG_TE5)
+
+/**
+  * @brief  Return the current DMA Channel Global interrupt flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
+   DMA_FLAG_GL5)
+   
+/**
+  * @brief  Get the DMA Channel pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCx:  Transfer complete flag
+  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+  *            @arg DMA_FLAG_TEx:  Transfer error flag
+  *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.   
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
+  (DMA1->ISR & (__FLAG__)))
+
+/**
+  * @brief  Clears the DMA Channel pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCx:  Transfer complete flag
+  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+  *            @arg DMA_FLAG_TEx:  Transfer error flag
+  *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.   
+  * @retval None
+  */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
+  (DMA1->IFCR = (__FLAG__)))
+
+/**
+  * @}
+  */
+
+#else
+/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
+  * @{
+  */
+
+/**
+  * @brief  Returns the current DMA Channel transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer complete flag index.
+  */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+   DMA_FLAG_TC7)
+
+/**
+  * @brief  Return the current DMA Channel half transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified half transfer complete flag index.
+  */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+   DMA_FLAG_HT7)
+
+/**
+  * @brief  Return the current DMA Channel transfer error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+   DMA_FLAG_TE7)
+
+/**
+  * @brief  Return the current DMA Channel Global interrupt flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
+   DMA_FLAG_GL7)
+
+/**
+  * @brief  Get the DMA Channel pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCx:  Transfer complete flag
+  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+  *            @arg DMA_FLAG_TEx:  Transfer error flag
+  *            @arg DMA_FLAG_GLx:  Global interrupt flag
+  *         Where x can be 1_7 to select the DMA Channel flag.   
+  * @retval The state of FLAG (SET or RESET).
+  */
+
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)   (DMA1->ISR & (__FLAG__))
+
+/**
+  * @brief  Clear the DMA Channel pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCx:  Transfer complete flag
+  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+  *            @arg DMA_FLAG_TEx:  Transfer error flag
+  *            @arg DMA_FLAG_GLx:  Global interrupt flag
+  *         Where x can be 1_7 to select the DMA Channel flag.   
+  * @retval None
+  */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
+
+/**
+  * @}
+  */
+
+#endif
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */
+       /* STM32F103xG || STM32F105xC || STM32F107xC */
+
+#endif /* __STM32F1xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/STM32F1xx_HAL/inc/stm32f1xx_hal_flash.h

@@ -0,0 +1,328 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_flash.h
+  * @author  MCD Application Team
+  * @brief   Header file of Flash HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_FLASH_H
+#define __STM32F1xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+   
+/** @addtogroup STM32F1xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+  
+/** @addtogroup FLASH_Private_Constants
+  * @{
+  */
+#define FLASH_TIMEOUT_VALUE              50000U /* 50 s */
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Private_Macros
+  * @{
+  */
+
+#define IS_FLASH_TYPEPROGRAM(VALUE)  (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
+                                      ((VALUE) == FLASH_TYPEPROGRAM_WORD)     || \
+                                      ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))  
+
+#if   defined(FLASH_ACR_LATENCY)
+#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
+                                       ((__LATENCY__) == FLASH_LATENCY_1) || \
+                                       ((__LATENCY__) == FLASH_LATENCY_2))
+
+#else
+#define IS_FLASH_LATENCY(__LATENCY__)   ((__LATENCY__) == FLASH_LATENCY_0)
+#endif /* FLASH_ACR_LATENCY */
+/**
+  * @}
+  */  
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+  * @{
+  */  
+
+/**
+  * @brief  FLASH Procedure structure definition
+  */
+typedef enum 
+{
+  FLASH_PROC_NONE              = 0U, 
+  FLASH_PROC_PAGEERASE         = 1U,
+  FLASH_PROC_MASSERASE         = 2U,
+  FLASH_PROC_PROGRAMHALFWORD   = 3U,
+  FLASH_PROC_PROGRAMWORD       = 4U,
+  FLASH_PROC_PROGRAMDOUBLEWORD = 5U
+} FLASH_ProcedureTypeDef;
+
+/** 
+  * @brief  FLASH handle Structure definition  
+  */
+typedef struct
+{
+  __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
+  
+  __IO uint32_t               DataRemaining;    /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
+
+  __IO uint32_t               Address;          /*!< Internal variable to save address selected for program or erase */
+
+  __IO uint64_t               Data;             /*!< Internal variable to save data to be programmed */
+
+  HAL_LockTypeDef             Lock;             /*!< FLASH locking object                */
+
+  __IO uint32_t               ErrorCode;        /*!< FLASH error code                    
+                                                     This parameter can be a value of @ref FLASH_Error_Codes  */
+} FLASH_ProcessTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+  * @{
+  */  
+
+/** @defgroup FLASH_Error_Codes FLASH Error Codes
+  * @{
+  */
+
+#define HAL_FLASH_ERROR_NONE      0x00U  /*!< No error */
+#define HAL_FLASH_ERROR_PROG      0x01U  /*!< Programming error */
+#define HAL_FLASH_ERROR_WRP       0x02U  /*!< Write protection error */
+#define HAL_FLASH_ERROR_OPTV      0x04U  /*!< Option validity error */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Type_Program FLASH Type Program
+  * @{
+  */ 
+#define FLASH_TYPEPROGRAM_HALFWORD             0x01U  /*!<Program a half-word (16-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_WORD                 0x02U  /*!<Program a word (32-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_DOUBLEWORD           0x03U  /*!<Program a double word (64-bit) at a specified address*/
+
+/**
+  * @}
+  */
+
+#if   defined(FLASH_ACR_LATENCY)
+/** @defgroup FLASH_Latency FLASH Latency
+  * @{
+  */
+#define FLASH_LATENCY_0            0x00000000U               /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_1            FLASH_ACR_LATENCY_0       /*!< FLASH One Latency cycle */
+#define FLASH_LATENCY_2            FLASH_ACR_LATENCY_1       /*!< FLASH Two Latency cycles */
+
+/**
+  * @}
+  */
+
+#else
+/** @defgroup FLASH_Latency FLASH Latency
+  * @{
+  */
+#define FLASH_LATENCY_0            0x00000000U    /*!< FLASH Zero Latency cycle */
+
+/**
+  * @}
+  */
+
+#endif /* FLASH_ACR_LATENCY */
+/**
+  * @}
+  */  
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+ *  @brief macros to control FLASH features 
+ *  @{
+ */
+ 
+/** @defgroup FLASH_Half_Cycle FLASH Half Cycle
+ *  @brief macros to handle FLASH half cycle
+ * @{
+ */
+
+/**
+  * @brief  Enable the FLASH half cycle access.
+  * @note   half cycle access can only be used with a low-frequency clock of less than
+            8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
+  * @retval None
+  */
+#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE()  (FLASH->ACR |= FLASH_ACR_HLFCYA)
+
+/**
+  * @brief  Disable the FLASH half cycle access.
+  * @note   half cycle access can only be used with a low-frequency clock of less than
+            8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
+  * @retval None
+  */
+#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
+
+/**
+  * @}
+  */
+
+#if defined(FLASH_ACR_LATENCY)
+/** @defgroup FLASH_EM_Latency FLASH Latency
+ *  @brief macros to handle FLASH Latency
+ * @{
+ */ 
+  
+/**
+  * @brief  Set the FLASH Latency.
+  * @param  __LATENCY__ FLASH Latency                   
+  *         The value of this parameter depend on device used within the same series
+  * @retval None
+  */ 
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__)    (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
+
+
+/**
+  * @brief  Get the FLASH Latency.
+  * @retval FLASH Latency                   
+  *         The value of this parameter depend on device used within the same series
+  */ 
+#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
+/**
+  * @}
+  */
+
+#endif /* FLASH_ACR_LATENCY */
+/** @defgroup FLASH_Prefetch FLASH Prefetch
+ *  @brief macros to handle FLASH Prefetch buffer
+ * @{
+ */   
+/**
+  * @brief  Enable the FLASH prefetch buffer.
+  * @retval None
+  */ 
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    (FLASH->ACR |= FLASH_ACR_PRFTBE)
+
+/**
+  * @brief  Disable the FLASH prefetch buffer.
+  * @retval None
+  */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/* Include FLASH HAL Extended module */
+#include "stm32f1xx_hal_flash_ex.h"  
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+  * @{
+  */
+  
+/** @addtogroup FLASH_Exported_Functions_Group1
+  * @{
+  */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+
+/* FLASH IRQ handler function */
+void       HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */ 
+void       HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void       HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+void HAL_FLASH_OB_Launch(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State and Error functions ***************************************/
+uint32_t HAL_FLASH_GetError(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private function -------------------------------------------------*/
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+HAL_StatusTypeDef       FLASH_WaitForLastOperation(uint32_t Timeout);
+#if defined(FLASH_BANK2_END)
+HAL_StatusTypeDef       FLASH_WaitForLastOperationBank2(uint32_t Timeout);
+#endif /* FLASH_BANK2_END */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/STM32F1xx_HAL/inc/stm32f1xx_hal_flash_ex.h

@@ -0,0 +1,786 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_flash_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of Flash HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_FLASH_EX_H
+#define __STM32F1xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASHEx
+  * @{
+  */ 
+
+/** @addtogroup FLASHEx_Private_Constants
+  * @{
+  */
+
+#define FLASH_SIZE_DATA_REGISTER     0x1FFFF7E0U
+#define OBR_REG_INDEX                1U
+#define SR_FLAG_MASK                 ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))
+
+/**
+  * @}
+  */  
+
+/** @addtogroup FLASHEx_Private_Macros
+  * @{
+  */
+
+#define IS_FLASH_TYPEERASE(VALUE)   (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#define IS_OPTIONBYTE(VALUE)        (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
+
+#define IS_WRPSTATE(VALUE)          (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
+
+#define IS_OB_RDP_LEVEL(LEVEL)      (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) 
+
+#define IS_OB_IWDG_SOURCE(SOURCE)   (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE)   (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE)  (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#if defined(FLASH_BANK2_END)
+#define IS_OB_BOOT1(BOOT1)         (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
+#endif /* FLASH_BANK2_END */
+
+/* Low Density */
+#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \
+                                           ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU))
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+
+/* Medium Density */
+#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
+                                           (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \
+                                           (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \
+                                           ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU))))
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
+
+/* High Density */
+#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \
+                                           (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \
+                                           ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU)))
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+
+/* XL Density */
+#if defined(FLASH_BANK2_END)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \
+                                           ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU))
+#endif /* FLASH_BANK2_END */
+
+/* Connectivity Line */
+#if (defined(STM32F105xC) || defined(STM32F107xC))
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \
+                                           (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) ==  0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
+                                           ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU)))
+#endif /* STM32F105xC || STM32F107xC */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
+
+#if defined(FLASH_BANK2_END)
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)  || \
+                             ((BANK) == FLASH_BANK_2)  || \
+                             ((BANK) == FLASH_BANK_BOTH))
+#else
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
+#endif /* FLASH_BANK2_END */
+
+/* Low Density */
+#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)  (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
+                                            ((ADDRESS) <= FLASH_BANK1_END) :  ((ADDRESS) <= 0x08003FFFU)))
+
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+
+/* Medium Density */
+#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
+                                           ((ADDRESS) <= FLASH_BANK1_END) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
+                                           ((ADDRESS) <= 0x0800FFFF) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
+                                           ((ADDRESS) <= 0x08007FFF) :  ((ADDRESS) <= 0x08003FFFU)))))
+
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
+
+/* High Density */
+#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \
+                                           ((ADDRESS) <= FLASH_BANK1_END) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \
+                                           ((ADDRESS) <= 0x0805FFFFU) :  ((ADDRESS) <= 0x0803FFFFU))))
+
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+
+/* XL Density */
+#if defined(FLASH_BANK2_END)
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \
+                                           ((ADDRESS) <= FLASH_BANK2_END) :  ((ADDRESS) <= 0x080BFFFFU)))
+
+#endif /* FLASH_BANK2_END */
+
+/* Connectivity Line */
+#if (defined(STM32F105xC) || defined(STM32F107xC))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \
+                                           ((ADDRESS) <= FLASH_BANK1_END) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
+                                           ((ADDRESS) <= 0x0801FFFFU) :  ((ADDRESS) <= 0x0800FFFFU))))
+
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+  * @}
+  */  
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
+  * @{
+  */  
+
+/**
+  * @brief  FLASH Erase structure definition
+  */
+typedef struct
+{
+  uint32_t TypeErase;   /*!< TypeErase: Mass erase or page erase.
+                             This parameter can be a value of @ref FLASHEx_Type_Erase */
+  
+  uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
+                             This parameter must be a value of @ref FLASHEx_Banks */    
+  
+  uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
+                             This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END 
+                             (x = 1 or 2 depending on devices)*/
+  
+  uint32_t NbPages;     /*!< NbPages: Number of pagess to be erased.
+                             This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
+                                                          
+} FLASH_EraseInitTypeDef;
+
+/**
+  * @brief  FLASH Options bytes program structure definition
+  */
+typedef struct
+{
+  uint32_t OptionType;  /*!< OptionType: Option byte to be configured.
+                             This parameter can be a value of @ref FLASHEx_OB_Type */
+
+  uint32_t WRPState;    /*!< WRPState: Write protection activation or deactivation.
+                             This parameter can be a value of @ref FLASHEx_OB_WRP_State */
+
+  uint32_t WRPPage;     /*!< WRPPage: specifies the page(s) to be write protected
+                             This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
+
+  uint32_t Banks;        /*!< Select banks for WRP activation/deactivation of all sectors.
+                              This parameter must be a value of @ref FLASHEx_Banks */ 
+    
+  uint8_t RDPLevel;     /*!< RDPLevel: Set the read protection level..
+                             This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
+
+#if defined(FLASH_BANK2_END)
+  uint8_t USERConfig;   /*!< USERConfig: Program the FLASH User Option Byte: 
+                             IWDG / STOP / STDBY / BOOT1
+                             This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, 
+                             @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */
+#else
+  uint8_t USERConfig;   /*!< USERConfig: Program the FLASH User Option Byte: 
+                             IWDG / STOP / STDBY
+                             This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, 
+                             @ref FLASHEx_OB_nRST_STDBY */
+#endif /* FLASH_BANK2_END */
+
+  uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
+                             This parameter can be a value of @ref FLASHEx_OB_Data_Address */
+  
+  uint8_t DATAData;     /*!< DATAData: Data to be stored in the option byte DATA
+                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+} FLASH_OBProgramInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
+  * @{
+  */  
+
+/** @defgroup FLASHEx_Constants FLASH Constants
+  * @{
+  */ 
+
+/** @defgroup FLASHEx_Page_Size Page Size
+  * @{
+  */ 
+#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
+#define FLASH_PAGE_SIZE          0x400U
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+       /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC))
+#define FLASH_PAGE_SIZE          0x800U
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+       /* STM32F101xG || STM32F103xG */ 
+       /* STM32F105xC || STM32F107xC */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Type_Erase Type Erase
+  * @{
+  */ 
+#define FLASH_TYPEERASE_PAGES     0x00U  /*!<Pages erase only*/
+#define FLASH_TYPEERASE_MASSERASE 0x02U  /*!<Flash mass erase activation*/
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_Banks Banks
+  * @{
+  */
+#if defined(FLASH_BANK2_END)
+#define FLASH_BANK_1     1U /*!< Bank 1   */
+#define FLASH_BANK_2     2U /*!< Bank 2   */
+#define FLASH_BANK_BOTH  ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
+
+#else
+#define FLASH_BANK_1     1U /*!< Bank 1   */
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
+  * @{
+  */ 
+
+/** @defgroup FLASHEx_OB_Type Option Bytes Type
+  * @{
+  */
+#define OPTIONBYTE_WRP            0x01U  /*!<WRP option byte configuration*/
+#define OPTIONBYTE_RDP            0x02U  /*!<RDP option byte configuration*/
+#define OPTIONBYTE_USER           0x04U  /*!<USER option byte configuration*/
+#define OPTIONBYTE_DATA           0x08U  /*!<DATA option byte configuration*/
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
+  * @{
+  */ 
+#define OB_WRPSTATE_DISABLE       0x00U  /*!<Disable the write protection of the desired pages*/
+#define OB_WRPSTATE_ENABLE        0x01U  /*!<Enable the write protection of the desired pagess*/
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_Write_Protection Option Bytes Write Protection
+  * @{
+  */
+/* STM32 Low and Medium density devices */
+#if  defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) \
+  || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) \
+  || defined(STM32F103xB)
+#define OB_WRP_PAGES0TO3               0x00000001U /*!< Write protection of page 0 to 3 */
+#define OB_WRP_PAGES4TO7               0x00000002U /*!< Write protection of page 4 to 7 */
+#define OB_WRP_PAGES8TO11              0x00000004U /*!< Write protection of page 8 to 11 */
+#define OB_WRP_PAGES12TO15             0x00000008U /*!< Write protection of page 12 to 15 */
+#define OB_WRP_PAGES16TO19             0x00000010U /*!< Write protection of page 16 to 19 */
+#define OB_WRP_PAGES20TO23             0x00000020U /*!< Write protection of page 20 to 23 */
+#define OB_WRP_PAGES24TO27             0x00000040U /*!< Write protection of page 24 to 27 */
+#define OB_WRP_PAGES28TO31             0x00000080U /*!< Write protection of page 28 to 31 */
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+       /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+       
+/* STM32 Medium-density devices */
+#if  defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+#define OB_WRP_PAGES32TO35             0x00000100U   /*!< Write protection of page 32 to 35 */
+#define OB_WRP_PAGES36TO39             0x00000200U   /*!< Write protection of page 36 to 39 */
+#define OB_WRP_PAGES40TO43             0x00000400U   /*!< Write protection of page 40 to 43 */
+#define OB_WRP_PAGES44TO47             0x00000800U   /*!< Write protection of page 44 to 47 */
+#define OB_WRP_PAGES48TO51             0x00001000U   /*!< Write protection of page 48 to 51 */
+#define OB_WRP_PAGES52TO55             0x00002000U   /*!< Write protection of page 52 to 55 */
+#define OB_WRP_PAGES56TO59             0x00004000U   /*!< Write protection of page 56 to 59 */
+#define OB_WRP_PAGES60TO63             0x00008000U   /*!< Write protection of page 60 to 63 */
+#define OB_WRP_PAGES64TO67             0x00010000U   /*!< Write protection of page 64 to 67 */
+#define OB_WRP_PAGES68TO71             0x00020000U   /*!< Write protection of page 68 to 71 */
+#define OB_WRP_PAGES72TO75             0x00040000U   /*!< Write protection of page 72 to 75 */
+#define OB_WRP_PAGES76TO79             0x00080000U   /*!< Write protection of page 76 to 79 */
+#define OB_WRP_PAGES80TO83             0x00100000U   /*!< Write protection of page 80 to 83 */
+#define OB_WRP_PAGES84TO87             0x00200000U   /*!< Write protection of page 84 to 87 */
+#define OB_WRP_PAGES88TO91             0x00400000U   /*!< Write protection of page 88 to 91 */
+#define OB_WRP_PAGES92TO95             0x00800000U   /*!< Write protection of page 92 to 95 */
+#define OB_WRP_PAGES96TO99             0x01000000U   /*!< Write protection of page 96 to 99 */
+#define OB_WRP_PAGES100TO103           0x02000000U   /*!< Write protection of page 100 to 103 */
+#define OB_WRP_PAGES104TO107           0x04000000U   /*!< Write protection of page 104 to 107 */
+#define OB_WRP_PAGES108TO111           0x08000000U   /*!< Write protection of page 108 to 111 */
+#define OB_WRP_PAGES112TO115           0x10000000U   /*!< Write protection of page 112 to 115 */
+#define OB_WRP_PAGES116TO119           0x20000000U   /*!< Write protection of page 115 to 119 */
+#define OB_WRP_PAGES120TO123           0x40000000U   /*!< Write protection of page 120 to 123 */
+#define OB_WRP_PAGES124TO127           0x80000000U    /*!< Write protection of page 124 to 127 */
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+
+
+/* STM32 High-density, XL-density and Connectivity line devices */
+#if  defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \
+  || defined(STM32F101xG) || defined(STM32F103xG) \
+  || defined(STM32F105xC) || defined(STM32F107xC)
+#define OB_WRP_PAGES0TO1               0x00000001U  /*!< Write protection of page 0 TO 1 */
+#define OB_WRP_PAGES2TO3               0x00000002U  /*!< Write protection of page 2 TO 3 */
+#define OB_WRP_PAGES4TO5               0x00000004U  /*!< Write protection of page 4 TO 5 */
+#define OB_WRP_PAGES6TO7               0x00000008U  /*!< Write protection of page 6 TO 7 */
+#define OB_WRP_PAGES8TO9               0x00000010U  /*!< Write protection of page 8 TO 9 */
+#define OB_WRP_PAGES10TO11             0x00000020U  /*!< Write protection of page 10 TO 11 */
+#define OB_WRP_PAGES12TO13             0x00000040U  /*!< Write protection of page 12 TO 13 */
+#define OB_WRP_PAGES14TO15             0x00000080U  /*!< Write protection of page 14 TO 15 */
+#define OB_WRP_PAGES16TO17             0x00000100U  /*!< Write protection of page 16 TO 17 */
+#define OB_WRP_PAGES18TO19             0x00000200U  /*!< Write protection of page 18 TO 19 */
+#define OB_WRP_PAGES20TO21             0x00000400U  /*!< Write protection of page 20 TO 21 */
+#define OB_WRP_PAGES22TO23             0x00000800U  /*!< Write protection of page 22 TO 23 */
+#define OB_WRP_PAGES24TO25             0x00001000U  /*!< Write protection of page 24 TO 25 */
+#define OB_WRP_PAGES26TO27             0x00002000U  /*!< Write protection of page 26 TO 27 */
+#define OB_WRP_PAGES28TO29             0x00004000U  /*!< Write protection of page 28 TO 29 */
+#define OB_WRP_PAGES30TO31             0x00008000U  /*!< Write protection of page 30 TO 31 */
+#define OB_WRP_PAGES32TO33             0x00010000U  /*!< Write protection of page 32 TO 33 */
+#define OB_WRP_PAGES34TO35             0x00020000U  /*!< Write protection of page 34 TO 35 */
+#define OB_WRP_PAGES36TO37             0x00040000U  /*!< Write protection of page 36 TO 37 */
+#define OB_WRP_PAGES38TO39             0x00080000U  /*!< Write protection of page 38 TO 39 */
+#define OB_WRP_PAGES40TO41             0x00100000U  /*!< Write protection of page 40 TO 41 */
+#define OB_WRP_PAGES42TO43             0x00200000U  /*!< Write protection of page 42 TO 43 */
+#define OB_WRP_PAGES44TO45             0x00400000U  /*!< Write protection of page 44 TO 45 */
+#define OB_WRP_PAGES46TO47             0x00800000U  /*!< Write protection of page 46 TO 47 */
+#define OB_WRP_PAGES48TO49             0x01000000U  /*!< Write protection of page 48 TO 49 */
+#define OB_WRP_PAGES50TO51             0x02000000U  /*!< Write protection of page 50 TO 51 */
+#define OB_WRP_PAGES52TO53             0x04000000U  /*!< Write protection of page 52 TO 53 */
+#define OB_WRP_PAGES54TO55             0x08000000U  /*!< Write protection of page 54 TO 55 */
+#define OB_WRP_PAGES56TO57             0x10000000U  /*!< Write protection of page 56 TO 57 */
+#define OB_WRP_PAGES58TO59             0x20000000U  /*!< Write protection of page 58 TO 59 */
+#define OB_WRP_PAGES60TO61             0x40000000U  /*!< Write protection of page 60 TO 61 */
+#define OB_WRP_PAGES62TO127            0x80000000U   /*!< Write protection of page 62 TO 127 */
+#define OB_WRP_PAGES62TO255            0x80000000U   /*!< Write protection of page 62 TO 255 */
+#define OB_WRP_PAGES62TO511            0x80000000U   /*!< Write protection of page 62 TO 511 */
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
+       /* STM32F101xG || STM32F103xG */ 
+       /* STM32F105xC || STM32F107xC */
+
+#define OB_WRP_ALLPAGES                0xFFFFFFFFU  /*!< Write protection of all Pages */
+ 
+/* Low Density */
+#if  defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)
+#define OB_WRP_PAGES0TO31MASK          0x000000FFU 
+#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
+
+/* Medium Density */
+#if  defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
+#define OB_WRP_PAGES0TO31MASK          0x000000FFU
+#define OB_WRP_PAGES32TO63MASK         0x0000FF00U
+#define OB_WRP_PAGES64TO95MASK         0x00FF0000U
+#define OB_WRP_PAGES96TO127MASK        0xFF000000U
+#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
+       
+/* High Density */
+#if  defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)  
+#define OB_WRP_PAGES0TO15MASK          0x000000FFU
+#define OB_WRP_PAGES16TO31MASK         0x0000FF00U
+#define OB_WRP_PAGES32TO47MASK         0x00FF0000U
+#define OB_WRP_PAGES48TO255MASK        0xFF000000U
+#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
+
+/* XL Density */
+#if  defined(STM32F101xG) || defined(STM32F103xG) 
+#define OB_WRP_PAGES0TO15MASK          0x000000FFU
+#define OB_WRP_PAGES16TO31MASK         0x0000FF00U
+#define OB_WRP_PAGES32TO47MASK         0x00FF0000U
+#define OB_WRP_PAGES48TO511MASK        0xFF000000U
+#endif /* STM32F101xG || STM32F103xG */
+      
+/* Connectivity line devices */
+#if defined(STM32F105xC) || defined(STM32F107xC)
+#define OB_WRP_PAGES0TO15MASK          0x000000FFU
+#define OB_WRP_PAGES16TO31MASK         0x0000FF00U
+#define OB_WRP_PAGES32TO47MASK         0x00FF0000U
+#define OB_WRP_PAGES48TO127MASK        0xFF000000U
+#endif /* STM32F105xC || STM32F107xC */
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
+  * @{
+  */
+#define OB_RDP_LEVEL_0            ((uint8_t)0xA5)
+#define OB_RDP_LEVEL_1            ((uint8_t)0x00)
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
+  * @{
+  */ 
+#define OB_IWDG_SW                ((uint16_t)0x0001)  /*!< Software IWDG selected */
+#define OB_IWDG_HW                ((uint16_t)0x0000)  /*!< Hardware IWDG selected */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
+  * @{
+  */ 
+#define OB_STOP_NO_RST            ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST               ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
+  * @{
+  */ 
+#define OB_STDBY_NO_RST           ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST              ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
+/**
+  * @}
+  */
+
+#if defined(FLASH_BANK2_END)
+/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
+  * @{
+  */
+#define OB_BOOT1_RESET            ((uint16_t)0x0000) /*!< BOOT1 Reset */
+#define OB_BOOT1_SET              ((uint16_t)0x0008) /*!< BOOT1 Set */
+/**
+  * @}
+  */
+#endif /* FLASH_BANK2_END */
+
+/** @defgroup FLASHEx_OB_Data_Address  Option Byte Data Address
+  * @{
+  */
+#define OB_DATA_ADDRESS_DATA0     0x1FFFF804U
+#define OB_DATA_ADDRESS_DATA1     0x1FFFF806U
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup FLASHEx_Constants
+  * @{
+  */ 
+
+/** @defgroup FLASH_Flag_definition Flag definition
+  * @brief Flag definition
+  * @{
+  */
+#if defined(FLASH_BANK2_END)
+ #define FLASH_FLAG_BSY             FLASH_FLAG_BSY_BANK1       /*!< FLASH Bank1 Busy flag                   */ 
+ #define FLASH_FLAG_PGERR           FLASH_FLAG_PGERR_BANK1     /*!< FLASH Bank1 Programming error flag      */
+ #define FLASH_FLAG_WRPERR          FLASH_FLAG_WRPERR_BANK1    /*!< FLASH Bank1 Write protected error flag  */
+ #define FLASH_FLAG_EOP             FLASH_FLAG_EOP_BANK1       /*!< FLASH Bank1 End of Operation flag       */
+
+ #define FLASH_FLAG_BSY_BANK1       FLASH_SR_BSY               /*!< FLASH Bank1 Busy flag                   */ 
+ #define FLASH_FLAG_PGERR_BANK1     FLASH_SR_PGERR             /*!< FLASH Bank1 Programming error flag      */
+ #define FLASH_FLAG_WRPERR_BANK1    FLASH_SR_WRPRTERR          /*!< FLASH Bank1 Write protected error flag  */
+ #define FLASH_FLAG_EOP_BANK1       FLASH_SR_EOP               /*!< FLASH Bank1 End of Operation flag       */
+       
+ #define FLASH_FLAG_BSY_BANK2       (FLASH_SR2_BSY << 16U)      /*!< FLASH Bank2 Busy flag                   */ 
+ #define FLASH_FLAG_PGERR_BANK2     (FLASH_SR2_PGERR << 16U)    /*!< FLASH Bank2 Programming error flag      */
+ #define FLASH_FLAG_WRPERR_BANK2    (FLASH_SR2_WRPRTERR << 16U) /*!< FLASH Bank2 Write protected error flag  */
+ #define FLASH_FLAG_EOP_BANK2       (FLASH_SR2_EOP << 16U)      /*!< FLASH Bank2 End of Operation flag       */
+
+#else  
+
+ #define FLASH_FLAG_BSY             FLASH_SR_BSY              /*!< FLASH Busy flag                          */ 
+ #define FLASH_FLAG_PGERR           FLASH_SR_PGERR            /*!< FLASH Programming error flag             */
+ #define FLASH_FLAG_WRPERR          FLASH_SR_WRPRTERR         /*!< FLASH Write protected error flag         */
+ #define FLASH_FLAG_EOP             FLASH_SR_EOP              /*!< FLASH End of Operation flag              */
+
+#endif
+ #define FLASH_FLAG_OPTVERR         ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR)) /*!< Option Byte Error        */
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Interrupt_definition Interrupt definition
+  * @brief FLASH Interrupt definition
+  * @{
+  */
+#if defined(FLASH_BANK2_END)
+ #define FLASH_IT_EOP               FLASH_IT_EOP_BANK1        /*!< End of FLASH Operation Interrupt source Bank1 */
+ #define FLASH_IT_ERR               FLASH_IT_ERR_BANK1        /*!< Error Interrupt source Bank1                  */
+
+ #define FLASH_IT_EOP_BANK1         FLASH_CR_EOPIE            /*!< End of FLASH Operation Interrupt source Bank1 */
+ #define FLASH_IT_ERR_BANK1         FLASH_CR_ERRIE            /*!< Error Interrupt source Bank1                  */
+
+ #define FLASH_IT_EOP_BANK2         (FLASH_CR2_EOPIE << 16U)   /*!< End of FLASH Operation Interrupt source Bank2 */
+ #define FLASH_IT_ERR_BANK2         (FLASH_CR2_ERRIE << 16U)   /*!< Error Interrupt source Bank2                  */
+
+#else
+
+ #define FLASH_IT_EOP               FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */
+ #define FLASH_IT_ERR               FLASH_CR_ERRIE          /*!< Error Interrupt source                  */
+
+#endif
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */
+  
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
+  * @{
+  */
+
+/** @defgroup FLASH_Interrupt Interrupt
+ *  @brief macros to handle FLASH interrupts
+ * @{
+ */ 
+
+#if defined(FLASH_BANK2_END)
+/**
+  * @brief  Enable the specified FLASH interrupt.
+  * @param  __INTERRUPT__  FLASH interrupt 
+  *     This parameter can be any combination of the following values:
+  *     @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
+  *     @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
+  *     @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
+  *     @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
+  * @retval none
+  */ 
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  do { \
+                          /* Enable Bank1 IT */ \
+                          SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
+                          /* Enable Bank2 IT */ \
+                          SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
+                    } while(0U)
+
+/**
+  * @brief  Disable the specified FLASH interrupt.
+  * @param  __INTERRUPT__  FLASH interrupt 
+  *     This parameter can be any combination of the following values:
+  *     @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
+  *     @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
+  *     @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
+  *     @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
+  * @retval none
+  */ 
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  do { \
+                          /* Disable Bank1 IT */ \
+                          CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
+                          /* Disable Bank2 IT */ \
+                          CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
+                    } while(0U)
+
+/**
+  * @brief  Get the specified FLASH flag status. 
+  * @param  __FLAG__ specifies the FLASH flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref FLASH_FLAG_EOP_BANK1    FLASH End of Operation flag on bank1
+  *            @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
+  *            @arg @ref FLASH_FLAG_PGERR_BANK1  FLASH Programming error flag on bank1
+  *            @arg @ref FLASH_FLAG_BSY_BANK1    FLASH Busy flag on bank1
+  *            @arg @ref FLASH_FLAG_EOP_BANK2    FLASH End of Operation flag on bank2
+  *            @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
+  *            @arg @ref FLASH_FLAG_PGERR_BANK2  FLASH Programming error flag on bank2
+  *            @arg @ref FLASH_FLAG_BSY_BANK2    FLASH Busy flag on bank2
+  *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
+                                            (FLASH->OBR & FLASH_OBR_OPTERR) : \
+                                        ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \
+                                            (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \
+                                            (FLASH->SR2 & ((__FLAG__) >> 16U))))
+
+/**
+  * @brief  Clear the specified FLASH flag.
+  * @param  __FLAG__ specifies the FLASH flags to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref FLASH_FLAG_EOP_BANK1    FLASH End of Operation flag on bank1
+  *            @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
+  *            @arg @ref FLASH_FLAG_PGERR_BANK1  FLASH Programming error flag on bank1
+  *            @arg @ref FLASH_FLAG_BSY_BANK1    FLASH Busy flag on bank1
+  *            @arg @ref FLASH_FLAG_EOP_BANK2    FLASH End of Operation flag on bank2
+  *            @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
+  *            @arg @ref FLASH_FLAG_PGERR_BANK2  FLASH Programming error flag on bank2
+  *            @arg @ref FLASH_FLAG_BSY_BANK2    FLASH Busy flag on bank2
+  *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
+  * @retval none
+  */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)  do { \
+                          /* Clear FLASH_FLAG_OPTVERR flag */ \
+                          if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
+                          { \
+                            CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
+                          } \
+                          else { \
+                          /* Clear Flag in Bank1 */ \
+                          if (((__FLAG__) & SR_FLAG_MASK) != RESET) \
+                          { \
+                            FLASH->SR  = ((__FLAG__) & SR_FLAG_MASK); \
+                          } \
+                          /* Clear Flag in Bank2 */ \
+                          if (((__FLAG__) >> 16U) != RESET) \
+                          { \
+                            FLASH->SR2 = ((__FLAG__) >> 16U); \
+                          } \
+                          } \
+                    } while(0U)
+#else
+/**
+  * @brief  Enable the specified FLASH interrupt.
+  * @param  __INTERRUPT__  FLASH interrupt 
+  *         This parameter can be any combination of the following values:
+  *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
+  *     @arg @ref FLASH_IT_ERR Error Interrupt    
+  * @retval none
+  */ 
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified FLASH interrupt.
+  * @param  __INTERRUPT__  FLASH interrupt 
+  *         This parameter can be any combination of the following values:
+  *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
+  *     @arg @ref FLASH_IT_ERR Error Interrupt    
+  * @retval none
+  */ 
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)   (FLASH->CR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Get the specified FLASH flag status. 
+  * @param  __FLAG__ specifies the FLASH flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref FLASH_FLAG_EOP    FLASH End of Operation flag 
+  *            @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag 
+  *            @arg @ref FLASH_FLAG_PGERR  FLASH Programming error flag
+  *            @arg @ref FLASH_FLAG_BSY    FLASH Busy flag
+  *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define __HAL_FLASH_GET_FLAG(__FLAG__)  (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
+                                            (FLASH->OBR & FLASH_OBR_OPTERR) : \
+                                            (FLASH->SR & (__FLAG__)))
+/**
+  * @brief  Clear the specified FLASH flag.
+  * @param  __FLAG__ specifies the FLASH flags to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref FLASH_FLAG_EOP    FLASH End of Operation flag 
+  *            @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag 
+  *            @arg @ref FLASH_FLAG_PGERR  FLASH Programming error flag 
+  *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
+  * @retval none
+  */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   do { \
+                          /* Clear FLASH_FLAG_OPTVERR flag */ \
+                          if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
+                          { \
+                            CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
+                          } \
+                          else { \
+                            /* Clear Flag in Bank1 */ \
+                            FLASH->SR  = (__FLAG__); \
+                          } \
+                    } while(0U)
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+  * @{
+  */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef  HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
+HAL_StatusTypeDef  HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+
+/**
+  * @}
+  */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef  HAL_FLASHEx_OBErase(void);
+HAL_StatusTypeDef  HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void               HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+uint32_t           HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/STM32F1xx_HAL/inc/stm32f1xx_hal_gpio.h

@@ -0,0 +1,308 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F1xx_HAL_GPIO_H
+#define STM32F1xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+  * @{
+  */
+
+/**
+  * @brief GPIO Init structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
+                           This parameter can be any value of @ref GPIO_pins_define */
+
+  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref GPIO_mode_define */
+
+  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                           This parameter can be a value of @ref GPIO_pull_define */
+
+  uint32_t Speed;     /*!< Specifies the speed for the selected pins.
+                           This parameter can be a value of @ref GPIO_speed_define */
+} GPIO_InitTypeDef;
+
+/**
+  * @brief  GPIO Bit SET and Bit RESET enumeration
+  */
+typedef enum
+{
+  GPIO_PIN_RESET = 0u,
+  GPIO_PIN_SET
+} GPIO_PinState;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_pins_define GPIO pins define
+  * @{
+  */
+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
+#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
+
+#define GPIO_PIN_MASK              0x0000FFFFu /* PIN mask for assert test */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_mode_define GPIO mode define
+  * @brief GPIO Configuration Mode
+  *        Elements values convention: 0xX0yz00YZ
+  *           - X  : GPIO mode or EXTI Mode
+  *           - y  : External IT or Event trigger detection
+  *           - z  : IO configuration on External IT or Event
+  *           - Y  : Output type (Push Pull or Open Drain)
+  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
+  * @{
+  */
+#define  GPIO_MODE_INPUT                        0x00000000u   /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                    0x00000001u   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                    0x00000011u   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                        0x00000002u   /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                        0x00000012u   /*!< Alternate Function Open Drain Mode    */
+#define  GPIO_MODE_AF_INPUT                     GPIO_MODE_INPUT          /*!< Alternate Function Input Mode         */
+
+#define  GPIO_MODE_ANALOG                       0x00000003u   /*!< Analog Mode  */
+
+#define  GPIO_MODE_IT_RISING                    0x10110000u   /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING                   0x10210000u   /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING            0x10310000u   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+
+#define  GPIO_MODE_EVT_RISING                   0x10120000u   /*!< External Event Mode with Rising edge trigger detection               */
+#define  GPIO_MODE_EVT_FALLING                  0x10220000u   /*!< External Event Mode with Falling edge trigger detection              */
+#define  GPIO_MODE_EVT_RISING_FALLING           0x10320000u   /*!< External Event Mode with Rising/Falling edge trigger detection       */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_speed_define  GPIO speed define
+  * @brief GPIO Output Maximum frequency
+  * @{
+  */
+#define  GPIO_SPEED_FREQ_LOW              (GPIO_CRL_MODE0_1) /*!< Low speed */
+#define  GPIO_SPEED_FREQ_MEDIUM           (GPIO_CRL_MODE0_0) /*!< Medium speed */
+#define  GPIO_SPEED_FREQ_HIGH             (GPIO_CRL_MODE0)   /*!< High speed */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_pull_define GPIO pull define
+  * @brief GPIO Pull-Up or Pull-Down Activation
+  * @{
+  */
+#define  GPIO_NOPULL        0x00000000u   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        0x00000001u   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      0x00000002u   /*!< Pull-down activation                */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
+/**
+  * @}
+  */
+
+/* Include GPIO HAL Extension module */
+#include "stm32f1xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
+/**
+  * @}
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+  * @{
+  */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+#define IS_GPIO_PIN(PIN)           (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00u) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00u))
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
+                            ((MODE) == GPIO_MODE_AF_PP)              ||\
+                            ((MODE) == GPIO_MODE_AF_OD)              ||\
+                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
+                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
+                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
+                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+                            ((MODE) == GPIO_MODE_ANALOG))
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \
+                              ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+                            ((PULL) == GPIO_PULLDOWN))
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Functions GPIO Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F1xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/STM32F1xx_HAL/inc/stm32f1xx_hal_gpio_ex.h

@@ -0,0 +1,894 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_gpio_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F1xx_HAL_GPIO_EX_H
+#define STM32F1xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIOEx GPIOEx
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
+  * @brief This section propose definition to use the Cortex EVENTOUT signal.
+  * @{
+  */
+
+/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin
+  * @{
+  */
+
+#define AFIO_EVENTOUT_PIN_0  AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
+#define AFIO_EVENTOUT_PIN_1  AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
+#define AFIO_EVENTOUT_PIN_2  AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
+#define AFIO_EVENTOUT_PIN_3  AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
+#define AFIO_EVENTOUT_PIN_4  AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
+#define AFIO_EVENTOUT_PIN_5  AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
+#define AFIO_EVENTOUT_PIN_6  AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
+#define AFIO_EVENTOUT_PIN_7  AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
+#define AFIO_EVENTOUT_PIN_8  AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
+#define AFIO_EVENTOUT_PIN_9  AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
+#define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
+#define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
+#define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
+#define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
+#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
+#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
+
+#define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \
+                                       ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \
+                                       ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \
+                                       ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \
+                                       ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \
+                                       ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
+                                       ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
+                                       ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
+                                       ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
+                                       ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
+                                       ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
+                                       ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
+                                       ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
+                                       ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
+                                       ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
+                                       ((__PIN__) == AFIO_EVENTOUT_PIN_15))
+/**
+  * @}
+  */
+
+/** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
+  * @{
+  */
+
+#define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
+#define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
+#define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
+#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
+#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
+
+#define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \
+                                         ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \
+                                         ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
+                                         ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
+                                         ((__PORT__) == AFIO_EVENTOUT_PORT_E))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
+  * @brief This section propose definition to remap the alternate function to some other port/pins.
+  * @{
+  */
+
+/**
+  * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
+  * @note  ENABLE: Remap     (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_SPI1_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP)
+
+/**
+  * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
+  * @note  DISABLE: No remap (NSS/PA4,  SCK/PA5, MISO/PA6, MOSI/PA7)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_SPI1_DISABLE()  AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP)
+
+/**
+  * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
+  * @note  ENABLE: Remap     (SCL/PB8, SDA/PB9)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_I2C1_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP)
+
+/**
+  * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
+  * @note  DISABLE: No remap (SCL/PB6, SDA/PB7)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP)
+
+/**
+  * @brief Enable the remapping of USART1 alternate function TX and RX.
+  * @note  ENABLE: Remap     (TX/PB6, RX/PB7)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_USART1_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP)
+
+/**
+  * @brief Disable the remapping of USART1 alternate function TX and RX.
+  * @note  DISABLE: No remap (TX/PA9, RX/PA10)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP)
+
+/**
+  * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
+  * @note  ENABLE: Remap     (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_USART2_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP)
+
+/**
+  * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
+  * @note  DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP)
+
+/**
+  * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+  * @note  ENABLE: Full remap     (TX/PD8,  RX/PD9,  CK/PD10, CTS/PD11, RTS/PD12)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_USART3_ENABLE()  AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
+
+/**
+  * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+  * @note  PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_USART3_PARTIAL()  AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
+
+/**
+  * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+  * @note  DISABLE: No remap      (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_USART3_DISABLE()  AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
+
+/**
+  * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+  * @note  ENABLE: Full remap     (ETR/PE7,  CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8,  CH2N/PE10, CH3N/PE12)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM1_ENABLE()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
+
+/**
+  * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+  * @note  PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PA6,  CH1N/PA7,  CH2N/PB0,  CH3N/PB1)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM1_PARTIAL()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
+
+/**
+  * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+  * @note  DISABLE: No remap      (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM1_DISABLE()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
+
+/**
+  * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+  * @note  ENABLE: Full remap       (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM2_ENABLE()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
+
+/**
+  * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+  * @note  PARTIAL_2: Partial remap (CH1/ETR/PA0,  CH2/PA1, CH3/PB10, CH4/PB11)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
+
+/**
+  * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+  * @note  PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2,  CH4/PA3)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
+
+/**
+  * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+  * @note  DISABLE: No remap        (CH1/ETR/PA0,  CH2/PA1, CH3/PA2,  CH4/PA3)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM2_DISABLE()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
+
+/**
+  * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
+  * @note  ENABLE: Full remap     (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
+  * @note  TIM3_ETR on PE0 is not re-mapped.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM3_ENABLE()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
+
+/**
+  * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
+  * @note  PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
+  * @note  TIM3_ETR on PE0 is not re-mapped.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM3_PARTIAL()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
+
+/**
+  * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
+  * @note  DISABLE: No remap      (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
+  * @note  TIM3_ETR on PE0 is not re-mapped.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM3_DISABLE()  AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
+
+/**
+  * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
+  * @note  ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
+  * @note  TIM4_ETR on PE0 is not re-mapped.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM4_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP)
+
+/**
+  * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
+  * @note  DISABLE: No remap  (TIM4_CH1/PB6,  TIM4_CH2/PB7,  TIM4_CH3/PB8,  TIM4_CH4/PB9)
+  * @note  TIM4_ETR on PE0 is not re-mapped.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP)
+
+#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
+
+/**
+  * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+  * @note  CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_CAN1_1()  AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP)
+
+/**
+  * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+  * @note  CASE 2: CAN_RX mapped to PB8,  CAN_TX mapped to PB9 (not available on 36-pin package)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_CAN1_2()  AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP)
+
+/**
+  * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+  * @note  CASE 3: CAN_RX mapped to PD0,  CAN_TX mapped to PD1
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_CAN1_3()  AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP)
+
+#endif
+
+/**
+  * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
+  *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
+  *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
+  *        on 100-pin and 144-pin packages, no need for remapping).
+  * @note  ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_PD01_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP)
+
+/**
+  * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
+  *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
+  *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
+  *        on 100-pin and 144-pin packages, no need for remapping).
+  * @note  DISABLE: No remapping of PD0 and PD1
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP)
+
+#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
+/**
+  * @brief Enable the remapping of TIM5CH4.
+  * @note  ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
+  * @note  This function is available only in high density value line devices.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM5CH4_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP)
+
+/**
+  * @brief Disable the remapping of TIM5CH4.
+  * @note  DISABLE: TIM5_CH4 is connected to PA3
+  * @note  This function is available only in high density value line devices.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP)
+#endif
+
+#if defined(AFIO_MAPR_ETH_REMAP)
+/**
+  * @brief Enable the remapping of Ethernet MAC connections with the PHY.
+  * @note  ENABLE: Remap     (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
+  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_ETH_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP)
+
+/**
+  * @brief Disable the remapping of Ethernet MAC connections with the PHY.
+  * @note  DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5,  RXD2/PB0,  RXD3/PB1)
+  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP)
+#endif
+
+#if defined(AFIO_MAPR_CAN2_REMAP)
+
+/**
+  * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
+  * @note  ENABLE: Remap     (CAN2_RX/PB5,  CAN2_TX/PB6)
+  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_CAN2_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP)
+
+/**
+  * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
+  * @note  DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
+  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP)
+#endif
+
+#if defined(AFIO_MAPR_MII_RMII_SEL)
+/**
+  * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
+  * @note  ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
+  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+  * @retval None
+  */
+#define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL)
+
+/**
+  * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
+  * @note  ETH_MII: Configure Ethernet MAC for connection with an MII PHY
+  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+  * @retval None
+  */
+#define __HAL_AFIO_ETH_MII()  AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL)
+#endif
+
+/**
+  * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
+  * @note  ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
+
+/**
+  * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
+  * @note  DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
+
+/**
+  * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
+  * @note  ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
+
+/**
+  * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
+  * @note  DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
+
+#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
+
+/**
+  * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
+  * @note  ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
+
+/**
+  * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
+  * @note  DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
+#endif
+
+#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
+
+/**
+  * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+  * @note  ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
+
+/**
+  * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+  * @note  DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
+#endif
+
+/**
+  * @brief Enable the Serial wire JTAG configuration
+  * @note  ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_SWJ_ENABLE()  AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET)
+
+/**
+  * @brief Enable the Serial wire JTAG configuration
+  * @note  NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_SWJ_NONJTRST()  AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST)
+
+/**
+  * @brief Enable the Serial wire JTAG configuration
+  * @note  NOJTAG: JTAG-DP Disabled and SW-DP Enabled
+  * @retval None
+  */
+
+#define __HAL_AFIO_REMAP_SWJ_NOJTAG()  AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE)
+
+/**
+  * @brief Disable the Serial wire JTAG configuration
+  * @note  DISABLE: JTAG-DP Disabled and SW-DP Disabled
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_SWJ_DISABLE()  AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE)
+
+#if defined(AFIO_MAPR_SPI3_REMAP)
+
+/**
+  * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
+  * @note  ENABLE: Remap     (SPI3_NSS-I2S3_WS/PA4,  SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
+  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_SPI3_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP)
+
+/**
+  * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
+  * @note  DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3,  SPI3_MISO/PB4,  SPI3_MOSI-I2S3_SD/PB5).
+  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP)
+#endif
+
+#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
+
+/**
+  * @brief Control of TIM2_ITR1 internal mapping.
+  * @note  TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
+  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+  * @retval None
+  */
+#define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
+
+/**
+  * @brief Control of TIM2_ITR1 internal mapping.
+  * @note  TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
+  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+  * @retval None
+  */
+#define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
+#endif
+
+#if defined(AFIO_MAPR_PTP_PPS_REMAP)
+
+/**
+  * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+  * @note  ENABLE: PTP_PPS is output on PB5 pin.
+  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+  * @retval None
+  */
+#define __HAL_AFIO_ETH_PTP_PPS_ENABLE()  AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP)
+
+/**
+  * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+  * @note  DISABLE: PTP_PPS not output on PB5 pin.
+  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
+  * @retval None
+  */
+#define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM9_REMAP)
+
+/**
+  * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
+  * @note  ENABLE: Remap     (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM9_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
+
+/**
+  * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
+  * @note  DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM10_REMAP)
+
+/**
+  * @brief Enable the remapping of TIM10_CH1.
+  * @note  ENABLE: Remap     (TIM10_CH1 on PF6).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM10_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
+
+/**
+  * @brief Disable the remapping of TIM10_CH1.
+  * @note  DISABLE: No remap (TIM10_CH1 on PB8).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM11_REMAP)
+/**
+  * @brief Enable the remapping of TIM11_CH1.
+  * @note  ENABLE: Remap     (TIM11_CH1 on PF7).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM11_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
+
+/**
+  * @brief Disable the remapping of TIM11_CH1.
+  * @note  DISABLE: No remap (TIM11_CH1 on PB9).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM13_REMAP)
+
+/**
+  * @brief Enable the remapping of TIM13_CH1.
+  * @note  ENABLE: Remap     STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM13_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
+
+/**
+  * @brief Disable the remapping of TIM13_CH1.
+  * @note  DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM14_REMAP)
+
+/**
+  * @brief Enable the remapping of TIM14_CH1.
+  * @note  ENABLE: Remap     STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM14_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
+
+/**
+  * @brief Disable the remapping of TIM14_CH1.
+  * @note  DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
+
+/**
+  * @brief Controls the use of the optional FSMC_NADV signal.
+  * @note  DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
+  * @retval None
+  */
+#define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
+
+/**
+  * @brief Controls the use of the optional FSMC_NADV signal.
+  * @note  CONNECTED: The NADV signal is connected to the output (default).
+  * @retval None
+  */
+#define __HAL_AFIO_FSMCNADV_CONNECTED()    CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM15_REMAP)
+
+/**
+  * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
+  * @note  ENABLE: Remap     (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM15_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
+
+/**
+  * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
+  * @note  DISABLE: No remap (TIM15_CH1 on PA2  and TIM15_CH2 on PA3).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM16_REMAP)
+
+/**
+  * @brief Enable the remapping of TIM16_CH1.
+  * @note  ENABLE: Remap     (TIM16_CH1 on PA6).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM16_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
+
+/**
+  * @brief Disable the remapping of TIM16_CH1.
+  * @note  DISABLE: No remap (TIM16_CH1 on PB8).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM17_REMAP)
+
+/**
+  * @brief Enable the remapping of TIM17_CH1.
+  * @note  ENABLE: Remap     (TIM17_CH1 on PA7).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM17_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
+
+/**
+  * @brief Disable the remapping of TIM17_CH1.
+  * @note  DISABLE: No remap (TIM17_CH1 on PB9).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_CEC_REMAP)
+
+/**
+  * @brief Enable the remapping of CEC.
+  * @note  ENABLE: Remap     (CEC on PB10).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_CEC_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
+
+/**
+  * @brief Disable the remapping of CEC.
+  * @note  DISABLE: No remap (CEC on PB8).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
+
+/**
+  * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
+  * @note  ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM1DMA_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
+
+/**
+  * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
+  * @note  DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
+
+/**
+  * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
+  * @note  ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
+
+/**
+  * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
+  * @note  DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_TIM12_REMAP)
+
+/**
+  * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
+  * @note  ENABLE: Remap     (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
+  * @note  This bit is available only in high density value line devices.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM12_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
+
+/**
+  * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
+  * @note  DISABLE: No remap (TIM12_CH1 on PC4  and TIM12_CH2 on PC5).
+  * @note  This bit is available only in high density value line devices.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
+#endif
+
+#if defined(AFIO_MAPR2_MISC_REMAP)
+
+/**
+  * @brief Miscellaneous features remapping.
+  *        This bit is set and cleared by software. It controls miscellaneous features.
+  *        The DMA2 channel 5 interrupt position in the vector table.
+  *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
+  * @note  ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
+  *        selected as DAC Trigger 3, TIM15 triggers TIM1/3.
+  * @note  This bit is available only in high density value line devices.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_MISC_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
+
+/**
+  * @brief Miscellaneous features remapping.
+  *        This bit is set and cleared by software. It controls miscellaneous features.
+  *        The DMA2 channel 5 interrupt position in the vector table.
+  *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
+  * @note  DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
+  *        event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
+  * @note  This bit is available only in high density value line devices.
+  * @retval None
+  */
+#define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
+  * @{
+  */
+#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
+                                   ((__GPIOx__) == (GPIOB))? 1uL :\
+                                   ((__GPIOx__) == (GPIOC))? 2uL :3uL)
+#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
+                                   ((__GPIOx__) == (GPIOB))? 1uL :\
+                                   ((__GPIOx__) == (GPIOC))? 2uL :\
+                                   ((__GPIOx__) == (GPIOD))? 3uL :4uL)
+#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
+                                   ((__GPIOx__) == (GPIOB))? 1uL :\
+                                   ((__GPIOx__) == (GPIOC))? 2uL :\
+                                   ((__GPIOx__) == (GPIOD))? 3uL :\
+                                   ((__GPIOx__) == (GPIOE))? 4uL :\
+                                   ((__GPIOx__) == (GPIOF))? 5uL :6uL)
+#endif
+
+#define AFIO_REMAP_ENABLE(REMAP_PIN)       do{ uint32_t tmpreg = AFIO->MAPR; \
+                                               tmpreg |= AFIO_MAPR_SWJ_CFG;  \
+                                               tmpreg |= REMAP_PIN;          \
+                                               AFIO->MAPR = tmpreg;          \
+                                               }while(0u)
+
+#define AFIO_REMAP_DISABLE(REMAP_PIN)      do{ uint32_t tmpreg = AFIO->MAPR;  \
+                                               tmpreg |= AFIO_MAPR_SWJ_CFG;   \
+                                               tmpreg &= ~REMAP_PIN;          \
+                                               AFIO->MAPR = tmpreg;           \
+                                               }while(0u)
+
+#define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \
+                                                          tmpreg &= ~REMAP_PIN_MASK;    \
+                                                          tmpreg |= AFIO_MAPR_SWJ_CFG;  \
+                                                          tmpreg |= REMAP_PIN;          \
+                                                          AFIO->MAPR = tmpreg;          \
+                                                          }while(0u)
+
+#define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG)  do{ uint32_t tmpreg = AFIO->MAPR;     \
+                                               tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \
+                                               tmpreg |= DBGAFR_SWJCFG;          \
+                                               AFIO->MAPR = tmpreg;              \
+                                               }while(0u)
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup GPIOEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIOEx_Exported_Functions_Group1
+  * @{
+  */
+void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource);
+void HAL_GPIOEx_EnableEventout(void);
+void HAL_GPIOEx_DisableEventout(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F1xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/STM32F1xx_HAL/inc/stm32f1xx_hal_i2c.h

@@ -0,0 +1,735 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_i2c.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_I2C_H
+#define __STM32F1xx_HAL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+  * @{
+  */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+  * @brief  I2C Configuration Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t ClockSpeed;       /*!< Specifies the clock frequency.
+                                  This parameter must be set to a value lower than 400kHz */
+
+  uint32_t DutyCycle;        /*!< Specifies the I2C fast mode duty cycle.
+                                  This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+  uint32_t OwnAddress1;      /*!< Specifies the first device own address.
+                                  This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode;   /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_addressing_mode */
+
+  uint32_t DualAddressMode;  /*!< Specifies if dual addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_dual_addressing_mode */
+
+  uint32_t OwnAddress2;      /*!< Specifies the second device own address if dual addressing mode is selected
+                                  This parameter can be a 7-bit address. */
+
+  uint32_t GeneralCallMode;  /*!< Specifies if general call mode is selected.
+                                  This parameter can be a value of @ref I2C_general_call_addressing_mode */
+
+  uint32_t NoStretchMode;    /*!< Specifies if nostretch mode is selected.
+                                  This parameter can be a value of @ref I2C_nostretch_mode */
+
+} I2C_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+  * @brief  HAL State structure definition
+  * @note  HAL I2C State value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : Abort (Abort user request on going)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     Peripheral initilisation status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized and ready to use. HAL I2C Init function called)
+  *          b4     (not used)
+  *             x  : Should be set to 0
+  *          b3
+  *             0  : Ready or Busy (No Listen mode ongoing)
+  *             1  : Listen (Peripheral in Address Listen Mode)
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (Peripheral busy with some configuration or internal operations)
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
+  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
+  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
+  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
+  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
+  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
+  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
+  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
+  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
+
+} HAL_I2C_StateTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+  * @brief  HAL Mode structure definition
+  * @note  HAL I2C Mode value coding follow below described bitmap :\n
+  *          b7     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b6\n
+  *             0  : None\n
+  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
+  *          b5\n
+  *             0  : None\n
+  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
+  *          b4\n
+  *             0  : None\n
+  *             1  : Master (HAL I2C communication is in Master Mode)\n
+  *          b3-b2-b1-b0  (not used)\n
+  *             xxxx : Should be set to 0000
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
+  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
+  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
+  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
+
+} HAL_I2C_ModeTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+  * @brief  I2C Error Code definition
+  * @{
+  */
+#define HAL_I2C_ERROR_NONE              0x00000000U    /*!< No error              */
+#define HAL_I2C_ERROR_BERR              0x00000001U    /*!< BERR error            */
+#define HAL_I2C_ERROR_ARLO              0x00000002U    /*!< ARLO error            */
+#define HAL_I2C_ERROR_AF                0x00000004U    /*!< AF error              */
+#define HAL_I2C_ERROR_OVR               0x00000008U    /*!< OVR error             */
+#define HAL_I2C_ERROR_DMA               0x00000010U    /*!< DMA transfer error    */
+#define HAL_I2C_ERROR_TIMEOUT           0x00000020U    /*!< Timeout Error         */
+#define HAL_I2C_ERROR_SIZE              0x00000040U    /*!< Size Management error */
+#define HAL_I2C_ERROR_DMA_PARAM         0x00000080U    /*!< DMA Parameter Error   */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define HAL_I2C_ERROR_INVALID_CALLBACK  0x00000100U    /*!< Invalid Callback error */
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+  * @brief  I2C handle Structure definition
+  * @{
+  */
+typedef struct __I2C_HandleTypeDef
+{
+  I2C_TypeDef                *Instance;      /*!< I2C registers base address               */
+
+  I2C_InitTypeDef            Init;           /*!< I2C communication parameters             */
+
+  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer           */
+
+  uint16_t                   XferSize;       /*!< I2C transfer size                        */
+
+  __IO uint16_t              XferCount;      /*!< I2C transfer counter                     */
+
+  __IO uint32_t              XferOptions;    /*!< I2C transfer options                     */
+
+  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state and mode
+                                                  context for internal usage               */
+
+  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters             */
+
+  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters             */
+
+  HAL_LockTypeDef            Lock;           /*!< I2C locking object                       */
+
+  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                  */
+
+  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                   */
+
+  __IO uint32_t              ErrorCode;      /*!< I2C Error code                           */
+
+  __IO uint32_t              Devaddress;     /*!< I2C Target device address                */
+
+  __IO uint32_t              Memaddress;     /*!< I2C Target memory address                */
+
+  __IO uint32_t              MemaddSize;     /*!< I2C Target memory address  size          */
+
+  __IO uint32_t              EventCount;     /*!< I2C Event counter                        */
+
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Tx Transfer completed callback */
+  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Rx Transfer completed callback */
+  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Tx Transfer completed callback  */
+  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Rx Transfer completed callback  */
+  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);             /*!< I2C Listen Complete callback              */
+  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Tx Transfer completed callback */
+  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Rx Transfer completed callback */
+  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);                  /*!< I2C Error callback                        */
+  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Abort callback                        */
+
+  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< I2C Slave Address Match callback */
+
+  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);                /*!< I2C Msp Init callback                     */
+  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Msp DeInit callback                   */
+
+#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
+} I2C_HandleTypeDef;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL I2C Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
+  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
+  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
+  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
+  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
+  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
+  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
+  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
+  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
+
+  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
+  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
+
+} HAL_I2C_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL I2C Callback pointer definition
+  */
+typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
+typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
+  * @{
+  */
+#define I2C_DUTYCYCLE_2                 0x00000000U
+#define I2C_DUTYCYCLE_16_9              I2C_CCR_DUTY
+/**
+  * @}
+  */
+
+/** @defgroup I2C_addressing_mode I2C addressing mode
+  * @{
+  */
+#define I2C_ADDRESSINGMODE_7BIT         0x00004000U
+#define I2C_ADDRESSINGMODE_10BIT        (I2C_OAR1_ADDMODE | 0x00004000U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_dual_addressing_mode  I2C dual addressing mode
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLE        0x00000000U
+#define I2C_DUALADDRESS_ENABLE         I2C_OAR2_ENDUAL
+/**
+  * @}
+  */
+
+/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
+  * @{
+  */
+#define I2C_GENERALCALL_DISABLE        0x00000000U
+#define I2C_GENERALCALL_ENABLE         I2C_CR1_ENGC
+/**
+  * @}
+  */
+
+/** @defgroup I2C_nostretch_mode I2C nostretch mode
+  * @{
+  */
+#define I2C_NOSTRETCH_DISABLE          0x00000000U
+#define I2C_NOSTRETCH_ENABLE           I2C_CR1_NOSTRETCH
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
+  * @{
+  */
+#define I2C_MEMADD_SIZE_8BIT            0x00000001U
+#define I2C_MEMADD_SIZE_16BIT           0x00000010U
+/**
+  * @}
+  */
+
+/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
+  * @{
+  */
+#define I2C_DIRECTION_RECEIVE           0x00000000U
+#define I2C_DIRECTION_TRANSMIT          0x00000001U
+/**
+  * @}
+  */
+
+/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
+  * @{
+  */
+#define  I2C_FIRST_FRAME                0x00000001U
+#define  I2C_FIRST_AND_NEXT_FRAME       0x00000002U
+#define  I2C_NEXT_FRAME                 0x00000004U
+#define  I2C_FIRST_AND_LAST_FRAME       0x00000008U
+#define  I2C_LAST_FRAME_NO_STOP         0x00000010U
+#define  I2C_LAST_FRAME                 0x00000020U
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define  I2C_OTHER_FRAME                (0x00AA0000U)
+#define  I2C_OTHER_AND_LAST_FRAME       (0xAA000000U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+  * @brief I2C Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define I2C_IT_BUF                      I2C_CR2_ITBUFEN
+#define I2C_IT_EVT                      I2C_CR2_ITEVTEN
+#define I2C_IT_ERR                      I2C_CR2_ITERREN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+  * @{
+  */
+
+#define I2C_FLAG_OVR                    0x00010800U
+#define I2C_FLAG_AF                     0x00010400U
+#define I2C_FLAG_ARLO                   0x00010200U
+#define I2C_FLAG_BERR                   0x00010100U
+#define I2C_FLAG_TXE                    0x00010080U
+#define I2C_FLAG_RXNE                   0x00010040U
+#define I2C_FLAG_STOPF                  0x00010010U
+#define I2C_FLAG_ADD10                  0x00010008U
+#define I2C_FLAG_BTF                    0x00010004U
+#define I2C_FLAG_ADDR                   0x00010002U
+#define I2C_FLAG_SB                     0x00010001U
+#define I2C_FLAG_DUALF                  0x00100080U
+#define I2C_FLAG_GENCALL                0x00100010U
+#define I2C_FLAG_TRA                    0x00100004U
+#define I2C_FLAG_BUSY                   0x00100002U
+#define I2C_FLAG_MSL                    0x00100001U
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @brief Reset I2C handle state.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \
+                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \
+                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                                  } while(0)
+#else
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#endif
+
+/** @brief  Enable or disable the specified I2C interrupts.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg I2C_IT_BUF: Buffer interrupt enable
+  *            @arg I2C_IT_EVT: Event interrupt enable
+  *            @arg I2C_IT_ERR: Error interrupt enable
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+
+/** @brief  Checks if the specified I2C interrupt source is enabled or disabled.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_IT_BUF: Buffer interrupt enable
+  *            @arg I2C_IT_EVT: Event interrupt enable
+  *            @arg I2C_IT_ERR: Error interrupt enable
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Checks whether the specified I2C flag is set or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag
+  *            @arg I2C_FLAG_AF: Acknowledge failure flag
+  *            @arg I2C_FLAG_ARLO: Arbitration lost flag
+  *            @arg I2C_FLAG_BERR: Bus error flag
+  *            @arg I2C_FLAG_TXE: Data register empty flag
+  *            @arg I2C_FLAG_RXNE: Data register not empty flag
+  *            @arg I2C_FLAG_STOPF: Stop detection flag
+  *            @arg I2C_FLAG_ADD10: 10-bit header sent flag
+  *            @arg I2C_FLAG_BTF: Byte transfer finished flag
+  *            @arg I2C_FLAG_ADDR: Address sent flag
+  *                                Address matched flag
+  *            @arg I2C_FLAG_SB: Start bit flag
+  *            @arg I2C_FLAG_DUALF: Dual flag
+  *            @arg I2C_FLAG_GENCALL: General call header flag
+  *            @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+  *            @arg I2C_FLAG_BUSY: Bus busy flag
+  *            @arg I2C_FLAG_MSL: Master/Slave flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? \
+                                                  (((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) : \
+                                                  (((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET))
+
+/** @brief  Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+  *            @arg I2C_FLAG_AF: Acknowledge failure flag
+  *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+  *            @arg I2C_FLAG_BERR: Bus error flag
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
+
+/** @brief  Clears the I2C ADDR pending flag.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__)    \
+  do{                                           \
+    __IO uint32_t tmpreg = 0x00U;               \
+    tmpreg = (__HANDLE__)->Instance->SR1;       \
+    tmpreg = (__HANDLE__)->Instance->SR2;       \
+    UNUSED(tmpreg);                             \
+  } while(0)
+
+/** @brief  Clears the I2C STOPF pending flag.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)           \
+  do{                                                  \
+    __IO uint32_t tmpreg = 0x00U;                      \
+    tmpreg = (__HANDLE__)->Instance->SR1;              \
+    SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE);  \
+    UNUSED(tmpreg);                                    \
+  } while(0)
+
+/** @brief  Enable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE(__HANDLE__)                  SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
+
+/** @brief  Disable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE(__HANDLE__)                 CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions******************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* IO operation functions  ****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+  * @{
+  */
+/* Peripheral State, Mode and Error functions  *********************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+  * @{
+  */
+#define I2C_FLAG_MASK                    0x0000FFFFU
+#define I2C_MIN_PCLK_FREQ_STANDARD       2000000U     /*!< 2 MHz                     */
+#define I2C_MIN_PCLK_FREQ_FAST           4000000U     /*!< 4 MHz                     */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macros I2C Private Macros
+  * @{
+  */
+
+#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__)             (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))
+#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__)     (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)
+#define I2C_FREQRANGE(__PCLK__)                            ((__PCLK__)/1000000U)
+#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__)            (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
+#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__)            ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
+#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
+#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)      (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
+                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
+                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
+
+#define I2C_7BIT_ADD_WRITE(__ADDRESS__)                    ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0)))
+#define I2C_7BIT_ADD_READ(__ADDRESS__)                     ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
+
+#define I2C_10BIT_ADDRESS(__ADDRESS__)                     ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
+#define I2C_10BIT_HEADER_WRITE(__ADDRESS__)                ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0)))
+#define I2C_10BIT_HEADER_READ(__ADDRESS__)                 ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1))))
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__)                       ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)                       ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
+
+/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
+  * @{
+  */
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
+                                  ((CYCLE) == I2C_DUTYCYCLE_16_9))
+#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
+                                         ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+                                      ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
+                                   ((CALL) == I2C_GENERALCALL_ENABLE))
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+                                    ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+                                  ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U))
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U)
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == I2C_FIRST_FRAME)              || \
+                                                       ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME)     || \
+                                                       ((REQUEST) == I2C_NEXT_FRAME)               || \
+                                                       ((REQUEST) == I2C_FIRST_AND_LAST_FRAME)     || \
+                                                       ((REQUEST) == I2C_LAST_FRAME)               || \
+                                                       ((REQUEST) == I2C_LAST_FRAME_NO_STOP)       || \
+                                                       IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
+                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
+
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F1xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Ubiquitous/XiUOS/board/stm32f103-nano/third_party_driver/libraries/STM32F1xx_HAL/inc/stm32f1xx_hal_pwr.h

@@ -0,0 +1,388 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_PWR_H
+#define __STM32F1xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal_def.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+  * @{
+  */ 
+
+/**
+  * @brief  PWR PVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
+                            This parameter can be a value of @ref PWR_PVD_detection_level */
+
+  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref PWR_PVD_Mode */
+}PWR_PVDTypeDef;
+
+
+/**
+  * @}
+  */
+
+
+/* Internal constants --------------------------------------------------------*/
+
+/** @addtogroup PWR_Private_Constants
+  * @{
+  */ 
+
+#define PWR_EXTI_LINE_PVD  ((uint32_t)0x00010000)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+
+/**
+  * @}
+  */
+
+ 
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+  * @{
+  */ 
+
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level
+  * @{
+  */
+#define PWR_PVDLEVEL_0                  PWR_CR_PLS_2V2
+#define PWR_PVDLEVEL_1                  PWR_CR_PLS_2V3
+#define PWR_PVDLEVEL_2                  PWR_CR_PLS_2V4
+#define PWR_PVDLEVEL_3                  PWR_CR_PLS_2V5
+#define PWR_PVDLEVEL_4                  PWR_CR_PLS_2V6
+#define PWR_PVDLEVEL_5                  PWR_CR_PLS_2V7
+#define PWR_PVDLEVEL_6                  PWR_CR_PLS_2V8
+#define PWR_PVDLEVEL_7                  PWR_CR_PLS_2V9 
+                                                          
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVD_Mode PWR PVD Mode
+  * @{
+  */
+#define PWR_PVD_MODE_NORMAL                 0x00000000U   /*!< basic mode is used */
+#define PWR_PVD_MODE_IT_RISING              0x00010001U   /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING             0x00010002U   /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING      0x00010003U   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING           0x00020001U   /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING          0x00020002U   /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING   0x00020003U   /*!< Event Mode with Rising/Falling edge trigger detection */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
+  * @{
+  */
+
+#define PWR_WAKEUP_PIN1                 PWR_CSR_EWUP
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
+  * @{
+  */
+#define PWR_MAINREGULATOR_ON                        0x00000000U
+#define PWR_LOWPOWERREGULATOR_ON                    PWR_CR_LPDS
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+  * @{
+  */
+#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)
+#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+  * @{
+  */
+#define PWR_STOPENTRY_WFI               ((uint8_t)0x01)
+#define PWR_STOPENTRY_WFE               ((uint8_t)0x02)
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag PWR Flag
+  * @{
+  */
+#define PWR_FLAG_WU                     PWR_CSR_WUF
+#define PWR_FLAG_SB                     PWR_CSR_SBF
+#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macros PWR Exported Macros
+  * @{
+  */
+
+/** @brief  Check PWR flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *           This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
+  *                  was received from the WKUP pin or from the RTC alarm
+  *                  An additional wakeup event is detected if the WKUP pin is enabled
+  *                  (by setting the EWUP bit) when the WKUP pin level is already high.
+  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+  *                  resumed from StandBy mode.
+  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
+  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
+  *                  For this reason, this bit is equal to 0 after Standby or reset
+  *                  until the PVDE bit is set.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the PWR's pending flags.
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WU: Wake Up flag
+  *            @arg PWR_FLAG_SB: StandBy flag
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
+
+/**
+  * @brief Enable interrupt on PVD Exti Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable interrupt on PVD Exti Line 16. 
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable event on PVD Exti Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable event on PVD Exti Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
+
+
+/**
+  * @brief  PVD EXTI line configuration: set falling edge trigger.  
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+
+/**
+  * @brief Disable the PVD Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+
+/**
+  * @brief  PVD EXTI line configuration: set rising edge trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Rising Trigger.
+  * This parameter can be:
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+  * This parameter can be:
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+
+
+
+/**
+  * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
+  * @retval EXTI PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG()       (EXTI->PR & (PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief Clear the PVD EXTI flag.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()     (EXTI->PR = (PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief Generate a Software interrupt on selected EXTI line.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup PWR_Private_Macros PWR Private Macros
+  * @{
+  */
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+
+
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
+                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
+                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
+                              ((MODE) == PWR_PVD_MODE_NORMAL)) 
+
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
+
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+
+/**
+  * @}
+  */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+  
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
+  * @{
+  */
+
+/* Initialization and de-initialization functions *******************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+/* #define HAL_PWR_ConfigPVD 12*/
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+/* WakeUp pins configuration functions ****************************************/
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes configuration functions ************************************/
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+
+
+
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F1xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/