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Merge branch 'prepare_for_master' of https://git.trustie.net/xuos/xiuos into prepare_for_master

This commit is contained in:
wgzAIIT 2022-11-02 09:34:43 +08:00
parent 3352d4be6b 094986ac76
commit a39bc41597
237 changed files with 103103 additions and 28 deletions
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2
APP_Framework/Applications/lv_app/Makefile
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@ -1,4 +1,4 @@
SRC_FILES := lv_init.c lv_demo.c lv_demo_calendar.c
SRC_FILES += lv_sensor_info.c lv_sensor_update_info.c lv_sensor_info_update_demo.c
# SRC_FILES += lv_sensor_info.c lv_sensor_update_info.c lv_sensor_info_update_demo.c
include $(KERNEL_ROOT)/compiler.mk

2
APP_Framework/Applications/lv_app/lv_demo_calendar.c
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@ -39,7 +39,7 @@ static void event_handler(lv_event_t * e)
void lv_demo_calendar(void)
{
lv_obj_t * calendar = lv_calendar_create(lv_scr_act());
lv_obj_set_size(calendar, 800, 480);//lv_obj_set_size(calendar, 800, 480);
lv_obj_set_size(calendar, 320, 320);//lv_obj_set_size(calendar, 800, 480);
lv_obj_align(calendar, LV_ALIGN_CENTER, 0, 0);
lv_obj_add_event_cb(calendar, event_handler, LV_EVENT_ALL, NULL);

14
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/Kconfig Executable file
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@ -0,0 +1,14 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_HC32F4A0
config HC32F4A0_BOARD
bool "HDSC HC32F4A0 base board"
default n
---help---
Select if you are using the HC32F4A0 base board with the HC32F4A0.
endif

28
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/README.txt Executable file
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@ -0,0 +1,28 @@
README
======
This README discusses issues unique to NuttX configurations for the
HC32F4A0 development board featuring the HC32F4A0 MCU.
The board features:
NOTE: This port was developed on the original board
ways:
Contents
========
- UARTs
- HC32F4A0-specific Configuration Options
- BASIC
- Testing LLVM LIBC++ with NuttX
- Configurations
UARTs
=====
UART/USART PINS
---------------
Default USART/UART Configuration
--------------------------------

54
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/configs/nsh/defconfig Executable file
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@ -0,0 +1,54 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_ARCH_FPU is not set
# CONFIG_NSH_ARGCAT is not set
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
# CONFIG_NSH_CMDPARMS is not set
CONFIG_ADD_NUTTX_FETURES=y
CONFIG_ARCH="arm"
CONFIG_ARCH_ARMV7M=y
CONFIG_ARCH_CORTEXM4=y
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARM_THUMB=y
CONFIG_ARCH_BOARD="hc32f4a0"
CONFIG_ARCH_BOARD_HC32F4A0=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="hc32"
CONFIG_ARCH_CHIP_HC32=y
CONFIG_ARCH_CHIP_HC32F4A0=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH_TOOLCHAIN_GNU=y
CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
CONFIG_HC32F4A0_BOARD=y
CONFIG_BOARD_LATE_INITIALIZE=y
CONFIG_BUILTIN=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_FS_PROCFS=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_INTELHEX_BINARY=y
CONFIG_MM_REGIONS=1
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_START_DAY=6
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2011
CONFIG_SYSTEM_NSH=y
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_USART6_SERIAL_CONSOLE=y
CONFIG_HC32_UART6=y
CONFIG_HC32_UART6_SERIALDRIVER=y
CONFIG_UART6_SERIAL_CONSOLE=y

94
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/include/board.h Executable file
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@ -0,0 +1,94 @@
/****************************************************************************
* boards/arm/hc32/hc32f4a0/include/board.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file board.h
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-10-10
*/
#ifndef __BOARDS_ARM_HC32_HC32F4A0_INCLUDE_BOARD_H
#define __BOARDS_ARM_HC32_HC32F4A0_INCLUDE_BOARD_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
# include <stdbool.h>
#endif
/* Do not include HC32-specific header files here */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define LED_GREEN_PORT (GPIO_PORT_I)
#define LED_GREEN_PIN (GPIO_PIN_03)
/* Key port&pin definition */
#define KEY_PORT (GPIO_PORT_I)
#define KEY_PIN (GPIO_PIN_07)
/* for lowputc device output */
/* UART RX/TX Port/Pin definition */
#define LP_RX_PORT (GPIO_PORT_H) /* PH6: USART6_RX */
#define LP_RX_PIN (GPIO_PIN_06)
#define LP_RX_GPIO_FUNC (GPIO_FUNC_37_USART6_RX)
#define LP_TX_PORT (GPIO_PORT_E) /* PE6: USART6_TX */
#define LP_TX_PIN (GPIO_PIN_06)
#define LP_TX_GPIO_FUNC (GPIO_FUNC_36_USART6_TX)
/* UART unit definition */
#define LP_UNIT (M4_USART6)
#define LP_FUNCTION_CLK_GATE (PWC_FCG3_USART6)
/* UART unit interrupt definition */
#define LP_UNIT_ERR_INT_SRC (INT_USART6_EI)
#define LP_UNIT_ERR_INT_IRQn (Int015_IRQn + HC32_IRQ_FIRST)
#define LP_UNIT_RX_INT_SRC (INT_USART6_RI)
#define LP_UNIT_RX_INT_IRQn (Int103_IRQn + HC32_IRQ_FIRST)
#define LP_UNIT_TX_INT_SRC (INT_USART6_TI)
#define LP_UNIT_TX_INT_IRQn (Int102_IRQn + HC32_IRQ_FIRST)
#define LP_UNIT_TCI_INT_SRC (INT_USART6_TCI)
#define LP_UNIT_TCI_INT_IRQn (Int099_IRQn + HC32_IRQ_FIRST)
/* printf device s*/
#define BSP_PRINTF_DEVICE LP_UNIT
#define BSP_PRINTF_BAUDRATE (115200)
#define BSP_PRINTF_PORT LP_TX_PORT
#define BSP_PRINTF_PIN LP_TX_PIN
#define BSP_PRINTF_PORT_FUNC LP_TX_GPIO_FUNC
#endif /* __BOARDS_ARM_HC32_HC32F4A0_INCLUDE_BOARD_H */

92
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/kernel/Makefile Executable file
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@ -0,0 +1,92 @@
############################################################################
# boards/arm/hc32/hc32f4a0/kernel/Makefile
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/Make.defs
# The entry point name (if none is provided in the .config file)
CONFIG_INIT_ENTRYPOINT ?= user_start
ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT))
# Get the paths to the libraries and the links script path in format that
# is appropriate for the host OS
USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS)))))
USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld)
USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld)
USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex)
USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec)
USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin)
USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT)
USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS))))
USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}"
# Source files
CSRCS = stm32_userspace.c
COBJS = $(CSRCS:.c=$(OBJEXT))
OBJS = $(COBJS)
# Targets:
all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map
.PHONY: nuttx_user.elf depend clean distclean
$(COBJS): %$(OBJEXT): %.c
$(call COMPILE, $<, $@)
# Create the nuttx_user.elf file containing all of the user-mode code
nuttx_user.elf: $(OBJS)
$(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) $(USER_LIBGCC) --end-group
$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf
@echo "LD: nuttx_user.elf"
$(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf
ifeq ($(CONFIG_INTELHEX_BINARY),y)
@echo "CP: nuttx_user.hex"
$(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE)
endif
ifeq ($(CONFIG_MOTOROLA_SREC),y)
@echo "CP: nuttx_user.srec"
$(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE)
endif
ifeq ($(CONFIG_RAW_BINARY),y)
@echo "CP: nuttx_user.bin"
$(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE)
endif
$(TOPDIR)$(DELIM)User.map: nuttx_user.elf
@echo "MK: User.map"
$(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map
$(Q) $(CROSSDEV)size nuttx_user.elf
.depend:
depend: .depend
clean:
$(call DELFILE, nuttx_user.elf)
$(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*")
$(call DELFILE, "$(TOPDIR)$(DELIM)User.map")
$(call CLEAN)
distclean: clean

123
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/kernel/hc32_userspace.c Executable file
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@ -0,0 +1,123 @@
/****************************************************************************
* boards/arm/hc32/hc32f4a0/kernel/hc32_userspace.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file hc32_userspace.c
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-17
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdlib.h>
#include <nuttx/arch.h>
#include <nuttx/mm/mm.h>
#include <nuttx/wqueue.h>
#include <nuttx/userspace.h>
#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#ifndef CONFIG_NUTTX_USERSPACE
# error "CONFIG_NUTTX_USERSPACE not defined"
#endif
#if CONFIG_NUTTX_USERSPACE != 0x20060000
# error "CONFIG_NUTTX_USERSPACE must be 0x20060000 to match memory.ld"
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* These 'addresses' of these values are setup by the linker script. They are
* not actual uint32_t storage locations! They are only used meaningfully in
* the following way:
*
* - The linker script defines, for example, the symbol_sdata.
* - The declaration extern uint32_t _sdata; makes C happy. C will believe
* that the value _sdata is the address of a uint32_t variable _data (it
* is not!).
* - We can recover the linker value then by simply taking the address of
* of _data. like: uint32_t *pdata = &_sdata;
*/
extern uint32_t _stext; /* Start of .text */
extern uint32_t _etext; /* End_1 of .text + .rodata */
extern const uint32_t _eronly; /* End+1 of read only section (.text + .rodata) */
extern uint32_t _sdata; /* Start of .data */
extern uint32_t _edata; /* End+1 of .data */
extern uint32_t _sbss; /* Start of .bss */
extern uint32_t _ebss; /* End+1 of .bss */
/* This is the user space entry point */
int CONFIG_INIT_ENTRYPOINT(int argc, char *argv[]);
const struct userspace_s userspace locate_data(".userspace") =
{
/* General memory map */
.us_entrypoint = (main_t)CONFIG_INIT_ENTRYPOINT,
.us_textstart = (uintptr_t)&_stext,
.us_textend = (uintptr_t)&_etext,
.us_datasource = (uintptr_t)&_eronly,
.us_datastart = (uintptr_t)&_sdata,
.us_dataend = (uintptr_t)&_edata,
.us_bssstart = (uintptr_t)&_sbss,
.us_bssend = (uintptr_t)&_ebss,
/* Memory manager heap structure */
.us_heap = &g_mmheap,
/* Task/thread startup routines */
.task_startup = nxtask_startup,
/* Signal handler trampoline */
.signal_handler = up_signal_handler,
/* User-space work queue support (declared in include/nuttx/wqueue.h) */
#ifdef CONFIG_LIBC_USRWORK
.work_usrstart = work_usrstart,
#endif
};
/****************************************************************************
* Public Functions
****************************************************************************/
#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */

86
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/Make.defs Executable file
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@ -0,0 +1,86 @@
############################################################################
# boards/arm/hc32/hc32f4a0/scripts/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = ld.script
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
ARCHOPTIMIZATION = -g
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing
endif
ARCHCFLAGS = -fno-common -ffunction-sections -fdata-sections
ARCHCXXFLAGS = -fno-common -ffunction-sections -fdata-sections
ifneq ($(CONFIG_CXX_EXCEPTION),y)
ARCHCXXFLAGS = -fno-exceptions -fcheck-new
endif
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
ifeq ($(CONFIG_ARMV7M_TOOLCHAIN_CLANGL),y)
ARCHCFLAGS += -nostdlib -ffreestanding
ARCHCXXFLAGS += -nostdlib -ffreestanding
else
ARCHCFLAGS += -funwind-tables
ARCHCXXFLAGS += -fno-rtti -funwind-tables
endif
CFLAGS := $(APPPATHS) $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048
LDFLAGS += --gc-sections
# Loadable module definitions
CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs
LDMODULEFLAGS = -r -e module_initialize
LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld)
# ELF module definitions
CELFFLAGS = $(CFLAGS) -mlong-calls # --target1-abs
CXXELFFLAGS = $(CXXFLAGS) -mlong-calls # --target1-abs
LDELFFLAGS = -r -e main
LDELFFLAGS += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld)
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
LDFLAGS += -g
endif

126
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/gnu-elf.ld Executable file
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/****************************************************************************
* boards/arm/stm32/aiit-arm32-board/scripts/gnu-elf.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
SECTIONS
{
.text 0x00000000 :
{
_stext = . ;
*(.text)
*(.text.*)
*(.gnu.warning)
*(.stub)
*(.glue_7)
*(.glue_7t)
*(.jcr)
/* C++ support: The .init and .fini sections contain specific logic
* to manage static constructors and destructors.
*/
*(.gnu.linkonce.t.*)
*(.init) /* Old ABI */
*(.fini) /* Old ABI */
_etext = . ;
}
.ARM.extab :
{
*(.ARM.extab*)
}
.ARM.exidx :
{
*(.ARM.exidx*)
}
.rodata :
{
_srodata = . ;
*(.rodata)
*(.rodata1)
*(.rodata.*)
*(.gnu.linkonce.r*)
_erodata = . ;
}
.data :
{
_sdata = . ;
*(.data)
*(.data1)
*(.data.*)
*(.gnu.linkonce.d*)
. = ALIGN(4);
_edata = . ;
}
/* C++ support. For each global and static local C++ object,
* GCC creates a small subroutine to construct the object. Pointers
* to these routines (not the routines themselves) are stored as
* simple, linear arrays in the .ctors section of the object file.
* Similarly, pointers to global/static destructor routines are
* stored in .dtors.
*/
.ctors :
{
_sctors = . ;
*(.ctors) /* Old ABI: Unallocated */
*(.init_array) /* New ABI: Allocated */
_edtors = . ;
}
.dtors :
{
_sdtors = . ;
*(.dtors) /* Old ABI: Unallocated */
*(.fini_array) /* New ABI: Allocated */
_edtors = . ;
}
.bss :
{
_sbss = . ;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.b*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
}
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

96
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/kernel-space.ld Executable file
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@ -0,0 +1,96 @@
/****************************************************************************
* boards/arm/stm32/aiit-arm32-board/scripts/kernel-space.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* NOTE: This depends on the memory.ld script having been included prior to
* this script.
*/
OUTPUT_ARCH(arm)
ENTRY(_stext)
SECTIONS
{
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > kflash
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > kflash
.ARM.extab : {
*(.ARM.extab*)
} > kflash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > kflash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
. = ALIGN(4);
_edata = ABSOLUTE(.);
} > ksram AT > kflash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > ksram
/* Stabs debugging sections */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

123
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/ld.script Executable file
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@ -0,0 +1,123 @@
/****************************************************************************
* boards/arm/hc32/hc32f4a0/scripts/ld.script
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and
* 192Kb of SRAM. SRAM is split up into three blocks:
*
* 1) 112Kb of SRAM beginning at address 0x2000:0000
* 2) 16Kb of SRAM beginning at address 0x2001:c000
* 3) 64Kb of CCM SRAM beginning at address 0x1000:0000
*
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
* where the code expects to begin execution by jumping to the entry point in
* the 0x0800:0000 address
* range.
*/
MEMORY
{
flash (rx) : ORIGIN = 0x00000000, LENGTH = 2M
sram (rwx) : ORIGIN = 0x1FFE0000, LENGTH = 512K
}
OUTPUT_ARCH(arm)
ENTRY(_stext)
EXTERN(_vectors)
SECTIONS
{
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
.init_section : ALIGN(4) {
_sinit = ABSOLUTE(.);
KEEP(*(.init_array .init_array.*))
_einit = ABSOLUTE(.);
} > flash
.ARM.extab : ALIGN(4) {
*(.ARM.extab*)
} > flash
.ARM.exidx : ALIGN(4) {
__exidx_start = ABSOLUTE(.);
*(.ARM.exidx*)
__exidx_end = ABSOLUTE(.);
} > flash
.tdata : {
_stdata = ABSOLUTE(.);
*(.tdata .tdata.* .gnu.linkonce.td.*);
_etdata = ABSOLUTE(.);
} > flash
.tbss : {
_stbss = ABSOLUTE(.);
*(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon);
_etbss = ABSOLUTE(.);
} > flash
_eronly = ABSOLUTE(.);
.data : ALIGN(4) {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
. = ALIGN(4);
_edata = ABSOLUTE(.);
} > sram AT > flash
.bss : ALIGN(4) {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > sram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

85
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/memory.ld Executable file
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@ -0,0 +1,85 @@
/****************************************************************************
* boards/arm/hc32/hc32f4a0/scripts/memory.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and
* 192Kb of SRAM. SRAM is split up into three blocks:
*
* 1) 112KB of SRAM beginning at address 0x2000:0000
* 2) 16KB of SRAM beginning at address 0x2001:c000
* 3) 64KB of CCM SRAM beginning at address 0x1000:0000
*
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
* where the code expects to begin execution by jumping to the entry point in
* the 0x0800:0000 address range.
*
* For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of
* FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which
* should fit into 64KB and, of course, can be optimized as needed (See
* also boards/arm/stm32/aiit-arm32-board/scripts/kernel-space.ld). Allowing the
* additional does permit addition debug instrumentation to be added to the
* kernel space without overflowing the partition.
*
* Alignment of the user space FLASH partition is also a critical factor:
* The user space FLASH partition will be spanned with a single region of
* size 2**n bytes. The alignment of the user-space region must be the same.
* As a consequence, as the user-space increases in size, the alignment
* requirement also increases.
*
* This alignment requirement means that the largest user space FLASH region
* you can have will be 512KB at it would have to be positioned at
* 0x08800000. If you change this address, don't forget to change the
* CONFIG_NUTTX_USERSPACE configuration setting to match and to modify
* the check in kernel/userspace.c.
*
* For the same reasons, the maximum size of the SRAM mapping is limited to
* 4KB. Both of these alignment limitations could be reduced by using
* multiple regions to map the FLASH/SDRAM range or perhaps with some
* clever use of subregions.
*
* A detailed memory map for the 112KB SRAM region is as follows:
*
* 0x20000 0000: Kernel .data region. Typical size: 0.1KB
* ------- ---- Kernel .bss region. Typical size: 1.8KB
* 0x20000 0800: Kernel IDLE thread stack (approximate). Size is
* determined by CONFIG_IDLETHREAD_STACKSIZE and
* adjustments for alignment. Typical is 1KB.
* ------- ---- Padded to 4KB
* 0x20000 1000: User .data region. Size is variable.
* ------- ---- User .bss region Size is variable.
* 0x20000 2000: Beginning of kernel heap. Size determined by
* CONFIG_MM_KERNEL_HEAPSIZE.
* ------- ---- Beginning of user heap. Can vary with other settings.
* 0x20001 c000: End+1 of CPU RAM
*/
MEMORY
{
/* 2Mb FLASH */
kflash (rx) : ORIGIN = 0x00000000, LENGTH = 2M
uflash (rx) : ORIGIN = 0x00200000, LENGTH = 128K
xflash (rx) : ORIGIN = 0x00220000, LENGTH = 768K
/* 512Kb of contiguous SRAM */
ksram (rwx) : ORIGIN = 0x1FFE0000, LENGTH = 512K
usram (rwx) : ORIGIN = 0x20060000, LENGTH = 4K
xsram (rwx) : ORIGIN = 0x20062000, LENGTH = 4K
}

98
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/user-space.ld Executable file
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@ -0,0 +1,98 @@
/****************************************************************************
* boards/arm/hc32/hc32f4a0/scripts/user-space.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* NOTE: This depends on the memory.ld script having been included prior to
* this script.
*/
OUTPUT_ARCH(arm)
SECTIONS
{
.userspace : {
*(.userspace)
} > uflash
.text : {
_stext = ABSOLUTE(.);
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > uflash
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > kflash
.ARM.extab : {
*(.ARM.extab*)
} > kflash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > kflash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
. = ALIGN(4);
_edata = ABSOLUTE(.);
} > ksram AT > kflash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > ksram
/* Stabs debugging sections */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

0
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/.depend Executable file
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32
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/Make.defs Executable file
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@ -0,0 +1,32 @@
############################################################################
# boards/arm/hc32/hc32f4a0/src/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/Make.defs
CSRCS = hc32_bringup.c hc32_appinit.c hc32_boot.c
ifeq ($(CONFIG_ARCH_LEDS),y)
CSRCS +=
endif
DEPPATH += --dep-path board
VPATH += :board
CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board)

115
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/Make.dep Executable file
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@ -0,0 +1,115 @@
hc32_boot.o: hc32_boot.c \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/config.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/debug.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/compiler.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/syslog.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stdint.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/types.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/inttypes.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/limits.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/limits.h \
/usr/local/arm/gcc-arm-none-eabi-6-2017-q1-update/lib/gcc/arm-none-eabi/6.3.1/include/stdarg.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stdbool.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/sys/uio.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/sys/types.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/board.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/board/board.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/common/arm_internal.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/arch.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/arch.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/pgalloc.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/addrenv.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/cache.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/sched.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/queue.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/sched.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/strings.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/string.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stddef.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/time.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/queue.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/signal.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/semaphore.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/clock.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/irq.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/irq.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/chip/irq.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/armv7-m/irq.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/armv7-m/nvicpri.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/chip/chip.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/armv7-m/irq_cmnvector.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/tls.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/pthread.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/unistd.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/wdog.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/mm/shm.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/mm/gran.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/fs/fs.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/semaphore.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/errno.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/net/net.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/armv7-m/nvic.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/armv7-m/itm.h
hc32_appinit.o: hc32_appinit.c \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/config.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/board.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stdint.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/compiler.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/types.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/inttypes.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/limits.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/limits.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stdbool.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/chip/hc32f4a0.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/chip/core_cm4.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/armv7-m/itm.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/chip/cmsis_version.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/chip/cmsis_compiler.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/chip/cmsis_gcc.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/chip/mpu_armv7.h
hc32_bringup.o: hc32_bringup.c \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/config.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stdbool.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/compiler.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stdint.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/types.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/inttypes.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/limits.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/limits.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stdio.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/sys/types.h \
/usr/local/arm/gcc-arm-none-eabi-6-2017-q1-update/lib/gcc/arm-none-eabi/6.3.1/include/stdarg.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/time.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/fs/fs.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/semaphore.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/errno.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/semaphore.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/clock.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/sched.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/queue.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/sched.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/strings.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/string.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stddef.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/queue.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/signal.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/irq.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/irq.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/chip/irq.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/armv7-m/irq.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/armv7-m/nvicpri.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/chip/chip.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/armv7-m/irq_cmnvector.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/tls.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/pthread.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/unistd.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/wdog.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/mm/shm.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/mm/gran.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/net/net.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/arch.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/pgalloc.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/addrenv.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/debug.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/syslog.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/sys/uio.h

25
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/Makefile Executable file
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@ -0,0 +1,25 @@
############################################################################
# boards/arm/imxrt/xidatong-arm32/src/Makefile
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/Make.defs
CSRCS = hc32_boot.c hc32_appinit.c hc32_bringup.c
include $(TOPDIR)/boards/Board.mk

79
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_appinit.c Executable file
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@ -0,0 +1,79 @@
/****************************************************************************
* boards/arm/hc32/hc32f4a0/src/hc32_appinit.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/board.h>
#include "hc32f4a0.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef OK
# define OK 0
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_app_initialize
*
* Description:
* Perform application specific initialization. This function is never
* called directly from application code, but only indirectly via the
* (non-standard) boardctl() interface using the command BOARDIOC_INIT.
*
* Input Parameters:
* arg - The boardctl() argument is passed to the board_app_initialize()
* implementation without modification. The argument has no
* meaning to NuttX; the meaning of the argument is a contract
* between the board-specific initialization logic and the
* matching application logic. The value could be such things as a
* mode enumeration value, a set of DIP switch switch settings, a
* pointer to configuration data read from a file or serial FLASH,
* or whatever you would like to do with it. Every implementation
* should accept zero/NULL as a default configuration.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure to indicate the nature of the failure.
*
****************************************************************************/
int board_app_initialize(uintptr_t arg)
{
#ifdef CONFIG_BOARD_LATE_INITIALIZE
/* Board initialization already performed by board_late_initialize() */
return OK;
#else
/* Perform board-specific initialization */
return hc32_bringup();
#endif
}

128
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_boot.c Executable file
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/****************************************************************************
* boards/arm/hc32/hc32f4a0/src/hc32_boot.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "nvic.h"
#include "itm.h"
/****************************************************************************
* Public Functions
****************************************************************************/
extern int hc32_bringup(void);
/****************************************************************************
* Name: hc32_boardinitialize
*
* Description:
* All HC32 architectures must provide the following entry point. This
* entry point is called early in the initialization -- after all memory
* has been configured and mapped but before any devices have been
* initialized.
*
****************************************************************************/
void hc32_boardinitialize(void)
{
//#ifdef CONFIG_SCHED_CRITMONITOR
// /* Enable ITM and DWT resources, if not left enabled by debugger. */
//
// modifyreg32(NVIC_DEMCR, 0, NVIC_DEMCR_TRCENA);
//
// /* Make sure the high speed cycle counter is running. It will be started
// * automatically only if a debugger is connected.
// */
//
// putreg32(0xc5acce55, ITM_LAR);
// modifyreg32(DWT_CTRL, 0, DWT_CTRL_CYCCNTENA_MASK);
//#endif
//
//#if defined(CONFIG_HC32_SPI1) || defined(CONFIG_HC32_SPI2) || defined(CONFIG_HC32_SPI3)
// /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak
// * function hc32_spidev_initialize() has been brought into the link.
// */
//
// if (hc32_spidev_initialize)
// {
// hc32_spidev_initialize();
// }
//#endif
//
//#ifdef CONFIG_HC32_OTGFS
// /* Initialize USB if the 1) OTG FS controller is in the configuration and
// * 2) disabled, and 3) the weak function hc32_usbinitialize() has been
// * brought into the build. Presumably either CONFIG_USBDEV or
// * CONFIG_USBHOST is also selected.
// */
//
// if (hc32_usbinitialize)
// {
// hc32_usbinitialize();
// }
//#endif
//
//#ifdef HAVE_NETMONITOR
// /* Configure board resources to support networking. */
//
// if (hc32_netinitialize)
// {
// hc32_netinitialize();
// }
//#endif
//
//#ifdef CONFIG_ARCH_LEDS
// /* Configure on-board LEDs if LED support has been selected. */
//
// board_autoled_initialize();
//#endif
}
/****************************************************************************
* Name: board_late_initialize
*
* Description:
* If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
* initialization call will be performed in the boot-up sequence to a
* function called board_late_initialize(). board_late_initialize() will be
* called immediately after up_initialize() is called and just before the
* initial application is started. This additional initialization phase
* may be used, for example, to initialize board-specific device drivers.
*
****************************************************************************/
#ifdef CONFIG_BOARD_LATE_INITIALIZE
void board_late_initialize(void)
{
/* Perform board-specific initialization */
hc32_bringup();
}
#endif

53
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_bringup.c Executable file
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/****************************************************************************
* boards/arm/hc32/hc32f4a0/src/hc32f4a0_bringup.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdio.h>
#include <debug.h>
#include <errno.h>
#include <nuttx/fs/fs.h>
/****************************************************************************
* Name: hc32_bringup
*
* Description:
* Perform architecture-specific initialization
*
* CONFIG_BOARD_LATE_INITIALIZE=y :
* Called from board_late_initialize().
*
* CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y :
* Called from the NSH library
*
****************************************************************************/
int hc32_bringup(void)
{
int ret = 0;
printf("start %s\n", __func__);
return ret;
}

1
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/build.sh
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@ -19,5 +19,6 @@ cp -rf $nuttx/aiit_board/aiit-arm32-board $nuttx/nuttx/boards/arm/stm32
cp -rf $nuttx/aiit_board/aiit-riscv64-board $nuttx/nuttx/boards/risc-v/k210
cp -rf $nuttx/aiit_board/xidatong-riscv64 $nuttx/nuttx/boards/risc-v/k210
cp -rf $nuttx/aiit_board/xidatong-arm32 $nuttx/nuttx/boards/arm/imxrt
cp -rf $nuttx/aiit_board/hc32f4a0 $nuttx/nuttx/boards/arm/hc32
cd ../nuttx

1229
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/Kconfig Executable file
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30
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/include/hc32/chip.h Executable file
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/****************************************************************************
* arch/arm/include/stm32f7/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_HC32F4A0_CHIP_H
#define __ARCH_ARM_INCLUDE_HC32F4A0_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#endif /* __ARCH_ARM_INCLUDE_HC32F4A0_CHIP_H */

102
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/include/hc32/irq.h Executable file
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/****************************************************************************
* arch/arm/include/HC32F4A0/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_HC32F4A0_IRQ_H
#define __ARCH_ARM_INCLUDE_HC32F4A0_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/* Processor Exceptions (vectors 0-15) */
#define HC32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define HC32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define HC32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define HC32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define HC32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define HC32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define HC32_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define HC32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define HC32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define HC32_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16).
* These definitions are chip-specific
*/
#define HC32_IRQ_FIRST (16) /* Vector number of the first external interrupt */
#define NR_IRQS (144 + 15)
#define NVIC_SYSH_PRIORITY_MIN 0xf0
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80
#define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_PRIORITY_DEFAULT
#define ARMV7M_PERIPHERAL_INTERRUPTS NR_IRQS
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_HC32F4A0_IRQ_H */

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Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/Kconfig Executable file
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#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
comment "HC32 Configuration Options"
choice
prompt "HC32 Chip Selection"
default HC32F4A0_CHIP
config HC32F4A0_CHIP
bool "HC32F4A0"
---help---
endchoice
menu "HC32 U[S]ART Selection"
config HC32_UART1
bool "UART1"
default n
select UART_SERIALDRIVER
select UART1_SERIALDRIVER
select HC32_UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
select HC32_UART
config HC32_UART2
bool "UART2"
default n
select HC32_UART2_SERIALDRIVER
select UART_SERIALDRIVER
select UART2_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
select HC32_UART
config HC32_UART3
bool "UART3"
default n
select ARCH_HAVE_SERIAL_TERMIOS
select UART_SERIALDRIVER
select UART3_SERIALDRIVER
select HC32_UART3_SERIALDRIVER
select HC32_UART
config HC32_UART4
bool "UART4"
default n
select ARCH_HAVE_SERIAL_TERMIOS
select UART_SERIALDRIVER
select UART4_SERIALDRIVER
select HC32_UART4_SERIALDRIVER
select HC32_UART
config HC32_UART5
bool "UART5"
default n
select ARCH_HAVE_SERIAL_TERMIOS
select UART_SERIALDRIVER
select UART5_SERIALDRIVER
select HC32_UART5_SERIALDRIVER
select HC32_UART
config HC32_UART6
bool "UART6"
default n
select ARCH_HAVE_SERIAL_TERMIOS
select UART_SERIALDRIVER
select UART6_SERIALDRIVER
select HC32_UART6_SERIALDRIVER
select HC32_UART
config HC32_UART6_SERIALDRIVER
bool "UART6SERIAL"
default n
if HC32_UART6
menu "UART6 Configuration"
depends on UART6_SERIALDRIVER
config UART6_RXBUFSIZE
int "Receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config UART6_TXBUFSIZE
int "Transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config UART6_BAUD
int "BAUD rate"
default 115200
---help---
The configured BAUD of the UART.
config UART6_BITS
int "Character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config UART6_PARITY
int "Parity setting"
range 0 2
default 0
---help---
0=no parity, 1=odd parity, 2=even parity
config UART6_2STOP
int "use 2 stop bits"
default 0
---help---
1=Two stop bits
config UART6_IFLOWCONTROL
bool "UART6 RTS flow control"
default n
select SERIAL_IFLOWCONTROL
---help---
Enable UART6 RTS flow control
config UART6_OFLOWCONTROL
bool "UART6 CTS flow control"
default n
select SERIAL_OFLOWCONTROL
---help---
Enable UART6 CTS flow control
config UART6_RXDMA
bool "UART6 Rx DMA support"
default n
select SERIAL_RXDMA
---help---
Enable Rx DMA transfers on UART6
config UART6_TXDMA
bool "UART6 Tx DMA support"
default n
select SERIAL_TXDMA
---help---
Enable Tx DMA transfers on UART6
endmenu
endif
config HC32_UART7
bool "UART7"
default n
select ARCH_HAVE_SERIAL_TERMIOS
select UART_SERIALDRIVER
select UART7_SERIALDRIVER
select HC32_UART7_SERIALDRIVER
select HC32_UART
config HC32_UART8
bool "UART8"
default n
select ARCH_HAVE_SERIAL_TERMIOS
select UART_SERIALDRIVER
select UART8_SERIALDRIVER
select HC32_UART8_SERIALDRIVER
select HC32_UART
endmenu # HC32 U[S]ART Selection

88
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/Make.defs Executable file
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############################################################################
# arch/arm/src/hc32/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S
CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_copyfullstate.c arm_createstack.c
CMN_CSRCS += arm_exit.c arm_hardfault.c arm_initialize.c arm_initialstate.c
CMN_CSRCS += arm_interruptcontext.c arm_memfault.c arm_modifyreg8.c arm_mdelay.c
CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_releasepending.c
CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_stackframe.c arm_svcall.c arm_systemreset.c
CMN_CSRCS += arm_trigger_irq.c arm_unblocktask.c arm_udelay.c arm_usestack.c
CMN_CSRCS += arm_doirq.c arm_vfork.c arm_switchcontext.c arm_puts.c
CMN_CSRCS += arm_tcbinfo.c
ifeq ($(CONFIG_HC32_TICKLESS_SYSTICK),y)
CMN_CSRCS += arm_systick.c
endif
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += arm_lazyexception.S
else
CMN_ASRCS += arm_exception.S
endif
CMN_CSRCS += arm_vectors.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifneq ($(filter y,$(CONFIG_ARM_MPU) $(CONFIG_ARM_MPU_EARLY_RESET)),)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_copyarmstate.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
CMN_CSRCS += arm_itm_syslog.c
endif
ifeq ($(CONFIG_SCHED_THREAD_LOCAL),y)
CMN_CSRCS += arm_tls.c
endif
CHIP_CSRCS = hc32_allocateheap.c hc32_gpio.c
CHIP_CSRCS += hc32_irq.c hc32_idle.c hc32_mpuinit.c
CHIP_CSRCS += hc32_rcc.c hc32_start.c hc32_serial.c
CHIP_CSRCS += hc32_pm.c hc32_timerisr.c hc32_lowputc.c
CHIP_CSRCS += hc32f4a0_clk.c hc32f4a0_efm.c hc32f4a0_gpio.c
CHIP_CSRCS += hc32f4a0_interrupts.c hc32f4a0_usart.c hc32f4a0_utility.c
CHIP_CSRCS += hc32f4a0_sram.c hc32f4a0_pwc.c

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Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/chip.h Executable file
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/****************************************************************************
* arch/arm/src/hc32/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_HC32_CHIP_H
#define __ARCH_ARM_SRC_HC32_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Include the chip capabilities file */
#include <arch/hc32/chip.h>
/* Include the chip interrupt definition file */
#include <arch/hc32/irq.h>
/* Include the chip memory map */
//#include "hardware/hc32_memorymap.h"
/* Include the chip pinmap */
//#include "hardware/hc32_pinmap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Provide the required number of peripheral interrupt vector definitions as
* well. The definition HC32_IRQ_NEXTINT simply comes from the chip-specific
* IRQ header file included by arch/hc32/irq.h.
*/
//#define ARMV7M_PERIPHERAL_INTERRUPTS HC32_IRQ_NEXTINT
#endif /* __ARCH_ARM_SRC_HC32_CHIP_H */

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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.7
* @date 19. June 2018
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2018 IAR Systems
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/core_cm4.h Executable file
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214
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/ddl_config.h Executable file
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/**
*******************************************************************************
* @file usart/uart_int/source/ddl_config.h
* @brief This file contains HC32 Series Device Driver Library usage management.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __DDL_CONFIG_H__
#define __DDL_CONFIG_H__
/*******************************************************************************
* Include files
******************************************************************************/
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/* Chip module on-off define */
#define DDL_ON (1U)
#define DDL_OFF (0U)
/**
* @brief This is the list of modules to be used in the Device Driver Library.
* Select the modules you need to use to DDL_ON.
* @note DDL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
* properly.
* @note DDL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
* Library.
* @note DDL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
*/
#define DDL_ICG_ENABLE (DDL_ON)
#define DDL_UTILITY_ENABLE (DDL_ON)
#define DDL_PRINT_ENABLE (DDL_ON)
#define DDL_ADC_ENABLE (DDL_OFF)
#define DDL_AES_ENABLE (DDL_OFF)
#define DDL_CAN_ENABLE (DDL_OFF)
#define DDL_CLK_ENABLE (DDL_ON)
#define DDL_CMP_ENABLE (DDL_OFF)
#define DDL_CRC_ENABLE (DDL_OFF)
#define DDL_CTC_ENABLE (DDL_OFF)
#define DDL_DAC_ENABLE (DDL_OFF)
#define DDL_DCU_ENABLE (DDL_OFF)
#define DDL_DMA_ENABLE (DDL_OFF)
#define DDL_DMC_ENABLE (DDL_OFF)
#define DDL_DVP_ENABLE (DDL_OFF)
#define DDL_EFM_ENABLE (DDL_ON)
#define DDL_EMB_ENABLE (DDL_OFF)
#define DDL_ETH_ENABLE (DDL_OFF)
#define DDL_EVENT_PORT_ENABLE (DDL_OFF)
#define DDL_FCM_ENABLE (DDL_OFF)
#define DDL_FMAC_ENABLE (DDL_OFF)
#define DDL_GPIO_ENABLE (DDL_ON)
#define DDL_HASH_ENABLE (DDL_OFF)
#define DDL_HRPWM_ENABLE (DDL_OFF)
#define DDL_I2C_ENABLE (DDL_ON)
#define DDL_I2S_ENABLE (DDL_OFF)
#define DDL_INTERRUPTS_ENABLE (DDL_ON)
#define DDL_KEYSCAN_ENABLE (DDL_ON)
#define DDL_MAU_ENABLE (DDL_OFF)
#define DDL_MPU_ENABLE (DDL_OFF)
#define DDL_NFC_ENABLE (DDL_OFF)
#define DDL_OTS_ENABLE (DDL_OFF)
#define DDL_PWC_ENABLE (DDL_ON)
#define DDL_QSPI_ENABLE (DDL_OFF)
#define DDL_RMU_ENABLE (DDL_OFF)
#define DDL_RTC_ENABLE (DDL_OFF)
#define DDL_SDIOC_ENABLE (DDL_OFF)
#define DDL_SMC_ENABLE (DDL_OFF)
#define DDL_SPI_ENABLE (DDL_OFF)
#define DDL_SRAM_ENABLE (DDL_ON)
#define DDL_SWDT_ENABLE (DDL_OFF)
#define DDL_TMR0_ENABLE (DDL_OFF)
#define DDL_TMR2_ENABLE (DDL_OFF)
#define DDL_TMR4_ENABLE (DDL_OFF)
#define DDL_TMR6_ENABLE (DDL_OFF)
#define DDL_TMRA_ENABLE (DDL_OFF)
#define DDL_TRNG_ENABLE (DDL_OFF)
#define DDL_USART_ENABLE (DDL_ON)
#define DDL_USBFS_ENABLE (DDL_OFF)
#define DDL_USBHS_ENABLE (DDL_OFF)
#define DDL_WDT_ENABLE (DDL_OFF)
/* BSP on-off define */
#define BSP_ON (1U)
#define BSP_OFF (0U)
/**
* @brief The following is a list of currently supported BSP boards.
*/
#define BSP_EV_HC32F4A0_LQFP176 (1U)
#define BSP_MS_HC32F4A0_LQFP176_050_MEM (2U)
/**
* @brief The macro BSP_EV_HC32F4A0 is used to specify the BSP board currently
* in use.
* The value should be set to one of the list of currently supported BSP boards.
* @note If there is no supported BSP board or the BSP function is not used,
* the value needs to be set to BSP_EV_HC32F4A0.
*/
#define BSP_EV_HC32F4A0 (BSP_EV_HC32F4A0_LQFP176)
/**
* @brief This is the list of BSP components to be used.
* Select the components you need to use to BSP_ON.
*/
#define BSP_CY62167EV30LL_ENABLE (BSP_OFF)
#define BSP_IS42S16400J7TLI_ENABLE (BSP_OFF)
#define BSP_IS62WV51216_ENABLE (BSP_OFF)
#define BSP_MT29F2G08AB_ENABLE (BSP_OFF)
#define BSP_NT35510_ENABLE (BSP_OFF)
#define BSP_OV5640_ENABLE (BSP_OFF)
#define BSP_S29GL064N90TFI03_ENABLE (BSP_OFF)
#define BSP_TCA9539_ENABLE (BSP_OFF)
#define BSP_W25QXX_ENABLE (BSP_ON)
#define BSP_WM8731_ENABLE (BSP_OFF)
/**
* @brief Ethernet and PHY Configuration.
* @note PHY delay these values are based on a 1 ms Systick interrupt.
*/
/* MAC ADDRESS */
#define ETH_MAC_ADDR0 (2U)
#define ETH_MAC_ADDR1 (0U)
#define ETH_MAC_ADDR2 (0U)
#define ETH_MAC_ADDR3 (0U)
#define ETH_MAC_ADDR4 (0U)
#define ETH_MAC_ADDR5 (0U)
/* Ethernet driver buffers size and count */
#define ETH_TXBUF_SIZE (ETH_PACKET_MAX_SIZE) /* Buffer size for receive */
#define ETH_RXBUF_SIZE (ETH_PACKET_MAX_SIZE) /* Buffer size for transmit */
#define ETH_TXBUF_NUMBER (4UL) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_RXBUF_NUMBER (4UL) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* PHY Address*/
#define PHY_ADDRESS (0x00U) /* RTL8201F */
/* PHY Configuration delay */
#define PHY_HW_RESET_DELAY (0x0000003FUL)
#define PHY_RESET_DELAY (0x0000007FUL)
#define PHY_CONFIG_DELAY (0x0000003FUL)
#define PHY_READ_TIMEOUT (0x00000005UL)
#define PHY_WRITE_TIMEOUT (0x00000005UL)
/* Common PHY Registers */
#define PHY_BCR (0x00U) /*!< Basic Control Register */
#define PHY_BSR (0x01U) /*!< Basic Status Register */
#define PHY_SOFT_RESET (0x8000U) /*!< PHY Soft Reset */
#define PHY_LOOPBACK (0x4000U) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M (0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M (0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M (0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M (0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION (0x1000U) /*!< Enable auto-negotiation function */
#define PHY_POWERDOWN (0x0800U) /*!< Select the power down mode */
#define PHY_ISOLATE (0x0400U) /*!< Isolate PHY from MII */
#define PHY_RESTART_AUTONEGOTIATION (0x0200U) /*!< Restart auto-negotiation function */
#define PHY_100BASE_TX_FD (0x4000U) /*!< 100Base-TX full duplex support */
#define PHY_100BASE_TX_HD (0x2000U) /*!< 100Base-TX half duplex support */
#define PHY_10BASE_T_FD (0x1000U) /*!< 10Base-T full duplex support */
#define PHY_10BASE_T_HD (0x0800U) /*!< 10Base-T half duplex support */
#define PHY_AUTONEGO_COMPLETE (0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_LINK_STATUS (0x0004U) /*!< Valid link established */
#define PHY_JABBER_DETECTION (0x0002U) /*!< Jabber condition detected */
/**
* @brief External clock source for I2S peripheral
*/
#ifndef I2S_EXT_CLK_FREQ
#define I2S_EXT_CLK_FREQ (12288000UL) /*!< Value of the external oscillator */
#endif /* I2S_EXT_CLK_FREQ */
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* __DDL_CONFIG_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/****************************************************************************
* arch/arm/src/hc32/hc32_allocateheap.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <string.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/kmalloc.h>
#include <nuttx/userspace.h>
#include <arch/board/board.h>
#include "chip.h"
#include "mpu.h"
#include "arm_internal.h"
#include "hc32_mpuinit.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Internal SRAM is available in all members of the HC32 family. The
* following definitions must be provided to specify the size and
* location of internal(system) SRAM:
*
* CONFIG_RAM_END : End address (+1) of SRAM (F1 family only, the
* : F4 family uses the a priori end of SRAM)
*
* The F4 family also contains internal CCM SRAM. This SRAM is different
* because it cannot be used for DMA. So if DMA needed, then the following
* should be defined to exclude CCM SRAM from the heap:
*
* CONFIG_HC32_CCMEXCLUDE : Exclude CCM SRAM from the HEAP
*
* In addition to internal SRAM, external RAM may also be available through
* the FMC/FSMC. To use external RAM, the following things need to be present
* in the NuttX configuration file:
*
* CONFIG_HC32_FSMC=y : Enables the FSMC
* CONFIG_HC32_FMC=y : Enables the FMC
* CONFIG_HC32_EXTERNAL_RAM=y : Indicates external RAM is available via the
* FMC/FSMC (as opposed to an LCD or FLASH).
* CONFIG_HEAP2_BASE : The base address of the external RAM
* CONFIG_HEAP2_SIZE : The size of the external RAM
* CONFIG_MM_REGIONS : Must be set to a large enough value to
* include the external RAM (as determined by
* the rules provided below)
*/
#if !defined(CONFIG_HC32_FSMC) && !defined(CONFIG_HC32_FMC)
# undef CONFIG_HC32_EXTERNAL_RAM
#endif
//#if defined(CONFIG_HC32_HC32F4A0)
/* The HC32 F4A0 have no CCM SRAM */
# if defined(CONFIG_HC32_HC32F4A0)
# undef CONFIG_HC32_CCMEXCLUDE
# define CONFIG_HC32_CCMEXCLUDE 1
# endif
/* Set the end of system SRAM */
#define SRAM1_END 0x20073880
/* Set the range of CCM SRAM as well (although we may not use it) */
#define SRAM2_START 0x1FE00000
#define SRAM2_END 0x20073880
/* There are 4 possible SRAM configurations:
*
* Configuration 1. System SRAM (only)
* CONFIG_MM_REGIONS == 1
* CONFIG_HC32_EXTERNAL_RAM NOT defined
* CONFIG_HC32_CCMEXCLUDE defined
* Configuration 2. System SRAM and CCM SRAM
* CONFIG_MM_REGIONS == 2
* CONFIG_HC32_EXTERNAL_RAM NOT defined
* CONFIG_HC32_CCMEXCLUDE NOT defined
* Configuration 3. System SRAM and FSMC SRAM
* CONFIG_MM_REGIONS == 2
* CONFIG_HC32_EXTERNAL_RAM defined
* CONFIG_HC32_CCMEXCLUDE defined
* Configuration 4. System SRAM, CCM SRAM, and FSMC SRAM
* CONFIG_MM_REGIONS == 3
* CONFIG_HC32_EXTERNAL_RAM defined
* CONFIG_HC32_CCMEXCLUDE NOT defined
*
* Let's make sure that all definitions are consistent before doing
* anything else
*/
# if defined(CONFIG_HC32_EXTERNAL_RAM)
/* Configuration 3 or 4. External SRAM is available. CONFIG_MM_REGIONS
* should be at least 2.
*/
# if CONFIG_MM_REGIONS < 2
/* Only one memory region. Force Configuration 1 */
# warning "FSMC SRAM (and CCM SRAM) excluded from the heap"
# undef CONFIG_HC32_EXTERNAL_RAM
# undef CONFIG_HC32_CCMEXCLUDE
# define CONFIG_HC32_CCMEXCLUDE 1
/* CONFIG_MM_REGIONS may be 3 if CCM SRAM is included in the head */
# elif CONFIG_MM_REGIONS > 2
/* More than two memory regions. This is okay if CCM SRAM is not
* disabled.
*/
# if defined(CONFIG_HC32_CCMEXCLUDE)
/* Configuration 3: CONFIG_MM_REGIONS should have been 2 */
# error "CONFIG_MM_REGIONS > 2 but I don't know what some of the region(s) are"
# undef CONFIG_MM_REGIONS
# define CONFIG_MM_REGIONS 2
# else
/* Configuration 4: DMA should be disabled and CONFIG_MM_REGIONS
* should be 3.
*/
# ifdef CONFIG_ARCH_DMA
# warning "CCM SRAM is included in the heap AND DMA is enabled"
# endif
# if CONFIG_MM_REGIONS != 3
# error "CONFIG_MM_REGIONS > 3 but I don't know what some of the region(s) are"
# undef CONFIG_MM_REGIONS
# define CONFIG_MM_REGIONS 3
# endif
# endif
/* CONFIG_MM_REGIONS is exactly 2. We cannot support both CCM SRAM and
* FSMC SRAM.
*/
# elif !defined(CONFIG_HC32_CCMEXCLUDE)
# error "CONFIG_MM_REGIONS == 2, cannot support both CCM SRAM and FSMC SRAM"
# undef CONFIG_HC32_CCMEXCLUDE
# define CONFIG_HC32_CCMEXCLUDE 1
# endif
# elif !defined(CONFIG_HC32_CCMEXCLUDE)
/* Configuration 2: FSMC SRAM is not used, but CCM SRAM is requested.
* DMA should be disabled and CONFIG_MM_REGIONS should be 2.
*/
# ifdef CONFIG_ARCH_DMA
# warning "CCM SRAM is included in the heap AND DMA is enabled"
# endif
# if CONFIG_MM_REGIONS < 2
# ifdef CONFIG_HC32_HAVE_CCM
# error "CCM SRAM excluded from the heap because CONFIG_MM_REGIONS < 2"
# endif
# undef CONFIG_HC32_CCMEXCLUDE
# define CONFIG_HC32_CCMEXCLUDE 1
# elif CONFIG_MM_REGIONS > 2
# error "CONFIG_MM_REGIONS > 2 but I don't know what some of the region(s) are"
# undef CONFIG_MM_REGIONS
# define CONFIG_MM_REGIONS 2
# endif
# endif
/* There are 4 possible SRAM configurations:
*
* Configuration 1. System SRAM (only)
* CONFIG_MM_REGIONS == 1
* CONFIG_HC32_EXTERNAL_RAM NOT defined
* CONFIG_HC32_CCMEXCLUDE defined
* Configuration 2. System SRAM and CCM SRAM
* CONFIG_MM_REGIONS == 2
* CONFIG_HC32_EXTERNAL_RAM NOT defined
* CONFIG_HC32_CCMEXCLUDE NOT defined
* Configuration 3. System SRAM and FSMC SRAM
* CONFIG_MM_REGIONS == 2
* CONFIG_HC32_EXTERNAL_RAM defined
* CONFIG_HC32_CCMEXCLUDE defined
* Configuration 4. System SRAM, CCM SRAM, and FSMC SRAM
* CONFIG_MM_REGIONS == 3
* CONFIG_HC32_EXTERNAL_RAM defined
* CONFIG_HC32_CCMEXCLUDE NOT defined
*
* Let's make sure that all definitions are consistent before doing
* anything else
*/
# if defined(CONFIG_HC32_EXTERNAL_RAM)
# if (CONFIG_MM_REGIONS == 2)
/* OK: This is Configuration 3: SRAM and FSMC */
# elif (CONFIG_MM_REGIONS == 3)
/* OK: This is Configuration 3: SRAM, CCM, and FSMC */
# else
# error "Expected CONFIG_MM_REGIONS to be either 2 (SRAM + FSMC) or 3 (SRAM + CCM + FSMC)!"
# endif
# else
# if (CONFIG_MM_REGIONS == 1)
/* OK: Configuration 1: SRAM only. */
# elif (CONFIG_MM_REGIONS == 2)
/* OK: Configuration 2: SRAM and CCM SRAM. */
# else
# error "Expected CONFIG_MM_REGIONS to be either 1 (SRAM) or 2 (SRAM + CCM)!"
# endif
# endif
/* If FSMC SRAM is going to be used as heap, then verify that the starting
* address and size of the external SRAM region has been provided in the
* configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE).
*/
#ifdef CONFIG_HC32_EXTERNAL_RAM
# if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE)
# error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided"
# undef CONFIG_HC32_EXTERNAL_RAM
# endif
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_heap_color
*
* Description:
* Set heap memory to a known, non-zero state to checking heap usage.
*
****************************************************************************/
#ifdef CONFIG_HEAP_COLORATION
static inline void up_heap_color(FAR void *start, size_t size)
{
memset(start, HEAP_COLOR, size);
}
#else
# define up_heap_color(start,size)
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_heap
*
* Description:
* This function will be called to dynamically set aside the heap region.
*
* For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
* size of the unprotected, user-space heap.
*
* If a protected kernel-space heap is provided, the kernel heap must be
* allocated (and protected) by an analogous up_allocate_kheap().
*
* The following memory map is assumed for the flat build:
*
* .data region. Size determined at link time.
* .bss region Size determined at link time.
* IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
* Heap. Extends to the end of SRAM.
*
* The following memory map is assumed for the kernel build:
*
* Kernel .data region Size determined at link time
* Kernel .bss region Size determined at link time
* Kernel IDLE thread stack Size determined by
* CONFIG_IDLETHREAD_STACKSIZE
* Padding for alignment
* User .data region Size determined at link time
* User .bss region Size determined at link time
* Kernel heap Size determined by
* CONFIG_MM_KERNEL_HEAPSIZE
* User heap Extends to the end of SRAM
*
****************************************************************************/
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = SRAM1_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)SRAM1_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the SRAM1_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
usize = (1 << log2);
ubase = SRAM1_END - usize;
/* Return the user-space heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
/* Colorize the heap for debug */
up_heap_color((FAR void *)ubase, usize);
/* Allow user-mode access to the user heap memory */
hc32_mpu_uheap((uintptr_t)ubase, usize);
#else
/* Return the heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = SRAM1_END - g_idle_topstack;
/* Colorize the heap for debug */
up_heap_color(*heap_start, *heap_size);
#endif
}
/****************************************************************************
* Name: up_allocate_kheap
*
* Description:
* For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates
* (and protects) the kernel-space heap.
*
****************************************************************************/
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
{
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = SRAM1_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)SRAM1_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the SRAM1_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
usize = (1 << log2);
ubase = SRAM1_END - usize;
/* Return the kernel heap settings (i.e., the part of the heap region
* that was not dedicated to the user heap).
*/
*heap_start = (FAR void *)USERSPACE->us_bssend;
*heap_size = ubase - (uintptr_t)USERSPACE->us_bssend;
}
#endif
/****************************************************************************
* Name: arm_addregion
*
* Description:
* Memory may be added in non-contiguous chunks. Additional chunks are
* added by calling this function.
*
****************************************************************************/
#if CONFIG_MM_REGIONS > 1
void arm_addregion(void)
{
#ifndef CONFIG_HC32_CCMEXCLUDE
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the HC32F40xxx CCM SRAM heap */
hc32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START);
#endif
/* Colorize the heap for debug */
up_heap_color((FAR void *)SRAM2_START, SRAM2_END - SRAM2_START);
/* Add the HC32F40xxx CCM SRAM user heap region. */
kumm_addregion((FAR void *)SRAM2_START, SRAM2_END - SRAM2_START);
#endif
#ifdef CONFIG_HC32_EXTERNAL_RAM
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the FSMC SRAM user heap memory */
hc32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
#endif
/* Colorize the heap for debug */
up_heap_color((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
/* Add the external FSMC SRAM user heap region. */
kumm_addregion((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
#endif
}
#endif

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/**
*******************************************************************************
* @file hc32_common.h
* @brief This file contains the common part of the HC32 series.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
2020-09-07 Yangjp Add the precompiled configuration of ARM compiler V6
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_COMMON_H__
#define __HC32_COMMON_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include <stddef.h>
#include <string.h>
//configure the hc32 nuttx adapter
#define HC32F4A0 1
#define USE_DDL_DRIVER 1
#define getreg32(a) (*(volatile uint32_t *)(a))
#define putreg32(v,a) (*(volatile uint32_t *)(a) = (v))
#define getreg16(a) (*(volatile uint16_t *)(a))
#define putreg16(v,a) (*(volatile uint16_t *)(a) = (v))
extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */
extern uint32_t HRC_VALUE; /*!< HRC frequency */
/**
* @brief Clock setup macro definition
*/
#define CLOCK_SETTING_NONE 0U /*!< User provides own clock setting in application */
#define CLOCK_SETTING_CMSIS 1U
#define HRC_FREQ_MON() (*((volatile unsigned int*)(0x40010684UL)))
/**
* @addtogroup HC32F4A0_System_Clock_Source
* @{
*/
#if !defined (HRC_16MHz_VALUE)
#define HRC_16MHz_VALUE ((uint32_t)16000000UL) /*!< Internal high speed RC freq.(16MHz) */
#endif
#if !defined (HRC_20MHz_VALUE)
#define HRC_20MHz_VALUE ((uint32_t)20000000UL) /*!< Internal high speed RC freq.(20MHz) */
#endif
#if !defined (MRC_VALUE)
#define MRC_VALUE ((uint32_t)8000000UL) /*!< Internal middle speed RC freq.(8MHz) */
#endif
#if !defined (LRC_VALUE)
#define LRC_VALUE ((uint32_t)32768UL) /*!< Internal low speed RC freq.(32.768KHz) */
#endif
#if !defined (RTCLRC_VALUE)
#define RTCLRC_VALUE ((uint32_t)32768UL) /*!< Internal RTC low speed RC freq.(32.768KHz) */
#endif
#if !defined (SWDTLRC_VALUE)
#define SWDTLRC_VALUE ((uint32_t)10000UL) /*!< External low speed OSC freq.(10KHz) */
#endif
#if !defined (XTAL_VALUE)
#define XTAL_VALUE ((uint32_t)8000000UL) /*!< External high speed OSC freq.(8MHz) */
#endif
#if !defined (XTAL32_VALUE)
#define XTAL32_VALUE ((uint32_t)32768UL) /*!< External low speed OSC freq.(32.768KHz) */
#endif
#if !defined (HCLK_VALUE)
extern uint32_t SystemCoreClock;
#define HCLK_VALUE (SystemCoreClock >> ((M4_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS))
#endif
#define HC32_SYSCLK_FREQUENCY SystemCoreClock
#define HC32_HCLK_FREQUENCY HCLK_VALUE
/**
* @addtogroup CMSIS
* @{
*/
/**
* @addtogroup HC32_Common_Part
* @{
*/
/**
* @brief HC32 Common Device Include
*/
#include "hc32f4a0.h"
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup HC32_Common_Global_Types HC32 Common Global Types
* @{
*/
/**
* @brief Single precision floating point number (4 byte)
*/
typedef float float32_t;
/**
* @brief Double precision floating point number (8 byte)
*/
typedef double float64_t;
/**
* @brief Function pointer type to void/void function
*/
typedef void (*func_ptr_t)(void);
/**
* @brief Function pointer type to void/uint8_t function
*/
typedef void (*func_ptr_arg1_t)(uint8_t);
/**
* @brief Functional state
*/
typedef enum
{
Disable = 0U,
Enable = 1U,
} en_functional_state_t;
/* Check if it is a functional state */
#define IS_FUNCTIONAL_STATE(state) (((state) == Disable) || ((state) == Enable))
/**
* @brief Flag status
*/
typedef enum
{
Reset = 0U,
Set = 1U,
} en_flag_status_t, en_int_status_t;
/**
* @brief Generic error codes
*/
typedef enum
{
Ok = 0U, /*!< No error */
Error = 1U, /*!< Non-specific error code */
ErrorAddressAlignment = 2U, /*!< Address alignment does not match */
ErrorAccessRights = 3U, /*!< Wrong mode (e.g. user/system) mode is set */
ErrorInvalidParameter = 4U, /*!< Provided parameter is not valid */
ErrorOperationInProgress = 5U, /*!< A conflicting or requested operation is still in progress */
ErrorInvalidMode = 6U, /*!< Operation not allowed in current mode */
ErrorUninitialized = 7U, /*!< Module (or part of it) was not initialized properly */
ErrorBufferEmpty = 8U, /*!< Circular buffer can not be read because the buffer is empty */
ErrorBufferFull = 9U, /*!< Circular buffer can not be written because the buffer is full */
ErrorTimeout = 10U, /*!< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) */
ErrorNotReady = 11U, /*!< A requested final state is not reached */
OperationInProgress = 12U, /*!< Indicator for operation in progress (e.g. ADC conversion not finished, DMA channel used, etc.) */
} en_result_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup HC32_Common_Global_Macros HC32 Common Global Macros
* @{
*/
/**
* @brief Compiler Macro Definitions
*/
#ifndef __UNUSED
#define __UNUSED __attribute__((unused))
#endif /* __UNUSED */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#ifndef __WEAKDEF
#define __WEAKDEF __attribute__((weak))
#endif /* __WEAKDEF */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN __attribute__((aligned(4)))
#endif /* __ALIGN_BEGIN */
#ifndef __NOINLINE
#define __NOINLINE __attribute__((noinline))
#endif /* __NOINLINE */
#ifndef __RAM_FUNC
#define __RAM_FUNC __attribute__((long_call, section(".ramfunc")))
/* Usage: void __RAM_FUNC foo(void) */
#endif /* __RAM_FUNC */
#ifndef __NO_INIT
#define __NO_INIT
#endif /* __NO_INIT */
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /*!< GNU Compiler */
#ifndef __WEAKDEF
#define __WEAKDEF __attribute__((weak))
#endif /* __WEAKDEF */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN __attribute__((aligned (4)))
#endif /* __ALIGN_BEGIN */
#ifndef __NOINLINE
#define __NOINLINE __attribute__((noinline))
#endif /* __NOINLINE */
#ifndef __RAM_FUNC
#define __RAM_FUNC __attribute__((long_call, section(".ramfunc")))
/* Usage: void __RAM_FUNC foo(void) */
#endif /* __RAM_FUNC */
#ifndef __NO_INIT
#define __NO_INIT __attribute__((section(".noinit")))
#endif /* __NO_INIT */
#elif defined (__ICCARM__) /*!< IAR Compiler */
#ifndef __WEAKDEF
#define __WEAKDEF __weak
#endif /* __WEAKDEF */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN _Pragma("data_alignment=4")
#endif /* __ALIGN_BEGIN */
#ifndef __NOINLINE
#define __NOINLINE _Pragma("optimize = no_inline")
#endif /* __NOINLINE */
#ifndef __RAM_FUNC
#define __RAM_FUNC __ramfunc
#endif /* __RAM_FUNC */
#ifndef __NO_INIT
#define __NO_INIT __no_init
#endif /* __NO_INIT */
#elif defined (__CC_ARM) /*!< ARM Compiler */
#ifndef __WEAKDEF
#define __WEAKDEF __attribute__((weak))
#endif /* __WEAKDEF */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN __align(4)
#endif /* __ALIGN_BEGIN */
#ifndef __NOINLINE
#define __NOINLINE __attribute__((noinline))
#endif /* __NOINLINE */
#ifndef __NO_INIT
#define __NO_INIT
#endif /* __NO_INIT */
/* RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM. */
#define __RAM_FUNC
#else
#error "unsupported compiler!!"
#endif
/**
* @defgroup Extend_Macro_Definitions Extend Macro Definitions
* @{
*/
/* Decimal to BCD */
#define DEC2BCD(x) ((((x) / 10U) << 4U) + ((x) % 10U))
/* BCD to decimal */
#define BCD2DEC(x) ((((x) >> 4U) * 10U) + ((x) & 0x0FU))
/* Returns the minimum value out of two values */
#define MIN(x, y) ((x) < (y) ? (x) : (y))
/* Returns the maximum value out of two values */
#define MAX(x, y) ((x) > (y) ? (x) : (y))
/* Returns the dimension of an array */
#define ARRAY_SZ(x) ((sizeof(x)) / (sizeof((x)[0])))
/**
* @}
*/
/**
* @defgroup Address_Align Address Align
* @{
*/
#define IS_ADDRESS_ALIGN(addr, align) (0UL == (((uint32_t)(addr)) & (((uint32_t)(align)) - 1UL)))
#define IS_ADDRESS_ALIGN_HALFWORD(addr) (0UL == (((uint32_t)(addr)) & 0x1UL))
#define IS_ADDRESS_ALIGN_WORD(addr) (0UL == (((uint32_t)(addr)) & 0x3UL))
/**
* @}
*/
/**
* @defgroup Register_Macro_Definitions Register Macro Definitions
* @{
*/
#define RW_MEM8(addr) (*(volatile uint8_t *)(addr))
#define RW_MEM16(addr) (*(volatile uint16_t *)(addr))
#define RW_MEM32(addr) (*(volatile uint32_t *)(addr))
#define SET_REG8_BIT(REG, BIT) ((REG) |= ((uint8_t)(BIT)))
#define SET_REG16_BIT(REG, BIT) ((REG) |= ((uint16_t)(BIT)))
#define SET_REG32_BIT(REG, BIT) ((REG) |= ((uint32_t)(BIT)))
#define CLEAR_REG8_BIT(REG, BIT) ((REG) &= ((uint8_t)(~((uint8_t)(BIT)))))
#define CLEAR_REG16_BIT(REG, BIT) ((REG) &= ((uint16_t)(~((uint16_t)(BIT)))))
#define CLEAR_REG32_BIT(REG, BIT) ((REG) &= ((uint32_t)(~((uint32_t)(BIT)))))
#define READ_REG8_BIT(REG, BIT) ((REG) & ((uint8_t)(BIT)))
#define READ_REG16_BIT(REG, BIT) ((REG) & ((uint16_t)(BIT)))
#define READ_REG32_BIT(REG, BIT) ((REG) & ((uint32_t)(BIT)))
#define CLEAR_REG8(REG) ((REG) = ((uint8_t)(0U)))
#define CLEAR_REG16(REG) ((REG) = ((uint16_t)(0U)))
#define CLEAR_REG32(REG) ((REG) = ((uint32_t)(0UL)))
#define WRITE_REG8(REG, VAL) ((REG) = ((uint8_t)(VAL)))
#define WRITE_REG16(REG, VAL) ((REG) = ((uint16_t)(VAL)))
#define WRITE_REG32(REG, VAL) ((REG) = ((uint32_t)(VAL)))
#define READ_REG8(REG) (REG)
#define READ_REG16(REG) (REG)
#define READ_REG32(REG) (REG)
#define MODIFY_REG8(REGS, CLEARMASK, SETMASK) (WRITE_REG8((REGS), (((READ_REG8((REGS))) & ((uint8_t)(~((uint8_t)(CLEARMASK))))) | ((uint8_t)(SETMASK) & (uint8_t)(CLEARMASK)))))
#define MODIFY_REG16(REGS, CLEARMASK, SETMASK) (WRITE_REG16((REGS), (((READ_REG16((REGS))) & ((uint16_t)(~((uint16_t)(CLEARMASK))))) | ((uint16_t)(SETMASK) & (uint16_t)(CLEARMASK)))))
#define MODIFY_REG32(REGS, CLEARMASK, SETMASK) (WRITE_REG32((REGS), (((READ_REG32((REGS))) & ((uint32_t)(~((uint32_t)(CLEARMASK))))) | ((uint32_t)(SETMASK) & (uint32_t)(CLEARMASK)))))
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_COMMON_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ddl.h
* @brief This file contains HC32 Series Device Driver Library file call
* management.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_DDL_H__
#define __HC32_DDL_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/* Defined use Device Driver Library */
#if !defined (USE_DDL_DRIVER)
/**
* @brief Comment the line below if you will not use the Device Driver Library.
* In this case, the application code will be based on direct access to
* peripherals registers.
*/
/* #define USE_DDL_DRIVER */
#endif /* USE_DDL_DRIVER */
/**
* @brief HC32 Series Device Driver Library version number
*/
#define HC32_DDL_VERSION_MAIN 0x01U /*!< [31:24] main version */
#define HC32_DDL_VERSION_SUB1 0x04U /*!< [23:16] sub1 version */
#define HC32_DDL_VERSION_SUB2 0x00U /*!< [15:8] sub2 version */
#define HC32_DDL_VERSION_RC 0x00U /*!< [7:0] release candidate */
#define HC32_DDL_VERSION ((HC32_DDL_VERSION_MAIN << 24) | \
(HC32_DDL_VERSION_SUB1 << 16) | \
(HC32_DDL_VERSION_SUB2 << 8 ) | \
(HC32_DDL_VERSION_RC))
/* Use Device Driver Library */
#if defined (USE_DDL_DRIVER)
/**
* @brief Include peripheral module's header file
*/
#if (DDL_ADC_ENABLE == DDL_ON)
#include "hc32f4a0_adc.h"
#endif /* DDL_ADC_ENABLE */
#if (DDL_AES_ENABLE == DDL_ON)
#include "hc32f4a0_aes.h"
#endif /* DDL_AES_ENABLE */
#if (DDL_CAN_ENABLE == DDL_ON)
#include "hc32f4a0_can.h"
#endif /* DDL_CAN_ENABLE */
#if (DDL_CLK_ENABLE == DDL_ON)
#include "hc32f4a0_clk.h"
#endif /* DDL_CLK_ENABLE */
#if (DDL_CMP_ENABLE == DDL_ON)
#include "hc32f4a0_cmp.h"
#endif /* DDL_CMP_ENABLE */
#if (DDL_CRC_ENABLE == DDL_ON)
#include "hc32f4a0_crc.h"
#endif /* DDL_CRC_ENABLE */
#if (DDL_CTC_ENABLE == DDL_ON)
#include "hc32f4a0_ctc.h"
#endif /* DDL_CTC_ENABLE */
#if (DDL_DAC_ENABLE == DDL_ON)
#include "hc32f4a0_dac.h"
#endif /* DDL_DAC_ENABLE */
#if (DDL_DCU_ENABLE == DDL_ON)
#include "hc32f4a0_dcu.h"
#endif /* DDL_DCU_ENABLE */
#if (DDL_DMA_ENABLE == DDL_ON)
#include "hc32f4a0_dma.h"
#endif /* DDL_DMA_ENABLE */
#if (DDL_DMC_ENABLE == DDL_ON)
#include "hc32f4a0_dmc.h"
#endif /* DDL_DMC_ENABLE */
#if (DDL_DVP_ENABLE == DDL_ON)
#include "hc32f4a0_dvp.h"
#endif /* DDL_DVP_ENABLE */
#if (DDL_EFM_ENABLE == DDL_ON)
#include "hc32f4a0_efm.h"
#endif /* DDL_EFM_ENABLE */
#if (DDL_EMB_ENABLE == DDL_ON)
#include "hc32f4a0_emb.h"
#endif /* DDL_EMB_ENABLE */
#if (DDL_ETH_ENABLE == DDL_ON)
#include "hc32f4a0_eth.h"
#endif /* DDL_ETH_ENABLE */
#if (DDL_EVENT_PORT_ENABLE == DDL_ON)
#include "hc32f4a0_event_port.h"
#endif /* DDL_EVENT_PORT_ENABLE */
#if (DDL_FCM_ENABLE == DDL_ON)
#include "hc32f4a0_fcm.h"
#endif /* DDL_FCM_ENABLE */
#if (DDL_FMAC_ENABLE == DDL_ON)
#include "hc32f4a0_fmac.h"
#endif /* DDL_FMAC_ENABLE */
#if (DDL_GPIO_ENABLE == DDL_ON)
#include "hc32f4a0_gpio.h"
#endif /* DDL_GPIO_ENABLE */
#if (DDL_HASH_ENABLE == DDL_ON)
#include "hc32f4a0_hash.h"
#endif /* DDL_HASH_ENABLE */
#if (DDL_I2C_ENABLE == DDL_ON)
#include "hc32f4a0_i2c.h"
#endif /* DDL_I2C_ENABLE */
#if (DDL_I2S_ENABLE == DDL_ON)
#include "hc32f4a0_i2s.h"
#endif /* DDL_I2S_ENABLE */
#if (DDL_ICG_ENABLE == DDL_ON)
#include "hc32f4a0_icg.h"
#endif /* DDL_ICG_ENABLE */
#if (DDL_INTERRUPTS_ENABLE == DDL_ON)
#include "hc32f4a0_interrupts.h"
#endif /* DDL_INTERRUPTS_ENABLE */
#if (DDL_KEYSCAN_ENABLE == DDL_ON)
#include "hc32f4a0_keyscan.h"
#endif /* DDL_KEYSCAN_ENABLE */
#if (DDL_MAU_ENABLE == DDL_ON)
#include "hc32f4a0_mau.h"
#endif /* DDL_MAU_ENABLE */
#if (DDL_MPU_ENABLE == DDL_ON)
#include "hc32f4a0_mpu.h"
#endif /* DDL_MPU_ENABLE */
#if (DDL_NFC_ENABLE == DDL_ON)
#include "hc32f4a0_nfc.h"
#endif /* DDL_NFC_ENABLE */
#if (DDL_OTS_ENABLE == DDL_ON)
#include "hc32f4a0_ots.h"
#endif /* DDL_OTS_ENABLE */
#if (DDL_PWC_ENABLE == DDL_ON)
#include "hc32f4a0_pwc.h"
#endif /* DDL_PWC_ENABLE */
#if (DDL_QSPI_ENABLE == DDL_ON)
#include "hc32f4a0_qspi.h"
#endif /* DDL_QSPI_ENABLE */
#if (DDL_RMU_ENABLE == DDL_ON)
#include "hc32f4a0_rmu.h"
#endif /* DDL_RMU_ENABLE */
#if (DDL_RTC_ENABLE == DDL_ON)
#include "hc32f4a0_rtc.h"
#endif /* DDL_RTC_ENABLE */
#if (DDL_SDIOC_ENABLE == DDL_ON)
#include "hc32f4a0_sdioc.h"
#endif /* DDL_SDIOC_ENABLE */
#if (DDL_SMC_ENABLE == DDL_ON)
#include "hc32f4a0_smc.h"
#endif /* DDL_SMC_ENABLE */
#if (DDL_SPI_ENABLE == DDL_ON)
#include "hc32f4a0_spi.h"
#endif /* DDL_SPI_ENABLE */
#if (DDL_SRAM_ENABLE == DDL_ON)
#include "hc32f4a0_sram.h"
#endif /* DDL_SRAM_ENABLE */
#if (DDL_SWDT_ENABLE == DDL_ON)
#include "hc32f4a0_swdt.h"
#endif /* DDL_SWDT_ENABLE */
#if (DDL_TMR0_ENABLE == DDL_ON)
#include "hc32f4a0_tmr0.h"
#endif /* DDL_TMR0_ENABLE */
#if (DDL_TMR2_ENABLE == DDL_ON)
#include "hc32f4a0_tmr2.h"
#endif /* DDL_TMR2_ENABLE */
#if (DDL_TMR4_ENABLE == DDL_ON)
#include "hc32f4a0_tmr4.h"
#endif /* DDL_TMR4_ENABLE */
#if (DDL_TMR6_ENABLE == DDL_ON)
#include "hc32f4a0_tmr6.h"
#endif /* DDL_TMR6_ENABLE */
#if (DDL_TMRA_ENABLE == DDL_ON)
#include "hc32f4a0_tmra.h"
#endif /* DDL_TMRA_ENABLE */
#if (DDL_TRNG_ENABLE == DDL_ON)
#include "hc32f4a0_trng.h"
#endif /* DDL_TRNG_ENABLE */
#if (DDL_USART_ENABLE == DDL_ON)
#include "hc32f4a0_usart.h"
#endif /* DDL_USART_ENABLE */
#if (DDL_USBFS_ENABLE == DDL_ON)
#include "hc32f4a0_usbfs.h"
#endif /* DDL_USBFS_ENABLE */
#if (DDL_USBHS_ENABLE == DDL_ON)
#include "hc32f4a0_usbhs.h"
#endif /* DDL_USBHS_ENABLE */
#if (DDL_UTILITY_ENABLE == DDL_ON)
#include "hc32f4a0_utility.h"
#endif /* DDL_UTILITY_ENABLE */
#if (DDL_WDT_ENABLE == DDL_ON)
#include "hc32f4a0_wdt.h"
#endif /* DDL_WDT_ENABLE */
#if (DDL_HRPWM_ENABLE == DDL_ON)
#include "hc32f4a0_hrpwm.h"
#endif /* DDL_HRPWM_ENABLE */
/**
* @brief Include BSP board's header file
*/
/**
* @brief Include BSP device component's header file
*/
#if (BSP_CY62167EV30LL_ENABLE == BSP_ON)
#include "cy62167ev30ll.h"
#endif /* BSP_CY62167EV30LL_ENABLE */
#if (BSP_IS42S16400J7TLI_ENABLE == BSP_ON)
#include "is42s16400j7tli.h"
#endif /* BSP_IS42S16400J7TLI_ENABLE */
#if (BSP_IS62WV51216_ENABLE == BSP_ON)
#include "is62wv51216.h"
#endif /* BSP_IS62WV51216_ENABLE */
#if (BSP_MT29F2G08AB_ENABLE == BSP_ON)
#include "mt29f2g08ab.h"
#endif /* BSP_MT29F2G08AB_ENABLE */
#if (BSP_NT35510_ENABLE == BSP_ON)
#include "nt35510.h"
#endif /* BSP_NT35510_ENABLE */
#if (BSP_OV5640_ENABLE == BSP_ON)
#include "ov5640.h"
#endif /* BSP_OV5640_ENABLE */
#if (BSP_S29GL064N90TFI03_ENABLE == BSP_ON)
#include "s29gl064n90tfi03.h"
#endif /* BSP_S29GL064N90TFI03_ENABLE */
//#if (BSP_TCA9539_ENABLE == BSP_ON)
// #include "ev_hc32f4a0_lqfp176_tca9539.h"
// #include "tca9539.h"
//#endif /* BSP_TCA9539_ENABLE */
#if (BSP_W25QXX_ENABLE == BSP_ON)
#include "w25qxx.h"
#endif /* BSP_W25QXX_ENABLE */
#if (BSP_WM8731_ENABLE == BSP_ON)
#include "wm8731.h"
#endif /* BSP_WM8731_ENABLE */
#endif /* USE_DDL_DRIVER */
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_DDL_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/****************************************************************************
* arch/arm/src/hc32/hc32_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include "arm_internal.h"
#include "chip.h"
#include <arch/board/board.h>
#include "hc32_gpio.h"
#include "hc32f4a0_gpio.h"
#include "hc32f4a0_utility.h"
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
void hc32_gpio_flick(void)
{
uint32_t pinset = (GPIO_PINSET(LED_GREEN_PORT, LED_GREEN_PIN) | GPIO_OUTPUT_SET);
hc32_configgpio(pinset);
for(int i = 0; i < 3; i++)
{
hc32_gpiowrite(pinset, true);
DDL_DelayMS(200UL);
hc32_gpiowrite(pinset, false);
DDL_DelayMS(200UL);
}
}
/****************************************************************************
* Function: hc32_gpioremap
*
* Description:
*
* Based on configuration within the .config file, this function will
* remaps positions of alternative functions.
*
****************************************************************************/
static inline void hc32_gpioremap(void)
{
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: hc32_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from hc32_start().
*
* Assumptions:
* This function is called early in the initialization sequence so that
* no mutual exclusion is necessary.
*
****************************************************************************/
void hc32_gpioinit(void)
{
/* Remap according to the configuration within .config file */
hc32_gpioremap();
hc32_gpio_flick();
}
/****************************************************************************
* Name: hc32_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with hc32_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
* Returned Value:
* OK on success
* A negated errno value on invalid port, or when pin is locked as ALT
* function.
*
* To-Do: Auto Power Enable
****************************************************************************/
/****************************************************************************
* Name: hc32_configgpio (for the HC32F10xxx family)
****************************************************************************/
int hc32_configgpio(uint32_t cfgset)
{
unsigned int port;
unsigned int pin;
irqstate_t flags;
stc_gpio_init_t stcGpioInit;
/* Verify that this hardware supports the select GPIO port */
port = (cfgset >> GPIO_PORT_SHIFT) & GPIO_PORT_MASK;
if (port > GPIO_PORT_MASK)
{
return -EINVAL;
}
/* Get the pin number and select the port configuration register for that pin */
pin = (cfgset >> GPIO_PIN_SHIFT) & GPIO_PIN_MASK;
/* Interrupts must be disabled from here on out so that we have mutually
* exclusive access to all of the GPIO configuration registers.
*/
flags = enter_critical_section();
/* If it is an output... set the pin to the correct initial state.
* If it is pull-down or pull up, then we need to set the ODR
* appropriately for that function.
*/
GPIO_Unlock();
/* LED initialize */
(void)GPIO_StructInit(&stcGpioInit);
(void)GPIO_Init(port, pin, &stcGpioInit);
GPIO_Lock();
/* Register write protected for some required peripherals. */
if ((cfgset & GPIO_OUTPUT_SET) != 0)
{
/* "Turn off" LED before set to output */
GPIO_ResetPins(port, pin);
GPIO_OE(port, pin, Enable);
}
else
{
GPIO_OE(port, pin, Disable);
}
leave_critical_section(flags);
return OK;
}
/****************************************************************************
* Name: hc32_unconfiggpio
*
* Description:
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
* it into default HiZ state (and possibly mark it's unused) and unlock it
* whether it was previously selected as an alternative function
* (GPIO_ALT | GPIO_CNF_AFPP | ...).
*
* This is a safety function and prevents hardware from shocks, as
* unexpected write to the Timer Channel Output GPIO to fixed '1' or '0'
* while it should operate in PWM mode could produce excessive on-board
* currents and trigger over-current/alarm function.
*
* Returned Value:
* OK on success
* A negated errno value on invalid port
*
* To-Do: Auto Power Disable
****************************************************************************/
int hc32_unconfiggpio(uint32_t cfgset)
{
/* Reuse port and pin number and set it to default HiZ INPUT */
cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK;
cfgset |= GPIO_INPUT;
return hc32_configgpio(cfgset);
}
/****************************************************************************
* Name: hc32_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void hc32_gpiowrite(uint32_t pinset, bool value)
{
unsigned int port;
unsigned int pin;
port = (pinset >> GPIO_PORT_SHIFT) & GPIO_PORT_MASK;
if (port < GPIO_PORT_MASK)
{
/* Get the pin number */
pin = (pinset >> GPIO_PIN_SHIFT) & GPIO_PIN_MASK;
/* Set or clear the output on the pin */
if (value)
{
GPIO_SetPins(port, pin);
}
else
{
GPIO_ResetPins(port, pin);
}
}
}
/****************************************************************************
* Name: hc32_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool hc32_gpioread(uint32_t pinset)
{
unsigned int port;
unsigned int pin;
port = (pinset >> GPIO_PORT_SHIFT) & GPIO_PORT_MASK;
if (port < GPIO_PORT_MASK)
{
/* Get the pin number and return the input state of that pin */
pin = (pinset >> GPIO_PIN_SHIFT) & GPIO_PIN_MASK;
return (GPIO_ReadInputPins(port, pin) == Pin_Set);
}
return 0;
}
/****************************************************************************
* Name: hc32_iocompensation
*
* Description:
* Enable I/O compensation.
*
* By default the I/O compensation cell is not used. However when the I/O
* output buffer speed is configured in 50 MHz or 100 MHz mode, it is
* recommended to use the compensation cell for slew rate control on I/O
* tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power
* supply.
*
* The I/O compensation cell can be used only when the supply voltage
* ranges from 2.4 to 3.6 V.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_HC32_HAVE_IOCOMPENSATION
void hc32_iocompensation(void)
{
#ifdef HC32_SYSCFG_CMPCR
/* Enable I/O Compensation. Writing '1' to the CMPCR power-down bit
* enables the I/O compensation cell.
*/
#endif
}
#endif

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/****************************************************************************
* arch/arm/src/hc32/hc32_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_HC32_HC32_GPIO_H
#define __ARCH_ARM_SRC_HC32_HC32_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
# include <stdbool.h>
#endif
#include <nuttx/irq.h>
#include "chip.h"
/****************************************************************************
* Pre-Processor Declarations
****************************************************************************/
#define GPIO_OUTPUT_SET (1 << 25) /* Bit 8: If output, initial value of output */
#define GPIO_OUTPUT_CLEAR (0)
#define GPIO_MODE_SHIFT (18) /* Bits 18-19: GPIO port mode */
#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode */
# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* General purpose output mode */
# define GPIO_ALT (2 << GPIO_MODE_SHIFT) /* Alternate function mode */
# define GPIO_ANALOG (3 << GPIO_MODE_SHIFT) /* Analog mode */
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: hc32_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with hc32_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
* Returned Value:
* OK on success
* ERROR on invalid port, or when pin is locked as ALT function.
*
****************************************************************************/
int hc32_configgpio(uint32_t cfgset);
/****************************************************************************
* Name: hc32_unconfiggpio
*
* Description:
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
* it into default HiZ state (and possibly mark it's unused) and unlock it
* whether it was previously selected as alternative function
* (GPIO_ALT|GPIO_CNF_AFPP|...).
*
* This is a safety function and prevents hardware from shocks, as
* unexpected write to the Timer Channel Output GPIO to fixed '1' or '0'
* while it should operate in PWM mode could produce excessive on-board
* currents and trigger over-current/alarm function.
*
* Returned Value:
* OK on success
* ERROR on invalid port
*
****************************************************************************/
int hc32_unconfiggpio(uint32_t cfgset);
/****************************************************************************
* Name: hc32_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void hc32_gpiowrite(uint32_t pinset, bool value);
/****************************************************************************
* Name: hc32_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool hc32_gpioread(uint32_t pinset);
/****************************************************************************
* Name: hc32_iocompensation
*
* Description:
* Enable I/O compensation.
*
* By default the I/O compensation cell is not used. However when the I/O
* output buffer speed is configured in 50 MHz or 100 MHz mode, it is
* recommended to use the compensation cell for slew rate control on I/O
* tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power
* supply.
*
* The I/O compensation cell can be used only when the supply voltage
* ranges from 2.4 to 3.6 V.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_HC32_HAVE_IOCOMPENSATION
void hc32_iocompensation(void);
#endif
/****************************************************************************
* Function: hc32_dumpgpio
*
* Description:
* Dump all GPIO registers associated with the provided base address
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
int hc32_dumpgpio(uint32_t pinset, const char *msg);
#else
# define hc32_dumpgpio(p,m)
#endif
/****************************************************************************
* Function: hc32_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from hc32_start().
*
****************************************************************************/
void hc32_gpioinit(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_HC32_HC32_GPIO_H */

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/****************************************************************************
* arch/arm/src/hc32/hc32_idle.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/board/board.h>
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/power/pm.h>
#include <nuttx/irq.h>
#include "chip.h"
#include "hc32_pm.h"
#include "arm_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Does the board support an IDLE LED to indicate that the board is in the
* IDLE state?
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
#endif
#define PM_IDLE_DOMAIN 0 /* Revisit */
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_idlepm
*
* Description:
* Perform IDLE state power management.
*
****************************************************************************/
#ifdef CONFIG_PM
static void up_idlepm(void)
{
static enum pm_state_e oldstate = PM_NORMAL;
enum pm_state_e newstate;
irqstate_t flags;
int ret;
/* Decide, which power saving level can be obtained */
newstate = pm_checkstate(PM_IDLE_DOMAIN);
/* Check for state changes */
if (newstate != oldstate)
{
flags = enter_critical_section();
/* Perform board-specific, state-dependent logic here */
_info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
ret = pm_changestate(PM_IDLE_DOMAIN, newstate);
if (ret < 0)
{
/* The new state change failed, revert to the preceding state */
pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
/* Save the new state */
oldstate = newstate;
}
/* MCU-specific power management logic */
switch (newstate)
{
case PM_NORMAL:
break;
case PM_IDLE:
break;
case PM_STANDBY:
// hc32_pmstop(true);
break;
case PM_SLEEP:
// hc32_pmstandby();
break;
default:
break;
}
leave_critical_section(flags);
}
}
#else
# define up_idlepm()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when there is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
nxsched_process_timer();
#else
/* Perform IDLE mode power management */
up_idlepm();
/* Sleep until an interrupt occurs to save power.
*
* NOTE: There is an HC32F107 errata that is fixed by the following
* workaround:
*
* "2.17.11 Ethernet DMA not working after WFI/WFE instruction
* Description
* If a WFI/WFE instruction is executed to put the system in sleep mode
* while the Ethernet MAC master clock on the AHB bus matrix is ON and
* all remaining masters clocks are OFF, the Ethernet DMA will be not
* able to perform any AHB master accesses during sleep mode."
*
* Workaround
* Enable DMA1 or DMA2 clocks in the RCC_AHBENR register before
* executing the WFI/WFE instruction."
*
* Here the workaround is just to avoid SLEEP mode for the connectivity
* line parts if Ethernet is enabled. The errate recommends a more
* general solution: Enabling DMA1/2 clocking in hc32f10xx_rcc.c if the
* HC32107 Ethernet peripheral is enabled.
*/
#if !defined(CONFIG_HC32_CONNECTIVITYLINE) || !defined(CONFIG_HC32_ETHMAC)
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_HC32_DISABLE_IDLE_SLEEP_DURING_DEBUG))
BEGIN_IDLE();
asm("WFI");
END_IDLE();
#endif
#endif
#endif
}

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/****************************************************************************
* arch/arm/src/hc32/hc32_irq.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <inttypes.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
#include "nvic.h"
#ifdef CONFIG_ARCH_RAMVECTORS
# include "ram_vectors.h"
#endif
#include "arm_internal.h"
#include "hc32f4a0.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Get a 32-bit version of the default priority */
#define DEFPRIORITY32 \
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | \
NVIC_SYSH_PRIORITY_DEFAULT)
/* Given the address of a NVIC ENABLE register, this is the offset to
* the corresponding CLEAR ENABLE register.
*/
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Public Data
****************************************************************************/
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
volatile uint32_t *g_current_regs[1];
/* This is the address of the exception vector table (determined by the
* linker script).
*/
#if defined(__ICCARM__)
/* _vectors replaced on __vector_table for IAR C-SPY Simulator */
extern uint32_t __vector_table[];
#else
extern uint32_t _vectors[];
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: hc32_dumpnvic
*
* Description:
* Dump some interesting NVIC registers
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void hc32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x "
"SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA),
getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA),
getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE),
getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY),
getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY),
getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY),
getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY),
getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY),
getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY),
getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY),
getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY),
getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY),
getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
leave_critical_section(flags);
}
#else
# define hc32_dumpnvic(msg, irq)
#endif
/****************************************************************************
* Name: hc32_nmi, hc32_busfault, hc32_usagefault, hc32_pendsv,
* hc32_dbgmonitor, hc32_pendsv, hc32_reserved
*
* Description:
* Handlers for various exceptions. None are handled and all are fatal
* error conditions. The only advantage these provided over the default
* unexpected interrupt handler is that they provide a diagnostic output.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
static int hc32_nmi(int irq, FAR void *context, FAR void *arg)
{
up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
static int hc32_busfault(int irq, FAR void *context, FAR void *arg)
{
up_irq_save();
_err("PANIC!!! Bus fault received: %08" PRIx32 "\n",
getreg32(NVIC_CFAULTS));
PANIC();
return 0;
}
static int hc32_usagefault(int irq, FAR void *context, FAR void *arg)
{
up_irq_save();
_err("PANIC!!! Usage fault received: %08" PRIx32 "\n",
getreg32(NVIC_CFAULTS));
PANIC();
return 0;
}
static int hc32_pendsv(int irq, FAR void *context, FAR void *arg)
{
up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
static int hc32_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
}
static int hc32_reserved(int irq, FAR void *context, FAR void *arg)
{
up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
#endif
/****************************************************************************
* Name: hc32_prioritize_syscall
*
* Description:
* Set the priority of an exception. This function may be needed
* internally even if support for prioritized interrupts is not enabled.
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_USEBASEPRI
static inline void hc32_prioritize_syscall(int priority)
{
uint32_t regval;
/* SVCALL is system handler 11 */
regval = getreg32(NVIC_SYSH8_11_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK;
regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
putreg32(regval, NVIC_SYSH8_11_PRIORITY);
}
#endif
/****************************************************************************
* Name: hc32_irqinfo
*
* Description:
* Given an IRQ number, provide the register and bit setting to enable or
* disable the irq.
*
****************************************************************************/
static int hc32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
int n;
DEBUGASSERT(irq >= HC32_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= HC32_IRQ_FIRST)
{
n = irq - HC32_IRQ_FIRST;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
*bit = (uint32_t)1 << (n & 0x1f);
}
/* Handle processor exceptions. Only a few can be disabled */
else
{
*regaddr = NVIC_SYSHCON;
if (irq == HC32_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
else if (irq == HC32_IRQ_BUSFAULT)
{
*bit = NVIC_SYSHCON_BUSFAULTENA;
}
else if (irq == HC32_IRQ_USAGEFAULT)
{
*bit = NVIC_SYSHCON_USGFAULTENA;
}
else if (irq == HC32_IRQ_SYSTICK)
{
*regaddr = NVIC_SYSTICK_CTRL;
*bit = NVIC_SYSTICK_CTRL_ENABLE;
}
else
{
return ERROR; /* Invalid or unsupported exception */
}
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
uint32_t regaddr;
int num_priority_registers;
int i;
/* Disable all interrupts */
for (i = 0; i < NR_IRQS - HC32_IRQ_FIRST; i += 32)
{
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
/* The standard location for the vector table is at the beginning of FLASH
* at address 0x0800:0000. If we are using the STMicro DFU bootloader,
* then the vector table will be offset to a different location in FLASH
* and we will need to set the NVIC vector location to this alternative
* location.
*/
#if defined(__ICCARM__)
putreg32((uint32_t)__vector_table, NVIC_VECTAB);
#else
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#endif
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
arm_ramvec_initialize();
#endif
/* Set all interrupts (and exceptions) to the default priority */
putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
/* The NVIC ICTR register (bits 0-4) holds the number of interrupt
* lines that the NVIC supports:
*
* 0 -> 32 interrupt lines, 8 priority registers
* 1 -> 64 " " " ", 16 priority registers
* 2 -> 96 " " " ", 32 priority registers
* ...
*/
num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8;
/* Now set all of the interrupt lines to the default priority */
regaddr = NVIC_IRQ0_3_PRIORITY;
while (num_priority_registers--)
{
putreg32(DEFPRIORITY32, regaddr);
regaddr += 4;
}
/* currents_regs is non-NULL only while processing an interrupt */
CURRENT_REGS = NULL;
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
* exception is used for performing context switches; The Hard Fault
* must also be caught because a SVCall may show up as a Hard Fault
* under certain conditions.
*/
irq_attach(HC32_IRQ_SVCALL, arm_svcall, NULL);
irq_attach(HC32_IRQ_HARDFAULT, arm_hardfault, NULL);
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(HC32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
hc32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
#endif
/* If the MPU is enabled, then attach and enable the Memory Management
* Fault handler.
*/
#ifdef CONFIG_ARM_MPU
irq_attach(HC32_IRQ_MEMFAULT, arm_memfault, NULL);
up_enable_irq(HC32_IRQ_MEMFAULT);
#endif
#if defined(CONFIG_RTC) && !defined(CONFIG_RTC_EXTERNAL)
/* RTC was initialized earlier but IRQs weren't ready at that time */
hc32_rtc_irqinitialize();
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG_FEATURES
irq_attach(HC32_IRQ_NMI, hc32_nmi, NULL);
#ifndef CONFIG_ARM_MPU
irq_attach(HC32_IRQ_MEMFAULT, arm_memfault, NULL);
#endif
irq_attach(HC32_IRQ_BUSFAULT, hc32_busfault, NULL);
irq_attach(HC32_IRQ_USAGEFAULT, hc32_usagefault, NULL);
irq_attach(HC32_IRQ_PENDSV, hc32_pendsv, NULL);
irq_attach(HC32_IRQ_DBGMONITOR, hc32_dbgmonitor, NULL);
irq_attach(HC32_IRQ_RESERVED, hc32_reserved, NULL);
#endif
hc32_dumpnvic("initial", NR_IRQS);
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts */
up_irq_enable();
#endif
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
****************************************************************************/
void up_disable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (hc32_irqinfo(irq, &regaddr, &bit, NVIC_CLRENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to disable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Clear Enable register. For other exceptions, we need to
* clear the bit in the System Handler Control and State Register.
*/
if (irq >= HC32_IRQ_FIRST)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval &= ~bit;
putreg32(regval, regaddr);
}
}
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'
*
****************************************************************************/
void up_enable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (hc32_irqinfo(irq, &regaddr, &bit, NVIC_ENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to enable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Set Enable register. For other exceptions, we need to
* set the bit in the System Handler Control and State Register.
*/
if (irq >= HC32_IRQ_FIRST)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval |= bit;
putreg32(regval, regaddr);
}
}
}
/****************************************************************************
* Name: arm_ack_irq
*
* Description:
* Acknowledge the IRQ
*
****************************************************************************/
void arm_ack_irq(int irq)
{
}
/****************************************************************************
* Name: up_prioritize_irq
*
* Description:
* Set the priority of an IRQ.
*
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
****************************************************************************/
#ifdef CONFIG_ARCH_IRQPRIO
int up_prioritize_irq(int irq, int priority)
{
uint32_t regaddr;
uint32_t regval;
int shift;
DEBUGASSERT(irq >= HC32_IRQ_MEMFAULT && irq < NR_IRQS &&
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < HC32_IRQ_FIRST)
{
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
* registers (0-3 are invalid)
*/
regaddr = NVIC_SYSH_PRIORITY(irq);
irq -= 4;
}
else
{
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
irq -= HC32_IRQ_FIRST;
regaddr = NVIC_IRQ_PRIORITY(irq);
}
regval = getreg32(regaddr);
shift = ((irq & 3) << 3);
regval &= ~(0xff << shift);
regval |= (priority << shift);
putreg32(regval, regaddr);
hc32_dumpnvic("prioritize", irq);
return OK;
}
#endif

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/****************************************************************************
* arch/arm/src/hc32/hc32_lowputc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "chip.h"
#include "hc32_rcc.h"
#include "hc32_gpio.h"
#include "hc32_uart.h"
#include "hc32_lowputc.h"
#include "hc32f4a0_usart.h"
#include "hc32_ddl.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* UART multiple processor ID definition */
#define UART_MASTER_STATION_ID (0x20U)
#define UART_SLAVE_STATION_ID (0x21U)
/* Ring buffer size */
#define IS_RING_BUFFER_EMPTY(x) (0U == ((x)->u16UsedSize))
/* Multi-processor silence mode */
#define LP_UART_NORMAL_MODE (0U)
#define LP_UART_SILENCE_MODE (1U)
/**
* @brief Ring buffer structure definition
*/
typedef struct
{
uint16_t u16Capacity;
__IO uint16_t u16UsedSize;
uint16_t u16InIdx;
uint16_t u16OutIdx;
uint8_t au8Buf[50];
} stc_ring_buffer_t;
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
static uint8_t m_u8UartSilenceMode = LP_UART_NORMAL_MODE;
static stc_ring_buffer_t m_stcRingBuf = {
.u16InIdx = 0U,
.u16OutIdx = 0U,
.u16UsedSize = 0U,
.u16Capacity = sizeof (m_stcRingBuf.au8Buf),
};
/****************************************************************************
* Private Functions
****************************************************************************/
/**
* @brief Set silence mode.
* @param [in] u8Mode Silence mode
* This parameter can be one of the following values:
* @arg LP_UART_SILENCE_MODE: UART silence mode
* @arg LP_UART_NORMAL_MODE: UART normal mode
* @retval None
*/
static void UsartSetSilenceMode(uint8_t u8Mode)
{
m_u8UartSilenceMode = u8Mode;
}
/**
* @brief Get silence mode.
* @param [in] None
* @retval Returned value can be one of the following values:
* @arg LP_UART_SILENCE_MODE: UART silence mode
* @arg LP_UART_NORMAL_MODE: UART normal mode
*/
static uint8_t UsartGetSilenceMode(void)
{
return m_u8UartSilenceMode;
}
/**
* @brief Instal IRQ handler.
* @param [in] pstcConfig Pointer to struct @ref stc_irq_signin_config_t
* @param [in] u32Priority Interrupt priority
* @retval None
*/
static void InstalIrqHandler(const stc_irq_signin_config_t *pstcConfig,
uint32_t u32Priority)
{
if (NULL != pstcConfig)
{
(void)INTC_IrqSignIn(pstcConfig);
NVIC_ClearPendingIRQ(pstcConfig->enIRQn);
NVIC_SetPriority(pstcConfig->enIRQn, u32Priority);
NVIC_EnableIRQ(pstcConfig->enIRQn);
}
}
/**
* @brief Write ring buffer.
* @param [in] pstcBuffer Pointer to a @ref stc_ring_buffer_t structure
* @param [in] pu8Data Pointer to data buffer to read
* @retval An en_result_t enumeration value:
* - Ok: Write success.
* - ErrorNotReady: Buffer is empty.
*/
static en_result_t RingBufRead(stc_ring_buffer_t *pstcBuffer, uint8_t *pu8Data)
{
en_result_t enRet = Ok;
if (pstcBuffer->u16UsedSize == 0U)
{
enRet = ErrorNotReady;
}
else
{
*pu8Data = pstcBuffer->au8Buf[pstcBuffer->u16OutIdx++];
pstcBuffer->u16OutIdx %= pstcBuffer->u16Capacity;
pstcBuffer->u16UsedSize--;
}
return enRet;
}
/**
* @brief UART TX Empty IRQ callback.
* @param None
* @retval None
*/
static void USART_TxEmpty_IrqCallback(void)
{
uint8_t u8Data = 0U;
en_flag_status_t enFlag = USART_GetStatus(LP_UNIT, USART_FLAG_TXE);
en_functional_state_t enState = USART_GetFuncState(LP_UNIT, USART_INT_TXE);
if ((Set == enFlag) && (Enable == enState))
{
USART_SendId(LP_UNIT, UART_SLAVE_STATION_ID);
while (Reset == USART_GetStatus(LP_UNIT, USART_FLAG_TC)) /* Wait Tx data register empty */
{
}
if (Ok == RingBufRead(&m_stcRingBuf, &u8Data))
{
USART_SendData(LP_UNIT, (uint16_t)u8Data);
}
if (IS_RING_BUFFER_EMPTY(&m_stcRingBuf))
{
USART_FuncCmd(LP_UNIT, USART_INT_TXE, Disable);
USART_FuncCmd(LP_UNIT, USART_INT_TC, Enable);
}
}
}
/**
* @brief UART TX Complete IRQ callback.
* @param None
* @retval None
*/
static void USART_TxComplete_IrqCallback(void)
{
en_flag_status_t enFlag = USART_GetStatus(LP_UNIT, USART_FLAG_TC);
en_functional_state_t enState = USART_GetFuncState(LP_UNIT, USART_INT_TC);
if ((Set == enFlag) && (Enable == enState))
{
/* Disable TX function */
USART_FuncCmd(LP_UNIT, (USART_TX | USART_RX | USART_INT_TC), Disable);
/* Enable RX function */
USART_FuncCmd(LP_UNIT, (USART_RX | USART_INT_RX), Enable);
}
}
/**
* @brief Write ring buffer.
* @param [in] pstcBuffer Pointer to a @ref stc_ring_buffer_t structure
* @param [in] u8Data Data to write
* @retval An en_result_t enumeration value:
* - Ok: Write success.
* - ErrorBufferFull: Buffer is full.
*/
static en_result_t write_ring_buf(stc_ring_buffer_t *pstcBuffer, uint8_t u8Data)
{
en_result_t enRet = Ok;
if (pstcBuffer->u16UsedSize >= pstcBuffer->u16Capacity)
{
enRet = ErrorBufferFull;
}
else
{
pstcBuffer->au8Buf[pstcBuffer->u16InIdx++] = u8Data;
pstcBuffer->u16InIdx %= pstcBuffer->u16Capacity;
pstcBuffer->u16UsedSize++;
}
return enRet;
}
/**
* @brief UART RX IRQ callback.
* @param None
* @retval None
*/
static void USART_Rx_IrqCallback(void)
{
uint8_t u8RxData;
en_flag_status_t enFlag = USART_GetStatus(LP_UNIT, USART_FLAG_RXNE);
en_functional_state_t enState = USART_GetFuncState(LP_UNIT, USART_INT_RX);
if ((Set == enFlag) && (Enable == enState))
{
u8RxData = (uint8_t)USART_RecData(LP_UNIT);
if ((Reset == USART_GetStatus(LP_UNIT, USART_FLAG_MPB)) &&
(LP_UART_NORMAL_MODE == UsartGetSilenceMode()))
{
write_ring_buf(&m_stcRingBuf, u8RxData);
}
else
{
if (UART_MASTER_STATION_ID != u8RxData)
{
USART_SilenceCmd(LP_UNIT, Enable);
UsartSetSilenceMode(LP_UART_SILENCE_MODE);
}
else
{
UsartSetSilenceMode(LP_UART_NORMAL_MODE);
}
}
}
}
/**
* @brief UART RX Error IRQ callback.
* @param None
* @retval None
*/
static void USART_RxErr_IrqCallback(void)
{
USART_ClearStatus(LP_UNIT, (USART_CLEAR_FLAG_FE | USART_CLEAR_FLAG_PE | USART_CLEAR_FLAG_ORE));
}
void hc32_unlock(void)
{
/* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */
GPIO_Unlock();
/* Unlock PWC register: FCG0 */
PWC_FCG0_Unlock();
/* Unlock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */
PWC_Unlock(PWC_UNLOCK_CODE_0);
/* Unlock SRAM register: WTCR */
SRAM_WTCR_Unlock();
/* Unlock SRAM register: CKCR */
// SRAM_CKCR_Unlock();
/* Unlock all EFM registers */
EFM_Unlock();
}
void hc32_lock(void)
{
/* Lock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */
GPIO_Lock();
/* Lock PWC register: FCG0 */
PWC_FCG0_Lock();
/* Lock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */
PWC_Lock(PWC_UNLOCK_CODE_0);
/* Lock SRAM register: WTCR */
SRAM_WTCR_Lock();
/* Lock SRAM register: CKCR */
// SRAM_CKCR_Lock();
/* Lock EFM OTP write protect registers */
// EFM_OTP_WP_Lock();
/* Lock EFM register: FWMC */
// EFM_FWMC_Lock();
/* Lock all EFM registers */
EFM_Lock();
}
void hc32_print_portinit(void)
{
GPIO_SetFunc(BSP_PRINTF_PORT, BSP_PRINTF_PIN, BSP_PRINTF_PORT_FUNC, PIN_SUBFUNC_DISABLE);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_lowputc
*
* Description:
* Output one byte on the serial console
*
****************************************************************************/
void arm_lowputc(char ch)
{
while(Set != USART_GetStatus(LP_UNIT, USART_FLAG_TXE));
USART_SendData(LP_UNIT, ch);
}
/****************************************************************************
* Name: hc32_lowsetup
*
* Description:
* This performs basic initialization of the USART used for the serial
* console. Its purpose is to get the console output available as soon
* as possible.
*
****************************************************************************/
void hc32_lowsetup(void)
{
stc_irq_signin_config_t stcIrqSigninCfg;
const stc_usart_multiprocessor_init_t stcUartMultiProcessorInit = {
.u32Baudrate = 115200UL,
.u32BitDirection = USART_LSB,
.u32StopBit = USART_STOPBIT_1BIT,
.u32DataWidth = USART_DATA_LENGTH_8BIT,
.u32ClkMode = USART_INTERNCLK_NONE_OUTPUT,
.u32PclkDiv = USART_PCLK_DIV64,
.u32OversamplingBits = USART_OVERSAMPLING_8BIT,
.u32NoiseFilterState = USART_NOISE_FILTER_DISABLE,
.u32SbDetectPolarity = USART_SB_DETECT_FALLING,
};
hc32_unlock();
hc32_clk_config();
/* Initialize UART for debug print function. */
DDL_PrintfInit(BSP_PRINTF_DEVICE, BSP_PRINTF_BAUDRATE, hc32_print_portinit);
/* Configure USART RX/TX pin. */
GPIO_SetFunc(LP_RX_PORT, LP_RX_PIN, LP_RX_GPIO_FUNC, PIN_SUBFUNC_DISABLE);
GPIO_SetFunc(LP_TX_PORT, LP_TX_PIN, LP_TX_GPIO_FUNC, PIN_SUBFUNC_DISABLE);
hc32_lock();
/* Enable peripheral clock */
PWC_Fcg3PeriphClockCmd(LP_FUNCTION_CLK_GATE, Enable);
/* Set silence mode */
UsartSetSilenceMode(LP_UART_SILENCE_MODE);
/* Initialize UART function. */
(void)USART_MultiProcessorInit(LP_UNIT, &stcUartMultiProcessorInit);
/* Register error IRQ handler && configure NVIC. */
stcIrqSigninCfg.enIRQn = LP_UNIT_ERR_INT_IRQn;
stcIrqSigninCfg.enIntSrc = LP_UNIT_ERR_INT_SRC;
stcIrqSigninCfg.pfnCallback = &USART_RxErr_IrqCallback;
InstalIrqHandler(&stcIrqSigninCfg, DDL_IRQ_PRIORITY_DEFAULT);
/* Register RX IRQ handler && configure NVIC. */
stcIrqSigninCfg.enIRQn = LP_UNIT_RX_INT_IRQn;
stcIrqSigninCfg.enIntSrc = LP_UNIT_RX_INT_SRC;
stcIrqSigninCfg.pfnCallback = &USART_Rx_IrqCallback;
InstalIrqHandler(&stcIrqSigninCfg, DDL_IRQ_PRIORITY_00);
/* Register TX IRQ handler && configure NVIC. */
stcIrqSigninCfg.enIRQn = LP_UNIT_TX_INT_IRQn;
stcIrqSigninCfg.enIntSrc = LP_UNIT_TX_INT_SRC;
stcIrqSigninCfg.pfnCallback = &USART_TxEmpty_IrqCallback;
InstalIrqHandler(&stcIrqSigninCfg, DDL_IRQ_PRIORITY_DEFAULT);
/* Register TC IRQ handler && configure NVIC. */
stcIrqSigninCfg.enIRQn = LP_UNIT_TCI_INT_IRQn;
stcIrqSigninCfg.enIntSrc = LP_UNIT_TCI_INT_SRC;
stcIrqSigninCfg.pfnCallback = &USART_TxComplete_IrqCallback;
InstalIrqHandler(&stcIrqSigninCfg, DDL_IRQ_PRIORITY_DEFAULT);
}

67
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/****************************************************************************
* arch/arm/src/hc32/hc32_lowputc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_HC32_HC32_LOWPUTC_H
#define __ARCH_ARM_SRC_HC32_HC32_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: hc32_lowsetup
*
* Description:
* Called at the very beginning of _start.
* Performs low level initialization of serial console.
*
****************************************************************************/
void hc32_lowsetup(void);
void hc32_unlock(void);
void hc32_lock(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_HC32_HC32_LOWPUTC_H */

112
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/****************************************************************************
* arch/arm/src/hc32/hc32_mpuinit.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <assert.h>
#include <nuttx/userspace.h>
#include "mpu.h"
#include "hc32_mpuinit.h"
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef MAX
# define MAX(a,b) a > b ? a : b
#endif
#ifndef MIN
# define MIN(a,b) a < b ? a : b
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: hc32_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only restricted SAM3U
* resources.
*
****************************************************************************/
void hc32_mpuinitialize(void)
{
uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart);
uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend);
DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart &&
dataend >= datastart);
/* Show MPU information */
mpu_showtype();
/* Reset MPU if enabled */
mpu_reset();
/* Configure user flash and SRAM space */
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_user_intsram(datastart, dataend - datastart);
/* Then enable the MPU */
mpu_control(true, false, true);
}
/****************************************************************************
* Name: hc32_mpu_uheap
*
* Description:
* Map the user-heap region.
*
* This logic may need an extension to handle external SDRAM).
*
****************************************************************************/
void hc32_mpu_uheap(uintptr_t start, size_t size)
{
mpu_user_intsram(start, size);
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARM_MPU */

75
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/****************************************************************************
* arch/arm/src/hc32/hc32_mpuinit.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_HC32_HC32_MPUINIT_H
#define __ARCH_ARM_SRC_HC32_HC32_MPUINIT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: hc32_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only unrestricted MCU
* resources.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void hc32_mpuinitialize(void);
#else
# define hc32_mpuinitialize()
#endif
/****************************************************************************
* Name: hc32_mpu_uheap
*
* Description:
* Map the user heap region.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void hc32_mpu_uheap(uintptr_t start, size_t size);
#else
# define hc32_mpu_uheap(start,size)
#endif
#endif /* __ARCH_ARM_SRC_HC32_HC32_MPUINIT_H */

58
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_pm.c Executable file
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/****************************************************************************
* arch/arm/src/hc32/hc32_pminitialize.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_internal.h"
#include "hc32_pm.h"
#ifdef CONFIG_PM
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_pminitialize
*
* Description:
* This function is called by MCU-specific logic at power-on reset in
* order to provide one-time initialization the power management subsystem.
* This function must be called *very* early in the initialization sequence
* *before* any other device drivers are initialized (since they may
* attempt to register with the power management subsystem).
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void arm_pminitialize(void)
{
}
#endif /* CONFIG_PM */

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/****************************************************************************
* arch/arm/src/hc32/hc32_pm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_HC32_HC32_PM_H
#define __ARCH_ARM_SRC_HC32_HC32_PM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include "chip.h"
#include "arm_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: hc32_pmstop
*
* Description:
* Enter STOP mode.
*
* Input Parameters:
* lpds - true: To further reduce power consumption in Stop mode, put the
* internal voltage regulator in low-power mode using the LPDS bit
* of the Power control register (PWR_CR).
*
* Returned Value:
* Zero means that the STOP was successfully entered and the system has
* been re-awakened. The internal voltage regulator is back to its
* original state. Otherwise, STOP mode did not occur and a negated
* errno value is returned to indicate the cause of the failure.
*
****************************************************************************/
int hc32_pmstop(bool lpds);
/****************************************************************************
* Name: hc32_pmstandby
*
* Description:
* Enter STANDBY mode.
*
* Input Parameters:
* None
*
* Returned Value:
* On success, this function will not return (STANDBY mode can only be
* terminated with a reset event). Otherwise, STANDBY mode did not occur
* and a negated errno value is returned to indicate the cause of the
* failure.
*
****************************************************************************/
int hc32_pmstandby(void);
/****************************************************************************
* Name: hc32_pmsleep
*
* Description:
* Enter SLEEP mode.
*
* Input Parameters:
* sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is
* executed, the MCU enters Sleep mode as soon as it
* exits the lowest priority ISR.
* - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep
* mode as soon as WFI or WFE instruction is executed.
* Returned Value:
* None
*
****************************************************************************/
void hc32_pmsleep(bool sleeponexit);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_HC32_HC32_PM_H */

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/****************************************************************************
* arch/arm/src/hc32/hc32_rcc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdio.h>
#include <assert.h>
#include <debug.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "chip.h"
#include "hc32_rcc.h"
#include "hc32f4a0_clk.h"
#include "hc32f4a0_sram.h"
#include "hc32f4a0_efm.h"
#include "hc32f4a0_pwc.h"
#include "hc32f4a0_gpio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Allow up to 100 milliseconds for the high speed clock to become ready.
* that is a very long delay, but if the clock does not become ready we are
* hosed anyway.
*/
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
/*!< System clock frequency (Core clock) */
__NO_INIT uint32_t SystemCoreClock;
/*!< High speed RC frequency (HCR clock) */
__NO_INIT uint32_t HRC_VALUE;
/****************************************************************************
* Included Files
****************************************************************************/
/* Include chip-specific clocking initialization logic */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/**
* @brief Setup the microcontroller system. Initialize the System and update
* the SystemCoreClock variable.
* @param None
* @retval None
*/
void hc32_sysclk_init(void)
{
/* FPU settings */
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
hc32_sysclk_update();
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* @param None
* @retval None
*/
void hc32_sysclk_update(void)
{
uint8_t tmp;
uint32_t plln;
uint32_t pllp;
uint32_t pllm;
/* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */
/* ICG1.HRCFREQSEL = '0' represent HRC_VALUE = 20000000UL */
/* ICG1.HRCFREQSEL = '1' represent HRC_VALUE = 16000000UL */
if (1UL == (HRC_FREQ_MON() & 1UL))
{
HRC_VALUE = HRC_16MHz_VALUE;
}
else
{
HRC_VALUE = HRC_20MHz_VALUE;
}
tmp = M4_CMU->CKSWR & CMU_CKSWR_CKSW;
switch(tmp)
{
case 0x00U: /* use internal high speed RC */
SystemCoreClock = HRC_VALUE;
break;
case 0x01U: /* use internal middle speed RC */
SystemCoreClock = MRC_VALUE;
break;
case 0x02U: /* use internal low speed RC */
SystemCoreClock = LRC_VALUE;
break;
case 0x03U: /* use external high speed OSC */
SystemCoreClock = XTAL_VALUE;
break;
case 0x04U: /* use external low speed OSC */
SystemCoreClock = XTAL32_VALUE;
break;
case 0x05U: /* use PLLH */
/* PLLCLK = ((pllsrc / pllm) * plln) / pllp */
pllp = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHP_POS) & 0x0FUL);
plln = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHN_POS) & 0xFFUL);
pllm = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHM_POS) & 0x03UL);
/* use external high speed OSC as PLL source */
if (0UL == bM4_CMU->PLLHCFGR_b.PLLSRC)
{
SystemCoreClock = (XTAL_VALUE) / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL);
}
/* use internal high RC as PLL source */
else
{
SystemCoreClock = (HRC_VALUE) / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL);
}
break;
default:
break;
}
}
/**
* @brief BSP clock initialize.
* Set board system clock to PLLH@240MHz
* Flash: 5 wait
* SRAM_HS: 1 wait
* SRAM1_2_3_4_B: 2 wait
* PCLK0: 240MHz
* PCLK1: 120MHz
* PCLK2: 60MHz
* PCLK3: 60MHz
* PCLK4: 120MHz
* EXCLK: 120MHz
* HCLK: 240MHz
* @param None
* @retval None
*/
void hc32_clk_config(void)
{
stc_clk_xtal_init_t stcXtalInit;
stc_clk_pllh_init_t stcPLLHInit;
/* PCLK0, HCLK Max 240MHz */
/* PCLK1, PCLK4 Max 120MHz */
/* PCLK2, PCLK3 Max 60MHz */
/* EX BUS Max 120MHz */
CLK_ClkDiv(CLK_CATE_ALL, \
(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \
CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \
CLK_HCLK_DIV1));
CLK_XtalStructInit(&stcXtalInit);
/* Config Xtal and enable Xtal */
stcXtalInit.u8XtalMode = CLK_XTALMODE_OSC;
stcXtalInit.u8XtalDrv = CLK_XTALDRV_LOW;
stcXtalInit.u8XtalState = CLK_XTAL_ON;
stcXtalInit.u8XtalStb = CLK_XTALSTB_2MS;
CLK_XtalInit(&stcXtalInit);
(void)CLK_PLLHStructInit(&stcPLLHInit);
/* VCO = (8/1)*120 = 960MHz*/
stcPLLHInit.u8PLLState = CLK_PLLH_ON;
stcPLLHInit.PLLCFGR = 0UL;
stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLLSRC_XTAL;
(void)CLK_PLLHInit(&stcPLLHInit);
/* Highspeed SRAM set to 1 Read/Write wait cycle */
SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE_1, SRAM_WAIT_CYCLE_1);
/* SRAM1_2_3_4_backup set to 2 Read/Write wait cycle */
SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE_2, SRAM_WAIT_CYCLE_2);
/* 0-wait @ 40MHz */
EFM_SetWaitCycle(EFM_WAIT_CYCLE_5);
/* 4 cycles for 200 ~ 250MHz */
GPIO_SetReadWaitCycle(GPIO_READ_WAIT_4);
CLK_SetSysClkSrc(CLK_SYSCLKSOURCE_PLLH);
}
/****************************************************************************
* Name: rcc_resetbkp
*
* Description:
* The RTC needs to reset the Backup Domain to change RTCSEL and resetting
* the Backup Domain renders to disabling the LSE as consequence.
* In order to avoid resetting the Backup Domain when we already
* configured LSE we will reset the Backup Domain early (here).
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#if defined(CONFIG_HC32_RTC) && defined(CONFIG_HC32_PWR)
static inline void rcc_resetbkp(void)
{
uint32_t regval;
/* Check if the RTC is already configured */
// hc32_pwr_initbkp(false);
regval = getreg32(RTC_MAGIC_REG);
if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET)
{
hc32_pwr_enablebkp(true);
/* We might be changing RTCSEL - to ensure such changes work, we must
* reset the backup domain (having backed up the RTC_MAGIC token)
*/
modifyreg32(HC32_RCC_XXX, 0, RCC_XXX_YYYRST);
modifyreg32(HC32_RCC_XXX, RCC_XXX_YYYRST, 0);
hc32_pwr_enablebkp(false);
}
}
#else
# define rcc_resetbkp()
#endif
/****************************************************************************
* Name: rcc_reset
*
* Description:
* Reset the RCC clock configuration to the default reset state
*
****************************************************************************/
static inline void rcc_reset(void)
{
}
static inline void rcc_enableperipherals(void)
{
}
#ifndef CONFIG_ARCH_BOARD_HC32_CUSTOM_CLOCKCONFIG
static void hc32_stdclockconfig(void)
{
}
#endif
void hc32_clk_init(void)
{
hc32_sysclk_init();
/* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */
GPIO_Unlock();
/* Unlock PWC register: FCG0 */
// PWC_FCG0_Unlock();
// /* Unlock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */
// PWC_Unlock(PWC_UNLOCK_CODE_0);
/* Unlock SRAM register: WTCR */
SRAM_WTCR_Unlock();
/* Unlock SRAM register: CKCR */
// SRAM_CKCR_Unlock();
/* Unlock all EFM registers */
EFM_Unlock();
hc32_clk_config();
/* Lock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */
GPIO_Lock();
/* Lock PWC register: FCG0 */
PWC_FCG0_Lock();
/* Lock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */
PWC_Lock(PWC_UNLOCK_CODE_0);
/* Lock SRAM register: WTCR */
SRAM_WTCR_Lock();
/* Lock SRAM register: CKCR */
// SRAM_CKCR_Lock();
/* Lock EFM OTP write protect registers */
// EFM_OTP_WP_Lock();
/* Lock EFM register: FWMC */
// EFM_FWMC_Lock();
/* Lock all EFM registers */
EFM_Lock();
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: hc32_clockconfig
*
* Description:
* Called to establish the clock settings based on the values in board.h.
* This function (by default) will reset most everything, enable the PLL,
* and enable peripheral clocking for all peripherals enabled in the NuttX
* configuration file.
*
* If CONFIG_ARCH_BOARD_HC32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called hc32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void hc32_clockconfig(void)
{
/* Make sure that we are starting in the reset state */
rcc_reset();
/* Reset backup domain if appropriate */
rcc_resetbkp();
#if defined(CONFIG_ARCH_BOARD_HC32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
hc32_board_clockconfig();
#else
/* Invoke standard, fixed clock configuration based on definitions
* in board.h
*/
hc32_stdclockconfig();
#endif
/* Enable peripheral clocking */
rcc_enableperipherals();
#ifdef CONFIG_HC32_SYSCFG_IOCOMPENSATION
/* Enable I/O Compensation */
hc32_iocompensation();
#endif
hc32_clk_init();
}
/****************************************************************************
* Name: hc32_clockenable
*
* Description:
* Re-enable the clock and restore the clock settings based on settings
* in board.h. This function is only available to support low-power
* modes of operation: When re-awakening from deep-sleep modes, it is
* necessary to re-enable/re-start the PLL
*
* This functional performs a subset of the operations performed by
* hc32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_HC32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called hc32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_PM
void hc32_clockenable(void)
{
#if defined(CONFIG_ARCH_BOARD_HC32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
hc32_board_clockconfig();
#else
/* Invoke standard, fixed clock configuration based on definitions
* in board.h
*/
hc32_stdclockconfig();
#endif
}
#endif

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/****************************************************************************
* arch/arm/src/hc32/hc32_rcc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_HC32_HC32_RCC_H
#define __ARCH_ARM_SRC_HC32_HC32_RCC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_internal.h"
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* This symbol references the Cortex-M3/4 vector table (as positioned by the
* linker script, ld.script or ld.script.dfu. The standard location for the
* vector table is at the beginning of FLASH at address 0x0800:0000. If we
* are using the STMicro DFU bootloader, then the vector table will be offset
* to a different location in FLASH and we will need to set the NVIC vector
* location to this alternative location.
*/
#if defined(__ICCARM__)
/* _vectors replaced on __vector_table for IAR C-SPY Simulator */
extern uint32_t __vector_table[];
#else
extern uint32_t _vectors[];
#endif
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: hc32_clockconfig
*
* Description:
* Called to establish the clock settings based on the values in board.h.
* This function (by default) will reset most everything, enable the PLL,
* and enable peripheral clocking for all periperipherals enabled in the
* NuttX configuration file.
*
* If CONFIG_ARCH_BOARD_HC32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called hc32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void hc32_clockconfig(void);
/****************************************************************************
* Name: hc32_board_clockconfig
*
* Description:
* Any HC32 board may replace the "standard" board clock configuration
* logic with its own, custom clock configuration logic.
*
****************************************************************************/
#ifdef CONFIG_ARCH_BOARD_HC32_CUSTOM_CLOCKCONFIG
void hc32_board_clockconfig(void);
#endif
/****************************************************************************
* Name: hc32_clockenable
*
* Description:
* Re-enable the clock and restore the clock settings based on settings in
* board.h.
* This function is only available to support low-power modes of operation:
* When re-awakening from deep-sleep modes, it is necessary to re-enable/
* re-start the PLL
*
* This functional performs a subset of the operations performed by
* hc32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_HC32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called hc32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_PM
void hc32_clockenable(void);
#endif
/****************************************************************************
* Name: hc32_rcc_enablelse
*
* Description:
* Enable the External Low-Speed (LSE) Oscillator.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void hc32_rcc_enablelse(void);
/****************************************************************************
* Name: hc32_rcc_enablelsi
*
* Description:
* Enable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void hc32_rcc_enablelsi(void);
/****************************************************************************
* Name: hc32_rcc_disablelsi
*
* Description:
* Disable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void hc32_rcc_disablelsi(void);
void hc32_clk_init(void);
void hc32_clk_config(void);
void hc32_sysclk_init(void); /*!< Initialize the system */
void hc32_sysclk_update(void); /*!< Update SystemCoreClock variable */
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_HC32_HC32_RCC_H */

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/****************************************************************************
* arch/arm/src/stm32/stm32_rtc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32_RTC_H
#define __ARCH_ARM_SRC_STM32_STM32_RTC_H
#include <nuttx/config.h>
#include "chip.h"
/* The STM32 F1 has a simple battery-backed counter for its RTC and has a
* separate block for the BKP registers.
*/
#if defined(CONFIG_STM32_STM32F10XX)
# include "hardware/stm32_rtc.h"
# include "hardware/stm32_bkp.h"
/* The other families use a more traditional Realtime Clock/Calendar (RTCC)
* with broken-out data/time in BCD format. The backup registers are
* integrated into the RTCC in these families.
*/
#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F4XXX)
# include "hardware/stm32_rtcc.h"
#endif
/* Alarm function differs from part to part */
#if defined(CONFIG_STM32_STM32F4XXX)
# include "stm32f40xxx_alarm.h"
#elif defined(CONFIG_STM32_STM32L15XX)
# include "stm32l15xxx_alarm.h"
#else
# include "stm32_alarm.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a
* second base */
#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */
#if defined(CONFIG_STM32_STM32F10XX)
/* RTC is only a counter, store RTC data in backup domain register DR1 (if
* CONFIG_RTC_HIRES) and DR2 (state).
*/
#if !defined(CONFIG_STM32_RTC_MAGIC)
# define CONFIG_STM32_RTC_MAGIC (0xface) /* only 16 bit */
#endif
#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET)
# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00d)
#endif
#define RTC_MAGIC_REG STM32_BKP_DR2
#else /* !CONFIG_STM32_STM32F10XX */
#if !defined(CONFIG_STM32_RTC_MAGIC)
# define CONFIG_STM32_RTC_MAGIC (0xfacefeed)
#endif
#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET)
# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface)
#endif
#if !defined(CONFIG_STM32_RTC_MAGIC_REG)
# define CONFIG_STM32_RTC_MAGIC_REG (0)
#endif
#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG)
#endif /* CONFIG_STM32_STM32F10XX */
#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC
#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_rtc_irqinitialize
*
* Description:
* Initialize IRQs for RTC, not possible during up_rtc_initialize because
* up_irqinitialize is called later.
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int stm32_rtc_irqinitialize(void);
/****************************************************************************
* Name: stm32_rtc_getdatetime_with_subseconds
*
* Description:
* Get the current date and time from the date/time RTC. This interface
* is only supported by the date/time RTC hardware implementation.
* It is used to replace the system timer. It is only used by the RTOS
* during initialization to set up the system time when CONFIG_RTC and
* CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not).
*
* NOTE: Some date/time RTC hardware is capability of sub-second accuracy.
* Thatsub-second accuracy is returned through 'nsec'.
*
* Input Parameters:
* tp - The location to return the high resolution time value.
* nsec - The location to return the subsecond time value.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
int stm32_rtc_getdatetime_with_subseconds(FAR struct tm *tp, FAR long *nsec);
#endif
/****************************************************************************
* Name: stm32_rtc_setdatetime
*
* Description:
* Set the RTC to the provided time. RTC implementations which provide
* up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide
* this function.
*
* Input Parameters:
* tp - the time to use
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_RTC_DATETIME
struct tm;
int stm32_rtc_setdatetime(FAR const struct tm *tp);
#endif
/****************************************************************************
* Name: stm32_rtc_lowerhalf
*
* Description:
* Instantiate the RTC lower half driver for the STM32. General usage:
*
* #include <nuttx/timers/rtc.h>
* #include "stm32_rtc.h"
*
* struct rtc_lowerhalf_s *lower;
* lower = stm32_rtc_lowerhalf();
* rtc_initialize(0, lower);
*
* Input Parameters:
* None
*
* Returned Value:
* On success, a non-NULL RTC lower interface is returned. NULL is
* returned on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_DRIVER
struct rtc_lowerhalf_s;
FAR struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32_STM32_RTC_H */

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/****************************************************************************
* arch/arm/src/hc32/hc32_start.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/init.h>
#include "arm_internal.h"
#include "nvic.h"
#include "mpu.h"
#include "hc32_rcc.h"
#include "hc32_lowputc.h"
#include "hc32_gpio.h"
#include "hc32_uart.h"
#include "hc32_start.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* .data is positioned first in the primary RAM followed immediately by .bss.
* The IDLE thread stack lies just after .bss and has size give by
* CONFIG_IDLETHREAD_STACKSIZE; The heap then begins just after the IDLE.
* ARM EABI requires 64 bit stack alignment.
*/
#define HEAP_BASE ((uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE)
/****************************************************************************
* Public Data
****************************************************************************/
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
* linker script. _ebss lies at the end of the BSS region. The idle task
* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
* The IDLE thread is the thread that the system boots on and, eventually,
* becomes the IDLE, do nothing task that runs only when there is nothing
* else to run. The heap continues from there until the end of memory.
* g_idle_topstack is a read-only variable the provides this computed
* address.
*/
const uintptr_t g_idle_topstack = HEAP_BASE;
/****************************************************************************
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void hc32_fpuconfig(void);
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: showprogress
*
* Description:
* Print a character on the UART to show boot status.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) arm_lowputc(c)
#else
# define showprogress(c)
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
#ifdef CONFIG_ARMV7M_STACKCHECK
/* we need to get r10 set before we can allow instrumentation calls */
void __start(void) noinstrument_function;
#endif
/****************************************************************************
* Name: hc32_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void hc32_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void hc32_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define hc32_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: _start
*
* Description:
* This is the reset entry point.
*
****************************************************************************/
void __start(void)
{
const uint32_t *src;
uint32_t *dest;
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile("sub r10, sp, %0" : :
"r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* If enabled reset the MPU */
mpu_early_reset();
/* Configure the UART so that we can get debug output as soon as possible */
hc32_clockconfig();
hc32_fpuconfig();
hc32_lowsetup();
hc32_gpioinit();
showprogress('A');
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables.
*/
for (dest = _START_BSS; dest < _END_BSS; )
{
*dest++ = 0;
}
showprogress('B');
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
*/
for (src = _DATA_INIT, dest = _START_DATA; dest < _END_DATA; )
{
*dest++ = *src++;
}
showprogress('C');
#ifdef CONFIG_ARMV7M_ITMSYSLOG
/* Perform ARMv7-M ITM SYSLOG initialization */
itm_syslog_initialize();
#endif
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT
arm_earlyserialinit();
#endif
showprogress('D');
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*/
#ifdef CONFIG_BUILD_PROTECTED
hc32_userspace();
showprogress('E');
#endif
/* Initialize onboard resources */
hc32_boardinitialize();
showprogress('F');
hc32_print("nuttx start ...\n");
/* Then start NuttX */
showprogress('\r');
showprogress('\n');
nx_start();
/* Shouldn't get here */
for (; ; );
}

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/****************************************************************************
* arch/arm/src/hc32/hc32_start.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_HC32_HC32_START_H
#define __ARCH_ARM_SRC_HC32_HC32_START_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: hc32_boardinitialize
*
* Description:
* All HC32 architectures must provide the following entry point.
* This entry point is called early in the initialization -- after
* clocking and memory have been configured but before caches have been
* enabled and before any devices have been initialized.
*
****************************************************************************/
void hc32_boardinitialize(void);
#endif /* __ARCH_ARM_SRC_HC32_HC32_START_H */

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/****************************************************************************
* arch/arm/src/hc32/hc32_timerisr.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/timers/arch_timer.h>
#include <arch/board/board.h>
#include "nvic.h"
#include "clock/clock.h"
#include "arm_internal.h"
#include "systick.h"
#include "chip.h"
#include "hc32f4a0.h"
#include "hc32_common.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The desired timer interrupt frequency is provided by the definition
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
* system clock ticks per second. That value is a user configurable setting
* that defaults to 100 (100 ticks per second = 10 MS interval).
*
* The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK)
* divided by 8. The SysTick can work either with this clock or with the
* Cortex clock (HCLK), configurable in the SysTick Control and Status
* register.
*/
#undef CONFIG_HC32_SYSTICK_HCLKd8 /* Power up default is HCLK, not HCLK/8 */
/* And I don't know now to re-configure it yet */
#ifdef CONFIG_HC32_SYSTICK_HCLKd8
# define SYSTICK_RELOAD ((HC32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
#else
# define SYSTICK_RELOAD ((HC32_HCLK_FREQUENCY / CLK_TCK) - 1)
#endif
/* The size of the reload field is 24 bits. Verify that the reload value
* will fit in the reload register.
*/
//#if SYSTICK_RELOAD > 0x00ffffff
//# error SYSTICK_RELOAD exceeds the range of the RELOAD register
//#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: hc32_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
****************************************************************************/
#if !defined(CONFIG_ARMV7M_SYSTICK) && !defined(CONFIG_TIMER_ARCH)
static int hc32_timerisr(int irq, uint32_t *regs, void *arg)
{
/* Process timer interrupt */
nxsched_process_timer();
return 0;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: up_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void up_timer_initialize(void)
{
uint32_t regval;
/* Set the SysTick interrupt to the default priority */
regval = getreg32(NVIC_SYSH12_15_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
putreg32(regval, NVIC_SYSH12_15_PRIORITY);
/* Make sure that the SYSTICK clock source is set correctly */
#if 0 /* Does not work. Comes up with HCLK source and I can't change it */
regval = getreg32(NVIC_SYSTICK_CTRL);
#ifdef CONFIG_HC32_SYSTICK_HCLKd8
regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
#else
regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
#endif
putreg32(regval, NVIC_SYSTICK_CTRL);
#endif
#if defined(CONFIG_ARMV7M_SYSTICK) && defined(CONFIG_TIMER_ARCH)
up_timer_set_lowerhalf(systick_initialize(true, HC32_HCLK_FREQUENCY, -1));
#else
/* Configure SysTick to interrupt at the requested rate */
putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
/* Attach the timer interrupt vector */
irq_attach(HC32_IRQ_SYSTICK, (xcpt_t)hc32_timerisr, NULL);
/* Enable SysTick interrupts */
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
/* And enable the timer interrupt */
up_enable_irq(HC32_IRQ_SYSTICK);
#endif
}

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/****************************************************************************
* arch/arm/src/hc32/hc32_uart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_STC_HC32_HC32_UART_H
#define __ARCH_ARM_STC_HC32_HC32_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/serial/serial.h>
#include "chip.h"
#define CONSOLE_UART 6
#define HC32_NUSART 6
#ifndef USE_SERIALDRIVER
#define USE_SERIALDRIVER 1
#endif
#ifndef HAVE_SERIALDRIVER
#define HAVE_SERIALDRIVER 1
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Make sure that we have not enabled more U[S]ARTs than are supported by the
* device.
*/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Name: hc32_serial_get_uart
*
* Description:
* Get serial driver structure for HC32 UART
*
****************************************************************************/
FAR uart_dev_t *hc32_serial_get_uart(int uart_num);
void hc32_print(const char *fmt, ...);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_STC_HC32_HC32_UART_H */

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/**
*******************************************************************************
* @file hc32f4a0_gpio.c
* @brief This file provides firmware functions to manage the General Purpose
* Input/Output(GPIO).
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Zhangxl First version
2020-09-18 Zhangxl Optimize GPIO_DeInit() API
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32f4a0_gpio.h"
#include "hc32f4a0_utility.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @defgroup DDL_GPIO GPIO
* @brief GPIO Driver Library
* @{
*/
#if (DDL_GPIO_ENABLE == DDL_ON)
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup GPIO_Local_Macros GPIO Local Macros
* @{
*/
/**
* @defgroup GPIO_Registers_Reset_Value GPIO Registers Reset Value
* @{
*/
#define GPIO_PSPCR_RESET_VALUE (0x001FU)
#define GPIO_PCCR_RESET_VALUE (0x1000U)
#define GPIO_PINAER_RESET_VALUE (0x0000U)
/**
* @}
*/
/**
* @defgroup GPIO_Check_Parameters_Validity GPIO Check Parameters Validity
* @{
*/
/*! Parameter validity check for pin state. */
#define IS_GPIO_PIN_STATE(state) \
( ((state) == PIN_STATE_RESET) || \
((state) == PIN_STATE_SET))
/*! Parameter validity check for pin direction. */
#define IS_GPIO_DIR(dir) \
( ((dir) == PIN_DIR_IN) || \
((dir) == PIN_DIR_OUT))
/*! Parameter validity check for pin output type. */
#define IS_GPIO_OTYPE(otype) \
( ((otype) == PIN_OTYPE_CMOS) || \
((otype) == PIN_OTYPE_NMOS))
/*! Parameter validity check for pin driver capacity. */
#define IS_GPIO_PIN_DRV(drv) \
( ((drv) == PIN_DRV_LOW) || \
((drv) == PIN_DRV_MID) || \
((drv) == PIN_DRV_HIGH))
/*! Parameter validity check for pin latch function. */
#define IS_GPIO_LATCH(latch) \
( ((latch) == PIN_LATCH_OFF) || \
((latch) == PIN_LATCH_ON))
/*! Parameter validity check for internal pull-up resistor. */
#define IS_GPIO_PIN_PU(pu) \
( ((pu) == PIN_PU_OFF) || \
((pu) == PIN_PU_ON))
/*! Parameter validity check for pin state invert. */
#define IS_GPIO_PIN_INVERT(invert) \
( ((invert) == PIN_INVERT_OFF) || \
((invert) == PIN_INVERT_ON))
/*! Parameter validity check for pin input type. */
#define IS_GPIO_ITYPE(itype) \
( ((itype) == PIN_ITYPE_SMT) || \
((itype) == PIN_ITYPE_CMOS))
/*! Parameter validity check for external interrupt function. */
#define IS_GPIO_EXINT(exint) \
( ((exint) == PIN_EXINT_OFF) || \
((exint) == PIN_EXINT_ON))
/*! Parameter validity check for pin attribute. */
#define IS_GPIO_ATTR(attr) \
( ((attr) == PIN_ATTR_DIGITAL) || \
((attr) == PIN_ATTR_ANALOG))
/*! Parameter validity check for pin number. */
#define IS_GPIO_PIN(pin) (((pin) & GPIO_PIN_MASK ) != 0x0000U)
/*! Parameter validity check for port source. */
#define IS_GPIO_PORT(port) \
( ((port) != 0x00U) && \
(((port) | GPIO_PORT_MASK) == GPIO_PORT_MASK))
/*! Parameter validity check for port source. */
#define IS_GPIO_PORT_SOURCE(port) \
( ((port) == GPIO_PORT_A) || \
((port) == GPIO_PORT_B) || \
((port) == GPIO_PORT_C) || \
((port) == GPIO_PORT_D) || \
((port) == GPIO_PORT_E) || \
((port) == GPIO_PORT_F) || \
((port) == GPIO_PORT_G) || \
((port) == GPIO_PORT_H) || \
((port) == GPIO_PORT_I))
/*! Parameter validity check for pin function. */
#define IS_GPIO_FUNC(func) \
( ((func) <= GPIO_FUNC_20) || \
(((func) >= GPIO_FUNC_32) && ((func) <= GPIO_FUNC_63)))
/*! Parameter validity check for debug pin definition. */
#define IS_GPIO_DEBUG_PORT(port) \
( ((port) != 0x00U) && \
(((port) | GPIO_PIN_DEBUG_JTAG) == GPIO_PIN_DEBUG_JTAG))
/*! Parameter validity check for pin sub-function setting. */
#define IS_GPIO_PIN_BFE(bfe) \
( ((bfe) == PIN_SUBFUNC_ENABLE) || \
((bfe) == PIN_SUBFUNC_DISABLE))
/*! Parameter validity check for pin read wait cycle. */
#define IS_GPIO_READ_WAIT(wait) \
( ((wait) == GPIO_READ_WAIT_0) || \
((wait) == GPIO_READ_WAIT_1) || \
((wait) == GPIO_READ_WAIT_2) || \
((wait) == GPIO_READ_WAIT_3) || \
((wait) == GPIO_READ_WAIT_4) || \
((wait) == GPIO_READ_WAIT_5) || \
((wait) == GPIO_READ_WAIT_6) || \
((wait) == GPIO_READ_WAIT_7))
/* Check GPIO register lock status. */
#define IS_GPIO_UNLOCKED() (GPIO_PWPR_WE == (M4_GPIO->PWPR & GPIO_PWPR_WE))
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup GPIO_Global_Functions GPIO Global Functions
* @{
*/
/**
* @brief Initialize GPIO.
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index
* @param [in] pstcGpioInit: Pointer to a stc_gpio_init_t structure that
* contains configuration information.
* @retval Ok: GPIO initialize successful
* ErrorInvalidParameter: NULL pointer
*/
en_result_t GPIO_Init(uint8_t u8Port, uint16_t u16Pin, const stc_gpio_init_t *pstcGpioInit)
{
__IO uint16_t *PCRx;
uint16_t u16PinPos;
uint16_t u16PCRVal;
en_result_t enRet = Ok;
/* Check if pointer is NULL */
if (NULL == pstcGpioInit)
{
enRet = ErrorInvalidParameter;
}
else
{
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
DDL_ASSERT(IS_GPIO_PIN(u16Pin));
DDL_ASSERT(IS_GPIO_PIN_STATE(pstcGpioInit->u16PinState));
DDL_ASSERT(IS_GPIO_DIR(pstcGpioInit->u16PinDir));
DDL_ASSERT(IS_GPIO_OTYPE(pstcGpioInit->u16PinOType));
DDL_ASSERT(IS_GPIO_PIN_DRV(pstcGpioInit->u16PinDrv));
DDL_ASSERT(IS_GPIO_LATCH(pstcGpioInit->u16Latch));
DDL_ASSERT(IS_GPIO_PIN_PU(pstcGpioInit->u16PullUp));
DDL_ASSERT(IS_GPIO_PIN_INVERT(pstcGpioInit->u16Invert));
DDL_ASSERT(IS_GPIO_ITYPE(pstcGpioInit->u16PinIType));
DDL_ASSERT(IS_GPIO_EXINT(pstcGpioInit->u16ExInt));
DDL_ASSERT(IS_GPIO_UNLOCKED());
for (u16PinPos = 0U; u16PinPos < 16U; u16PinPos++)
{
if ((u16Pin & (1UL<<u16PinPos)) != 0U)
{
PCRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PCRA0) + \
((uint32_t)(u8Port) * 0x40UL) + u16PinPos * 4UL);
u16PCRVal = pstcGpioInit->u16ExInt | pstcGpioInit->u16PinIType | \
pstcGpioInit->u16Invert | pstcGpioInit->u16PullUp | \
pstcGpioInit->u16Latch | pstcGpioInit->u16PinDrv | \
pstcGpioInit->u16PinOType | pstcGpioInit->u16PinState | \
pstcGpioInit->u16PinDir | pstcGpioInit->u16PinAttr;
WRITE_REG16(*PCRx, u16PCRVal);
}
}
}
return enRet;
}
/**
* @brief De-init GPIO register to default value
* @param None
* @retval None
*/
void GPIO_DeInit(void)
{
stc_gpio_init_t stcGpioInit;
DDL_ASSERT(IS_GPIO_UNLOCKED());
(void)GPIO_StructInit(&stcGpioInit);
/* PORTA reset */
(void)GPIO_Init(GPIO_PORT_A, GPIO_PIN_ALL, &stcGpioInit);
/* PORTB reset */
(void)GPIO_Init(GPIO_PORT_B, GPIO_PIN_ALL, &stcGpioInit);
/* PORTC reset */
(void)GPIO_Init(GPIO_PORT_C, GPIO_PIN_ALL, &stcGpioInit);
/* PORTD reset */
(void)GPIO_Init(GPIO_PORT_D, GPIO_PIN_ALL, &stcGpioInit);
/* PORTE reset */
(void)GPIO_Init(GPIO_PORT_E, GPIO_PIN_ALL, &stcGpioInit);
/* PORTF reset */
(void)GPIO_Init(GPIO_PORT_F, GPIO_PIN_ALL, &stcGpioInit);
/* PORTG reset */
(void)GPIO_Init(GPIO_PORT_G, GPIO_PIN_ALL, &stcGpioInit);
/* PORTH reset */
(void)GPIO_Init(GPIO_PORT_H, GPIO_PIN_ALL, &stcGpioInit);
/* PORTI reset */
(void)GPIO_Init(GPIO_PORT_I, (GPIO_PIN_00 | GPIO_PIN_01 | GPIO_PIN_02 | \
GPIO_PIN_03 | GPIO_PIN_04 | GPIO_PIN_05 | \
GPIO_PIN_06 | GPIO_PIN_07 | GPIO_PIN_08 | \
GPIO_PIN_09 | GPIO_PIN_10 | GPIO_PIN_11 | \
GPIO_PIN_12 | GPIO_PIN_13), &stcGpioInit);
/* PORT global register reset */
WRITE_REG16(M4_GPIO->PSPCR, GPIO_PSPCR_RESET_VALUE);
WRITE_REG16(M4_GPIO->PCCR, GPIO_PCCR_RESET_VALUE);
WRITE_REG16(M4_GPIO->PINAER, GPIO_PINAER_RESET_VALUE);
}
/**
* @brief Initialize GPIO config structure. Fill each pstcGpioInit with default value
* @param [in] pstcGpioInit: Pointer to a stc_gpio_init_t structure that
* contains configuration information.
* @retval Ok: GPIO structure initialize successful
* ErrorInvalidParameter: NULL pointer
*/
en_result_t GPIO_StructInit(stc_gpio_init_t *pstcGpioInit)
{
en_result_t enRet = Ok;
/* Check if pointer is NULL */
if (NULL == pstcGpioInit)
{
enRet = ErrorInvalidParameter;
}
else
{
/* Reset GPIO init structure parameters values */
pstcGpioInit->u16PinState = PIN_STATE_RESET;
pstcGpioInit->u16PinDir = PIN_DIR_IN;
pstcGpioInit->u16PinOType = PIN_OTYPE_CMOS;
pstcGpioInit->u16PinDrv = PIN_DRV_LOW;
pstcGpioInit->u16Latch = PIN_LATCH_OFF;
pstcGpioInit->u16PullUp = PIN_PU_OFF;
pstcGpioInit->u16Invert = PIN_INVERT_OFF;
pstcGpioInit->u16PinIType = PIN_ITYPE_SMT;
pstcGpioInit->u16ExInt = PIN_EXINT_OFF;
pstcGpioInit->u16PinAttr = PIN_ATTR_DIGITAL;
}
return enRet;
}
/**
* @brief GPIO debug port configure. Set debug pins to GPIO
* @param [in] u8DebugPort
* @arg GPIO_PIN_SWDIO
* @arg GPIO_PIN_SWCLK
* @arg GPIO_PIN_SWO
* @arg GPIO_PIN_DEBUG_SWD
* @arg GPIO_PIN_TCK
* @arg GPIO_PIN_TMS
* @arg GPIO_PIN_TDO
* @arg GPIO_PIN_TDI
* @arg GPIO_PIN_TRST
* @arg GPIO_PIN_DEBUG_JTAG
* @param [in] enNewState
* @arg Enable: set to debug port (SWD/JTAG)
* @arg Disable: set to GPIO
* @retval None
*/
void GPIO_SetDebugPort(uint8_t u8DebugPort, en_functional_state_t enNewState)
{
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_DEBUG_PORT(u8DebugPort));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
DDL_ASSERT(IS_GPIO_UNLOCKED());
if (Enable == enNewState)
{
SET_REG16_BIT(M4_GPIO->PSPCR, ((uint16_t)u8DebugPort & GPIO_PSPCR_SPFE));
}
else
{
CLEAR_REG16_BIT(M4_GPIO->PSPCR, ((uint16_t)u8DebugPort & GPIO_PSPCR_SPFE));
}
}
/**
* @brief Set specified Port Pin function , and turn ON/OFF its sub-function
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index
* @param [in] u8Func: GPIO_FUNC_x, x can be selected from GPIO function definitions
* @param [in] u16BFE: GPIO Sub-function enable setting
* @arg PIN_SUBFUNC_ENABLE
* @arg PIN_SUBFUNC_DISABLE
* @retval None
*/
void GPIO_SetFunc(uint8_t u8Port, uint16_t u16Pin, uint8_t u8Func, uint16_t u16BFE)
{
__IO uint16_t *PFSRx;
uint8_t u8PinPos;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
DDL_ASSERT(IS_GPIO_PIN(u16Pin));
DDL_ASSERT(IS_GPIO_FUNC(u8Func));
DDL_ASSERT(IS_GPIO_PIN_BFE(u16BFE));
DDL_ASSERT(IS_GPIO_UNLOCKED());
for (u8PinPos = 0U; u8PinPos < 16U; u8PinPos++)
{
if ((u16Pin & (uint16_t)(1UL << u8PinPos)) != 0U)
{
PFSRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PFSRA0) + \
(uint32_t)(u8Port * 0x40UL) + u8PinPos * 4UL);
WRITE_REG16(*PFSRx, (u16BFE | (uint16_t)u8Func));
}
}
}
/**
* @brief Set the sub-function, it's a global configuration
* @param [in] u8Func: GPIO_FUNC_x, x can be selected from GPIO function definitions
* @retval None
*/
void GPIO_SetSubFunc(uint8_t u8Func)
{
DDL_ASSERT(IS_GPIO_FUNC(u8Func));
DDL_ASSERT(IS_GPIO_UNLOCKED());
MODIFY_REG16(M4_GPIO->PCCR, GPIO_PCCR_BFSEL, u8Func);
}
/**
* @brief Initialize GPIO.
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index
* @param [in] enNewState
* @arg Enable: set specified pin output enable
* @arg Disable: set specified pin output disable
* @retval None
*/
void GPIO_OE(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState)
{
__IO uint16_t *POERx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
DDL_ASSERT(IS_GPIO_PIN(u16Pin));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
POERx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->POERA) + 0x10UL * u8Port);
if (Enable == enNewState)
{
SET_REG16_BIT(*POERx, u16Pin);
}
else
{
CLEAR_REG16_BIT(*POERx, u16Pin);
}
}
/**
* @brief GPIO read wait cycle configure.
* @param [in] u16ReadWait
* @arg GPIO_READ_WAIT_0: ~ 50MHz
* @arg GPIO_READ_WAIT_1: 50 ~ 100MHz
* @arg GPIO_READ_WAIT_2: 100 ~ 150MHz
* @arg GPIO_READ_WAIT_3: 150 ~ 200MHz
* @arg GPIO_READ_WAIT_4: 200 ~ 250MHz
* @arg GPIO_READ_WAIT_5: 250MHz above
* @arg GPIO_READ_WAIT_6: 250MHz above
* @arg GPIO_READ_WAIT_7: 250MHz above
* @retval None
*/
void GPIO_SetReadWaitCycle(uint16_t u16ReadWait)
{
DDL_ASSERT(IS_GPIO_READ_WAIT(u16ReadWait));
DDL_ASSERT(IS_GPIO_UNLOCKED());
MODIFY_REG16(M4_GPIO->PCCR, GPIO_PCCR_RDWT, u16ReadWait);
}
/**
* @brief GPIO input MOS always ON configure.
* @param [in] u16PortIdx: Port index
* @arg GPIO_PORTA_IDX
* @arg GPIO_PORTB_IDX
* @arg GPIO_PORTC_IDX
* @arg GPIO_PORTD_IDX
* @arg GPIO_PORTE_IDX
* @arg GPIO_PORTF_IDX
* @arg GPIO_PORTG_IDX
* @arg GPIO_PORTH_IDX
* @arg GPIO_PORTI_IDX
* @arg GPIO_PORT_ALL
* @param [in] enNewState
* @arg Enable: set input MOS always ON
* @arg Disable: set input MOS turns on while read operation
* @retval None
*/
void GPIO_InMOSCmd(uint16_t u16PortIdx, en_functional_state_t enNewState)
{
DDL_ASSERT(IS_GPIO_PORT(u16PortIdx));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
DDL_ASSERT(IS_GPIO_UNLOCKED());
if (Enable == enNewState)
{
SET_REG16_BIT(M4_GPIO->PINAER, u16PortIdx);
}
else
{
CLEAR_REG16_BIT(M4_GPIO->PINAER, u16PortIdx);
}
}
/**
* @brief Read specified GPIO input data port pins
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index
* @retval Specified GPIO port pin input value
*/
en_pin_state_t GPIO_ReadInputPins(uint8_t u8Port, uint16_t u16Pin)
{
__IO uint16_t *PIDRx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
DDL_ASSERT(IS_GPIO_PIN(u16Pin));
PIDRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PIDRA) + 0x10UL * u8Port);
return ((READ_REG16(*PIDRx) & (u16Pin)) != 0U) ? Pin_Set : Pin_Reset;
}
/**
* @brief Read specified GPIO input data port
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @retval Specified GPIO port input value
*/
uint16_t GPIO_ReadInputPort(uint8_t u8Port)
{
__IO uint16_t *PIDRx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
PIDRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PIDRA) + 0x10UL * u8Port);
return READ_REG16(*PIDRx);
}
/**
* @brief Read specified GPIO output data port pins
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index
* @retval Specified GPIO port pin output value
*/
en_pin_state_t GPIO_ReadOutputPins(uint8_t u8Port, uint16_t u16Pin)
{
__IO uint16_t *PODRx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
DDL_ASSERT(IS_GPIO_PIN(u16Pin));
PODRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PODRA) + 0x10UL * u8Port);
return ((*PODRx & (u16Pin)) != 0U) ? Pin_Set : Pin_Reset;
}
/**
* @brief Read specified GPIO output data port
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @retval Specified GPIO port output value
*/
uint16_t GPIO_ReadOutputPort(uint8_t u8Port)
{
__IO uint16_t *PODRx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
PODRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PODRA) + 0x10UL * u8Port);
return READ_REG16(*PODRx);
}
/**
* @brief Set specified GPIO output data port pins
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index
* @retval None
*/
void GPIO_SetPins(uint8_t u8Port, uint16_t u16Pin)
{
__IO uint16_t *POSRx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
DDL_ASSERT(IS_GPIO_PIN(u16Pin));
POSRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->POSRA) + 0x10UL * u8Port);
SET_REG16_BIT(*POSRx, u16Pin);
}
/**
* @brief Reset specified GPIO output data port pins
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index
* @retval None
*/
void GPIO_ResetPins(uint8_t u8Port, uint16_t u16Pin)
{
__IO uint16_t *PORRx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
DDL_ASSERT(IS_GPIO_PIN(u16Pin));
PORRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PORRA) + 0x10UL * u8Port);
SET_REG16_BIT(*PORRx, u16Pin);
}
/**
* @brief Write specified GPIO data port
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16PortVal: Pin output value
* @retval None
*/
void GPIO_WritePort(uint8_t u8Port, uint16_t u16PortVal)
{
__IO uint16_t *PODRx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
PODRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PODRA) + 0x10UL * u8Port);
WRITE_REG16(*PODRx, u16PortVal);
}
/**
* @brief Toggle specified GPIO output data port pin
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index
* @retval None
*/
void GPIO_TogglePins(uint8_t u8Port, uint16_t u16Pin)
{
__IO uint16_t *POTRx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
DDL_ASSERT(IS_GPIO_PIN(u16Pin));
POTRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->POTRA) + 0x10UL * u8Port);
SET_REG16_BIT(*POTRx, u16Pin);
}
/**
* @}
*/
#endif /* DDL_GPIO_ENABLE */
/**
* @}
*/
/**
* @}
*/
/******************************************************************************
* EOF (not truncated)
*****************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_i2c.h
* @brief This file contains all the functions prototypes of the Inter-Integrated
* Circuit(I2C).
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Hexiao First version
2020-07-15 Hexiao Modify I2C_SmBusCmd to I2C_SetMode
2020-08-31 Hexiao Remove invalid clock division value
2020-10-30 Hexiao Optimize data transfer api,etc.
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_I2C_H__
#define __HC32F4A0_I2C_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_I2C
* @{
*/
#if (DDL_I2C_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup I2C_Global_Types I2C Global Types
* @{
*/
/**
* @brief I2c configuration structure
*/
typedef struct
{
uint32_t u32ClkDiv; /*!< I2C clock division for pclk3*/
uint32_t u32Baudrate; /*!< I2C baudrate config*/
uint32_t u32SclTime; /*!< The SCL rising and falling time, count of T(pclk3)*/
}stc_i2c_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup I2C_Global_Macros I2C Global Macros
* @{
*/
/** @defgroup I2C_Buadrate_Max I2C baudrate max value
* @{
*/
#define I2C_BAUDRATE_MAX (400000UL)
/**
* @}
*/
/** @defgroup I2C_Mode Peripheral Mode
* @{
*/
#define I2C_MODE_I2C (0UL)
#define I2C_MODE_SMBUS (2UL)
/**
* @}
*/
/** @defgroup I2C_Transfer_Direction I2C transfer direction
* @{
*/
#define I2C_DIR_TX (0x0U)
#define I2C_DIR_RX (0x1U)
/**
* @}
*/
/** @defgroup I2C_Addr_Config I2C address configuration
* @{
*/
#define I2C_ADDR_MODE_7BIT (0x0U)
#define I2C_ADDR_MODE_10BIT (I2C_SLR0_ADDRMOD0)
/**
* @}
*/
/** @defgroup I2C_Clock_division I2C clock division
* @{
*/
#define I2C_CLK_DIV1 (0UL)
#define I2C_CLK_DIV2 (1UL)
#define I2C_CLK_DIV4 (2UL)
#define I2C_CLK_DIV8 (3UL)
#define I2C_CLK_DIV16 (4UL)
#define I2C_CLK_DIV32 (5UL)
#define I2C_CLK_DIV64 (6UL)
#define I2C_CLK_DIV128 (7UL)
/**
* @}
*/
/** @defgroup I2C_Address_Num I2C address number
* @{
*/
#define I2C_ADDR_0 (0UL)
#define I2C_ADDR_1 (1UL)
/**
* @}
*/
/** @defgroup I2C_Ack_Type I2C ack type
* @{
*/
#define I2C_ACK (0UL)
#define I2C_NACK (I2C_CR1_ACK)
/**
* @}
*/
/** @defgroup I2C_Smbus_Match_Cfg I2C smbus address match configuration
* @{
*/
#define I2C_SMBUS_MATCH_ALRT (I2C_CR1_SMBALRTEN)
#define I2C_SMBUS_MATCH_DEFAULT (I2C_CR1_SMBDEFAULTEN)
#define I2C_SMBUS_MATCH_HOST (I2C_CR1_SMBHOSTEN)
/**
* @}
*/
/** @defgroup I2C_Smbus_clear_mask I2C smbus clear mask
* @{
*/
#define I2C_SMBUS_CONFIG_CLEARMASK (I2C_CR1_SMBALRTEN|I2C_CR1_SMBDEFAULTEN|I2C_CR1_SMBHOSTEN)
/**
* @}
*/
/** @defgroup I2C_Digital_Filter_mode I2C digital filter mode
* @{
*/
#define I2C_DIG_FILTMODE_1CYCLE (0UL << I2C_FLTR_DNF_POS)
#define I2C_DIG_FILTMODE_2CYCLE (1UL << I2C_FLTR_DNF_POS)
#define I2C_DIG_FILTMODE_3CYCLE (2UL << I2C_FLTR_DNF_POS)
#define I2C_DIG_FILTMODE_4CYCLE (3UL << I2C_FLTR_DNF_POS)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup I2C_Global_Functions
* @{
*/
/* Initialization and Configuration **********************************/
void I2C_DeInit(M4_I2C_TypeDef* I2Cx);
en_result_t I2C_StructInit(stc_i2c_init_t* pstcI2C_InitStruct);
en_result_t I2C_Init(M4_I2C_TypeDef* I2Cx, const stc_i2c_init_t *pstcI2C_InitStruct, float32_t *pf32Err);
en_result_t I2C_BaudrateConfig(M4_I2C_TypeDef* I2Cx, const stc_i2c_init_t *pstcI2C_InitStruct, float32_t *pf32Err);
void I2C_SlaveAddrCmd(M4_I2C_TypeDef* I2Cx, uint32_t u32AddrNum, en_functional_state_t enNewState);
void I2C_SlaveAddrConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32Addr);
void I2C_SetMode(M4_I2C_TypeDef* I2Cx, uint32_t u32Mode);
void I2C_Cmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_FastAckCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_BusWaitCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_SoftwareResetCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_IntCmd(M4_I2C_TypeDef* I2Cx, uint32_t u32IntEn, en_functional_state_t enNewState);
void I2C_ClkHighTimeoutConfig(M4_I2C_TypeDef* I2Cx, uint16_t u16TimeoutH);
void I2C_ClkLowTimeoutConfig(M4_I2C_TypeDef* I2Cx, uint16_t u16TimeoutL);
void I2C_ClkHighTimeoutCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_ClkLowTimeoutCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_ClkTimeoutCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_SmbusConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32SmbusConfig, en_functional_state_t enNewState);
void I2C_DigitalFilterConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32DigFilterMode);
void I2C_DigitalFilterCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_AnalogFilterCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_GeneralCallCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
/* Start/Restart/Stop ************************************************/
void I2C_GenerateStart(M4_I2C_TypeDef* I2Cx);
void I2C_GenerateReStart(M4_I2C_TypeDef* I2Cx);
void I2C_GenerateStop(M4_I2C_TypeDef* I2Cx);
/* Status management *************************************************/
en_flag_status_t I2C_GetStatus(const M4_I2C_TypeDef *I2Cx, uint32_t u32StatusBit);
void I2C_ClearStatus(M4_I2C_TypeDef* I2Cx, uint32_t u32StatusBit);
/* Data transfer *****************************************************/
void I2C_WriteDataReg(M4_I2C_TypeDef* I2Cx, uint8_t u8Data);
uint8_t I2C_ReadDataReg(const M4_I2C_TypeDef *I2Cx);
void I2C_AckConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32AckConfig);
/* High level functions for reference ********************************/
en_result_t I2C_Start(M4_I2C_TypeDef* I2Cx, uint32_t u32Timeout);
en_result_t I2C_Restart(M4_I2C_TypeDef* I2Cx, uint32_t u32Timeout);
en_result_t I2C_TransAddr(M4_I2C_TypeDef* I2Cx, uint8_t u8Addr, uint8_t u8Dir, uint32_t u32Timeout);
en_result_t I2C_Trans10BitAddr(M4_I2C_TypeDef* I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout);
en_result_t I2C_TransData(M4_I2C_TypeDef* I2Cx, uint8_t const pau8TxData[], uint32_t u32Size, uint32_t u32Timeout);
en_result_t I2C_Receive(M4_I2C_TypeDef* I2Cx, uint8_t pau8RxData[], uint32_t u32Size, uint32_t u32Timeout);
en_result_t I2C_Stop(M4_I2C_TypeDef* I2Cx, uint32_t u32Timeout);
en_result_t I2C_MasterReceiveAndStop(M4_I2C_TypeDef* I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout);
/**
* @}
*/
#endif /* DDL_I2C_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_I2C_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_icg.h
* @brief This file contains all the Macro Definitions of the ICG driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_ICG_H__
#define __HC32F4A0_ICG_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_ICG
* @{
*/
#if (DDL_ICG_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup ICG_Global_Macros ICG Global Macros
* @{
*/
/**
* @defgroup ICG_SWDT_Reset_State ICG SWDT Reset State
* @{
*/
#define ICG_SWDT_RESET_AUTOSTART (0UL) /*!< SWDT Auto Start after reset */
#define ICG_SWDT_RESET_STOP (ICG_ICG0_SWDTAUTS) /*!< SWDT stop after reset */
/**
* @}
*/
/**
* @defgroup ICG_SWDT_Trigger_Type ICG SWDT Trigger Type
* @{
*/
#define ICG_SWDT_TRIG_INT (0UL) /*!< SWDT trigger interrupt */
#define ICG_SWDT_TRIG_RESET (ICG_ICG0_SWDTITS) /*!< SWDT trigger reset */
/**
* @}
*/
/**
* @defgroup ICG_SWDT_Counter_Cycle ICG SWDT Counter Cycle
* @{
*/
#define ICG_SWDT_COUNTER_CYCLE_256 (0UL) /*!< 256 clock cycle */
#define ICG_SWDT_COUNTER_CYCLE_4096 (ICG_ICG0_SWDTPERI_0) /*!< 4096 clock cycle */
#define ICG_SWDT_COUNTER_CYCLE_16384 (ICG_ICG0_SWDTPERI_1) /*!< 16384 clock cycle */
#define ICG_SWDT_COUNTER_CYCLE_65536 (ICG_ICG0_SWDTPERI) /*!< 65536 clock cycle */
/**
* @}
*/
/**
* @defgroup ICG_SWDT_Clock_Division ICG SWDT Clock Division
* @{
*/
#define ICG_SWDT_CLOCK_DIV1 (0UL) /*!< SWDTCLK */
#define ICG_SWDT_CLOCK_DIV16 (ICG_ICG0_SWDTCKS_2) /*!< SWDTCLK/16 */
#define ICG_SWDT_CLOCK_DIV32 (ICG_ICG0_SWDTCKS_2 | ICG_ICG0_SWDTCKS_0) /*!< SWDTCLK/32 */
#define ICG_SWDT_CLOCK_DIV64 (ICG_ICG0_SWDTCKS_2 | ICG_ICG0_SWDTCKS_1) /*!< SWDTCLK/64 */
#define ICG_SWDT_CLOCK_DIV128 (ICG_ICG0_SWDTCKS_2 | ICG_ICG0_SWDTCKS_1 | ICG_ICG0_SWDTCKS_0) /*!< SWDTCLK/128 */
#define ICG_SWDT_CLOCK_DIV256 (ICG_ICG0_SWDTCKS_3) /*!< SWDTCLK/256 */
#define ICG_SWDT_CLOCK_DIV2048 (ICG_ICG0_SWDTCKS_3 | ICG_ICG0_SWDTCKS_1 | ICG_ICG0_SWDTCKS_0) /*!< SWDTCLK/2048 */
/**
* @}
*/
/**
* @defgroup ICG_SWDT_Refresh_Range ICG SWDT Refresh Range
* @{
*/
#define ICG_SWDT_RANGE_0TO100PCT (0UL) /*!< 0%~100% */
#define ICG_SWDT_RANGE_0TO25PCT (ICG_ICG0_SWDTWDPT_0) /*!< 0%~25% */
#define ICG_SWDT_RANGE_25TO50PCT (ICG_ICG0_SWDTWDPT_1) /*!< 25%~50% */
#define ICG_SWDT_RANGE_0TO50PCT (ICG_ICG0_SWDTWDPT_1 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~50% */
#define ICG_SWDT_RANGE_50TO75PCT (ICG_ICG0_SWDTWDPT_2) /*!< 50%~75% */
#define ICG_SWDT_RANGE_0TO25PCT_50TO75PCT (ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~25% & 50%~75% */
#define ICG_SWDT_RANGE_25TO75PCT (ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_1)) /*!< 25%~75% */
#define ICG_SWDT_RANGE_0TO75PCT (ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_1 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~75% */
#define ICG_SWDT_RANGE_75TO100PCT (ICG_ICG0_SWDTWDPT_3) /*!< 75%~100% */
#define ICG_SWDT_RANGE_0TO25PCT_75TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~25% & 75%~100% */
#define ICG_SWDT_RANGE_25TO50PCT_75TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_1)) /*!< 25%~50% & 75%~100% */
#define ICG_SWDT_RANGE_0TO50PCT_75TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_1 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~50% & 75%~100% */
#define ICG_SWDT_RANGE_50TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_2)) /*!< 50%~100% */
#define ICG_SWDT_RANGE_0TO25PCT_50TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~25% & 50%~100% */
#define ICG_SWDT_RANGE_25TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_1)) /*!< 25%~100% */
/**
* @}
*/
/**
* @defgroup ICG_SWDT_LPM_Count ICG SWDT Low Power Mode Count
* @brief SWDT count control in the sleep/stop mode
* @{
*/
#define ICG_SWDT_LPM_COUNT_CONTINUE (0UL) /*!< SWDT count continue in the sleep/stop mode */
#define ICG_SWDT_LPM_COUNT_STOP (ICG_ICG0_SWDTSLPOFF) /*!< SWDT count stop in the sleep/stop mode */
/**
* @}
*/
/**
* @defgroup ICG_WDT_Reset_State ICG WDT Reset State
* @{
*/
#define ICG_WDT_RESET_AUTOSTART (0UL) /*!< WDT Auto Start after reset */
#define ICG_WDT_RESET_STOP (ICG_ICG0_WDTAUTS) /*!< WDT stop after reset */
/**
* @}
*/
/**
* @defgroup ICG_WDT_Trigger_Type ICG WDT Trigger Type
* @{
*/
#define ICG_WDT_TRIG_INT (0UL) /*!< WDT trigger interrupt */
#define ICG_WDT_TRIG_RESET (ICG_ICG0_WDTITS) /*!< WDT trigger reset */
/**
* @}
*/
/**
* @defgroup ICG_WDT_Counter_Cycle ICG WDT Counter Cycle
* @{
*/
#define ICG_WDT_COUNTER_CYCLE_256 (0UL) /*!< 256 clock cycle */
#define ICG_WDT_COUNTER_CYCLE_4096 (ICG_ICG0_WDTPERI_0) /*!< 4096 clock cycle */
#define ICG_WDT_COUNTER_CYCLE_16384 (ICG_ICG0_WDTPERI_1) /*!< 16384 clock cycle */
#define ICG_WDT_COUNTER_CYCLE_65536 (ICG_ICG0_WDTPERI) /*!< 65536 clock cycle */
/**
* @}
*/
/**
* @defgroup ICG_WDT_Clock_Division ICG WDT Clock Division
* @{
*/
#define ICG_WDT_CLOCK_DIV4 (ICG_ICG0_WDTCKS_1) /*!< PCLK3/4 */
#define ICG_WDT_CLOCK_DIV64 (ICG_ICG0_WDTCKS_2 | ICG_ICG0_WDTCKS_1) /*!< PCLK3/64 */
#define ICG_WDT_CLOCK_DIV128 (ICG_ICG0_WDTCKS_2 | ICG_ICG0_WDTCKS_1 | ICG_ICG0_WDTCKS_0) /*!< PCLK3/128 */
#define ICG_WDT_CLOCK_DIV256 (ICG_ICG0_WDTCKS_3) /*!< PCLK3/256 */
#define ICG_WDT_CLOCK_DIV512 (ICG_ICG0_WDTCKS_3 | ICG_ICG0_WDTCKS_0) /*!< PCLK3/512 */
#define ICG_WDT_CLOCK_DIV1024 (ICG_ICG0_WDTCKS_3 | ICG_ICG0_WDTCKS_1) /*!< PCLK3/1024 */
#define ICG_WDT_CLOCK_DIV2028 (ICG_ICG0_WDTCKS_3 | ICG_ICG0_WDTCKS_1 | ICG_ICG0_WDTCKS_0) /*!< PCLK3/2048 */
#define ICG_WDT_CLOCK_DIV8192 (ICG_ICG0_WDTCKS_3 | ICG_ICG0_WDTCKS_2 | ICG_ICG0_WDTCKS_0) /*!< PCLK3/8192 */
/**
* @}
*/
/**
* @defgroup ICG_WDT_Refresh_Range ICG WDT Refresh Range
* @{
*/
#define ICG_WDT_RANGE_0TO100PCT (0UL) /*!< 0%~100% */
#define ICG_WDT_RANGE_0TO25PCT (ICG_ICG0_WDTWDPT_0) /*!< 0%~25% */
#define ICG_WDT_RANGE_25TO50PCT (ICG_ICG0_WDTWDPT_1) /*!< 25%~50% */
#define ICG_WDT_RANGE_0TO50PCT (ICG_ICG0_WDTWDPT_1 | ICG_ICG0_WDTWDPT_0) /*!< 0%~50% */
#define ICG_WDT_RANGE_50TO75PCT (ICG_ICG0_WDTWDPT_2) /*!< 50%~75% */
#define ICG_WDT_RANGE_0TO25PCT_50TO75PCT (ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_0) /*!< 0%~25% & 50%~75% */
#define ICG_WDT_RANGE_25TO75PCT (ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_1) /*!< 25%~75% */
#define ICG_WDT_RANGE_0TO75PCT (ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_1 | ICG_ICG0_WDTWDPT_0) /*!< 0%~75% */
#define ICG_WDT_RANGE_75TO100PCT (ICG_ICG0_WDTWDPT_3) /*!< 75%~100% */
#define ICG_WDT_RANGE_0TO25PCT_75TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_0) /*!< 0%~25% & 75%~100% */
#define ICG_WDT_RANGE_25TO50PCT_75TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_1) /*!< 25%~50% & 75%~100% */
#define ICG_WDT_RANGE_0TO50PCT_75TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_1 | ICG_ICG0_WDTWDPT_0) /*!< 0%~50% & 75%~100% */
#define ICG_WDT_RANGE_50TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_2) /*!< 50%~100% */
#define ICG_WDT_RANGE_0TO25PCT_50TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_0) /*!< 0%~25% & 50%~100% */
#define ICG_WDT_RANGE_25TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_1) /*!< 25%~100% */
/**
* @}
*/
/**
* @defgroup ICG_WDT_LPM_Count ICG WDT Low Power Mode Count
* @brief WDT count control in the sleep mode
* @{
*/
#define ICG_WDT_LPM_COUNT_CONTINUE (0UL) /*!< WDT count continue in the sleep mode */
#define ICG_WDT_LPM_COUNT_STOP (ICG_ICG0_WDTSLPOFF) /*!< WDT count stop in the sleep mode */
/**
* @}
*/
/**
* @defgroup ICG_HRC_Frequency_Select ICG HRC Frequency Select
* @{
*/
#define ICG_HRC_FREQ_20MHZ (0UL) /*!< HRC frequency 20MHZ */
#define ICG_HRC_FREQ_16MHZ (ICG_ICG1_HRCFREQSEL) /*!< HRC frequency 16MHZ */
/**
* @}
*/
/**
* @defgroup ICG_HRC_Reset_State ICG HRC Reset State
* @{
*/
#define ICG_HRC_RESET_OSCILLATION (0UL) /*!< HRC Oscillation after reset */
#define ICG_HRC_RESET_STOP (ICG_ICG1_HRCSTOP) /*!< HRC stop after reset */
/**
* @}
*/
/**
* @defgroup ICG_BOR_Voltage_Threshold ICG BOR Voltage Threshold
* @{
*/
#define ICG_BOR_VOL_THRESHOLD_1P9 (0UL) /*!< BOR voltage threshold 1.9V */
#define ICG_BOR_VOL_THRESHOLD_2P0 (ICG_ICG1_BOR_LEV_0) /*!< BOR voltage threshold 2.0V */
#define ICG_BOR_VOL_THRESHOLD_2P1 (ICG_ICG1_BOR_LEV_1) /*!< BOR voltage threshold 2.1V */
#define ICG_BOR_VOL_THRESHOLD_2P3 (ICG_ICG1_BOR_LEV) /*!< BOR voltage threshold 2.3V */
/**
* @}
*/
/**
* @defgroup ICG_BOR_Reset_State ICG BOR Reset State
* @{
*/
#define ICG_BOR_RESET_ENABLE (0UL) /*!< Enable BOR voltage detection after reset */
#define ICG_BOR_RESET_DISABLE (ICG_ICG1_BORDIS) /*!< Disable BOR voltage detection after reset */
/**
* @}
*/
/**
* @defgroup ICG_FLASH_Bank_Reset_State ICG FLASH Bank Reset State
* @{
*/
#define ICG_FLASH_BANK_1 (0xFFFFFFFFUL) /*!< After reset, 1MBytes flash are provided by bank0 */
#define ICG_FLASH_BANK_12 (0x004B4B4BUL) /*!< After reset, 1MBytes flash are provided by bank0 and bank1 with 512Bytes each */
/**
* @}
*/
/**
* @defgroup ICG_FLASH_Protect_Reset_State ICG FLASH Protect Reset State
* @brief Enable or disable D-BUS read protection for addresses 0x00000000 - 0x0001FFFF
* @{
*/
#define ICG_FLASH_PROTECT_RESET_ENABLE (0x00004450UL) /*!< Enable D-BUS read protection after reset */
#define ICG_FLASH_PROTECT_RESET_DISABLE (0xFFFFFFFFUL) /*!< Disable D-BUS read protection after reset */
/**
* @}
*/
/**
* @}
*/
/**
* @defgroup ICG_Register_Configuration ICG Register Configuration
* @{
*/
/**
*******************************************************************************
* @defgroup ICG_SWDT_Preload_Configuration ICG SWDT Preload Configuration
* @{
*******************************************************************************
*/
/* SWDT register config */
#define ICG0_RB_SWDT_AUTS (ICG_SWDT_RESET_STOP)
#define ICG0_RB_SWDT_ITS (ICG_SWDT_TRIG_INT)
#define ICG0_RB_SWDT_PERI (ICG_SWDT_COUNTER_CYCLE_65536)
#define ICG0_RB_SWDT_CKS (ICG_SWDT_CLOCK_DIV2048)
#define ICG0_RB_SWDT_WDPT (ICG_SWDT_RANGE_0TO100PCT)
#define ICG0_RB_SWDT_SLTPOFF (ICG_SWDT_LPM_COUNT_CONTINUE)
/* SWDT register value */
#define ICG0_RB_SWDT_CONFIG (ICG0_RB_SWDT_AUTS | ICG0_RB_SWDT_ITS | \
ICG0_RB_SWDT_PERI | ICG0_RB_SWDT_CKS | \
ICG0_RB_SWDT_WDPT | ICG0_RB_SWDT_SLTPOFF)
/**
* @}
*/
/**
*******************************************************************************
* @defgroup ICG_WDT_Preload_Configuration ICG WDT Preload Configuration
* @{
*******************************************************************************
*/
/* WDT register config */
#define ICG0_RB_WDT_AUTS (ICG_WDT_RESET_STOP)
#define ICG0_RB_WDT_ITS (ICG_WDT_TRIG_INT)
#define ICG0_RB_WDT_PERI (ICG_WDT_COUNTER_CYCLE_65536)
#define ICG0_RB_WDT_CKS (ICG_WDT_CLOCK_DIV8192)
#define ICG0_RB_WDT_WDPT (ICG_WDT_RANGE_0TO100PCT)
#define ICG0_RB_WDT_SLTPOFF (ICG_WDT_LPM_COUNT_CONTINUE)
/* WDT register value */
#define ICG0_RB_WDT_CONFIG (ICG0_RB_WDT_AUTS | ICG0_RB_WDT_ITS | \
ICG0_RB_WDT_PERI | ICG0_RB_WDT_CKS | \
ICG0_RB_WDT_WDPT | ICG0_RB_WDT_SLTPOFF)
/**
* @}
*/
/**
*******************************************************************************
* @defgroup ICG_HRC_Preload_Configuration ICG HRC Preload Configuration
* @{
*******************************************************************************
*/
/* HRC register config */
#define ICG1_RB_HRC_FREQSEL (ICG_HRC_FREQ_16MHZ)
#define ICG1_RB_HRC_STOP (ICG_HRC_RESET_STOP)
/* HRC register value */
#define ICG1_RB_HRC_CONFIG (ICG1_RB_HRC_FREQSEL | ICG1_RB_HRC_STOP)
/**
* @}
*/
/**
*******************************************************************************
* @defgroup ICG_BOR_Preload_Configuration ICG BOR Preload Configuration
* @{
*******************************************************************************
*/
/* BOR register config */
#define ICG1_RB_BOR_LEV (ICG_BOR_VOL_THRESHOLD_2P3)
#define ICG1_RB_BOR_DIS (ICG_BOR_RESET_DISABLE)
/* BOR register value */
#define ICG1_RB_BOR_CONFIG (ICG1_RB_BOR_LEV | ICG1_RB_BOR_DIS)
/**
* @}
*/
/**
*******************************************************************************
* @defgroup ICG_FLASH_Bank_Preload_Configuration ICG FLASH Bank Preload Configuration
* @{
*******************************************************************************
*/
/* FLASH Bank register value */
#define ICG2_RB_FLASH_BANK_CONFIG (ICG_FLASH_BANK_1)
/**
* @}
*/
/**
*******************************************************************************
* @defgroup ICG_FLASH_Protect_Preload_Configuration ICG FLASH Protect Preload Configuration
* @{
*******************************************************************************
*/
/* FLASH Read Protect register value */
#define ICG3_RB_FLASH_PROTECT_CONFIG (ICG_FLASH_PROTECT_RESET_DISABLE)
/**
* @}
*/
/**
* @}
*/
/**
* @defgroup ICG_Register_Value ICG Register Value
* @{
*/
/* ICG register value */
#define ICG_REG_CFG0_CONSTANT (ICG0_RB_WDT_CONFIG | ICG0_RB_SWDT_CONFIG | 0xE000E000UL)
#define ICG_REG_CFG1_CONSTANT (ICG1_RB_BOR_CONFIG | ICG1_RB_HRC_CONFIG | 0xFFF8FEFEUL)
#define ICG_REG_CFG2_CONSTANT (ICG2_RB_FLASH_BANK_CONFIG | 0xFF000000UL)
#define ICG_REG_CFG3_CONSTANT (ICG3_RB_FLASH_PROTECT_CONFIG | 0xFFFF0000UL)
/* ICG reserved value */
#define ICG_RESERVED_CONSTANT (0xFFFFFFFFUL)
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
#endif /* DDL_ICG_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_ICG_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_keyscan.h
* @brief This file contains all the functions prototypes of the KEYSCAN driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Zhangxl First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_KEYSCAN_H__
#define __HC32F4A0_KEYSCAN_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_KEYSCAN
* @{
*/
#if (DDL_KEYSCAN_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup KEYSCAN_Global_Types KEYSCAN Global Types
* @{
*/
/**
* @brief KEYSCAN configuration
*/
typedef struct
{
uint32_t u32HizCycle; /*!< Specifies the KEYSCAN Hiz cycles.
This parameter can be a value of @ref KEYSCAN_Hiz_Cycle_Sel */
uint32_t u32LowCycle; /*!< Specifies the KEYSCAN low cycles.
This parameter can be a value of @ref KEYSCAN_Low_Cycle_Sel */
uint32_t u32KeyClk; /*!< Specifies the KEYSCAN low cycles.
This parameter can be a value of @ref KEYSCAN_Clock_Sel */
uint32_t u32KeyOut; /*!< Specifies the KEYSCAN low cycles.
This parameter can be a value of @ref KEYSCAN_Keyout_Sel */
uint32_t u32KeyIn; /*!< Specifies the KEYSCAN low cycles.
This parameter can be a value of @ref KEYSCAN_Keyin_Sel */
} stc_keyscan_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup KEYSCAN_Global_Macros KEYSCAN Global Macros
* @{
*/
/**
* @defgroup KEYSCAN_Hiz_Cycle_Sel KEYSCAN Hiz cycles during low ouput selection
* @{
*/
#define KEYSCAN_HIZ_CLC_4 (0x00UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 4 cycles during low ouput */
#define KEYSCAN_HIZ_CLC_8 (0x01UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 8 cycles during low ouput */
#define KEYSCAN_HIZ_CLC_16 (0x02UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 16 cycles during low ouput */
#define KEYSCAN_HIZ_CLC_32 (0x03UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 32 cycles during low ouput */
#define KEYSCAN_HIZ_CLC_64 (0x04UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 64 cycles during low ouput */
#define KEYSCAN_HIZ_CLC_256 (0x05UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 256 cycles during low ouput */
#define KEYSCAN_HIZ_CLC_512 (0x06UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 512 cycles during low ouput */
#define KEYSCAN_HIZ_CLC_1024 (0x07UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 1024 cycles during low ouput */
/**
* @}
*/
/**
* @defgroup KEYSCAN_Low_Cycle_Sel KEYSCAN low level output cycles selection
* @{
*/
#define KEYSCAN_LOW_CLC_4 (0x02UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^2=4 cycles */
#define KEYSCAN_LOW_CLC_8 (0x03UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^3=8 cycles */
#define KEYSCAN_LOW_CLC_16 (0x04UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^4=16 cycles */
#define KEYSCAN_LOW_CLC_32 (0x05UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^5=32 cycles */
#define KEYSCAN_LOW_CLC_64 (0x06UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^6=64 cycles */
#define KEYSCAN_LOW_CLC_128 (0x07UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^7=128 cycles */
#define KEYSCAN_LOW_CLC_256 (0x08UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^8=256 cycles */
#define KEYSCAN_LOW_CLC_512 (0x09UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^9=512 cycles */
#define KEYSCAN_LOW_CLC_1K (0x0AUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^10=1K cycles */
#define KEYSCAN_LOW_CLC_2K (0x0BUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^11=2K cycles */
#define KEYSCAN_LOW_CLC_4K (0x0CUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^12=4K cycles */
#define KEYSCAN_LOW_CLC_8K (0x0DUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^13=8K cycles */
#define KEYSCAN_LOW_CLC_16K (0x0EUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^14=16K cycles */
#define KEYSCAN_LOW_CLC_32K (0x0FUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^15=32K cycles */
#define KEYSCAN_LOW_CLC_64K (0x10UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^16=64K cycles */
#define KEYSCAN_LOW_CLC_128K (0x11UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^17=128K cycles */
#define KEYSCAN_LOW_CLC_256K (0x12UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^18=256K cycles */
#define KEYSCAN_LOW_CLC_512K (0x13UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^19=512K cycles */
#define KEYSCAN_LOW_CLC_1M (0x14UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^20=1M cycles */
#define KEYSCAN_LOW_CLC_2M (0x15UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^21=2M cycles */
#define KEYSCAN_LOW_CLC_4M (0x16UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^22=4M cycles */
#define KEYSCAN_LOW_CLC_8M (0x17UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^23=8M cycles */
#define KEYSCAN_LOW_CLC_16M (0x18UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^24=16M cycles */
/**
* @}
*/
/**
* @defgroup KEYSCAN_Clock_Sel KEYSCAN scan clock selection
* @{
*/
#define KEYSCAN_CLK_HCLK (0x00UL) /*!< Use as HCLK KEYSCAN clock */
#define KEYSCAN_CLK_LRC (KEYSCAN_SCR_CKSEL_0) /*!< Use as LRC KEYSCAN clock */
#define KEYSCAN_CLK_XTAL32 (KEYSCAN_SCR_CKSEL_1) /*!< Use as XTAL32 KEYSCAN clock */
/**
* @}
*/
/**
* @defgroup KEYSCAN_Keyout_Sel KEYSCAN keyout pins selection
* @{
*/
#define KEYSCAN_OUT_0T1 (0x01UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 1 are selected */
#define KEYSCAN_OUT_0T2 (0x02UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 2 are selected */
#define KEYSCAN_OUT_0T3 (0x03UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 3 are selected */
#define KEYSCAN_OUT_0T4 (0x04UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 4 are selected */
#define KEYSCAN_OUT_0T5 (0x05UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 5 are selected */
#define KEYSCAN_OUT_0T6 (0x06UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 6 are selected */
#define KEYSCAN_OUT_0T7 (0x07UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 7 are selected */
/**
* @}
*/
/**
* @defgroup KEYSCAN_Keyin_Sel KEYSCAN keyin pins selection
* @{
*/
#define KEYSCAN_IN_0 (KEYSCAN_SCR_KEYINSEL_0) /*!< KEYIN(EIRQ) 0 is selected */
#define KEYSCAN_IN_1 (KEYSCAN_SCR_KEYINSEL_1) /*!< KEYIN(EIRQ) 1 is selected */
#define KEYSCAN_IN_2 (KEYSCAN_SCR_KEYINSEL_2) /*!< KEYIN(EIRQ) 2 is selected */
#define KEYSCAN_IN_3 (KEYSCAN_SCR_KEYINSEL_3) /*!< KEYIN(EIRQ) 3 is selected */
#define KEYSCAN_IN_4 (KEYSCAN_SCR_KEYINSEL_4) /*!< KEYIN(EIRQ) 4 is selected */
#define KEYSCAN_IN_5 (KEYSCAN_SCR_KEYINSEL_5) /*!< KEYIN(EIRQ) 5 is selected */
#define KEYSCAN_IN_6 (KEYSCAN_SCR_KEYINSEL_6) /*!< KEYIN(EIRQ) 6 is selected */
#define KEYSCAN_IN_7 (KEYSCAN_SCR_KEYINSEL_7) /*!< KEYIN(EIRQ) 7 is selected */
#define KEYSCAN_IN_8 (KEYSCAN_SCR_KEYINSEL_8) /*!< KEYIN(EIRQ) 8 is selected */
#define KEYSCAN_IN_9 (KEYSCAN_SCR_KEYINSEL_9) /*!< KEYIN(EIRQ) 9 is selected */
#define KEYSCAN_IN_10 (KEYSCAN_SCR_KEYINSEL_10) /*!< KEYIN(EIRQ) 10 is selected */
#define KEYSCAN_IN_11 (KEYSCAN_SCR_KEYINSEL_11) /*!< KEYIN(EIRQ) 11 is selected */
#define KEYSCAN_IN_12 (KEYSCAN_SCR_KEYINSEL_12) /*!< KEYIN(EIRQ) 12 is selected */
#define KEYSCAN_IN_13 (KEYSCAN_SCR_KEYINSEL_13) /*!< KEYIN(EIRQ) 13 is selected */
#define KEYSCAN_IN_14 (KEYSCAN_SCR_KEYINSEL_14) /*!< KEYIN(EIRQ) 14 is selected */
#define KEYSCAN_IN_15 (KEYSCAN_SCR_KEYINSEL_15) /*!< KEYIN(EIRQ) 15 is selected */
#define KEYSCAN_IN_MASK (KEYSCAN_SCR_KEYINSEL) /*!< KEYIN(EIRQ) mask */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup KEYSCAN_Global_Functions
* @{
*/
/**
* @brief Get KEYOUT index.
* @param None.
* @retval uint32_t: KEYOUT index 0~7.
*/
__STATIC_INLINE uint32_t KEYSCAN_GetKeyoutIdx(void)
{
return READ_REG32_BIT(M4_KEYSCAN->SSR, KEYSCAN_SSR_INDEX);
}
en_result_t KEYSCAN_StructInit(stc_keyscan_init_t *pstcKeyscanInit);
en_result_t KEYSCAN_Init(const stc_keyscan_init_t *pstcKeyscanInit);
void KEYSCAN_Cmd(en_functional_state_t enNewState);
/**
* @}
*/
#endif /* DDL_KEYSCAN_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_KEYSCAN_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_pwc.h
* @brief This file contains all the functions prototypes of the PWC driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Zhangxl First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_PWC_H__
#define __HC32F4A0_PWC_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_PWC
* @{
*/
#if (DDL_PWC_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup PWC_Global_Types PWC Global Types
* @{
*/
typedef struct
{
uint32_t u32RamCtrl; /*!< Internal RAM power setting. */
uint32_t u32PRamCtrl; /*!< Peripheral RAM power setting. */
uint16_t u16RamMode; /*!< RAM setting for Operating mode, @ref PWC_RAM_Config for details */
} stc_pwc_ram_config_t;
typedef struct
{
uint8_t u8PvdEn; /*!< PVD function setting, @ref PWC_PVD_Config for details */
uint8_t u8Pvd2ExtInEn; /*!< PVD2 ext. pin input function setting, @ref PWC_PVD2_ExtIn_Config */
uint8_t u8PvdCmpOutEn; /*!< PVD compare output function setting, @ref PWC_PVD_CMP_Config for details */
uint8_t u8PvdIntRstSel; /*!< PVD interrupt or reset selection, @ref PWC_PVD_IntRst_Sel for details */
uint8_t u8PvdIntRstEn; /*!< PVD interrupt or reset function setting, @ref PWC_PVD_IR_Config for details */
uint8_t u8FilterEn; /*!< PVD digital filter function setting, @ref PWC_PVD_DF_Config for details */
uint8_t u8FilterClk; /*!< PVD digital filter clock setting, @ref PWC_PVD_DFS_Clk_Sel for details */
uint8_t u8PvdVoltage; /*!< PVD detect voltage setting, @ref PWC_PVD_detection_Vol for details */
uint8_t u8PvdNmiEn; /*!< PVD NMI function setting, @ref PWC_PVD_Int_Mode_Config for details */
uint8_t u8PvdTrigger; /*!< PVD trigger setting, @ref PWC_PVD_Trigger_Sel for details */
} stc_pwc_pvd_config_t;
typedef struct
{
uint8_t u8PDMode; /*!< Power down mode, @ref PWC_PDMode_Sel for details. */
uint8_t u8IOState; /*!< IO state in power down mode, @ref PWC_PDMode_IO_Sel for details. */
uint8_t u8WkUpSpeed; /*!< Wakeup speed selection, @ref PWC_PDMode_WKUP_TIME_Sel for details. */
}stc_pwc_pd_mode_config_t;
typedef struct
{
uint8_t u8StopDrv; /*!< Stop mode drive capacity, @ref PWC_STOP_DRV_Sel for details. */
uint16_t u16ExBusHold; /*!< Exbus status in stop mode, @ref PWC_STOP_EXBUS_Sel for details. */
uint16_t u16ClkKeep; /*!< System clock setting after wake-up from stop mode,
@ref PWC_STOP_CLK_Sel for details. */
uint16_t u16FlashWait; /*!< Waiting flash stable after wake-up from stop mode,
@ref STOP_FLASH_WAIT_Sel for details. */
} stc_pwc_stop_mode_config;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup PWC_Global_Macros PWC Global Macros
* @{
*/
/**
* @defgroup PWC_PDMode_Sel Power down mode selection
* @{
*/
#define PWC_PD_MODE1 (0x00U) /*!< Power down mode 0 */
#define PWC_PD_MODE2 (0x01U) /*!< Power down mode 1 */
#define PWC_PD_MODE3 (0x02U) /*!< Power down mode 2 */
#define PWC_PD_MODE4 (0x03U) /*!< Power down mode 3 */
/**
* @}
*/
/**
* @defgroup PWC_PDMode_IO_Sel IO state config in Power down mode
* @{
*/
#define PWC_PD_IO_STATE1 (0x00U) /*!< IO state retain in PD mode and configurable after wakeup */
#define PWC_PD_IO_STATE2 (PWC_PWRC0_IORTN_0) /*!< IO state retain in PD mode and configurable after wakeup & set IORTN[1:0]=00b */
#define PWC_PD_IO_STATE3 (PWC_PWRC0_IORTN_1) /*!< IO state switch to HiZ */
/**
* @}
*/
/**
* @defgroup PWC_STOP_DRV_Sel Drive capacity while enter stop mode
* @{
*/
#define PWC_STOP_DRV_HIGH (0x00U) /*!< Enter stop mode from high speed mode */
#define PWC_STOP_DRV_LOW (PWC_PWRC1_STPDAS) /*!< Enter stop mode from ultra low speed mode */
/**
* @}
*/
/**
* @defgroup PWC_STOP_EXBUS_Sel ExBus status while enter stop mode
* @{
*/
#define PWC_STOP_EXBUS_HIZ (0x00U) /*!< Ex-Bus Hiz in stop mode */
#define PWC_STOP_EXBUS_HOLD (PWC_STPMCR_EXBUSOE) /*!< Ex-Bus keep in stop mode */
/**
* @}
*/
/**
* @defgroup PWC_STOP_CLK_Sel System clock setting after wake-up from stop mode
* @{
*/
#define PWC_STOP_CLK_KEEP (0x00U) /*!< Keep System clock setting after wake-up from stop mode */
#define PWC_STOP_CLK_MRC (PWC_STPMCR_CKSMRC) /*!< System clock switch to MRC after wake-up from stop mode */
/**
* @}
*/
/**
* @defgroup STOP_FLASH_WAIT_Sel Whether wait flash stable or not after wake-up from stop mode
* @{
*/
#define PWC_STOP_FLASH_WAIT (0x00U) /*!< Wait flash stable after wake-up from stop mode */
#define PWC_STOP_FLASH_NOWAIT (PWC_STPMCR_FLNWT) /*!< Don't wait flash stable after wake-up from stop mode */
/**
* @}
*/
/**
* @defgroup PWC_PWR_DRV_Sel Drive capacity selection
* @{
*/
#define PWC_NOR_DRV_HIGH (PWC_PWRC2_DVS) /*!< Drive capacity in high speed operation */
#define PWC_NOR_DRV_LOW (PWC_PWRC2_DVS_1) /*!< Drive capacity in ultra low speed operation */
/**
* @}
*/
/**
* @defgroup PWC_PDMode_WKUP_TIME_Sel Wakeup speed config in Power down mode
* @{
*/
#define PWC_PD_WKUP_SLOW (0x00U) /*!< VCAP1/VCAP2 = 0.1uF x2 or 0.22uF x1 */
#define PWC_PD_WKUP_FAST (0x01U) /*!< VCAP1/VCAP2 = 0.047uF x2 or 0.1uF x1 */
/**
* @}
*/
/**
* @defgroup PWC_RAM_Config Operating mode for RAM Config
* @{
*/
#define PWC_RAM_HIGH (0x8043U) /*!< MCU operating under high frequency (lower than 240MHz) */
#define PWC_RAM_LOW (0x9062U) /*!< MCU operating under ultra low frequency (lower than 8MHz) */
/**
* @}
*/
/**
* @defgroup PWC_PWMON_Config PWC Power Monitor Config
* @{
*/
#define PWC_PWRMON_ON (PWC_PWRC_PWMONE)
#define PWC_PWRMON_OFF (0x00U)
/**
* @}
*/
/**
* @defgroup PWC_PWMON_Sel PWC Power Monitor Selection
* @{
*/
#define PWC_PWRMON_VINREF (0x00U) /*!< Internal reference voltage */
#define PWC_PWRMON_VOTS (PWC_PWRC_PWMONSEL) /*!< temperature sensor voltage */
/**
* @}
*/
/**
* @defgroup PWC_DRV_Sel PWC Driver ability selection
* @{
*/
#define PWC_DRV_LOW (0x00U) /*!< system clock = 32kHz */
#define PWC_DRV_HIGH (0x07U) /*!< system clock < 48Mhz */
/**
* @}
*/
/**
* @defgroup PWC_PVD_Channel PWC PVD channel
* @{
*/
#define PWC_PVD_CH1 (0x00U)
#define PWC_PVD_CH2 (0x01U)
/**
* @}
*/
/**
* @defgroup PWC_PVD_Config PWC PVD Config
* @{
*/
#define PWC_PVD_ON (0x01U)
#define PWC_PVD_OFF (0x00U)
/**
* @}
*/
/**
* @defgroup PWC_PVD2_ExtIn_Config PWC PVD2 external input Config
* @{
*/
#define PWC_PVD2_EXINP_ON (PWC_PVDCR0_EXVCCINEN)
#define PWC_PVD2_EXINP_OFF (0x00U)
/**
* @}
*/
/**
* @defgroup PWC_PVD_IR_Config PWC PVD Interrupt/Reset Config
* @{
*/
#define PWC_PVD_IR_ON (PWC_PVDCR1_PVD1IRE)
#define PWC_PVD_IR_OFF (0x00U)
/**
* @}
*/
/**
* @defgroup PWC_PVD_IntRst_Sel set PVD to interrupt or reset
* @{
*/
#define PWC_PVD_INT (0x00U)
#define PWC_PVD_RST (PWC_PVDCR1_PVD1IRS)
/**
* @}
*/
/**
* @defgroup PWC_PVD_CMP_Config PWC PVD Compare Config
* @{
*/
#define PWC_PVD_CMP_ON (PWC_PVDCR1_PVD1CMPOE)
#define PWC_PVD_CMP_OFF (0x00U)
/**
* @}
*/
/**
* @defgroup PWC_PVD_DF_Config PVD digital filter ON or OFF
* @{
*/
#define PWC_PVD_DF_ON (0x00U)
#define PWC_PVD_DF_OFF (PWC_PVDFCR_PVD1NFDIS)
/**
* @}
*/
/**
* @defgroup PWC_PVD_DFS_Clk_Sel PVD digital filter sample ability
* @note modified this value must when PWC_PVD_DF_OFF
* @{
*/
#define PWC_PVD_DFS_DIV4 (0x00U) /*!< 0.25 LRC cycle */
#define PWC_PVD_DFS_DIV2 (PWC_PVDFCR_PVD1NFCKS_0) /*!< 0.5 LRC cycle */
#define PWC_PVD_DFS_DIV1 (PWC_PVDFCR_PVD1NFCKS_1) /*!< 1 LRC cycle */
#define PWC_PVD_DFS_MUL2 (PWC_PVDFCR_PVD1NFCKS) /*!< 2 LRC cycles */
/**
* @}
*/
/**
* @defgroup PWC_PVD_detection_Vol PWC PVD Detection voltage
* @{
*/
#define PWC_PVD1_2V0_PVD2_2V1 (0x00U) /*!< Specifies the voltage of PVD1 is 2.0V or PVD2 is 2.0V. */
#define PWC_PVD1_2V1_PVD2_2V3 (0x01U) /*!< Specifies the voltage of PVD1 is 2.1V or PVD2 is 2.1V. */
#define PWC_PVD1_2V3_PVD2_2V5 (0x02U) /*!< Specifies the voltage of PVD1 is 2.3V or PVD2 is 2.3V. */
#define PWC_PVD1_2V5_PVD2_2V6 (0x03U) /*!< Specifies the voltage of PVD1 is 2.5V or PVD2 is 2.5V. */
#define PWC_PVD1_2V6_PVD2_2V7 (0x04U) /*!< Specifies the voltage of PVD1 is 2.6V or PVD2 is 2.6V. */
#define PWC_PVD1_2V7_PVD2_2V8 (0x05U) /*!< Specifies the voltage of PVD1 is 2.7V or PVD2 is 2.7V. */
#define PWC_PVD1_2V8_PVD2_2V9 (0x06U) /*!< Specifies the voltage of PVD1 is 2.8V or PVD2 is 2.8V. */
#define PWC_PVD1_2V9_PVD2_1V1 (0x07U) /*!< Specifies the voltage of PVD1 is 2.9V or PVD2 is 1.1V (only ext. input). */
/**
* @}
*/
/**
* @defgroup PWC_PVD_Int_Mode_Config PVD interrupt set to maskable or non_maskable
* @{
*/
#define PWC_PVD_INT_MASK (PWC_PVDICR_PVD1NMIS)
#define PWC_PVD_INT_NONMASK (0x00U)
/**
* @}
*/
/**
* @defgroup PWC_PVD_Trigger_Sel PVD trigger setting
* @{
*/
#define PWC_PVD_TRIGGER_FALLING (0x00U)
#define PWC_PVD_TRIGGER_RISING (PWC_PVDICR_PVD1EDGS_0)
#define PWC_PVD_TRIGGER_BOTH (PWC_PVDICR_PVD1EDGS_1)
/**
* @}
*/
/**
* @defgroup PWC_WKUP_Event_Sel Power down mode wakeup event selection
* @{
*/
#define PWC_PD_WKUP_TRIG_PVD1 (PWC_PDWKES_VD1EGS)
#define PWC_PD_WKUP_TRIG_PVD2 (PWC_PDWKES_VD2EGS)
#define PWC_PD_WKUP_TRIG_WKP0 (PWC_PDWKES_WK0EGS)
#define PWC_PD_WKUP_TRIG_WKP1 (PWC_PDWKES_WK1EGS)
#define PWC_PD_WKUP_TRIG_WKP2 (PWC_PDWKES_WK2EGS)
#define PWC_PD_WKUP_TRIG_WKP3 (PWC_PDWKES_WK3EGS)
#define PWC_PD_WKUP_TRIG_MASK (PWC_PDWKES_VD1EGS | PWC_PDWKES_VD2EGS | \
PWC_PDWKES_WK0EGS | PWC_PDWKES_WK1EGS | \
PWC_PDWKES_WK2EGS | PWC_PDWKES_WK3EGS)
/**
* @}
*/
/**
* @defgroup PWC_WKUP_Trigger_Edge_Sel Power down mode wakeup trigger edge selection
* @{
*/
#define PWC_PD_WKUP_FALLING (0x00U)
#define PWC_PD_WKUP_RISING (0x01U)
/**
* @}
*/
/**
* @defgroup PWC_DBGC_config PWC Debug Config
* @{
*/
#define PWC_AD_INTERN_REF (0x00U)
#define PWC_AD_VBAT_DIV2 (0x01U)
/**
* @}
*/
/**
* @defgroup PWC_VBAT_Voltage_Status PWC VBAT Voltage Status
* @{
*/
#define PWC_VOL_VBAT_MORE_THAN_VBATREF (0x00U) /*!< Vbat > VbatREF */
#define PWC_VOL_VBAT_LESS_THAN_VBATREF (0x01U) /*!< Vbat < VbatREF */
/**
* @}
*/
/**
* @defgroup PWC_VBAT_Reference_Voltage PWC VBAT Reference Voltage
* @{
*/
#define PWC_VBAT_REF_VOL_1P8V (0x00U) /*!< Vbat reference voltage is 1.8V */
#define PWC_VBAT_REF_VOL_2P0V (0x01U) /*!< Vbat reference voltage is 2.0V */
/**
* @}
*/
/**
* @defgroup PWC_BACKUP_RAM_Flag PWC Backup RAM Flag
* @{
*/
#define PWC_BACKUP_RAM_FLAG_RAMPDF (PWC_VBATCR_RAMPDF) /*!< Backup RAM power down flag */
#define PWC_BACKUP_RAM_FLAG_RAMVALID (PWC_VBATCR_RAMVALID) /*!< Backup RAM read/write flag */
/**
* @}
*/
/**
* @defgroup PWC_WKT_Clock_Source PWC WKT Clock Source
* @{
*/
#define PWC_WKT_CLK_SRC_64HZ (0U) /*!< 64Hz Clock */
#define PWC_WKT_CLK_SRC_XTAL32 (PWC_WKTC2_WKCKS_0) /*!< XTAL32 Clock */
#define PWC_WKT_CLK_SRC_RTCLRC (PWC_WKTC2_WKCKS_1) /*!< RTCLRC Clock */
/**
* @}
*/
/**
* @defgroup PWC_REG_Write_Unlock_Code PWC register unlock code.
* @brief Lock/unlock Code for each module
* PWC_UNLOCK_CODE_0:
* Below registers are locked in CLK module.
* XTALCFGR, XTALSTBCR, XTALCR, XTALSTDCR, XTALSTDSR, HRCTRM, HRCCR,
* MRCTRM, MRCCR, PLLCFGR, PLLCR, UPLLCFGR, UPLLCR, OSCSTBSR, CKSWR,
* SCFGR, UFSCKCFGR, TPIUCKCFGR, MCO1CFGR, MCO2CFGR, XTAL32CR,
* XTALC32CFGR, XTAL32NFR, LRCCR, LRCTRM.
* PWC_UNLOCK_CODE_1:
* Below registers are locked in PWC module.
* PWRC0, PWRC1, PWRC2, PWRC3, PDWKE0, PDWKE1, PDWKE2, PDWKES, PDWKF0,
* PDWKF1, PWCMR, PWR_STPMCR, RAMPC0, RAMOPM.
* Below registers are locked in CLK module.
* PERICKSEL, I2SCKSEL,
* Below register is locked in RMU module.
* RSTF0
* PWC_UNLOCK_CODE_2:
* Below registers are locked in PWC module.
* PVDCR0, PVDCR1, PVDFCR, PVDLCR, PVDICR, PVDDSR
* @{
*/
#define PWC_UNLOCK_CODE_0 (0xA501U)
#define PWC_UNLOCK_CODE_1 (0xA502U)
#define PWC_UNLOCK_CODE_2 (0xA508U)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup PWC_Global_Functions
* @{
*/
/**
* @brief Lock PWC, CLK, RMU register.
* @param [in] u16Module Lock code for each module.
* @arg PWC_UNLOCK_CODE_0:
* Below registers are locked in CLK module.
* XTALCFGR, XTALSTBCR, XTALCR, XTALSTDCR, XTALSTDSR, HRCTRM, HRCCR,
* MRCTRM, MRCCR, PLLCFGR, PLLCR, UPLLCFGR, UPLLCR, OSCSTBSR, CKSWR,
* SCFGR, UFSCKCFGR, TPIUCKCFGR, MCO1CFGR, MCO2CFGR, XTAL32CR,
* XTALC32CFGR, XTAL32NFR, LRCCR, LRCTRM.
* @arg PWC_UNLOCK_CODE_1:
* Below registers are locked in PWC module.
* PWRC0, PWRC1, PWRC2, PWRC3, PDWKE0, PDWKE1, PDWKE2, PDWKES, PDWKF0,
* PDWKF1, PWCMR, PWR_STPMCR, RAMPC0, RAMOPM.
* Below registers are locked in VBAT module.
* RSTR, BATCR0, VBTBKR0~VBTBK127.
* Below registers are locked in CLK module.
* PERICKSEL, I2SCKSEL,
* Below register is locked in RMU module.
* RSTF0
* @arg PWC_UNLOCK_CODE_2:
* Below registers are locked in PWC module.
* PVDCR0, PVDCR1, PVDFCR, PVDLCR, PVDICR, PVDDSR
* @retval None
*/
__STATIC_INLINE void PWC_Lock(uint16_t u16Module)
{
M4_PWC->FPRC = (0xA500U | (uint16_t)((uint16_t)(~u16Module) & (M4_PWC->FPRC)));
}
/**
* @brief Unlock PWC, CLK, RMU register.
* @param [in] u16Module Unlock code for each module.
* @arg PWC_UNLOCK_CODE_0:
* Below registers are unlocked in CLK module.
* XTALCFGR, XTALSTBCR, XTALCR, XTALSTDCR, XTALSTDSR, HRCTRM, HRCCR,
* MRCTRM, MRCCR, PLLCFGR, PLLCR, UPLLCFGR, UPLLCR, OSCSTBSR, CKSWR,
* SCFGR, UFSCKCFGR, TPIUCKCFGR, MCO1CFGR, MCO2CFGR, XTAL32CR,
* XTALC32CFGR, XTAL32NFR, LRCCR, LRCTRM.
* @arg PWC_UNLOCK_CODE_1:
* Below registers are unlocked in PWC module.
* PWRC0, PWRC1, PWRC2, PWRC3, PDWKE0, PDWKE1, PDWKE2, PDWKES, PDWKF0,
* PDWKF1, PWCMR, PWR_STPMCR, RAMPC0, RAMOPM.
* Below registers are unlocked in VBAT module.
* RSTR, BATCR0, VBTBKR0~VBTBK127.
* Below registers are unlocked in CLK module.
* PERICKSEL, I2SCKSEL,
* Below register is unlocked in RMU module.
* RSTF0
* @arg PWC_UNLOCK_CODE_2:
* Below registers are unlocked in PWC module.
* PVDCR0, PVDCR1, PVDFCR, PVDLCR, PVDICR, PVDDSR
* @retval None
*/
__STATIC_INLINE void PWC_Unlock(uint16_t u16Module)
{
SET_REG16_BIT(M4_PWC->FPRC, u16Module);
}
/**
* @brief Lock PWC_FCG0 register .
* @param None
* @retval None
*/
__STATIC_INLINE void PWC_FCG0_Lock(void)
{
WRITE_REG32(M4_PWC->FCG0PC, 0xA5A50000UL);
}
/**
* @brief Unlock PWR_FCG0 register.
* @param None
* @retval None
* @note Call this function before PWC_Fcg0PeriphClockCmd()
*/
__STATIC_INLINE void PWC_FCG0_Unlock(void)
{
WRITE_REG32(M4_PWC->FCG0PC, 0xA5A50001UL);
}
en_result_t PWC_PowerDownStructInit(stc_pwc_pd_mode_config_t *pstcPDModeConfig);
en_result_t PWC_PowerDownConfig(const stc_pwc_pd_mode_config_t *pstcPDModeConfig);
void PWC_EnterPowerDownMode(void);
void PWC_EnterStopMode(void);
void PWC_EnterSleepMode(void);
en_result_t PWC_StopStructInit(stc_pwc_stop_mode_config *pstcStopConfig);
en_result_t PWC_StopConfig(const stc_pwc_stop_mode_config *pstcStopConfig);
void PWC_StopDrvConfig(uint8_t u8StopDrv);
void PWC_StopClockKeepConfig(uint16_t u16ClkKeep);
void PWC_StopFlashWaitConfig(uint16_t u16FlashWait);
void PWC_StopExBusHoldConfig(uint16_t u16ExBusHold);
en_result_t PWC_HighSpeedToLowSpeed(void);
en_result_t PWC_LowSpeedToHighSpeed(void);
void PWC_HrcPwrCmd(en_functional_state_t enNewState);
void PWC_PllPwrCmd(en_functional_state_t enNewState);
void PWC_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState);
void PWC_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState);
void PWC_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState);
void PWC_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState);
en_result_t PWC_RamConfig(const stc_pwc_ram_config_t *pstcRamConfig);
en_result_t PWC_PVD_Init(uint8_t u8Ch, const stc_pwc_pvd_config_t *pstcPvdConfig);
en_result_t PWC_PVD_StructInit(stc_pwc_pvd_config_t *pstcPvdConfig);
en_flag_status_t PWC_PVD_GetStatus(uint8_t u8Flag);
void PWC_PVD_ClearStatus(void);
void PWC_PdWakeup0Cmd(uint8_t u8Wkup0Evt, en_functional_state_t enNewState);
void PWC_PdWakeup1Cmd(uint8_t u8Wkup1Evt, en_functional_state_t enNewState);
void PWC_PdWakeup2Cmd(uint8_t u8Wkup2Evt, en_functional_state_t enNewState);
void PWC_PdWakeupTrigConfig(uint8_t u8WkupEvt, uint8_t u8TrigEdge);
en_flag_status_t PWC_GetWakeup0Status(uint8_t u8Flag);
en_flag_status_t PWC_GetWakeup1Status(uint8_t u8Flag);
void PWC_AdcBufCmd(en_functional_state_t enNewState);
void PWC_AdcInternVolSel(uint8_t u8AdcInternVol);
void PWC_VBAT_MonitorVolSel(uint8_t u8RefVol);
void PWC_VBAT_MonitorCmd(en_functional_state_t enNewState);
uint8_t PWC_VBAT_GetVolStatus(void);
void PWC_VBAT_MeasureVolCmd(en_functional_state_t enNewState);
void PWC_VBAT_Reset(void);
void PWC_VBAT_PwrCmd(en_functional_state_t enNewState);
void PWC_BkRamPwrCmd(en_functional_state_t enNewState);
en_flag_status_t PWC_GetBkRamStatus(uint8_t u8Flag);
void PWC_WriteBackupReg(uint8_t u8RegNum, uint8_t u8RegVal);
uint8_t PWC_ReadBackupReg(uint8_t u8RegNum);
void PWC_WKT_Init(uint8_t u8ClkSrc, uint16_t u16CmpVal);
void PWC_WKT_SetCompareValue(uint16_t u16CmpVal);
uint16_t PWC_WKT_GetCompareValue(void);
void PWC_WKT_Cmd(en_functional_state_t enNewState);
en_flag_status_t PWC_WKT_GetStatus(void);
void PWC_WKT_ClearStatus(void);
/**
* @}
*/
#endif /* DDL_PWC_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_PWC_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_sram.c
* @brief This file provides firmware functions to manage the SRAM.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Wuze First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32f4a0_sram.h"
#include "hc32f4a0_utility.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @defgroup DDL_SRAM SRAM
* @brief SRAM Driver Library
* @{
*/
#if (DDL_SRAM_ENABLE == DDL_ON)
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup SRAM_Local_Macros SRAM Local Macros
* @{
*/
/**
* @defgroup SRAM_Configuration_Bits_Mask SRAM Configuration Bits Mask
* @{
*/
#define SRAM_ECC_MODE_MSK (SRAMC_CKCR_ECCMOD)
#define SRAM_CYCLE_MSK (SRAMC_WTCR_SRAM123RWT)
/**
* @}
*/
/**
* @defgroup SRAM_Check_Parameters_Validity SRAM check parameters validity
* @{
*/
#define IS_SRAM_ERR_OP(x) \
( ((x) == SRAM_ERR_OP_NMI) || \
((x) == SRAM_ERR_OP_RESET))
#define IS_SRAM_CYCLE(x) \
( ((x) <= SRAM_WAIT_CYCLE_7))
#define IS_SRAM_ECC_MODE(x) \
( ((x) == SRAM_ECC_MODE_INVALID) || \
((x) == SRAM_ECC_MODE_1) || \
((x) == SRAM_ECC_MODE_2) || \
((x) == SRAM_ECC_MODE_3))
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup SRAM_Global_Functions SRAM Global Functions
* @{
*/
/**
* @brief Initializes SRAM.
* @param None
* @retval None
*/
void SRAM_Init(void)
{
SET_REG32_BIT(M4_SRAMC->CKSR, SRAM_FLAG_ALL);
}
/**
* @brief De-initializes SRAM. Reset the registers of SRAM.
* @param None
* @retval None
* @note Call SRAM_WTCR_Unlock to unlock register WTCR and SRAM_CKCR_Unlock to unlock register CKCR first.
*/
void SRAM_DeInit(void)
{
/* Call SRAM_WTCR_Unlock to unlock register WTCR. */
DDL_ASSERT(M4_SRAMC->WTPR == SRAM_UNLOCK_CMD);
/* Call SRAM_CKCR_Unlock to unlock register CKCR. */
DDL_ASSERT(M4_SRAMC->CKPR == SRAM_UNLOCK_CMD);
WRITE_REG32(M4_SRAMC->WTCR, 0U);
WRITE_REG32(M4_SRAMC->CKCR, 0U);
SET_REG32_BIT(M4_SRAMC->CKSR, SRAM_FLAG_ALL);
}
/**
* @brief Set access wait cycle for SRAM(s).
* @param [in] u32SramIndex The SRAM(s) index bit mask.
* This parameter can be values of @ref SRAM_Index_Bit_Mask
* @arg SRAM_SRAMH: SRAMH.
* @arg SRAM_SRAM123: SRAM1, SRAM2 and SRAM3. When the CPU clock frequency is higher
* than 200MHz, access wait cycle is needed.
* @arg SRAM_SRAM4: SRAM4. When the CPU clock frequency is higher than 200MHz,
* access wait cycle is needed.
* @arg SRAM_SRAMB: SRAMB. When the CPU clock frequency is higher than 120MHz,
* access wait cycle is needed.
* @param [in] u32WriteCycle The write access wait cycle for the specified SRAM(s)
* This parameter can be a value of @ref SRAM_Access_Wait_Cycle
* @arg SRAM_WAIT_CYCLE_0: Wait 0 CPU cycle.
* @arg SRAM_WAIT_CYCLE_1: Wait 1 CPU cycle.
* @arg SRAM_WAIT_CYCLE_2: Wait 2 CPU cycles.
* @arg SRAM_WAIT_CYCLE_3: Wait 3 CPU cycles.
* @arg SRAM_WAIT_CYCLE_4: Wait 4 CPU cycles.
* @arg SRAM_WAIT_CYCLE_5: Wait 5 CPU cycles.
* @arg SRAM_WAIT_CYCLE_6: Wait 6 CPU cycles.
* @arg SRAM_WAIT_CYCLE_7: Wait 7 CPU cycles.
* @param [in] u32ReadCycle The read access wait cycle for the specified SRAM(s)
* This parameter can be a value of @ref SRAM_Access_Wait_Cycle
* The arguments are same as u32WriteCycle.
* @retval None
* @note Call SRAM_WTCR_Unlock to unlock register WTCR first.
*/
void SRAM_SetWaitCycle(uint32_t u32SramIndex, uint32_t u32WriteCycle, uint32_t u32ReadCycle)
{
uint8_t i;
uint8_t u8OfsWt;
uint8_t u8OfsRd;
uint32_t au32SramList[4U] = {SRAM_SRAM123, SRAM_SRAM4, SRAM_SRAMH, SRAM_SRAMB};
DDL_ASSERT(IS_SRAM_CYCLE(u32WriteCycle));
DDL_ASSERT(IS_SRAM_CYCLE(u32ReadCycle));
DDL_ASSERT(M4_SRAMC->WTPR == SRAM_UNLOCK_CMD);
for (i=0U; i<4U; i++)
{
if ((u32SramIndex & au32SramList[i]) != 0U)
{
u8OfsWt = i << 3U;
u8OfsRd = u8OfsWt + 4U;
MODIFY_REG32(M4_SRAMC->WTCR,
((SRAM_CYCLE_MSK << u8OfsWt) | (SRAM_CYCLE_MSK << u8OfsRd)),
((u32WriteCycle << u8OfsWt) | (u32ReadCycle << u8OfsRd)));
}
}
}
/**
* @brief Set ECC mode for SRAM4 and SRAMB.
* @param [in] u32SramIndex The SRAM(s) index bit mask.This function is used to set the
* ECC mode of SRAM4 and SRAMB, so u32SramIndex must contain
* SRAM_SRAM4 or SRAM_SRAMB or both, from @ref SRAM_Index_Bit_Mask
* @param [in] u32EccMode The ECC mode of SRAM4 and SRAMB.
* This parameter can be a value of @ref SRAM_ECC_Mode
* @arg SRAM_ECC_MODE_INVALID: The ECC mode is invalid.
* @arg SRAM_ECC_MODE_1: When 1-bit error occurred:
* ECC error corrects.
* No 1-bit-error status flag setting, no interrupt or reset.
* When 2-bit error occurred:
* ECC error detects.
* 2-bit-error status flag sets and interrupt or reset occurred.
* @arg SRAM_ECC_MODE_2: When 1-bit error occurred:
* ECC error corrects.
* 1-bit-error status flag sets, no interrupt or reset.
* When 2-bit error occurred:
* ECC error detects.
* 2-bit-error status flag sets and interrupt or reset occurred.
* @arg SRAM_ECC_MODE_3: When 1-bit error occurred:
* ECC error corrects.
* 1-bit-error status flag sets and interrupt or reset occurred.
* When 2-bit error occurred:
* ECC error detects.
* 2-bit-error status flag sets and interrupt or reset occurred.
* @retval None
* @note Call SRAM_CKCR_Unlock to unlock register CKCR first.
*/
void SRAM_SetEccMode(uint32_t u32SramIndex, uint32_t u32EccMode)
{
DDL_ASSERT(IS_SRAM_ECC_MODE(u32EccMode));
DDL_ASSERT(M4_SRAMC->CKPR == SRAM_UNLOCK_CMD);
if ((u32SramIndex & SRAM_SRAM4) != 0U)
{
MODIFY_REG32(M4_SRAMC->CKCR, SRAM_ECC_MODE_MSK, u32EccMode);
}
if ((u32SramIndex & SRAM_SRAMB) != 0U)
{
MODIFY_REG32(M4_SRAMC->CKCR, SRAM_ECC_MODE_MSK<<2U, u32EccMode<<2U);
}
}
/**
* @brief Set the operation which is operated after check error occurred.
* @param [in] u32SramIndex The SRAM(s) index bit mask.
* This parameter can be values of @ref SRAM_Index_Bit_Mask
* @arg SRAM_SRAMH: SRAMH.
* @arg SRAM_SRAM123: SRAM1, SRAM2 and SRAM3.
* @arg SRAM_SRAM4: SRAM4.
* @arg SRAM_SRAMB: SRAMB.
* @param [out] u32OpAfterError The operation after check error occurred.
* This parameter can be a value of @ref SRAM_Operation_After_Check_Error
* @arg SRAM_ERR_OP_NMI: Check error generates NMI(non-maskable interrupt).
* @arg SRAM_ERR_OP_RESET: Check error generates system reset.
* @retval None
* @note Call SRAM_CKCR_Unlock to unlock register CKCR first.
*/
void SRAM_SetErrOperation(uint32_t u32SramIndex, uint32_t u32OpAfterError)
{
DDL_ASSERT(IS_SRAM_ERR_OP(u32OpAfterError));
DDL_ASSERT(M4_SRAMC->CKPR == SRAM_UNLOCK_CMD);
if ((u32SramIndex & (SRAM_SRAM123 | SRAM_SRAMH)) != 0U)
{
WRITE_REG32(bM4_SRAMC->CKCR_b.PYOAD, u32OpAfterError);
}
if ((u32SramIndex & SRAM_SRAM4) != 0U)
{
WRITE_REG32(bM4_SRAMC->CKCR_b.ECCOAD, u32OpAfterError);
}
if ((u32SramIndex & SRAM_SRAMB) != 0U)
{
WRITE_REG32(bM4_SRAMC->CKCR_b.BECCOAD, u32OpAfterError);
}
}
/**
* @brief Get the status of the specified flag of SRAM.
* @param [in] u32Flag The flag of SRAM.
* This parameter can be a value of @ref SRAM_Check_Status_Flag
* @arg SRAM_FLAG_SRAM1_PYERR: SRAM1 parity error.
* @arg SRAM_FLAG_SRAM2_PYERR: SRAM2 parity error.
* @arg SRAM_FLAG_SRAM3_PYERR: SRAM3 parity error.
* @arg SRAM_FLAG_SRAMH_PYERR: SRAMH parity error.
* @arg SRAM_FLAG_SRAM4_1ERR: SRAM4 ECC 1-bit error.
* @arg SRAM_FLAG_SRAM4_2ERR: SRAM4 ECC 2-bit error.
* @arg SRAM_FLAG_SRAMB_1ERR: SRAMB ECC 1-bit error.
* @arg SRAM_FLAG_SRAMB_2ERR: SRAMB ECC 2-bit error.
* @arg SRAM_FLAG_CACHE_PYERR: Cache RAM parity error.
* @retval An en_flag_status_t enumeration type value.
* @arg Set: The specified flag is set.
* @arg Reset: The specified flag is not set.
*/
en_flag_status_t SRAM_GetStatus(uint32_t u32Flag)
{
en_flag_status_t enFlag = Reset;
if (READ_REG32_BIT(M4_SRAMC->CKSR, (u32Flag & SRAM_FLAG_ALL)) != 0U)
{
enFlag = Set;
}
return enFlag;
}
/**
* @brief Clear the status of the specified flag of SRAM.
* @param [in] u32Flag The flag of SRAM.
* This parameter can be a value(s) of @ref SRAM_Check_Status_Flag
* @arg SRAM_FLAG_SRAM1_PYERR: SRAM1 parity error.
* @arg SRAM_FLAG_SRAM2_PYERR: SRAM2 parity error.
* @arg SRAM_FLAG_SRAM3_PYERR: SRAM3 parity error.
* @arg SRAM_FLAG_SRAMH_PYERR: SRAMH parity error.
* @arg SRAM_FLAG_SRAM4_1ERR: SRAM4 ECC 1-bit error.
* @arg SRAM_FLAG_SRAM4_2ERR: SRAM4 ECC 2-bit error.
* @arg SRAM_FLAG_SRAMB_1ERR: SRAMB ECC 1-bit error.
* @arg SRAM_FLAG_SRAMB_2ERR: SRAMB ECC 2-bit error.
* @arg SRAM_FLAG_CACHE_PYERR: Cache RAM parity error.
* @retval None
*/
void SRAM_ClrStatus(uint32_t u32Flag)
{
SET_REG32_BIT(M4_SRAMC->CKSR, (u32Flag & SRAM_FLAG_ALL));
}
/**
* @}
*/
#endif /* DDL_SRAM_ENABLE */
/**
* @}
*/
/**
* @}
*/
/******************************************************************************
* EOF (not truncated)
*****************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_sram.h
* @brief This file contains all the functions prototypes of the SRAM driver
* library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Wuze First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_SRAM_H__
#define __HC32F4A0_SRAM_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_SRAM
* @{
*/
#if (DDL_SRAM_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup SRAM_Global_Macros SRAM Global Macros
* @{
*/
/**
* @defgroup SRAM_Index_Bit_Mask SRAM Index Bit Mask
* @{
*/
#define SRAM_SRAMH (1UL << 2U) /*!< 0x1FFE0000~0x1FFFFFFF, 128KB */
#define SRAM_SRAM123 (1UL << 0U) /*!< SRAM1: 0x20000000~0x2001FFFF, 128KB \
SRAM2: 0x20020000~0x2003FFFF, 128KB \
SRAM3: 0x20040000~0x20057FFF, 96KB */
#define SRAM_SRAM4 (1UL << 1U) /*!< 0x20058000~0x2005FFFF, 32KB */
#define SRAM_SRAMB (1UL << 3U) /*!< 0x200F0000~0x200F0FFF, 4KB */
#define SRAM_SRAM_ALL (SRAM_SRAMH | SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB)
/**
* @}
*/
/**
* @defgroup SRAM_Access_Wait_Cycle SRAM Access Wait Cycle
* @{
*/
#define SRAM_WAIT_CYCLE_0 (0U) /*!< Wait 0 CPU cycle. */
#define SRAM_WAIT_CYCLE_1 (1U) /*!< Wait 1 CPU cycle. */
#define SRAM_WAIT_CYCLE_2 (2U) /*!< Wait 2 CPU cycles. */
#define SRAM_WAIT_CYCLE_3 (3U) /*!< Wait 3 CPU cycles. */
#define SRAM_WAIT_CYCLE_4 (4U) /*!< Wait 4 CPU cycles. */
#define SRAM_WAIT_CYCLE_5 (5U) /*!< Wait 5 CPU cycles. */
#define SRAM_WAIT_CYCLE_6 (6U) /*!< Wait 6 CPU cycles. */
#define SRAM_WAIT_CYCLE_7 (7U) /*!< Wait 7 CPU cycles. */
/**
* @}
*/
/**
* @defgroup SRAM_Operation_After_Check_Error SRAM Operation After Check Error
* @note For: Even-parity check error of SRAM1, SRAM2, SRAM3 and SRAMH. ECC check error of SRAM4 and SRAMB.
* @{
*/
#define SRAM_ERR_OP_NMI (0U) /*!< Non-maskable interrupt occurres while check error occurres. */
#define SRAM_ERR_OP_RESET (SRAMC_CKCR_PYOAD) /*!< System reset occurres while check error occurres. */
/**
* @}
*/
/**
* @defgroup SRAM_ECC_Mode SRAM ECC Mode
* @note For: SRAM4 and SRAMB.
* @{
*/
#define SRAM_ECC_MODE_INVALID (0U) /*!< The ECC mode is invalid. */
#define SRAM_ECC_MODE_1 (SRAMC_CKCR_ECCMOD_0) /*!< When 1-bit error occurres: \
ECC error corrects. \
No 1-bit-error status flag setting, no interrupt or reset. \
When 2-bit error occurres: \
ECC error detects. \
2-bit-error status flag sets and interrupt or reset occurres. */
#define SRAM_ECC_MODE_2 (SRAMC_CKCR_ECCMOD_1) /*!< When 1-bit error occurres: \
ECC error corrects. \
1-bit-error status flag sets, no interrupt or reset. \
When 2-bit error occurres: \
ECC error detects. \
2-bit-error status flag sets and interrupt or reset occurres. */
#define SRAM_ECC_MODE_3 (SRAMC_CKCR_ECCMOD_1 | \
SRAMC_CKCR_ECCMOD_0) /*!< When 1-bit error occurres: \
ECC error corrects. \
1-bit-error status flag sets and interrupt or reset occurres. \
When 2-bit error occurres: \
ECC error detects. \
2-bit-error status flag sets and interrupt or reset occurres. */
/**
* @}
*/
/**
* @defgroup SRAM_Check_Status_Flag SRAM Check Status Flag
* @{
*/
#define SRAM_FLAG_SRAM1_PYERR (SRAMC_CKSR_SRAM1_PYERR) /*!< SRAM1 parity error. */
#define SRAM_FLAG_SRAM2_PYERR (SRAMC_CKSR_SRAM2_PYERR) /*!< SRAM2 parity error. */
#define SRAM_FLAG_SRAM3_PYERR (SRAMC_CKSR_SRAM3_PYERR) /*!< SRAM3 parity error. */
#define SRAM_FLAG_SRAMH_PYERR (SRAMC_CKSR_SRAMH_PYERR) /*!< SRAMH parity error. */
#define SRAM_FLAG_SRAM4_1ERR (SRAMC_CKSR_SRAM4_1ERR) /*!< SRAM4 ECC 1-bit error. */
#define SRAM_FLAG_SRAM4_2ERR (SRAMC_CKSR_SRAM4_2ERR) /*!< SRAM4 ECC 2-bit error. */
#define SRAM_FLAG_SRAMB_1ERR (SRAMC_CKSR_SRAMB_1ERR) /*!< SRAMB ECC 1-bit error. */
#define SRAM_FLAG_SRAMB_2ERR (SRAMC_CKSR_SRAMB_2ERR) /*!< SRAMB ECC 2-bit error. */
#define SRAM_FLAG_CACHE_PYERR (SRAMC_CKSR_CACHE_PYERR) /*!< Cache RAM parity error. */
#define SRAM_FLAG_ALL (0x1FFUL)
/**
* @}
*/
/**
* @defgroup SRAM_Register_Protect_Command SRAM Register Protect Command
* @{
*/
#define SRAM_LOCK_CMD (0x76U)
#define SRAM_UNLOCK_CMD (0x77U)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup SRAM_Global_Functions
* @{
*/
/**
* @brief Lock access wait cycle control register.
* @param None
* @retval None
*/
__STATIC_INLINE void SRAM_WTCR_Lock(void)
{
WRITE_REG32(M4_SRAMC->WTPR, SRAM_LOCK_CMD);
}
/**
* @brief Unlock access wait cycle control register.
* @param None
* @retval None
*/
__STATIC_INLINE void SRAM_WTCR_Unlock(void)
{
WRITE_REG32(M4_SRAMC->WTPR, SRAM_UNLOCK_CMD);
}
/**
* @brief Lock check control register.
* @param None
* @retval None
*/
__STATIC_INLINE void SRAM_CKCR_Lock(void)
{
WRITE_REG32(M4_SRAMC->CKPR, SRAM_LOCK_CMD);
}
/**
* @brief Unlock check control register.
* @param None
* @retval None
*/
__STATIC_INLINE void SRAM_CKCR_Unlock(void)
{
WRITE_REG32(M4_SRAMC->CKPR, SRAM_UNLOCK_CMD);
}
void SRAM_Init(void);
void SRAM_DeInit(void);
void SRAM_WTCR_Lock(void);
void SRAM_WTCR_Unlock(void);
void SRAM_CKCR_Lock(void);
void SRAM_CKCR_Unlock(void);
void SRAM_SetWaitCycle(uint32_t u32SramIndex, uint32_t u32WriteCycle, uint32_t u32ReadCycle);
void SRAM_SetEccMode(uint32_t u32SramIndex, uint32_t u32EccMode);
void SRAM_SetErrOperation(uint32_t u32SramIndex, uint32_t u32OpAfterError);
en_flag_status_t SRAM_GetStatus(uint32_t u32Flag);
void SRAM_ClrStatus(uint32_t u32Flag);
/**
* @}
*/
#endif /* DDL_SRAM_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_SRAM_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_usart.h
* @brief This file contains all the functions prototypes of the USART(Universal
* Synchronous/Asynchronous Receiver Transmitter) driver library.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Hongjh First version
2021-01-21 Hongjh 1. Add API:USART_StopModeNoiseFilterCmd
2. Refine macro-define group:USART_Stop_Mode_Noise_Filter_Width_Level
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_USART_H__
#define __HC32F4A0_USART_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_USART
* @{
*/
#if (DDL_USART_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup USART_Global_Types USART Global Types
* @{
*/
/**
* @brief UART mode initialization structure definition
*/
typedef struct
{
uint32_t u32Baudrate; /*!< UART baudrate. The baudrate is valid when clock source is PCLK. */
uint32_t u32ClkMode; /*!< Clock mode.
This parameter can be a value of @ref USART_Clock_Mode */
uint32_t u32PclkDiv; /*!< PCLK division. The PCLK division function is valid when clock source is PCLK.
This parameter can be a value of @ref USART_PCLK_Division */
uint32_t u32Parity; /*!< Parity format.
This parameter can be a value of @ref USART_Parity_Control */
uint32_t u32DataWidth; /*!< Data width.
This parameter can be a value of @ref USART_Data_Length_Bits */
uint32_t u32StopBit; /*!< Stop Bits.
This parameter can be a value of @ref USART_Stop_Bits */
uint32_t u32OversamplingBits; /*!< Oversampling Bits.
This parameter can be a value of @ref USART_Oversampling_Bits */
uint32_t u32BitDirection; /*!< Significant bit.
This parameter can be a value of @ref USART_Significant_Bit */
uint32_t u32NoiseFilterState; /*!< RX pin noise filter state.
This parameter can be a value of @ref USART_Noise_Filter_State */
uint32_t u32SbDetectPolarity; /*!< Start Bit Detect Polarity.
This parameter can be a value of @ref USART_Start_Bit_Detect_Polarity */
uint32_t u32HwFlowCtrl; /*!< Hardware flow control.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} stc_usart_uart_init_t;
/**
* @brief UART multiple-processor initialization structure definition
*/
typedef struct
{
uint32_t u32Baudrate; /*!< UART baudrate. The baudrate is valid when clock source is PCLK. */
uint32_t u32ClkMode; /*!< Clock mode.
This parameter can be a value of @ref USART_Clock_Mode */
uint32_t u32PclkDiv; /*!< PCLK division. The PCLK division function is valid when clock source is PCLK.
This parameter can be a value of @ref USART_PCLK_Division */
uint32_t u32DataWidth; /*!< Data width.
This parameter can be a value of @ref USART_Data_Length_Bits */
uint32_t u32StopBit; /*!< Stop Bits.
This parameter can be a value of @ref USART_Stop_Bits */
uint32_t u32OversamplingBits; /*!< Oversampling Bits.
This parameter can be a value of @ref USART_Oversampling_Bits */
uint32_t u32BitDirection; /*!< Significant bit.
This parameter can be a value of @ref USART_Significant_Bit */
uint32_t u32NoiseFilterState; /*!< RX pin noise filter state.
This parameter can be a value of @ref USART_Noise_Filter_State */
uint32_t u32SbDetectPolarity; /*!< Start Bit Detect Polarity.
This parameter can be a value of @ref USART_Start_Bit_Detect_Polarity */
uint32_t u32HwFlowCtrl; /*!< Hardware flow control.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} stc_usart_multiprocessor_init_t;
/**
* @brief LIN mode initialization structure definition
*/
typedef struct
{
uint32_t u32Baudrate; /*!< UART baudrate. The baudrate is valid when clock source is PCLK. */
uint32_t u32ClkMode; /*!< Clock mode.
This parameter can be a value of @ref USART_Clock_Mode */
uint32_t u32PclkDiv; /*!< PCLK division. The PCLK division function is valid when clock source is PCLK.
This parameter can be a value of @ref USART_PCLK_Division */
uint32_t u32BmcPclkDiv; /*!< BMC PCLK division. The PCLK division function is valid when clock source is PCLK.
This parameter can be a value of @ref USART_LIN_BMC_PCLK_Division */
uint32_t u32OversamplingBits; /*!< Oversampling Bits.
This parameter can be a value of @ref USART_Oversampling_Bits */
uint32_t u32DetectBreakLen; /*!< Detect break length.
This parameter can be a value of @ref USART_LIN_Detect_Break_Length */
uint32_t u32SendBreakLen; /*!< Send break length.
This parameter can be a value of @ref USART_LIN_Send_Break_Length */
uint32_t u32SendBreakMode; /*!< Send break mode.
This parameter can be a value of @ref USART_LIN_Send_Break_Mode */
} stc_usart_lin_init_t;
/**
* @brief Smart card mode initialization structure definition
*/
typedef struct
{
uint32_t u32Baudrate; /*!< UART baudrate */
uint32_t u32ClkMode; /*!< Clock mode.
This parameter can be a value of @ref USART_Clock_Mode */
uint32_t u32PclkDiv; /*!< PCLK division. The PCLK division function is valid when clock source is PCLK.
This parameter can be a value of @ref USART_PCLK_Division */
uint32_t u32StopBit; /*!< Stop Bits.
This parameter can be a value of @ref USART_Stop_Bits */
uint32_t u32BitDirection; /*!< Significant bit.
This parameter can be a value of @ref USART_Significant_Bit */
} stc_usart_smartcard_init_t;
/**
* @brief clock synchronization mode initialization structure definition
*/
typedef struct
{
uint32_t u32Baudrate; /*!< UART baudrate. The baudrate is valid when clock source is PCLK. */
uint32_t u32ClkMode; /*!< Clock mode.
This parameter can be a value of @ref USART_Clock_Mode */
uint32_t u32PclkDiv; /*!< PCLK division. The PCLK division function is valid when clock source is PCLK.
This parameter can be a value of @ref USART_PCLK_Division */
uint32_t u32BitDirection; /*!< Significant bit.
This parameter can be a value of @ref USART_Significant_Bit */
uint32_t u32HwFlowCtrl; /*!< Hardware flow control.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} stc_usart_clksync_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup USART_Global_Macros USART Global Macros
* @{
*/
/**
* @defgroup USART_Flag USART Flag
* @{
*/
#define USART_FLAG_PE (USART_SR_PE) /*!< Parity error flag */
#define USART_FLAG_FE (USART_SR_FE) /*!< Framing error flag */
#define USART_FLAG_ORE (USART_SR_ORE) /*!< Overrun error flag */
#define USART_FLAG_BE (USART_SR_BE) /*!< LIN bus error flag */
#define USART_FLAG_RXNE (USART_SR_RXNE) /*!< Receive data register not empty flag */
#define USART_FLAG_TC (USART_SR_TC) /*!< Transmission complete flag */
#define USART_FLAG_TXE (USART_SR_TXE) /*!< Transmit data register empty flag */
#define USART_FLAG_RTOF (USART_SR_RTOF) /*!< Receive timeout flag */
#define USART_FLAG_LBD (USART_SR_LBD) /*!< LIN break signal detection flag */
#define USART_FLAG_WKUP (USART_SR_WKUP) /*!< LIN wakeup signal detection flag */
#define USART_FLAG_MPB (USART_SR_MPB) /*!< Receive processor ID flag */
/**
* @}
*/
/**
* @defgroup USART_Transmission_Type USART Transmission Type
* @{
*/
#define USART_TRANSMISSION_ID (USART_DR_MPID)
#define USART_TRANSMISSION_DATA (0UL)
/**
* @}
*/
/**
* @defgroup USART_Clear_Flag USART Clear Flag
* @{
*/
#define USART_CLEAR_FLAG_PE (USART_CR1_CPE) /*!< Clear Parity error flag */
#define USART_CLEAR_FLAG_FE (USART_CR1_CFE) /*!< Clear Framing error flag */
#define USART_CLEAR_FLAG_ORE (USART_CR1_CORE) /*!< Clear Overrun error flag */
#define USART_CLEAR_FLAG_RTOF (USART_CR1_CRTOF) /*!< Clear RX timeout flag */
#define USART_CLEAR_FLAG_BE (USART_CR1_CBE) /*!< Clear LIN bus error flag */
#define USART_CLEAR_FLAG_WKUP (USART_CR1_CWKUP) /*!< Clear LIN wakeup signal flag */
#define USART_CLEAR_FLAG_LBD (USART_CR1_CLBD) /*!< Clear LIN break detection flag */
/**
* @}
*/
/**
* @defgroup USART_Transmit_Receive_Function USART Transmit/Receive Function
* @{
*/
#define USART_RX (USART_CR1_RE) /*!< USART RX function */
#define USART_TX (USART_CR1_TE) /*!< USART TX function */
#define USART_RTO (USART_CR1_RTOE) /*!< USART RX timerout function */
#define USART_INT_RX (USART_CR1_RIE) /*!< USART receive data register not empty && receive error interrupt */
#define USART_INT_TXE (USART_CR1_TXEIE) /*!< USART transmit data register empty interrupt */
#define USART_INT_TC (USART_CR1_TCIE) /*!< USART transmission complete interrupt */
#define USART_INT_RTO (USART_CR1_RTOIE) /*!< USART RX timerout interrupt */
/**
* @}
*/
/**
* @defgroup USART_LIN_Function USART LIN Function
* @{
*/
#define USART_LIN (USART_CR2_LINEN) /*!< USART LIN function */
#define USART_LIN_WKUP (USART_CR2_WKUPE) /*!< USART LIN wakeup signal detect function */
#define USART_LIN_INT_WKUP (USART_CR2_WKUPIE) /*!< USART LIN wakeup signal detect interrupt function */
#define USART_LIN_BUSERR (USART_CR2_BEE) /*!< USART LIN bus error detect function */
#define USART_LIN_INT_BUSERR (USART_CR2_BEIE) /*!< USART LIN bus error detect interrupt function */
#define USART_LIN_INT_BREAK (USART_CR2_LBDIE) /*!< USART LIN break field detect interrupt function */
/**
* @}
*/
/**
* @defgroup USART_Parity_Control USART Parity Control
* @{
*/
#define USART_PARITY_NONE (0UL) /*!< Parity control disabled */
#define USART_PARITY_EVEN (USART_CR1_PCE) /*!< Parity control enabled and Even Parity is selected */
#define USART_PARITY_ODD (USART_CR1_PCE | \
USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
/**
* @}
*/
/**
* @defgroup USART_Data_Length_Bits Data Length Bits
* @{
*/
#define USART_DATA_LENGTH_8BIT (0UL) /*!< 8 bits */
#define USART_DATA_LENGTH_9BIT (USART_CR1_M) /*!< 9 bits */
/**
* @}
*/
/**
* @defgroup USART_Oversampling_Bits USART Oversampling Bits
* @{
*/
#define USART_OVERSAMPLING_16BIT (0UL) /*!< Oversampling by 16 bits */
#define USART_OVERSAMPLING_8BIT (USART_CR1_OVER8) /*!< Oversampling by 8 bits */
/**
* @}
*/
/**
* @defgroup USART_Significant_Bit USART Significant Bit
* @{
*/
#define USART_LSB (0UL) /*!< LSB(Least Significant Bit) */
#define USART_MSB (USART_CR1_ML) /*!< MSB(Most Significant Bit) */
/**
* @}
*/
/**
* @defgroup USART_Noise_Filter_State USART Noise Filter State
* @{
*/
#define USART_NOISE_FILTER_DISABLE (0UL) /*!< Disable noise filter */
#define USART_NOISE_FILTER_ENABLE (USART_CR1_NFE) /*!< Enable noise filter */
/**
* @}
*/
/**
* @defgroup USART_Start_Bit_Detect_Polarity USART Start Bit Detect Polarity
* @{
*/
#define USART_SB_DETECT_LOW (0UL) /*!< Detect RX pin low level */
#define USART_SB_DETECT_FALLING (USART_CR1_SBS) /*!< Detect RX pin falling edge */
/**
* @}
*/
/**
* @defgroup USART_LIN_Send_Break_Mode USART LIN Send Break Mode
* @{
*/
#define USART_LIN_SEND_BREAK_MODE_SBK (0UL) /*!< Start send break after USART_CR2 SBK bit set 1 value */
#define USART_LIN_SEND_BREAK_MODE_TDR (USART_CR2_SBKM) /*!< Start send break after USART_DR TDR write 0x00 value */
/**
* @}
*/
/**
* @defgroup USART_Multiple_Processor_State USART Multiple Processor State
* @{
*/
#define USART_MULTIPLE_PROCESSOR_DISABLE (0UL) /*!< Disable multiple processor function */
#define USART_MULTIPLE_PROCESSOR_ENABLE (USART_CR2_MPE) /*!< Enable multiple processor function */
/**
* @}
*/
/**
* @defgroup USART_LIN_Detect_Break_Length USART LIN Detect Break Length
* @{
*/
#define USART_LIN_DETECT_BREAK_10BIT (0UL) /*!< Detect break 10-bit */
#define USART_LIN_DETECT_BREAK_11BIT (USART_CR2_LBDL) /*!< Detect break 11-bit */
/**
* @}
*/
/**
* @defgroup USART_LIN_Send_Break_Length USART LIN Send Break Length
* @{
*/
#define USART_LIN_SEND_BREAK_10BIT (0UL) /*!< Send break 10-bit */
#define USART_LIN_SEND_BREAK_11BIT (USART_CR2_SBKL_0) /*!< Send break 11-bit */
#define USART_LIN_SEND_BREAK_13BIT (USART_CR2_SBKL_1) /*!< Send break 13-bit */
#define USART_LIN_SEND_BREAK_14BIT (USART_CR2_SBKL) /*!< Send break 14-bit */
/**
* @}
*/
/**
* @defgroup USART_Clock_Mode USART Clock Mode Selection
* @{
*/
#define USART_EXTCLK (USART_CR2_CLKC_1) /*!< Select external clock source. */
#define USART_INTERNCLK_OUTPUT (USART_CR2_CLKC_0) /*!< Select internal clock source and output clock. */
#define USART_INTERNCLK_NONE_OUTPUT (0UL) /*!< Select internal clock source and don't output clock */
/**
* @}
*/
/**
* @defgroup USART_Stop_Bits USART Stop Bits
* @{
*/
#define USART_STOPBIT_1BIT (0UL) /*!< 1 stop bit */
#define USART_STOPBIT_2BIT (USART_CR2_STOP) /*!< 2 stop bit */
/**
* @}
*/
/**
* @defgroup USART_DUPLEX_SEL USART Half-duplex/Full-duplex Selection
* @{
*/
#define USART_FULLDUPLEX_MODE (0UL) /*!< USART full-duplex mode */
#define USART_HALFDUPLEX_MODE (USART_CR3_HDSEL) /*!< USART half-duplex mode */
/**
* @}
*/
/**
* @defgroup USART_Hardware_Flow_Control USART Hardware Flow Control RTS/CTS
* @{
*/
#define USART_HWFLOWCTRL_NONE (0UL) /*!< Disable USART hardware flow controle */
#define USART_HWFLOWCTRL_RTS (USART_CR3_RTSE) /*!< USART hardware flow control RTS mode */
#define USART_HWFLOWCTRL_CTS (USART_CR3_CTSE) /*!< USART hardware flow control CTS mode */
#define USART_HWFLOWCTRL_RTS_CTS (USART_CR3_RTSE | \
USART_CR3_CTSE) /*!< USART hardware flow control RTS and CTS mode */
/**
* @}
*/
/**
* @defgroup USART_Smartcard_ETU_Clock USART Smartcard ETU Clock
* @{
*/
#define USART_SC_ETU_CLK_32 (0UL) /*!< 1 etu = 32/f */
#define USART_SC_ETU_CLK_64 (USART_CR3_BCN_0) /*!< 1 etu = 64/f */
#define USART_SC_ETU_CLK_128 (USART_CR3_BCN_1 | \
USART_CR3_BCN_0) /*!< 1 etu = 128/f */
#define USART_SC_ETU_CLK_256 (USART_CR3_BCN_2 | \
USART_CR3_BCN_0) /*!< 1 etu = 256/f */
#define USART_SC_ETU_CLK_372 (USART_CR3_BCN_2 | \
USART_CR3_BCN_1) /*!< 1 etu = 372/f */
/**
* @}
*/
/**
* @defgroup USART_PCLK_Division USART PCLK Clock Prescaler Division
* @{
*/
#define USART_PCLK_DIV1 (0UL) /*!< PCLK */
#define USART_PCLK_DIV4 (USART_PR_PSC_0) /*!< PCLK/4 */
#define USART_PCLK_DIV16 (USART_PR_PSC_1) /*!< PCLK/16 */
#define USART_PCLK_DIV64 (USART_PR_PSC) /*!< PCLK/64 */
/**
* @}
*/
/**
* @defgroup USART_LIN_BMC_PCLK_Division USART LIN Baudrate Measure Counter PCLK Division
* @{
*/
#define USART_LIN_BMC_PCLK_DIV1 (0UL) /*!< PCLK */
#define USART_LIN_BMC_PCLK_DIV2 (USART_PR_LBMPSC_0) /*!< PCLK/2 */
#define USART_LIN_BMC_PCLK_DIV4 (USART_PR_LBMPSC_1) /*!< PCLK/4 */
#define USART_LIN_BMC_PCLK_DIV8 (USART_PR_LBMPSC) /*!< PCLK/8 */
/**
* @}
*/
/**
* @defgroup USART_Stop_Mode_Noise_Filter_Width_Level USART Stop Mode Noise Filter Width Level
* @{
*/
#define USART_STOP_MODE_FILTER_WIDTH_LEVEL_1 (0UL) /*!< Filter width level 1 */
#define USART_STOP_MODE_FILTER_WIDTH_LEVEL_2 (PERIC_USART1_NFC_USASRT1_NFS_0) /*!< Filter width level 2 */
#define USART_STOP_MODE_FILTER_WIDTH_LEVEL_3 (PERIC_USART1_NFC_USASRT1_NFS_1) /*!< Filter width level 3 */
#define USART_STOP_MODE_FILTER_WIDTH_LEVEL_4 (PERIC_USART1_NFC_USASRT1_NFS) /*!< Filter width level 4 */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup USART_Global_Functions
* @{
*/
en_result_t USART_UartInit(M4_USART_TypeDef *USARTx,
const stc_usart_uart_init_t *pstcInit);
en_result_t USART_HalfduplexInit(M4_USART_TypeDef *USARTx,
const stc_usart_uart_init_t *pstcInit);
en_result_t USART_UartStructInit(stc_usart_uart_init_t *pstcInit);
en_result_t USART_MultiProcessorInit(M4_USART_TypeDef *USARTx,
const stc_usart_multiprocessor_init_t *pstcInit);
en_result_t USART_MultiProcessorStructInit(stc_usart_multiprocessor_init_t *pstcInit);
en_result_t USART_LinInit(M4_USART_TypeDef *USARTx,
const stc_usart_lin_init_t *pstcInit);
en_result_t USART_LinStructInit(stc_usart_lin_init_t *pstcInit);
en_result_t USART_SmartcardInit(M4_USART_TypeDef *USARTx,
const stc_usart_smartcard_init_t *pstcInit);
en_result_t USART_SmartcardStructInit(stc_usart_smartcard_init_t *pstcInit);
en_result_t USART_ClkSyncInit(M4_USART_TypeDef *USARTx,
const stc_usart_clksync_init_t *pstcInit);
en_result_t USART_ClkSyncStructInit(stc_usart_clksync_init_t *pstcInit);
void USART_DeInit(M4_USART_TypeDef *USARTx);
void USART_FuncCmd(M4_USART_TypeDef *USARTx,
uint32_t u32Func,
en_functional_state_t enNewState);
en_functional_state_t USART_GetFuncState(const M4_USART_TypeDef *USARTx,
uint32_t u32Func);
en_flag_status_t USART_GetStatus(const M4_USART_TypeDef *USARTx,
uint32_t u32Flag);
void USART_ClearStatus(M4_USART_TypeDef *USARTx, uint32_t u32Flag);
void USART_SetTransmissionType(M4_USART_TypeDef *USARTx, uint32_t u32Type);
uint32_t USART_GetTransmissionType(const M4_USART_TypeDef *USARTx);
void USART_SetParity(M4_USART_TypeDef *USARTx, uint32_t u32Parity);
uint32_t USART_GetParity(const M4_USART_TypeDef *USARTx);
void USART_SetDataWidth(M4_USART_TypeDef *USARTx, uint32_t u32DataWidth);
uint32_t USART_GetDataWidth(const M4_USART_TypeDef *USARTx);
void USART_SetOversmaplingBits(M4_USART_TypeDef *USARTx,
uint32_t u32OversamplingBits);
uint32_t USART_GetOversmaplingBits(const M4_USART_TypeDef *USARTx);
void USART_SetBitDirection(M4_USART_TypeDef *USARTx, uint32_t u32BitDir);
uint32_t USART_GetBitDirection(const M4_USART_TypeDef *USARTx);
void USART_SetSbDetectPolarity(M4_USART_TypeDef *USARTx,
uint32_t u32Polarity);
uint32_t USART_GetSbDetectPolarity(const M4_USART_TypeDef *USARTx);
void USART_SetClockMode(M4_USART_TypeDef *USARTx, uint32_t u32ClkMode);
uint32_t USART_GetClockMode(const M4_USART_TypeDef *USARTx);
void USART_SetStopBits(M4_USART_TypeDef *USARTx, uint32_t u32StopBits);
uint32_t USART_GetStopBits(const M4_USART_TypeDef *USARTx);
uint16_t USART_RecData(const M4_USART_TypeDef *USARTx);
void USART_SendData(M4_USART_TypeDef *USARTx, uint16_t u16Data);
void USART_SendId(M4_USART_TypeDef *USARTx, uint16_t u16ID);
void USART_SilenceCmd(M4_USART_TypeDef *USARTx,
en_functional_state_t enNewState);
void USART_LinLoopCmd(M4_USART_TypeDef *USARTx,
en_functional_state_t enNewState);
void USART_LinRequestBreakSending(M4_USART_TypeDef *USARTx);
en_flag_status_t USART_GetLinRequestBreakStatus(const M4_USART_TypeDef *USARTx);
void USART_SetLinBreakMode(M4_USART_TypeDef *USARTx, uint32_t u32Mode);
uint32_t USART_GetLinBreakMode(const M4_USART_TypeDef *USARTx);
void USART_SetDuplexMode(M4_USART_TypeDef *USARTx, uint32_t u32Mode);
uint32_t USART_GetDuplexMode(const M4_USART_TypeDef *USARTx);
void USART_SetHwFlowCtrl(M4_USART_TypeDef *USARTx, uint32_t u32HwFlowCtrl);
uint32_t USART_GetHwFlowCtrl(const M4_USART_TypeDef *USARTx);
void USART_SetSmartcardEtuClk(M4_USART_TypeDef *USARTx,
uint32_t u32EtuClk);
uint32_t USART_GetSmartcardEtuClk(const M4_USART_TypeDef *USARTx);
void USART_SetPclkDiv(M4_USART_TypeDef *USARTx,
uint32_t u32PclkDiv);
uint32_t USART_GetPclkDiv(const M4_USART_TypeDef *USARTx);
void USART_SetLinBmcPclkDiv(M4_USART_TypeDef *USARTx,
uint32_t u32PclkDiv);
uint32_t USART_GetLinBmcPclkDiv(const M4_USART_TypeDef *USARTx);
void USART_StopModeNoiseFilterCmd(const M4_USART_TypeDef *USARTx,
en_functional_state_t enNewState);
void USART_SetStopModeNoiseFilter(const M4_USART_TypeDef *USARTx,
uint32_t u32Level);
uint32_t USART_GetStopModeNoiseFilter(const M4_USART_TypeDef *USARTx);
void USART_LinFuncCmd(M4_USART_TypeDef *USARTx,
uint32_t u32Func,
en_functional_state_t enNewState);
en_functional_state_t USART_GetLinFuncState(const M4_USART_TypeDef *USARTx,
uint32_t u32Func);
uint32_t USART_GetLinMeasureCnt(const M4_USART_TypeDef *USARTx);
uint32_t USART_GetLinMeasureBaudrate(const M4_USART_TypeDef *USARTx);
void USART_SetLinDetectBreakLen(M4_USART_TypeDef *USARTx,
uint32_t u32Len);
uint32_t USART_GetLinDetectBreakLen(const M4_USART_TypeDef *USARTx);
void USART_SetLinSendBreakLen(M4_USART_TypeDef *USARTx, uint32_t u32Len);
uint32_t USART_GetLinSendBreakLen(const M4_USART_TypeDef *USARTx);
en_result_t USART_SetBaudrate(M4_USART_TypeDef *USARTx,
uint32_t u32Baudrate,
float32_t *pf32Err);
/**
* @}
*/
#endif /* DDL_USART_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_USART_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

609
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32f4a0_utility.c Executable file
View File

@ -0,0 +1,609 @@
/**
*******************************************************************************
* @file hc32f4a0_utility.c
* @brief This file provides utility functions for DDL.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
2020-12-03 Yangjp Fixed SysTick_Delay function overflow handling
2021-04-15 Hongjh Re-implement print initialization API: UART_PrintfInit.
2021-05-24 Hongjh Delete code for writing LBMC register in UART_PrintfInit.
2021-08-19 Yangjp Delete error compensation in SysTick_Delay function.
2021-10-08 Hongjh 1. Rename function parameter for UART_PrintfInit.
2. Added AC6 supporting of printf retartget.
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32f4a0_utility.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @defgroup DDL_UTILITY UTILITY
* @brief DDL Utility Driver
* @{
*/
#if (DDL_UTILITY_ENABLE == DDL_ON)
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup UTILITY_Local_Macros UTILITY Local Macros
* @{
*/
#if (DDL_PRINT_ENABLE == DDL_ON)
/*!< Parameter valid check for USART Instances. */
#define IS_USART_UNIT(x) \
( ((x) == M4_USART1) || \
((x) == M4_USART2) || \
((x) == M4_USART3) || \
((x) == M4_USART4) || \
((x) == M4_USART5) || \
((x) == M4_USART6) || \
((x) == M4_USART7) || \
((x) == M4_USART8) || \
((x) == M4_USART9) || \
((x) == M4_USART10))
#define UART_EnableClk(x) \
do { \
if ((x) == M4_USART1) \
{ \
CLEAR_REG32_BIT(M4_PWC->FCG3, PWC_FCG3_USART1); \
} \
else if ((x) == M4_USART2) \
{ \
CLEAR_REG32_BIT(M4_PWC->FCG3, PWC_FCG3_USART2); \
} \
else if ((x) == M4_USART3) \
{ \
CLEAR_REG32_BIT(M4_PWC->FCG3, PWC_FCG3_USART3); \
} \
else if ((x) == M4_USART4) \
{ \
CLEAR_REG32_BIT(M4_PWC->FCG3, PWC_FCG3_USART4); \
} \
else if ((x) == M4_USART5) \
{ \
CLEAR_REG32_BIT(M4_PWC->FCG3, PWC_FCG3_USART5); \
} \
else if ((x) == M4_USART6) \
{ \
CLEAR_REG32_BIT(M4_PWC->FCG3, PWC_FCG3_USART2); \
} \
else if ((x) == M4_USART7) \
{ \
CLEAR_REG32_BIT(M4_PWC->FCG3, PWC_FCG3_USART3); \
} \
else if ((x) == M4_USART8) \
{ \
CLEAR_REG32_BIT(M4_PWC->FCG3, PWC_FCG3_USART4); \
} \
else if ((x) == M4_USART9) \
{ \
CLEAR_REG32_BIT(M4_PWC->FCG3, PWC_FCG3_USART5); \
} \
else \
{ \
CLEAR_REG32_BIT(M4_PWC->FCG3, PWC_FCG3_USART6); \
} \
} while (0)
#endif
/**
* @}
*/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/**
* @addtogroup UTILITY_Local_Functions UTILITY Local Functions
* @{
*/
#if (DDL_PRINT_ENABLE == DDL_ON)
static en_result_t UartPutChar(M4_USART_TypeDef *USARTx, char cData);
static en_result_t UartSetBaudrate(M4_USART_TypeDef *USARTx,
uint32_t u32Baudrate);
#endif
/**
* @}
*/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/**
* @defgroup UTILITY_Local_Variables UTILITY Local Variables
* @{
*/
static uint32_t m_u32TickStep = 0UL;
static __IO uint32_t m_u32TickCount = 0UL;
#if (DDL_PRINT_ENABLE == DDL_ON)
static M4_USART_TypeDef *m_PrintfDevice;
static uint32_t m_u32PrintfTimeout;
#endif
/**
* @}
*/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup UTILITY_Global_Functions UTILITY Global Functions
* @{
*/
/**
* @brief Delay function, delay ms approximately
* @param [in] u32Cnt ms
* @retval None
*/
void DDL_DelayMS(uint32_t u32Cnt)
{
__IO uint32_t i;
const uint32_t u32Cyc = HCLK_VALUE / 10000UL;
while (u32Cnt-- > 0UL)
{
i = u32Cyc;
while (i-- > 0UL)
{
;
}
}
}
/**
* @brief Delay function, delay us approximately
* @param [in] u32Cnt us
* @retval None
*/
void DDL_DelayUS(uint32_t u32Cnt)
{
__IO uint32_t i;
const uint32_t u32Cyc = HCLK_VALUE / 10000000UL;
while (u32Cnt-- > 0UL)
{
i = u32Cyc;
while (i-- > 0UL)
{
;
}
}
}
/**
* @brief This function Initializes the interrupt frequency of the SysTick.
* @param [in] u32Freq SysTick interrupt frequency (1 to 1000).
* @retval An en_result_t enumeration value:
* - Ok: SysTick Initializes succeed
* - Error: SysTick Initializes failed
*/
__WEAKDEF en_result_t SysTick_Init(uint32_t u32Freq)
{
en_result_t enRet = Error;
if ((0UL != u32Freq) && (u32Freq <= 1000UL))
{
m_u32TickStep = 1000UL / u32Freq;
/* Configure the SysTick interrupt */
if (0UL == SysTick_Config(HCLK_VALUE / u32Freq))
{
enRet = Ok;
}
}
return enRet;
}
/**
* @brief This function provides minimum delay (in milliseconds).
* @param [in] u32Delay Delay specifies the delay time.
* @retval None
*/
__WEAKDEF void SysTick_Delay(uint32_t u32Delay)
{
const uint32_t tickStart = SysTick_GetTick();
uint32_t tickEnd = u32Delay;
uint32_t tickMax;
if (m_u32TickStep != 0UL)
{
tickMax = 0xFFFFFFFFUL / m_u32TickStep * m_u32TickStep;
/* Add a freq to guarantee minimum wait */
if ((u32Delay >= tickMax) || ((tickMax - u32Delay) < m_u32TickStep))
{
tickEnd = tickMax;
}
while ((SysTick_GetTick() - tickStart) < tickEnd)
{
}
}
}
/**
* @brief This function is called to increment a global variable "u32TickCount".
* @note This variable is incremented in SysTick ISR.
* @param None
* @retval None
*/
__WEAKDEF void SysTick_IncTick(void)
{
m_u32TickCount += m_u32TickStep;
}
/**
* @brief Provides a tick value in millisecond.
* @param None
* @retval Tick value
*/
__WEAKDEF uint32_t SysTick_GetTick(void)
{
return m_u32TickCount;
}
/**
* @brief Suspend SysTick increment.
* @param None
* @retval None
*/
__WEAKDEF void SysTick_Suspend(void)
{
/* Disable SysTick Interrupt */
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
/**
* @brief Resume SysTick increment.
* @param None
* @retval None
*/
__WEAKDEF void SysTick_Resume(void)
{
/* Enable SysTick Interrupt */
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
}
#ifdef __DEBUG
/**
* @brief DDL assert error handle function
* @param [in] file Point to the current assert the wrong file.
* @param [in] line Point line assert the wrong file in the current.
* @retval None
*/
__WEAKDEF void DDL_AssertHandler(const char *file, int line)
{
/* Users can re-implement this function to print information */
DDL_Printf("Wrong parameters value: file %s on line %d\r\n", file, line);
for (;;)
{
;
}
}
#endif /* __DEBUG */
#if (DDL_PRINT_ENABLE == DDL_ON)
#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \
(defined (__ICCARM__)) || (defined (__CC_ARM))
/**
* @brief Re-target fputc function.
* @param [in] ch
* @param [in] f
* @retval int32_t
*/
int32_t fputc(int32_t ch, FILE *f)
{
(void)f; /* Prevent unused argument compilation warning */
return (Ok == UartPutChar(m_PrintfDevice, (char)ch)) ? ch : -1;
}
#elif defined ( __GNUC__ ) && !defined (__CC_ARM)
/**
* @brief Re-target _write function.
* @param [in] fd
* @param [in] data
* @param [in] size
* @retval int32_t
*/
int32_t _write(int fd, char data[], int32_t size)
{
int32_t i = -1;
if (NULL != data)
{
(void)fd; /* Prevent unused argument compilation warning */
for (i = 0; i < size; i++)
{
if (Ok != UartPutChar(m_PrintfDevice, data[i]))
{
break;
}
}
}
return i ? i : -1;
}
#endif
/**
* @brief Initialize UART for debug printf function
* @param [in] USARTx Pointer to USART instance register base
* This parameter can be one of the following values:
* @arg M4_USART1: USART unit 1 instance register base
* @arg M4_USART2: USART unit 2 instance register base
* @arg M4_USART3: USART unit 3 instance register base
* @arg M4_USART4: USART unit 4 instance register base
* @arg M4_USART5: USART unit 5 instance register base
* @arg M4_USART6: USART unit 6 instance register base
* @arg M4_USART7: USART unit 7 instance register base
* @arg M4_USART8: USART unit 8 instance register base
* @arg M4_USART9: USART unit 9 instance register base
* @arg M4_USART10: USART unit 10 instance register base
* @param [in] u32Baudrate UART baudrate
**@param [in] PortInit The pointer of printf port initialization function
* @retval An en_result_t enumeration value:
* - Ok: Initialize successfully
* - Error: Don't permit write the GPIO configuration register or set baudrate unsuccessfully
*/
en_result_t UART_PrintfInit(M4_USART_TypeDef *USARTx,
uint32_t u32Baudrate,
void (*PortInit)(void))
{
en_result_t enRet = Error;
if (IS_USART_UNIT(USARTx) && (0UL != u32Baudrate) && (NULL != PortInit))
{
/* Initialize port */
PortInit();
/* Enable clock */
UART_EnableClk(USARTx);
/***********************************************************************
* Configure UART
***********************************************************************
* Baud rate: u32Baudrate
* Bit direction: LSB
* Data bits: 8
* Stop bits: 1
* Parity: None
* Sampling bits: 8
**********************************************************************/
/* Disbale TX/RX && clear flag */
WRITE_REG32(USARTx->_CR1, (USART_CR1_CPE | USART_CR1_CORE | \
USART_CR1_CFE | USART_CR1_CRTOF | \
USART_CR1_CBE | USART_CR1_CWKUP | \
USART_CR1_CLBD));
/* Set CR1 */
WRITE_REG32(USARTx->_CR1, (USART_CR1_NFE | USART_CR1_SBS));
/* Set CR2: reset value */
WRITE_REG32(USARTx->_CR2, 0x00000600UL);
/* Set CR3: reset value */
WRITE_REG32(USARTx->_CR3, 0x00UL);
/* Set baudrate */
enRet = UartSetBaudrate(USARTx, u32Baudrate);
if (Ok == enRet)
{
/* Enable TX function */
SET_REG32_BIT(USARTx->_CR1, USART_CR1_TE);
m_PrintfDevice = USARTx;
m_u32PrintfTimeout = (HCLK_VALUE / u32Baudrate);
}
}
return enRet;
}
#endif /* DDL_PRINT_ENABLE */
/**
* @}
*/
/**
* @defgroup UTILITY_Local_Functions UTILITY Local Functions
* @{
*/
#if (DDL_PRINT_ENABLE == DDL_ON)
/**
* @brief UART transmit.
* @param [in] USARTx Pointer to USART instance register base
* This parameter can be one of the following values:
* @arg M4_USART1: USART unit 1 instance register base
* @arg M4_USART2: USART unit 2 instance register base
* @arg M4_USART3: USART unit 3 instance register base
* @arg M4_USART4: USART unit 4 instance register base
* @arg M4_USART5: USART unit 5 instance register base
* @arg M4_USART6: USART unit 6 instance register base
* @arg M4_USART7: USART unit 7 instance register base
* @arg M4_USART8: USART unit 8 instance register base
* @arg M4_USART9: USART unit 9 instance register base
* @arg M4_USART10: USART unit 10 instance register base
* @param [in] cData The data for transmitting
* @retval An en_result_t enumeration value:
* - Ok: Send successfully
* - ErrorTimeout: Send timeout
* - ErrorInvalidParameter: The parameter USARTx is invalid
*/
static en_result_t UartPutChar(M4_USART_TypeDef *USARTx, char cData)
{
uint32_t u32TxEmpty;
en_result_t enRet = ErrorInvalidParameter;
__IO uint32_t u32Timeout = m_u32PrintfTimeout;
if (NULL != USARTx)
{
/* Wait TX data register empty */
do
{
u32Timeout--;
u32TxEmpty = READ_REG32_BIT(USARTx->SR, USART_SR_TXE);
} while ((u32Timeout > 0UL) && (0UL == u32TxEmpty));
if (0UL != u32TxEmpty)
{
WRITE_REG32(USARTx->DR, (uint32_t)cData);
enRet = Ok;
}
else
{
enRet = ErrorTimeout;
}
}
return enRet;
}
/**
* @brief Set UART baudrate.
* @param [in] USARTx Pointer to USART instance register base
* This parameter can be one of the following values:
* @arg M4_USART1: USART unit 1 instance register base
* @arg M4_USART2: USART unit 2 instance register base
* @arg M4_USART3: USART unit 3 instance register base
* @arg M4_USART4: USART unit 4 instance register base
* @arg M4_USART5: USART unit 5 instance register base
* @arg M4_USART6: USART unit 6 instance register base
* @arg M4_USART7: USART unit 7 instance register base
* @arg M4_USART8: USART unit 8 instance register base
* @arg M4_USART9: USART unit 9 instance register base
* @arg M4_USART10: USART unit 10 instance register base
* @param [in] u32Baudrate UART baudrate
* @retval An en_result_t enumeration value:
* - Ok: Set successfully
* - Error: Baudrate set unsuccessfully
*/
static en_result_t UartSetBaudrate(M4_USART_TypeDef *USARTx,
uint32_t u32Baudrate)
{
uint32_t B;
uint32_t C;
uint32_t OVER8;
float32_t DIV;
uint32_t DIV_Integer;
uint32_t u32Prescaler;
uint32_t u32Pclk;
uint64_t u64Temp;
en_result_t enRet = Error;
uint32_t DIV_Fraction = 0UL;
if (u32Baudrate > 0UL)
{
B = u32Baudrate;
OVER8 = (0UL != (READ_REG32(USARTx->_CR1) & USART_CR1_OVER8)) ? 1UL : 0UL;
u32Pclk = (SystemCoreClock >> ((uint32_t)(READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS)));
for (u32Prescaler = 0UL; u32Prescaler <= USART_PR_PSC; u32Prescaler++)
{
C = (u32Pclk / (1UL << (u32Prescaler * 2UL)));
if (C > 0UL)
{
/* UART mode baudrate integer calculation formula: */
/* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */
/* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */
DIV = ((float)C / ((float)B * 8.0F * (2.0F - (float)OVER8))) - 1.0F;
DIV_Integer = (uint32_t)(DIV);
if ((DIV > 0.0F) && (DIV_Integer < 0xFFUL))
{
enRet = Ok;
if ((DIV - (float32_t)DIV_Integer) > 0.00001F)
{
/* UART mode baudrate fraction calculation formula: */
/* B = C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256) */
/* DIV_Fraction = (256 * (8 * (2 - OVER8) * (DIV_Integer + 1) * B) / C) - 128 */
u64Temp = (uint64_t)((uint64_t)8UL * ((uint64_t)2UL - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + 1UL) * (uint64_t)B);
DIV_Fraction = (uint32_t)(256UL * u64Temp / C - 128UL);
if (DIV_Fraction > 0x7FUL)
{
enRet = Error;
}
}
if (Ok == enRet)
{
/* Set clock prescaler */
WRITE_REG32(USARTx->PR, u32Prescaler);
/* Enable or disable baudrate fraction function */
MODIFY_REG32(USARTx->_CR1, USART_CR1_FBME, (0UL != DIV_Fraction) ? USART_CR1_FBME : 0UL);
/* Set USART_BRR register */
WRITE_REG32(USARTx->BRR, ((DIV_Integer << USART_BRR_DIV_INTEGER_POS) + DIV_Fraction));
break;
}
}
}
}
}
return enRet;
}
#endif /* DDL_PRINT_ENABLE */
/**
* @}
*/
#endif /* DDL_UTILITY_ENABLE */
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_utility.h
* @brief This file contains all the functions prototypes of the DDL utility.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
2021-04-15 Hongjh Add DDL printf macro-define.
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_UTILITY_H__
#define __HC32F4A0_UTILITY_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_UTILITY
* @{
*/
#if (DDL_UTILITY_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup UTILITY_Global_Functions
* @{
*/
/* Imprecise delay */
void DDL_DelayMS(uint32_t u32Cnt);
void DDL_DelayUS(uint32_t u32Cnt);
/* Systick functions */
en_result_t SysTick_Init(uint32_t u32Freq);
void SysTick_Delay(uint32_t u32Delay);
void SysTick_IncTick(void);
uint32_t SysTick_GetTick(void);
void SysTick_Suspend(void);
void SysTick_Resume(void);
/* You can add your own assert functions by implement the function DDL_AssertHandler
definition follow the function DDL_AssertHandler declaration */
#ifdef __DEBUG
#define DDL_ASSERT(x) \
do{ \
((x) ? (void)0 : DDL_AssertHandler(__FILE__, __LINE__)); \
}while(0)
/* Exported function */
void DDL_AssertHandler(const char *file, int line);
#else
#define DDL_ASSERT(x) ((void)0U)
#endif /* __DEBUG */
#if (DDL_PRINT_ENABLE == DDL_ON)
#include <stdio.h>
en_result_t UART_PrintfInit(M4_USART_TypeDef *USARTx,
uint32_t u32Baudrate,
void (*PortInit)(void));
#define DDL_PrintfInit (void)UART_PrintfInit
#define DDL_Printf (void)printf
#else
#define DDL_PrintfInit(x, y, z)
#define DDL_Printf(fmt, ...)
#endif
/**
* @}
*/
#endif /* DDL_UTILITY_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_UTILITY_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if non-shareable) or 010b (if shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/**
*******************************************************************************
* @file w25qxx.c
* @brief This midware file provides firmware functions to W25QXX group spi flash.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Wangmin First version
2020-08-31 Wangmin Modify for MISRAC2012
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "w25qxx.h"
#include "ev_hc32f4a0_lqfp176_w25qxx.h"
/**
* @addtogroup BSP
* @{
*/
/**
* @addtogroup Components
* @{
*/
/** @defgroup W25QXX Flash Driver for W25QXX
* @{
*/
#if (BSP_W25QXX_ENABLE == BSP_ON)
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup W25QXX_Local_Macros W25QXX Local Macros
* @{
*/
#define W25Q_BIT_0 (1UL << 0U)
#define W25Q_BIT_1 (1UL << 1U)
#define W25Q_BIT_2 (1UL << 2U)
#define W25Q_BIT_3 (1UL << 3U)
#define W25Q_BIT_4 (1UL << 4U)
#define W25Q_BIT_5 (1UL << 5U)
#define W25Q_BIT_6 (1UL << 6U)
#define W25Q_BIT_7 (1UL << 7U)
#define W25Q_BIT_8 (1UL << 8U)
#define W25Q_BIT_9 (1UL << 9U)
#define W25Q_BIT_10 (1UL << 10U)
#define W25Q_BIT_11 (1UL << 11U)
#define W25Q_BIT_12 (1UL << 12U)
#define W25Q_BIT_13 (1UL << 13U)
#define W25Q_BIT_14 (1UL << 14U)
#define W25Q_BIT_15 (1UL << 15U)
#define W25Q_ST_BUSY ((uint16_t)W25Q_BIT_0)
#define W25Q_ST_WEL ((uint16_t)W25Q_BIT_1) /*<! Write enable latch. */
#define LOAD_CMD(a, cmd, addr) do { \
(a)[0U] = (cmd); \
(a)[1U] = (uint8_t)((addr) >> 16U); \
(a)[2U] = (uint8_t)((addr) >> 8U); \
(a)[3U] = (uint8_t)(addr); \
} while (0U)
/**
* @}
*/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/**
* @defgroup W25QXX_Local_Functions W25QXX Local Functions
* @{
*/
static void W25QXX_WriteCmd(uint8_t u8Cmd, const uint8_t *pu8CmdData, uint32_t u32CmdDataLength);
static void W25QXX_ReadCmd(uint8_t u8Cmd, uint8_t *pu8CmdData, uint32_t u32CmdDataLength,
uint8_t *pu8Info, uint8_t u8InfoLength);
static void W25QXX_Wt(uint8_t u8Cmd, uint32_t u32Address, const uint8_t *pu8Data, uint32_t u32DataLength);
static void W25QXX_Rd(uint8_t u8Cmd, uint32_t u32Address, uint8_t *pu8Data, uint32_t u32DataLength);
static void W25QXX_WaitBusy(void);
static void W25QXX_WriteEnable(void);
static void W25QXX_WriteDisable(void);
static void W25QXX_WritePage(uint32_t u32Address, const uint8_t *pu8Data, uint32_t u32DataLength);
static void W25QXX_Write_NoCheck(const uint8_t *pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite);
static void W25QXX_WriteCmd(uint8_t u8Cmd, const uint8_t *pu8CmdData, uint32_t u32CmdDataLength);
static void W25QXX_ReadCmd(uint8_t u8Cmd, uint8_t *pu8CmdData, uint32_t u32CmdDataLength,
uint8_t *pu8Info, uint8_t u8InfoLength);
/**
* @}
*/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
static uint8_t W25QXX_BUFFER[4096U];
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup W25QXX_Global_Functions W25QXX Global Functions
* @{
*/
/**
* @brief Initializes W25QXX.
* @param [out] pstcW25qxx Pointer to a stc_w25qxx_t structure which contains the information of the SPI flash.
* @retval None
*/
void W25QXX_Init(stc_w25qxx_t *pstcW25qxx)
{
BSP_W25Q_SPI_Init();
if (pstcW25qxx != NULL)
{
/* Read Flash ID */
pstcW25qxx->u16ManId = W25QXX_ReadManDeviceId();
switch (pstcW25qxx->u16ManId)
{
case W25Q64:
pstcW25qxx->u32PageCount = 32768UL; /* W25Q64 contains 32768 pages. */
pstcW25qxx->u32SectorCount = 2048U; /* W25Q64 contains 2048 sectors. */
pstcW25qxx->u32BlockCount32k = 0U; /* DO NOT support 32K block. */
pstcW25qxx->u32BlockCount64k = 128U;
pstcW25qxx->u32CapacityInBytes = pstcW25qxx->u32PageCount * W25Q_SIZE_PAGE;
pstcW25qxx->u32CapacityInKB = pstcW25qxx->u32CapacityInBytes * W25Q_SIZE_1K;
break;
default:
break;
}
}
}
/**
* @brief Read manufacturer device ID.
* @param None
* @retval 16 bit manufacturer device ID.
*/
uint16_t W25QXX_ReadManDeviceId(void)
{
uint8_t au8TempId[2U];
uint8_t au8Dummy[3U] = {0U};
uint16_t u16ManID;
W25QXX_ReadCmd(W25Q_MANUFACTURER_DEVICE_ID, au8Dummy, 3U, au8TempId, 2U);
u16ManID = (uint16_t)au8TempId[0U] << 8U;
u16ManID |= au8TempId[1U];
return u16ManID;
}
/**
* @brief Read unique ID.
* @param [out] pu8UniqueId Pointer to a buffer the 64 bit unique ID to be stored.
* @retval None
*/
void W25QXX_ReadUniqueId(uint8_t *pu8UniqueId)
{
uint8_t au8Dummy[4U] = {0U};
W25QXX_ReadCmd(W25Q_READ_UNIQUE_ID, au8Dummy, 4U, pu8UniqueId, 8U);
}
/**
* @brief W25QXX read status register.
* @param None
* @retval 16 bit W25QXX status.
*/
uint16_t W25QXX_ReadStatus(void)
{
uint8_t u8TempStatus;
uint16_t u16RetStatus;
W25QXX_ReadCmd(W25Q_READ_STATUS_REG_2, NULL, 0U, &u8TempStatus, 1U);
u16RetStatus = u8TempStatus;
W25QXX_ReadCmd(W25Q_READ_STATUS_REG_1, NULL, 0U, &u8TempStatus, 1U);
u16RetStatus <<= 8U;
u16RetStatus |= u8TempStatus;
return u16RetStatus;
}
/**
* @brief W25QXX write status register
* @param [in] u16Status Specified status.
* @retval None
*/
void W25QXX_WriteStatus(uint16_t u16Status)
{
uint8_t au8Data[2U];
au8Data[0U] = (uint8_t)u16Status;
au8Data[1U] = (uint8_t)(u16Status >> 8U);
W25QXX_WriteCmd(W25Q_WRITE_STATUS_REG, au8Data, 2U);
}
/**
* @brief W25QXX power down.
* @param None
* @retval None
*/
void W25QXX_PowerDown(void)
{
W25QXX_WriteCmd(W25Q_POWER_DOWN, NULL, 0U);
W25QXX_DELAY_MS(1U);
}
/**
* @brief W25QXX release power down.
* @param None
* @retval None
*/
void W25QXX_ReleasePowerDown(void)
{
W25QXX_WriteCmd(W25Q_RELEASE_POWER_DOWN, NULL, 0U);
W25QXX_DELAY_MS(1U);
}
/**
* @brief W25QXX chip ease.
* @param None
* @retval None
*/
void W25QXX_EraseChip(void)
{
W25QXX_WriteEnable();
W25QXX_WaitBusy();
W25QXX_WriteCmd(W25Q_CHIP_ERASE, NULL, 0U);
W25QXX_WaitBusy();
}
/**
* @brief W25QXX sector ease.
* @param [in] u32SectorAddress The address of the specified sector.
* @retval None
*/
void W25QXX_EraseSector(uint32_t u32SectorAddress)
{
u32SectorAddress *= W25Q_SIZE_SECTOR;
W25QXX_WriteEnable();
W25QXX_WaitBusy();
W25QXX_Wt(W25Q_SECTOR_ERASE, u32SectorAddress, NULL, 0U);
W25QXX_WaitBusy();
W25QXX_WriteDisable();
}
/**
* @brief W25QXX block ease.
* @param [in] u32BlockAddress The address of the specified block.
* @retval None
*/
void W25QXX_EraseBlock(uint32_t u32BlockAddress)
{
W25QXX_Wt(W25Q_BLOCK_ERASE_64K, u32BlockAddress, NULL, 0U);
}
/**
* @brief W25QXX flash write
* @param [in] pBuffer Data buffer to be written
* @param [in] WriteAddr Address to be written
* @param [in] NumByteToWrite Number to be written, (MAX. 65535)
* @retval None
*/
static void W25QXX_Write_NoCheck(const uint8_t *pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite)
{
uint32_t pageremain;
uint32_t u32BufAdrTmp = (uint32_t)pBuffer;
pageremain = 256U - WriteAddr % 256U;
if (NumByteToWrite <= pageremain)
{
pageremain = NumByteToWrite;
}
for(;;)
{
W25QXX_WritePage(WriteAddr, (uint8_t *)u32BufAdrTmp, pageremain);
if (NumByteToWrite == (uint16_t)pageremain)
{
break;
}
else //NumByteToWrite>pageremain
{
u32BufAdrTmp += pageremain;
WriteAddr += pageremain;
NumByteToWrite -= (uint16_t)pageremain;
if (NumByteToWrite > 256U)
{
pageremain = 256U;
}
else
{
pageremain = (uint32_t)NumByteToWrite;
}
}
}
}
/**
* @brief W25QXX write data.
* @param [in] u32Address The start address of the data to be written.
* @param [in] pu8WriteBuf The pointer to the buffer contains the data to be written.
* @param [in] u32NumByteToWrite Buffer size in bytes.
* @retval None
*/
void W25QXX_WriteData(uint32_t u32Address, const uint8_t *pu8WriteBuf, uint32_t u32NumByteToWrite)
{
uint32_t secpos;
uint16_t secoff;
uint16_t secremain;
uint16_t i;
uint8_t *pW25QXX_BUF;
pW25QXX_BUF = W25QXX_BUFFER;
uint32_t u32WriteBufAddr = (uint32_t)&pu8WriteBuf;
secpos = u32Address / 4096U;
secoff = (uint16_t)(u32Address % 4096U);
secremain = 4096U - secoff;
if (u32NumByteToWrite <= secremain)
{
secremain = (uint16_t)u32NumByteToWrite;
}
for(;;)
{
W25QXX_ReadData(secpos * 4096U, pW25QXX_BUF, 4096U); // read one sector content
for (i = 0U; i < secremain; i++) // check if blank sector
{
if (pW25QXX_BUF[secoff + i] != (uint8_t)0xFFU)
{
break;
}
}
if (i < secremain)
{
W25QXX_EraseSector(secpos); // not blank, need erase
for (i = 0U; i < secremain; i++) // backup first
{
pW25QXX_BUF[i + secoff] = pu8WriteBuf[i];
}
W25QXX_Write_NoCheck(pW25QXX_BUF, secpos * 4096U, 4096U); // write back after erase
}
else
{
W25QXX_Write_NoCheck((const uint8_t *)u32WriteBufAddr, u32Address, secremain);
}
if (u32NumByteToWrite == secremain)
{
break;
}
else
{
secpos++; // next sector
secoff = 0U;
u32WriteBufAddr += secremain;
u32Address += secremain;
u32NumByteToWrite -= secremain;
if (u32NumByteToWrite > 4096U)
{
secremain = 4096U;
}
else
{
secremain = (uint16_t)u32NumByteToWrite;
}
}
}
}
/**
* @brief W25QXX read data.
* @param [in] u32Address The start address of the data to be read.
* @param [in] pu8ReadBuf The pointer to the buffer contains the data to be stored.
* @param [in] u32NumByteToRead Buffer size in bytes.
* @retval None
*/
void W25QXX_ReadData(uint32_t u32Address, uint8_t *pu8ReadBuf, uint32_t u32NumByteToRead)
{
W25QXX_Rd(W25Q_READ_DATA, u32Address, pu8ReadBuf, u32NumByteToRead);
}
/**
* @}
*/
/**
* @addtogroup W25QXX_Local_Functions W25QXX Local Functions
* @{
*/
/**
* @brief W25QXX write command.
* @param [in] u8Cmd Command of W25QXX.
* @param [in] pu8CmdData Pointer to a buffer that contains the data following the command.
* @param [in] u32CmdDataLength The length of the command data in bytes.
* @retval None
*/
static void W25QXX_WriteCmd(uint8_t u8Cmd, const uint8_t *pu8CmdData, uint32_t u32CmdDataLength)
{
W25Q_CS_ACTIVE();
(void)BSP_W25Q_SPI_Transmit(&u8Cmd, 1U);
(void)BSP_W25Q_SPI_Transmit(pu8CmdData, u32CmdDataLength);
W25Q_CS_INACTIVE();
}
/**
* @brief W25QXX read command.
* @param [in] u8Cmd Command of W25QXX.
* @param [in] pu8CmdData Pointer to a buffer that contains the data following the command.
* @param [in] u32CmdDataLength The length of the command data in bytes.
* @param [in] pu8Info The information of the command.
* @param [in] u8InfoLength The length of the information.
* @retval None
*/
static void W25QXX_ReadCmd(uint8_t u8Cmd, uint8_t *pu8CmdData, uint32_t u32CmdDataLength,
uint8_t *pu8Info, uint8_t u8InfoLength)
{
W25Q_CS_ACTIVE();
(void)BSP_W25Q_SPI_Transmit(&u8Cmd, 1U);
(void)BSP_W25Q_SPI_Transmit(pu8CmdData, u32CmdDataLength);
(void)BSP_W25Q_SPI_Receive(pu8Info, (uint32_t)u8InfoLength);
W25Q_CS_INACTIVE();
}
/**
* @brief W25QXX write data.
* @param [in] u8Cmd Command of W25QXX.
* @param [in] u32Address The start address of the data to be written.
* @param [in] pu8Data The data to be written.
* @param [in] u32DataLength The length of the data in bytes.
* @retval None
*/
static void W25QXX_Wt(uint8_t u8Cmd, uint32_t u32Address, const uint8_t *pu8Data, uint32_t u32DataLength)
{
uint8_t au8Cmd[4U];
LOAD_CMD(au8Cmd, u8Cmd, u32Address);
W25Q_CS_ACTIVE();
(void)BSP_W25Q_SPI_Transmit(au8Cmd, 4U);
(void)BSP_W25Q_SPI_Transmit(pu8Data, u32DataLength);
W25Q_CS_INACTIVE();
}
/**
* @brief W25QXX read data.
* @param [in] u8Cmd Command of W25QXX.
* @param [in] u32Address The start address of the data to be written.
* @param [in] pu8Data The data to be stored.
* @param [in] u32DataLength The length of the data in bytes.
* @retval None
*/
static void W25QXX_Rd(uint8_t u8Cmd, uint32_t u32Address, uint8_t *pu8Data, uint32_t u32DataLength)
{
uint8_t au8Cmd[4U];
LOAD_CMD(au8Cmd, u8Cmd, u32Address);
W25Q_CS_ACTIVE();
(void)BSP_W25Q_SPI_Transmit(au8Cmd, 4U);
(void)BSP_W25Q_SPI_Receive(pu8Data, u32DataLength);
W25Q_CS_INACTIVE();
}
/**
* @brief W25QXX Write enable.
* @param None
* @retval None
*/
static void W25QXX_WriteEnable(void)
{
W25QXX_WriteCmd(W25Q_WRITE_ENABLE, NULL, 0U);
}
/**
* @brief W25QXX Write disable.
* @param None
* @retval None
*/
static void W25QXX_WriteDisable(void)
{
W25QXX_WriteCmd(W25Q_WRITE_DISABLE, NULL, 0U);
}
/**
* @brief Wait while W25QXX is busy.
* @param None
* @retval None
*/
static void W25QXX_WaitBusy(void)
{
while ((W25QXX_ReadStatus() & W25Q_ST_BUSY) == W25Q_ST_BUSY)
{
;
}
}
/**
* @brief W25QXX page program.
* @param [in] u32Address Start address of the page.
* @param [in] pu8Data Pointer to a buffer that contains the data to be written.
* @param [in] u32DataLength Size of the buffer in bytes.
* @retval None
*/
static void W25QXX_WritePage(uint32_t u32Address, const uint8_t *pu8Data, uint32_t u32DataLength)
{
W25QXX_WriteEnable();
W25QXX_Wt(W25Q_PAGE_PROGRAM, u32Address, pu8Data, u32DataLength);
W25QXX_WaitBusy();
}
/**
* @}
*/
#endif /* BSP_W25QXX_ENABLE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

197
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/w25qxx.h Executable file
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@ -0,0 +1,197 @@
/**
*******************************************************************************
* @file w25qxx.h
* @brief This file provides firmware functions to W25QXX group spi flash.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Wangmin First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __W25QXX_H__
#define __W25QXX_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
/**
* @addtogroup BSP
* @{
*/
/**
* @addtogroup Components
* @{
*/
/** @addtogroup W25QXX
* @{
*/
#if (BSP_W25QXX_ENABLE == BSP_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup W25QXX_Global_Types W25QXX Global Types
* @{
*/
/**
* @brief Structure definition of W25QXX information.
*/
typedef struct
{
uint16_t u16ManId; /*!< Manufacturer device ID. */
uint8_t au8UniqueId[8U]; /*!< 64 bit unique ID number. */
uint32_t u32PageCount;
uint32_t u32SectorCount;
uint32_t u32BlockCount32k;
uint32_t u32BlockCount64k;
uint32_t u32CapacityInBytes;
uint32_t u32CapacityInKB;
} stc_w25qxx_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup W25QXX_Global_Macros W25QXX Global Macros
* @{
*/
/**
* @defgroup W25QXX_ID W25QXX ID
* @{
*/
#define W25Q80 (0xEF13U)
#define W25Q16 (0xEF14U)
#define W25Q32 (0xEF15U)
#define W25Q64 (0xEF16U)
#define W25Q128 (0xEF17U)
/**
* @}
*/
/**
* @defgroup W25QXX_Command W25QXX Command
* @{
*/
#define W25Q_WRITE_ENABLE ((uint8_t)0x06U)
#define W25Q_VOLATILE_SR_WRITE_ENABLE ((uint8_t)0x50U)
#define W25Q_WRITE_DISABLE ((uint8_t)0x04U)
#define W25Q_READ_STATUS_REG_1 ((uint8_t)0x05U)
#define W25Q_READ_STATUS_REG_2 ((uint8_t)0x35U)
#define W25Q_WRITE_STATUS_REG ((uint8_t)0x01U)
#define W25Q_PAGE_PROGRAM ((uint8_t)0x02U)
#define W25Q_SECTOR_ERASE ((uint8_t)0x20U)
#define W25Q_BLOCK_ERASE_32K ((uint8_t)0x52U)
#define W25Q_BLOCK_ERASE_64K ((uint8_t)0xD8U)
#define W25Q_CHIP_ERASE ((uint8_t)0xC7U)
#define W25Q_ERASE_PROGRAM_SUSPEND ((uint8_t)0x75U)
#define W25Q_ERASE_PROGRAM_RESUME ((uint8_t)0x7AU)
#define W25Q_POWER_DOWN ((uint8_t)0xB9U)
#define W25Q_READ_DATA ((uint8_t)0x03U)
#define W25Q_FAST_READ ((uint8_t)0x0BU)
#define W25Q_DEVICE_ID ((uint8_t)0xABU)
#define W25Q_RELEASE_POWER_DOWN (W25Q_DEVICE_ID)
#define W25Q_MANUFACTURER_DEVICE_ID ((uint8_t)0x90U)
#define W25Q_JEDEC_ID ((uint8_t)0x9FU)
#define W25Q_READ_UNIQUE_ID ((uint8_t)0x4BU)
#define W25Q_READ_SFDP_REG ((uint8_t)0x5AU)
#define W25Q_REASE_SECURITY_REG ((uint8_t)0x44U)
#define W25Q_PROGRAM_SECURITY_REG ((uint8_t)0x42U)
#define W25Q_READ_SECURITY_REG ((uint8_t)0x48U)
#define W25Q_ENABLE_QPI ((uint8_t)0x38U)
#define W25Q_ENABLE_RESET ((uint8_t)0x66U)
#define W25Q_RESET ((uint8_t)0x99U)
/**
* @}
*/
#define W25Q_SIZE_1K (1024U) /*!< 1KB */
#define W25Q_SIZE_PAGE (256U) /*!< 256B/page */
#define W25Q_SIZE_SECTOR (W25Q_SIZE_1K * 4U) /*!< 4KB/sector */
#define W25Q_SIZE_BLOCK (W25Q_SIZE_1K * 64U) /*!< 64KB/block */
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup W25QXX_Global_Functions W25QXX Global Functions
* @{
*/
void W25QXX_Init(stc_w25qxx_t *pstcW25qxx);
uint16_t W25QXX_ReadManDeviceId(void);
void W25QXX_ReadUniqueId(uint8_t *pu8UniqueId);
uint16_t W25QXX_ReadStatus(void);
void W25QXX_WriteStatus(uint16_t u16Status);
void W25QXX_PowerDown(void);
void W25QXX_ReleasePowerDown(void);
void W25QXX_EraseChip(void);
void W25QXX_EraseSector(uint32_t u32SectorAddress);
void W25QXX_EraseBlock(uint32_t u32BlockAddress);
void W25QXX_WriteData(uint32_t u32Address, const uint8_t *pu8WriteBuf, uint32_t u32NumByteToWrite);
void W25QXX_ReadData(uint32_t u32Address, uint8_t *pu8ReadBuf, uint32_t u32NumByteToRead);
/**
* @}
*/
#endif /* BSP_W25QXX_ENABLE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __W25QXX_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

9
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/boards/Kconfig
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@ -2367,6 +2367,11 @@ config ARCH_BOARD_CUSTOM
Don't see the board you want? You must first select the exact MCU part
number, then the boards supporting that part will be available for selection.
config ARCH_BOARD_HC32F4A0
bool "HDSC HC32F4A0 Board"
---help---
none
endchoice
if ARCH_BOARD_CUSTOM
@ -2667,6 +2672,7 @@ config ARCH_BOARD
default "spresense" if ARCH_BOARD_SPRESENSE
default "xx3803" if ARCH_BOARD_XX3803
default "xx3823" if ARCH_BOARD_XX3823
default "hc32f4a0" if ARCH_BOARD_HC32F4A0
comment "Common Board Options"
@ -3428,6 +3434,9 @@ endif
if ARCH_BOARD_XX3823
source "boards/sparc/bm3823/xx3823/Kconfig"
endif
if ARCH_BOARD_HC32F4A0
source "boards/arm/hc32/hc32f4a0/Kconfig"
endif
comment "Board-Common Options"

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# XIZI_AIOT

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