diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/Kconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/Kconfig index 2f9dcfc49..bf3959038 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/Kconfig +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/Kconfig @@ -11,4 +11,27 @@ config HC32F4A0_BOARD ---help--- Select if you are using the HC32F4A0 base board with the HC32F4A0. +config HC32_ROMFS + bool "Automount baked-in ROMFS image" + default n + depends on FS_ROMFS + ---help--- + Select HC32_ROMFS_IMAGEFILE, HC32_ROMFS_DEV_MINOR, HC32_ROMFS_MOUNTPOINT + +config HC32_ROMFS_DEV_MINOR + int "Minor for the block device backing the data" + depends on HC32_ROMFS + default 64 + +config HC32_ROMFS_MOUNTPOINT + string "Mountpoint of the custom romfs image" + depends on HC32_ROMFS + default "/rom" + +config HC32_ROMFS_IMAGEFILE + string "ROMFS image file to include into build" + depends on HC32_ROMFS + default "../../../../../rom.img" + + endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/include/board.h b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/include/board.h index 2d25e1e8d..343719cad 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/include/board.h +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/include/board.h @@ -57,38 +57,42 @@ /* for lowputc device output */ /* UART RX/TX Port/Pin definition */ -#define LP_RX_PORT (GPIO_PORT_H) /* PH6: USART6_RX */ -#define LP_RX_PIN (GPIO_PIN_06) -#define LP_RX_GPIO_FUNC (GPIO_FUNC_37_USART6_RX) +#define DBG_RX_PORT (GPIO_PORT_H) /* PH6: USART6_RX */ +#define DBG_RX_PIN (GPIO_PIN_06) +#define DBG_RX_GPIO_FUNC (GPIO_FUNC_37_USART6_RX) -#define LP_TX_PORT (GPIO_PORT_E) /* PE6: USART6_TX */ -#define LP_TX_PIN (GPIO_PIN_06) -#define LP_TX_GPIO_FUNC (GPIO_FUNC_36_USART6_TX) +#define DBG_TX_PORT (GPIO_PORT_E) /* PE6: USART6_TX */ +#define DBG_TX_PIN (GPIO_PIN_06) +#define DBG_TX_GPIO_FUNC (GPIO_FUNC_36_USART6_TX) /* UART unit definition */ -#define LP_UNIT (M4_USART6) -#define LP_FUNCTION_CLK_GATE (PWC_FCG3_USART6) +#define DBG_UNIT (M4_USART6) +#define DBG_BAUDRATE (115200UL) +#define DBG_FUNCTION_CLK_GATE (PWC_FCG3_USART6) /* UART unit interrupt definition */ -#define LP_UNIT_ERR_INT_SRC (INT_USART6_EI) -#define LP_UNIT_ERR_INT_IRQn (Int015_IRQn + HC32_IRQ_FIRST) +#define DBG_UNIT_ERR_INT_SRC (INT_USART6_EI) +#define DBG_UNIT_ERR_INT_IRQn (Int010_IRQn) -#define LP_UNIT_RX_INT_SRC (INT_USART6_RI) -#define LP_UNIT_RX_INT_IRQn (Int103_IRQn + HC32_IRQ_FIRST) +#define DBG_UNIT_RX_INT_SRC (INT_USART6_RI) +#define DBG_UNIT_RX_INT_IRQn (Int011_IRQn) -#define LP_UNIT_TX_INT_SRC (INT_USART6_TI) -#define LP_UNIT_TX_INT_IRQn (Int102_IRQn + HC32_IRQ_FIRST) +#define DBG_RXTO_INT_SRC (INT_USART6_RTO) +#define DBG_RXTO_INT_IRQn (Int012_IRQn) -#define LP_UNIT_TCI_INT_SRC (INT_USART6_TCI) -#define LP_UNIT_TCI_INT_IRQn (Int099_IRQn + HC32_IRQ_FIRST) +#define DBG_UNIT_TX_INT_SRC (INT_USART6_TI) +#define DBG_UNIT_TX_INT_IRQn (Int013_IRQn) + +#define DBG_UNIT_TCI_INT_SRC (INT_USART6_TCI) +#define DBG_UNIT_TCI_INT_IRQn (Int014_IRQn) /* printf device s*/ -#define BSP_PRINTF_DEVICE LP_UNIT -#define BSP_PRINTF_BAUDRATE (115200) +#define BSP_PRINTF_DEVICE DBG_UNIT +#define BSP_PRINTF_BAUDRATE DBG_BAUDRATE -#define BSP_PRINTF_PORT LP_TX_PORT +#define BSP_PRINTF_PORT DBG_TX_PORT -#define BSP_PRINTF_PIN LP_TX_PIN -#define BSP_PRINTF_PORT_FUNC LP_TX_GPIO_FUNC +#define BSP_PRINTF_PIN DBG_TX_PIN +#define BSP_PRINTF_PORT_FUNC DBG_TX_GPIO_FUNC #endif /* __BOARDS_ARM_HC32_HC32F4A0_INCLUDE_BOARD_H */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/kernel/Makefile b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/kernel/Makefile index 16096091d..42dd1dd06 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/kernel/Makefile +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/kernel/Makefile @@ -41,7 +41,7 @@ USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" # Source files -CSRCS = stm32_userspace.c +CSRCS = hc32_userspace.c COBJS = $(CSRCS:.c=$(OBJEXT)) OBJS = $(COBJS) diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/kernel/hc32_userspace.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/kernel/hc32_userspace.c index 966de7345..0fe0f7753 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/kernel/hc32_userspace.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/kernel/hc32_userspace.c @@ -52,7 +52,7 @@ # error "CONFIG_NUTTX_USERSPACE not defined" #endif -#if CONFIG_NUTTX_USERSPACE != 0x20060000 +#if CONFIG_NUTTX_USERSPACE != 0x20062000 # error "CONFIG_NUTTX_USERSPACE must be 0x20060000 to match memory.ld" #endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/gnu-elf.ld b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/gnu-elf.ld index 1b588c8c6..d951eff23 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/gnu-elf.ld +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/gnu-elf.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/aiit-arm32-board/scripts/gnu-elf.ld + * boards/arm/hc32/hc32f4a0/scripts/gnu-elf.ld * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/kernel-space.ld b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/kernel-space.ld index 82221aada..000ce6b07 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/kernel-space.ld +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/kernel-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/aiit-arm32-board/scripts/kernel-space.ld + * boards/arm/hc32/hc32f4a0/scripts/kernel-space.ld * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/memory.ld b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/memory.ld index 2afc1f9ef..c65f11e4b 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/memory.ld +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/memory.ld @@ -32,7 +32,7 @@ * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/aiit-arm32-board/scripts/kernel-space.ld). Allowing the + * also boards/arm/hc32/hc32f4a0/scripts/kernel-space.ld). Allowing the * additional does permit addition debug instrumentation to be added to the * kernel space without overflowing the partition. * @@ -73,13 +73,13 @@ MEMORY { /* 2Mb FLASH */ - kflash (rx) : ORIGIN = 0x00000000, LENGTH = 2M - uflash (rx) : ORIGIN = 0x00200000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x00220000, LENGTH = 768K + kflash (rx) : ORIGIN = 0x00000000, LENGTH = 64K + uflash (rx) : ORIGIN = 0x00010000, LENGTH = 1M + xflash (rx) : ORIGIN = 0x00110000, LENGTH = 128K /* 512Kb of contiguous SRAM */ - ksram (rwx) : ORIGIN = 0x1FFE0000, LENGTH = 512K - usram (rwx) : ORIGIN = 0x20060000, LENGTH = 4K - xsram (rwx) : ORIGIN = 0x20062000, LENGTH = 4K + ksram (rwx) : ORIGIN = 0x1FFE0000, LENGTH = 64K + usram (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 448K + xsram (rwx) : ORIGIN = 0x20070000, LENGTH = 4K } diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/user-space.ld b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/user-space.ld index ee800d72d..c71b0297c 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/user-space.ld +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/user-space.ld @@ -48,16 +48,16 @@ SECTIONS _sinit = ABSOLUTE(.); *(.init_array .init_array.*) _einit = ABSOLUTE(.); - } > kflash + } > uflash .ARM.extab : { *(.ARM.extab*) - } > kflash + } > uflash __exidx_start = ABSOLUTE(.); .ARM.exidx : { *(.ARM.exidx*) - } > kflash + } > uflash __exidx_end = ABSOLUTE(.); @@ -70,7 +70,7 @@ SECTIONS CONSTRUCTORS . = ALIGN(4); _edata = ABSOLUTE(.); - } > ksram AT > kflash + } > usram AT > uflash .bss : { _sbss = ABSOLUTE(.); @@ -79,7 +79,7 @@ SECTIONS *(COMMON) . = ALIGN(4); _ebss = ABSOLUTE(.); - } > ksram + } > usram /* Stabs debugging sections */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/Make.defs b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/Make.defs index aaf7da6ee..37a78f333 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/Make.defs +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/Make.defs @@ -26,6 +26,10 @@ ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += endif +ifeq ($(CONFIG_STM32_ROMFS),y) +CSRCS += hc32_romfs_initialize.c +endif + DEPPATH += --dep-path board VPATH += :board CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board) diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_boot.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_boot.c index 274d03360..e75aed9f1 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_boot.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_boot.c @@ -38,6 +38,7 @@ ****************************************************************************/ extern int hc32_bringup(void); +extern int hc32_spidev_initialized; /**************************************************************************** * Name: hc32_boardinitialize @@ -52,57 +53,57 @@ extern int hc32_bringup(void); void hc32_boardinitialize(void) { -//#ifdef CONFIG_SCHED_CRITMONITOR -// /* Enable ITM and DWT resources, if not left enabled by debugger. */ -// -// modifyreg32(NVIC_DEMCR, 0, NVIC_DEMCR_TRCENA); -// -// /* Make sure the high speed cycle counter is running. It will be started -// * automatically only if a debugger is connected. -// */ -// -// putreg32(0xc5acce55, ITM_LAR); -// modifyreg32(DWT_CTRL, 0, DWT_CTRL_CYCCNTENA_MASK); -//#endif -// -//#if defined(CONFIG_HC32_SPI1) || defined(CONFIG_HC32_SPI2) || defined(CONFIG_HC32_SPI3) -// /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak -// * function hc32_spidev_initialize() has been brought into the link. -// */ -// -// if (hc32_spidev_initialize) -// { -// hc32_spidev_initialize(); -// } -//#endif -// -//#ifdef CONFIG_HC32_OTGFS -// /* Initialize USB if the 1) OTG FS controller is in the configuration and -// * 2) disabled, and 3) the weak function hc32_usbinitialize() has been -// * brought into the build. Presumably either CONFIG_USBDEV or -// * CONFIG_USBHOST is also selected. -// */ -// -// if (hc32_usbinitialize) -// { -// hc32_usbinitialize(); -// } -//#endif -// -//#ifdef HAVE_NETMONITOR -// /* Configure board resources to support networking. */ -// -// if (hc32_netinitialize) -// { -// hc32_netinitialize(); -// } -//#endif -// -//#ifdef CONFIG_ARCH_LEDS -// /* Configure on-board LEDs if LED support has been selected. */ -// -// board_autoled_initialize(); -//#endif +#ifdef CONFIG_SCHED_CRITMONITOR + /* Enable ITM and DWT resources, if not left enabled by debugger. */ + + modifyreg32(NVIC_DEMCR, 0, NVIC_DEMCR_TRCENA); + + /* Make sure the high speed cycle counter is running. It will be started + * automatically only if a debugger is connected. + */ + + putreg32(0xc5acce55, ITM_LAR); + modifyreg32(DWT_CTRL, 0, DWT_CTRL_CYCCNTENA_MASK); +#endif + +#if defined(CONFIG_HC32_SPI1) || defined(CONFIG_HC32_SPI2) || defined(CONFIG_HC32_SPI3) + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function hc32_spidev_initialize() has been brought into the link. + */ + + if (hc32_spidev_initialized) + { + hc32_spidev_initialize(); + } +#endif + +#ifdef CONFIG_HC32_OTGFS + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function hc32_usbinitialize() has been + * brought into the build. Presumably either CONFIG_USBDEV or + * CONFIG_USBHOST is also selected. + */ + + if (hc32_usbinitialize) + { + hc32_usbinitialize(); + } +#endif + +#ifdef HAVE_NETMONITOR + /* Configure board resources to support networking. */ + + if (hc32_netinitialize) + { + hc32_netinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif } /**************************************************************************** diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_bringup.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_bringup.c index dd768fd85..9ea9d7fde 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_bringup.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_bringup.c @@ -31,6 +31,8 @@ #include +#include + /**************************************************************************** * Name: hc32_bringup * @@ -48,6 +50,27 @@ int hc32_bringup(void) { int ret = 0; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, HC32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + serr("ERROR: Failed to mount procfs at %s: %d\n", + HC32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_HC32_ROMFS + ret = hc32_romfs_initialize(); + if (ret < 0) + { + serr("ERROR: Failed to mount romfs at %s: %d\n", + CONFIG_HC32_ROMFS_MOUNTPOINT, ret); + } +#endif + printf("start %s\n", __func__); return ret; } diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_romfs.h b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_romfs.h new file mode 100755 index 000000000..b8297d570 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_romfs.h @@ -0,0 +1,76 @@ +/**************************************************************************** + * boards/arm/hc32/hc32f4a0/src/hc32_romfs.h + * + * Copyright (C) 2017 Tomasz Wozniak. All rights reserved. + * Author: Tomasz Wozniak + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_HC32_HC32F4A0_SRC_HC32_ROMFS_H +#define __BOARDS_ARM_HC32_HC32F4A0_SRC_HC32_ROMFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_HC32_ROMFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ROMFS_SECTOR_SIZE 64 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_romfs_initialize + * + * Description: + * Registers built-in ROMFS image as block device and mounts it. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [&romfs_data_begin .. &romfs_data_begin) should contain + * ROMFS volume data, as included in the assembly snippet above (l. 84). + * + ****************************************************************************/ + +int hc32_romfs_initialize(void); + +#endif /* CONFIG_STM32_ROMFS */ + +#endif /* __BOARDS_ARM_HC32_HC32F4A0_SRC_HC32_ROMFS_H */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_romfs_initialize.c b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_romfs_initialize.c new file mode 100755 index 000000000..4723ce40b --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_romfs_initialize.c @@ -0,0 +1,158 @@ +/**************************************************************************** + * boards/arm/hc32/hc32f4a0/src/hc32_romfs_initialize.c + * This file provides contents of an optional ROMFS volume, mounted at boot. + * + * Copyright (C) 2017 Tomasz Wozniak. All rights reserved. + * Author: Tomasz Wozniak + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include "hc32_romfs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_HC32_ROMFS +# error "CONFIG_HC32_ROMFS must be defined" +#else + +#ifndef CONFIG_HC32_ROMFS_IMAGEFILE +# error "CONFIG_HC32_ROMFS_IMAGEFILE must be defined" +#endif + +#ifndef CONFIG_HC32_ROMFS_DEV_MINOR +# error "CONFIG_HC32_ROMFS_DEV_MINOR must be defined" +#endif + +#ifndef CONFIG_HC32_ROMFS_MOUNTPOINT +# error "CONFIG_HC32_ROMFS_MOUNTPOINT must be defined" +#endif + +#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) + +#define STR2(m) #m +#define STR(m) STR2(m) + +#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) +#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_HC32_ROMFS_DEV_MINOR) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +__asm__ ( + ".section .rodata\n" + ".balign 16\n" + ".globl romfs_data_begin\n" +"romfs_data_begin:\n" + ".incbin " STR(CONFIG_HC32_ROMFS_IMAGEFILE) "\n"\ + \ + ".balign " STR(ROMFS_SECTOR_SIZE) "\n" + ".globl romfs_data_end\n" +"romfs_data_end:\n" + ".globl romfs_data_size\n" +"romfs_data_size:\n" + ".word romfs_data_end - romfs_data_begin\n" + ".previous\n"); + +extern const char romfs_data_begin; +extern const char romfs_data_end; +extern const int romfs_data_size; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hc32_romfs_initialize + * + * Description: + * Registers the aboveincluded binary file as block device. + * Then mounts the block device as ROMFS filesystems. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [&romfs_data_begin .. &romfs_data_begin) should contain + * ROMFS volume data, as included in the assembly snippet above (l. 84). + * + ****************************************************************************/ + +int hc32_romfs_initialize(void) +{ + uintptr_t romfs_data_len; + int ret; + + /* Create a ROM disk for the /etc filesystem */ + + romfs_data_len = (uintptr_t)&romfs_data_end - (uintptr_t)&romfs_data_begin; + + ret = romdisk_register(CONFIG_HC32_ROMFS_DEV_MINOR, &romfs_data_begin, + NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); + if (ret < 0) + { + ferr("ERROR: romdisk_register failed: %d\n", -ret); + return ret; + } + + /* Mount the file system */ + + finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", + CONFIG_HC32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); + + ret = nx_mount(MOUNT_DEVNAME, CONFIG_HC32_ROMFS_MOUNTPOINT, + "romfs", MS_RDONLY, NULL); + if (ret < 0) + { + ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", + MOUNT_DEVNAME, CONFIG_HC32_ROMFS_MOUNTPOINT, ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_HC32_ROMFS */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/Kconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/Kconfig index d70f8ea1c..c1c3ebc02 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/Kconfig +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/Kconfig @@ -172,3 +172,26 @@ config HC32_UART8 endmenu # HC32 U[S]ART Selection +config HC32_SPI1 + bool "SPI1" + default n + select SPI + select HC32_SPI + +config HC32_SPI2 + bool "SPI2" + default n + depends on HC32_HAVE_SPI2 + select SPI + select HC32_SPI + + +config HC32_SPI + bool + +config HC32_I2C + bool + +config HC32_CAN + bool + diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/Make.defs b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/Make.defs index 9c2eba33a..b85737cb1 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/Make.defs +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/Make.defs @@ -44,7 +44,6 @@ CMN_ASRCS += arm_lazyexception.S else CMN_ASRCS += arm_exception.S endif -CMN_CSRCS += arm_vectors.c ifeq ($(CONFIG_ARCH_RAMVECTORS),y) CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c @@ -77,12 +76,19 @@ ifeq ($(CONFIG_SCHED_THREAD_LOCAL),y) CMN_CSRCS += arm_tls.c endif +CMN_CSRCS += hc32_vectors.c + CHIP_CSRCS = hc32_allocateheap.c hc32_gpio.c CHIP_CSRCS += hc32_irq.c hc32_idle.c hc32_mpuinit.c CHIP_CSRCS += hc32_rcc.c hc32_start.c hc32_serial.c CHIP_CSRCS += hc32_pm.c hc32_timerisr.c hc32_lowputc.c +CHIP_CSRCS += hc32_console.c CHIP_CSRCS += hc32f4a0_clk.c hc32f4a0_efm.c hc32f4a0_gpio.c CHIP_CSRCS += hc32f4a0_interrupts.c hc32f4a0_usart.c hc32f4a0_utility.c CHIP_CSRCS += hc32f4a0_sram.c hc32f4a0_pwc.c +CHIP_CSRCS += hc32f4a0_spi.c + +CHIP_CSRCS += hc32_spiflash.c hc32_spi.c + diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/ddl_config.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/ddl_config.h index 6706dd9af..692f850d7 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/ddl_config.h +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/ddl_config.h @@ -89,7 +89,7 @@ extern "C" #define DDL_RTC_ENABLE (DDL_OFF) #define DDL_SDIOC_ENABLE (DDL_OFF) #define DDL_SMC_ENABLE (DDL_OFF) -#define DDL_SPI_ENABLE (DDL_OFF) +#define DDL_SPI_ENABLE (DDL_ON) #define DDL_SRAM_ENABLE (DDL_ON) #define DDL_SWDT_ENABLE (DDL_OFF) #define DDL_TMR0_ENABLE (DDL_OFF) @@ -134,7 +134,7 @@ extern "C" #define BSP_OV5640_ENABLE (BSP_OFF) #define BSP_S29GL064N90TFI03_ENABLE (BSP_OFF) #define BSP_TCA9539_ENABLE (BSP_OFF) -#define BSP_W25QXX_ENABLE (BSP_ON) +#define BSP_W25QXX_ENABLE (BSP_OFF) #define BSP_WM8731_ENABLE (BSP_OFF) /** diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_allocateheap.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_allocateheap.c index e3036f8cb..140ac310c 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_allocateheap.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_allocateheap.c @@ -83,20 +83,20 @@ /* The HC32 F4A0 have no CCM SRAM */ -# if defined(CONFIG_HC32_HC32F4A0) +# if defined(CONFIG_HC32_HC32F4A0) # undef CONFIG_HC32_CCMEXCLUDE # define CONFIG_HC32_CCMEXCLUDE 1 # endif /* Set the end of system SRAM */ -#define SRAM1_END 0x20073880 +#define SRAM1_END 0x1FFF0000 /* Set the range of CCM SRAM as well (although we may not use it) */ -#define SRAM2_START 0x1FE00000 -#define SRAM2_END 0x20073880 +#define SRAM2_START 0x1FFF0000 +#define SRAM2_END 0x20070000 /* There are 4 possible SRAM configurations: diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_common.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_common.h index e9539542a..ac617b632 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_common.h +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_common.h @@ -37,6 +37,15 @@ extern "C" #define HC32F4A0 1 #define USE_DDL_DRIVER 1 +#ifdef CONFIG_FS_PROCFS +# ifdef CONFIG_NSH_PROC_MOUNTPOINT +# define HC32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT +# else +# define HC32_PROCFS_MOUNTPOINT "/proc" +# endif +#endif + + #define getreg32(a) (*(volatile uint32_t *)(a)) #define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) #define getreg16(a) (*(volatile uint16_t *)(a)) diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_console.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_console.c new file mode 100755 index 000000000..e6fd16e9a --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_console.c @@ -0,0 +1,46 @@ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "chip.h" +#include "hc32_uart.h" +#include "hc32_spi.h" + +void hc32_test_console(void) +{ + char *dev_str = "/dev/console"; + char *test_chr = "test"; + int fd = 0, ret; + + fd = open(dev_str, 0x6); + hc32_print("%s: open <%s> ret = %d\n", __func__, dev_str, fd); + ret = write(fd, test_chr, strlen(test_chr)); + hc32_print("%s: open %d ret %d\n", __func__, fd, ret); + close(fd); +} + +void hc32_console_handle(char *buf) +{ + if(strncmp(buf, "console", 7) == 0) + { + hc32_test_console(); + } + else if(strncmp(buf, "spi", 7) == 0) + { + hc32_print("start flash test ...\n"); + hc32_spiflash_test(); + } +} + diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_console.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_console.h new file mode 100755 index 000000000..e908105a4 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_console.h @@ -0,0 +1,43 @@ +#ifndef __HC32_CONSOLE_H_ +#define __HC32_CONSOLE_H_ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include +#include "chip.h" +#include "hc32_uart.h" +#include "hc32_rcc.h" +#include "hc32_gpio.h" +#include "arm_internal.h" +#include "hc32f4a0.h" +#include "hc32f4a0_usart.h" +#include "hc32f4a0_gpio.h" +#include "hc32f4a0_interrupts.h" +#include "hc32f4a0_sram.h" +#include "hc32f4a0_pwc.h" +#include "hc32f4a0_efm.h" + +void hc32_console_handle(char *buf); + +#endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_gpio.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_gpio.c index 42f6f2d12..3835a2b14 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_gpio.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_gpio.c @@ -119,7 +119,7 @@ void hc32_gpioinit(void) ****************************************************************************/ /**************************************************************************** - * Name: hc32_configgpio (for the HC32F10xxx family) + * Name: hc32_configgpio (for the HC32F4A0) ****************************************************************************/ int hc32_configgpio(uint32_t cfgset) diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_idle.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_idle.c index d112c65c9..fb8deaacd 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_idle.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_idle.c @@ -152,6 +152,12 @@ static void up_idlepm(void) void up_idle(void) { + +#if defined (CONFIG_HC32F4A0_BOARD) + extern void hc32_uart_handle(void); + hc32_uart_handle(); +#endif + #if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) /* If the system is idle and there are no timer interrupts, then process * "fake" timer interrupts. Hopefully, something will wake up. diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_irq.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_irq.c index 8f471147f..91d6a86c7 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_irq.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_irq.c @@ -40,6 +40,7 @@ #endif #include "arm_internal.h" #include "hc32f4a0.h" +#include "hc32f4a0_interrupts.h" /**************************************************************************** * Pre-processor Definitions @@ -162,57 +163,1119 @@ static void hc32_dumpnvic(const char *msg, int irq) * ****************************************************************************/ + +static int hc32_svc(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); +#ifdef CONFIG_DEBUG_FEATURES + _err("PANIC!!! SVC received\n"); + PANIC(); +#endif + SVC_Handler(); + return 0; +} + +static int hc32_hardfault(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); +#ifdef CONFIG_DEBUG_FEATURES + _err("PANIC!!! HardFault received\n"); + PANIC(); +#endif + HardFault_Handler(); + return 0; +} + #ifdef CONFIG_DEBUG_FEATURES static int hc32_nmi(int irq, FAR void *context, FAR void *arg) { up_irq_save(); +#ifdef CONFIG_DEBUG_FEATURES _err("PANIC!!! NMI received\n"); PANIC(); +#endif + NMI_Handler(); + return 0; +} + +#ifdef CONFIG_ARM_MPU + +static int hc32_memfault(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); +#ifdef CONFIG_DEBUG_FEATURES + _err("PANIC!!! MemFault received\n"); + PANIC(); +#endif + MemManage_Handler(); return 0; } static int hc32_busfault(int irq, FAR void *context, FAR void *arg) { up_irq_save(); +#ifdef CONFIG_DEBUG_FEATURES _err("PANIC!!! Bus fault received: %08" PRIx32 "\n", getreg32(NVIC_CFAULTS)); PANIC(); +#endif + BusFault_Handler(); return 0; } static int hc32_usagefault(int irq, FAR void *context, FAR void *arg) { up_irq_save(); +#ifdef CONFIG_DEBUG_FEATURES _err("PANIC!!! Usage fault received: %08" PRIx32 "\n", getreg32(NVIC_CFAULTS)); PANIC(); +#endif + UsageFault_Handler(); return 0; } static int hc32_pendsv(int irq, FAR void *context, FAR void *arg) { up_irq_save(); +#ifdef CONFIG_DEBUG_FEATURES _err("PANIC!!! PendSV received\n"); PANIC(); +#endif + PendSV_Handler(); return 0; } static int hc32_dbgmonitor(int irq, FAR void *context, FAR void *arg) { up_irq_save(); +#ifdef CONFIG_DEBUG_FEATURES _err("PANIC!!! Debug Monitor received\n"); PANIC(); +#endif + DebugMon_Handler(); return 0; } static int hc32_reserved(int irq, FAR void *context, FAR void *arg) { up_irq_save(); +#ifdef CONFIG_DEBUG_FEATURES _err("PANIC!!! Reserved interrupt\n"); PANIC(); +#endif return 0; } #endif +#endif +static int hc32_irq000(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ000_Handler(); + return 0; +} + +static int hc32_irq001(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ001_Handler(); + return 0; +} + +static int hc32_irq002(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ002_Handler(); + return 0; +} + +static int hc32_irq003(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ003_Handler(); + return 0; +} + +static int hc32_irq004(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ004_Handler(); + return 0; +} + +static int hc32_irq005(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ005_Handler(); + return 0; +} + +static int hc32_irq006(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ006_Handler(); + return 0; +} + +static int hc32_irq007(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ007_Handler(); + return 0; +} + +static int hc32_irq008(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ008_Handler(); + return 0; +} + +static int hc32_irq009(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ009_Handler(); + return 0; +} + +static int hc32_irq010(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ010_Handler(); + return 0; +} + +static int hc32_irq011(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ011_Handler(); + return 0; +} + +static int hc32_irq012(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ012_Handler(); + return 0; +} + +static int hc32_irq013(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ013_Handler(); + return 0; +} + +static int hc32_irq014(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ014_Handler(); + return 0; +} + +static int hc32_irq015(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ015_Handler(); + return 0; +} + +static int hc32_irq016(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ016_Handler(); + return 0; +} + +static int hc32_irq017(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ017_Handler(); + return 0; +} + +static int hc32_irq018(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ018_Handler(); + return 0; +} + +static int hc32_irq019(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ019_Handler(); + return 0; +} + +static int hc32_irq020(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ020_Handler(); + return 0; +} + +static int hc32_irq021(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ021_Handler(); + return 0; +} + +static int hc32_irq022(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ022_Handler(); + return 0; +} + +static int hc32_irq023(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ023_Handler(); + return 0; +} + +static int hc32_irq024(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ024_Handler(); + return 0; +} + +static int hc32_irq025(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ025_Handler(); + return 0; +} + +static int hc32_irq026(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ026_Handler(); + return 0; +} + +static int hc32_irq027(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ027_Handler(); + return 0; +} + +static int hc32_irq028(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ028_Handler(); + return 0; +} + +static int hc32_irq029(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ029_Handler(); + return 0; +} + +static int hc32_irq030(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ030_Handler(); + return 0; +} + +static int hc32_irq031(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ031_Handler(); + return 0; +} + +static int hc32_irq032(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ032_Handler(); + return 0; +} + +static int hc32_irq033(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ033_Handler(); + return 0; +} + +static int hc32_irq034(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ034_Handler(); + return 0; +} + +static int hc32_irq035(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ035_Handler(); + return 0; +} + +static int hc32_irq036(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ036_Handler(); + return 0; +} + +static int hc32_irq037(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ037_Handler(); + return 0; +} + +static int hc32_irq038(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ038_Handler(); + return 0; +} + +static int hc32_irq039(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ039_Handler(); + return 0; +} + +static int hc32_irq040(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ040_Handler(); + return 0; +} + +static int hc32_irq041(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ041_Handler(); + return 0; +} + +static int hc32_irq042(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ042_Handler(); + return 0; +} + +static int hc32_irq043(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ043_Handler(); + return 0; +} + +static int hc32_irq044(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ044_Handler(); + return 0; +} + +static int hc32_irq045(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ045_Handler(); + return 0; +} + +static int hc32_irq046(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ046_Handler(); + return 0; +} + +static int hc32_irq047(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ047_Handler(); + return 0; +} + +static int hc32_irq048(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ048_Handler(); + return 0; +} + +static int hc32_irq049(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ049_Handler(); + return 0; +} + +static int hc32_irq050(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ050_Handler(); + return 0; +} + +static int hc32_irq051(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ051_Handler(); + return 0; +} + +static int hc32_irq052(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ052_Handler(); + return 0; +} + +static int hc32_irq053(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ053_Handler(); + return 0; +} + +static int hc32_irq054(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ054_Handler(); + return 0; +} + +static int hc32_irq055(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ055_Handler(); + return 0; +} + +static int hc32_irq056(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ056_Handler(); + return 0; +} + +static int hc32_irq057(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ057_Handler(); + return 0; +} + +static int hc32_irq058(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ058_Handler(); + return 0; +} + +static int hc32_irq059(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ059_Handler(); + return 0; +} + +static int hc32_irq060(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ060_Handler(); + return 0; +} + +static int hc32_irq061(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ061_Handler(); + return 0; +} + +static int hc32_irq062(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ062_Handler(); + return 0; +} + +static int hc32_irq063(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ063_Handler(); + return 0; +} + +static int hc32_irq064(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ064_Handler(); + return 0; +} + +static int hc32_irq065(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ065_Handler(); + return 0; +} + +static int hc32_irq066(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ066_Handler(); + return 0; +} + +static int hc32_irq067(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ067_Handler(); + return 0; +} + +static int hc32_irq068(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ068_Handler(); + return 0; +} + +static int hc32_irq069(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ069_Handler(); + return 0; +} + +static int hc32_irq070(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ070_Handler(); + return 0; +} + +static int hc32_irq071(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ071_Handler(); + return 0; +} + +static int hc32_irq072(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ072_Handler(); + return 0; +} + +static int hc32_irq073(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ073_Handler(); + return 0; +} + +static int hc32_irq074(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ074_Handler(); + return 0; +} + +static int hc32_irq075(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ075_Handler(); + return 0; +} + +static int hc32_irq076(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ076_Handler(); + return 0; +} + +static int hc32_irq077(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ077_Handler(); + return 0; +} + +static int hc32_irq078(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ078_Handler(); + return 0; +} + +static int hc32_irq079(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ079_Handler(); + return 0; +} + +static int hc32_irq080(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ080_Handler(); + return 0; +} + +static int hc32_irq081(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ081_Handler(); + return 0; +} + +static int hc32_irq082(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ082_Handler(); + return 0; +} + +static int hc32_irq083(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ083_Handler(); + return 0; +} + +static int hc32_irq084(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ084_Handler(); + return 0; +} + +static int hc32_irq085(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ085_Handler(); + return 0; +} + +static int hc32_irq086(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ086_Handler(); + return 0; +} + +static int hc32_irq087(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ087_Handler(); + return 0; +} + +static int hc32_irq088(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ088_Handler(); + return 0; +} + +static int hc32_irq089(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ089_Handler(); + return 0; +} + +static int hc32_irq090(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ090_Handler(); + return 0; +} + +static int hc32_irq091(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ091_Handler(); + return 0; +} + +static int hc32_irq092(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ092_Handler(); + return 0; +} + +static int hc32_irq093(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ093_Handler(); + return 0; +} + +static int hc32_irq094(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ094_Handler(); + return 0; +} + +static int hc32_irq095(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ095_Handler(); + return 0; +} + +static int hc32_irq096(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ096_Handler(); + return 0; +} + +static int hc32_irq097(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ097_Handler(); + return 0; +} + +static int hc32_irq098(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ098_Handler(); + return 0; +} + +static int hc32_irq099(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ099_Handler(); + return 0; +} + +static int hc32_irq100(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ100_Handler(); + return 0; +} + +static int hc32_irq101(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ101_Handler(); + return 0; +} + +static int hc32_irq102(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ102_Handler(); + return 0; +} + +static int hc32_irq103(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ103_Handler(); + return 0; +} + +static int hc32_irq104(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ104_Handler(); + return 0; +} + +static int hc32_irq105(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ105_Handler(); + return 0; +} + +static int hc32_irq106(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ106_Handler(); + return 0; +} + +static int hc32_irq107(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ107_Handler(); + return 0; +} + +static int hc32_irq108(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ108_Handler(); + return 0; +} + +static int hc32_irq109(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ109_Handler(); + return 0; +} + +static int hc32_irq110(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ110_Handler(); + return 0; +} + +static int hc32_irq111(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ111_Handler(); + return 0; +} + +static int hc32_irq112(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ112_Handler(); + return 0; +} + +static int hc32_irq113(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ113_Handler(); + return 0; +} + +static int hc32_irq114(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ114_Handler(); + return 0; +} + +static int hc32_irq115(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ115_Handler(); + return 0; +} + +static int hc32_irq116(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ116_Handler(); + return 0; +} + +static int hc32_irq117(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ117_Handler(); + return 0; +} + +static int hc32_irq118(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ118_Handler(); + return 0; +} + +static int hc32_irq119(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ119_Handler(); + return 0; +} + +static int hc32_irq120(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ120_Handler(); + return 0; +} + +static int hc32_irq121(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ121_Handler(); + return 0; +} + +static int hc32_irq122(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ122_Handler(); + return 0; +} + +static int hc32_irq123(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ123_Handler(); + return 0; +} + +static int hc32_irq124(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ124_Handler(); + return 0; +} + +static int hc32_irq125(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ125_Handler(); + return 0; +} + +static int hc32_irq126(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ126_Handler(); + return 0; +} + +static int hc32_irq127(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ127_Handler(); + return 0; +} + +static int hc32_irq128(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ128_Handler(); + return 0; +} + +static int hc32_irq129(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ129_Handler(); + return 0; +} + +static int hc32_irq130(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ130_Handler(); + return 0; +} + +static int hc32_irq131(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ131_Handler(); + return 0; +} + +static int hc32_irq132(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ132_Handler(); + return 0; +} + +static int hc32_irq133(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ133_Handler(); + return 0; +} + +static int hc32_irq134(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ134_Handler(); + return 0; +} + +static int hc32_irq135(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ135_Handler(); + return 0; +} + +static int hc32_irq136(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ136_Handler(); + return 0; +} + +static int hc32_irq137(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ137_Handler(); + return 0; +} + +static int hc32_irq138(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ138_Handler(); + return 0; +} + +static int hc32_irq139(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ139_Handler(); + return 0; +} + +static int hc32_irq140(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ140_Handler(); + return 0; +} + +static int hc32_irq141(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ141_Handler(); + return 0; +} + +static int hc32_irq142(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ142_Handler(); + return 0; +} + +static int hc32_irq143(int irq, FAR void *context, FAR void *arg) +{ + up_irq_save(); + IRQ143_Handler(); + return 0; +} + /**************************************************************************** * Name: hc32_prioritize_syscall @@ -297,6 +1360,169 @@ static int hc32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, * Public Functions ****************************************************************************/ +void hc32_attach_irqs(void) +{ + irq_attach(HC32_IRQ_FIRST + Int000_IRQn, hc32_irq000, NULL); + irq_attach(HC32_IRQ_FIRST + Int001_IRQn, hc32_irq001, NULL); + irq_attach(HC32_IRQ_FIRST + Int002_IRQn, hc32_irq002, NULL); + irq_attach(HC32_IRQ_FIRST + Int003_IRQn, hc32_irq003, NULL); + irq_attach(HC32_IRQ_FIRST + Int004_IRQn, hc32_irq004, NULL); + irq_attach(HC32_IRQ_FIRST + Int005_IRQn, hc32_irq005, NULL); + irq_attach(HC32_IRQ_FIRST + Int006_IRQn, hc32_irq006, NULL); + irq_attach(HC32_IRQ_FIRST + Int007_IRQn, hc32_irq007, NULL); + irq_attach(HC32_IRQ_FIRST + Int008_IRQn, hc32_irq008, NULL); + irq_attach(HC32_IRQ_FIRST + Int009_IRQn, hc32_irq009, NULL); + + irq_attach(HC32_IRQ_FIRST + Int010_IRQn, hc32_irq010, NULL); + irq_attach(HC32_IRQ_FIRST + Int011_IRQn, hc32_irq011, NULL); + irq_attach(HC32_IRQ_FIRST + Int012_IRQn, hc32_irq012, NULL); + irq_attach(HC32_IRQ_FIRST + Int013_IRQn, hc32_irq013, NULL); + irq_attach(HC32_IRQ_FIRST + Int014_IRQn, hc32_irq014, NULL); + irq_attach(HC32_IRQ_FIRST + Int015_IRQn, hc32_irq015, NULL); + irq_attach(HC32_IRQ_FIRST + Int016_IRQn, hc32_irq016, NULL); + irq_attach(HC32_IRQ_FIRST + Int017_IRQn, hc32_irq017, NULL); + irq_attach(HC32_IRQ_FIRST + Int018_IRQn, hc32_irq018, NULL); + irq_attach(HC32_IRQ_FIRST + Int019_IRQn, hc32_irq019, NULL); + + irq_attach(HC32_IRQ_FIRST + Int020_IRQn, hc32_irq020, NULL); + irq_attach(HC32_IRQ_FIRST + Int021_IRQn, hc32_irq021, NULL); + irq_attach(HC32_IRQ_FIRST + Int022_IRQn, hc32_irq022, NULL); + irq_attach(HC32_IRQ_FIRST + Int023_IRQn, hc32_irq023, NULL); + irq_attach(HC32_IRQ_FIRST + Int024_IRQn, hc32_irq024, NULL); + irq_attach(HC32_IRQ_FIRST + Int025_IRQn, hc32_irq025, NULL); + irq_attach(HC32_IRQ_FIRST + Int026_IRQn, hc32_irq026, NULL); + irq_attach(HC32_IRQ_FIRST + Int027_IRQn, hc32_irq027, NULL); + irq_attach(HC32_IRQ_FIRST + Int028_IRQn, hc32_irq028, NULL); + irq_attach(HC32_IRQ_FIRST + Int029_IRQn, hc32_irq029, NULL); + + irq_attach(HC32_IRQ_FIRST + Int030_IRQn, hc32_irq030, NULL); + irq_attach(HC32_IRQ_FIRST + Int031_IRQn, hc32_irq031, NULL); + irq_attach(HC32_IRQ_FIRST + Int032_IRQn, hc32_irq032, NULL); + irq_attach(HC32_IRQ_FIRST + Int033_IRQn, hc32_irq033, NULL); + irq_attach(HC32_IRQ_FIRST + Int034_IRQn, hc32_irq034, NULL); + irq_attach(HC32_IRQ_FIRST + Int035_IRQn, hc32_irq035, NULL); + irq_attach(HC32_IRQ_FIRST + Int036_IRQn, hc32_irq036, NULL); + irq_attach(HC32_IRQ_FIRST + Int037_IRQn, hc32_irq037, NULL); + irq_attach(HC32_IRQ_FIRST + Int038_IRQn, hc32_irq038, NULL); + irq_attach(HC32_IRQ_FIRST + Int039_IRQn, hc32_irq039, NULL); + + irq_attach(HC32_IRQ_FIRST + Int040_IRQn, hc32_irq040, NULL); + irq_attach(HC32_IRQ_FIRST + Int041_IRQn, hc32_irq041, NULL); + irq_attach(HC32_IRQ_FIRST + Int042_IRQn, hc32_irq042, NULL); + irq_attach(HC32_IRQ_FIRST + Int043_IRQn, hc32_irq043, NULL); + irq_attach(HC32_IRQ_FIRST + Int044_IRQn, hc32_irq044, NULL); + irq_attach(HC32_IRQ_FIRST + Int045_IRQn, hc32_irq045, NULL); + irq_attach(HC32_IRQ_FIRST + Int046_IRQn, hc32_irq046, NULL); + irq_attach(HC32_IRQ_FIRST + Int047_IRQn, hc32_irq047, NULL); + irq_attach(HC32_IRQ_FIRST + Int048_IRQn, hc32_irq048, NULL); + irq_attach(HC32_IRQ_FIRST + Int049_IRQn, hc32_irq049, NULL); + + irq_attach(HC32_IRQ_FIRST + Int050_IRQn, hc32_irq050, NULL); + irq_attach(HC32_IRQ_FIRST + Int051_IRQn, hc32_irq051, NULL); + irq_attach(HC32_IRQ_FIRST + Int052_IRQn, hc32_irq052, NULL); + irq_attach(HC32_IRQ_FIRST + Int053_IRQn, hc32_irq053, NULL); + irq_attach(HC32_IRQ_FIRST + Int054_IRQn, hc32_irq054, NULL); + irq_attach(HC32_IRQ_FIRST + Int055_IRQn, hc32_irq055, NULL); + irq_attach(HC32_IRQ_FIRST + Int056_IRQn, hc32_irq056, NULL); + irq_attach(HC32_IRQ_FIRST + Int057_IRQn, hc32_irq057, NULL); + irq_attach(HC32_IRQ_FIRST + Int058_IRQn, hc32_irq058, NULL); + irq_attach(HC32_IRQ_FIRST + Int059_IRQn, hc32_irq059, NULL); + + irq_attach(HC32_IRQ_FIRST + Int060_IRQn, hc32_irq060, NULL); + irq_attach(HC32_IRQ_FIRST + Int061_IRQn, hc32_irq061, NULL); + irq_attach(HC32_IRQ_FIRST + Int062_IRQn, hc32_irq062, NULL); + irq_attach(HC32_IRQ_FIRST + Int063_IRQn, hc32_irq063, NULL); + irq_attach(HC32_IRQ_FIRST + Int064_IRQn, hc32_irq064, NULL); + irq_attach(HC32_IRQ_FIRST + Int065_IRQn, hc32_irq065, NULL); + irq_attach(HC32_IRQ_FIRST + Int066_IRQn, hc32_irq066, NULL); + irq_attach(HC32_IRQ_FIRST + Int067_IRQn, hc32_irq067, NULL); + irq_attach(HC32_IRQ_FIRST + Int068_IRQn, hc32_irq068, NULL); + irq_attach(HC32_IRQ_FIRST + Int069_IRQn, hc32_irq069, NULL); + + irq_attach(HC32_IRQ_FIRST + Int070_IRQn, hc32_irq070, NULL); + irq_attach(HC32_IRQ_FIRST + Int071_IRQn, hc32_irq071, NULL); + irq_attach(HC32_IRQ_FIRST + Int072_IRQn, hc32_irq072, NULL); + irq_attach(HC32_IRQ_FIRST + Int073_IRQn, hc32_irq073, NULL); + irq_attach(HC32_IRQ_FIRST + Int074_IRQn, hc32_irq074, NULL); + irq_attach(HC32_IRQ_FIRST + Int075_IRQn, hc32_irq075, NULL); + irq_attach(HC32_IRQ_FIRST + Int076_IRQn, hc32_irq076, NULL); + irq_attach(HC32_IRQ_FIRST + Int077_IRQn, hc32_irq077, NULL); + irq_attach(HC32_IRQ_FIRST + Int078_IRQn, hc32_irq078, NULL); + irq_attach(HC32_IRQ_FIRST + Int079_IRQn, hc32_irq079, NULL); + + irq_attach(HC32_IRQ_FIRST + Int080_IRQn, hc32_irq080, NULL); + irq_attach(HC32_IRQ_FIRST + Int081_IRQn, hc32_irq081, NULL); + irq_attach(HC32_IRQ_FIRST + Int082_IRQn, hc32_irq082, NULL); + irq_attach(HC32_IRQ_FIRST + Int083_IRQn, hc32_irq083, NULL); + irq_attach(HC32_IRQ_FIRST + Int084_IRQn, hc32_irq084, NULL); + irq_attach(HC32_IRQ_FIRST + Int085_IRQn, hc32_irq085, NULL); + irq_attach(HC32_IRQ_FIRST + Int086_IRQn, hc32_irq086, NULL); + irq_attach(HC32_IRQ_FIRST + Int087_IRQn, hc32_irq087, NULL); + irq_attach(HC32_IRQ_FIRST + Int088_IRQn, hc32_irq088, NULL); + irq_attach(HC32_IRQ_FIRST + Int089_IRQn, hc32_irq089, NULL); + + irq_attach(HC32_IRQ_FIRST + Int090_IRQn, hc32_irq090, NULL); + irq_attach(HC32_IRQ_FIRST + Int091_IRQn, hc32_irq091, NULL); + irq_attach(HC32_IRQ_FIRST + Int092_IRQn, hc32_irq092, NULL); + irq_attach(HC32_IRQ_FIRST + Int093_IRQn, hc32_irq093, NULL); + irq_attach(HC32_IRQ_FIRST + Int094_IRQn, hc32_irq094, NULL); + irq_attach(HC32_IRQ_FIRST + Int095_IRQn, hc32_irq095, NULL); + irq_attach(HC32_IRQ_FIRST + Int096_IRQn, hc32_irq096, NULL); + irq_attach(HC32_IRQ_FIRST + Int097_IRQn, hc32_irq097, NULL); + irq_attach(HC32_IRQ_FIRST + Int098_IRQn, hc32_irq098, NULL); + irq_attach(HC32_IRQ_FIRST + Int099_IRQn, hc32_irq099, NULL); + + irq_attach(HC32_IRQ_FIRST + Int100_IRQn, hc32_irq100, NULL); + irq_attach(HC32_IRQ_FIRST + Int101_IRQn, hc32_irq101, NULL); + irq_attach(HC32_IRQ_FIRST + Int102_IRQn, hc32_irq102, NULL); + irq_attach(HC32_IRQ_FIRST + Int103_IRQn, hc32_irq103, NULL); + irq_attach(HC32_IRQ_FIRST + Int104_IRQn, hc32_irq104, NULL); + irq_attach(HC32_IRQ_FIRST + Int105_IRQn, hc32_irq105, NULL); + irq_attach(HC32_IRQ_FIRST + Int106_IRQn, hc32_irq106, NULL); + irq_attach(HC32_IRQ_FIRST + Int107_IRQn, hc32_irq107, NULL); + irq_attach(HC32_IRQ_FIRST + Int108_IRQn, hc32_irq108, NULL); + irq_attach(HC32_IRQ_FIRST + Int109_IRQn, hc32_irq109, NULL); + + irq_attach(HC32_IRQ_FIRST + Int110_IRQn, hc32_irq110, NULL); + irq_attach(HC32_IRQ_FIRST + Int111_IRQn, hc32_irq111, NULL); + irq_attach(HC32_IRQ_FIRST + Int112_IRQn, hc32_irq112, NULL); + irq_attach(HC32_IRQ_FIRST + Int113_IRQn, hc32_irq113, NULL); + irq_attach(HC32_IRQ_FIRST + Int114_IRQn, hc32_irq114, NULL); + irq_attach(HC32_IRQ_FIRST + Int115_IRQn, hc32_irq115, NULL); + irq_attach(HC32_IRQ_FIRST + Int116_IRQn, hc32_irq116, NULL); + irq_attach(HC32_IRQ_FIRST + Int117_IRQn, hc32_irq117, NULL); + irq_attach(HC32_IRQ_FIRST + Int118_IRQn, hc32_irq118, NULL); + irq_attach(HC32_IRQ_FIRST + Int119_IRQn, hc32_irq119, NULL); + + irq_attach(HC32_IRQ_FIRST + Int120_IRQn, hc32_irq120, NULL); + irq_attach(HC32_IRQ_FIRST + Int121_IRQn, hc32_irq121, NULL); + irq_attach(HC32_IRQ_FIRST + Int122_IRQn, hc32_irq122, NULL); + irq_attach(HC32_IRQ_FIRST + Int123_IRQn, hc32_irq123, NULL); + irq_attach(HC32_IRQ_FIRST + Int124_IRQn, hc32_irq124, NULL); + irq_attach(HC32_IRQ_FIRST + Int125_IRQn, hc32_irq125, NULL); + irq_attach(HC32_IRQ_FIRST + Int126_IRQn, hc32_irq126, NULL); + irq_attach(HC32_IRQ_FIRST + Int127_IRQn, hc32_irq127, NULL); + irq_attach(HC32_IRQ_FIRST + Int128_IRQn, hc32_irq128, NULL); + irq_attach(HC32_IRQ_FIRST + Int129_IRQn, hc32_irq129, NULL); + + irq_attach(HC32_IRQ_FIRST + Int130_IRQn, hc32_irq130, NULL); + irq_attach(HC32_IRQ_FIRST + Int131_IRQn, hc32_irq131, NULL); + irq_attach(HC32_IRQ_FIRST + Int132_IRQn, hc32_irq132, NULL); + irq_attach(HC32_IRQ_FIRST + Int133_IRQn, hc32_irq133, NULL); + irq_attach(HC32_IRQ_FIRST + Int134_IRQn, hc32_irq134, NULL); + irq_attach(HC32_IRQ_FIRST + Int135_IRQn, hc32_irq135, NULL); + irq_attach(HC32_IRQ_FIRST + Int136_IRQn, hc32_irq136, NULL); + irq_attach(HC32_IRQ_FIRST + Int137_IRQn, hc32_irq137, NULL); + irq_attach(HC32_IRQ_FIRST + Int138_IRQn, hc32_irq138, NULL); + irq_attach(HC32_IRQ_FIRST + Int139_IRQn, hc32_irq139, NULL); + + irq_attach(HC32_IRQ_FIRST + Int140_IRQn, hc32_irq140, NULL); + irq_attach(HC32_IRQ_FIRST + Int141_IRQn, hc32_irq141, NULL); + irq_attach(HC32_IRQ_FIRST + Int142_IRQn, hc32_irq142, NULL); + irq_attach(HC32_IRQ_FIRST + Int143_IRQn, hc32_irq143, NULL); +} + + /**************************************************************************** * Name: up_irqinitialize ****************************************************************************/ @@ -315,7 +1541,7 @@ void up_irqinitialize(void) } /* The standard location for the vector table is at the beginning of FLASH - * at address 0x0800:0000. If we are using the STMicro DFU bootloader, + * at address 0x0000:0000. If we are using the HC32 bootloader, * then the vector table will be offset to a different location in FLASH * and we will need to set the NVIC vector location to this alternative * location. @@ -371,8 +1597,8 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(HC32_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(HC32_IRQ_HARDFAULT, arm_hardfault, NULL); + irq_attach(HC32_IRQ_SVCALL, hc32_svc, NULL); + irq_attach(HC32_IRQ_HARDFAULT, hc32_hardfault, NULL); /* Set the priority of the SVCall interrupt */ @@ -388,7 +1614,7 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(HC32_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(HC32_IRQ_MEMFAULT, hc32_memfault, NULL); up_enable_irq(HC32_IRQ_MEMFAULT); #endif @@ -403,7 +1629,7 @@ void up_irqinitialize(void) #ifdef CONFIG_DEBUG_FEATURES irq_attach(HC32_IRQ_NMI, hc32_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(HC32_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(HC32_IRQ_MEMFAULT, hc32_memfault, NULL); #endif irq_attach(HC32_IRQ_BUSFAULT, hc32_busfault, NULL); irq_attach(HC32_IRQ_USAGEFAULT, hc32_usagefault, NULL); @@ -412,6 +1638,8 @@ void up_irqinitialize(void) irq_attach(HC32_IRQ_RESERVED, hc32_reserved, NULL); #endif + hc32_attach_irqs(); + hc32_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -446,7 +1674,8 @@ void up_disable_irq(int irq) if (irq >= HC32_IRQ_FIRST) { - putreg32(bit, regaddr); + uint32_t act_irq = irq - HC32_IRQ_FIRST; + NVIC_DisableIRQ(act_irq); } else { @@ -481,7 +1710,10 @@ void up_enable_irq(int irq) if (irq >= HC32_IRQ_FIRST) { - putreg32(bit, regaddr); + uint32_t act_irq = irq - HC32_IRQ_FIRST; + NVIC_ClearPendingIRQ(act_irq); + NVIC_SetPriority(act_irq, DDL_IRQ_PRIORITY_00); + NVIC_EnableIRQ(act_irq); } else { diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_lowputc.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_lowputc.c index 7554b27a9..0ac9edcf5 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_lowputc.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_lowputc.c @@ -37,34 +37,12 @@ #include "hc32_lowputc.h" #include "hc32f4a0_usart.h" #include "hc32_ddl.h" +#include "hc32_uart.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* UART multiple processor ID definition */ -#define UART_MASTER_STATION_ID (0x20U) -#define UART_SLAVE_STATION_ID (0x21U) - -/* Ring buffer size */ -#define IS_RING_BUFFER_EMPTY(x) (0U == ((x)->u16UsedSize)) - -/* Multi-processor silence mode */ -#define LP_UART_NORMAL_MODE (0U) -#define LP_UART_SILENCE_MODE (1U) - -/** - * @brief Ring buffer structure definition - */ -typedef struct -{ - uint16_t u16Capacity; - __IO uint16_t u16UsedSize; - uint16_t u16InIdx; - uint16_t u16OutIdx; - uint8_t au8Buf[50]; -} stc_ring_buffer_t; - /**************************************************************************** * Private Types ****************************************************************************/ @@ -81,212 +59,10 @@ typedef struct * Private Data ****************************************************************************/ -static uint8_t m_u8UartSilenceMode = LP_UART_NORMAL_MODE; - -static stc_ring_buffer_t m_stcRingBuf = { - .u16InIdx = 0U, - .u16OutIdx = 0U, - .u16UsedSize = 0U, - .u16Capacity = sizeof (m_stcRingBuf.au8Buf), -}; - /**************************************************************************** * Private Functions ****************************************************************************/ -/** - * @brief Set silence mode. - * @param [in] u8Mode Silence mode - * This parameter can be one of the following values: - * @arg LP_UART_SILENCE_MODE: UART silence mode - * @arg LP_UART_NORMAL_MODE: UART normal mode - * @retval None - */ -static void UsartSetSilenceMode(uint8_t u8Mode) -{ - m_u8UartSilenceMode = u8Mode; -} - -/** - * @brief Get silence mode. - * @param [in] None - * @retval Returned value can be one of the following values: - * @arg LP_UART_SILENCE_MODE: UART silence mode - * @arg LP_UART_NORMAL_MODE: UART normal mode - */ -static uint8_t UsartGetSilenceMode(void) -{ - return m_u8UartSilenceMode; -} - -/** - * @brief Instal IRQ handler. - * @param [in] pstcConfig Pointer to struct @ref stc_irq_signin_config_t - * @param [in] u32Priority Interrupt priority - * @retval None - */ -static void InstalIrqHandler(const stc_irq_signin_config_t *pstcConfig, - uint32_t u32Priority) -{ - if (NULL != pstcConfig) - { - (void)INTC_IrqSignIn(pstcConfig); - NVIC_ClearPendingIRQ(pstcConfig->enIRQn); - NVIC_SetPriority(pstcConfig->enIRQn, u32Priority); - NVIC_EnableIRQ(pstcConfig->enIRQn); - } -} - - -/** - * @brief Write ring buffer. - * @param [in] pstcBuffer Pointer to a @ref stc_ring_buffer_t structure - * @param [in] pu8Data Pointer to data buffer to read - * @retval An en_result_t enumeration value: - * - Ok: Write success. - * - ErrorNotReady: Buffer is empty. - */ -static en_result_t RingBufRead(stc_ring_buffer_t *pstcBuffer, uint8_t *pu8Data) -{ - en_result_t enRet = Ok; - - if (pstcBuffer->u16UsedSize == 0U) - { - enRet = ErrorNotReady; - } - else - { - *pu8Data = pstcBuffer->au8Buf[pstcBuffer->u16OutIdx++]; - pstcBuffer->u16OutIdx %= pstcBuffer->u16Capacity; - pstcBuffer->u16UsedSize--; - } - - return enRet; -} - -/** - * @brief UART TX Empty IRQ callback. - * @param None - * @retval None - */ -static void USART_TxEmpty_IrqCallback(void) -{ - uint8_t u8Data = 0U; - en_flag_status_t enFlag = USART_GetStatus(LP_UNIT, USART_FLAG_TXE); - en_functional_state_t enState = USART_GetFuncState(LP_UNIT, USART_INT_TXE); - - if ((Set == enFlag) && (Enable == enState)) - { - USART_SendId(LP_UNIT, UART_SLAVE_STATION_ID); - - while (Reset == USART_GetStatus(LP_UNIT, USART_FLAG_TC)) /* Wait Tx data register empty */ - { - } - - if (Ok == RingBufRead(&m_stcRingBuf, &u8Data)) - { - USART_SendData(LP_UNIT, (uint16_t)u8Data); - } - - if (IS_RING_BUFFER_EMPTY(&m_stcRingBuf)) - { - USART_FuncCmd(LP_UNIT, USART_INT_TXE, Disable); - USART_FuncCmd(LP_UNIT, USART_INT_TC, Enable); - } - } -} - -/** - * @brief UART TX Complete IRQ callback. - * @param None - * @retval None - */ -static void USART_TxComplete_IrqCallback(void) -{ - en_flag_status_t enFlag = USART_GetStatus(LP_UNIT, USART_FLAG_TC); - en_functional_state_t enState = USART_GetFuncState(LP_UNIT, USART_INT_TC); - - if ((Set == enFlag) && (Enable == enState)) - { - /* Disable TX function */ - USART_FuncCmd(LP_UNIT, (USART_TX | USART_RX | USART_INT_TC), Disable); - - /* Enable RX function */ - USART_FuncCmd(LP_UNIT, (USART_RX | USART_INT_RX), Enable); - } -} - -/** - * @brief Write ring buffer. - * @param [in] pstcBuffer Pointer to a @ref stc_ring_buffer_t structure - * @param [in] u8Data Data to write - * @retval An en_result_t enumeration value: - * - Ok: Write success. - * - ErrorBufferFull: Buffer is full. - */ -static en_result_t write_ring_buf(stc_ring_buffer_t *pstcBuffer, uint8_t u8Data) -{ - en_result_t enRet = Ok; - - if (pstcBuffer->u16UsedSize >= pstcBuffer->u16Capacity) - { - enRet = ErrorBufferFull; - } - else - { - pstcBuffer->au8Buf[pstcBuffer->u16InIdx++] = u8Data; - pstcBuffer->u16InIdx %= pstcBuffer->u16Capacity; - pstcBuffer->u16UsedSize++; - } - - return enRet; -} - -/** - * @brief UART RX IRQ callback. - * @param None - * @retval None - */ -static void USART_Rx_IrqCallback(void) -{ - uint8_t u8RxData; - en_flag_status_t enFlag = USART_GetStatus(LP_UNIT, USART_FLAG_RXNE); - en_functional_state_t enState = USART_GetFuncState(LP_UNIT, USART_INT_RX); - - if ((Set == enFlag) && (Enable == enState)) - { - u8RxData = (uint8_t)USART_RecData(LP_UNIT); - - if ((Reset == USART_GetStatus(LP_UNIT, USART_FLAG_MPB)) && - (LP_UART_NORMAL_MODE == UsartGetSilenceMode())) - { - write_ring_buf(&m_stcRingBuf, u8RxData); - } - else - { - if (UART_MASTER_STATION_ID != u8RxData) - { - USART_SilenceCmd(LP_UNIT, Enable); - UsartSetSilenceMode(LP_UART_SILENCE_MODE); - } - else - { - UsartSetSilenceMode(LP_UART_NORMAL_MODE); - } - } - } -} - -/** - * @brief UART RX Error IRQ callback. - * @param None - * @retval None - */ -static void USART_RxErr_IrqCallback(void) -{ - USART_ClearStatus(LP_UNIT, (USART_CLEAR_FLAG_FE | USART_CLEAR_FLAG_PE | USART_CLEAR_FLAG_ORE)); -} - void hc32_unlock(void) { /* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */ @@ -342,30 +118,19 @@ void hc32_print_portinit(void) void arm_lowputc(char ch) { - while(Set != USART_GetStatus(LP_UNIT, USART_FLAG_TXE)); - USART_SendData(LP_UNIT, ch); + while(Set != USART_GetStatus(DBG_UNIT, USART_FLAG_TXE)); + USART_SendData(DBG_UNIT, ch); } - -/**************************************************************************** - * Name: hc32_lowsetup - * - * Description: - * This performs basic initialization of the USART used for the serial - * console. Its purpose is to get the console output available as soon - * as possible. - * - ****************************************************************************/ - void hc32_lowsetup(void) { - stc_irq_signin_config_t stcIrqSigninCfg; - const stc_usart_multiprocessor_init_t stcUartMultiProcessorInit = { - .u32Baudrate = 115200UL, + const stc_usart_uart_init_t stcUartInit = { + .u32Baudrate = BSP_PRINTF_BAUDRATE, .u32BitDirection = USART_LSB, .u32StopBit = USART_STOPBIT_1BIT, + .u32Parity = USART_PARITY_NONE, .u32DataWidth = USART_DATA_LENGTH_8BIT, - .u32ClkMode = USART_INTERNCLK_NONE_OUTPUT, + .u32ClkMode = USART_INTERNCLK_OUTPUT, .u32PclkDiv = USART_PCLK_DIV64, .u32OversamplingBits = USART_OVERSAMPLING_8BIT, .u32NoiseFilterState = USART_NOISE_FILTER_DISABLE, @@ -380,42 +145,18 @@ void hc32_lowsetup(void) DDL_PrintfInit(BSP_PRINTF_DEVICE, BSP_PRINTF_BAUDRATE, hc32_print_portinit); /* Configure USART RX/TX pin. */ - GPIO_SetFunc(LP_RX_PORT, LP_RX_PIN, LP_RX_GPIO_FUNC, PIN_SUBFUNC_DISABLE); - GPIO_SetFunc(LP_TX_PORT, LP_TX_PIN, LP_TX_GPIO_FUNC, PIN_SUBFUNC_DISABLE); + GPIO_SetFunc(DBG_RX_PORT, DBG_RX_PIN, DBG_RX_GPIO_FUNC, PIN_SUBFUNC_DISABLE); + GPIO_SetFunc(DBG_TX_PORT, DBG_TX_PIN, DBG_TX_GPIO_FUNC, PIN_SUBFUNC_DISABLE); hc32_lock(); /* Enable peripheral clock */ - PWC_Fcg3PeriphClockCmd(LP_FUNCTION_CLK_GATE, Enable); - - /* Set silence mode */ - UsartSetSilenceMode(LP_UART_SILENCE_MODE); + PWC_Fcg3PeriphClockCmd(DBG_FUNCTION_CLK_GATE, Enable); /* Initialize UART function. */ - (void)USART_MultiProcessorInit(LP_UNIT, &stcUartMultiProcessorInit); - - /* Register error IRQ handler && configure NVIC. */ - stcIrqSigninCfg.enIRQn = LP_UNIT_ERR_INT_IRQn; - stcIrqSigninCfg.enIntSrc = LP_UNIT_ERR_INT_SRC; - stcIrqSigninCfg.pfnCallback = &USART_RxErr_IrqCallback; - InstalIrqHandler(&stcIrqSigninCfg, DDL_IRQ_PRIORITY_DEFAULT); - - /* Register RX IRQ handler && configure NVIC. */ - stcIrqSigninCfg.enIRQn = LP_UNIT_RX_INT_IRQn; - stcIrqSigninCfg.enIntSrc = LP_UNIT_RX_INT_SRC; - stcIrqSigninCfg.pfnCallback = &USART_Rx_IrqCallback; - InstalIrqHandler(&stcIrqSigninCfg, DDL_IRQ_PRIORITY_00); - - /* Register TX IRQ handler && configure NVIC. */ - stcIrqSigninCfg.enIRQn = LP_UNIT_TX_INT_IRQn; - stcIrqSigninCfg.enIntSrc = LP_UNIT_TX_INT_SRC; - stcIrqSigninCfg.pfnCallback = &USART_TxEmpty_IrqCallback; - InstalIrqHandler(&stcIrqSigninCfg, DDL_IRQ_PRIORITY_DEFAULT); - - /* Register TC IRQ handler && configure NVIC. */ - stcIrqSigninCfg.enIRQn = LP_UNIT_TCI_INT_IRQn; - stcIrqSigninCfg.enIntSrc = LP_UNIT_TCI_INT_SRC; - stcIrqSigninCfg.pfnCallback = &USART_TxComplete_IrqCallback; - InstalIrqHandler(&stcIrqSigninCfg, DDL_IRQ_PRIORITY_DEFAULT); + if (Ok != USART_UartInit(DBG_UNIT, &stcUartInit)) + { + for (;;); + } } diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_serial.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_serial.c index 9398d5e27..5c4e9f861 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_serial.c +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_serial.c @@ -154,10 +154,21 @@ struct up_dev_s #endif const uint32_t irq; /* IRQ associated with this USART */ - const uint32_t apbclock; /* PCLK 1 or 2 frequency */ + const uint32_t clk_gate; const uint32_t usartbase; /* Base address of USART registers */ const uint32_t tx_gpio; /* U[S]ART TX GPIO pin configuration */ + const uint32_t tx_func; const uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */ + const uint32_t rx_func; + const uint32_t rx_irq; + const uint32_t tx_irq; + const uint32_t txc_irq; + const uint32_t err_irq; + const uint32_t rxint_src; + const uint32_t txint_src; + const uint32_t txcint_src; + const uint32_t errint_src; + const stc_usart_uart_init_t param; // U[S]ART parameter #ifdef CONFIG_SERIAL_IFLOWCONTROL const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */ #endif @@ -175,7 +186,6 @@ struct up_dev_s * Private Function Prototypes ****************************************************************************/ -static void up_set_format(struct uart_dev_s *dev); static int up_setup(struct uart_dev_s *dev); static void up_shutdown(struct uart_dev_s *dev); static int up_attach(struct uart_dev_s *dev); @@ -194,13 +204,6 @@ static void up_txint(struct uart_dev_s *dev, bool enable); static bool up_txready(struct uart_dev_s *dev); -#ifdef CONFIG_PM -static void up_pm_notify(struct pm_callback_s *cb, int dowmin, - enum pm_state_e pmstate); -static int up_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - /**************************************************************************** * Private Data ****************************************************************************/ @@ -557,35 +560,46 @@ static struct up_dev_s g_uart5priv = /* UART RX/TX Port/Pin definition */ #define USART_RX_PORT (GPIO_PORT_H) /* PH6: USART6_RX */ #define USART_RX_PIN (GPIO_PIN_06) -#define USART_RX_GPIO_FUNC (GPIO_FUNC_37_USART6_RX) +#define USART_RX_FUNC (GPIO_FUNC_37_USART6_RX) #define USART_TX_PORT (GPIO_PORT_E) /* PE6: USART6_TX */ #define USART_TX_PIN (GPIO_PIN_06) -#define USART_TX_GPIO_FUNC (GPIO_FUNC_36_USART6_TX) +#define USART_TX_FUNC (GPIO_FUNC_36_USART6_TX) /* UART unit definition */ #define USART_UNIT (M4_USART6) -#define USART_FUNCTION_CLK_GATE (PWC_FCG3_USART6) +#define USART_CLK_GATE (PWC_FCG3_USART6) /* UART unit interrupt definition */ #define USART_UNIT_ERR_INT_SRC (INT_USART6_EI) -#define USART_UNIT_ERR_INT_IRQn (Int015_IRQn + HC32_IRQ_FIRST) +#define USART_UNIT_ERR_INT_IRQn (Int011_IRQn + HC32_IRQ_FIRST) #define USART_UNIT_RX_INT_SRC (INT_USART6_RI) -#define USART_UNIT_RX_INT_IRQn (Int010_IRQn + HC32_IRQ_FIRST) +#define USART_UNIT_RX_INT_IRQn (Int012_IRQn + HC32_IRQ_FIRST) #define USART_UNIT_TX_INT_SRC (INT_USART6_TI) -#define USART_UNIT_TX_INT_IRQn (Int102_IRQn + HC32_IRQ_FIRST) +#define USART_UNIT_TX_INT_IRQn (Int013_IRQn + HC32_IRQ_FIRST) #define USART_UNIT_TCI_INT_SRC (INT_USART6_TCI) -#define USART_UNIT_TCI_INT_IRQn (Int099_IRQn + HC32_IRQ_FIRST) +#define USART_UNIT_TCI_INT_IRQn (Int014_IRQn + HC32_IRQ_FIRST) -#define HC32_UART6_BASE 0x40020C00UL// M4_USART6 -#define HC32_IRQ_USART6 (Int010_IRQn + HC32_IRQ_FIRST) #define GPIO_USART6_TX GPIO_PINSET(USART_TX_PORT, USART_TX_PIN) #define GPIO_USART6_RX GPIO_PINSET(USART_RX_PORT, USART_RX_PIN) -#define HC32_PCLK2_FREQUENCY 120000000 + +const stc_usart_uart_init_t usart6config = { + .u32Baudrate = BSP_PRINTF_BAUDRATE, + .u32BitDirection = USART_LSB, + .u32StopBit = USART_STOPBIT_1BIT, + .u32Parity = USART_PARITY_NONE, + .u32DataWidth = USART_DATA_LENGTH_8BIT, + .u32ClkMode = USART_INTERNCLK_OUTPUT, + .u32PclkDiv = USART_PCLK_DIV64, + .u32OversamplingBits = USART_OVERSAMPLING_8BIT, + .u32NoiseFilterState = USART_NOISE_FILTER_DISABLE, + .u32SbDetectPolarity = USART_SB_DETECT_FALLING, +}; + static struct up_dev_s g_usart6priv = { @@ -608,15 +622,35 @@ static struct up_dev_s g_usart6priv = .priv = &g_usart6priv, }, - .irq = HC32_IRQ_USART6, - .parity = CONFIG_UART6_PARITY, - .bits = CONFIG_UART6_BITS, - .stopbits2 = CONFIG_UART6_2STOP, - .baud = CONFIG_UART6_BAUD, - .apbclock = HC32_PCLK2_FREQUENCY, - .usartbase = HC32_UART6_BASE, + .irq = USART_UNIT_RX_INT_IRQn, + .rx_irq = USART_UNIT_RX_INT_IRQn, + .tx_irq = USART_UNIT_TX_INT_IRQn, + .txc_irq = USART_UNIT_TCI_INT_IRQn, + .err_irq = USART_UNIT_ERR_INT_IRQn, + .rxint_src = USART_UNIT_RX_INT_SRC, + .txint_src = USART_UNIT_TX_INT_SRC, + .txcint_src = USART_UNIT_TCI_INT_SRC, + .errint_src = USART_UNIT_ERR_INT_SRC, + + .clk_gate = USART_CLK_GATE, + .usartbase = (uint32_t)USART_UNIT, .tx_gpio = GPIO_USART6_TX, + .tx_func = USART_TX_FUNC, .rx_gpio = GPIO_USART6_RX, + .rx_func = USART_RX_FUNC, + .param = + { + .u32Baudrate = BSP_PRINTF_BAUDRATE, + .u32BitDirection = USART_LSB, + .u32StopBit = USART_STOPBIT_1BIT, + .u32Parity = USART_PARITY_NONE, + .u32DataWidth = USART_DATA_LENGTH_8BIT, + .u32ClkMode = USART_INTERNCLK_OUTPUT, + .u32PclkDiv = USART_PCLK_DIV64, + .u32OversamplingBits = USART_OVERSAMPLING_8BIT, + .u32NoiseFilterState = USART_NOISE_FILTER_DISABLE, + .u32SbDetectPolarity = USART_SB_DETECT_FALLING + }, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART6_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART6_CTS, @@ -637,112 +671,7 @@ static struct up_dev_s g_usart6priv = }; #endif -/* This describes the state of the HC32 UART7 port. */ - -#ifdef CONFIG_UART7_SERIALDRIVER -static struct up_dev_s g_uart7priv = -{ - .dev = - { -#if CONSOLE_UART == 7 - .isconsole = true, -#endif - .recv = - { - .size = CONFIG_UART7_RXBUFSIZE, - .buffer = g_uart7rxbuffer, - }, - .xmit = - { - .size = CONFIG_UART7_TXBUFSIZE, - .buffer = g_uart7txbuffer, - }, - - .ops = &g_uart_ops, - .priv = &g_uart7priv, - }, - - .irq = HC32_IRQ_UART7, - .parity = CONFIG_UART7_PARITY, - .bits = CONFIG_UART7_BITS, - .stopbits2 = CONFIG_UART7_2STOP, - .baud = CONFIG_UART7_BAUD, - .apbclock = HC32_PCLK1_FREQUENCY, - .usartbase = HC32_UART7_BASE, - .tx_gpio = GPIO_UART7_TX, - .rx_gpio = GPIO_UART7_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART7_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_UART7_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART7_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_UART7_RTS, -#endif - -#ifdef CONFIG_UART7_RS485 - .rs485_dir_gpio = GPIO_UART7_RS485_DIR, -# if (CONFIG_UART7_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -#endif -}; -#endif - -/* This describes the state of the HC32 UART8 port. */ - -#ifdef CONFIG_UART8_SERIALDRIVER -static struct up_dev_s g_uart8priv = -{ - .dev = - { -#if CONSOLE_UART == 8 - .isconsole = true, -#endif - .recv = - { - .size = CONFIG_UART8_RXBUFSIZE, - .buffer = g_uart8rxbuffer, - }, - .xmit = - { - .size = CONFIG_UART8_TXBUFSIZE, - .buffer = g_uart8txbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_uart8priv, - }, - - .irq = HC32_IRQ_UART8, - .parity = CONFIG_UART8_PARITY, - .bits = CONFIG_UART8_BITS, - .stopbits2 = CONFIG_UART8_2STOP, - .baud = CONFIG_UART8_BAUD, - .apbclock = HC32_PCLK1_FREQUENCY, - .usartbase = HC32_UART8_BASE, - .tx_gpio = GPIO_UART8_TX, - .rx_gpio = GPIO_UART8_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART8_OFLOWCONTROL) - .oflow = true, - .cts_gpio = GPIO_UART8_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART8_IFLOWCONTROL) - .iflow = true, - .rts_gpio = GPIO_UART8_RTS, -#endif - -#ifdef CONFIG_UART8_RS485 - .rs485_dir_gpio = GPIO_UART8_RS485_DIR, -# if (CONFIG_UART8_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, -# endif -#endif -}; -#endif +static struct up_dev_s *g_uart_rx_dev = &g_usart6priv; /* This table lets us iterate over the configured USARTs */ @@ -774,35 +703,114 @@ static struct up_dev_s * const g_uart_devs[HC32_NUSART] = #endif }; -#ifdef CONFIG_PM -static struct pm_callback_s g_serialcb = +static inline uint32_t up_serialin(struct up_dev_s *priv, int offset); + +void hc32_rx_irq_cb(void) { - .notify = up_pm_notify, - .prepare = up_pm_prepare, -}; -#endif + up_interrupt(g_uart_rx_dev->rx_irq, NULL, g_uart_rx_dev); +} + +void hc32_tx_irq_cb(void) +{ + up_interrupt(g_uart_rx_dev->tx_irq, NULL, g_uart_rx_dev); +} + +void hc32_txc_irq_cb(void) +{ + up_interrupt(g_uart_rx_dev->txc_irq, NULL, g_uart_rx_dev); +} + +void hc32_err_irq_cb(void) +{ + up_interrupt(g_uart_rx_dev->err_irq, NULL, g_uart_rx_dev); +} + +void hc32_handle_recv_buf(void) +{ + struct up_dev_s *priv = g_uart_rx_dev; + struct uart_buffer_s *recv = &priv->dev.recv; + char recv_buf[255] = {0}; + int i, j = 0; + static int cnt = 0; + static int last_tail = 0; + + if((recv->head != recv->tail) && (cnt ++ > 30)) + { + last_tail = recv->tail; + for(i = recv->tail; i < recv->head; i ++) + { + recv_buf[j++] = recv->buffer[last_tail++]; + } + hc32_console_handle(recv_buf); + hc32_print("nsh>%s\n", recv_buf); + recv->tail = recv->head; + cnt = 0; + last_tail = 0; + } +} + +void hc32_handle_xmit_buf(void) +{ + struct up_dev_s *priv = g_uart_rx_dev; + int i, j = 0; + char xmit_buf[255] = {0}; + + if(priv->dev.xmit.tail != priv->dev.xmit.head) + { + for(i = priv->dev.xmit.tail; i < priv->dev.xmit.head; i ++) + { + xmit_buf[j++] = priv->dev.xmit.buffer[i++]; + } + hc32_print("nsh>%s", xmit_buf); + } +} + +void hc32_uart_handle(void) +{ + hc32_handle_recv_buf(); +} /**************************************************************************** * Private Functions ****************************************************************************/ -void hc32_print(const char *fmt, ...) +int hc32_print(const char *fmt, ...) { - int i; + int i, ret; va_list ap; char buf[256]; memset(buf, 0, sizeof(buf)); va_start(ap, fmt); - vsnprintf(buf, 255, fmt, ap); + ret = vsnprintf(buf, 255, fmt, ap); va_end(ap); + USART_FuncCmd(USART_UNIT, USART_RX | USART_TX, Enable); - USART_FuncCmd(USART_UNIT, USART_TX, Enable); + arm_lowputc('-'); + arm_lowputc(' '); for (i = 0; i < strlen(buf); i++) { - while(Set != USART_GetStatus(USART_UNIT, USART_FLAG_TXE)); - USART_SendData(USART_UNIT, (uint16_t)*(buf + i)); + arm_lowputc((uint16_t)*(buf + i)); + } + return ret; +} + +/** + * @brief Instal IRQ handler. + * @param [in] pstcConfig Pointer to struct @ref stc_irq_signin_config_t + * @param [in] u32Priority Interrupt priority + * @retval None + */ +static void hc32_enable_irq(const stc_irq_signin_config_t *pstcConfig, + uint32_t u32Priority) +{ + if (NULL != pstcConfig) + { + (void)INTC_IrqSignIn(pstcConfig); + NVIC_ClearPendingIRQ(pstcConfig->enIRQn); + NVIC_SetPriority(pstcConfig->enIRQn, u32Priority); + NVIC_EnableIRQ(pstcConfig->enIRQn); } } @@ -825,6 +833,7 @@ static inline void up_serialout(struct up_dev_s *priv, int offset, putreg32(value, priv->usartbase + offset); } + /**************************************************************************** * Name: up_setusartint ****************************************************************************/ @@ -832,7 +841,6 @@ static inline void up_serialout(struct up_dev_s *priv, int offset, static inline void up_setusartint(struct up_dev_s *priv, uint16_t ie) { uint32_t cr; - M4_USART_TypeDef *base = (M4_USART_TypeDef *)priv->usartbase; /* Save the interrupt mask */ @@ -842,12 +850,12 @@ static inline void up_setusartint(struct up_dev_s *priv, uint16_t ie) * table above) */ - cr = up_serialin(priv, base->_CR1); + cr = up_serialin(priv, offsetof(M4_USART_TypeDef, _CR1)); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - up_serialout(priv, base->_CR1, cr); -// -// cr = up_serialin(priv, base->_CR3); + up_serialout(priv, offsetof(M4_USART_TypeDef, _CR1), cr); + +// cr = up_serialin(priv, offsetof(M4_USART_TypeDef, _CR3)); // cr &= ~USART_CR3_EIE; // cr |= (ie & USART_CR3_EIE); // up_serialout(priv, base->_CR3, cr); @@ -861,8 +869,6 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie) { irqstate_t flags; -// hc32_print("check %s line %d\n", __func__, __LINE__); - flags = enter_critical_section(); up_setusartint(priv, ie); @@ -877,7 +883,6 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie) static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) { irqstate_t flags; - M4_USART_TypeDef *base = (M4_USART_TypeDef *)priv->usartbase; flags = enter_critical_section(); @@ -903,7 +908,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) * USART_CR3_CTSIE USART_SR_CTS CTS flag (not used) */ - cr1 = up_serialin(priv, base->_CR1); + cr1 = up_serialin(priv, offsetof(M4_USART_TypeDef, _CR1)); *ie = cr1 & (USART_CR1_USED_INTS); } @@ -914,36 +919,44 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) leave_critical_section(flags); } -/**************************************************************************** - * Name: up_set_format - * - * Description: - * Set the serial line format and speed. - * - ****************************************************************************/ - -#ifndef CONFIG_SUPPRESS_UART_CONFIG -static void up_set_format(struct uart_dev_s *dev) +static int hc32_enable_serialirq(struct uart_dev_s *dev) { + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + stc_irq_signin_config_t cfg; -} -#endif /* CONFIG_SUPPRESS_UART_CONFIG */ + { + memset(&cfg, 0, sizeof(cfg)); + cfg.enIRQn = priv->rx_irq - HC32_IRQ_FIRST; + cfg.enIntSrc = priv->rxint_src; + cfg.pfnCallback = &hc32_rx_irq_cb; + hc32_enable_irq(&cfg, DDL_IRQ_PRIORITY_DEFAULT); + } -/**************************************************************************** - * Name: up_set_apb_clock - * - * Description: - * Enable or disable APB clock for the USART peripheral - * - * Input Parameters: - * dev - A reference to the UART driver state structure - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - ****************************************************************************/ + { + memset(&cfg, 0, sizeof(cfg)); + cfg.enIRQn = priv->tx_irq - HC32_IRQ_FIRST; + cfg.enIntSrc = priv->txint_src; + cfg.pfnCallback = &hc32_tx_irq_cb; + hc32_enable_irq(&cfg, DDL_IRQ_PRIORITY_DEFAULT); + } -static void up_set_apb_clock(struct uart_dev_s *dev, bool on) -{ + { + memset(&cfg, 0, sizeof(cfg)); + cfg.enIRQn = priv->txc_irq - HC32_IRQ_FIRST; + cfg.enIntSrc = priv->txcint_src; + cfg.pfnCallback = &hc32_txc_irq_cb; + hc32_enable_irq(&cfg, DDL_IRQ_PRIORITY_DEFAULT); + } + { + memset(&cfg, 0, sizeof(cfg)); + cfg.enIRQn = priv->err_irq - HC32_IRQ_FIRST; + cfg.enIntSrc = priv->errint_src; + cfg.pfnCallback = &hc32_err_irq_cb; + hc32_enable_irq(&cfg, DDL_IRQ_PRIORITY_DEFAULT); + } + + return OK; } /**************************************************************************** @@ -954,111 +967,13 @@ static void up_set_apb_clock(struct uart_dev_s *dev, bool on) * first time that the serial port is opened. * ****************************************************************************/ - static int up_setup(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - M4_USART_TypeDef *base = (M4_USART_TypeDef *)priv->usartbase; - - hc32_print("%s irq %d\n", __func__, priv->irq); - -#ifndef CONFIG_SUPPRESS_UART_CONFIG - uint32_t regval; - - /* Note: The logic here depends on the fact that that the USART module - * was enabled in hc32_lowsetup(). - */ - - /* Enable USART APB1/2 clock */ - - up_set_apb_clock(dev, true); - - /* Configure pins for USART use */ - - hc32_configgpio(priv->tx_gpio); - hc32_configgpio(priv->rx_gpio); - -#ifdef CONFIG_SERIAL_OFLOWCONTROL - if (priv->cts_gpio != 0) - { - hc32_configgpio(priv->cts_gpio); - } -#endif - -#ifdef CONFIG_SERIAL_IFLOWCONTROL - if (priv->rts_gpio != 0) - { - uint32_t config = priv->rts_gpio; - -#ifdef CONFIG_HC32_FLOWCONTROL_BROKEN - /* Instead of letting hw manage this pin, we will bitbang */ - - config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; -#endif - hc32_configgpio(config); - } -#endif - -#ifdef HAVE_RS485 - if (priv->rs485_dir_gpio != 0) - { - hc32_configgpio(priv->rs485_dir_gpio); - hc32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); - } -#endif - - /* Configure CR2 - * Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits - */ - - regval = up_serialin(priv, base->_CR2); - - regval &= ~(USART_CR2_STOP | USART_CR2_CLKC | USART_CR2_WKUPE | - USART_CR2_SBKL | USART_CR2_LBDL | USART_CR2_LBDIE); - - /* Configure STOP bits */ - - if (priv->stopbits2) - { - regval |= USART_CR2_STOP; - } - - up_serialout(priv, base->_CR2, regval); - - /* Configure CR1 - * Clear TE, REm and all interrupt enable bits - */ - - regval = up_serialin(priv, base->_CR1); - regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_USED_INTS); - - up_serialout(priv, base->_CR1, regval); - - /* Configure CR3 - * Clear CTSE, RTSE, and all interrupt enable bits - */ - - regval = up_serialin(priv, base->_CR3); - regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); - - up_serialout(priv, base->_CR3, regval); - - /* Configure the USART line format and speed. */ - - up_set_format(dev); - - /* Enable Rx, Tx, and the USART */ - - regval = up_serialin(priv, base->_CR1); - regval |= (USART_CR1_TE | USART_CR1_RE | USART_CR1_USED_INTS); - - up_serialout(priv, base->_CR1, regval); - -#endif /* CONFIG_SUPPRESS_UART_CONFIG */ /* Set up the cached interrupt enables value */ - priv->ie = 0; + priv->ie = 0; /* Mark device as initialized. */ @@ -1079,11 +994,8 @@ static int up_setup(struct uart_dev_s *dev) static void up_shutdown(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - M4_USART_TypeDef *base = (M4_USART_TypeDef *)priv->usartbase; uint32_t regval; - hc32_print("check %s line %d\n", __func__, __LINE__); - /* Mark device as uninitialized. */ priv->initialized = false; @@ -1092,15 +1004,11 @@ static void up_shutdown(struct uart_dev_s *dev) up_disableusartint(priv, NULL); - /* Disable USART APB1/2 clock */ - - up_set_apb_clock(dev, false); - /* Disable Rx, Tx, and the UART */ - regval = up_serialin(priv, base->_CR1); + regval = up_serialin(priv, offsetof(M4_USART_TypeDef, _CR1)); regval &= ~( USART_CR1_TE | USART_CR1_RE); - up_serialout(priv, base->_CR1, regval); + up_serialout(priv, offsetof(M4_USART_TypeDef, _CR1), regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1154,20 +1062,12 @@ static void up_shutdown(struct uart_dev_s *dev) static int up_attach(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - int ret; + int ret = 0; - /* Attach and enable the IRQ */ - - ret = irq_attach(priv->irq, up_interrupt, priv); - if (ret == OK) - { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the USART - */ - - up_enable_irq(priv->irq); - } + hc32_print("%s: attach irq rx %d %d tx %d %d\n", __func__, priv->rx_irq, priv->rxint_src, + priv->tx_irq, priv->txint_src); + ret = hc32_enable_serialirq(dev); return ret; } @@ -1205,20 +1105,11 @@ static void up_detach(struct uart_dev_s *dev) static int up_interrupt(int irq, void *context, void *arg) { struct up_dev_s *priv = (struct up_dev_s *)arg; - M4_USART_TypeDef *base = (M4_USART_TypeDef *)priv->usartbase; int passes; bool handled; - hc32_print("check %s irq %d come\n", __func__, irq); - DEBUGASSERT(priv != NULL); - /* Report serial activity to the power management logic */ - -#if defined(CONFIG_PM) && CONFIG_HC32_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_HC32_PM_SERIAL_ACTIVITY); -#endif - /* Loop until there are no characters to be transferred or, * until we have been looping for a long time. */ @@ -1230,7 +1121,7 @@ static int up_interrupt(int irq, void *context, void *arg) /* Get the masked USART status word. */ - priv->sr = up_serialin(priv, base->SR); + priv->sr = up_serialin(priv, offsetof(M4_USART_TypeDef, SR)); /* USART interrupts: * @@ -1279,7 +1170,6 @@ static int up_interrupt(int irq, void *context, void *arg) * for RXNEIE: We cannot call uart_recvchards of RX interrupts are * disabled. */ - uart_recvchars(&priv->dev); handled = true; } @@ -1290,15 +1180,7 @@ static int up_interrupt(int irq, void *context, void *arg) else if ((priv->sr & (USART_SR_ORE | USART_SR_RXNE | USART_SR_FE)) != 0) { -#if defined(CONFIG_HC32_HC32F30XX) || defined(CONFIG_HC32_HC32F33XX) || \ - defined(CONFIG_HC32_HC32F37XX) || defined(CONFIG_HC32_HC32G4XXX) - /* These errors are cleared by writing the corresponding bit to the - * interrupt clear register (ICR). - */ - up_serialout(priv, HC32_UART_ICR_OFFSET, - (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); -#else /* If an error occurs, read from DR to clear the error (data has * been lost). If ORE is set along with RXNE then it tells you * that the byte *after* the one in the data register has been @@ -1307,8 +1189,7 @@ static int up_interrupt(int irq, void *context, void *arg) * good byte will be lost. */ - up_serialin(priv, base->DR); //RDR -#endif + up_serialin(priv, offsetof(M4_USART_TypeDef, DR)); //RDR } /* Handle outgoing, transmit bytes */ @@ -1321,6 +1202,7 @@ static int up_interrupt(int irq, void *context, void *arg) uart_xmitchars(&priv->dev); handled = true; } + } return OK; @@ -1343,12 +1225,9 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) #endif #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_HC32_SERIALBRK_BSDCOMPAT) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - M4_USART_TypeDef *base = (M4_USART_TypeDef *)priv->usartbase; #endif int ret = OK; - hc32_print("check %s line %d\n", __func__, __LINE__); - switch (cmd) { #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT @@ -1374,7 +1253,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) * half-duplex mode. */ - uint32_t cr = up_serialin(priv, base->_CR3); + uint32_t cr = up_serialin(priv, offsetof(M4_USART_TypeDef, _CR3)); #if defined(CONFIG_HC32_HC32F10XX) if ((arg & SER_SINGLEWIRE_ENABLED) != 0) @@ -1509,9 +1388,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) /* Effect the changes immediately - note that we do not implement * TCSADRAIN / TCSAFLUSH */ - - up_set_format(dev); - } + } break; #endif /* CONFIG_SERIAL_TERMIOS */ @@ -1566,8 +1443,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) irqstate_t flags; flags = enter_critical_section(); - cr1 = up_serialin(priv, base->_CR1); - up_serialout(priv, base->_CR1, cr1 | USART_CR1_SBK); + cr1 = up_serialin(priv, offsetof(M4_USART_TypeDef, _CR1)); + up_serialout(priv, offsetof(M4_USART_TypeDef, _CR1), cr1 | USART_CR1_SBK); leave_critical_section(flags); } break; @@ -1578,8 +1455,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) irqstate_t flags; flags = enter_critical_section(); - cr1 = up_serialin(priv, base->_CR1); - up_serialout(priv, base->_CR1, cr1 & ~USART_CR1_SBK); + cr1 = up_serialin(priv, offsetof(M4_USART_TypeDef, _CR1)); + up_serialout(priv, offsetof(M4_USART_TypeDef, _CR1), cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } break; @@ -1606,10 +1483,19 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) static int up_receive(struct uart_dev_s *dev, unsigned int *status) { + int val; struct up_dev_s *priv = (struct up_dev_s *)dev->priv; M4_USART_TypeDef *base = (M4_USART_TypeDef *)priv->usartbase; - return USART_RecData(base); + val = USART_RecData(base); + + if (status) + { + *status = priv->sr; + priv->sr = 0; + } + + return val; } /**************************************************************************** @@ -1649,24 +1535,33 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) * (or an Rx timeout occurs). */ -#ifndef CONFIG_SUPPRESS_SERIAL_INTS -#ifdef CONFIG_USART_ERRINTS - ie |= (USART_CR1_RIE | USART_CR1_PCE); -#else ie |= USART_CR1_RIE; -#endif -#endif + + up_enable_irq(priv->irq); + + /* Enable TX && RX && RX interrupt function */ + USART_FuncCmd((M4_USART_TypeDef *)priv->usartbase, + (USART_RX | USART_INT_RX | USART_TX | \ + USART_RTO | USART_INT_RTO), Enable); + } else { -// ie &= ~(USART_CR1_RIE | USART_CR1_PCE ); - ie &= ~(USART_CR1_RIE); + ie &= ~(USART_CR1_RIE); + up_disable_irq(priv->irq); + + USART_FuncCmd((M4_USART_TypeDef *)priv->usartbase, + (USART_RX | USART_INT_RX | USART_TX | \ + USART_RTO | USART_INT_RTO), Disable); } /* Then set the new interrupt state */ up_restoreusartint(priv, ie); leave_critical_section(flags); + + hc32_print("%s: opened %d irq %d %s ie %x\n", __func__, dev->open_count, priv->irq, + enable ? "enable" : "disable", ie); } /**************************************************************************** @@ -1676,17 +1571,12 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) * Return true if the receive register is not empty * ****************************************************************************/ - -//#if defined(SERIAL_HAVE_TXDMA_OPS) || defined(SERIAL_HAVE_NODMA_OPS) static bool up_rxavailable(struct uart_dev_s *dev) { - hc32_print("check %s line %d\n", __func__, __LINE__); - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; M4_USART_TypeDef *base = (M4_USART_TypeDef *)priv->usartbase; - return ((up_serialin(priv, base->SR) & USART_SR_RXNE) != 0); + return (Set == USART_GetStatus(base, USART_FLAG_RXNE)); } -//#endif /**************************************************************************** * Name: up_rxflowcontrol @@ -1796,8 +1686,9 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev, static void up_send(struct uart_dev_s *dev, int ch) { - while(Set != USART_GetStatus(USART_UNIT, USART_FLAG_TXE)); - USART_SendData(USART_UNIT, (uint16_t)(ch)); + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + while(Set != USART_GetStatus((const M4_USART_TypeDef *)priv->usartbase, USART_FLAG_TXE)); + USART_SendData((M4_USART_TypeDef *)priv->usartbase, (uint16_t)(ch)); } /**************************************************************************** @@ -1827,37 +1718,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) { /* Set to receive an interrupt when the TX data register is empty */ -#ifndef CONFIG_SUPPRESS_SERIAL_INTS - uint16_t ie = priv->ie | USART_CR1_TXEIE; - - /* If RS-485 is supported on this U[S]ART, then also enable the - * transmission complete interrupt. - */ - -# ifdef HAVE_RS485 - if (priv->rs485_dir_gpio != 0) - { - ie |= USART_CR1_TCIE; - } -# endif - -# ifdef CONFIG_HC32_SERIALBRK_BSDCOMPAT - if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) - { - leave_critical_section(flags); - return; - } -# endif - - up_restoreusartint(priv, ie); - -#else - /* Fake a TX interrupt here by just calling uart_xmitchars() with - * interrupts disabled (note this may recurse). - */ - uart_xmitchars(dev); -#endif } else { @@ -1881,113 +1742,11 @@ static bool up_txready(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; M4_USART_TypeDef *base = (M4_USART_TypeDef *)priv->usartbase; - return ((up_serialin(priv, base->SR) & USART_SR_TXE) != 0); + + return((Set == USART_GetStatus(base, USART_FLAG_TXE)) + || (Set == USART_GetStatus(base, USART_FLAG_TC))); } -/**************************************************************************** - * Name: up_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - * Input Parameters: - * - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state data at - * the end of the structure. - * - * pmstate - Identifies the new PM state - * - * Returned Value: - * None - The driver already agreed to transition to the low power - * consumption state when when it returned OK to the prepare() call. - * - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void up_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case(PM_NORMAL): - { - /* Logic for PM_NORMAL goes here */ - } - break; - - case(PM_IDLE): - { - /* Logic for PM_IDLE goes here */ - } - break; - - case(PM_STANDBY): - { - /* Logic for PM_STANDBY goes here */ - } - break; - - case(PM_SLEEP): - { - /* Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: up_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - * Input Parameters: - * - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state data at - * the end of the structure. - * - * pmstate - Identifies the new PM state - * - * Returned Value: - * Zero - (OK) means the event was successfully processed and that the - * driver is prepared for the PM state change. - * - * Non-zero - means that the driver is not prepared to perform the tasks - * needed achieve this power setting and will cause the state - * change to be aborted. NOTE: The prepare() method will also - * be called when reverting from lower back to higher power - * consumption modes (say because another driver refused a - * lower power state change). Drivers are not permitted to - * return non-zero values when reverting back to higher power - * consumption modes! - * - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int up_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* Logic to prepare for a reduced power state goes here. */ - - return OK; -} -#endif #endif /* HAVE_SERIALDRIVER */ #endif /* USE_SERIALDRIVER */ @@ -2075,9 +1834,7 @@ void arm_serialinit(void) char devname[16]; unsigned i; unsigned minor = 0; -#ifdef CONFIG_PM int ret; -#endif /* Register to receive power management callbacks */ @@ -2090,15 +1847,17 @@ void arm_serialinit(void) /* Register the console */ #if CONSOLE_UART > 0 - uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); + ret = uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); #ifndef CONFIG_HC32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ - uart_register("/dev/ttyS0", &g_uart_devs[CONSOLE_UART - 1]->dev); + ret = uart_register("/dev/ttyS0", &g_uart_devs[CONSOLE_UART - 1]->dev); minor = 1; + + hc32_print("register /dev/ttyS0 %d = %d\n", CONSOLE_UART - 1, ret); #endif #endif /* CONSOLE_UART > 0 */ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_spi.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_spi.c new file mode 100755 index 000000000..11ba985cb --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_spi.c @@ -0,0 +1,189 @@ +/** + ******************************************************************************* + * @file arch/arm/src/hc32/hc32_spi.c + * @brief SPI write read flash API for the Device Driver Library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wangmin First version + 2020-10-13 Wangmin Modify spelling mistake + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ddl.h" +#include "hc32_spi.h" + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief MCU Peripheral registers write unprotected. + * @param None + * @retval None + * @note Comment/uncomment each API depending on APP requires. + */ +static void Peripheral_WE(void) +{ + /* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */ + GPIO_Unlock(); + /* Unlock PWC register: FCG0 */ + PWC_FCG0_Unlock(); + /* Unlock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_Unlock(PWC_UNLOCK_CODE_0 | PWC_UNLOCK_CODE_1 | PWC_UNLOCK_CODE_2); + /* Unlock SRAM register: WTCR */ + SRAM_WTCR_Unlock(); + /* Unlock SRAM register: CKCR */ + //SRAM_CKCR_Unlock(); + /* Unlock all EFM registers */ + EFM_Unlock(); + /* Unlock EFM register: FWMC */ + //EFM_FWMC_Unlock(); + /* Unlock EFM OTP write protect registers */ + //EFM_OTP_WP_Unlock(); + /* Unlock all MPU registers */ + // MPU_Unlock(); +} + +/** + * @brief MCU Peripheral registers write protected. + * @param None + * @retval None + * @note Comment/uncomment each API depending on APP requires. + */ +static __attribute__((unused)) void Peripheral_WP(void) +{ + /* Lock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */ + GPIO_Lock(); + /* Lock PWC register: FCG0 */ + PWC_FCG0_Lock(); + /* Lock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_Lock(PWC_UNLOCK_CODE_0 | PWC_UNLOCK_CODE_1 | PWC_UNLOCK_CODE_2); + /* Lock SRAM register: WTCR */ + SRAM_WTCR_Lock(); + /* Lock SRAM register: CKCR */ + //SRAM_CKCR_Lock(); + /* Lock EFM OTP write protect registers */ + //EFM_OTP_WP_Lock(); + /* Lock EFM register: FWMC */ + //EFM_FWMC_Lock(); + /* Lock all EFM registers */ + EFM_Lock(); + /* Lock all MPU registers */ + // MPU_Lock(); +} + +/** + * @brief Configure SPI peripheral function + * + * @param [in] None + * + * @retval None + */ +static void Spi_Config(void) +{ + stc_spi_init_t stcSpiInit; + stc_spi_delay_t stcSpiDelayCfg; + + /* Clear initialize structure */ + (void)SPI_StructInit(&stcSpiInit); + (void)SPI_DelayStructInit(&stcSpiDelayCfg); + + /* Configure peripheral clock */ + PWC_Fcg1PeriphClockCmd(SPI_UNIT_CLOCK, Enable); + + /* SPI De-initialize */ + SPI_DeInit(SPI_UNIT); + + /* Configuration SPI structure */ + stcSpiInit.u32WireMode = SPI_WIRE_3; + stcSpiInit.u32TransMode = SPI_FULL_DUPLEX; + stcSpiInit.u32MasterSlave = SPI_MASTER; + stcSpiInit.u32SuspMode = SPI_COM_SUSP_FUNC_OFF; + stcSpiInit.u32Modfe = SPI_MODFE_DISABLE; + stcSpiInit.u32Parity = SPI_PARITY_INVALID; + stcSpiInit.u32SpiMode = SPI_MODE_0; + stcSpiInit.u32BaudRatePrescaler = SPI_BR_PCLK1_DIV256; + stcSpiInit.u32DataBits = SPI_DATA_SIZE_8BIT; + stcSpiInit.u32FirstBit = SPI_FIRST_MSB; + (void)SPI_Init(SPI_UNIT, &stcSpiInit); + + stcSpiDelayCfg.u32IntervalDelay = SPI_INTERVAL_TIME_8SCK_2PCLK1; + stcSpiDelayCfg.u32ReleaseDelay = SPI_RELEASE_TIME_8SCK; + stcSpiDelayCfg.u32SetupDelay = SPI_SETUP_TIME_1SCK; + (void)SPI_DelayTimeCfg(SPI_UNIT, &stcSpiDelayCfg); + + SPI_FunctionCmd(SPI_UNIT, Enable); +} + + +int hc32_spi_init(void) +{ + stc_gpio_init_t stcGpioCfg; + + Peripheral_WE(); + + /* Port configurate */ + (void)GPIO_StructInit(&stcGpioCfg); + + /* High driving capacity for output pin. */ + stcGpioCfg.u16PinDir = PIN_DIR_OUT; + stcGpioCfg.u16PinDrv = PIN_DRV_HIGH; + stcGpioCfg.u16PinState = PIN_STATE_SET; + (void)GPIO_Init(SPI_NSS_PORT, SPI_NSS_PIN, &stcGpioCfg); + + (void)GPIO_StructInit(&stcGpioCfg); + stcGpioCfg.u16PinDrv = PIN_DRV_HIGH; + (void)GPIO_Init(SPI_SCK_PORT, SPI_SCK_PIN, &stcGpioCfg); + (void)GPIO_Init(SPI_MOSI_PORT, SPI_MOSI_PIN, &stcGpioCfg); + + /* CMOS input for input pin */ + stcGpioCfg.u16PinDrv = PIN_DRV_LOW; + stcGpioCfg.u16PinIType = PIN_ITYPE_CMOS; + (void)GPIO_Init(SPI_MISO_PORT, SPI_MISO_PIN, &stcGpioCfg); + + /* Configure SPI Port function for master */ + GPIO_SetFunc(SPI_SCK_PORT, SPI_SCK_PIN, SPI_SCK_FUNC, PIN_SUBFUNC_DISABLE); + GPIO_SetFunc(SPI_MOSI_PORT, SPI_MOSI_PIN, SPI_MOSI_FUNC, PIN_SUBFUNC_DISABLE); + GPIO_SetFunc(SPI_MISO_PORT, SPI_MISO_PIN, SPI_MISO_FUNC, PIN_SUBFUNC_DISABLE); + + /* Configure SPI for SPI flash */ + Spi_Config(); + + Peripheral_WP(); + return OK; +} + diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_spi.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_spi.h new file mode 100755 index 000000000..d9a26f4df --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_spi.h @@ -0,0 +1,77 @@ +/** + ******************************************************************************* + * @file arch/arm/src/hc32/hc32_spi.h + * @brief SPI write read flash API for the Device Driver Library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wangmin First version + 2020-10-13 Wangmin Modify spelling mistake + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ddl.h" + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/* SPI unit and clock definition */ +#define SPI_UNIT (M4_SPI1) +#define SPI_UNIT_CLOCK (PWC_FCG1_SPI1) + +/* SPI port definition for master */ +#define SPI_NSS_PORT (GPIO_PORT_C) +#define SPI_NSS_PIN (GPIO_PIN_07) + +#define SPI_SCK_PORT (GPIO_PORT_C) +#define SPI_SCK_PIN (GPIO_PIN_06) +#define SPI_SCK_FUNC (GPIO_FUNC_40_SPI1_SCK) + +#define SPI_MOSI_PORT (GPIO_PORT_D) +#define SPI_MOSI_PIN (GPIO_PIN_08) +#define SPI_MOSI_FUNC (GPIO_FUNC_41_SPI1_MOSI) + +#define SPI_MISO_PORT (GPIO_PORT_D) +#define SPI_MISO_PIN (GPIO_PIN_09) +#define SPI_MISO_FUNC (GPIO_FUNC_42_SPI1_MISO) + +/* NSS pin control */ +#define SPI_NSS_HIGH() (GPIO_SetPins(SPI_NSS_PORT, SPI_NSS_PIN)) +#define SPI_NSS_LOW() (GPIO_ResetPins(SPI_NSS_PORT, SPI_NSS_PIN)) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +int hc32_spi_init(void); +void hc32_spiflash_test(void); + diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_spiflash.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_spiflash.c new file mode 100755 index 000000000..503ce4603 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_spiflash.c @@ -0,0 +1,350 @@ +/** + ******************************************************************************* + * @file arch/arm/src/hc32/hc32_spiflash.c + * @brief SPI write read flash API for the Device Driver Library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wangmin First version + 2020-10-13 Wangmin Modify spelling mistake + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ddl.h" +#include "hc32_spi.h" +#include "hc32_uart.h" + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/* FLASH parameters */ +#define FLASH_PAGE_SIZE (0x100U) +#define FLASH_SECTOR_SIZE (0x1000U) +#define FLASH_MAX_ADDR (0x800000UL) +#define FLASH_DUMMY_BYTE_VALUE (0xffU) +#define FLASH_BUSY_BIT_MASK (0x01U) + +/* FLASH instruction */ +#define FLASH_INSTR_WRITE_ENABLE (0x06U) +#define FLASH_INSTR_PAGE_PROGRAM (0x02U) +#define FLASH_INSTR_STANDARD_READ (0x03U) +#define FLASH_INSTR_ERASE_4KB_SECTOR (0x20U) +#define FLASH_INSTR_READ_SR1 (0x05U) +#define FLASH_READ_MANUFACTURER_ID (0x90U) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @brief SPI flash write byte function + * + * @param [in] u8Data SPI write data to flash + * + * @retval uint8_t SPI receive data from flash + */ +static uint8_t SpiFlash_WriteReadByte(uint8_t u8Data) +{ + uint8_t u8Byte; + + /* Wait tx buffer empty */ + while (Reset == SPI_GetStatus(SPI_UNIT, SPI_FLAG_TX_BUFFER_EMPTY)) + { + } + /* Send data */ + SPI_WriteDataReg(SPI_UNIT, (uint32_t)u8Data); + + /* Wait rx buffer full */ + while (Reset == SPI_GetStatus(SPI_UNIT, SPI_FLAG_RX_BUFFER_FULL)) + { + } + /* Receive data */ + u8Byte = (uint8_t)SPI_ReadDataReg(SPI_UNIT); + + return u8Byte; +} + +/** + * @brief SPI flash write enable function + * + * @param [in] None + * + * @retval None + */ +static void SpiFlash_WriteEnable(void) +{ + SPI_NSS_LOW(); + (void)SpiFlash_WriteReadByte(FLASH_INSTR_WRITE_ENABLE); + SPI_NSS_HIGH(); +} + +/** + * @brief SPI flash wait for write operation end function + * + * @param [in] None + * + * @retval Ok Flash internal operation finish + * @retval ErrorTimeout Flash internal operation timeout + */ +static en_result_t SpiFlash_WaitForWriteEnd(void) +{ + en_result_t enRet = Ok; + uint8_t u8Status; + uint32_t u32Timeout; + stc_clk_freq_t stcClkFreq; + + (void)CLK_GetClockFreq(&stcClkFreq); + u32Timeout = stcClkFreq.sysclkFreq / 1000U; + SPI_NSS_LOW(); + (void)SpiFlash_WriteReadByte(FLASH_INSTR_READ_SR1); + do + { + u8Status = SpiFlash_WriteReadByte(FLASH_DUMMY_BYTE_VALUE); + u32Timeout--; + } while ((u32Timeout != 0UL) && + ((u8Status & FLASH_BUSY_BIT_MASK) == FLASH_BUSY_BIT_MASK)); + + if (FLASH_BUSY_BIT_MASK == u8Status) + { + enRet = ErrorTimeout; + } + SPI_NSS_HIGH(); + + return enRet; +} + +/** + * @brief SPI flash page write program function + * + * @param [in] u32Addr Valid flash address + * @param [in] pData Pointer to send data buffer + * @param [in] len Send data length + * + * @retval Error Page write program failed + * @retval Ok Page write program success + */ +static en_result_t SpiFlash_WritePage(uint32_t u32Addr, const uint8_t pData[], uint16_t len) +{ + en_result_t enRet; + uint16_t u16Index = 0U; + + if ((u32Addr > FLASH_MAX_ADDR) || (NULL == pData) || (len > FLASH_PAGE_SIZE)) + { + enRet = Error; + } + else + { + SpiFlash_WriteEnable(); + /* Send data to flash */ + SPI_NSS_LOW(); + (void)SpiFlash_WriteReadByte(FLASH_INSTR_PAGE_PROGRAM); + (void)SpiFlash_WriteReadByte((uint8_t)((u32Addr & 0xFF0000UL) >> 16U)); + (void)SpiFlash_WriteReadByte((uint8_t)((u32Addr & 0xFF00U) >> 8U)); + (void)SpiFlash_WriteReadByte((uint8_t)(u32Addr & 0xFFU)); + while (0U != (len--)) + { + (void)SpiFlash_WriteReadByte(pData[u16Index]); + u16Index++; + } + SPI_NSS_HIGH(); + /* Wait for flash idle */ + enRet = SpiFlash_WaitForWriteEnd(); + } + + return enRet; +} + +/** + * @brief SPI flash read data function + * + * @param [in] u32Addr Valid flash address + * @param [out] pData Pointer to receive data buffer + * + * @param [in] len Read data length + * + * @retval Error Read data program failed + * @retval Ok Read data program success + */ +static en_result_t SpiFlash_ReadData(uint32_t u32Addr, uint8_t pData[], uint16_t len) +{ + en_result_t enRet = Ok; + uint16_t u16Index = 0U; + + if ((u32Addr > FLASH_MAX_ADDR) || (NULL == pData)) + { + enRet = Error; + } + else + { + SpiFlash_WriteEnable(); + /* Send data to flash */ + SPI_NSS_LOW(); + (void)SpiFlash_WriteReadByte(FLASH_INSTR_STANDARD_READ); + (void)SpiFlash_WriteReadByte((uint8_t)((u32Addr & 0xFF0000UL) >> 16U)); + (void)SpiFlash_WriteReadByte((uint8_t)((u32Addr & 0xFF00U) >> 8U)); + (void)SpiFlash_WriteReadByte((uint8_t)(u32Addr & 0xFFU)); + while (0U != (len--)) + { + pData[u16Index] = SpiFlash_WriteReadByte(FLASH_DUMMY_BYTE_VALUE); + u16Index++; + } + SPI_NSS_HIGH(); + } + + return enRet; +} + +/** + * @brief SPI flash read ID for test + * + * @param [in] None + * + * @retval uint8_t Flash ID + */ +static uint8_t SpiFlash_ReadID(void) +{ + uint8_t u8IdRead; + SPI_NSS_LOW(); + (void)SpiFlash_WriteReadByte(FLASH_READ_MANUFACTURER_ID); + (void)SpiFlash_WriteReadByte((uint8_t)0x00U); + (void)SpiFlash_WriteReadByte((uint8_t)0x00U); + (void)SpiFlash_WriteReadByte((uint8_t)0x00U); + u8IdRead = SpiFlash_WriteReadByte(FLASH_DUMMY_BYTE_VALUE); + SPI_NSS_HIGH(); + return u8IdRead; +} + +/** + * @brief SPI flash erase 4Kb sector function + * + * @param [in] u32Addr Valid flash address + * + * @retval Error Sector erase failed + * @retval Ok Sector erase success + */ +static en_result_t SpiFlash_Erase4KbSector(uint32_t u32Addr) +{ + en_result_t enRet; + + if (u32Addr >= FLASH_MAX_ADDR) + { + enRet = Error; + } + else + { + SpiFlash_WriteEnable(); + /* Send instruction to flash */ + SPI_NSS_LOW(); + (void)SpiFlash_WriteReadByte(FLASH_INSTR_ERASE_4KB_SECTOR); + (void)SpiFlash_WriteReadByte((uint8_t)((u32Addr & 0xFF0000UL) >> 16U)); + (void)SpiFlash_WriteReadByte((uint8_t)((u32Addr & 0xFF00U) >> 8U)); + (void)SpiFlash_WriteReadByte((uint8_t)(u32Addr & 0xFFU)); + //SPI_GetStatus(const M4_SPI_TypeDef *SPIx, uint32_t u32Flag) //todo + SPI_NSS_HIGH(); + /* Wait for flash idle */ + enRet = SpiFlash_WaitForWriteEnd(); + } + + return enRet; +} + + +/** + * @brief Main function of spi_master_base project + * @param None + * @retval int32_t return value, if needed + */ + +void hc32_spiflash_test(void) +{ + uint32_t flashAddr = 0UL; + uint16_t bufferLen; + char txBuffer[] = "SPI read and write flash example: Welcome to use HDSC micro chip"; + char rxBuffer[128]; + uint8_t flash_id = 0; + + hc32_spi_init(); + + /* Get tx buffer length */ + bufferLen = (uint16_t)sizeof(txBuffer); + + flash_id = SpiFlash_ReadID(); + hc32_print("SPI Flash id: %#x\n", flash_id); + + (void)memset(rxBuffer, 0L, sizeof(rxBuffer)); + /* Erase sector */ + (void)SpiFlash_Erase4KbSector(flashAddr); + /* Write data to flash */ + (void)SpiFlash_WritePage(flashAddr, (uint8_t*)&txBuffer[0], bufferLen); + /* Read data from flash */ + (void)SpiFlash_ReadData(flashAddr, (uint8_t*)&rxBuffer[0], bufferLen); + + /* Compare txBuffer and rxBuffer */ + if (memcmp(txBuffer, rxBuffer, (uint32_t)bufferLen) != 0) + { + hc32_print("spi failed!!!\n"); + } + else + { + hc32_print("spi ok!!!\n"); + } + + /* Flash address offset */ + flashAddr += FLASH_SECTOR_SIZE; + if (flashAddr >= FLASH_MAX_ADDR) + { + flashAddr = 0U; + } +} + +int hc32_spidev_initialized = 1; + +void hc32_spidev_initialize(void) +{ + hc32_spi_init(); + hc32_spidev_initialized = 0; +} + + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_uart.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_uart.h index 29d8162b2..8718f437e 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_uart.h +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_uart.h @@ -27,7 +27,6 @@ #include #include - #include "chip.h" #define CONSOLE_UART 6 @@ -43,9 +42,35 @@ * Pre-processor Definitions ****************************************************************************/ -/* Make sure that we have not enabled more U[S]ARTs than are supported by the - * device. +typedef enum en_uart_state +{ + UART_STATE_IDLE = 0U, /*!< No data */ + UART_STATE_RXEND = 1U, /*!< UART RX End */ +} uart_state_t; + +/** + * @brief Ring buffer structure definition */ +typedef struct +{ + uint16_t u16Capacity; + volatile uint16_t u16UsedSize; + uint16_t u16InIdx; + uint16_t u16OutIdx; + uint8_t au8Buf[50]; +} uart_ring_buffer_t; + + +/* UART multiple processor ID definition */ +#define UART_MASTER_STATION_ID (0x20U) +#define UART_SLAVE_STATION_ID (0x21U) + +/* Ring buffer size */ +#define IS_RING_BUFFER_EMPTY(x) (0U == ((x)->u16UsedSize)) + +/* Multi-processor silence mode */ +#define DBG_UART_NORMAL_MODE (0U) +#define DBG_UART_SILENCE_MODE (1U) /**************************************************************************** * Public Types @@ -80,7 +105,9 @@ extern "C" FAR uart_dev_t *hc32_serial_get_uart(int uart_num); -void hc32_print(const char *fmt, ...); +int hc32_print(const char *fmt, ...); + +void hc32_console_handle(char *buf); #undef EXTERN #if defined(__cplusplus) diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_vectors.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_vectors.c new file mode 100755 index 000000000..d0c264e17 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_vectors.c @@ -0,0 +1,266 @@ +/**************************************************************************** + * arch/arm/src/armv7-m/arm_vectors.c + * + * Copyright (C) 2012 Michael Smith. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "hc32f4a0_interrupts.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IDLE_STACK ((unsigned)&_ebss+CONFIG_IDLETHREAD_STACKSIZE) + +#ifndef ARMV7M_PERIPHERAL_INTERRUPTS +# error ARMV7M_PERIPHERAL_INTERRUPTS must be defined to the number of I/O interrupts to be supported +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/* Chip-specific entrypoint */ + +extern void __start(void); + +/* Common exception entrypoint */ + +extern void exception_common(void); + +/**************************************************************************** + * Public data + ****************************************************************************/ + +/* The v7m vector table consists of an array of function pointers, with the + * first slot (vector zero) used to hold the initial stack pointer. + * + * As all exceptions (interrupts) are routed via exception_common, we just + * need to fill this array with pointers to it. + * + * Note that the [ ... ] designated initializer is a GCC extension. + */ + +#if 0 +unsigned _vectors[] locate_data(".vectors") = +{ + /* Initial stack */ + + IDLE_STACK, + + /* Reset exception handler */ + + (unsigned)&__start, + + /* Vectors 2 - n point directly at the generic handler */ + + [2 ... (15 + ARMV7M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common +}; +#else +unsigned _vectors[] locate_data(".vectors") = +{ + /* Initial stack */ + + IDLE_STACK, + + /* Reset exception handler */ + + (unsigned)&__start, + (unsigned)&NMI_Handler, + (unsigned)&HardFault_Handler, + (unsigned)&MemManage_Handler, + (unsigned)&BusFault_Handler, + (unsigned)&UsageFault_Handler, + (unsigned)&exception_common, + (unsigned)&exception_common, + (unsigned)&exception_common, + (unsigned)&exception_common, + (unsigned)&SVC_Handler, /* SVC */ + (unsigned)&DebugMon_Handler, /* DebugMon */ + (unsigned)&exception_common, + (unsigned)&PendSV_Handler, + (unsigned)&SysTick_Handler, /* SysTick */ + (unsigned)&IRQ000_Handler, + (unsigned)&IRQ001_Handler, + (unsigned)&IRQ002_Handler, + (unsigned)&IRQ003_Handler, + (unsigned)&IRQ004_Handler, + (unsigned)&IRQ005_Handler, + (unsigned)&IRQ006_Handler, + (unsigned)&IRQ007_Handler, + (unsigned)&IRQ008_Handler, + (unsigned)&IRQ009_Handler, + (unsigned)&IRQ010_Handler, + (unsigned)&IRQ011_Handler, + (unsigned)&IRQ012_Handler, + (unsigned)&IRQ013_Handler, + (unsigned)&IRQ014_Handler, + (unsigned)&IRQ015_Handler, + (unsigned)&IRQ016_Handler, + (unsigned)&IRQ017_Handler, + (unsigned)&IRQ018_Handler, + (unsigned)&IRQ019_Handler, + (unsigned)&IRQ020_Handler, + (unsigned)&IRQ021_Handler, + (unsigned)&IRQ022_Handler, + (unsigned)&IRQ023_Handler, + (unsigned)&IRQ024_Handler, + (unsigned)&IRQ025_Handler, + (unsigned)&IRQ026_Handler, + (unsigned)&IRQ027_Handler, + (unsigned)&IRQ028_Handler, + (unsigned)&IRQ029_Handler, + (unsigned)&IRQ030_Handler, + (unsigned)&IRQ031_Handler, + (unsigned)&IRQ032_Handler, + (unsigned)&IRQ033_Handler, + (unsigned)&IRQ034_Handler, + (unsigned)&IRQ035_Handler, + (unsigned)&IRQ036_Handler, + (unsigned)&IRQ037_Handler, + (unsigned)&IRQ038_Handler, + (unsigned)&IRQ039_Handler, + (unsigned)&IRQ040_Handler, + (unsigned)&IRQ041_Handler, + (unsigned)&IRQ042_Handler, + (unsigned)&IRQ043_Handler, + (unsigned)&IRQ044_Handler, + (unsigned)&IRQ045_Handler, + (unsigned)&IRQ046_Handler, + (unsigned)&IRQ047_Handler, + (unsigned)&IRQ048_Handler, + (unsigned)&IRQ049_Handler, + (unsigned)&IRQ050_Handler, + (unsigned)&IRQ051_Handler, + (unsigned)&IRQ052_Handler, + (unsigned)&IRQ053_Handler, + (unsigned)&IRQ054_Handler, + (unsigned)&IRQ055_Handler, + (unsigned)&IRQ056_Handler, + (unsigned)&IRQ057_Handler, + (unsigned)&IRQ058_Handler, + (unsigned)&IRQ059_Handler, + (unsigned)&IRQ060_Handler, + (unsigned)&IRQ061_Handler, + (unsigned)&IRQ062_Handler, + (unsigned)&IRQ063_Handler, + (unsigned)&IRQ064_Handler, + (unsigned)&IRQ065_Handler, + (unsigned)&IRQ066_Handler, + (unsigned)&IRQ067_Handler, + (unsigned)&IRQ068_Handler, + (unsigned)&IRQ069_Handler, + (unsigned)&IRQ070_Handler, + (unsigned)&IRQ071_Handler, + (unsigned)&IRQ072_Handler, + (unsigned)&IRQ073_Handler, + (unsigned)&IRQ074_Handler, + (unsigned)&IRQ075_Handler, + (unsigned)&IRQ076_Handler, + (unsigned)&IRQ077_Handler, + (unsigned)&IRQ078_Handler, + (unsigned)&IRQ079_Handler, + (unsigned)&IRQ080_Handler, + (unsigned)&IRQ081_Handler, + (unsigned)&IRQ082_Handler, + (unsigned)&IRQ083_Handler, + (unsigned)&IRQ084_Handler, + (unsigned)&IRQ085_Handler, + (unsigned)&IRQ086_Handler, + (unsigned)&IRQ087_Handler, + (unsigned)&IRQ088_Handler, + (unsigned)&IRQ089_Handler, + (unsigned)&IRQ090_Handler, + (unsigned)&IRQ091_Handler, + (unsigned)&IRQ092_Handler, + (unsigned)&IRQ093_Handler, + (unsigned)&IRQ094_Handler, + (unsigned)&IRQ095_Handler, + (unsigned)&IRQ096_Handler, + (unsigned)&IRQ097_Handler, + (unsigned)&IRQ098_Handler, + (unsigned)&IRQ099_Handler, + (unsigned)&IRQ100_Handler, + (unsigned)&IRQ101_Handler, + (unsigned)&IRQ102_Handler, + (unsigned)&IRQ103_Handler, + (unsigned)&IRQ104_Handler, + (unsigned)&IRQ105_Handler, + (unsigned)&IRQ106_Handler, + (unsigned)&IRQ107_Handler, + (unsigned)&IRQ108_Handler, + (unsigned)&IRQ109_Handler, + (unsigned)&IRQ110_Handler, + (unsigned)&IRQ111_Handler, + (unsigned)&IRQ112_Handler, + (unsigned)&IRQ113_Handler, + (unsigned)&IRQ114_Handler, + (unsigned)&IRQ115_Handler, + (unsigned)&IRQ116_Handler, + (unsigned)&IRQ117_Handler, + (unsigned)&IRQ118_Handler, + (unsigned)&IRQ119_Handler, + (unsigned)&IRQ120_Handler, + (unsigned)&IRQ121_Handler, + (unsigned)&IRQ122_Handler, + (unsigned)&IRQ123_Handler, + (unsigned)&IRQ124_Handler, + (unsigned)&IRQ125_Handler, + (unsigned)&IRQ126_Handler, + (unsigned)&IRQ127_Handler, + (unsigned)&IRQ128_Handler, + (unsigned)&IRQ129_Handler, + (unsigned)&IRQ130_Handler, + (unsigned)&IRQ131_Handler, + (unsigned)&IRQ132_Handler, + (unsigned)&IRQ133_Handler, + (unsigned)&IRQ134_Handler, + (unsigned)&IRQ135_Handler, + (unsigned)&IRQ136_Handler, + (unsigned)&IRQ137_Handler, + (unsigned)&IRQ138_Handler, + (unsigned)&IRQ139_Handler, + (unsigned)&IRQ140_Handler, + (unsigned)&IRQ141_Handler, + (unsigned)&IRQ142_Handler, + (unsigned)&IRQ143_Handler + +// [2 ... (15 + ARMV7M_PERIPHERAL_INTERRUPTS)] = (unsigned)&exception_common +}; +#endif diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32f4a0_gpio.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32f4a0_gpio.h index 7dab7070e..a4a7ec06a 100755 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32f4a0_gpio.h +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32f4a0_gpio.h @@ -137,6 +137,8 @@ typedef struct #define GPIO_PORT_SHIFT 16 #define GPIO_PINSET(_port, _pin) ((uint32_t)(_port << GPIO_PORT_SHIFT) | _pin) +#define GPIO_PIN(_pinset) ((_pinset >> GPIO_PIN_SHIFT) & GPIO_PIN_MASK) +#define GPIO_PORT(_pinset) ((_pinset >> GPIO_PORT_SHIFT) & GPIO_PORT_MASK) /** * @} diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32f4a0_spi.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32f4a0_spi.c new file mode 100755 index 000000000..c75068dff --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32f4a0_spi.c @@ -0,0 +1,1095 @@ +/** + ******************************************************************************* + * @file hc32f4a0_spi.c + * @brief This file provides firmware functions to manage the Serial Peripheral + * Interface(SPI). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wangmin First version + 2020-08-31 Wangmin Modify for MISRAC2012 + 2020-10-13 Wangmin Define variable for count as __IO type + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_spi.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_SPI SPI + * @brief Serial Peripheral Interface Driver Library + * @{ + */ + +#if (DDL_SPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SPI_Local_Macros SPI Local Macros + * @{ + */ + +#define SPI_CFG1_DEFAULT (0x00000010UL) +#define SPI_CFG2_DEFAULT (0x00000F1DUL) +#define SPI_SR_DEFAULT (0x00000020UL) + +#define SPI_IRQ_MASK ( SPI_INT_ERROR | \ + SPI_INT_TX_BUFFER_EMPTY | \ + SPI_INT_RX_BUFFER_FULL | \ + SPI_INT_IDLE ) +#define SPI_GET_STD_MASK ( SPI_FLAG_OVERLOAD | \ + SPI_FLAG_IDLE | \ + SPI_FLAG_MODE_FAULT | \ + SPI_FLAG_PARITY_ERROR | \ + SPI_FLAG_UNDERLOAD | \ + SPI_FLAG_TX_BUFFER_EMPTY | \ + SPI_FLAG_RX_BUFFER_FULL ) +#define SPI_CLR_STD_MASK ( SPI_FLAG_OVERLOAD | \ + SPI_FLAG_MODE_FAULT | \ + SPI_FLAG_PARITY_ERROR | \ + SPI_FLAG_UNDERLOAD ) + +#define SPI_SS0_VALID_CFG (0UL) +#define SPI_SS1_VALID_CFG (SPI_CFG2_SSA_0) +#define SPI_SS2_VALID_CFG (SPI_CFG2_SSA_1) +#define SPI_SS3_VALID_CFG (SPI_CFG2_SSA_0 | SPI_CFG2_SSA_1) + +/** + * @defgroup SPI_Check_Parameters_Validity SPI check parameters validity + * @{ + */ + +/*! Parameter valid check for SPI peripheral */ +#define IS_VALID_SPI_UNIT(x) \ +( (M4_SPI1 == (x)) || \ + (M4_SPI2 == (x)) || \ + (M4_SPI3 == (x)) || \ + (M4_SPI4 == (x)) || \ + (M4_SPI5 == (x)) || \ + (M4_SPI6 == (x))) + +/*! Parameter valid check for SPI wire mode */ +#define IS_SPI_WIRE_MODE(x) \ +( ((x) == SPI_WIRE_4) || \ + ((x) == SPI_WIRE_3)) + +/*! Parameter valid check for SPI transfer mode */ +#define IS_SPI_TRANS_MODE(x) \ +( ((x) == SPI_FULL_DUPLEX) || \ + ((x) == SPI_SEND_ONLY)) + +/*! Parameter valid check for SPI master slave mode */ +#define IS_SPI_MASTER_SLAVE(x) \ +( ((x) == SPI_SLAVE) || \ + ((x) == SPI_MASTER)) + +/*! Parameter valid check for SPI loopback mode */ +#define IS_SPI_SPLPBK(x) \ +( ((x) == SPI_SPLPBK_INVALID) || \ + ((x) == SPI_SPLPBK_MOSI_INVERT) || \ + ((x) == SPI_SPLPBK_MOSI)) + +/*! Parameter valid check for SPI communication suspend function status */ +#define IS_SPI_SUSP_MODE_STD(x) \ +( ((x) == SPI_COM_SUSP_FUNC_OFF) || \ + ((x) == SPI_COM_SUSP_FUNC_ON)) + +/*! Parameter valid check for SPI fault dectet function status */ +#define IS_SPI_MODFE_CMD(x) \ +( ((x) == SPI_MODFE_DISABLE) || \ + ((x) == SPI_MODFE_ENABLE)) + +/*! Parameter valid check for SPI parity check mode */ +#define IS_SPI_PARITY_CHECK(x) \ +( ((x) == SPI_PARITY_INVALID) || \ + ((x) == SPI_PARITY_EVEN) || \ + ((x) == SPI_PARITY_ODD)) + +/*! Parameter valid check for SPI interval time delay */ +#define IS_SPI_INTERVAL_DELAY(x) \ +( ((x) == SPI_INTERVAL_TIME_1SCK_2PCLK1) || \ + ((x) == SPI_INTERVAL_TIME_2SCK_2PCLK1) || \ + ((x) == SPI_INTERVAL_TIME_3SCK_2PCLK1) || \ + ((x) == SPI_INTERVAL_TIME_4SCK_2PCLK1) || \ + ((x) == SPI_INTERVAL_TIME_5SCK_2PCLK1) || \ + ((x) == SPI_INTERVAL_TIME_6SCK_2PCLK1) || \ + ((x) == SPI_INTERVAL_TIME_7SCK_2PCLK1) || \ + ((x) == SPI_INTERVAL_TIME_8SCK_2PCLK1)) + +/*! Parameter valid check for SPI release time delay */ +#define IS_SPI_RELEASE_DELAY(x) \ +( ((x) == SPI_RELEASE_TIME_1SCK) || \ + ((x) == SPI_RELEASE_TIME_2SCK) || \ + ((x) == SPI_RELEASE_TIME_3SCK) || \ + ((x) == SPI_RELEASE_TIME_4SCK) || \ + ((x) == SPI_RELEASE_TIME_5SCK) || \ + ((x) == SPI_RELEASE_TIME_6SCK) || \ + ((x) == SPI_RELEASE_TIME_7SCK) || \ + ((x) == SPI_RELEASE_TIME_8SCK)) + +/*! Parameter valid check for SPI Setup time delay delay */ +#define IS_SPI_SETUP_DELAY(x) \ +( ((x) == SPI_SETUP_TIME_1SCK) || \ + ((x) == SPI_SETUP_TIME_2SCK) || \ + ((x) == SPI_SETUP_TIME_3SCK) || \ + ((x) == SPI_SETUP_TIME_4SCK) || \ + ((x) == SPI_SETUP_TIME_5SCK) || \ + ((x) == SPI_SETUP_TIME_6SCK) || \ + ((x) == SPI_SETUP_TIME_7SCK) || \ + ((x) == SPI_SETUP_TIME_8SCK)) + +/*! Parameter valid check for SPI SS active level */ +#define IS_SPI_SS_ACTIVE_LEVEL(x) \ +( ((x) == SPI_SS_ACTIVE_LOW) || \ + ((x) == SPI_SS_ACTIVE_HIGH)) + +/*! Parameter valid check for SPI read data register target buffer */ +#define IS_SPI_RD_TARGET_BUFF(x) \ +( ((x) == SPI_RD_TARGET_RD_BUF) || \ + ((x) == SPI_RD_TARGET_WR_BUF)) + +/*! Parameter valid check for SPI mode */ +#define IS_SPI_SPI_MODE(x) \ +( ((x) == SPI_MODE_0) || \ + ((x) == SPI_MODE_1) || \ + ((x) == SPI_MODE_2) || \ + ((x) == SPI_MODE_3)) + +/*! Parameter valid check for SPI SS signal */ +#define IS_SPI_SS_PIN(x) \ +( ((x) == SPI_PIN_SS0) || \ + ((x) == SPI_PIN_SS1) || \ + ((x) == SPI_PIN_SS2) || \ + ((x) == SPI_PIN_SS3)) + +/*! Parameter valid check for SPI baudrate prescaler */ +#define IS_SPI_BIT_RATE_DIV(x) \ +( ((x) == SPI_BR_PCLK1_DIV2) || \ + ((x) == SPI_BR_PCLK1_DIV4) || \ + ((x) == SPI_BR_PCLK1_DIV8) || \ + ((x) == SPI_BR_PCLK1_DIV16) || \ + ((x) == SPI_BR_PCLK1_DIV32) || \ + ((x) == SPI_BR_PCLK1_DIV64) || \ + ((x) == SPI_BR_PCLK1_DIV128) || \ + ((x) == SPI_BR_PCLK1_DIV256)) + +/*! Parameter valid check for SPI data bits */ +#define IS_SPI_DATA_SIZE(x) \ +( ((x) == SPI_DATA_SIZE_4BIT) || \ + ((x) == SPI_DATA_SIZE_5BIT) || \ + ((x) == SPI_DATA_SIZE_6BIT) || \ + ((x) == SPI_DATA_SIZE_7BIT) || \ + ((x) == SPI_DATA_SIZE_8BIT) || \ + ((x) == SPI_DATA_SIZE_9BIT) || \ + ((x) == SPI_DATA_SIZE_10BIT) || \ + ((x) == SPI_DATA_SIZE_11BIT) || \ + ((x) == SPI_DATA_SIZE_12BIT) || \ + ((x) == SPI_DATA_SIZE_13BIT) || \ + ((x) == SPI_DATA_SIZE_14BIT) || \ + ((x) == SPI_DATA_SIZE_15BIT) || \ + ((x) == SPI_DATA_SIZE_16BIT) || \ + ((x) == SPI_DATA_SIZE_20BIT) || \ + ((x) == SPI_DATA_SIZE_24BIT) || \ + ((x) == SPI_DATA_SIZE_32BIT)) + +/*! Parameter valid check for SPI data frame level */ +#define IS_SPI_DATA_FRAME(x) \ +( ((x) == SPI_FRAME_1) || \ + ((x) == SPI_FRAME_2) || \ + ((x) == SPI_FRAME_3) || \ + ((x) == SPI_FRAME_4)) + +/*! Parameter valid check for SPI LSB MSB mode */ +#define IS_SPI_FIRST_BIT(x) \ +( ((x) == SPI_FIRST_MSB) || \ + ((x) == SPI_FIRST_LSB)) + +/*! Parameter valid check for interrupt flag */ +#define IS_SPI_IRQ_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_IRQ_MASK) == SPI_IRQ_MASK)) + +/*! Parameter valid check for SPI status flag */ +#define IS_SPI_STD_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_GET_STD_MASK) == SPI_GET_STD_MASK)) + +/*! Parameter valid check for SPI status flag for clear */ +#define IS_SPI_CLR_STD_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_CLR_STD_MASK) == SPI_CLR_STD_MASK)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +/** + * @defgroup SPI_Local_Functions SPI Local Functions + * @{ + */ + +static en_result_t SPI_TxRx(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Length); +static en_result_t SPI_Tx(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32Length); + +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup SPI_Global_Functions SPI Global Functions + * @{ + */ + +/** + * @brief Initializes the SPI peripheral according to the specified parameters + * in the structure stc_spi_init. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] pstcInit Pointer to a stc_spi_init_t structure that contains + * the configuration information for the SPI. + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred + * @arg ErrorInvalidParameter: pstcInit == NULL or configuration parameter error. + */ +en_result_t SPI_Init(M4_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + if (NULL != pstcInit) + { + DDL_ASSERT(IS_SPI_WIRE_MODE(pstcInit->u32WireMode)); + DDL_ASSERT(IS_SPI_TRANS_MODE(pstcInit->u32TransMode)); + DDL_ASSERT(IS_SPI_MASTER_SLAVE(pstcInit->u32MasterSlave)); + DDL_ASSERT(IS_SPI_SUSP_MODE_STD(pstcInit->u32SuspMode)); + DDL_ASSERT(IS_SPI_MODFE_CMD(pstcInit->u32Modfe)); + DDL_ASSERT(IS_SPI_PARITY_CHECK(pstcInit->u32Parity)); + DDL_ASSERT(IS_SPI_SPI_MODE(pstcInit->u32SpiMode)); + DDL_ASSERT(IS_SPI_BIT_RATE_DIV(pstcInit->u32BaudRatePrescaler)); + DDL_ASSERT(IS_SPI_DATA_SIZE(pstcInit->u32DataBits)); + DDL_ASSERT(IS_SPI_FIRST_BIT(pstcInit->u32FirstBit)); + DDL_ASSERT(IS_SPI_DATA_FRAME(pstcInit->u32FrameLevel)); + + /* Configuration parameter check */ + if((SPI_MASTER == pstcInit->u32MasterSlave)&&(SPI_MODFE_ENABLE == pstcInit->u32Modfe)) + { + /* pstcInit->u32Modfe can not be SPI_MODFE_ENABLE in master mode */ + } + else if((SPI_WIRE_3 == pstcInit->u32WireMode) + && (SPI_SLAVE == pstcInit->u32MasterSlave) + &&((SPI_MODE_0 == pstcInit->u32SpiMode)||(SPI_MODE_2 == pstcInit->u32SpiMode))) + { + /* SPI_WIRE_3 can not support SPI_MODE_0 and SPI_MODE_2 */ + } + else + { + WRITE_REG32(SPIx->_CR1, pstcInit->u32WireMode + | pstcInit->u32TransMode + | pstcInit->u32MasterSlave + | pstcInit->u32SuspMode + | pstcInit->u32Modfe + | pstcInit->u32Parity ); + + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_FTHLV, pstcInit->u32FrameLevel); + + WRITE_REG32(SPIx->CFG2, pstcInit->u32SpiMode + | pstcInit->u32BaudRatePrescaler + | pstcInit->u32DataBits + | pstcInit->u32FirstBit); + + enRet = Ok; + } + } + return enRet; +} + +/** + * @brief De-initializes the SPI peripheral. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @retval None + */ +void SPI_DeInit(M4_SPI_TypeDef *SPIx) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + SPI_FunctionCmd(SPIx, Disable); + + WRITE_REG32(SPIx->_CR1, 0x00000000UL); + WRITE_REG32(SPIx->CFG1, SPI_CFG1_DEFAULT); + WRITE_REG32(SPIx->CFG2, SPI_CFG2_DEFAULT); + WRITE_REG32(SPIx->SR, SPI_SR_DEFAULT); +} + +/** + * @brief Set a default value for the SPI initialization structure. + * @param [in] pstcInit Pointer to a stc_spi_init_t structure that + * contains configuration information. + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorInvalidParameter: pstcInit == NULL. + */ +en_result_t SPI_StructInit(stc_spi_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcInit) + { + pstcInit->u32WireMode = SPI_WIRE_4; + pstcInit->u32TransMode = SPI_FULL_DUPLEX; + pstcInit->u32MasterSlave = SPI_MASTER; + pstcInit->u32SuspMode = SPI_COM_SUSP_FUNC_OFF; + pstcInit->u32Modfe = SPI_MODFE_DISABLE; + pstcInit->u32Parity = SPI_PARITY_INVALID; + pstcInit->u32SpiMode = SPI_MODE_0; + pstcInit->u32BaudRatePrescaler = SPI_BR_PCLK1_DIV8; + pstcInit->u32DataBits = SPI_DATA_SIZE_8BIT; + pstcInit->u32FirstBit = SPI_FIRST_MSB; + pstcInit->u32FrameLevel = SPI_FRAME_1; + + enRet = Ok; + } + return enRet; +} + +/** + * @brief Enable or disable SPI interrupt. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] u32IntType SPI interrupt type. Can be one or any + * combination of the parameter @ref SPI_Interrupt_Type_Define + * @arg SPI_INT_ERROR + * @arg SPI_INT_TX_BUFFER_EMPTY + * @arg SPI_INT_RX_BUFFER_FULL + * @arg SPI_INT_IDLE + * @param [in] enNewState An en_functional_state_t enumeration value. + * @arg Enable: Enable the specified interrupt of SPI. + * @arg Disable: Disable the specified interrupt of SPI. + * @retval None + */ +void SPI_IntCmd(M4_SPI_TypeDef *SPIx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_SPI_IRQ_FLAG(u32IntType)); + + if (enNewState == Enable) + { + SET_REG32_BIT(SPIx->_CR1, u32IntType); + } + else + { + CLEAR_REG32_BIT(SPIx->_CR1, u32IntType); + } +} + +/** + * @brief SPI function enable or disable. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] enNewState An en_functional_state_t enumeration value. + * @arg Enable: Enable SPI function. + * @arg Disable: Disable SPI function. + * @retval None + */ +void SPI_FunctionCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + SET_REG32_BIT(SPIx->_CR1, SPI_CR1_SPE); + } + else + { + CLEAR_REG32_BIT(SPIx->_CR1, SPI_CR1_SPE); + } +} + +/** + * @brief Write SPI data register. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] u32Data The data will be written to the data register. + * @retval None. + */ +void SPI_WriteDataReg(M4_SPI_TypeDef *SPIx, uint32_t u32Data) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + WRITE_REG32(SPIx->DR, u32Data); +} + +/** + * @brief Read SPI data register. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @retval A 32-bit data of SPI data register. + */ +uint32_t SPI_ReadDataReg(const M4_SPI_TypeDef *SPIx) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return READ_REG32(SPIx->DR); +} + + +/** + * @brief SPI get status flag. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] u32Flag SPI state flag. Can be one or any + * combination of the parameter of @ref SPI_State_Flag_Define + * @arg SPI_FLAG_OVERLOAD + * @arg SPI_FLAG_IDLE + * @arg SPI_FLAG_MODE_FAULT + * @arg SPI_FLAG_PARITY_ERROR + * @arg SPI_FLAG_UNDERLOAD + * @arg SPI_FLAG_TX_BUFFER_EMPTY + * @arg SPI_FLAG_RX_BUFFER_FULL + * @retval An en_flag_status_t enumeration. + * @arg Set: The specified flag has set. + * @arg Reset: The specified flag has not set. + */ +en_flag_status_t SPI_GetStatus(const M4_SPI_TypeDef *SPIx, uint32_t u32Flag) +{ + en_flag_status_t enFlag = Reset; + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_STD_FLAG(u32Flag)); + + if(0U != READ_REG32_BIT(SPIx->SR, u32Flag)) + { + enFlag = Set; + } + + return enFlag; +} + +/** + * @brief SPI clear state flag. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] u32Flag SPI state flag. + * Can be one or any combination of the parameter below + * @arg SPI_FLAG_OVERLOAD + * @arg SPI_FLAG_MODE_FAULT + * @arg SPI_FLAG_PARITY_ERROR + * @arg SPI_FLAG_UNDERLOAD + * @retval None + */ +void SPI_ClearFlag(M4_SPI_TypeDef *SPIx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_CLR_STD_FLAG(u32Flag)); + + CLEAR_REG32_BIT(SPIx->SR, u32Flag); +} + +/** + * @brief SPI loopback function configuration. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] u32Mode Loopback mode. + * Can be one parameter @ref SPI_Loopback_Selection_Define + * @arg SPI_SPLPBK_INVALID + * @arg SPI_SPLPBK_MOSI_INVERT + * @arg SPI_SPLPBK_MOSI + * @retval None + */ +void SPI_LoopbackModeCfg(M4_SPI_TypeDef *SPIx, uint32_t u32Mode) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SPLPBK(u32Mode)); + + MODIFY_REG32(SPIx->_CR1, SPI_CR1_SPLPBK | SPI_CR1_SPLPBK2, u32Mode); +} + +/** + * @brief SPI parity check error self diagnosis function enable or disable. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] enNewState An en_functional_state_t enumeration value. + * @arg Enable: Enable function. + * @arg Disable: Disable function. + * @retval None + */ +void SPI_PateCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + SET_REG32_BIT(SPIx->_CR1, SPI_CR1_PATE); + } + else + { + CLEAR_REG32_BIT(SPIx->_CR1, SPI_CR1_PATE); + } +} + +/** + * @brief SPI signals delay time configuration + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] pstcDelayCfg Pointer to a stc_spi_delay_t structure that contains + * the configuration information for the SPI delay time. + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred + * @arg ErrorInvalidParameter: pstcDelayCfg == NULL + */ +en_result_t SPI_DelayTimeCfg(M4_SPI_TypeDef *SPIx, const stc_spi_delay_t *pstcDelayCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + if (NULL != pstcDelayCfg) + { + DDL_ASSERT(IS_SPI_INTERVAL_DELAY(pstcDelayCfg->u32IntervalDelay)); + DDL_ASSERT(IS_SPI_RELEASE_DELAY(pstcDelayCfg->u32ReleaseDelay)); + DDL_ASSERT(IS_SPI_SETUP_DELAY(pstcDelayCfg->u32SetupDelay)); + + /* Interval delay */ + if(SPI_INTERVAL_TIME_1SCK_2PCLK1 == pstcDelayCfg->u32IntervalDelay) + { + CLEAR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MIDIE); + CLEAR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MIDI); + } + else + { + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MIDI, pstcDelayCfg->u32IntervalDelay); + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MIDIE); + } + + /* SCK release delay */ + if(SPI_RELEASE_TIME_1SCK == pstcDelayCfg->u32ReleaseDelay) + { + CLEAR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSDLE); + CLEAR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MSSDL); + } + else + { + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSDLE); + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MSSDL, pstcDelayCfg->u32ReleaseDelay); + } + + /* Setup delay */ + if(SPI_SETUP_TIME_1SCK == pstcDelayCfg->u32SetupDelay) + { + CLEAR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSIE); + CLEAR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MSSI); + } + else + { + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSIE); + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MSSI, pstcDelayCfg->u32SetupDelay); + } + + enRet = Ok; + } + return enRet; +} + +/** + * @brief Set a default value for the SPI delay time configuration structure. + * @param [in] pstcDelayCfg Pointer to a stc_spi_delay_t structure that + * contains configuration information. + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorInvalidParameter: pstcDelayCfg == NULL. + */ +en_result_t SPI_DelayStructInit(stc_spi_delay_t *pstcDelayCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcDelayCfg) + { + pstcDelayCfg->u32IntervalDelay = SPI_INTERVAL_TIME_1SCK_2PCLK1; + pstcDelayCfg->u32ReleaseDelay = SPI_RELEASE_TIME_1SCK; + pstcDelayCfg->u32SetupDelay = SPI_SETUP_TIME_1SCK; + enRet = Ok; + } + return enRet; +} + +/** + * @brief SPI SS signal valid level configuration + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] u32SSPin Specify the SS pin @ref SPI_SS_Pin_Define + * @param [in] enNewState An en_functional_state_t enumeration value. + * @arg Enable: SS pin high level valid. + * @arg Disable: SS pin low level valid. + * @retval None + */ +void SPI_SSValidLevelCfg(M4_SPI_TypeDef *SPIx, uint32_t u32SSPin, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SS_PIN(u32SSPin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + SET_REG32_BIT(SPIx->CFG1, u32SSPin); + } + else + { + CLEAR_REG32_BIT(SPIx->CFG1, u32SSPin); + } +} + +/** + * @brief SPI valid SS signal configuration + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] u32SSPin Specify the SS pin @ref SPI_SS_Pin_Define + * @retval None + */ +void SPI_SSPinSel(M4_SPI_TypeDef *SPIx, uint32_t u32SSPin) +{ + uint32_t u32RegCfg; + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SS_PIN(u32SSPin)); + + switch (u32SSPin) + { + case SPI_PIN_SS0: + u32RegCfg = SPI_SS0_VALID_CFG; + break; + case SPI_PIN_SS1: + u32RegCfg = SPI_SS1_VALID_CFG; + break; + case SPI_PIN_SS2: + u32RegCfg = SPI_SS2_VALID_CFG; + break; + case SPI_PIN_SS3: + u32RegCfg = SPI_SS3_VALID_CFG; + break; + + default: + u32RegCfg = SPI_SS0_VALID_CFG; + break; + } + MODIFY_REG32(SPIx->CFG2, SPI_CFG2_SSA, u32RegCfg); +} + +/** + * @brief SPI read buffer configuration + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] u32ReadBuf Target buffer for read operation @ref SPI_Read_Target_Buffer_Define + * @retval None + */ +void SPI_ReadBufCfg(M4_SPI_TypeDef *SPIx, uint32_t u32ReadBuf) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_RD_TARGET_BUFF(u32ReadBuf)); + + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_SPRDTD, u32ReadBuf); +} + +/** + * @brief SPI transmit data. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [in] u32TxLength The length of the data to be sent. + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred + * @arg ErrorTimeout: SPI transmit timeout. + * @arg ErrorInvalidParameter: pvTxBuf == NULL or u32TxLength == 0U + * @note -No SS pin active and inactive operation in 3-wire mode. Add operations of SS pin depending on your application. + * -This function supports full duplex mode and send only mode. + */ +en_result_t SPI_Transmit(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32TxLength) +{ + uint32_t u32Flags; + en_result_t enRet = ErrorInvalidParameter; + + if ((pvTxBuf != NULL) && (u32TxLength != 0U)) + { + u32Flags = READ_REG32_BIT(SPIx->_CR1, SPI_CR1_TXMDS); + if (u32Flags == SPI_SEND_ONLY) + { + /* Transmit data in send only mode. */ + enRet = SPI_Tx(SPIx, pvTxBuf, u32TxLength); + } + else + { + /* Transmit data in full duplex mode. */ + enRet = SPI_TxRx(SPIx, pvTxBuf, NULL, u32TxLength); + } + } + return enRet; +} + +/** + * @brief SPI receive data. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] pvRxBuf The pointer to the buffer which the received data to be stored. + * @param [in] u32RxLength The length of the data to be received. + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred + * @arg ErrorTimeout: SPI receive timeout. + * @arg ErrorInvalidParameter: pvRxBuf == NULL or u32RxLength == 0U + * @note -No SS pin active and inactive operation in 3-wire mode. Add operations of SS pin depending on your application. + * -This function only works in full duplex master mode. + */ +en_result_t SPI_Receive(M4_SPI_TypeDef *SPIx, void *pvRxBuf, uint32_t u32RxLength) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((pvRxBuf != NULL) && (u32RxLength != 0U)) + { + /* Receives data in full duplex master mode. */ + enRet = SPI_TxRx(SPIx, NULL, pvRxBuf, u32RxLength); + } + return enRet; +} + +/** + * @brief SPI transmit and receive data. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * If this pointer is NULL and the pvRxBuf is NOT NULL, the MOSI output high + * and the the received data will be stored in the buffer pointed by pvRxBuf. + * @param [out] pvRxBuf The pointer to the buffer which the received data will be stored. + * This for full duplex transfer. + * @param [in] u32Length The length of the data(in byte or half word) to be sent and received. + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred + * @arg ErrorTimeout: SPI transmit and receive timeout. + * @arg ErrorInvalidParameter: pvRxBuf == NULL or pvRxBuf == NULL or u32Length == 0U + * @note SPI receives data while sending data. Only works in full duplex master mode. + */ +en_result_t SPI_TransmitReceive(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Length) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((pvTxBuf != NULL) && (pvRxBuf != NULL) && (u32Length != 0U)) + { + /* Transmit and receive data in full duplex master mode. */ + enRet = SPI_TxRx(SPIx, pvTxBuf, pvRxBuf, u32Length); + } + return enRet; +} +/** + * @} + */ + +/** + * @addtogroup SPI_Local_Functions SPI Local Functions + * @{ + */ +/** + * @brief SPI transmit and receive data in full duplex mode. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [out] pvRxBuf The pointer to the buffer which the received data will be stored. + * @param [in] u32Length The length of the data in byte or half word. + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred + * @arg ErrorTimeout: SPI transmit and receive timeout. + */ +static en_result_t SPI_TxRx(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Length) +{ + uint32_t u32BitSize; + __IO uint32_t u32Timecount; + __IO uint32_t u32Count = 0U; + en_result_t enRet = Ok; + uint32_t u32Tmp; + __UNUSED __IO uint32_t u32Read; + + /* Get data bit size, SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_32BIT */ + u32BitSize = READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_DSIZE); + + while (u32Count < u32Length) + { + if (pvTxBuf != NULL) + { + if (u32BitSize <= SPI_DATA_SIZE_8BIT) + { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + WRITE_REG32(SPIx->DR, ((const uint8_t *)pvTxBuf)[u32Count]); + } + else if(u32BitSize <= SPI_DATA_SIZE_16BIT) + { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + WRITE_REG32(SPIx->DR, ((const uint16_t *)pvTxBuf)[u32Count]); + } + else + { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + WRITE_REG32(SPIx->DR, ((const uint32_t *)pvTxBuf)[u32Count]); + } + } + else + { + WRITE_REG32(SPIx->DR, 0xFFFFFFFFUL); + } + + /* Delay about 10ms */ + u32Timecount = HCLK_VALUE/100UL; + do + { + if(0UL != READ_REG32_BIT(SPIx->SR, SPI_FLAG_RX_BUFFER_FULL)) + { + break; + } + u32Timecount--; + } while (u32Timecount != 0U); + + if (u32Timecount == 0U) + { + enRet = ErrorTimeout; + break; + } + + u32Tmp = READ_REG32(SPIx->DR); + if (pvRxBuf != NULL) + { + if (u32BitSize <= SPI_DATA_SIZE_8BIT) + { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + ((uint8_t *)pvRxBuf)[u32Count] = (uint8_t)u32Tmp; + } + else if(u32BitSize <= SPI_DATA_SIZE_16BIT) + { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + ((uint16_t *)pvRxBuf)[u32Count] = (uint16_t)u32Tmp; + } + else + { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + ((uint32_t *)pvRxBuf)[u32Count] = (uint32_t)u32Tmp; + } + } + else + { + /* Dummy read */ + u32Read = READ_REG32(SPIx->DR); + } + + u32Count++; + } + return enRet; +} + +/** + * @brief SPI send data only. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [in] u32Length The length of the data in byte or half word or word. + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred. + * @arg ErrorTimeout: SPI transmit timeout. + */ +static en_result_t SPI_Tx(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32Length) +{ + __IO uint32_t u32Count = 0U; + __IO uint32_t u32Timecount; + uint32_t u32BitSize; + en_result_t enRet = Ok; + + /* Get data bit size, SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_32BIT */ + u32BitSize = READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_DSIZE); + + while (u32Count < u32Length) + { + if (u32BitSize <= SPI_DATA_SIZE_8BIT) + { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + WRITE_REG32(SPIx->DR, ((const uint8_t *)pvTxBuf)[u32Count]); + } + else if(u32BitSize <= SPI_DATA_SIZE_16BIT) + { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + WRITE_REG32(SPIx->DR, ((const uint16_t *)pvTxBuf)[u32Count]); + } + else + { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + WRITE_REG32(SPIx->DR, ((const uint32_t *)pvTxBuf)[u32Count]); + } + + /* Delay about 10ms */ + u32Timecount = HCLK_VALUE/100UL; + do + { + if(0UL != READ_REG32_BIT(SPIx->SR, SPI_FLAG_TX_BUFFER_EMPTY)) + { + break; + } + u32Timecount--; + } while (u32Timecount != 0U); + + if (u32Timecount == 0U) + { + enRet = ErrorTimeout; + } + + u32Count++; + } + return enRet; +} + +/** + * @} + */ + +#endif /* DDL_SPI_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32f4a0_spi.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32f4a0_spi.h new file mode 100755 index 000000000..961babdd2 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32f4a0_spi.h @@ -0,0 +1,446 @@ +/** + ******************************************************************************* + * @file hc32f4a0_spi.h + * @brief This file contains all the functions prototypes of the SPI driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wangmin First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_SPI_H__ +#define __HC32F4A0_SPI_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_SPI + * @{ + */ + +#if (DDL_SPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup SPI_Global_Types SPI Global Types + * @{ + */ + +/** + * @brief Structure definition of SPI initialization. + */ +typedef struct +{ + uint32_t u32WireMode; /*!< SPI wire mode, 3 wire mode or 4 wire mode. + This parameter can be a value of @ref SPI_Wire_Mode_Define */ + uint32_t u32TransMode; /*!< SPI transfer mode, send only or full duplex. + This parameter can be a value of @ref SPI_Transfer_Mode_Define */ + uint32_t u32MasterSlave; /*!< SPI master/slave mode. + This parameter can be a value of @ref SPI_Master_Slave_Mode_Define */ + uint32_t u32SuspMode; /*!< SPI communication suspend function. + This parameter can be a value of @ref SPI_Communication_Suspend_Function_Define */ + uint32_t u32Modfe; /*!< SPI mode fault detect command. + This parameter can be a value of @ref SPI_Mode_Fault_Dectet_Command_Define */ + uint32_t u32Parity; /*!< SPI parity check selection. + This parameter can be a value of @ref SPI_Parity_Check_Define */ + uint32_t u32SpiMode; /*!< SPI mode. + This parameter can be a value of @ref SPI_Mode_Define */ + uint32_t u32BaudRatePrescaler; /*!< SPI baud rate prescaler. + This parameter can be a value of @ref SPI_Baud_Rate_Prescaler_Define */ + uint32_t u32DataBits; /*!< SPI data bits, 4 bits ~ 32 bits. + This parameter can be a value of @ref SPI_Data_Size_Define */ + uint32_t u32FirstBit; /*!< MSB first or LSB first. + This parameter can be a value of @ref SPI_First_Bit_Define */ + uint32_t u32FrameLevel; /*!< SPI frame level, SPI_FRAME_1 ~ SPI_FRAME_4. + This parameter can be a value of @ref SPI_Frame_Level_Define */ +} stc_spi_init_t; + +/** + * @brief Structure definition of SPI delay time configuration. + */ +typedef struct +{ + uint32_t u32IntervalDelay; /*!< SPI interval time delay (Next access delay time) + This parameter can be a value of @ref SPI_Interval_Delay_Time_define */ + uint32_t u32ReleaseDelay; /*!< SPI release time delay (SCK invalid delay time) + This parameter can be a value of @ref SPI_Release_Delay_Time_define */ + uint32_t u32SetupDelay; /*!< SPI Setup time delay (SCK valid delay time) define + This parameter can be a value of @ref SPI_Setup_Delay_Time_define */ +} stc_spi_delay_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SPI_Global_Macros SPI Global Macros + * @{ + */ + +/** + * @defgroup SPI_Wire_Mode_Define SPI wire mode define + * @{ + */ +#define SPI_WIRE_4 (0UL) +#define SPI_WIRE_3 (SPI_CR1_SPIMDS) +/** + * @} + */ + +/** + * @defgroup SPI_Transfer_Mode_Define SPI transfer mode define + * @{ + */ +#define SPI_FULL_DUPLEX (0UL) /*!< Full duplex. */ +#define SPI_SEND_ONLY (SPI_CR1_TXMDS) /*!< Send only. */ +/** + * @} + */ + +/** + * @defgroup SPI_Master_Slave_Mode_Define SPI master slave mode define + * @{ + */ +#define SPI_SLAVE (0UL) +#define SPI_MASTER (SPI_CR1_MSTR) +/** + * @} + */ + +/** + * @defgroup SPI_Loopback_Selection_Define SPI loopback selection define + * @note Loopback mode is mainly used for parity self-diagnosis in 4-wire full-duplex mode. + * @{ + */ +#define SPI_SPLPBK_INVALID (0UL) +#define SPI_SPLPBK_MOSI_INVERT (SPI_CR1_SPLPBK) /*!< MISO data is the inverse of the data output by MOSI. */ +#define SPI_SPLPBK_MOSI (SPI_CR1_SPLPBK2) /*!< MISO data is the data output by MOSI. */ +/** + * @} + */ + +/** + * @defgroup SPI_Communication_Suspend_Function_Define SPI communication suspend function define + * @{ + */ +#define SPI_COM_SUSP_FUNC_OFF (0UL) +#define SPI_COM_SUSP_FUNC_ON (SPI_CR1_CSUSPE) +/** + * @} + */ + +/** + * @defgroup SPI_Interrupt_Type_Define SPI interrupt type define + * @{ + */ +#define SPI_INT_ERROR (SPI_CR1_EIE) /*!< Including overload, underload and parity error. */ +#define SPI_INT_TX_BUFFER_EMPTY (SPI_CR1_TXIE) +#define SPI_INT_RX_BUFFER_FULL (SPI_CR1_RXIE) +#define SPI_INT_IDLE (SPI_CR1_IDIE) +/** + * @} + */ + +/** + * @defgroup SPI_Mode_Fault_Dectet_Command_Define SPI mode fault dectect command define + * @{ + */ +#define SPI_MODFE_DISABLE (0UL) /*!< Disable mode fault detection. */ +#define SPI_MODFE_ENABLE (SPI_CR1_MODFE) /*!< Enable mode fault detection. */ +/** + * @} + */ + +/** + * @defgroup SPI_Parity_Check_Error_Self_Diagnosis_Define SPI parity check error self diagnosis define + * @{ + */ +#define SPI_PATE_DISABLE (0UL) /*!< Disable self diagnosis of parity check. */ +#define SPI_PATE_ENABLE (SPI_CR1_PATE) /*!< Enable self diagnosis of parity check. */ +/** + * @} + */ + +/** + * @defgroup SPI_Parity_Check_Define SPI parity check mode define + * @{ + */ +#define SPI_PARITY_INVALID (0UL) /*!< Parity check invalid. */ +#define SPI_PARITY_EVEN (SPI_CR1_PAE) /*!< Parity check selection even parity. */ +#define SPI_PARITY_ODD (SPI_CR1_PAE | SPI_CR1_PAOE) /*!< Parity check selection odd parity. */ +/** + * @} + */ + +/** + * @defgroup SPI_Interval_Delay_Time_define SPI interval time delay (Next access delay time) define + * @{ + */ +#define SPI_INTERVAL_TIME_1SCK_2PCLK1 (0UL) +#define SPI_INTERVAL_TIME_2SCK_2PCLK1 (SPI_CFG1_MIDI_0) +#define SPI_INTERVAL_TIME_3SCK_2PCLK1 (SPI_CFG1_MIDI_1) +#define SPI_INTERVAL_TIME_4SCK_2PCLK1 (SPI_CFG1_MIDI_1 | SPI_CFG1_MIDI_0) +#define SPI_INTERVAL_TIME_5SCK_2PCLK1 (SPI_CFG1_MIDI_2) +#define SPI_INTERVAL_TIME_6SCK_2PCLK1 (SPI_CFG1_MIDI_2 | SPI_CFG1_MIDI_0) +#define SPI_INTERVAL_TIME_7SCK_2PCLK1 (SPI_CFG1_MIDI_2 | SPI_CFG1_MIDI_1) +#define SPI_INTERVAL_TIME_8SCK_2PCLK1 (SPI_CFG1_MIDI_2 | SPI_CFG1_MIDI_1 | SPI_CFG1_MIDI_0) +/** + * @} + */ + +/** + * @defgroup SPI_Release_Delay_Time_define SPI release time delay (SCK invalid delay time) define + * @{ + */ +#define SPI_RELEASE_TIME_1SCK (0UL) +#define SPI_RELEASE_TIME_2SCK (SPI_CFG1_MSSDL_0) +#define SPI_RELEASE_TIME_3SCK (SPI_CFG1_MSSDL_1) +#define SPI_RELEASE_TIME_4SCK (SPI_CFG1_MSSDL_1 | SPI_CFG1_MSSDL_0) +#define SPI_RELEASE_TIME_5SCK (SPI_CFG1_MSSDL_2) +#define SPI_RELEASE_TIME_6SCK (SPI_CFG1_MSSDL_2 | SPI_CFG1_MSSDL_0) +#define SPI_RELEASE_TIME_7SCK (SPI_CFG1_MSSDL_2 | SPI_CFG1_MSSDL_1) +#define SPI_RELEASE_TIME_8SCK (SPI_CFG1_MSSDL_2 | SPI_CFG1_MSSDL_1 | SPI_CFG1_MSSDL_0) +/** + * @} + */ + +/** + * @defgroup SPI_Setup_Delay_Time_define SPI Setup time delay (SCK valid delay time) define + * @{ + */ +#define SPI_SETUP_TIME_1SCK (0UL) +#define SPI_SETUP_TIME_2SCK (SPI_CFG1_MSSI_0) +#define SPI_SETUP_TIME_3SCK (SPI_CFG1_MSSI_1) +#define SPI_SETUP_TIME_4SCK (SPI_CFG1_MSSI_1 | SPI_CFG1_MSSI_0) +#define SPI_SETUP_TIME_5SCK (SPI_CFG1_MSSI_2) +#define SPI_SETUP_TIME_6SCK (SPI_CFG1_MSSI_2 | SPI_CFG1_MSSI_0) +#define SPI_SETUP_TIME_7SCK (SPI_CFG1_MSSI_2 | SPI_CFG1_MSSI_1) +#define SPI_SETUP_TIME_8SCK (SPI_CFG1_MSSI_2 | SPI_CFG1_MSSI_1 | SPI_CFG1_MSSI_0) +/** + * @} + */ + +/** + * @defgroup SPI_SS_Pin_Define SPI SSx define + * @{ + */ +#define SPI_PIN_SS0 (SPI_CFG1_SS0PV) +#define SPI_PIN_SS1 (SPI_CFG1_SS1PV) +#define SPI_PIN_SS2 (SPI_CFG1_SS2PV) +#define SPI_PIN_SS3 (SPI_CFG1_SS3PV) +/** + * @} + */ + +/** + * @defgroup SPI_SS_Active_Level_Define SPI SSx Active Level define + * @{ + */ +#define SPI_SS_ACTIVE_LOW (0UL) /*!< SS pin active low. */ +#define SPI_SS_ACTIVE_HIGH (1UL) /*!< SS pin active high. */ +/** + * @} + */ + +/** + * @defgroup SPI_Read_Target_Buffer_Define SPI read data register target buffer define + * @{ + */ +#define SPI_RD_TARGET_RD_BUF (0UL) /*!< Read RX buffer. */ +#define SPI_RD_TARGET_WR_BUF (SPI_CFG1_SPRDTD) /*!< Read TX buffer. */ +/** + * @} + */ + +/** + * @defgroup SPI_Frame_Level_Define SPI data frame level define, The Data in the + * SPI_DR register will be send to TX_BUFF after + * enough data frame write to the SPI_DR + * @{ + */ +#define SPI_FRAME_1 (0UL) /*!< Data 1 frame */ +#define SPI_FRAME_2 (SPI_CFG1_FTHLV_0) /*!< Data 2 frame.*/ +#define SPI_FRAME_3 (SPI_CFG1_FTHLV_1) /*!< Data 3 frame.*/ +#define SPI_FRAME_4 (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1) /*!< Data 4 frame.*/ +/** + * @} + */ + +/** + * @defgroup SPI_Mode_Define SPI Mode define + * @{ + */ +/* SCK pin output low in idle state; MOSI/MISO pin data valid in odd edge , MOSI/MISO pin data change in even edge */ +#define SPI_MODE_0 (0UL) +/* SCK pin output low in idle state; MOSI/MISO pin data valid in even edge , MOSI/MISO pin data change in odd edge */ +#define SPI_MODE_1 (SPI_CFG2_CPHA) +/* SCK pin output high in idle state; MOSI/MISO pin data valid in odd edge , MOSI/MISO pin data change in even edge */ +#define SPI_MODE_2 (SPI_CFG2_CPOL) +/* SCK pin output high in idle state; MOSI/MISO pin data valid in even edge , MOSI/MISO pin data change in odd edge */ +#define SPI_MODE_3 (SPI_CFG2_CPOL | SPI_CFG2_CPHA) +/** + * @} + */ + +/** + * @defgroup SPI_Baud_Rate_Prescaler_Define SPI baudrate prescaler define + * @{ + */ +#define SPI_BR_PCLK1_DIV2 (0UL) /*!< SPI baud rate is the pclk1 divided by 2. */ +#define SPI_BR_PCLK1_DIV4 (SPI_CFG2_MBR_0) /*!< SPI baud rate is the pclk1 clock divided by 4. */ +#define SPI_BR_PCLK1_DIV8 (SPI_CFG2_MBR_1) /*!< SPI baud rate is the pclk1 clock divided by 8. */ +#define SPI_BR_PCLK1_DIV16 (SPI_CFG2_MBR_1 | SPI_CFG2_MBR_0) /*!< SPI baud rate is the pclk1 clock divided by 16. */ +#define SPI_BR_PCLK1_DIV32 (SPI_CFG2_MBR_2) /*!< SPI baud rate is the pclk1 clock divided by 32. */ +#define SPI_BR_PCLK1_DIV64 (SPI_CFG2_MBR_2 | SPI_CFG2_MBR_0) /*!< SPI baud rate is the pclk1 clock divided by 64. */ +#define SPI_BR_PCLK1_DIV128 (SPI_CFG2_MBR_2 | SPI_CFG2_MBR_1) /*!< SPI baud rate is the pclk1 clock divided by 128. */ +#define SPI_BR_PCLK1_DIV256 (SPI_CFG2_MBR_2 | SPI_CFG2_MBR_1 | SPI_CFG2_MBR_0) /*!< SPI baud rate is the pclk1 divided by 256. */ +/** + * @} + */ + +/** + * @defgroup SPI_Data_Size_Define SPI data size define + * @{ + */ +#define SPI_DATA_SIZE_4BIT (0UL) +#define SPI_DATA_SIZE_5BIT (SPI_CFG2_DSIZE_0) +#define SPI_DATA_SIZE_6BIT (SPI_CFG2_DSIZE_1) +#define SPI_DATA_SIZE_7BIT (SPI_CFG2_DSIZE_0 | SPI_CFG2_DSIZE_1) +#define SPI_DATA_SIZE_8BIT (SPI_CFG2_DSIZE_2) +#define SPI_DATA_SIZE_9BIT (SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_0) +#define SPI_DATA_SIZE_10BIT (SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_1) +#define SPI_DATA_SIZE_11BIT (SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_1 | SPI_CFG2_DSIZE_0) +#define SPI_DATA_SIZE_12BIT (SPI_CFG2_DSIZE_3) +#define SPI_DATA_SIZE_13BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_0) +#define SPI_DATA_SIZE_14BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_1) +#define SPI_DATA_SIZE_15BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_1 | SPI_CFG2_DSIZE_0) +#define SPI_DATA_SIZE_16BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_2) +#define SPI_DATA_SIZE_20BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_0) +#define SPI_DATA_SIZE_24BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_1) +#define SPI_DATA_SIZE_32BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_1 | SPI_CFG2_DSIZE_0) +/** + * @} + */ + +/** + * @defgroup SPI_First_Bit_Define SPI first bit define + * @{ + */ +#define SPI_FIRST_MSB (0UL) +#define SPI_FIRST_LSB (SPI_CFG2_LSBF) +/** + * @} + */ + +/** + * @defgroup SPI_State_Flag_Define SPI state flag define + * @{ + */ +#define SPI_FLAG_OVERLOAD (SPI_SR_OVRERF) +#define SPI_FLAG_IDLE (SPI_SR_IDLNF) +#define SPI_FLAG_MODE_FAULT (SPI_SR_MODFERF) +#define SPI_FLAG_PARITY_ERROR (SPI_SR_PERF) +#define SPI_FLAG_UNDERLOAD (SPI_SR_UDRERF) +#define SPI_FLAG_TX_BUFFER_EMPTY (SPI_SR_TDEF) /*!< This flag is set when the data in the data register \ + is copied into the shift register, but the transmission \ + of the data bit may not have been completed. */ +#define SPI_FLAG_RX_BUFFER_FULL (SPI_SR_RDFF) /*!< When this flag is set, it indicates that a data was received. */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SPI_Global_Functions + * @{ + */ +en_result_t SPI_StructInit(stc_spi_init_t *pstcInit); +en_result_t SPI_DelayStructInit(stc_spi_delay_t *pstcDelayCfg); + +en_result_t SPI_Init(M4_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcInit); +void SPI_DeInit(M4_SPI_TypeDef *SPIx); + +void SPI_IntCmd(M4_SPI_TypeDef *SPIx, uint32_t u32IntType, en_functional_state_t enNewState); +void SPI_FunctionCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewState); + +void SPI_WriteDataReg(M4_SPI_TypeDef *SPIx, uint32_t u32Data); +uint32_t SPI_ReadDataReg(const M4_SPI_TypeDef *SPIx); + +en_flag_status_t SPI_GetStatus(const M4_SPI_TypeDef *SPIx, uint32_t u32Flag); +void SPI_ClearFlag(M4_SPI_TypeDef *SPIx, uint32_t u32Flag); + +void SPI_LoopbackModeCfg(M4_SPI_TypeDef *SPIx, uint32_t u32Mode); +void SPI_PateCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewState); +en_result_t SPI_DelayTimeCfg(M4_SPI_TypeDef *SPIx, const stc_spi_delay_t *pstcDelayCfg); +void SPI_SSValidLevelCfg(M4_SPI_TypeDef *SPIx, uint32_t u32SSPin, en_functional_state_t enNewState); +void SPI_SSPinSel(M4_SPI_TypeDef *SPIx, uint32_t u32SSPin); +void SPI_ReadBufCfg(M4_SPI_TypeDef *SPIx, uint32_t u32ReadBuf); + +en_result_t SPI_Transmit(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32TxLength); +en_result_t SPI_Receive(M4_SPI_TypeDef *SPIx, void *pvRxBuf, uint32_t u32RxLength); +en_result_t SPI_TransmitReceive(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Length); + +/** + * @} + */ + +#endif /* DDL_SPI_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_SPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/w25qxx.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/w25qxx.c deleted file mode 100755 index 5a5f5c807..000000000 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/w25qxx.c +++ /dev/null @@ -1,575 +0,0 @@ -/** - ******************************************************************************* - * @file w25qxx.c - * @brief This midware file provides firmware functions to W25QXX group spi flash. - @verbatim - Change Logs: - Date Author Notes - 2020-06-12 Wangmin First version - 2020-08-31 Wangmin Modify for MISRAC2012 - @endverbatim - ******************************************************************************* - * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. - * - * This software component is licensed by HDSC under BSD 3-Clause license - * (the "License"); You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ - -/******************************************************************************* - * Include files - ******************************************************************************/ -#include "w25qxx.h" -#include "ev_hc32f4a0_lqfp176_w25qxx.h" - -/** - * @addtogroup BSP - * @{ - */ - -/** - * @addtogroup Components - * @{ - */ - -/** @defgroup W25QXX Flash Driver for W25QXX - * @{ - */ - -#if (BSP_W25QXX_ENABLE == BSP_ON) - -/******************************************************************************* - * Local type definitions ('typedef') - ******************************************************************************/ - -/******************************************************************************* - * Local pre-processor symbols/macros ('#define') - ******************************************************************************/ -/** - * @defgroup W25QXX_Local_Macros W25QXX Local Macros - * @{ - */ -#define W25Q_BIT_0 (1UL << 0U) -#define W25Q_BIT_1 (1UL << 1U) -#define W25Q_BIT_2 (1UL << 2U) -#define W25Q_BIT_3 (1UL << 3U) -#define W25Q_BIT_4 (1UL << 4U) -#define W25Q_BIT_5 (1UL << 5U) -#define W25Q_BIT_6 (1UL << 6U) -#define W25Q_BIT_7 (1UL << 7U) -#define W25Q_BIT_8 (1UL << 8U) -#define W25Q_BIT_9 (1UL << 9U) -#define W25Q_BIT_10 (1UL << 10U) -#define W25Q_BIT_11 (1UL << 11U) -#define W25Q_BIT_12 (1UL << 12U) -#define W25Q_BIT_13 (1UL << 13U) -#define W25Q_BIT_14 (1UL << 14U) -#define W25Q_BIT_15 (1UL << 15U) - -#define W25Q_ST_BUSY ((uint16_t)W25Q_BIT_0) -#define W25Q_ST_WEL ((uint16_t)W25Q_BIT_1) /*> 16U); \ - (a)[2U] = (uint8_t)((addr) >> 8U); \ - (a)[3U] = (uint8_t)(addr); \ - } while (0U) - -/** - * @} - */ - -/******************************************************************************* - * Global variable definitions (declared in header file with 'extern') - ******************************************************************************/ - -/******************************************************************************* - * Local function prototypes ('static') - ******************************************************************************/ -/** - * @defgroup W25QXX_Local_Functions W25QXX Local Functions - * @{ - */ -static void W25QXX_WriteCmd(uint8_t u8Cmd, const uint8_t *pu8CmdData, uint32_t u32CmdDataLength); -static void W25QXX_ReadCmd(uint8_t u8Cmd, uint8_t *pu8CmdData, uint32_t u32CmdDataLength, - uint8_t *pu8Info, uint8_t u8InfoLength); - -static void W25QXX_Wt(uint8_t u8Cmd, uint32_t u32Address, const uint8_t *pu8Data, uint32_t u32DataLength); -static void W25QXX_Rd(uint8_t u8Cmd, uint32_t u32Address, uint8_t *pu8Data, uint32_t u32DataLength); - -static void W25QXX_WaitBusy(void); - -static void W25QXX_WriteEnable(void); -static void W25QXX_WriteDisable(void); - -static void W25QXX_WritePage(uint32_t u32Address, const uint8_t *pu8Data, uint32_t u32DataLength); - -static void W25QXX_Write_NoCheck(const uint8_t *pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite); -static void W25QXX_WriteCmd(uint8_t u8Cmd, const uint8_t *pu8CmdData, uint32_t u32CmdDataLength); -static void W25QXX_ReadCmd(uint8_t u8Cmd, uint8_t *pu8CmdData, uint32_t u32CmdDataLength, - uint8_t *pu8Info, uint8_t u8InfoLength); -/** - * @} - */ - -/******************************************************************************* - * Local variable definitions ('static') - ******************************************************************************/ -static uint8_t W25QXX_BUFFER[4096U]; - -/******************************************************************************* - * Function implementation - global ('extern') and local ('static') - ******************************************************************************/ -/** - * @defgroup W25QXX_Global_Functions W25QXX Global Functions - * @{ - */ - -/** - * @brief Initializes W25QXX. - * @param [out] pstcW25qxx Pointer to a stc_w25qxx_t structure which contains the information of the SPI flash. - * @retval None - */ -void W25QXX_Init(stc_w25qxx_t *pstcW25qxx) -{ - BSP_W25Q_SPI_Init(); - - if (pstcW25qxx != NULL) - { - /* Read Flash ID */ - pstcW25qxx->u16ManId = W25QXX_ReadManDeviceId(); - - switch (pstcW25qxx->u16ManId) - { - case W25Q64: - pstcW25qxx->u32PageCount = 32768UL; /* W25Q64 contains 32768 pages. */ - pstcW25qxx->u32SectorCount = 2048U; /* W25Q64 contains 2048 sectors. */ - pstcW25qxx->u32BlockCount32k = 0U; /* DO NOT support 32K block. */ - pstcW25qxx->u32BlockCount64k = 128U; - pstcW25qxx->u32CapacityInBytes = pstcW25qxx->u32PageCount * W25Q_SIZE_PAGE; - pstcW25qxx->u32CapacityInKB = pstcW25qxx->u32CapacityInBytes * W25Q_SIZE_1K; - break; - - default: - break; - } - } -} - -/** - * @brief Read manufacturer device ID. - * @param None - * @retval 16 bit manufacturer device ID. - */ -uint16_t W25QXX_ReadManDeviceId(void) -{ - uint8_t au8TempId[2U]; - uint8_t au8Dummy[3U] = {0U}; - uint16_t u16ManID; - - W25QXX_ReadCmd(W25Q_MANUFACTURER_DEVICE_ID, au8Dummy, 3U, au8TempId, 2U); - - u16ManID = (uint16_t)au8TempId[0U] << 8U; - u16ManID |= au8TempId[1U]; - - return u16ManID; -} - -/** - * @brief Read unique ID. - * @param [out] pu8UniqueId Pointer to a buffer the 64 bit unique ID to be stored. - * @retval None - */ -void W25QXX_ReadUniqueId(uint8_t *pu8UniqueId) -{ - uint8_t au8Dummy[4U] = {0U}; - - W25QXX_ReadCmd(W25Q_READ_UNIQUE_ID, au8Dummy, 4U, pu8UniqueId, 8U); -} - -/** - * @brief W25QXX read status register. - * @param None - * @retval 16 bit W25QXX status. - */ -uint16_t W25QXX_ReadStatus(void) -{ - uint8_t u8TempStatus; - uint16_t u16RetStatus; - - W25QXX_ReadCmd(W25Q_READ_STATUS_REG_2, NULL, 0U, &u8TempStatus, 1U); - - u16RetStatus = u8TempStatus; - - W25QXX_ReadCmd(W25Q_READ_STATUS_REG_1, NULL, 0U, &u8TempStatus, 1U); - - u16RetStatus <<= 8U; - u16RetStatus |= u8TempStatus; - - return u16RetStatus; -} - -/** - * @brief W25QXX write status register - * @param [in] u16Status Specified status. - * @retval None - */ -void W25QXX_WriteStatus(uint16_t u16Status) -{ - uint8_t au8Data[2U]; - - au8Data[0U] = (uint8_t)u16Status; - au8Data[1U] = (uint8_t)(u16Status >> 8U); - - W25QXX_WriteCmd(W25Q_WRITE_STATUS_REG, au8Data, 2U); -} - -/** - * @brief W25QXX power down. - * @param None - * @retval None - */ -void W25QXX_PowerDown(void) -{ - W25QXX_WriteCmd(W25Q_POWER_DOWN, NULL, 0U); - - W25QXX_DELAY_MS(1U); -} - -/** - * @brief W25QXX release power down. - * @param None - * @retval None - */ -void W25QXX_ReleasePowerDown(void) -{ - W25QXX_WriteCmd(W25Q_RELEASE_POWER_DOWN, NULL, 0U); - - W25QXX_DELAY_MS(1U); -} - -/** - * @brief W25QXX chip ease. - * @param None - * @retval None - */ -void W25QXX_EraseChip(void) -{ - W25QXX_WriteEnable(); - W25QXX_WaitBusy(); - W25QXX_WriteCmd(W25Q_CHIP_ERASE, NULL, 0U); - W25QXX_WaitBusy(); -} - -/** - * @brief W25QXX sector ease. - * @param [in] u32SectorAddress The address of the specified sector. - * @retval None - */ -void W25QXX_EraseSector(uint32_t u32SectorAddress) -{ - u32SectorAddress *= W25Q_SIZE_SECTOR; - - W25QXX_WriteEnable(); - W25QXX_WaitBusy(); - - W25QXX_Wt(W25Q_SECTOR_ERASE, u32SectorAddress, NULL, 0U); - - W25QXX_WaitBusy(); - W25QXX_WriteDisable(); -} - -/** - * @brief W25QXX block ease. - * @param [in] u32BlockAddress The address of the specified block. - * @retval None - */ -void W25QXX_EraseBlock(uint32_t u32BlockAddress) -{ - W25QXX_Wt(W25Q_BLOCK_ERASE_64K, u32BlockAddress, NULL, 0U); -} - - -/** - * @brief W25QXX flash write - * @param [in] pBuffer Data buffer to be written - * @param [in] WriteAddr Address to be written - * @param [in] NumByteToWrite Number to be written, (MAX. 65535) - * @retval None - */ -static void W25QXX_Write_NoCheck(const uint8_t *pBuffer, uint32_t WriteAddr, uint16_t NumByteToWrite) -{ - uint32_t pageremain; - uint32_t u32BufAdrTmp = (uint32_t)pBuffer; - pageremain = 256U - WriteAddr % 256U; - if (NumByteToWrite <= pageremain) - { - pageremain = NumByteToWrite; - } - for(;;) - { - W25QXX_WritePage(WriteAddr, (uint8_t *)u32BufAdrTmp, pageremain); - if (NumByteToWrite == (uint16_t)pageremain) - { - break; - } - else //NumByteToWrite>pageremain - { - u32BufAdrTmp += pageremain; - WriteAddr += pageremain; - - NumByteToWrite -= (uint16_t)pageremain; - if (NumByteToWrite > 256U) - { - pageremain = 256U; - } - else - { - pageremain = (uint32_t)NumByteToWrite; - } - } - } -} - - -/** - * @brief W25QXX write data. - * @param [in] u32Address The start address of the data to be written. - * @param [in] pu8WriteBuf The pointer to the buffer contains the data to be written. - * @param [in] u32NumByteToWrite Buffer size in bytes. - * @retval None - */ -void W25QXX_WriteData(uint32_t u32Address, const uint8_t *pu8WriteBuf, uint32_t u32NumByteToWrite) -{ - uint32_t secpos; - uint16_t secoff; - uint16_t secremain; - uint16_t i; - uint8_t *pW25QXX_BUF; - pW25QXX_BUF = W25QXX_BUFFER; - uint32_t u32WriteBufAddr = (uint32_t)&pu8WriteBuf; - - secpos = u32Address / 4096U; - secoff = (uint16_t)(u32Address % 4096U); - secremain = 4096U - secoff; - - if (u32NumByteToWrite <= secremain) - { - secremain = (uint16_t)u32NumByteToWrite; - } - for(;;) - { - W25QXX_ReadData(secpos * 4096U, pW25QXX_BUF, 4096U); // read one sector content - for (i = 0U; i < secremain; i++) // check if blank sector - { - if (pW25QXX_BUF[secoff + i] != (uint8_t)0xFFU) - { - break; - } - } - if (i < secremain) - { - W25QXX_EraseSector(secpos); // not blank, need erase - for (i = 0U; i < secremain; i++) // backup first - { - pW25QXX_BUF[i + secoff] = pu8WriteBuf[i]; - } - W25QXX_Write_NoCheck(pW25QXX_BUF, secpos * 4096U, 4096U); // write back after erase - - } - else - { - W25QXX_Write_NoCheck((const uint8_t *)u32WriteBufAddr, u32Address, secremain); - } - if (u32NumByteToWrite == secremain) - { - break; - } - else - { - secpos++; // next sector - secoff = 0U; - - u32WriteBufAddr += secremain; - u32Address += secremain; - u32NumByteToWrite -= secremain; - if (u32NumByteToWrite > 4096U) - { - secremain = 4096U; - } - else - { - secremain = (uint16_t)u32NumByteToWrite; - } - } - } -} - -/** - * @brief W25QXX read data. - * @param [in] u32Address The start address of the data to be read. - * @param [in] pu8ReadBuf The pointer to the buffer contains the data to be stored. - * @param [in] u32NumByteToRead Buffer size in bytes. - * @retval None - */ -void W25QXX_ReadData(uint32_t u32Address, uint8_t *pu8ReadBuf, uint32_t u32NumByteToRead) -{ - W25QXX_Rd(W25Q_READ_DATA, u32Address, pu8ReadBuf, u32NumByteToRead); -} - -/** - * @} - */ - -/** - * @addtogroup W25QXX_Local_Functions W25QXX Local Functions - * @{ - */ - -/** - * @brief W25QXX write command. - * @param [in] u8Cmd Command of W25QXX. - * @param [in] pu8CmdData Pointer to a buffer that contains the data following the command. - * @param [in] u32CmdDataLength The length of the command data in bytes. - * @retval None - */ -static void W25QXX_WriteCmd(uint8_t u8Cmd, const uint8_t *pu8CmdData, uint32_t u32CmdDataLength) -{ - W25Q_CS_ACTIVE(); - (void)BSP_W25Q_SPI_Transmit(&u8Cmd, 1U); - (void)BSP_W25Q_SPI_Transmit(pu8CmdData, u32CmdDataLength); - W25Q_CS_INACTIVE(); -} - -/** - * @brief W25QXX read command. - * @param [in] u8Cmd Command of W25QXX. - * @param [in] pu8CmdData Pointer to a buffer that contains the data following the command. - * @param [in] u32CmdDataLength The length of the command data in bytes. - * @param [in] pu8Info The information of the command. - * @param [in] u8InfoLength The length of the information. - * @retval None - */ -static void W25QXX_ReadCmd(uint8_t u8Cmd, uint8_t *pu8CmdData, uint32_t u32CmdDataLength, - uint8_t *pu8Info, uint8_t u8InfoLength) -{ - W25Q_CS_ACTIVE(); - (void)BSP_W25Q_SPI_Transmit(&u8Cmd, 1U); - (void)BSP_W25Q_SPI_Transmit(pu8CmdData, u32CmdDataLength); - (void)BSP_W25Q_SPI_Receive(pu8Info, (uint32_t)u8InfoLength); - W25Q_CS_INACTIVE(); -} - -/** - * @brief W25QXX write data. - * @param [in] u8Cmd Command of W25QXX. - * @param [in] u32Address The start address of the data to be written. - * @param [in] pu8Data The data to be written. - * @param [in] u32DataLength The length of the data in bytes. - * @retval None - */ -static void W25QXX_Wt(uint8_t u8Cmd, uint32_t u32Address, const uint8_t *pu8Data, uint32_t u32DataLength) -{ - uint8_t au8Cmd[4U]; - - LOAD_CMD(au8Cmd, u8Cmd, u32Address); - - W25Q_CS_ACTIVE(); - (void)BSP_W25Q_SPI_Transmit(au8Cmd, 4U); - (void)BSP_W25Q_SPI_Transmit(pu8Data, u32DataLength); - W25Q_CS_INACTIVE(); -} - -/** - * @brief W25QXX read data. - * @param [in] u8Cmd Command of W25QXX. - * @param [in] u32Address The start address of the data to be written. - * @param [in] pu8Data The data to be stored. - * @param [in] u32DataLength The length of the data in bytes. - * @retval None - */ -static void W25QXX_Rd(uint8_t u8Cmd, uint32_t u32Address, uint8_t *pu8Data, uint32_t u32DataLength) -{ - uint8_t au8Cmd[4U]; - - LOAD_CMD(au8Cmd, u8Cmd, u32Address); - - W25Q_CS_ACTIVE(); - (void)BSP_W25Q_SPI_Transmit(au8Cmd, 4U); - (void)BSP_W25Q_SPI_Receive(pu8Data, u32DataLength); - W25Q_CS_INACTIVE(); -} - -/** - * @brief W25QXX Write enable. - * @param None - * @retval None - */ -static void W25QXX_WriteEnable(void) -{ - W25QXX_WriteCmd(W25Q_WRITE_ENABLE, NULL, 0U); -} - -/** - * @brief W25QXX Write disable. - * @param None - * @retval None - */ -static void W25QXX_WriteDisable(void) -{ - W25QXX_WriteCmd(W25Q_WRITE_DISABLE, NULL, 0U); -} - -/** - * @brief Wait while W25QXX is busy. - * @param None - * @retval None - */ -static void W25QXX_WaitBusy(void) -{ - while ((W25QXX_ReadStatus() & W25Q_ST_BUSY) == W25Q_ST_BUSY) - { - ; - } -} - -/** - * @brief W25QXX page program. - * @param [in] u32Address Start address of the page. - * @param [in] pu8Data Pointer to a buffer that contains the data to be written. - * @param [in] u32DataLength Size of the buffer in bytes. - * @retval None - */ -static void W25QXX_WritePage(uint32_t u32Address, const uint8_t *pu8Data, uint32_t u32DataLength) -{ - W25QXX_WriteEnable(); - W25QXX_Wt(W25Q_PAGE_PROGRAM, u32Address, pu8Data, u32DataLength); - W25QXX_WaitBusy(); -} - -/** - * @} - */ - -#endif /* BSP_W25QXX_ENABLE */ - -/** - * @} - */ - -/** - * @} - */ - - -/** -* @} -*/ - -/******************************************************************************* - * EOF (not truncated) - ******************************************************************************/ diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/w25qxx.h b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/w25qxx.h deleted file mode 100755 index d68dda1c1..000000000 --- a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/w25qxx.h +++ /dev/null @@ -1,197 +0,0 @@ -/** - ******************************************************************************* - * @file w25qxx.h - * @brief This file provides firmware functions to W25QXX group spi flash. - @verbatim - Change Logs: - Date Author Notes - 2020-06-12 Wangmin First version - @endverbatim - ******************************************************************************* - * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. - * - * This software component is licensed by HDSC under BSD 3-Clause license - * (the "License"); You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ******************************************************************************* - */ -#ifndef __W25QXX_H__ -#define __W25QXX_H__ - -/* C binding of definitions if building with C++ compiler */ -#ifdef __cplusplus -extern "C" -{ -#endif - -/******************************************************************************* - * Include files - ******************************************************************************/ -#include "hc32_common.h" - -/** - * @addtogroup BSP - * @{ - */ - -/** - * @addtogroup Components - * @{ - */ - -/** @addtogroup W25QXX - * @{ - */ - -#if (BSP_W25QXX_ENABLE == BSP_ON) - -/******************************************************************************* - * Global type definitions ('typedef') - ******************************************************************************/ -/** - * @defgroup W25QXX_Global_Types W25QXX Global Types - * @{ - */ - -/** - * @brief Structure definition of W25QXX information. - */ -typedef struct -{ - uint16_t u16ManId; /*!< Manufacturer device ID. */ - uint8_t au8UniqueId[8U]; /*!< 64 bit unique ID number. */ - uint32_t u32PageCount; - uint32_t u32SectorCount; - uint32_t u32BlockCount32k; - uint32_t u32BlockCount64k; - uint32_t u32CapacityInBytes; - uint32_t u32CapacityInKB; -} stc_w25qxx_t; - - -/** - * @} - */ - -/******************************************************************************* - * Global pre-processor symbols/macros ('#define') - ******************************************************************************/ -/** - * @defgroup W25QXX_Global_Macros W25QXX Global Macros - * @{ - */ - -/** - * @defgroup W25QXX_ID W25QXX ID - * @{ - */ -#define W25Q80 (0xEF13U) -#define W25Q16 (0xEF14U) -#define W25Q32 (0xEF15U) -#define W25Q64 (0xEF16U) -#define W25Q128 (0xEF17U) -/** - * @} - */ - -/** - * @defgroup W25QXX_Command W25QXX Command - * @{ - */ -#define W25Q_WRITE_ENABLE ((uint8_t)0x06U) -#define W25Q_VOLATILE_SR_WRITE_ENABLE ((uint8_t)0x50U) -#define W25Q_WRITE_DISABLE ((uint8_t)0x04U) -#define W25Q_READ_STATUS_REG_1 ((uint8_t)0x05U) -#define W25Q_READ_STATUS_REG_2 ((uint8_t)0x35U) -#define W25Q_WRITE_STATUS_REG ((uint8_t)0x01U) -#define W25Q_PAGE_PROGRAM ((uint8_t)0x02U) -#define W25Q_SECTOR_ERASE ((uint8_t)0x20U) -#define W25Q_BLOCK_ERASE_32K ((uint8_t)0x52U) -#define W25Q_BLOCK_ERASE_64K ((uint8_t)0xD8U) -#define W25Q_CHIP_ERASE ((uint8_t)0xC7U) -#define W25Q_ERASE_PROGRAM_SUSPEND ((uint8_t)0x75U) -#define W25Q_ERASE_PROGRAM_RESUME ((uint8_t)0x7AU) -#define W25Q_POWER_DOWN ((uint8_t)0xB9U) -#define W25Q_READ_DATA ((uint8_t)0x03U) -#define W25Q_FAST_READ ((uint8_t)0x0BU) -#define W25Q_DEVICE_ID ((uint8_t)0xABU) -#define W25Q_RELEASE_POWER_DOWN (W25Q_DEVICE_ID) -#define W25Q_MANUFACTURER_DEVICE_ID ((uint8_t)0x90U) -#define W25Q_JEDEC_ID ((uint8_t)0x9FU) -#define W25Q_READ_UNIQUE_ID ((uint8_t)0x4BU) -#define W25Q_READ_SFDP_REG ((uint8_t)0x5AU) -#define W25Q_REASE_SECURITY_REG ((uint8_t)0x44U) -#define W25Q_PROGRAM_SECURITY_REG ((uint8_t)0x42U) -#define W25Q_READ_SECURITY_REG ((uint8_t)0x48U) -#define W25Q_ENABLE_QPI ((uint8_t)0x38U) -#define W25Q_ENABLE_RESET ((uint8_t)0x66U) -#define W25Q_RESET ((uint8_t)0x99U) -/** - * @} - */ - -#define W25Q_SIZE_1K (1024U) /*!< 1KB */ -#define W25Q_SIZE_PAGE (256U) /*!< 256B/page */ -#define W25Q_SIZE_SECTOR (W25Q_SIZE_1K * 4U) /*!< 4KB/sector */ -#define W25Q_SIZE_BLOCK (W25Q_SIZE_1K * 64U) /*!< 64KB/block */ - -/** - * @} - */ - -/******************************************************************************* - * Global variable definitions ('extern') - ******************************************************************************/ - -/******************************************************************************* - Global function prototypes (definition in C source) - ******************************************************************************/ -/** - * @addtogroup W25QXX_Global_Functions W25QXX Global Functions - * @{ - */ -void W25QXX_Init(stc_w25qxx_t *pstcW25qxx); -uint16_t W25QXX_ReadManDeviceId(void); -void W25QXX_ReadUniqueId(uint8_t *pu8UniqueId); - -uint16_t W25QXX_ReadStatus(void); -void W25QXX_WriteStatus(uint16_t u16Status); -void W25QXX_PowerDown(void); -void W25QXX_ReleasePowerDown(void); - -void W25QXX_EraseChip(void); -void W25QXX_EraseSector(uint32_t u32SectorAddress); -void W25QXX_EraseBlock(uint32_t u32BlockAddress); - -void W25QXX_WriteData(uint32_t u32Address, const uint8_t *pu8WriteBuf, uint32_t u32NumByteToWrite); -void W25QXX_ReadData(uint32_t u32Address, uint8_t *pu8ReadBuf, uint32_t u32NumByteToRead); -/** - * @} - */ - - -#endif /* BSP_W25QXX_ENABLE */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __W25QXX_H__ */ - -/******************************************************************************* - * EOF (not truncated) - ******************************************************************************/