1、modify the 'link.lds' file accroding to sdk;2、add irq enable and disable function

This commit is contained in:
Wang_Weigen 2023-01-11 14:32:41 +08:00
parent 6b091797ae
commit 806492e271
12 changed files with 4684 additions and 38 deletions

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@ -0,0 +1,18 @@
#
# Automatically generated file; DO NOT EDIT.
# XiZi_AIoT Project Configuration
#
CONFIG_BOARD_IMX6Q_SABRELITE_EVB=y
CONFIG_ARCH_ARM=y
#
# imx6q sabrelite feature
#
#
# Lib
#
CONFIG_LIB=y
CONFIG_LIB_POSIX=y
CONFIG_LIB_NEWLIB=y
# CONFIG_LIB_MUSLLIB is not set

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@ -81,7 +81,7 @@ struct InterruptServiceRoutines {
extern struct InterruptServiceRoutines isrManager ;
unsigned long DisableLocalInterrupt();
uint32_t DisableLocalInterrupt();
void EnableLocalInterrupt(unsigned long level);
#define DISABLE_INTERRUPT DisableLocalInterrupt

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@ -22,6 +22,14 @@
int32_t ArchEnableHwIrq(uint32_t irq_num);
int32_t ArchDisableHwIrq(uint32_t irq_num);
//! @brief
typedef enum {
CPU_0,
CPU_1,
CPU_2,
CPU_3,
} cpuid_e;
struct ExceptionStackRegister
{
uint32_t r0;

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@ -1,18 +1,8 @@
@ .equ Mode_USR, 0x10
@ .equ Mode_FIQ, 0x11
@ .equ Mode_IRQ, 0x12
@ .equ Mode_SVC, 0x13
@ .equ Mode_ABT, 0x17
@ .equ Mode_UND, 0x1B
@ .equ Mode_SYS, 0x1F
#include <asm_defines.h>
@ .equ I_BIT, 0x80 @ when I bit is set, IRQ is disabled
@ .equ F_BIT, 0x40 @ when F bit is set, FIQ is disabled
.equ STACK_SIZE, 0x00000100
.global ExceptionVectors
.section ".startup","ax"
.globl _reset
_reset:
@ -30,7 +20,6 @@ _reset:
bic r0, #(1 << 0) /* mmu */
mcr p15, 0, r0, c1, c0, 0
ldr r0, =stack_top
@ Set the startup stack for svc
@ -39,26 +28,38 @@ _reset:
@ Enter Undefined Instruction Mode and set its Stack Pointer
msr cpsr_c, #MODE_UND|I_BIT|F_BIT
mov sp, r0
sub r0, r0, #STACK_SIZE
sub r0, r0, #EXCEPTION_STACK_SIZE
@ Enter Abort Mode and set its Stack Pointer
msr cpsr_c, #MODE_ABT|I_BIT|F_BIT
mov sp, r0
sub r0, r0, #STACK_SIZE
sub r0, r0, #EXCEPTION_STACK_SIZE
@ Enter FIQ Mode and set its Stack Pointer
msr cpsr_c, #MODE_FIQ|I_BIT|F_BIT
mov sp, r0
sub r0, r0, #STACK_SIZE
sub r0, r0, #EXCEPTION_STACK_SIZE
@ Enter IRQ Mode and set its Stack Pointer
msr cpsr_c, #MODE_IRQ|I_BIT|F_BIT
mov sp, r0
sub r0, r0, #STACK_SIZE
sub r0, r0, #EXCEPTION_STACK_SIZE
/* come back to SVC mode */
msr cpsr_c, #MODE_SVC|I_BIT|F_BIT
/*
* copy the vector table into the RAM vectors
* this assumes that the RAM vectors size is divisible by 3 words (12 bytes)
*/
ldr r1,=__ram_vectors_start
ldr r2,=__ram_vectors_end
ldr r3,=ExceptionVectors
1: cmp r1,r2
ldmlt r3!,{r4,r5,r6}
stmlt r1!,{r4,r5,r6}
blt 1b
/* clear .bss */
mov r0, #0 /* get a zero */
ldr r1,=__bss_start /* bss start */

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@ -1,6 +1,6 @@
#include <asm_defines.h>
.section .vectors, "ax"
.section .text.vectors, "ax"
.code 32
.globl ExceptionVectors

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@ -3,24 +3,43 @@
#include <stddef.h>
#include <isr.h>
unsigned long __attribute__((naked)) DisableLocalInterrupt()
uint32_t DisableLocalInterrupt(void)
{
uint32_t intSave;
__asm__ __volatile__(
"mrs %0, cpsr \n"
"cpsid if "
: "=r"(intSave)
:
: "memory");
return intSave;
}
void __attribute__((naked)) EnableLocalInterrupt(unsigned long level)
void EnableLocalInterrupt(unsigned long level)
{
uint32_t intSave;
__asm__ __volatile__(
"mrs %0, cpsr \n"
"cpsie if "
: "=r"(intSave)
:
: "memory");
return;
}
int32_t ArchEnableHwIrq(uint32_t irq_num)
{
// gic_set_irq_priority(irq_num, priority);
gic_set_irq_security(irq_num, false); // set IRQ as non-secure
// gic_set_cpu_target(irq_num, CPU_0, true);
gic_enable_irq(irq_num, true);
return 0;
}
int32_t ArchDisableHwIrq(uint32_t irq_num)
{
gic_enable_irq(irq_num, false);
// gic_set_cpu_target(irq_num, CPU_0, false);
return 0;
}

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@ -1,4 +1,4 @@
SRC_FILES := board.c
SRC_FILES := board.c ivt.c
SRC_DIR := third_party_driver

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@ -15,7 +15,7 @@ endif
# export LINK_LWIP := $(KERNEL_ROOT)/resources/ethernet/LwIP/liblwip.a
# endif
export DEFINES := -DHAVE_CCONFIG_H -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO
export DEFINES := -DHAVE_CCONFIG_H
export USING_NEWLIB =1
export USING_VFS = 1

File diff suppressed because it is too large Load Diff

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@ -0,0 +1,82 @@
/*
* Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <hab_defines.h>
extern unsigned * _start_image_add;
extern unsigned * __start_boot_data;
extern unsigned * _image_size;
extern unsigned * __hab_data;
extern uint8_t input_dcd_hdr[];
extern void _reset(void);
struct hab_ivt input_ivt __attribute__ ((section (".ivt"))) ={
/** @ref hdr word with tag #HAB_TAG_IVT, length and HAB version fields
* (see @ref data)
*/
IVT_HDR(sizeof(struct hab_ivt), HAB_VER(4, 0)),
/** Absolute address of the first instruction to execute from the
* image
*/
(hab_image_entry_f)_reset,
/** Reserved in this version of HAB: should be NULL. */
NULL,
/** Absolute address of the image DCD: may be NULL. */
&input_dcd_hdr,
/** Absolute address of the Boot Data: may be NULL, but not interpreted
* any further by HAB
*/
&__start_boot_data,
/** Absolute address of the IVT.*/
(const void*) (&input_ivt),
/** Absolute address of the image CSF.*/
(const void*) &__hab_data,
/** Reserved in this version of HAB: should be zero. */
0
};
typedef struct {
uint32_t start; /**< Start address of the image */
uint32_t size; /**< Size of the image */
uint32_t plugin; /**< Plugin flag */
} boot_data_t;
boot_data_t bd __attribute__ ((section (".boot_data"))) ={
(uint32_t) &_start_image_add,
(uint32_t) &_image_size,
0,
};

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@ -1,17 +1,88 @@
STACK_SIZE = 4096;
STACK_SIZE = 48*1024;
L1_PAGE_TABLE_SIZE = 16K;
RAM_VECTORS_SIZE = 72;
OUTPUT_FORMAT("elf32-littlearm")
OUTPUT_ARCH(arm)
MEMORY
{
OCRAM (rwx) : ORIGIN = 0x00900000, LENGTH = 256K
DDR (rwx) : ORIGIN = 0x10000000, LENGTH = 2048M
}
SECTIONS
{
. = 0x80100000;
/*
* -- OCRAM --
*
* Nothing in OCRAM can be loaded at boot, because the boot image must be a contiguous
* region of memory.
*/
/* MMU L1 page table */
.l1_page_table (NOLOAD) :
{
__l1_page_table_start = .;
. += L1_PAGE_TABLE_SIZE;
} > OCRAM
/* allocate a heap in ocram */
.heap.ocram (NOLOAD) : ALIGN(4)
{
__heap_ocram_start = .;
. += LENGTH(OCRAM) - L1_PAGE_TABLE_SIZE - RAM_VECTORS_SIZE ;
__heap_ocram_end = .;
} > OCRAM
/* RAM vector table comes at the end of OCRAM */
.ram_vectors (ORIGIN(OCRAM) + LENGTH(OCRAM) - RAM_VECTORS_SIZE) (NOLOAD) :
{
__ram_vectors_start = .;
. += RAM_VECTORS_SIZE;
__ram_vectors_end = .;
} > OCRAM
/*
* -- DDR --
*/
/* -- read-only sections -- */
_start_image_add = ORIGIN(DDR);
.ivt (ORIGIN(DDR)) :
{
. = . + 0x400;
*(.ivt)
} > DDR
.boot_data :
{
__start_boot_data = .;
*(.boot_data)
} > DDR
/* aligned to ease the hexdump read of generated binary */
.dcd_hdr : ALIGN(16)
{
__start_dcd = .;
*(.dcd_hdr)
} > DDR
.dcd_wrt_cmd :
{
*(.dcd_wrt_cmd)
} > DDR
.dcd_data :
{
*(.dcd_data)
} > DDR
__text_start = .;
.text :
{
*(.vectors)
*(.startup)
*(.text)
*(.text.*)
@ -23,11 +94,14 @@ SECTIONS
KEEP(*(.isrtbl))
__isrtbl_end = .;
. = ALIGN(4);
}
} > DDR
__text_end = .;
__rodata_start = .;
.rodata : { *(.rodata) *(.rodata.*) }
.rodata :
{
*(.rodata) *(.rodata.*)
} > DDR
__rodata_end = .;
. = ALIGN(4);
@ -37,7 +111,7 @@ SECTIONS
KEEP(*(SORT(.ctors.*)))
KEEP(*(.ctors))
PROVIDE(__ctors_end__ = .);
}
} > DDR
.dtors :
{
@ -45,14 +119,14 @@ SECTIONS
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
}
} > DDR
. = ALIGN(16 * 1024);
/* . = ALIGN(16 * 1024);
.l1_page_table :
{
__l1_page_table_start = .;
. += 16K;
}
} */
. = ALIGN(8);
__data_start = .;
@ -60,7 +134,7 @@ SECTIONS
{
*(.data)
*(.data.*)
}
} > DDR
__data_end = .;
. = ALIGN(8);
@ -71,7 +145,7 @@ SECTIONS
*(.bss.*)
*(COMMON)
. = ALIGN(4);
}
} > DDR
. = ALIGN(4);
__bss_end = .;
@ -81,7 +155,7 @@ SECTIONS
. += STACK_SIZE;
__stacks_end = .;
stack_top = .;
}
} > DDR
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }