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Merge branch 'prepare_for_master' of https://git.trustie.net/xuos/xiuos into develop

This commit is contained in:
Wang_Weigen 2022-04-18 14:59:32 +08:00
parent 92def035b9 f25a814f0f
commit 7d756cd22d
51 changed files with 16166 additions and 474 deletions
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98
APP_Framework/Applications/control_app/opcua_demo/opcua_demo.c
View File

@ -21,7 +21,6 @@
#include <list.h>
#include <transform.h>
#include "board.h"
#include <lwip/altcp.h>
#include "open62541.h"
#include "ua_api.h"
@ -40,6 +39,9 @@
/*******************************************************************************
* Variables
******************************************************************************/
// to count test
static int test_cnt = 0;
static int fail_cnt = 0; // count failure times
char test_ua_ip[] = {192, 168, 250, 2};
@ -50,37 +52,56 @@ char test_ua_ip[] = {192, 168, 250, 2};
static void UaConnectTestTask(void* arg)
{
struct netif net;
UA_StatusCode retval;
char ua_uri[UA_URL_SIZE];
memset(ua_uri, 0, sizeof(ua_uri));
UA_StatusCode ret;
char url[UA_URL_SIZE];
memset(url, 0, sizeof(url));
UA_Client* client = UA_Client_new();
if(client == NULL)
{
ua_print("ua: [%s] tcp client null\n", __func__);
ua_error("ua: [%s] tcp client null\n", __func__);
return;
}
UA_ClientConfig* config = UA_Client_getConfig(client);
UA_ClientConfig_setDefault(config);
snprintf(ua_uri, sizeof(ua_uri), "opc.tcp://%d.%d.%d.%d:4840",
test_ua_ip[0], test_ua_ip[1], test_ua_ip[2], test_ua_ip[3]);
ua_notice("ua uri: %d %s\n", strlen(ua_uri), ua_uri);
retval = UA_Client_connect(client,ua_uri);
if(retval != UA_STATUSCODE_GOOD)
UA_ClientConfig_setDefault(config);
snprintf(url, sizeof(url), "opc.tcp://%d.%d.%d.%d:4840",
test_ua_ip[0], test_ua_ip[1], test_ua_ip[2], test_ua_ip[3]);
ua_notice("ua connect cnt %d fail %d\n", test_cnt++, fail_cnt ++);
ua_notice("ua connect uri: %.*s\n", strlen(url), url);
ret = UA_Client_connect(client, url);
if(ret != UA_STATUSCODE_GOOD)
{
ua_notice("ua: [%s] connected failed %x\n", __func__, retval);
ua_error("ua: [%s] connected failed %x\n", __func__, ret);
UA_Client_delete(client);
fail_cnt++;
return;
}
ua_notice("ua: [%s] connected ok!\n", __func__);
ua_notice("ua connected ok!\n");
UA_Client_delete(client);
}
void UaConnectTest(void* arg)
static void UaConnectTest(int argc, char *argv[])
{
if(argc == 2)
{
if(isdigit(argv[1][0]))
{
if(sscanf(argv[1], "%d.%d.%d.%d", &test_ua_ip[0], &test_ua_ip[1], &test_ua_ip[2], &test_ua_ip[3]) == EOF)
{
lw_notice("input wrong ip\n");
return;
}
}
}
lwip_config_tcp(lwip_ipaddr, lwip_netmask, test_ua_ip);
sys_thread_new("ua test", UaConnectTestTask, NULL, UA_STACK_SIZE, UA_TASK_PRIO);
}
@ -90,10 +111,10 @@ SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) |
void UaBrowserObjectsTestTask(void* param)
{
static int test_cnt = 0;
UA_Client* client = UA_Client_new();
ua_notice("ua: [%s] start %d ...\n", __func__, test_cnt++);
UA_Client* client = UA_Client_new();
if(client == NULL)
{
ua_error("ua: [%s] tcp client NULL\n", __func__);
@ -102,25 +123,26 @@ void UaBrowserObjectsTestTask(void* param)
UA_ClientConfig* config = UA_Client_getConfig(client);
UA_ClientConfig_setDefault(config);
UA_StatusCode retval = UA_Client_connect(client, opc_server_url);
UA_StatusCode ret = UA_Client_connect(client, opc_server_url);
if(retval != UA_STATUSCODE_GOOD)
if(ret != UA_STATUSCODE_GOOD)
{
ua_error("ua: [%s] connect failed %#x\n", __func__, retval);
ua_error("ua: [%s] connect failed %#x\n", __func__, ret);
UA_Client_delete(client);
return;
}
ua_notice("--- start read time ---\n", __func__);
ua_read_time(client);
UaGetServerTime(client);
ua_notice("--- get server info ---\n", __func__);
ua_test_browser_objects(client);
UaTestBrowserObjects(client);
/* Clean up */
UA_Client_delete(client); /* Disconnects the client internally */
}
void* UaBrowserObjectsTest(int argc, char* argv[])
static void* UaBrowserObjectsTest(int argc, char* argv[])
{
if(argc == 2)
{
@ -140,35 +162,33 @@ void* UaBrowserObjectsTest(int argc, char* argv[])
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3),
UaObj, UaBrowserObjectsTest, UaObj [IP]);
UaObject, UaBrowserObjectsTest, UaObject [IP]);
void UaGetInfoTestTask(void* param)
{
UA_Client* client = UA_Client_new();
ua_notice("ua: [%s] start ...\n", __func__);
ua_notice("--- Get OPUCA objects ---\n", __func__);
if(client == NULL)
{
ua_print("ua: [%s] tcp client null\n", __func__);
ua_error("ua: [%s] tcp client null\n", __func__);
return;
}
UA_ClientConfig* config = UA_Client_getConfig(client);
UA_ClientConfig_setDefault(config);
UA_StatusCode retval = UA_Client_connect(client, opc_server_url);
UA_StatusCode ret = UA_Client_connect(client, opc_server_url);
if(retval != UA_STATUSCODE_GOOD)
if(ret != UA_STATUSCODE_GOOD)
{
ua_print("ua: [%s] connect failed %#x\n", __func__, retval);
ua_error("ua: [%s] connect failed %#x\n", __func__, ret);
UA_Client_delete(client);
return;
}
ua_print("ua: [%s] connect ok!\n", __func__);
ua_notice("--- interactive server ---\n", __func__);
ua_test_interact_server(client);
/* Clean up */
UA_Client_disconnect(client);
UaTestInteractServer(client);
UA_Client_delete(client); /* Disconnects the client internally */
}
@ -201,26 +221,24 @@ void UaAddNodesTask(void* param)
if(client == NULL)
{
ua_print("ua: [%s] tcp client null\n", __func__);
ua_error("ua: [%s] client null\n", __func__);
return;
}
UA_ClientConfig* config = UA_Client_getConfig(client);
UA_ClientConfig_setDefault(config);
UA_StatusCode retval = UA_Client_connect(client, opc_server_url);
UA_StatusCode ret = UA_Client_connect(client, opc_server_url);
if(retval != UA_STATUSCODE_GOOD)
if(ret != UA_STATUSCODE_GOOD)
{
ua_print("ua: [%s] connect failed %#x\n", __func__, retval);
ua_print("ua: [%s] connect failed %#x\n", __func__, ret);
UA_Client_delete(client);
return;
}
ua_print("ua: [%s] connect ok!\n", __func__);
ua_notice("--- add nodes ---\n", __func__);
ua_add_nodes(client);
/* Clean up */
UA_Client_disconnect(client);
UaAddNodes(client);
UA_Client_delete(client); /* Disconnects the client internally */
}

265
APP_Framework/Applications/control_app/plc_demo/plc_control_demo.c
View File

@ -30,12 +30,49 @@ struct PlcChannel plc_demo_ch;
struct PlcDriver plc_demo_drv;
struct PlcDevice plc_demo_dev;
int plc_test_flag = 0;
PlcCtrlParamType plc_ctrl_param;
UA_NodeId test_nodeid = {4, UA_NODEIDTYPE_NUMERIC, 5};
/******************************************************************************/
void PlcDelay(int sec)
{
volatile uint32_t i = 0;
for (i = 0; i < 100000000 * sec; ++i)
{
__asm("NOP"); /* delay */
}
}
// get NodeId from str
void PlcGetTestNodeId(char *str, UA_NodeId *id)
{
static char node_str[UA_NODE_LEN];
memset(node_str, 0, sizeof(node_str));
plc_print("plc: arg %s\n", str);
if(sscanf(str, PLC_NS_FORMAT, &id->namespaceIndex, node_str) != EOF)
{
if(isdigit(node_str[0]))
{
id->identifierType = UA_NODEIDTYPE_NUMERIC;
id->identifier.numeric = atoi(node_str);
plc_print("ns %d num %d\n", id->namespaceIndex, id->identifier.numeric);
}
else
{
id->identifierType = UA_NODEIDTYPE_STRING;
id->identifier.string.length = strlen(node_str);
id->identifier.string.data = node_str;
plc_print("ns %d str %s\n", id->namespaceIndex, id->identifier.string.data);
}
}
}
void PlcDemoChannelDrvInit(void)
{
static uint8_t init_flag = 0;
@ -52,33 +89,42 @@ void PlcDemoChannelDrvInit(void)
memset(&plc_demo_dev, 0, sizeof(plc_demo_dev));
}
static void PlcGetDemoDev(PlcDeviceType *dev, UA_NodeId *id)
{
// register plc device
dev->state = CHDEV_INIT;
strcpy(dev->name, "UA Demo");
dev->info.product = "CPU 1215C";
dev->info.vendor = "SIEMENS";
dev->info.model = "S7-1200";
dev->info.id = 123;
dev->net = PLC_IND_ENET_OPCUA;
// register UA parameter
if(!dev->priv_data)
{
dev->priv_data = (UaParamType*)malloc(sizeof(UaParamType));
}
UaParamType* ua_ptr = dev->priv_data;
memset(ua_ptr, 0, sizeof(UaParamType));
strcpy(ua_ptr->ua_remote_ip, opc_server_url);
ua_ptr->act = UA_ACT_ATTR;
memcpy(&ua_ptr->ua_id, id, sizeof(*id));
}
static void PlcCtrlDemoInit(void)
{
static uint8_t init_flag = 0;
PlcDemoChannelDrvInit();
// register plc device
plc_demo_dev.state = CHDEV_INIT;
strcpy(plc_demo_dev.name, "UA Demo");
plc_demo_dev.info.product = "CPU 1215C";
plc_demo_dev.info.vendor = "SIEMENS";
plc_demo_dev.info.model = "S7-1200";
plc_demo_dev.info.id = 123;
plc_demo_dev.net = PLC_IND_ENET_OPCUA;
// register UA parameter
if(!plc_demo_dev.priv_data)
{
plc_demo_dev.priv_data = (UaParamType*)malloc(sizeof(UaParamType));
}
UaParamType* ua_ptr = plc_demo_dev.priv_data;
memset(ua_ptr, 0, sizeof(UaParamType));
strcpy(ua_ptr->ua_remote_ip, opc_server_url);
ua_ptr->act = UA_ACT_ATTR;
memcpy(&ua_ptr->ua_id, &test_nodeid, sizeof(test_nodeid));
// register plc device
PlcGetDemoDev(&plc_demo_dev, &test_nodeid);
if(init_flag)
{
return;
}
init_flag = 1;
if(PlcDevRegister(&plc_demo_dev, NULL, plc_demo_dev.name) != EOK)
@ -114,38 +160,21 @@ void PlcReadUATask(void* arg)
ops->close(&plc_demo_dev);
}
void PlcReadTest(int argc, char* argv[])
void PlcReadTestShell(int argc, char* argv[])
{
static char node_str[UA_NODE_LEN];
memset(node_str, 0, sizeof(node_str));
if(argc > 1)
{
plc_print("plc: arg %s\n", argv[1]);
if(sscanf(argv[1], PLC_NS_FORMAT, &test_nodeid.namespaceIndex, node_str) != EOF)
{
if(isdigit(node_str[0]))
{
test_nodeid.identifierType = UA_NODEIDTYPE_NUMERIC;
test_nodeid.identifier.numeric = atoi(node_str);
plc_print("ns %d num %d\n", test_nodeid.namespaceIndex, test_nodeid.identifier.numeric);
}
else
{
test_nodeid.identifierType = UA_NODEIDTYPE_STRING;
test_nodeid.identifier.string.length = strlen(node_str);
test_nodeid.identifier.string.data = node_str;
plc_print("ns %d str %s\n", test_nodeid.namespaceIndex, test_nodeid.identifier.string.data);
}
}
PlcGetTestNodeId(argv[1], &test_nodeid);
}
sys_thread_new("plc read", PlcReadUATask, NULL, PLC_STACK_SIZE, PLC_TASK_PRIO);
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3),
PlcRead, PlcReadTest, Read PLC);
PlcRead, PlcReadTestShell, Read PLC);
void PlcWriteUATask(void* arg)
{
@ -168,13 +197,13 @@ void PlcWriteUATask(void* arg)
if(EOK != ret)
{
plc_print("plc: [%s] read failed\n", __func__);
plc_print("plc: [%s] write failed\n", __func__);
}
ops->close(&plc_demo_dev);
}
void PlcWriteTest(int argc, char* argv[])
void PlcWriteTestShell(int argc, char* argv[])
{
static char node_str[UA_NODE_LEN];
static char val_param[UA_NODE_LEN];
@ -183,35 +212,143 @@ void PlcWriteTest(int argc, char* argv[])
if(argc > 1)
{
plc_print("plc: arg %s\n", argv[1]);
PlcGetTestNodeId(argv[1], &test_nodeid);
}
if(sscanf(argv[1], PLC_NS_FORMAT, &test_nodeid.namespaceIndex, node_str) != EOF)
{
if(isdigit(node_str[0]))
{
test_nodeid.identifierType = UA_NODEIDTYPE_NUMERIC;
test_nodeid.identifier.numeric = atoi(node_str);
plc_print("ns %d num %d\n", test_nodeid.namespaceIndex, test_nodeid.identifier.numeric);
}
else
{
test_nodeid.identifierType = UA_NODEIDTYPE_STRING;
test_nodeid.identifier.string.length = strlen(node_str);
test_nodeid.identifier.string.data = node_str;
plc_print("ns %d str %s\n", test_nodeid.namespaceIndex, test_nodeid.identifier.string.data);
}
}
if(argc > 2)
{
strcpy(val_param, argv[2]);
plc_print("write value %s\n", val_param);
}
if(argc > 2)
{
strcpy(val_param, argv[2]);
plc_print("write value %s\n", val_param);
}
sys_thread_new("plc write", PlcWriteUATask, val_param, PLC_STACK_SIZE, PLC_TASK_PRIO);
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3),
PlcWrite, PlcWriteTest, Read PLC);
PlcWrite, PlcWriteTestShell, Read PLC);
// test motor
// clear parameter
// PlcWrite n4,2 0b
// PlcWrite n4,3 0b
// PlcWrite n4,4 0b
// PlcWrite n4,5 0b
//
// enable
// PlcWrite n4,2 1b
//
// set rotate speed
// PlcWrite n4,3 50
//
// positive turn
// PlcWrite n4,4 1b
//
// reversal turn
// PlcWrite n4,5 1b
static int plc_test_speed = 50;
static int plc_test_dir = 1; // direction positive: 1 reversal: 0
void PlcMotorTestTask(void* arg)
{
//support node id
char *test_nodeid[] = {"n4,2", "n4,3", "n4,4", "n4,5", "n4,7"};
// enable -> speed -> positive dir or inversal dir -> stop -> enable
char test_sort[] = {0, 4, 2, 1, 0};
char test_cmd[][4] = {"1b", "50", "1b", "1b", "0b"};
char *test_notice[] = {"Enable Motor", "Set Speed", "Set Forward", "Set Reverse", "Stop Motor"};
int ret = 0;
struct PlcOps* ops = NULL;
char buf[PLC_BUF_SIZE];
memset(buf, 0, sizeof(buf));
PlcCtrlDemoInit();
ops = plc_demo_dev.ops;
ret = ops->open(&plc_demo_dev);
if(EOK != ret)
{
plc_print("plc: [%s] open failed %#x\n", __func__, ret);
return;
}
UaParamType* ua_ptr = plc_demo_dev.priv_data;
// initialize step
for(int i = 0; i < 5; i++)
{
plc_print("###\n### Clear %s\n###\n", test_notice[i]);
PlcGetTestNodeId(test_nodeid[i], &ua_ptr->ua_id);
ret = ops->write(&plc_demo_dev, "0b", PLC_BUF_SIZE);
if(EOK != ret)
{
plc_print("plc: [%s] %d write failed\n", __func__, __LINE__);
}
PlcDelay(1);
}
if(plc_test_speed != 50)
{
snprintf(test_cmd[1], 4, "%d", plc_test_speed);
}
if(plc_test_dir == 0) // if not postive, next running
test_sort[2] = 3;
for(int i = 0; i < sizeof(test_sort)/sizeof(test_sort[0]); i++)
{
PlcGetTestNodeId(test_nodeid[test_sort[i]], &ua_ptr->ua_id);
plc_print("###\n### %s\n###\n", test_notice[i]);
ret = ops->write(&plc_demo_dev, test_cmd[i], PLC_BUF_SIZE);
if(EOK != ret)
{
plc_print("plc: [%s] %d write failed\n", __func__, __LINE__);
}
PlcDelay(1);
if(i == 2) // postive
{
PlcDelay(10);
}
}
ops->close(&plc_demo_dev);
plc_test_flag = 0;
}
// get parameter from
void PlcGetMotorParam(char *str)
{
static char node_str[UA_NODE_LEN];
memset(node_str, 0, sizeof(node_str));
plc_print("plc: arg %s\n", str);
sscanf(str, "speed=%d", &plc_test_speed);
sscanf(str, "dir=%d", &plc_test_dir);
plc_print("speed is %d\n", plc_test_speed);
plc_print("dir is %d\n", plc_test_dir);
}
void PlcMotorTestShell(int argc, char* argv[])
{
if(plc_test_flag)
{
plc_print("PLC Motor testing!\n");
return;
}
plc_test_flag = 1;
if(argc > 1)
{
for(int i = 0; i < argc; i++)
{
PlcGetMotorParam(argv[i]);
}
}
sys_thread_new("plc motor", PlcMotorTestTask, NULL, PLC_STACK_SIZE, PLC_TASK_PRIO);
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3),
PlcMotorTest, PlcMotorTestShell, Run motor);

2
APP_Framework/Applications/sensor_app/pm10_0_ps5308.c
View File

@ -11,7 +11,7 @@
*/
/**
* @filepm10_0_ps5308
* @file pm10_0_ps5308.c
* @brief PS5308 PM10.0 example
* @version 1.0
* @author AIIT XUOS Lab

2
APP_Framework/Applications/sensor_app/pm2_5_ps5308.c
View File

@ -11,7 +11,7 @@
*/
/**
* @file pm2_5_ps5308
* @file pm2_5_ps5308.c
* @brief PS5308 PM2.5 example
* @version 1.0
* @author AIIT XUOS Lab

6
APP_Framework/Framework/connection/Kconfig
View File

@ -62,12 +62,6 @@ if SUPPORT_CONNECTION_FRAMEWORK
default n
if CONNECTION_ADAPTER_ETHERNET
source "$APP_DIR/Framework/connection/ethernet/Kconfig"
config CONNECTION_ADAPTER_ETHERCAT
bool "Using ethercat on ethernet adapter device"
default n
if CONNECTION_ADAPTER_ETHERCAT
source "$APP_DIR/Framework/connection/ethercat/Kconfig"
endif
endif
menuconfig CONNECTION_ADAPTER_BLUETOOTH

4
APP_Framework/Framework/connection/Makefile
View File

@ -41,10 +41,6 @@ ifeq ($(CONFIG_ADD_XIZI_FETURES),y)
SRC_DIR += ethernet
endif
ifeq ($(CONFIG_CONNECTION_ADAPTER_ETHERCAT),y)
SRC_DIR += ethercat
endif
ifeq ($(CONFIG_CONNECTION_ADAPTER_BLUETOOTH),y)
SRC_DIR += bluetooth
endif

7
APP_Framework/Framework/connection/industrial_ethernet/Kconfig
View File

@ -0,0 +1,7 @@
config CONNECTION_ADAPTER_ETHERCAT
bool "Using ethercat on industrial_ethernet adapter device"
default n
if CONNECTION_ADAPTER_ETHERCAT
source "$APP_DIR/Framework/connection/industrial_ethernet/ethercat/Kconfig"
endif

3
APP_Framework/Framework/connection/industrial_ethernet/Makefile
View File

@ -1,2 +1,5 @@
ifeq ($(CONFIG_CONNECTION_ADAPTER_ETHERCAT),y)
SRC_DIR += ethercat
endif
include $(KERNEL_ROOT)/compiler.mk

7
APP_Framework/Framework/connection/ethercat/Kconfig → APP_Framework/Framework/connection/industrial_ethernet/ethercat/Kconfig
View File

@ -5,6 +5,7 @@ config ADAPTER_HFA21_ETHERCAT
bool "Using ethercat on ethernet adapter device HFA21"
default n
if ADAPTER_HFA21_ETHERCAT
source "$APP_DIR/Framework/connection/ethercat/hfa21_ethercat/Kconfig"
endif
if ADAPTER_HFA21_ETHERCAT
source "$APP_DIR/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/Kconfig"
endif

0
APP_Framework/Framework/connection/ethercat/Makefile → APP_Framework/Framework/connection/industrial_ethernet/ethercat/Makefile
View File

0
APP_Framework/Framework/connection/ethercat/adapter_ethercat.c → APP_Framework/Framework/connection/industrial_ethernet/ethercat/adapter_ethercat.c
View File

0
APP_Framework/Framework/connection/ethercat/ethercat.h → APP_Framework/Framework/connection/industrial_ethernet/ethercat/ethercat.h
View File

0
APP_Framework/Framework/connection/ethercat/hfa21_ethercat/Kconfig → APP_Framework/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/Kconfig
View File

0
APP_Framework/Framework/connection/ethercat/hfa21_ethercat/Makefile → APP_Framework/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/Makefile
View File

0
APP_Framework/Framework/connection/ethercat/hfa21_ethercat/hfa21_ethercat.c → APP_Framework/Framework/connection/industrial_ethernet/ethercat/hfa21_ethercat/hfa21_ethercat.c
View File

217
APP_Framework/Framework/control/plc/interoperability/opcua/open62541.c
View File

@ -23,6 +23,19 @@
* @date 2021.12.15
*/
/*************************************************
File name: open62541.c
Description: Support OPCUA protocol
Others: take https://github.com/open62541/open62541.git
History:
1. Date: 2021-12-15
Author: AIIT XUOS Lab
Modification:
1. added debug information for locate
2. avoid calling client NEW at same time
3. fixed the bug of free twice when receiveResponse timeout
*************************************************/
#ifndef UA_DYNAMIC_LINKING_EXPORT
# define UA_DYNAMIC_LINKING_EXPORT
# define MDNSD_DYNAMIC_LINKING
@ -36,6 +49,8 @@
#include "open62541.h"
#include "ua_api.h"
int ua_run_flag = 0;
#if LWIP_DNS
#else
@ -7482,10 +7497,6 @@ Array_encodeBinary(const void *src, size_t length, const UA_DataType *type, Ctx
}
UA_assert(ret != UA_STATUSCODE_BADENCODINGLIMITSEXCEEDED);
//tst by wly
ua_debug("ua: [%s] src %p len %d %d type %p <%d> <%d> %p ret %d\n", __func__,
src, length, signed_length, *type, type->typeKind, type->overlayable, ctx, ret);
return ret;
}
@ -8330,24 +8341,9 @@ encodeBinaryStruct(const void *src, const UA_DataType *type, Ctx *ctx) {
if(mt->typeKind > UA_DATATYPEKINDS)
{
ua_debug("ua: [%s] %d type %d %p ptr %p failed\n", __func__, i, mt->typeKind, m->memberType, ptr);
return ret;
}
ua_debug("ua: [%s] > %d < %d mt %p %d %d dep %d msg %p %p:<%x> <%d> isArry %d ret %d\n", __func__,
i,
type->membersSize,
mt,
mt->typeKind,
mt->memSize,
ctx->depth,
ptr,
src,
((UA_TcpMessageHeader *)src)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)src)->messageSize,
m->isArray,
ret);
/* Array. Buffer-exchange is done inside Array_encodeBinary if required. */
if(m->isArray) {
const size_t length = *((const size_t*)ptr);
@ -8362,20 +8358,6 @@ encodeBinaryStruct(const void *src, const UA_DataType *type, Ctx *ctx) {
ret = encodeWithExchangeBuffer((const void*)ptr, mt, ctx);
UA_assert(ret != UA_STATUSCODE_BADENCODINGLIMITSEXCEEDED);
ua_debug("ua: [%s] >> %d < %d mt %p %d %d dep %d msg %p %p:<%x> <%d> isArry %d ret %d\n", __func__,
i,
type->membersSize,
mt,
mt->typeKind,
mt->memSize,
ctx->depth,
ptr,
src,
((UA_TcpMessageHeader *)src)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)src)->messageSize,
m->isArray,
ret);
ptr += mt->memSize;
}
@ -8614,68 +8596,23 @@ decodeBinaryStructure(void *dst, const UA_DataType *type, Ctx *ctx) {
if(mt->typeKind >= UA_DATATYPEKINDS)
{
ua_debug("ua: [%s] fail %d < %d mt %p %d %d dep %d msg %p %p:<%x> <%d>\n", __func__,
i,
membersSize,
mt,
mt->typeKind,
mt->memSize,
ctx->depth,
ptr,
dst,
((UA_TcpMessageHeader *)dst)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)dst)->messageSize);
return ret;
}
ua_debug("ua: [%s] > %d < %d mt %p %d %d dep %d msg %p %p:<%x> <%d> isArry %d ret %d\n", __func__,
i,
membersSize,
mt,
mt->typeKind,
mt->memSize,
ctx->depth,
ptr,
dst,
((UA_TcpMessageHeader *)dst)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)dst)->messageSize,
m->isArray,
ret);
/* Array */
if(m->isArray) {
size_t *length = (size_t*)ptr;
ptr += sizeof(size_t);
ret = Array_decodeBinary((void *UA_RESTRICT *UA_RESTRICT)ptr, length, mt , ctx);
ptr += sizeof(void*);
ua_debug("ua: [%s] %d ret %d ptr %p len %d\n", __func__, i, ret, ptr, length);
continue;
}
/* Scalar */
ret = decodeBinaryJumpTable[mt->typeKind]((void *UA_RESTRICT)ptr, mt, ctx);
ptr += mt->memSize;
ua_debug("ua: [%s] >> %d < %d dep %d msg %p %p:<%x> <%d> ret %d\n", __func__,
i,
membersSize,
ctx->depth,
ptr,
dst,
((UA_TcpMessageHeader *)dst)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)dst)->messageSize,
ret);
}
ua_debug("ua: [%s] >>> dep %d msg %p %p:<%x> <%d> ret %d\n", __func__,
ctx->depth,
ptr,
dst,
((UA_TcpMessageHeader *)dst)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)dst)->messageSize,
ret);
ctx->depth--;
return ret;
}
@ -8818,17 +8755,8 @@ UA_decodeBinaryInternal(const UA_ByteString *src, size_t *offset,
/* Decode */
memset(dst, 0, type->memSize); /* Initialize the value */
ua_debug("ua: [%s] t %d mem %d len %d off %d pos %d end %d dst %p type %x size %x\n", __func__,
type->typeKind, type->memSize, src->length, *offset, *ctx.pos, *ctx.end,
dst, ((UA_TcpMessageHeader *)dst)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)dst)->messageSize);
status ret = decodeBinaryJumpTable[type->typeKind](dst, type, &ctx);
ua_debug("ua: [%s] -> t %d dst %p type %x size %x ret %d\n", __func__,
type->typeKind, dst, ((UA_TcpMessageHeader *)dst)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)dst)->messageSize, ret);
if(UA_LIKELY(ret == UA_STATUSCODE_GOOD)) {
/* Set the new offset */
*offset = (size_t)(ctx.pos - src->data) / sizeof(u8);
@ -8836,16 +8764,8 @@ UA_decodeBinaryInternal(const UA_ByteString *src, size_t *offset,
/* Clean up */
UA_clear(dst, type);
memset(dst, 0, type->memSize);
ua_debug("ua: [%s] => t %d dst %p type %x size %x\n", __func__,
type->typeKind, dst, ((UA_TcpMessageHeader *)dst)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)dst)->messageSize);
}
ua_debug("ua: [%s] #> off %d %p %p t %d dst %p type %x size %x\n", __func__, *offset,
ctx.pos, src->data,
type->typeKind, dst, ((UA_TcpMessageHeader *)dst)->messageTypeAndChunkType,
((UA_TcpMessageHeader *)dst)->messageSize);
return ret;
}
@ -17969,6 +17889,11 @@ UA_SecureChannel_close(UA_SecureChannel *channel) {
/* Set the status to closed */
channel->state = UA_SECURECHANNELSTATE_CLOSED;
if(channel->connection == 0)
{
ua_error("ua: [%s] conn null return!\n", __func__);
return;
}
/* Detach from the connection and close the connection */
if(channel->connection) {
if(channel->connection->state != UA_CONNECTIONSTATE_CLOSED)
@ -18613,12 +18538,6 @@ processChunks(UA_SecureChannel *channel, void *application,
channel->decryptedChunksCount > channel->config.localMaxChunkCount) ||
(channel->config.localMaxMessageSize != 0 &&
channel->decryptedChunksLength > channel->config.localMaxMessageSize)) {
ua_print("ua: [%s] count %d max %d len %d mess %d\n",
channel->decryptedChunksCount,
channel->config.localMaxChunkCount,
channel->decryptedChunksLength,
channel->config.localMaxMessageSize
);
return UA_STATUSCODE_BADTCPMESSAGETOOLARGE;
}
@ -18656,9 +18575,6 @@ extractCompleteChunk(UA_SecureChannel *channel, const UA_ByteString *buffer,
UA_decodeBinaryInternal(buffer, &initial_offset, &hdr,
&UA_TRANSPORT[UA_TRANSPORT_TCPMESSAGEHEADER], NULL);
ua_debug("ua: [%s] res %d buf %p offset %d hdr %d size %d\n", __func__, res, buffer, *offset,
hdr.messageTypeAndChunkType, hdr.messageSize);
UA_assert(res == UA_STATUSCODE_GOOD);
(void)res; /* pacify compilers if assert is ignored */
UA_MessageType msgType = (UA_MessageType)
@ -18671,7 +18587,6 @@ extractCompleteChunk(UA_SecureChannel *channel, const UA_ByteString *buffer,
return UA_STATUSCODE_BADTCPMESSAGETYPEINVALID;
if(hdr.messageSize > channel->config.recvBufferSize)
{
ua_debug("lw: [%s] msg size %d rec %d\n", __func__, hdr.messageSize, channel->config.recvBufferSize);
return UA_STATUSCODE_BADTCPMESSAGETOOLARGE;
}
@ -43657,6 +43572,8 @@ UA_Client_delete(UA_Client* client) {
UA_Client_clear(client);
UA_ClientConfig_clear(&client->config);
UA_free(client);
client = NULL;
ua_run_flag = 0;
}
void
@ -43976,7 +43893,7 @@ receiveResponse(UA_Client *client, void *response, const UA_DataType *responseTy
"Receiving the response failed with StatusCode %s",
UA_StatusCode_name(retval));
ua_print("ua: [%s] state %d ret %d %#x\n", __func__, client->channel.state, retval, retval);
closeSecureChannel(client);
// closeSecureChannel(client);
retval = UA_STATUSCODE_BADCONNECTIONCLOSED;
break;
}
@ -44244,7 +44161,7 @@ UA_Client_run_iterate(UA_Client *client, UA_UInt32 timeout) {
client->sessionState < UA_SESSIONSTATE_ACTIVATED) {
retval = connectIterate(client, timeout);
notifyClientState(client);
ua_print("lw: [%s] ret %d timeout %d state %d ch %d\n", __func__, retval, timeout,
ua_print("lw: [%s] ret %x timeout %d state %d ch %d\n", __func__, retval, timeout,
client->sessionState, client->channel.state);
return retval;
}
@ -45187,9 +45104,6 @@ connectIterate(UA_Client *client, UA_UInt32 timeout) {
return UA_STATUSCODE_BADCONNECTIONCLOSED;
}
ua_debug("ua: [%s] conn %d state %d handle %p\n", __func__, client->connectStatus,
client->connection.state, client->connection.handle);
/* The connection is closed. Reset the SecureChannel and open a new TCP
* connection */
if(client->connection.state == UA_CONNECTIONSTATE_CLOSED)
@ -45200,11 +45114,6 @@ connectIterate(UA_Client *client, UA_UInt32 timeout) {
client->connectStatus =
client->config.pollConnectionFunc(&client->connection, timeout,
&client->config.logger);
ua_debug("ua: [%s] exit conn %x %d time %d handle %p\n", __func__,
client->connectStatus,
client->connection.state, timeout, client->connection.handle);
return client->connectStatus;
}
@ -45399,8 +45308,6 @@ connectSync(UA_Client *client) {
UA_DateTime now = UA_DateTime_nowMonotonic();
UA_DateTime maxDate = now + ((UA_DateTime)client->config.timeout * UA_DATETIME_MSEC);
ua_print("ua; [%s] time %d\n", __func__, (UA_DateTime)client->config.timeout);
UA_StatusCode retval = initConnect(client);
if(retval != UA_STATUSCODE_GOOD)
return retval;
@ -70300,16 +70207,30 @@ UA_ServerConfig_setDefaultWithSecurityPolicies(UA_ServerConfig *conf,
UA_Client * UA_Client_new() {
UA_ClientConfig config;
UA_Client *ret = NULL;
if(ua_run_flag)
{
return NULL;
}
memset(&config, 0, sizeof(UA_ClientConfig));
config.logger.log = UA_Log_Stdout_log;
config.logger.context = NULL;
config.logger.clear = UA_Log_Stdout_clear;
return UA_Client_newWithConfig(&config);
ret = UA_Client_newWithConfig(&config);
if(ret)
{
ua_run_flag = 1;
}
return ret;
}
UA_StatusCode
UA_ClientConfig_setDefault(UA_ClientConfig *config) {
config->timeout = 20000;
config->timeout = 5000;
config->secureChannelLifeTime = 10 * 60 * 1000; /* 10 minutes */
if(!config->logger.log) {
@ -71205,7 +71126,6 @@ ServerNetworkLayerTCP_add(UA_ServerNetworkLayer *nl, ServerNetworkLayerTCP *laye
static UA_StatusCode
addServerSocket(ServerNetworkLayerTCP *layer, struct addrinfo *ai) {
/* Create the server socket */
ua_print("ua: [%s] %d %d %d\n", __func__, ai->ai_family, ai->ai_socktype, ai->ai_protocol);
UA_SOCKET newsock = UA_socket(ai->ai_family, ai->ai_socktype, ai->ai_protocol);
if(newsock == UA_INVALID_SOCKET)
{
@ -71341,18 +71261,12 @@ ServerNetworkLayerTCP_start(UA_ServerNetworkLayer *nl, const UA_Logger *logger,
int retcode = UA_getaddrinfo(customHostname->length ? hostname : NULL,
portno, &hints, &res);
ua_print("ua: [%s] host %s pro %d ret %d\n", __func__, hostname, portno, retcode);
if(retcode != 0) {
UA_LOG_SOCKET_ERRNO_GAI_WRAP(UA_LOG_WARNING(layer->logger, UA_LOGCATEGORY_NETWORK,
"getaddrinfo lookup of %s failed with error %d - %s", hostname, retcode, errno_str));
return UA_STATUSCODE_BADINTERNALERROR;
}
ua_print("ua: [%s] res %p fam %d len %d %s\n", __func__, res, res->ai_family,
customHostname->length,
customHostname->data);
/* There might be serveral addrinfos (for different network cards,
* IPv4/IPv6). Add a server socket for all of them. */
struct addrinfo *ai = res;
@ -71597,6 +71511,12 @@ typedef struct TCPClientConnection {
static void
ClientNetworkLayerTCP_close(UA_Connection *connection) {
if(connection == NULL)
{
ua_error("connection NULL!\n");
return;
}
if(connection->state == UA_CONNECTIONSTATE_CLOSED)
return;
@ -71637,10 +71557,6 @@ UA_ClientConnectionTCP_poll(UA_Connection *connection, UA_UInt32 timeout,
return UA_STATUSCODE_BADDISCONNECT;
}
ua_print("ua: [%s] conn handle %p fam %d sa %d\n", __func__,
connection->handle, tcpConnection->server->ai_family,
tcpConnection->server->ai_addr->sa_family);
/* Get a socket and connect (only once) if not already done in a previous
* call. On win32, calling connect multiple times is not recommended on
* non-blocking sockets
@ -71651,27 +71567,17 @@ UA_ClientConnectionTCP_poll(UA_Connection *connection, UA_UInt32 timeout,
* and getsockopt using SO_ERROR on win32 and posix.
*/
if(connection->sockfd == UA_INVALID_SOCKET) {
ua_print("ua: [%s] start socket %p ai %d sa %d\n", __func__,
tcpConnection->server,
tcpConnection->server->ai_family,
tcpConnection->server->ai_addr->sa_family);
connection->sockfd = UA_socket(tcpConnection->server->ai_family,
tcpConnection->server->ai_socktype,
tcpConnection->server->ai_protocol);
if(connection->sockfd == UA_INVALID_SOCKET) {
ua_print("ua: [%s] %s\n", __func__, strerror(UA_ERRNO));
UA_LOG_WARNING(logger, UA_LOGCATEGORY_NETWORK,
"Could not create client socket: %s", strerror(UA_ERRNO));
ClientNetworkLayerTCP_close(connection);
return UA_STATUSCODE_BADDISCONNECT;
}
ua_print("ua: [%s] socket fd %d %p fam %d sa %d\n", __func__,
connection->sockfd,
tcpConnection->server,
tcpConnection->server->ai_family,
tcpConnection->server->ai_addr->sa_family);
/* Non blocking connect to be able to timeout */
if(UA_socket_set_nonblocking(connection->sockfd) != UA_STATUSCODE_GOOD) {
UA_LOG_WARNING(logger, UA_LOGCATEGORY_NETWORK,
@ -71680,11 +71586,6 @@ UA_ClientConnectionTCP_poll(UA_Connection *connection, UA_UInt32 timeout,
return UA_STATUSCODE_BADDISCONNECT;
}
ua_print("ua: [%s] check fd %d %p fam %d sa %d\n", __func__,
connection->sockfd,
tcpConnection->server,
tcpConnection->server->ai_family,
tcpConnection->server->ai_addr->sa_family);
/* Don't have the socket create interrupt signals */
#ifdef SO_NOSIGPIPE
int val = 1;
@ -71693,12 +71594,6 @@ UA_ClientConnectionTCP_poll(UA_Connection *connection, UA_UInt32 timeout,
if(sso_result < 0)
UA_LOG_WARNING(logger, UA_LOGCATEGORY_NETWORK, "Couldn't set SO_NOSIGPIPE");
#endif
ua_print("ua: [%s] connect ai %d sa fam %d len %d %x addr len %d\n", __func__,
tcpConnection->server->ai_family,
tcpConnection->server->ai_addr->sa_family,
tcpConnection->server->ai_addr->sa_len,
tcpConnection->server->ai_addr->sa_data[0],
tcpConnection->server->ai_addrlen);
int error = UA_connect(connection->sockfd, tcpConnection->server->ai_addr,
tcpConnection->server->ai_addrlen);
@ -71708,7 +71603,6 @@ UA_ClientConnectionTCP_poll(UA_Connection *connection, UA_UInt32 timeout,
connection->state = UA_CONNECTIONSTATE_ESTABLISHED;
return UA_STATUSCODE_GOOD;
}
ua_print("ua: [%s] connected failed %d\n", __func__, error);
/* The connection failed */
if((UA_ERRNO != UA_ERR_CONNECTION_PROGRESS)) {
@ -71772,6 +71666,7 @@ UA_ClientConnectionTCP_poll(UA_Connection *connection, UA_UInt32 timeout,
(int)tcpConnection->endpointUrl.length,
tcpConnection->endpointUrl.data, strerror(UA_ERRNO));
ClientNetworkLayerTCP_close(connection);
ua_error("ua: [%s] line %d failed\n", __func__, __LINE__);
return UA_STATUSCODE_BADDISCONNECT;
}
@ -71802,6 +71697,7 @@ UA_ClientConnectionTCP_poll(UA_Connection *connection, UA_UInt32 timeout,
LocalFree(errno_str);
#endif
ClientNetworkLayerTCP_close(connection);
ua_error("ua: [%s] line %d failed\n", __func__, __LINE__);
return UA_STATUSCODE_BADDISCONNECT;
}
@ -71831,14 +71727,11 @@ UA_ClientConnectionTCP_init(UA_ConnectionConfig config, const UA_String endpoint
connection.releaseSendBuffer = connection_releasesendbuffer;
connection.releaseRecvBuffer = connection_releaserecvbuffer;
ua_print("ua: [%s] endpoint url (%d)%.28s %d\n", __func__, endpointUrl.length, endpointUrl.data,
sizeof(TCPClientConnection));
TCPClientConnection *tcpClientConnection = (TCPClientConnection*)
UA_malloc(sizeof(TCPClientConnection));
if(!tcpClientConnection) {
connection.state = UA_CONNECTIONSTATE_CLOSED;
ua_print("ua: [%s] malloc %d failed\n", __func__, sizeof(TCPClientConnection));
ua_error("ua: [%s] malloc %d failed\n", __func__, sizeof(TCPClientConnection));
return connection;
}
memset(tcpClientConnection, 0, sizeof(TCPClientConnection));
@ -71850,8 +71743,6 @@ UA_ClientConnectionTCP_init(UA_ConnectionConfig config, const UA_String endpoint
char hostname[512];
tcpClientConnection->connStart = UA_DateTime_nowMonotonic();
ua_print("ua: [%s] line %d!\n", __func__, __LINE__);
UA_String_copy(&endpointUrl, &tcpClientConnection->endpointUrl);
UA_StatusCode parse_retval =
@ -71864,8 +71755,6 @@ UA_ClientConnectionTCP_init(UA_ConnectionConfig config, const UA_String endpoint
return connection;
}
ua_print("ua: [%s] line %d!\n", __func__, __LINE__);
memcpy(hostname, hostnameString.data, hostnameString.length);
hostname[hostnameString.length] = 0;
@ -71875,22 +71764,16 @@ UA_ClientConnectionTCP_init(UA_ConnectionConfig config, const UA_String endpoint
"No port defined, using default port %" PRIu16, port);
}
ua_print("ua: [%s] line %d!\n", __func__, __LINE__);
memset(&tcpClientConnection->hints, 0, sizeof(tcpClientConnection->hints));
tcpClientConnection->hints.ai_family = AF_UNSPEC;
tcpClientConnection->hints.ai_socktype = SOCK_STREAM;
char portStr[6];
UA_snprintf(portStr, 6, "%d", port);
// ua_print("ua: [%s] host %s port %s fam %d\n", __func__, hostname, portStr,
// tcpClientConnection->server->ai_addr->sa_family);
#if LWIP_DNS
int error = UA_getaddrinfo(hostname, portStr, &tcpClientConnection->hints,
&tcpClientConnection->server);
if(error != 0 || !tcpClientConnection->server) {
ua_print("ua: [%s] host %s error %d\n", __func__, hostname, error);
UA_LOG_SOCKET_ERRNO_GAI_WRAP(UA_LOG_WARNING(logger, UA_LOGCATEGORY_NETWORK,
"DNS lookup of %s failed with error %d - %s",
hostname, error, errno_str));

23
APP_Framework/Framework/control/plc/interoperability/opcua/ua_api.c
View File

@ -22,7 +22,7 @@
#include <stdlib.h>
#include "ua_api.h"
int ua_open(void *dev)
int UaDevOpen(void *dev)
{
UaParamType *param = (UaParamType *)dev;
@ -32,7 +32,7 @@ int ua_open(void *dev)
if (param->client == NULL)
{
ua_print("ua: [%s] tcp client null\n", __func__);
ua_error("ua: [%s] tcp client null\n", __func__);
return EEMPTY;
}
@ -43,28 +43,29 @@ int ua_open(void *dev)
UA_StatusCode retval = UA_Client_connect(param->client, param->ua_remote_ip);
if(retval != UA_STATUSCODE_GOOD) {
ua_notice("ua: [%s] deleted ret %x!\n", __func__, retval);
ua_error("ua: [%s] deleted ret %x!\n", __func__, retval);
return (int)retval;
}
return EOK;
}
void ua_close(void *dev)
void UaDevClose(void *dev)
{
UaParamType *param = (UaParamType *)dev;
ua_notice("ua: [%s] close %s!\n", __func__, param->ua_remote_ip);
UA_Client_delete(param->client); /* Disconnects the client internally */
}
int ua_read(void *dev, void *buf, size_t len)
int UaDevRead(void *dev, void *buf, size_t len)
{
UaParamType *param = (UaParamType *)dev;
switch(param->act)
{
case UA_ACT_ATTR:
ua_read_nodeid_value(param->client, param->ua_id, buf);
UaReadNodeValue(param->client, param->ua_id, buf);
break;
case UA_ACT_OBJ:
ua_test_browser_objects(param->client);
UaTestBrowserObjects(param->client);
break;
default:
break;
@ -72,17 +73,17 @@ int ua_read(void *dev, void *buf, size_t len)
return EOK;
}
int ua_write(void *dev, const void *buf, size_t len)
int UaDevWrite(void *dev, const void *buf, size_t len)
{
UaParamType *param = (UaParamType *)dev;
switch(param->act)
{
case UA_ACT_ATTR:
ua_write_nodeid_value(param->client, param->ua_id, (char *)buf);
UaWriteNodeValue(param->client, param->ua_id, (char *)buf);
break;
case UA_ACT_OBJ:
ua_test_browser_objects(param->client);
UaTestBrowserObjects(param->client);
break;
default:
break;
@ -90,7 +91,7 @@ int ua_write(void *dev, const void *buf, size_t len)
return EOK;
}
int ua_ioctl(void *dev, int cmd, void *arg)
int UaDevIoctl(void *dev, int cmd, void *arg)
{
return EOK;
}

37
APP_Framework/Framework/control/plc/interoperability/opcua/ua_api.h
View File

@ -42,32 +42,31 @@ typedef struct UaParam
}UaParamType;
#define ua_print //KPrintf
#define ua_trace() //KPrintf("ua: [%s] line %d checked!\n", __func__, __LINE__)
#define ua_notice KPrintf
#define ua_debug //KPrintf
#define ua_error KPrintf
extern const char *opc_server_url;
extern char test_ua_ip[];
int ua_server_connect(void);
void ua_browser_nodes(UA_Client *client);
void ua_browser_id(UA_Client *client, UA_NodeId id);
void ua_read_time(UA_Client *client);
void ua_add_nodes(UA_Client *client);
int UaServerRun(void);
void UaBrowserNodes(UA_Client *client);
void UaBrowserNodeId(UA_Client *client, UA_NodeId id);
void UaGetServerTime(UA_Client *client);
void UaAddNodes(UA_Client *client);
int ua_open(void *dev); // open and connect PLC device
void ua_close(void* dev); // close and disconnect PLC device
int ua_read(void* dev, void *buf, size_t len); // read data from PLC
int ua_write(void* dev, const void *buf, size_t len); // write data from PLC
int ua_ioctl(void* dev, int cmd, void *arg); // send control command to PLC
int UaDevOpen(void *dev); // open and connect PLC device
void UaDevClose(void* dev); // close and disconnect PLC device
int UaDevRead(void* dev, void *buf, size_t len); // read data from PLC
int UaDevWrite(void* dev, const void *buf, size_t len); // write data from PLC
int UaDevIoctl(void* dev, int cmd, void *arg); // send control command to PLC
char *ua_get_nodeid_str(UA_NodeId *node_id);
void ua_read_nodeid_value(UA_Client *client, UA_NodeId id, UA_Int32 *value);
void ua_write_nodeid_value(UA_Client *client, UA_NodeId id, char* value);
void ua_test_attr(UA_Client *client);
UA_StatusCode ua_read_array_value(UA_Client *client, int array_size, UA_ReadValueId *array);
void ua_test_browser_objects(UA_Client *client);
int ua_test_interact_server(UA_Client *client);
char *UaGetNodeIdString(UA_NodeId *node_id);
void UaReadNodeValue(UA_Client *client, UA_NodeId id, UA_Int32 *value);
void UaWriteNodeValue(UA_Client *client, UA_NodeId id, char* value);
UA_StatusCode UaReadArrayValue(UA_Client *client, int array_size, UA_ReadValueId *array);
int UaGetNodeIdArray(UA_Client* client, UA_NodeId id, int array_size, int *id_array);
void UaTestBrowserObjects(UA_Client *client);
int UaTestInteractServer(UA_Client *client);
#endif

138
APP_Framework/Framework/control/plc/interoperability/opcua/ua_client.c
View File

@ -27,14 +27,14 @@
const char *opc_server_url = {"opc.tcp://192.168.250.2:4840"};
#ifdef UA_ENABLE_SUBSCRIPTIONS
static void handler_TheAnswerChanged(UA_Client* client, UA_UInt32 subId, void* subContext,
static void UaAnswerChangedHandler(UA_Client* client, UA_UInt32 subId, void* subContext,
UA_UInt32 monId, void* monContext, UA_DataValue* value)
{
ua_print("The Answer has changed!\n");
ua_notice("Answer changed!\n");
}
#endif
static UA_StatusCode nodeIter(UA_NodeId childId, UA_Boolean isInverse, UA_NodeId referenceTypeId, void* handle)
static UA_StatusCode UaShowNodeIdIterate(UA_NodeId childId, UA_Boolean isInverse, UA_NodeId referenceTypeId, void* handle)
{
if(isInverse)
{
@ -49,7 +49,7 @@ static UA_StatusCode nodeIter(UA_NodeId childId, UA_Boolean isInverse, UA_NodeId
return UA_STATUSCODE_GOOD;
}
int ua_get_points(UA_Client* client)
int UaGetEndPoints(UA_Client* client)
{
/* Listing endpoints */
UA_EndpointDescription* endpointArray = NULL;
@ -76,7 +76,7 @@ int ua_get_points(UA_Client* client)
return EXIT_SUCCESS;
}
void ua_print_value(UA_Variant* val)
static void UaShowNodeValue(UA_Variant* val)
{
if(val->type == &UA_TYPES[UA_TYPES_LOCALIZEDTEXT])
{
@ -103,6 +103,16 @@ void ua_print_value(UA_Variant* val)
UA_Int16* ptr = (UA_Int16*)val->data;
ua_notice("%d (Int16)\n", *ptr);
}
else if(val->type == &UA_TYPES[UA_TYPES_FLOAT])
{
UA_Float* ptr = (UA_Float*)val->data;
printf("%f (Float)\n", *ptr);
}
else if(val->type == &UA_TYPES[UA_TYPES_DOUBLE])
{
UA_Double* ptr = (UA_Double*)val->data;
printf("%f (Double)\n", *ptr);
}
else if(val->type == &UA_TYPES[UA_TYPES_STRING])
{
UA_String* ptr = (UA_String*)val->data;
@ -117,7 +127,7 @@ void ua_print_value(UA_Variant* val)
}
}
char *ua_get_nodeid_str(UA_NodeId *node_id)
char *UaGetNodeIdString(UA_NodeId *node_id)
{
static char nodeid_str[UA_NODE_LEN] = {0};
@ -139,7 +149,7 @@ char *ua_get_nodeid_str(UA_NodeId *node_id)
return nodeid_str;
}
void ua_print_nodeid(UA_NodeId *node_id)
static void UaShowNodeId(UA_NodeId *node_id)
{
switch(node_id->identifierType)
{
@ -158,7 +168,7 @@ void ua_print_nodeid(UA_NodeId *node_id)
}
}
void ua_print_object(UA_BrowseResponse* res)
static void UaShowObject(UA_BrowseResponse* res)
{
ua_notice("%-9s %-16s %-16s %-16s\n", "NAMESPACE", "NODEID", "BROWSE NAME", "DISPLAY NAME");
@ -191,7 +201,7 @@ void ua_print_object(UA_BrowseResponse* res)
ua_notice("\n");
}
UA_StatusCode ua_read_array_value(UA_Client* client, int array_size, UA_ReadValueId* array)
UA_StatusCode UaReadArrayValue(UA_Client* client, int array_size, UA_ReadValueId* array)
{
UA_ReadRequest request;
UA_ReadRequest_init(&request);
@ -209,14 +219,19 @@ UA_StatusCode ua_read_array_value(UA_Client* client, int array_size, UA_ReadValu
}
UA_StatusCode* arr_ret = malloc(array_size * sizeof(UA_StatusCode));
if(arr_ret == NULL)
{
ua_error("ua: [%s] malloc %d failed!\n", __func__, array_size * sizeof(UA_StatusCode));
return UA_STATUSCODE_BADOUTOFMEMORY;
}
for(int i = 0; i < array_size; ++i)
{
if((response.results[i].status == UA_STATUSCODE_GOOD)
&& (response.results[i].hasValue))
{
ua_notice("node %s: ", ua_get_nodeid_str(&array[i].nodeId));
ua_print_value(&response.results[i].value);
ua_notice("node %s: ", UaGetNodeIdString(&array[i].nodeId));
UaShowNodeValue(&response.results[i].value);
}
}
ua_notice("\n");
@ -226,32 +241,82 @@ UA_StatusCode ua_read_array_value(UA_Client* client, int array_size, UA_ReadValu
return UA_STATUSCODE_GOOD;
}
void ua_browser_id(UA_Client* client, UA_NodeId id)
void UaBrowserNodeId(UA_Client* client, UA_NodeId id)
{
UA_BrowseRequest ua_req;
UA_BrowseResponse ua_resp;
/* Browse some objects */
ua_notice("Browsing nodes in objects folder:\n");
UA_BrowseRequest bReq;
UA_BrowseRequest_init(&bReq);
bReq.requestedMaxReferencesPerNode = 0;
bReq.nodesToBrowse = UA_BrowseDescription_new();
bReq.nodesToBrowseSize = 1;
bReq.nodesToBrowse[0].nodeId = id; /* browse objects folder */
bReq.nodesToBrowse[0].resultMask = UA_BROWSERESULTMASK_ALL; /* return everything */
UA_BrowseResponse res = UA_Client_Service_browse(client, bReq);
ua_print_object(&res);
UA_BrowseResponse_clear(&res);
// UA_BrowseRequest_clear(&bReq);
UA_BrowseRequest_init(&ua_req);
ua_req.requestedMaxReferencesPerNode = 0;
ua_req.nodesToBrowse = UA_BrowseDescription_new();
ua_req.nodesToBrowseSize = 1;
ua_req.nodesToBrowse[0].nodeId = id; /* browse objects folder */
ua_req.nodesToBrowse[0].resultMask = UA_BROWSERESULTMASK_ALL; /* return everything */
ua_resp = UA_Client_Service_browse(client, ua_req);
UaShowObject(&ua_resp);
UA_BrowseResponse_clear(&ua_resp);
}
void ua_browser_nodes(UA_Client* client)
int UaGetNodeIdArray(UA_Client* client, UA_NodeId id, int array_size, int *id_array)
{
int i, j;
int array_cnt = 0;// return array number
UA_BrowseRequest ua_req;
UA_BrowseResponse ua_resp;
/* Browse some objects */
ua_notice("Browsing nodes in objects folder:\n");
UA_BrowseRequest_init(&ua_req);
ua_req.requestedMaxReferencesPerNode = 0;
ua_req.nodesToBrowse = UA_BrowseDescription_new();
ua_req.nodesToBrowseSize = 1;
ua_req.nodesToBrowse[0].nodeId = id; /* browse objects folder */
ua_req.nodesToBrowse[0].resultMask = UA_BROWSERESULTMASK_ALL; /* return everything */
ua_resp = UA_Client_Service_browse(client, ua_req);
for(i = 0; i < ua_resp.resultsSize; ++i)
{
for(j = 0; j < ua_resp.results[i].referencesSize; ++j)
{
UA_ReferenceDescription* ref = &(ua_resp.results[i].references[j]);
if(ref->nodeId.nodeId.identifierType == UA_NODEIDTYPE_NUMERIC)
{
*(id_array + array_cnt) = ref->nodeId.nodeId.identifier.numeric;
array_cnt ++;
if(array_cnt >= array_size)
{
UA_BrowseResponse_clear(&ua_resp);
return array_cnt;
}
}
}
}
UA_BrowseResponse_clear(&ua_resp);
return array_cnt;
}
void UaBrowserNodes(UA_Client* client)
{
UA_NodeId* parent = UA_NodeId_new();
*parent = UA_NODEID_NUMERIC(0, UA_NS0ID_OBJECTSFOLDER);
UA_Client_forEachChildNodeCall(client, UA_NODEID_NUMERIC(0, UA_NS0ID_OBJECTSFOLDER), nodeIter, (void*) parent);
UA_Client_forEachChildNodeCall(client, UA_NODEID_NUMERIC(0, UA_NS0ID_OBJECTSFOLDER), UaShowNodeIdIterate, (void*) parent);
UA_NodeId_delete(parent);
}
UA_UInt32 ua_start_sub(UA_Client* client, UA_NodeId node_id)
UA_UInt32 UaStartSubscription(UA_Client* client, UA_NodeId node_id)
{
/* Create a subscription */
UA_CreateSubscriptionRequest request = UA_CreateSubscriptionRequest_default();
@ -274,7 +339,7 @@ UA_UInt32 ua_start_sub(UA_Client* client, UA_NodeId node_id)
UA_MonitoredItemCreateResult monResponse =
UA_Client_MonitoredItems_createDataChange(client, response.subscriptionId,
UA_TIMESTAMPSTORETURN_BOTH,
monRequest, NULL, handler_TheAnswerChanged, NULL);
monRequest, NULL, UaAnswerChangedHandler, NULL);
if(monResponse.statusCode == UA_STATUSCODE_GOOD)
{
@ -290,7 +355,7 @@ UA_UInt32 ua_start_sub(UA_Client* client, UA_NodeId node_id)
return subId;
}
void ua_write_nodeid_value(UA_Client* client, UA_NodeId id, char* value)
void UaWriteNodeValue(UA_Client* client, UA_NodeId id, char* value)
{
UA_Boolean bool_val;
uint32_t integer_val;
@ -332,24 +397,17 @@ void ua_write_nodeid_value(UA_Client* client, UA_NodeId id, char* value)
UA_WriteRequest_clear(&wReq);
UA_WriteResponse_clear(&wResp);
// /* Write node attribute (using the highlevel API) */
// value++;
// UA_Variant *myVariant = UA_Variant_new();
// UA_Variant_setScalarCopy(myVariant, &value, &UA_TYPES[UA_TYPES_INT32]);
// UA_Client_writeValueAttribute(client, UA_NODEID_STRING(1, UA_NODE_STR), myVariant);
// UA_Variant_delete(myVariant);
}
/* Read attribute */
void ua_read_nodeid_value(UA_Client* client, UA_NodeId id, UA_Int32 *value)
void UaReadNodeValue(UA_Client* client, UA_NodeId id, UA_Int32 *value)
{
UA_Variant* val = UA_Variant_new();
UA_StatusCode ret = UA_Client_readValueAttribute(client, id, val);
if(ret == UA_STATUSCODE_GOOD)
{
ua_print_value(val);
UaShowNodeValue(val);
if(UA_Variant_isScalar(val))
{
if(val->type == &UA_TYPES[UA_TYPES_BOOLEAN])
@ -370,7 +428,7 @@ void ua_read_nodeid_value(UA_Client* client, UA_NodeId id, UA_Int32 *value)
UA_Variant_delete(val);
}
void ua_call_remote(UA_Client* client)
void UaCallRemote(UA_Client* client)
{
/* Call a remote method */
UA_Variant input;
@ -397,7 +455,7 @@ void ua_call_remote(UA_Client* client)
}
void ua_add_nodes(UA_Client* client)
void UaAddNodes(UA_Client* client)
{
/* Add new nodes*/
/* New ReferenceType */
@ -477,7 +535,7 @@ void ua_add_nodes(UA_Client* client)
}
}
void ua_read_time(UA_Client* client)
void UaGetServerTime(UA_Client* client)
{
UA_Variant value;
UA_Variant_init(&value);

28
APP_Framework/Framework/control/plc/interoperability/opcua/ua_server.c
View File

@ -10,29 +10,29 @@
* See the Mulan PSL v2 for more details.
*/
/**
* @file ua_server.c
* @brief Server for OpcUa function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021.11.11
*/
#include "open62541.h"
#include <signal.h>
#include <stdlib.h>
UA_Boolean ua_server_flag = true;
UA_Boolean running = true;
static void stopHandler(int sign) {
UA_LOG_INFO(UA_Log_Stdout, UA_LOGCATEGORY_SERVER, "received ctrl-c");
running = false;
}
int ua_server_connect(void)
int UaRunServer(void)
{
signal(SIGINT, stopHandler);
signal(SIGTERM, stopHandler);
UA_StatusCode ret;
UA_Server *server = UA_Server_new();
UA_ServerConfig_setDefault(UA_Server_getConfig(server));
UA_StatusCode retval = UA_Server_run(server, &running);
ret = UA_Server_run(server, &ua_server_flag);
UA_Server_delete(server);
return retval == UA_STATUSCODE_GOOD ? EXIT_SUCCESS : EXIT_FAILURE;
return ret;
}

72
APP_Framework/Framework/control/plc/interoperability/opcua/ua_test.c
View File

@ -27,72 +27,60 @@
#define UA_TEST_BROWSER_NODEID1 UA_NODEID_NUMERIC(4, 1)
#define UA_TEST_WRITE_NODEID UA_NODEID_NUMERIC(4, 5)
#define UA_TEST_NODE_ARRAY_NUM 10
static UA_StatusCode ua_test_read_array(UA_Client *client)
static UA_StatusCode UaTestReadArrayValue(UA_Client *client, UA_NodeId id)
{
const int item_size = 4;
UA_ReadValueId test_item[item_size];
int i;
int array_size = 0;
int test_id[UA_TEST_NODE_ARRAY_NUM];
UA_ReadValueId test_array[UA_TEST_NODE_ARRAY_NUM];
for (int i = 0; i < item_size; i++)
for(i = 0; i < UA_TEST_NODE_ARRAY_NUM; i++)
{
UA_ReadValueId_init(&test_item[i]);
test_item[i].attributeId = UA_ATTRIBUTEID_VALUE;
UA_ReadValueId_init(&test_array[i]);
test_array[i].attributeId = UA_ATTRIBUTEID_VALUE;
}
test_item[0].nodeId = UA_NODEID_NUMERIC(4, 2);
test_item[1].nodeId = UA_NODEID_NUMERIC(4, 3);
test_item[2].nodeId = UA_NODEID_NUMERIC(4, 4);
test_item[3].nodeId = UA_NODEID_NUMERIC(4, 5);
array_size = UaGetNodeIdArray(client, id, UA_TEST_NODE_ARRAY_NUM, test_id);
return ua_read_array_value(client, item_size, test_item);
for(i = 0; i < array_size; i++)
{
test_array[i].nodeId = UA_NODEID_NUMERIC(id.namespaceIndex, test_id[i]);
}
return UaReadArrayValue(client, array_size, test_array);
}
void ua_test_browser_objects(UA_Client *client)
void UaTestBrowserObjects(UA_Client *client)
{
UA_NodeId test_id;
ua_browser_id(client, UA_TEST_BROWSER_NODEID);
ua_browser_id(client, UA_TEST_BROWSER_NODEID1);
UaBrowserNodeId(client, UA_TEST_BROWSER_NODEID);
UaBrowserNodeId(client, UA_TEST_BROWSER_NODEID1);
test_id = UA_TEST_BROWSER_NODEID1;
ua_notice("Show values in %s:\n", ua_get_nodeid_str(&test_id));
ua_test_read_array(client);
ua_notice("Show values in %s:\n", UaGetNodeIdString(&test_id));
UaTestReadArrayValue(client, test_id);
return;
}
void ua_test_write_attr(UA_Client *client)
static void UaTestWriteNodeValue(UA_Client *client)
{
UA_Int32 value;
char val_str[UA_NODE_LEN];
UA_NodeId id = UA_TEST_WRITE_NODEID;
ua_notice("--- Test write %s ---\n", ua_get_nodeid_str(&id));
ua_read_nodeid_value(client, id, &value);
ua_write_nodeid_value(client, id, itoa(value + 1, val_str, 10));
ua_read_nodeid_value(client, id, &value);
ua_notice("--- Test write %s ---\n", UaGetNodeIdString(&id));
UaReadNodeValue(client, id, &value);
UaWriteNodeValue(client, id, itoa(value + 1, val_str, 10));
UaReadNodeValue(client, id, &value);
ua_notice("\n");
}
int ua_test_interact_server(UA_Client *client)
int UaTestInteractServer(UA_Client *client)
{
ua_read_time(client);
ua_test_browser_objects(client);
ua_test_write_attr(client);
return EXIT_SUCCESS;
}
int16 ua_test(void)
{
UA_Client *client = UA_Client_new();
UA_StatusCode retval = UA_Client_connect(client, opc_server_url);
if(retval != UA_STATUSCODE_GOOD) {
UA_Client_delete(client);
return (int)retval;
}
ua_read_time(client);
/* Clean up */
UA_Client_disconnect(client);
UA_Client_delete(client); /* Disconnects the client internally */
UaGetServerTime(client);
UaTestBrowserObjects(client);
UaTestWriteNodeValue(client);
return EXIT_SUCCESS;
}

2
APP_Framework/Framework/control/plc/shared/plc_channel.c
View File

@ -322,7 +322,7 @@ ChDevType ChannelFindDevice(struct Channel *ch, const char *device_name)
* @param dev_recv_callback - callback function
* @return successful:EOK,failed:ERROR
*/
uint32 ChannelDevRecvCallback(struct ChDev *dev, int (*dev_recv_callback) (void *dev, x_size_t length))
uint32 ChannelDevRecvCallback(struct ChDev *dev, int (*dev_recv_callback) (void *dev, size_t length))
{
CHECK_CH_PARAM(dev );

28
APP_Framework/Framework/control/plc/shared/plc_channel.h
View File

@ -12,7 +12,7 @@
/**
* @file plc_channel.h
* @brief define ch driver framework function and common API
* @brief define channel driver framework function and common API
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-03-01
@ -23,9 +23,6 @@
#include "list.h"
#define x_OffPos uint32
#define x_size_t size_t
#ifdef __cplusplus
extern "C" {
#endif
@ -97,27 +94,19 @@ struct ChConfigInfo
struct ChReadParam
{
x_OffPos pos;
uint32 pos;
void* buffer;
x_size_t size;
x_size_t read_length;
size_t size;
size_t read_length;
};
struct ChWriteParam
{
x_OffPos pos;
uint32 pos;
const void* buffer;
x_size_t size;
size_t size;
};
//struct ChHalDevBlockParam
//{
// uint32 cmd;
////tst by wly
//// struct DeviceBlockArrange dev_block;
//// struct DeviceBlockAddr *dev_addr;
//};
struct ChHalDevDone
{
uint32 (*open) (void *dev);
@ -134,8 +123,7 @@ struct ChDev
const struct ChHalDevDone *dev_done;
int (*dev_recv_callback) (void *dev, x_size_t length);
// int (*dev_block_control) (struct ChDev *dev, struct ChHalDevBlockParam *block_param);
int (*dev_recv_callback) (void *dev, size_t length);
struct Channel *owner_ch;
void *private_data;
@ -220,7 +208,7 @@ ChDrvType ChannelFindDriver(struct Channel *ch, const char *driver_name);
ChDevType ChannelFindDevice(struct Channel *ch, const char *device_name);
/*Dev receive data callback function*/
uint32 ChannelDevRecvCallback(struct ChDev *dev, int (*dev_recv_callback) (void *dev, x_size_t length));
uint32 ChannelDevRecvCallback(struct ChDev *dev, int (*dev_recv_callback) (void *dev, size_t length));
/*Open the device of the channel*/
uint32 ChannelDevOpen(struct ChDev *dev);

8
APP_Framework/Framework/control/plc/shared/plc_device.c
View File

@ -40,7 +40,7 @@ static int PlcDeviceOpen(void *dev)
if(plc_dev->net == PLC_IND_ENET_OPCUA)
{
return ua_open(plc_dev->priv_data);
return UaDevOpen(plc_dev->priv_data);
}
return EOK;
@ -54,7 +54,7 @@ static void PlcDeviceClose(void *dev)
if(plc_dev->net == PLC_IND_ENET_OPCUA)
{
ua_close(plc_dev->priv_data);
UaDevClose(plc_dev->priv_data);
}
}
@ -67,7 +67,7 @@ static int PlcDeviceWrite(void *dev, const void *buf, size_t len)
if(plc_dev->net == PLC_IND_ENET_OPCUA)
{
ret = ua_write(plc_dev->priv_data, buf, len);
ret = UaDevWrite(plc_dev->priv_data, buf, len);
}
return ret;
@ -83,7 +83,7 @@ static int PlcDeviceRead(void *dev, void *buf, size_t len)
if(plc_dev->net == PLC_IND_ENET_OPCUA)
{
ret = ua_read(plc_dev->priv_data, buf, len);
ret = UaDevRead(plc_dev->priv_data, buf, len);
}
return ret;

60
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/Kconfig
View File

@ -24,4 +24,64 @@ config XIDATONG_SDRAM
---help---
Activate DCD configuration of SDRAM
config XIDATONG_SDHC_AUTOMOUNT
bool "SDHC automounter"
default n
depends on FS_AUTOMOUNTER && IMXRT_USDHC
if XIDATONG_SDHC_AUTOMOUNT
config XIDATONG_SDHC_AUTOMOUNT_FSTYPE
string "SDHC file system type"
default "vfat"
config XIDATONG_SDHC_AUTOMOUNT_BLKDEV
string "SDHC block device"
default "/dev/mmcsd0"
config XIDATONG_SDHC_AUTOMOUNT_MOUNTPOINT
string "SDHC mount point"
default "/mnt/sdcard"
config XIDATONG_SDHC_AUTOMOUNT_DDELAY
int "SDHC debounce delay (milliseconds)"
default 1000
config XIDATONG_SDHC_AUTOMOUNT_UDELAY
int "SDHC unmount retry delay (milliseconds)"
default 2000
endif # XIDATONG_SDHC_AUTOMOUNT
config XIDATONG_USB_AUTOMOUNT
bool "USB Mass Storage automounter"
default n
depends on USBHOST_MSC && USBHOST_MSC_NOTIFIER
if XIDATONG_USB_AUTOMOUNT
config XIDATONG_USB_AUTOMOUNT_FSTYPE
string "USB file system type"
default "vfat"
config XIDATONG_USB_AUTOMOUNT_BLKDEV
string "USB block device prefix"
default "/dev/sd"
config XIDATONG_USB_AUTOMOUNT_MOUNTPOINT
string "USB mount point prefix"
default "/mnt/usb"
config XIDATONG_USB_AUTOMOUNT_NUM_BLKDEV
int "Number of block devices to monitor."
range 1 26
default 4
config XIDATONG_USB_AUTOMOUNT_UDELAY
int "USB unmount retry delay (milliseconds)"
default 2000
endif # XIDATONG_USB_AUTOMOUNT
endif

11
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/usdhc/defconfig → Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/sdionsh/defconfig
View File

@ -20,11 +20,6 @@ CONFIG_ARMV7M_ICACHE=y
CONFIG_ARMV7M_USEBASEPRI=y
CONFIG_BOARD_LOOPSPERMSEC=104926
CONFIG_BUILTIN=y
CONFIG_DEBUG_FEATURES=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_DEV_URANDOM=y
CONFIG_DEV_ZERO=y
CONFIG_FAT_LCNAMES=y
CONFIG_CLOCK_MONOTONIC=y
CONFIG_FAT_LFN=y
@ -32,8 +27,7 @@ CONFIG_FS_FAT=y
CONFIG_FS_PROCFS=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_EXAMPLES_HELLO=y
CONFIG_IMXRT1020_EVK_QSPI_FLASH=y
CONFIG_IMXRT_GPIO1_0_15_IRQ=y
CONFIG_IMXRT_GPIO2_16_31_IRQ=y
CONFIG_IMXRT_GPIO_IRQ=y
CONFIG_IMXRT_LPUART1=y
CONFIG_IMXRT_USDHC1=y
@ -42,9 +36,7 @@ CONFIG_INTELHEX_BINARY=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_NCHAINS=8
CONFIG_LIBC_STRERROR=y
CONFIG_LPUART1_RXBUFSIZE=1024
CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_LPUART1_TXBUFSIZE=1024
CONFIG_MMCSD=y
CONFIG_MMCSD_SDIO=y
CONFIG_MM_IOB=y
@ -69,5 +61,6 @@ CONFIG_START_DAY=14
CONFIG_START_MONTH=3
CONFIG_SYSTEM_CLE_CMD_HISTORY=y
CONFIG_SYSTEM_COLOR_CLE=y
CONFIG_FS_AUTOMOUNTER=y
CONFIG_SYSTEM_NSH=y
CONFIG_USER_ENTRYPOINT="nsh_main"

64
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/configs/usbnsh/defconfig Normal file
View File

@ -0,0 +1,64 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
CONFIG_ADD_NUTTX_FETURES=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="xidatong"
CONFIG_ARCH_BOARD_XIDATONG=y
CONFIG_ARCH_CHIP="imxrt"
CONFIG_ARCH_CHIP_IMXRT=y
CONFIG_ARCH_CHIP_MIMXRT1052CVL5B=y
CONFIG_ARCH_INTERRUPTSTACK=10240
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARMV7M_DCACHE=y
CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
CONFIG_ARMV7M_ICACHE=y
CONFIG_ARMV7M_USEBASEPRI=y
CONFIG_BOARD_LOOPSPERMSEC=104926
CONFIG_BUILTIN=y
CONFIG_FAT_LCNAMES=y
CONFIG_CLOCK_MONOTONIC=y
CONFIG_FAT_LFN=y
CONFIG_FS_FAT=y
CONFIG_FS_PROCFS=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_EXAMPLES_HELLO=y
CONFIG_IMXRT_LPUART1=y
CONFIG_INTELHEX_BINARY=y
CONFIG_IOB_NBUFFERS=24
CONFIG_IOB_NCHAINS=8
CONFIG_LIBC_STRERROR=y
CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_MM_IOB=y
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_CMDOPT_DD_STATS=y
CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_RAM_SIZE=524288
CONFIG_RAM_START=0x20200000
CONFIG_RAW_BINARY=y
CONFIG_SCHED_CHILD_STATUS=y
CONFIG_SCHED_HAVE_PARENT=y
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_LPWORK=y
CONFIG_SCHED_WAITPID=y
CONFIG_SERIAL_TERMIOS=y
CONFIG_START_DAY=14
CONFIG_START_MONTH=3
CONFIG_SYSTEM_CLE_CMD_HISTORY=y
CONFIG_SYSTEM_COLOR_CLE=y
CONFIG_SYSTEM_NSH=y
CONFIG_IMXRT_USBOTG=y
CONFIG_IMXRT_USBDEV=y
CONFIG_USBDEV=y
CONFIG_USBHOST=y
CONFIG_USBHOST_MSC=y
CONFIG_USBHOST_MSC_NOTIFIER=y
CONFIG_USER_ENTRYPOINT="nsh_main"

4
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/include/board.h
View File

@ -128,6 +128,7 @@
#define IMXRT_SYS_PLL_SELECT CCM_ANALOG_PLL_SYS_DIV_SELECT_22
#define IMXRT_USB1_PLL_DIV_SELECT CCM_ANALOG_PLL_USB1_DIV_SELECT_20
#define IMXRT_USB2_PLL_DIV_SELECT CCM_ANALOG_PLL_USB2_DIV_SELECT_20
// #define BOARD_CPU_FREQUENCY \
// (BOARD_XTAL_FREQUENCY * (IMXRT_ARM_PLL_DIV_SELECT / 2)) / IMXRT_ARM_PODF_DIVIDER
@ -214,9 +215,8 @@
#define PIN_USDHC1_D3 (GPIO_USDHC1_DATA3_1 | IOMUX_USDHC1_DATAX_DEFAULT) /* GPIO_SD_B0_05 */
#define PIN_USDHC1_DCLK (GPIO_USDHC1_CLK_1 | IOMUX_USDHC1_CLK_DEFAULT) /* GPIO_SD_B0_01 */
#define PIN_USDHC1_CMD (GPIO_USDHC1_CMD_1 | IOMUX_USDHC1_CMD_DEFAULT) /* GPIO_SD_B0_00 */
//#define PIN_USDHC1_CD (GPIO_USDHC1_CD_2 | IOMUX_USDHC1_CLK_DEFAULT)
#define PIN_USDHC1_CD_GPIO (IOMUX_VSD_DEFAULT | GPIO_PORT2 | GPIO_PIN28) /* GPIO_B1_12 */
#define PIN_USDHC1_CD (GPIO_USDHC1_CD_2 | IOMUX_USDHC1_CLK_DEFAULT) /* GPIO_B1_12 */
/* 386 KHz for initial inquiry stuff */

9
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/readme.md
View File

@ -137,8 +137,9 @@ source build.sh
执行完毕会自动进入./Ubiquitous/Nuttx_Fusion_XiUOS/nuttx下，继续执行
sudo ./tools/configure.sh xidatong:nsh
sudo make menuconfig
./tools/configure.sh xidatong:nsh
make menuconfig
视情况而定，如果需要前面加sudo
```
2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
@ -152,9 +153,9 @@ sudo make menuconfig
3.继续执行以下命令，进行编译
```shell
sudo make
make
或
sudo make -j8
make -j8
```
make时加上V=1参数可以看到较为详细的编译信息，但是编译过程会比较慢。

8
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/Makefile
View File

@ -66,4 +66,12 @@ ifeq ($(CONFIG_XIDATONG_SDRAM),y)
CSRCS += imxrt_sdram_ini_dcd.c
endif
ifeq ($(CONFIG_USBHOST),y)
CSRCS += imxrt_usbhost.c
endif
ifeq ($(CONFIG_XIDATONG_SDHC_AUTOMOUNT),y)
CSRCS += imxrt_sdhc_automount.c
endif
include $(TOPDIR)/boards/Board.mk

30
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_bringup.c
View File

@ -47,6 +47,10 @@
# include "imxrt_usdhc.h"
#endif
#ifdef CONFIG_USBMONITOR
# include <nuttx/usb/usbmonitor.h>
#endif
#include "xidatong.h"
#include <arch/board/board.h> /* Must always be included last */
@ -114,6 +118,13 @@ static int nsh_sdmmc_initialize(void)
"ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n",
ret);
}
#ifdef CONFIG_XIDATONG_SDHC_AUTOMOUNT
imxrt_automount_initialize();
imxrt_usdhc_set_sdio_card_isr(sdmmc, imxrt_sdhc_automount_event, NULL);
#else
imxrt_usdhc_set_sdio_card_isr(sdmmc, NULL, NULL);
#endif
}
return OK;
@ -175,6 +186,25 @@ int imxrt_bringup(void)
}
#endif
#if defined(CONFIG_IMXRT_USBOTG) || defined(CONFIG_USBHOST)
ret = imxrt_usbhost_initialize();
if (ret != OK)
{
syslog(LOG_ERR, "ERROR: Failed to start USB host services: %d\n", ret);
return ret;
}
#endif
#ifdef CONFIG_USBMONITOR
/* Start the USB Monitor */
ret = usbmonitor_start();
if (ret != OK)
{
syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret);
}
#endif
#ifdef CONFIG_DEV_GPIO
ret = imxrt_gpio_initialize();
if (ret < 0)

330
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_sdhc_automount.c Normal file
View File

@ -0,0 +1,330 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file imxrt_sdhc_automount.c
* @brief imxrt board sd card automount
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.04.07
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_FS_AUTOMOUNTER_DEBUG) && !defined(CONFIG_DEBUG_FS)
# define CONFIG_DEBUG_FS 1
#endif
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/clock.h>
#include <nuttx/fs/automount.h>
#include "hardware/imxrt_pinmux.h"
#include "xidatong.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef NULL
# define NULL (FAR void *)0
#endif
#ifndef OK
# define OK 0
#endif
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure represents the changeable state of the automounter */
struct imxrt_automount_state_s
{
volatile automount_handler_t handler; /* Upper half handler */
FAR void *arg; /* Handler argument */
bool enable; /* Fake interrupt enable */
bool pending; /* Set if there an event while disabled */
};
/* This structure represents the static configuration of an automounter */
struct imxrt_automount_config_s
{
/* This must be first thing in structure so that we can simply cast from
* struct automount_lower_s to struct imxrt_automount_config_s
*/
struct automount_lower_s lower; /* Publicly visible part */
FAR struct imxrt_automount_state_s *state; /* Changeable state */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int imxrt_sdhc_attach(FAR const struct automount_lower_s *lower,
automount_handler_t isr, FAR void *arg);
static void imxrt_sdhc_enable(FAR const struct automount_lower_s *lower,
bool enable);
static bool imxrt_sdhc_inserted(FAR const struct automount_lower_s *lower);
/****************************************************************************
* Private Data
****************************************************************************/
static struct imxrt_automount_state_s g_sdhc_state;
static const struct imxrt_automount_config_s g_sdhc_config =
{
.lower =
{
.fstype = CONFIG_XIDATONG_SDHC_AUTOMOUNT_FSTYPE,
.blockdev = CONFIG_XIDATONG_SDHC_AUTOMOUNT_BLKDEV,
.mountpoint = CONFIG_XIDATONG_SDHC_AUTOMOUNT_MOUNTPOINT,
.ddelay = MSEC2TICK(CONFIG_XIDATONG_SDHC_AUTOMOUNT_DDELAY),
.udelay = MSEC2TICK(CONFIG_XIDATONG_SDHC_AUTOMOUNT_UDELAY),
.attach = imxrt_sdhc_attach,
.enable = imxrt_sdhc_enable,
.inserted = imxrt_sdhc_inserted
},
.state = &g_sdhc_state
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_sdhc_attach
*
* Description:
* Attach a new SDHC event handler
*
* Input Parameters:
* lower - An instance of the auto-mounter lower half state structure
* isr - The new event handler to be attach
* arg - Client data to be provided when the event handler is invoked.
*
* Returned Value:
* Always returns OK
*
****************************************************************************/
static int imxrt_sdhc_attach(FAR const struct automount_lower_s *lower,
automount_handler_t isr, FAR void *arg)
{
FAR const struct imxrt_automount_config_s *config;
FAR struct imxrt_automount_state_s *state;
/* Recover references to our structure */
config = (FAR struct imxrt_automount_config_s *)lower;
DEBUGASSERT(config != NULL && config->state != NULL);
state = config->state;
/* Save the new handler info (clearing the handler first to eliminate race
* conditions).
*/
state->handler = NULL;
state->pending = false;
state->arg = arg;
state->handler = isr;
return OK;
}
/****************************************************************************
* Name: imxrt_sdhc_enable
*
* Description:
* Enable card insertion/removal event detection
*
* Input Parameters:
* lower - An instance of the auto-mounter lower half state structure
* enable - True: enable event detection; False: disable
*
* Returned Value:
* None
*
****************************************************************************/
static void imxrt_sdhc_enable(FAR const struct automount_lower_s *lower,
bool enable)
{
FAR const struct imxrt_automount_config_s *config;
FAR struct imxrt_automount_state_s *state;
irqstate_t flags;
/* Recover references to our structure */
config = (FAR struct imxrt_automount_config_s *)lower;
DEBUGASSERT(config != NULL && config->state != NULL);
state = config->state;
/* Save the fake enable setting */
flags = enter_critical_section();
state->enable = enable;
/* Did an interrupt occur while interrupts were disabled? */
if (enable && state->pending)
{
/* Yes.. perform the fake interrupt if the interrutp is attached */
if (state->handler)
{
uint8_t inserted = imxrt_gpio_read(PIN_USDHC1_CD);
if (0 == inserted)
{
state->handler(&config->lower, state->arg, true);
}
else
{
state->handler(&config->lower, state->arg, false);
}
}
state->pending = false;
}
leave_critical_section(flags);
}
/****************************************************************************
* Name: imxrt_sdhc_inserted
*
* Description:
* Check if a card is inserted into the slot.
*
* Input Parameters:
* lower - An instance of the auto-mounter lower half state structure
*
* Returned Value:
* True if the card is inserted; False otherwise
*
****************************************************************************/
static bool imxrt_sdhc_inserted(FAR const struct automount_lower_s *lower)
{
uint8_t inserted = imxrt_gpio_read(PIN_USDHC1_CD);
if (0 == inserted)
{
return true;
}
return false;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_sdhc_automount_event
*
* Description:
* The SDHC card detection logic has detected an insertion or removal
* event.
* It has already scheduled the MMC/SD block driver operations.
* Now we need to schedule the auto-mount event which will occur with a
* substantial delay to make sure that everything has settle down.
*
* Input Parameters:
* slotno - Identifies the SDHC0 slot: SDHC0_SLOTNO or SDHC1_SLOTNO.
* There is a terminology problem here: Each SDHC supports two slots,
* slot A and slot B. Only slot A is used.
* So this is not a really a slot, but an HSCMI peripheral number.
* inserted - True if the card is inserted in the slot. False otherwise.
*
* Returned Value:
* None
*
* Assumptions:
* Interrupts are disabled.
*
****************************************************************************/
int imxrt_sdhc_automount_event(void *arg)
{
FAR const struct imxrt_automount_config_s *config = &g_sdhc_config;
FAR struct imxrt_automount_state_s *state = &g_sdhc_state;
/* Is the auto-mounter interrupt attached? */
if (state->handler)
{
/* Yes.. Have we been asked to hold off interrupts? */
if (!state->enable)
{
/* Yes.. just remember that there is a pending interrupt. We will
* deliver the interrupt when interrupts are "re-enabled."
*/
state->pending = true;
}
else
{
/* No.. forward the event to the handler */
uint8_t inserted = imxrt_gpio_read(PIN_USDHC1_CD);
if (0 == inserted)
{
state->handler(&config->lower, state->arg, true);
}
else
{
state->handler(&config->lower, state->arg, false);
}
}
}
return 0;
}
/****************************************************************************
* Name: imxrt_automount_initialize
*
* Description:
* Configure auto-mounters for each enable and so configured SDHC
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void imxrt_automount_initialize(void)
{
FAR void *handle;
finfo("Initializing automounter(s)\n");
/* Initialize the SDHC0 auto-mounter */
handle = automount_initialize(&g_sdhc_config.lower);
if (!handle)
{
ferr("ERROR: Failed to initialize auto-mounter for SDHC0\n");
}
}

468
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_usbhost.c Normal file
View File

@ -0,0 +1,468 @@
/****************************************************************************
* boards/arm/imxrt/imxrt1020-evk/src/imxrt_usbhost.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <sched.h>
#include <errno.h>
#include <assert.h>
#include <debug.h>
#include <sys/mount.h>
#include <nuttx/fs/fs.h>
#include <nuttx/irq.h>
#include <nuttx/kthread.h>
#include <nuttx/usb/usbdev.h>
#include <nuttx/usb/usbhost.h>
#include <nuttx/usb/usbdev_trace.h>
#include <nuttx/usb/ehci.h>
#include <nuttx/wdog.h>
#include <imxrt_ehci.h>
#include "hardware/imxrt_pinmux.h"
#include "hardware/imxrt_usbotg.h"
#include "imxrt_periphclks.h"
#include "xidatong.h"
#include <arch/board/board.h> /* Must always be included last */
#if defined(CONFIG_IMXRT_USBOTG) || defined(CONFIG_USBHOST)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef CONFIG_USBHOST_DEFPRIO
# define CONFIG_USBHOST_DEFPRIO 50
#endif
#ifndef CONFIG_USBHOST_STACKSIZE
# ifdef CONFIG_USBHOST_HUB
# define CONFIG_USBHOST_STACKSIZE 1536
# else
# define CONFIG_USBHOST_STACKSIZE 1024
# endif
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/* Retained device driver handle */
static struct usbhost_connection_s *g_ehciconn;
#ifdef CONFIG_XIDATONG_USB_AUTOMOUNT
/* Unmount retry timer */
static struct wdog_s g_umount_tmr[CONFIG_XIDATONG_USB_AUTOMOUNT_NUM_BLKDEV];
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: ehci_waiter
*
* Description:
* Wait for USB devices to be connected to the EHCI root hub.
*
****************************************************************************/
static int ehci_waiter(int argc, char *argv[])
{
FAR struct usbhost_hubport_s *hport;
uinfo("ehci_waiter: Running\n");
for (; ; )
{
/* Wait for the device to change state */
DEBUGVERIFY(CONN_WAIT(g_ehciconn, &hport));
syslog(LOG_INFO, "ehci_waiter: %s\n",
hport->connected ? "connected" : "disconnected");
/* Did we just become connected? */
if (hport->connected)
{
/* Yes.. enumerate the newly connected device */
CONN_ENUMERATE(g_ehciconn, hport);
}
}
/* Keep the compiler from complaining */
return 0;
}
/****************************************************************************
* Public Functions
****************************************************************************/
#ifdef CONFIG_XIDATONG_USB_AUTOMOUNT
/****************************************************************************
* Name: usb_msc_connect
*
* Description:
* Mount the USB mass storage device
*
****************************************************************************/
static void usb_msc_connect(FAR void *arg)
{
int index = (int)arg;
char sdchar = 'a' + index;
int ret;
char blkdev[32];
char mntpnt[32];
DEBUGASSERT(index >= 0 &&
index < CONFIG_XIDATONG_USB_AUTOMOUNT_NUM_BLKDEV);
wd_cancel(&g_umount_tmr[index]);
/* Resetup the event. */
usbhost_msc_notifier_setup(usb_msc_connect, WORK_USB_MSC_CONNECT,
sdchar, arg);
snprintf(blkdev, sizeof(blkdev), "%s%c",
CONFIG_XIDATONG_USB_AUTOMOUNT_BLKDEV, sdchar);
snprintf(mntpnt, sizeof(mntpnt), "%s%c",
CONFIG_XIDATONG_USB_AUTOMOUNT_MOUNTPOINT, sdchar);
/* Mount */
ret = nx_mount((FAR const char *)blkdev, (FAR const char *)mntpnt,
CONFIG_XIDATONG_USB_AUTOMOUNT_FSTYPE, 0, NULL);
if (ret < 0)
{
ferr("ERROR: Mount failed: %d\n", ret);
}
}
/****************************************************************************
* Name: unmount_retry_timeout
*
* Description:
* A previous unmount failed because the volume was busy... busy meaning
* the volume could not be unmounted because there are open references
* the files or directories in the volume. When this failure occurred,
* the unmount logic setup a delay and this function is called as a result
* of that delay timeout.
*
* This function will attempt the unmount again.
*
* Input Parameters:
* Standard wdog timeout parameters
*
* Returned Value:
* None
*
****************************************************************************/
static void unmount_retry_timeout(wdparm_t arg)
{
int index = arg;
char sdchar = 'a' + index;
finfo("Timeout!\n");
DEBUGASSERT(index >= 0 &&
index < CONFIG_XIDATONG_USB_AUTOMOUNT_NUM_BLKDEV);
/* Resend the notification. */
usbhost_msc_notifier_signal(WORK_USB_MSC_DISCONNECT, sdchar);
}
/****************************************************************************
* Name: usb_msc_disconnect
*
* Description:
* Unmount the USB mass storage device
*
****************************************************************************/
static void usb_msc_disconnect(FAR void *arg)
{
int index = (int)arg;
char sdchar = 'a' + index;
int ret;
char mntpnt[32];
DEBUGASSERT(index >= 0 &&
index < CONFIG_XIDATONG_USB_AUTOMOUNT_NUM_BLKDEV);
wd_cancel(&g_umount_tmr[index]);
/* Resetup the event. */
usbhost_msc_notifier_setup(usb_msc_disconnect, WORK_USB_MSC_DISCONNECT,
sdchar, arg);
snprintf(mntpnt, sizeof(mntpnt), "%s%c",
CONFIG_XIDATONG_USB_AUTOMOUNT_MOUNTPOINT, sdchar);
/* Unmount */
ret = nx_umount2((FAR const char *)mntpnt, MNT_FORCE);
if (ret < 0)
{
/* We expect the error to be EBUSY meaning that the volume could
* not be unmounted because there are currently reference via open
* files or directories.
*/
if (ret == -EBUSY)
{
finfo("WARNING: Volume is busy, try again later\n");
/* Start a timer to retry the umount2 after a delay */
ret = wd_start(&g_umount_tmr[index],
MSEC2TICK(CONFIG_XIDATONG_USB_AUTOMOUNT_UDELAY),
unmount_retry_timeout, index);
if (ret < 0)
{
ferr("ERROR: wd_start failed: %d\n", ret);
}
}
/* Other errors are fatal */
else
{
ferr("ERROR: Unmount failed!\n");
}
}
}
#endif /* CONFIG_XIDATONG_USB_AUTOMOUNT */
/****************************************************************************
* Name: imxrt_usbhost_initialize
*
* Description:
* Called at application startup time to initialize the USB host
* functionality.
* This function will start a thread that will monitor for device
* connection/disconnection events.
*
****************************************************************************/
int imxrt_usbhost_initialize(void)
{
pid_t pid;
int ret;
#ifdef CONFIG_XIDATONG_USB_AUTOMOUNT
int index;
#endif
imxrt_clockall_usboh3();
/* Make sure we don't accidentally switch on USB bus power */
*((uint32_t *)IMXRT_USBNC_USB_OTG2_CTRL) = USBNC_PWR_POL;
*((uint32_t *)0x400d9030) = (1 << 21);
*((uint32_t *)0x400d9000) = 0;
/* Setup pins, with power initially off */
imxrt_config_gpio(GPIO_USBOTG_ID);
/* First, register all of the class drivers needed to support the drivers
* that we care about
*/
#ifdef CONFIG_USBHOST_HUB
/* Initialize USB hub support */
ret = usbhost_hub_initialize();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: usbhost_hub_initialize failed: %d\n", ret);
}
#endif
#ifdef CONFIG_USBHOST_MSC
/* Register the USB host Mass Storage Class */
#ifdef CONFIG_XIDATONG_USB_AUTOMOUNT
/* Initialize the notifier listener for automount */
for (index = 0; index < CONFIG_XIDATONG_USB_AUTOMOUNT_NUM_BLKDEV; index++)
{
char sdchar = 'a' + index;
usbhost_msc_notifier_setup(usb_msc_connect,
WORK_USB_MSC_CONNECT, sdchar, (FAR void *)(intptr_t)index);
usbhost_msc_notifier_setup(usb_msc_disconnect,
WORK_USB_MSC_DISCONNECT, sdchar, (FAR void *)(intptr_t)index);
}
#endif
ret = usbhost_msc_initialize();
if (ret != OK)
{
syslog(LOG_ERR,
"ERROR: Failed to register the mass storage class: %d\n", ret);
}
#endif
#ifdef CONFIG_USBHOST_CDCACM
/* Register the CDC/ACM serial class */
ret = usbhost_cdcacm_initialize();
if (ret != OK)
{
uerr("ERROR: Failed to register the CDC/ACM serial class\n");
}
#endif
#ifdef CONFIG_USBHOST_HIDKBD
/* Register the USB host HID keyboard class driver */
ret = usbhost_kbdinit();
if (ret != OK)
{
uerr("ERROR: Failed to register the KBD class\n");
}
#endif
/* Then get an instance of the USB EHCI interface. */
g_ehciconn = imxrt_ehci_initialize(0);
if (!g_ehciconn)
{
uerr("ERROR: imxrt_ehci_initialize failed\n");
return -ENODEV;
}
/* Start a thread to handle device connection. */
pid = kthread_create("EHCI Monitor", CONFIG_USBHOST_DEFPRIO,
CONFIG_USBHOST_STACKSIZE,
(main_t)ehci_waiter, (FAR char * const *)NULL);
if (pid < 0)
{
uerr("ERROR: Failed to create ehci_waiter task: %d\n", ret);
return -ENODEV;
}
return OK;
}
/****************************************************************************
* Name: imxrt_usbhost_vbusdrive
*
* Description:
* Enable/disable driving of VBUS 5V output. This function must be
* provided by each platform that implements the OHCI or EHCI host
* interface
*
* Input Parameters:
* rhport - Selects root hub port to be powered host interface.
* Since the IMXRT has only a downstream port, zero is
* the only possible value for this parameter.
* enable - true: enable VBUS power; false: disable VBUS power
*
* Returned Value:
* None
*
****************************************************************************/
#define HCOR ((volatile struct ehci_hcor_s *)IMXRT_USBOTG_HCOR_BASE)
void imxrt_usbhost_vbusdrive(int rhport, bool enable)
{
uint32_t regval;
uinfo("RHPort%d: enable=%d\n", rhport + 1, enable);
/* The IMXRT has only a single root hub port */
if (rhport == 0)
{
/* Then enable or disable VBUS power */
regval = HCOR->portsc[rhport];
regval &= ~EHCI_PORTSC_PP;
if (enable)
{
regval |= EHCI_PORTSC_PP;
}
HCOR->portsc[rhport] = regval;
}
}
/****************************************************************************
* Name: imxrt_setup_overcurrent
*
* Description:
* Setup to receive an interrupt-level callback if an overcurrent condition
* is detected.
*
* Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument that will accompany the interrupt
*
* Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
****************************************************************************/
#if 0 /* Not ready yet */
int imxrt_setup_overcurrent(xcpt_t handler, void *arg)
{
irqstate_t flags;
/* Disable interrupts until we are done. This guarantees that the
* following operations are atomic.
*/
flags = enter_critical_section();
/* Configure the interrupt */
#warning Missing logic
leave_critical_section(flags);
return OK;
}
#endif /* 0 */
#endif /* CONFIG_IMXRT_USBOTG || CONFIG_USBHOST */

21
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/xidatong.h
View File

@ -41,9 +41,13 @@
#include <arch/irq.h>
#include <nuttx/irq.h>
#include <nuttx/sdio.h>
#include <nuttx/mmcsd.h>
#include "imxrt_gpio.h"
#include "imxrt_iomuxc.h"
#include "imxrt_usdhc.h"
#include <arch/board/board.h>
/****************************************************************************
* Pre-processor Definitions
@ -119,6 +123,10 @@
#define GPIO_MMCSD_EN (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | \
GPIO_PORT3 | GPIO_PIN2 | IOMUX_MMCSD_EN)
/* USB OTG ID Pin： GPIO_AD_B1_01 */
#define GPIO_USBOTG_ID (GPIO_USB_OTG1_ID_2 | IOMUX_USBOTG_ID_DEFAULT) /* GPIO_AD_B1_01 */
/****************************************************************************
* Public Types
****************************************************************************/
@ -198,5 +206,18 @@ void imxrt_autoled_initialize(void);
int imxrt_gpio_initialize(void);
#endif
#if defined(CONFIG_IMXRT_USBOTG) || defined(CONFIG_USBHOST)
int imxrt_usbhost_initialize(void);
#endif
#if defined(CONFIG_IMXRT_USBOTG) || defined(CONFIG_USBHOST)
int imxrt_mmcsd_initialize(void);
#endif
#ifdef CONFIG_XIDATONG_SDHC_AUTOMOUNT
int imxrt_sdhc_automount_event(void *arg);
void imxrt_automount_initialize(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_ARM_IMXRT_XIDATONG_SRC_XIDATONG_H */

1
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/build.sh
View File

@ -11,7 +11,6 @@ git submodule update Ubiquitous/Nuttx_Fusion_XiUOS/apps
git submodule update Ubiquitous/Nuttx_Fusion_XiUOS/nuttx
cd $current
chmod -R +x $top
find $top -name Kconfig -exec dos2unix -q {} \;
cp -rf $current/nuttx $nuttx

739
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/hardware/imxrt_usbotg.h Normal file
View File

@ -0,0 +1,739 @@
/****************************************************************************
* arch/arm/src/imxrt/hardware/imxrt_usbotg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USBOTG_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USBOTG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IMXRT_EHCI_NRHPORT 1 /* There is only a single root hub port */
/* USBOTG register offsets (with respect to IMXRT_USB_BASE) *****************/
/* 0x000 - 0x0ff: Reserved */
/* Device/host capability registers */
#define IMXRT_USBOTG_HCCR_OFFSET 0x100 /* Offset to EHCI Host Controller Capabiliy registers */
#define IMXRT_USBOTG_CAPLENGTH_OFFSET 0x100 /* Capability register length (8-bit) */
#define IMXRT_USBHOST_HCIVERSION_OFFSET 0x102 /* Host interface version number (16-bit) */
#define IMXRT_USBHOST_HCSPARAMS_OFFSET 0x104 /* Host controller structural parameters */
#define IMXRT_USBHOST_HCCPARAMS_OFFSET 0x108 /* Host controller capability parameters */
#define IMXRT_USBDEV_DCIVERSION_OFFSET 0x120 /* Device interface version number */
#define IMXRT_USBDEV_DCCPARAMS_OFFSET 0x124 /* Device controller capability parameters */
/* Device/host/OTG operational registers */
#define IMXRT_USBOTG_HCOR_OFFSET 0x140 /* Offset to EHCI Host Controller Operational Registers */
#define IMXRT_USBOTG_USBCMD_OFFSET 0x140 /* USB command (both) */
#define IMXRT_USBOTG_USBSTS_OFFSET 0x144 /* USB status (both) */
#define IMXRT_USBOTG_USBINTR_OFFSET 0x148 /* USB interrupt enable (both) */
#define IMXRT_USBOTG_FRINDEX_OFFSET 0x14c /* USB frame index (both) */
/* EHCI 4G Segment Selector (not supported) */
#define IMXRT_USBOTG_PERIODICLIST_OFFSET 0x154 /* Frame list base address (host) */
#define IMXRT_USBOTG_DEVICEADDR_OFFSET 0x154 /* USB device address (device) */
#define IMXRT_USBOTG_ASYNCLISTADDR_OFFSET 0x158 /* Next asynchronous list address (host) */
#define IMXRT_USBOTG_ENDPOINTLIST_OFFSET 0x158 /* Address of endpoint list in memory (device) */
#define IMXRT_USBOTG_TTCTRL_OFFSET 0x15c /* Asynchronous buffer status for embedded TT (host) */
#define IMXRT_USBOTG_BURSTSIZE_OFFSET 0x160 /* Programmable burst size (both) */
#define IMXRT_USBOTG_TXFILLTUNING_OFFSET 0x164 /* Host transmit pre-buffer packet tuning (host) */
#define IMXRT_USBOTG_BINTERVAL_OFFSET 0x174 /* Length of virtual frame (both) */
#define IMXRT_USBOTG_ENDPTNAK_OFFSET 0x178 /* Endpoint NAK (device) */
#define IMXRT_USBOTG_ENDPTNAKEN_OFFSET 0x17c /* Endpoint NAK Enable (device) */
#define IMXRT_USBOTG_CONFIGFLAG_OFFSET 0x180 /* Configured flag register (not used in lpc313x) */
#define IMXRT_USBOTG_PORTSC1_OFFSET 0x184 /* Port status/control 1 (both) */
#define IMXRT_USBOTG_OTGSC_OFFSET 0x1a4 /* OTG status and control (otg) */
#define IMXRT_USBOTG_USBMODE_OFFSET 0x1a8 /* USB device mode (both) */
#define IMXRT_USBDEV_USBCMD_OFFSET 0x140 /* USB command (both) */
#define IMXRT_USBDEV_USBSTS_OFFSET 0x144 /* USB status (both) */
#define IMXRT_USBDEV_USBINTR_OFFSET 0x148 /* USB interrupt enable (both) */
#define IMXRT_USBDEV_FRINDEX_OFFSET 0x14c /* USB frame index (both) */
#define IMXRT_USBDEV_DEVICEADDR_OFFSET 0x154 /* USB device address (device) */
#define IMXRT_USBDEV_ENDPOINTLIST_OFFSET 0x158 /* Address of endpoint list in memory (device) */
#define IMXRT_USBDEV_BURSTSIZE_OFFSET 0x160 /* Programmable burst size (both) */
#define IMXRT_USBDEV_BINTERVAL_OFFSET 0x174 /* Length of virtual frame (both) */
#define IMXRT_USBDEV_ENDPTNAK_OFFSET 0x178 /* Endpoint NAK (device) */
#define IMXRT_USBDEV_ENDPTNAKEN_OFFSET 0x17c /* Endpoint NAK Enable (device) */
#define IMXRT_USBDEV_PORTSC1_OFFSET 0x184 /* Port status/control 1 (both) */
#define IMXRT_USBDEV_USBMODE_OFFSET 0x1a8 /* USB device mode (both) */
#define IMXRT_USBHOST_USBCMD_OFFSET 0x140 /* USB command (both) */
#define IMXRT_USBHOST_USBSTS_OFFSET 0x144 /* USB status (both) */
#define IMXRT_USBHOST_USBINTR_OFFSET 0x148 /* USB interrupt enable (both) */
#define IMXRT_USBHOST_FRINDEX_OFFSET 0x14c /* USB frame index (both) */
#define IMXRT_USBHOST_PERIODICLIST_OFFSET 0x154 /* Frame list base address (host) */
#define IMXRT_USBHOST_ASYNCLISTADDR_OFFSET 0x158 /* Next asynchronous list address (host) */
#define IMXRT_USBHOST_TTCTRL_OFFSET 0x15c /* Asynchronous buffer status for embedded TT (host) */
#define IMXRT_USBHOST_BURSTSIZE_OFFSET 0x160 /* Programmable burst size (both) */
#define IMXRT_USBHOST_TXFILLTUNING_OFFSET 0x164 /* Host transmit pre-buffer packet tuning (host) */
#define IMXRT_USBHOST_BINTERVAL_OFFSET 0x174 /* Length of virtual frame (both) */
#define IMXRT_USBHOST_PORTSC1_OFFSET 0x184 /* Port status/control 1 (both) */
#define IMXRT_USBHOST_USBMODE_OFFSET 0x1a8 /* USB device mode (both) */
/* Device endpoint registers */
#define IMXRT_USBDEV_ENDPTSETUPSTAT_OFFSET 0x1ac /* Endpoint setup status */
#define IMXRT_USBDEV_ENDPTPRIME_OFFSET 0x1b0 /* Endpoint initialization */
#define IMXRT_USBDEV_ENDPTFLUSH_OFFSET 0x1b4 /* Endpoint de-initialization */
#define IMXRT_USBDEV_ENDPTSTATUS_OFFSET 0x1b8 /* Endpoint status */
#define IMXRT_USBDEV_ENDPTCOMPLETE_OFFSET 0x1bc /* Endpoint complete */
#define IMXRT_USBDEV_ENDPTCTRL_OFFSET(n) (IMXRT_USBDEV_ENDPTCTRL0_OFFSET + ((n) * 4))
#define IMXRT_USBDEV_ENDPTCTRL0_OFFSET 0x1c0 /* Endpoint control 0 */
#define IMXRT_USBDEV_ENDPTCTRL1_OFFSET 0x1c4 /* Endpoint control 1 */
#define IMXRT_USBDEV_ENDPTCTRL2_OFFSET 0x1c8 /* Endpoint control 2 */
#define IMXRT_USBDEV_ENDPTCTRL3_OFFSET 0x1cc /* Endpoint control 3 */
#define IMXRT_USBDEV_ENDPTCTRL4_OFFSET 0x1d0 /* Endpoint control 4 */
#define IMXRT_USBDEV_ENDPTCTRL5_OFFSET 0x1d4 /* Endpoint control 5 */
#define IMXRT_USBDEV_ENDPTCTRL6_OFFSET 0x1d8 /* Endpoint control 6 */
#define IMXRT_USBDEV_ENDPTCTRL7_OFFSET 0x1dc /* Endpoint control 7 */
/* USB Non-core memory map & register definition */
#define IMXRT_USBNC_USB_OTG1_CTRL_OFFSET 0x0800 /* OTG1 Control Register */
#define IMXRT_USBNC_USB_OTG2_CTRL_OFFSET 0x0800 /* OTG2 Control Register */
#define IMXRT_USBNC_USB_OTG1_PHY_CTRL_0_OFFSET 0x0818 /* OTG1 Phy Control Register */
#define IMXRT_USBNC_USB_OTG2_PHY_CTRL_0_OFFSET 0x0818 /* OTG2 Phy Control Register */
/* USBOTG register (virtual) addresses **************************************/
/* Device/host capability registers */
#define IMXRT_USBOTG_HCCR_BASE (IMXRT_USB_BASE + IMXRT_USBOTG_HCCR_OFFSET)
#define IMXRT_USBOTG_CAPLENGTH (IMXRT_USB_BASE + IMXRT_USBOTG_CAPLENGTH_OFFSET)
#define IMXRT_USBHOST_HCIVERSION (IMXRT_USB_BASE + IMXRT_USBHOST_HCIVERSION_OFFSET)
#define IMXRT_USBHOST_HCSPARAMS (IMXRT_USB_BASE + IMXRT_USBHOST_HCSPARAMS_OFFSET)
#define IMXRT_USBHOST_HCCPARAMS (IMXRT_USB_BASE + IMXRT_USBHOST_HCCPARAMS_OFFSET)
#define IMXRT_USBDEV_DCIVERSION (IMXRT_USB_BASE + IMXRT_USBDEV_DCIVERSION_OFFSET)
#define IMXRT_USBDEV_DCCPARAMS (IMXRT_USB_BASE + IMXRT_USBDEV_DCCPARAMS_OFFSET)
/* Device/host operational registers */
#define IMXRT_USBOTG_HCOR_BASE (IMXRT_USB_BASE + IMXRT_USBOTG_HCOR_OFFSET)
#define IMXRT_USBOTG_USBCMD (IMXRT_USB_BASE + IMXRT_USBOTG_USBCMD_OFFSET)
#define IMXRT_USBOTG_USBSTS (IMXRT_USB_BASE + IMXRT_USBOTG_USBSTS_OFFSET)
#define IMXRT_USBOTG_USBINTR (IMXRT_USB_BASE + IMXRT_USBOTG_USBINTR_OFFSET)
#define IMXRT_USBOTG_FRINDEX (IMXRT_USB_BASE + IMXRT_USBOTG_FRINDEX_OFFSET)
#define IMXRT_USBOTG_PERIODICLIST (IMXRT_USB_BASE + IMXRT_USBOTG_PERIODICLIST_OFFSET)
#define IMXRT_USBOTG_DEVICEADDR (IMXRT_USB_BASE + IMXRT_USBOTG_DEVICEADDR_OFFSET)
#define IMXRT_USBOTG_ASYNCLISTADDR (IMXRT_USB_BASE + IMXRT_USBOTG_ASYNCLISTADDR_OFFSET)
#define IMXRT_USBOTG_ENDPOINTLIST (IMXRT_USB_BASE + IMXRT_USBOTG_ENDPOINTLIST_OFFSET)
#define IMXRT_USBOTG_TTCTRL (IMXRT_USB_BASE + IMXRT_USBOTG_TTCTRL_OFFSET)
#define IMXRT_USBOTG_BURSTSIZE (IMXRT_USB_BASE + IMXRT_USBOTG_BURSTSIZE_OFFSET)
#define IMXRT_USBOTG_TXFILLTUNING (IMXRT_USB_BASE + IMXRT_USBOTG_TXFILLTUNING_OFFSET)
#define IMXRT_USBOTG_BINTERVAL (IMXRT_USB_BASE + IMXRT_USBOTG_BINTERVAL_OFFSET)
#define IMXRT_USBOTG_ENDPTNAK (IMXRT_USB_BASE + IMXRT_USBOTG_ENDPTNAK_OFFSET)
#define IMXRT_USBOTG_ENDPTNAKEN (IMXRT_USB_BASE + IMXRT_USBOTG_ENDPTNAKEN_OFFSET)
#define IMXRT_USBOTG_PORTSC1 (IMXRT_USB_BASE + IMXRT_USBOTG_PORTSC1_OFFSET)
#define IMXRT_USBOTG_OTGSC (IMXRT_USB_BASE + IMXRT_USBOTG_OTGSC_OFFSET)
#define IMXRT_USBOTG_USBMODE (IMXRT_USB_BASE + IMXRT_USBOTG_USBMODE_OFFSET)
#define IMXRT_USBDEV_USBCMD (IMXRT_USB_BASE + IMXRT_USBDEV_USBCMD_OFFSET)
#define IMXRT_USBDEV_USBSTS (IMXRT_USB_BASE + IMXRT_USBDEV_USBSTS_OFFSET)
#define IMXRT_USBDEV_USBINTR (IMXRT_USB_BASE + IMXRT_USBDEV_USBINTR_OFFSET)
#define IMXRT_USBDEV_FRINDEX (IMXRT_USB_BASE + IMXRT_USBDEV_FRINDEX_OFFSET)
#define IMXRT_USBDEV_DEVICEADDR (IMXRT_USB_BASE + IMXRT_USBDEV_DEVICEADDR_OFFSET)
#define IMXRT_USBDEV_ENDPOINTLIST (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPOINTLIST_OFFSET)
#define IMXRT_USBDEV_BURSTSIZE (IMXRT_USB_BASE + IMXRT_USBDEV_BURSTSIZE_OFFSET)
#define IMXRT_USBDEV_BINTERVAL (IMXRT_USB_BASE + IMXRT_USBDEV_BINTERVAL_OFFSET)
#define IMXRT_USBDEV_ENDPTNAK (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTNAK_OFFSET)
#define IMXRT_USBDEV_ENDPTNAKEN (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTNAKEN_OFFSET)
#define IMXRT_USBDEV_PORTSC1 (IMXRT_USB_BASE + IMXRT_USBDEV_PORTSC1_OFFSET)
#define IMXRT_USBDEV_USBMODE (IMXRT_USB_BASE + IMXRT_USBDEV_USBMODE_OFFSET)
#define IMXRT_USBHOST_USBCMD (IMXRT_USB_BASE + IMXRT_USBHOST_USBCMD_OFFSET)
#define IMXRT_USBHOST_USBSTS (IMXRT_USB_BASE + IMXRT_USBHOST_USBSTS_OFFSET)
#define IMXRT_USBHOST_USBINTR (IMXRT_USB_BASE + IMXRT_USBHOST_USBINTR_OFFSET)
#define IMXRT_USBHOST_FRINDEX (IMXRT_USB_BASE + IMXRT_USBHOST_FRINDEX_OFFSET)
#define IMXRT_USBHOST_PERIODICLIST (IMXRT_USB_BASE + IMXRT_USBHOST_PERIODICLIST_OFFSET)
#define IMXRT_USBHOST_ASYNCLISTADDR (IMXRT_USB_BASE + IMXRT_USBHOST_ASYNCLISTADDR_OFFSET)
#define IMXRT_USBHOST_TTCTRL (IMXRT_USB_BASE + IMXRT_USBHOST_TTCTRL_OFFSET)
#define IMXRT_USBHOST_BURSTSIZE (IMXRT_USB_BASE + IMXRT_USBHOST_BURSTSIZE_OFFSET)
#define IMXRT_USBHOST_TXFILLTUNING (IMXRT_USB_BASE + IMXRT_USBHOST_TXFILLTUNING_OFFSET)
#define IMXRT_USBHOST_BINTERVAL (IMXRT_USB_BASE + IMXRT_USBHOST_BINTERVAL_OFFSET)
#define IMXRT_USBHOST_PORTSC1 (IMXRT_USB_BASE + IMXRT_USBHOST_PORTSC1_OFFSET)
#define IMXRT_USBHOST_USBMODE (IMXRT_USB_BASE + IMXRT_USBHOST_USBMODE_OFFSET)
/* Device endpoint registers */
#define IMXRT_USBDEV_ENDPTSETUPSTAT (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTSETUPSTAT_OFFSET)
#define IMXRT_USBDEV_ENDPTPRIME (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTPRIME_OFFSET)
#define IMXRT_USBDEV_ENDPTFLUSH (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTFLUSH_OFFSET)
#define IMXRT_USBDEV_ENDPTSTATUS (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTSTATUS_OFFSET)
#define IMXRT_USBDEV_ENDPTCOMPLETE (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCOMPLETE_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL(n) (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL_OFFSET(n))
#define IMXRT_USBDEV_ENDPTCTRL0 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL0_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL1 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL1_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL2 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL2_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL3 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL3_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL4 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL4_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL5 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL5_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL6 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL6_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL7 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL7_OFFSET)
/* Device non-core registers */
#define IMXRT_USBNC_USB_OTG1_CTRL (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG1_CTRL_OFFSET)
#define IMXRT_USBNC_USB_OTG1_PHY_CTRL_0 (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG1_PHY_CTRL_0_OFFSET)
#define IMXRT_USBNC_USB_OTG2_CTRL (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG2_CTRL_OFFSET)
#define IMXRT_USBNC_USB_OTG2_PHY_CTRL_0 (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG2_PHY_CTRL_0_OFFSET)
/* USBOTG register bit definitions ******************************************/
/* Device/host capability registers */
/* CAPLENGTH */
#define USBOTG_CAPLENGTH_SHIFT (0) /* Bits 0-7: Offset from register base to operational regs */
#define USBOTG_CAPLENGTH_MASK (0xff << USBOTG_CAPLENGTH_SHIFT)
/* HCIVERSION */
#define USBHOST_HCIVERSION_SHIFT (0) /* Bits 0-15: BCD encoding of the EHCI revision number */
#define USBHOST_HCIVERSION_MASK (0xffff << USBHOST_HCIVERSION_SHIFT)
/* HCSPARAMS */
#define USBHOST_HCSPARAMS_NTT_SHIFT (24) /* Bits 24-27: Number of Transaction Translators */
#define USBHOST_HCSPARAMS_NTT_MASK (15 << USBHOST_HCSPARAMS_NTT_SHIFT)
#define USBHOST_HCSPARAMS_NPTT_SHIFT (20) /* Bits 20-23: Number of Ports per Transaction Translator */
#define USBHOST_HCSPARAMS_NPTT_MASK (15 << USBHOST_HCSPARAMS_NPTT_SHIFT)
#define USBHOST_HCSPARAMS_PI (1 >> 16) /* Bit 16: Port indicators */
#define USBHOST_HCSPARAMS_NCC_SHIFT (15) /* Bits 12-15: Number of Companion Controller */
#define USBHOST_HCSPARAMS_NCC_MASK (15 << USBHOST_HCSPARAMS_NCC_SHIFT)
#define USBHOST_HCSPARAMS_NPCC_SHIFT (8) /* Bits 8-11: Number of Ports per Companion Controller */
#define USBHOST_HCSPARAMS_NPCC_MASK (15 << USBHOST_HCSPARAMS_NPCC_SHIFT)
#define USBHOST_HCSPARAMS_PPC (1 >> 4) /* Bit 4: Port Power Control */
#define USBHOST_HCSPARAMS_NPORTS_SHIF (0) /* Bits 0-3: Number of downstream ports */
#define USBHOST_HCSPARAMS_NPORTS_MASK (15 << USBHOST_HCSPARAMS_NPORTS_SHIFT)
/* HCCPARAMS */
#define USBHOST_HCCPARAMS_EECP_SHIFT (8) /* Bits 8-15: EHCI Extended Capabilities Pointer */
#define USBHOST_HCCPARAMS_EECP_MASK (255 << USBHOST_HCCPARAMS_EECP_SHIFT)
#define USBHOST_HCCPARAMS_IST_SHIFT (4) /* Bits 4-7: Isochronous Scheduling Threshold */
#define USBHOST_HCCPARAMS_IST_MASK (15 << USBHOST_HCCPARAMS_IST_SHIFT)
#define USBHOST_HCCPARAMS_ASP (1 >> 2) /* Bit 2: Asynchronous Schedule Park Capability */
#define USBHOST_HCCPARAMS_PFL (1 >> 1) /* Bit 1: Programmable Frame List Flag */
#define USBHOST_HCCPARAMS_ADC (1 >> 0) /* Bit 0: 64-bit Addressing Capability */
/* DCIVERSION */
#define USBDEV_DCIVERSION_SHIFT (0) /* Bits 0-15: BCD encoding of the device interface */
#define USBDEV_DCIVERSION_MASK (0xffff << USBDEV_DCIVERSION_SHIFT)
/* DCCPARAMS */
#define USBDEV_DCCPARAMS_HC (1 >> 8) /* Bit 8: Host Capable */
#define USBDEV_DCCPARAMS_DC (1 >> 7) /* Bit 7: Device Capable */
#define USBDEV_DCCPARAMS_DEN_SHIFT (0) /* Bits 0-4: DEN Device Endpoint Number */
#define USBDEV_DCCPARAMS_DEN_MASK (31 << USBDEV_DCCPARAMS_DEN_SHIFT)
/* Device/host operational registers */
/* USB Command register USBCMD -- Device Mode */
#define USBDEV_USBCMD_ITC_SHIFT (16) /* Bits 16-23: Interrupt threshold control */
#define USBDEV_USBCMD_ITC_MASK (255 << USBDEV_USBCMD_ITC_SHIFT)
# define USBDEV_USBCMD_ITCIMME (0 << USBDEV_USBCMD_ITC_SHIFT) /* Immediate (no threshold) */
# define USBDEV_USBCMD_ITC1UF (1 << USBDEV_USBCMD_ITC_SHIFT) /* 1 micro frame */
# define USBDEV_USBCMD_ITC2UF (2 << USBDEV_USBCMD_ITC_SHIFT) /* 2 micro frames */
# define USBDEV_USBCMD_ITC4UF (4 << USBDEV_USBCMD_ITC_SHIFT) /* 4 micro frames */
# define USBDEV_USBCMD_ITC8UF (8 << USBDEV_USBCMD_ITC_SHIFT) /* 8 micro frames */
# define USBDEV_USBCMD_ITC16UF (16 << USBDEV_USBCMD_ITC_SHIFT) /* 16 micro frames */
# define USBDEV_USBCMD_ITC32UF (32 << USBDEV_USBCMD_ITC_SHIFT) /* 32 micro frames */
# define USBDEV_USBCMD_ITC64UF (64 << USBDEV_USBCMD_ITC_SHIFT) /* 64 micro frames */
#define USBDEV_USBCMD_ATDTW (1 << 14) /* Bit 14: Add dTD trip wire */
#define USBDEV_USBCMD_SUTW (1 << 13) /* Bit 13: Setup trip wire */
#define USBDEV_USBCMD_RST (1 << 1) /* Bit 1: 1 Controller reset */
#define USBDEV_USBCMD_RS (1 << 0) /* Bit 0: 0 Run/Stop */
/* USB Command register USBCMD -- Host Mode */
#define USBHOST_USBCMD_ITC_SHIFT (16) /* Bits 16-13: Interrupt threshold control */
#define USBHOST_USBCMD_ITC_MASK (255 << USBHOST_USBCMD_ITC_SHIFT)
# define USBHOST_USBCMD_ITCIMMED (0 << USBHOST_USBCMD_ITC_SHIFT) /* Immediate (no threshold) */
# define USBHOST_USBCMD_ITC1UF (1 << USBHOST_USBCMD_ITC_SHIFT) /* 1 micro frame */
# define USBHOST_USBCMD_ITC2UF (2 << USBHOST_USBCMD_ITC_SHIFT) /* 2 micro frames */
# define USBHOST_USBCMD_ITC4UF (4 << USBHOST_USBCMD_ITC_SHIFT) /* 4 micro frames */
# define USBHOST_USBCMD_ITC8UF (8 << USBHOST_USBCMD_ITC_SHIFT) /* 8 micro frames */
# define USBHOST_USBCMD_ITC16UF (16 << USBHOST_USBCMD_ITC_SHIFT) /* 16 micro frames */
# define USBHOST_USBCMD_ITC32UF (32 << USBHOST_USBCMD_ITC_SHIFT) /* 32 micro frames */
# define USBHOST_USBCMD_ITC64UF (64 << USBHOST_USBCMD_ITC_SHIFT) /* 64 micro frames */
#define USBHOST_USBCMD_FS2 (1 << 15) /* Bit 15: Bit 2 of the Frame List Size bits */
#define USBHOST_USBCMD_ASPE (1 << 11) /* Bit 11: Asynchronous Schedule Park Mode Enable */
#define USBHOST_USBCMD_ASP_SHIFT (8) /* Bits 8-9: Asynchronous schedule park mode */
#define USBHOST_USBCMD_ASP_MASK (3 << USBHOST_USBCMD_ASP_SHIFT)
#define USBHOST_USBCMD_IAA (1 << 6) /* Bit 6: Interrupt next asynchronous schedule */
#define USBHOST_USBCMD_ASE (1 << 5) /* Bit 5: Skips processing asynchronous schedule */
#define USBHOST_USBCMD_PSE (1 << 4) /* Bit 4: Skips processing periodic schedule */
#define USBHOST_USBCMD_FS1 (1 << 3) /* Bit 3: Bit 1 of the Frame List Size bits */
#define USBHOST_USBCMD_FS0 (1 << 2) /* Bit 2: Bit 0 of the Frame List Size bits */
#define USBHOST_USBCMD_RST (1 << 1) /* Bit 1: Controller reset */
#define USBHOST_USBCMD_RS (1 << 0) /* Bit 0: Run/Stop */
/* USB Status register USBSTS -- Device Mode */
#define USBDEV_USBSTS_NAKI (1 << 16) /* Bit 16: NAK interrupt bit */
#define USBDEV_USBSTS_SLI (1 << 8) /* Bit 8: DCSuspend */
#define USBDEV_USBSTS_SRI (1 << 7) /* Bit 7: SOF received */
#define USBDEV_USBSTS_URI (1 << 6) /* Bit 6: USB reset received */
#define USBDEV_USBSTS_PCI (1 << 2) /* Bit 2: Port change detect */
#define USBDEV_USBSTS_UEI (1 << 1) /* Bit 1: USB error interrupt */
#define USBDEV_USBSTS_UI (1 << 0) /* Bit 0: USB interrupt */
/* USB Status register USBSTS -- Host Mode */
#define USBHOST_USBSTS_UPI (1 << 19) /* Bit 19: USB host periodic interrupt */
#define USBHOST_USBSTS_UAI (1 << 18) /* Bit 18: USB host asynchronous interrupt */
#define USBHOST_USBSTS_AS (1 << 15) /* Bit 15: Asynchronous schedule status */
#define USBHOST_USBSTS_PS (1 << 14) /* Bit 14: Periodic schedule status */
#define USBHOST_USBSTS_RCL (1 << 13) /* Bit 13: Reclamation */
#define USBHOST_USBSTS_HCH (1 << 12) /* Bit 12: HCHalted */
#define USBHOST_USBSTS_SRI (1 << 7) /* Bit 7: SOF received */
#define USBHOST_USBSTS_AAI (1 << 5) /* Bit 5: Interrupt on async advance */
#define USBHOST_USBSTS_FRI (1 << 3) /* Bit 3: Frame list roll-over */
#define USBHOST_USBSTS_PCI (1 << 2) /* Bit 2: Port change detect */
#define USBHOST_USBSTS_UEI (1 << 1) /* Bit 1: USB error interrupt */
#define USBHOST_USBSTS_UI (1 << 0) /* Bit 0: USB interrupt */
/* USB interrupt register USBINTR -- Device Mode */
#define USBDEV_USBINTR_NAKE (1 << 16) /* Bit 16: NAK interrupt enable */
#define USBDEV_USBINTR_SLE (1 << 8) /* Bit 8: Sleep enable */
#define USBDEV_USBINTR_SRE (1 << 7) /* Bit 7: SOF received enable */
#define USBDEV_USBINTR_URE (1 << 6) /* Bit 6: USB reset enable */
#define USBDEV_USBINTR_PCE (1 << 2) /* Bit 2: Port change detect enable */
#define USBDEV_USBINTR_UEE (1 << 1) /* Bit 1: USB error interrupt enable */
#define USBDEV_USBINTR_UE (1 << 0) /* Bit 0: USB interrupt enable */
/* USB interrupt register USBINTR (address 0x19000148) -- Host Mode */
#define USBHOST_USBINTR_UPIA (1 << 19) /* Bit 19: USB host periodic interrupt enable */
#define USBHOST_USBINTR_UAIE (1 << 18) /* Bit 18: USB host asynchronous interrupt enable */
#define USBHOST_USBINTR_SRE (1 << 7) /* Bit 7: SOF timer interrupt enable */
#define USBHOST_USBINTR_AAE (1 << 5) /* Bit 5: Interrupt on asynchronous advance enable */
#define USBHOST_USBINTR_FRE (1 << 3) /* Bit 3: Frame list rollover enable */
#define USBHOST_USBINTR_PCE (1 << 2) /* Bit 2: Port change detect enable */
#define USBHOST_USBINTR_UEE (1 << 1) /* Bit 1: USB error interrupt enable */
#define USBHOST_USBINTR_UE (1 << 0) /* Bit 0: USB interrupt enable */
/* Frame index register FRINDEX -- Device Mode */
#define USBDEV_FRINDEX_LFN_SHIFT (3) /* Bits 3-13: Frame number of last frame transmitted */
#define USBDEV_FRINDEX_LFN_MASK (0x7ff << USBDEV_FRINDEX_LFN_SHIFT)
#define USBDEV_FRINDEX_CUFN_SHIFT (0) /* Bits 0-2: Current micro frame number */
#define USBDEV_FRINDEX_CUFN_MASK (7 << USBDEV_FRINDEX_CUFN_SHIFT)
/* Frame index register FRINDEX -- Host Mode */
#define USBHOST_FRINDEX_FLI_SHIFT (3) /* Bits 3-13: Frame list current index */
#define USBHOST_FRINDEX_FLI_MASK(n) (0x7ff << ((n) + USBHOST_FRINDEX_FLI_SHIFT - 1)
#define USBHOST_FRINDEX_CUFN_SHIFT (0) /* Bits 0-2: Current micro frame number */
#define USBHOST_FRINDEX_CUFN_MASK (7 << USBHOST_FRINDEX_CUFN_SHIFT)
/* USB Device Address register DEVICEADDR -- Device Mode */
#define USBDEV_DEVICEADDR_SHIFT (25) /* Bits 25-31: USBADR USB device address */
#define USBDEV_DEVICEADDR_MASK (0x3c << USBDEV_DEVICEADDR_SHIFT)
#define USBDEV_DEVICEADDR_USBADRA (1 << 24) /* Bit 24: Device address advance */
/* USB Periodic List Base register PERIODICLIST -- Host Mode */
#define USBHOST_PERIODICLIST_PERBASE_SHIFT (12) /* Bits 12-31: Base Address (Low) */
#define USBHOST_PERIODICLIST_PERBASE_MASK (0x000fffff << USBHOST_PERIODICLIST_PERBASE_SHIFT)
/* USB Endpoint List Address register ENDPOINTLISTADDR -- Device Mode */
#define USBDEV_ENDPOINTLIST_EPBASE_SHIFT (11) /* Bits 11-31: Endpoint list pointer (low) */
#define USBDEV_ENDPOINTLIST_EPBASE_MASK (0x001fffff << USBDEV_ENDPOINTLIST_EPBASE_SHIFT)
/* USB Asynchronous List Address register ASYNCLISTADDR -- Host Mode */
#define USBHOST_ASYNCLISTADDR_ASYBASE_SHIFT (5) /* Bits 5-31: Link pointer (Low) LPL */
#define USBHOST_ASYNCLISTADDR_ASYBASE_MASK (0x07ffffff << USBHOST_ASYNCLISTADDR_ASYBASE_SHIFT)
/* USB TT Control register TTCTRL (address 0x1900015c) -- Host Mode */
#define USBHOST_TTCTRL_TTHA_SHIFT (24) /* Bits 24-30: Hub address */
#define USBHOST_TTCTRL_TTHA_MASK (0x7f << USBHOST_TTCTRL_TTHA_SHIFT)
/* USB burst size register BURSTSIZE -- Device/Host Mode */
#define USBDEV_BURSTSIZE_TXPBURST_SHIFT (8) /* Bits 8-15: Programmable TX burst length */
#define USBDEV_BURSTSIZE_TXPBURST_MASK (255 << USBDEV_BURSTSIZE_TXPBURST_SHIFT)
#define USBDEV_BURSTSIZE_RXPBURST_SHIFT (0) /* Bits 0-7: RXPBURST Programmable RX burst length */
#define USBDEV_BURSTSIZE_RXPBURST_MASK (255 << USBDEV_BURSTSIZE_RXPBURST_SHIFT)
#define USBHOST_BURSTSIZE_TXPBURST_SHIFT (8) /* Bits 8-15: Programmable TX burst length */
#define USBHOST_BURSTSIZE_TXPBURST_MASK (255 << USBHOST_BURSTSIZE_TXPBURST_SHIFT)
#define USBHOST_BURSTSIZE_RXPBURST_SHIFT (0) /* Bits 0-7: RXPBURST Programmable RX burst length */
#define USBHOST_BURSTSIZE_RXPBURST_MASK (255 << USBHOST_BURSTSIZE_RXPBURST_SHIFT)
/* USB Transfer buffer Fill Tuning register TXFIFOFILLTUNING -- Host Mode */
#define USBHOST_TXFILLTUNING_FIFOTHRES_SHIFT (16) /* Bits 16-21: Scheduler overhead */
#define USBHOST_TXFILLTUNING_FIFOTHRES_MASK (0x3c << USBHOST_TXFILLTUNING_FIFOTHRES_SHIFT)
#define USBHOST_TXFILLTUNING_SCHEATLTH_SHIFT (8) /* Bits 8-12: Scheduler health counter */
#define USBHOST_TXFILLTUNING_SCHEATLTH_MASK (0x1f << USBHOST_TXFILLTUNING_SCHEATLTH_SHIFT)
#define USBHOST_TXFILLTUNING_SCHOH_SHIFT (0) /* Bits 0-7: FIFO burst threshold */
#define USBHOST_TXFILLTUNING_SCHOH_MASK (0xff << USBHOST_TXFILLTUNING_SCHOH_SHIFT)
/* USB BINTERVAL register BINTERVAL -- Device/Host Mode */
#define USBDEV_BINTERVAL_SHIFT (0) /* Bits 0-3: bInterval value */
#define USBDEV_BINTERVAL_MASK (15 << USBDEV_BINTERVAL_SHIFT)
#define USBHOST_BINTERVAL_SHIFT (0) /* Bits 0-3: bInterval value */
#define USBHOST_BINTERVAL_MASK (15 << USBHOST_BINTERVAL_SHIFT)
/* USB endpoint NAK register ENDPTNAK -- Device Mode */
#define USBDEV_ENDPTNAK_EPTN_SHIFT (16) /* Bits 16-19: Tx endpoint NAK */
#define USBDEV_ENDPTNAK_EPTN_MASK (15 << USBDEV_ENDPTNAK_EPTN_SHIFT)
#define USBDEV_ENDPTNAK_EPRN_SHIFT (0) /* Bits 0-3: Rx endpoint NAK */
#define USBDEV_ENDPTNAK_EPRN_MASK (15 << USBDEV_ENDPTNAK_EPRN_SHIFT)
/* USB Endpoint NAK Enable register ENDPTNAKEN -- Device Mode */
#define USBDEV_ENDPTNAK_EPTNE_SHIFT (16) /* Bits 16-19: Tx endpoint NAK enable */
#define USBDEV_ENDPTNAK_EPTNE_MASK (15 << USBDEV_ENDPTNAK_EPTNE_SHIFT)
#define USBDEV_ENDPTNAK_EPRNE_SHIFT (0) /* Bits 0-3: Rx endpoint NAK enable */
#define USBDEV_ENDPTNAK_EPRNE_MASK (15 << USBDEV_ENDPTNAK_EPRNE_SHIFT)
/* Port Status and Control register PRTSC1 -- Device Mode */
#define USBDEV_PRTSC1_PSPD_SHIFT (26) /* Bits 26-27: Port speed */
#define USBDEV_PRTSC1_PSPD_MASK (3 << USBDEV_PRTSC1_PSPD_SHIFT)
# define USBDEV_PRTSC1_PSPD_FS (0 << USBDEV_PRTSC1_PSPD_SHIFT) /* Full-speed */
# define USBDEV_PRTSC1_PSPD_LS (1 << USBDEV_PRTSC1_PSPD_SHIFT) /* Low-speed */
# define USBDEV_PRTSC1_PSPD_HS (2 << USBDEV_PRTSC1_PSPD_SHIFT) /* High-speed */
#define USBDEV_PRTSC1_PFSC (1 << 24) /* Bit 24: Port force full speed connect */
#define USBDEV_PRTSC1_PHCD (1 << 23) /* Bit 23: PHY low power suspend - clock disable (PLPSCD) */
#define USBDEV_PRTSC1_PTC_SHIFT (16) /* Bits 16-19: 19: Port test control */
#define USBDEV_PRTSC1_PTC_MASK (15 << USBDEV_PRTSC1_PTC_SHIFT)
# define USBDEV_PRTSC1_PTC_DISABLE (0 << USBDEV_PRTSC1_PTC_SHIFT) /* TEST_MODE_DISABLE */
# define USBDEV_PRTSC1_PTC_JSTATE (1 << USBDEV_PRTSC1_PTC_SHIFT) /* J_STATE */
# define USBDEV_PRTSC1_PTC_KSTATE (2 << USBDEV_PRTSC1_PTC_SHIFT) /* K_STATE */
# define USBDEV_PRTSC1_PTC_SE0 (3 << USBDEV_PRTSC1_PTC_SHIFT) /* SE0 (host)/NAK (device) */
# define USBDEV_PRTSC1_PTC_PACKET (4 << USBDEV_PRTSC1_PTC_SHIFT) /* Packet */
# define USBDEV_PRTSC1_PTC_HS (5 << USBDEV_PRTSC1_PTC_SHIFT) /* FORCE_ENABLE_HS */
# define USBDEV_PRTSC1_PTC_FS (6 << USBDEV_PRTSC1_PTC_SHIFT) /* FORCE_ENABLE_FS */
#define USBDEV_PRTSC1_PIC_SHIFT (14) /* Bits 14-15: Port indicator control */
#define USBDEV_PRTSC1_PIC_MASK (3 << USBDEV_PRTSC1_PIC_SHIFT)
# define USBDEV_PRTSC1_PIC_OFF (0 << USBDEV_PRTSC1_PIC_SHIFT) /* 00 Port indicators are off */
# define USBDEV_PRTSC1_PIC_AMBER (1 << USBDEV_PRTSC1_PIC_SHIFT) /* 01 amber */
# define USBDEV_PRTSC1_PIC_GREEN (2 << USBDEV_PRTSC1_PIC_SHIFT) /* 10 green */
#define USBDEV_PRTSC1_HSP (1 << 9) /* Bit 9: High-speed status */
#define USBDEV_PRTSC1_PR (1 << 8) /* Bit 8: Port reset */
#define USBDEV_PRTSC1_SUSP (1 << 7) /* Bit 7: Suspend */
#define USBDEV_PRTSC1_FPR (1 << 6) /* Bit 6: Force port resume */
#define USBDEV_PRTSC1_PEC (1 << 3) /* Bit 3: Port enable/disable change */
#define USBDEV_PRTSC1_PE (1 << 2) /* Bit 2: Port enable */
#define USBDEV_PRTSC1_CCS (1 << 0) /* Bit 0: Current connect status */
/* Port Status and Control register PRTSC1 -- Host Mode */
#define USBHOST_PRTSC1_PSPD_SHIFT (26) /* Bits 26-27: Port speed */
#define USBHOST_PRTSC1_PSPD_MASK (3 << USBHOST_PRTSC1_PSPD_SHIFT)
# define USBHOST_PRTSC1_PSPD_FS (0 << USBHOST_PRTSC1_PSPD_SHIFT) /* Full-speed */
# define USBHOST_PRTSC1_PSPD_LS (1 << USBHOST_PRTSC1_PSPD_SHIFT) /* Low-speed */
# define USBHOST_PRTSC1_PSPD_HS (2 << USBHOST_PRTSC1_PSPD_SHIFT) /* High-speed */
#define USBHOST_PRTSC1_PFSC (1 << 24) /* Bit 24: Port force full speed connect */
#define USBHOST_PRTSC1_PHCD (1 << 23) /* Bit 23: PHY low power suspend - clock disable (PLPSCD) */
#define USBHOST_PRTSC1_WKOC (1 << 22) /* Bit 22: Wake on over-current enable (WKOC_E) */
#define USBHOST_PRTSC1_WKDC (1 << 21) /* Bit 21: Wake on disconnect enable (WKDSCNNT_E) */
#define USBHOST_PRTSC1_WKCN (1 << 20) /* Bit 20: Wake on connect enable (WKCNNT_E) */
#define USBHOST_PRTSC1_PTC_SHIFT (16) /* Bits 16-19: Port test control */
#define USBHOST_PRTSC1_PTC_MASK (15 << USBHOST_PRTSC1_PTC_SHIFT)
# define USBHOST_PRTSC1_PTC_DISABLE (0 << USBHOST_PRTSC1_PTC_SHIFT) /* 0000 TEST_MODE_DISABLE */
# define USBHOST_PRTSC1_PTC_JSTATE (1 << USBHOST_PRTSC1_PTC_SHIFT) /* 0001 J_STATE */
# define USBHOST_PRTSC1_PTC_KSTATE (2 << USBHOST_PRTSC1_PTC_SHIFT) /* 0010 K_STATE */
# define USBHOST_PRTSC1_PTC_SE0 (3 << USBHOST_PRTSC1_PTC_SHIFT) /* 0011 SE0 (host)/NAK (device) */
# define USBHOST_PRTSC1_PTC_PACKET (4 << USBHOST_PRTSC1_PTC_SHIFT) /* 0100 Packet */
# define USBHOST_PRTSC1_PTC_HS (5 << USBHOST_PRTSC1_PTC_SHIFT) /* 0101 FORCE_ENABLE_HS */
# define USBHOST_PRTSC1_PTC_FS (6 << USBHOST_PRTSC1_PTC_SHIFT) /* 0110 FORCE_ENABLE_FS */
# define USBHOST_PRTSC1_PTC_LS (7 << USBHOST_PRTSC1_PTC_SHIFT) /* 0111 FORCE_ENABLE_LS */
#define USBHOST_PRTSC1_PIC_SHIFT (14) /* Bits 14-15: Port indicator control */
#define USBHOST_PRTSC1_PIC_MASK (3 << USBHOST_PRTSC1_PIC_SHIFT)
# define USBHOST_PRTSC1_PIC_OFF (0 << USBHOST_PRTSC1_PIC_SHIFT) /* 00 Port indicators are off */
# define USBHOST_PRTSC1_PIC_AMBER (1 << USBHOST_PRTSC1_PIC_SHIFT) /* 01 Amber */
# define USBHOST_PRTSC1_PIC_GREEN (2 << USBHOST_PRTSC1_PIC_SHIFT) /* 10 Green */
#define USBHOST_PRTSC1_PP (1 << 12) /* Bit 12: Port power control */
#define USBHOST_PRTSC1_LS_SHIFT (10) /* Bits 10-11: Line status */
#define USBHOST_PRTSC1_LS_MASK (3 << USBHOST_PRTSC1_LS_SHIFT)
# define USBHOST_PRTSC1_LS_SE0 (0 << USBHOST_PRTSC1_LS_SHIFT) /* SE0 (USB_DP and USB_DM LOW) */
# define USBHOST_PRTSC1_LS_JSTATE (2 << USBHOST_PRTSC1_LS_SHIFT) /* J-state (USB_DP HIGH and USB_DM LOW) */
# define USBHOST_PRTSC1_LS_KSTATE (1 << USBHOST_PRTSC1_LS_SHIFT) /* K-state (USB_DP LOW and USB_DM HIGH) */
#define USBHOST_PRTSC1_HSP (1 << 9) /* Bit 9: High-speed status */
#define USBHOST_PRTSC1_PR (1 << 8) /* Bit 8: Port reset */
#define USBHOST_PRTSC1_SUSP (1 << 7) /* Bit 7: Suspend */
#define USBHOST_PRTSC1_FPR (1 << 6) /* Bit 6: Force port resume */
#define USBHOST_PRTSC1_OCC (1 << 5) /* Bit 5: Over-current change */
#define USBHOST_PRTSC1_OCA (1 << 4) /* Bit 4: Over-current active */
#define USBHOST_PRTSC1_PEC (1 << 3) /* Bit 3: Port disable/enable change */
#define USBHOST_PRTSC1_PE (1 << 2) /* Bit 2: Port enable */
#define USBHOST_PRTSC1_CSC (1 << 1) /* Bit 1: Connect status change */
#define USBHOST_PRTSC1_CCS (1 << 0) /* Bit 0: Current connect status */
/* OTG Status and Control register (OTGSC) */
/* OTG interrupt enable */
#define USBOTG_OTGSC_DPIE (1 << 30) /* Bit 30: Data pulse interrupt enable */
#define USBOTG_OTGSC_1MSE (1 << 29) /* Bit 29: 1 millisecond timer interrupt enable */
#define USBOTG_OTGSC_BSEIE (1 << 28) /* Bit 28: B-session end interrupt enable */
#define USBOTG_OTGSC_BSVIE (1 << 27) /* Bit 27: B-session valid interrupt enable */
#define USBOTG_OTGSC_ASVIE (1 << 26) /* Bit 26: A-session valid interrupt enable */
#define USBOTG_OTGSC_AVVIE (1 << 25) /* Bit 25: A-VBUS valid interrupt enable */
#define USBOTG_OTGSC_IDIE (1 << 24) /* Bit 24: USB ID interrupt enable */
/* OTG interrupt status */
#define USBOTG_OTGSC_DPIS (1 << 22) /* Bit 22: Data pulse interrupt status */
#define USBOTG_OTGSC_1MSS (1 << 21) /* Bit 21: 1 millisecond timer interrupt status */
#define USBOTG_OTGSC_BSEIS (1 << 20) /* Bit 20: B-Session end interrupt status */
#define USBOTG_OTGSC_BSVIS (1 << 19) /* Bit 19: B-Session valid interrupt status */
#define USBOTG_OTGSC_ASVIS (1 << 18) /* Bit 18: A-Session valid interrupt status */
#define USBOTG_OTGSC_AVVIS (1 << 17) /* Bit 17: A-VBUS valid interrupt status */
#define USBOTG_OTGSC_IDIS (1 << 16) /* Bit 16: USB ID interrupt status */
/* OTG status inputs */
#define USBOTG_OTGSC_DPS (1 << 14) /* Bit 14: Data bus pulsing status */
#define USBOTG_OTGSC_1MST (1 << 13) /* Bit 13: 1 millisecond timer toggle */
#define USBOTG_OTGSC_BSE (1 << 12) /* Bit 12: B-session end */
#define USBOTG_OTGSC_BSV (1 << 11) /* Bit 11: B-session valid */
#define USBOTG_OTGSC_ASV (1 << 10) /* Bit 10: A-session valid */
#define USBOTG_OTGSC_AVV (1 << 9) /* Bit 9: A-VBUS valid */
#define USBOTG_OTGSC_ID (1 << 8) /* Bit 8: USB ID */
/* OTG controls */
#define USBOTG_OTGSC_HABA (1 << 7) /* Bit 7: Hardware assist B-disconnect to A-connect */
#define USBOTG_OTGSC_HADP (1 << 6) /* Bit 6: Hardware assist data pulse */
#define USBOTG_OTGSC_IDPU (1 << 5) /* Bit 5: ID pull-up */
#define USBOTG_OTGSC_DP (1 << 4) /* Bit 4: Data pulsing */
#define USBOTG_OTGSC_OT (1 << 3) /* Bit 3: OTG termination */
#define USBOTG_OTGSC_HAAR (1 << 2) /* Bit 2: Hardware assist auto_reset */
#define USBOTG_OTGSC_VC (1 << 1) /* Bit 1: VBUS_Charge */
#define USBOTG_OTGSC_VD (1 << 0) /* Bit 0: VBUS_Discharge */
/* USB Mode register USBMODE -- Device Mode */
#define USBDEV_USBMODE_SDIS (1 << 4) /* Bit 4: Stream disable mode */
#define USBDEV_USBMODE_SLOM (1 << 3) /* Bit 3: Setup Lockout mode */
#define USBDEV_USBMODE_ES (1 << 2) /* Bit 2: Endian select */
#define USBDEV_USBMODE_CM_SHIFT (0) /* Bits 0-1: Controller mode */
#define USBDEV_USBMODE_CM_MASK (3 << USBDEV_USBMODE_CM_SHIFT)
# define USBDEV_USBMODE_CM_IDLE (0 << USBDEV_USBMODE_CM_SHIFT) /* Idle */
# define USBDEV_USBMODE_CM_DEVICE (2 << USBDEV_USBMODE_CM_SHIFT) /* Device controller */
# define USBDEV_USBMODE_CM_HOST (3 << USBDEV_USBMODE_CM_SHIFT) /* Host controller */
/* USB Mode register USBMODE -- Device Mode */
#define USBHOST_USBMODE_VBPS (1 << 5) /* Bit 5: VBUS power select */
#define USBHOST_USBMODE_SDIS (1 << 4) /* Bit 4: Stream disable mode */
#define USBHOST_USBMODE_ES (1 << 2) /* Bit 2: Endian select */
#define USBHOST_USBMODE_CM_SHIFT (0) /* Bits 0-1: Controller mode */
#define USBHOST_USBMODE_CM_MASK (3 << USBHOST_USBMODE_CM_SHIFT)
# define USBHOST_USBMODE_CM_IDLE (0 << USBHOST_USBMODE_CM_SHIFT) /* Idle */
# define USBHOST_USBMODE_CM_DEVICE (2 << USBHOST_USBMODE_CM_SHIFT) /* Device controller */
# define USBHOST_USBMODE_CM_HOST (3 << USBHOST_USBMODE_CM_SHIFT) /* Host controller */
/* Device endpoint registers */
/* USB Endpoint Setup Status register ENDPTSETUPSTAT */
#define USBDEV_ENDPTSETSTAT_STAT15 (1 << 15) /* Bit 15: Setup EP status for logical EP 15 */
#define USBDEV_ENDPTSETSTAT_STAT14 (1 << 14) /* Bit 14: Setup EP status for logical EP 14 */
#define USBDEV_ENDPTSETSTAT_STAT13 (1 << 13) /* Bit 13: Setup EP status for logical EP 13 */
#define USBDEV_ENDPTSETSTAT_STAT12 (1 << 12) /* Bit 12: Setup EP status for logical EP 12 */
#define USBDEV_ENDPTSETSTAT_STAT11 (1 << 11) /* Bit 11: Setup EP status for logical EP 11 */
#define USBDEV_ENDPTSETSTAT_STAT10 (1 << 10) /* Bit 10: Setup EP status for logical EP 10 */
#define USBDEV_ENDPTSETSTAT_STAT9 (1 << 9) /* Bit 9: Setup EP status for logical EP 9 */
#define USBDEV_ENDPTSETSTAT_STAT8 (1 << 8) /* Bit 8: Setup EP status for logical EP 8 */
#define USBDEV_ENDPTSETSTAT_STAT7 (1 << 7) /* Bit 7: Setup EP status for logical EP 7 */
#define USBDEV_ENDPTSETSTAT_STAT6 (1 << 6) /* Bit 6: Setup EP status for logical EP 6 */
#define USBDEV_ENDPTSETSTAT_STAT5 (1 << 5) /* Bit 5: Setup EP status for logical EP 5 */
#define USBDEV_ENDPTSETSTAT_STAT4 (1 << 4) /* Bit 4: Setup EP status for logical EP 4 */
#define USBDEV_ENDPTSETSTAT_STAT3 (1 << 3) /* Bit 3: Setup EP status for logical EP 3 */
#define USBDEV_ENDPTSETSTAT_STAT2 (1 << 2) /* Bit 2: Setup EP status for logical EP 2 */
#define USBDEV_ENDPTSETSTAT_STAT1 (1 << 1) /* Bit 1: Setup EP status for logical EP 1 */
#define USBDEV_ENDPTSETSTAT_STAT0 (1 << 0) /* Bit 0: Setup EP status for logical EP 0 */
/* USB Endpoint Prime register ENDPTPRIME */
#define USBDEV_ENDPTPRIM_PETB7 (1 << 23) /* Bit 23: Prime EP xmt buffer for physical IN EP 7 */
#define USBDEV_ENDPTPRIM_PETB6 (1 << 22) /* Bit 22: Prime EP xmt buffer for physical IN EP 6 */
#define USBDEV_ENDPTPRIM_PETB5 (1 << 21) /* Bit 21: Prime EP xmt buffer for physical IN EP 5 */
#define USBDEV_ENDPTPRIM_PETB4 (1 << 20) /* Bit 20: Prime EP xmt buffer for physical IN EP 4 */
#define USBDEV_ENDPTPRIM_PETB3 (1 << 19) /* Bit 19: Prime EP xmt buffer for physical IN EP 3 */
#define USBDEV_ENDPTPRIM_PETB2 (1 << 18) /* Bit 18: Prime EP xmt buffer for physical IN EP 2 */
#define USBDEV_ENDPTPRIM_PETB1 (1 << 17) /* Bit 17: Prime EP xmt buffer for physical IN EP 1 */
#define USBDEV_ENDPTPRIM_PETB0 (1 << 16) /* Bit 16: Prime EP xmt buffer for physical IN EP 0 */
#define USBDEV_ENDPTPRIM_PERB7 (1 << 7) /* Bit 7: Prime EP recv buffer for physical OUT EP 7 */
#define USBDEV_ENDPTPRIM_PERB6 (1 << 6) /* Bit 6: Prime EP recv buffer for physical OUT EP 6 */
#define USBDEV_ENDPTPRIM_PERB5 (1 << 5) /* Bit 5: Prime EP recv buffer for physical OUT EP 5 */
#define USBDEV_ENDPTPRIM_PERB4 (1 << 4) /* Bit 4: Prime EP recv buffer for physical OUT EP 4 */
#define USBDEV_ENDPTPRIM_PERB3 (1 << 3) /* Bit 3: Prime EP recv buffer for physical OUT EP 3 */
#define USBDEV_ENDPTPRIM_PERB2 (1 << 2) /* Bit 2: Prime EP recv buffer for physical OUT EP 2 */
#define USBDEV_ENDPTPRIM_PERB1 (1 << 1) /* Bit 1: Prime EP recv buffer for physical OUT EP 1 */
#define USBDEV_ENDPTPRIM_PERB0 (1 << 0) /* Bit 0: Prime EP recv buffer for physical OUT EP 0 */
/* USB Endpoint Flush register ENDPTFLUSH */
#define USBDEV_ENDPTFLUSH_FETB7 (1 << 23) /* Bit 23: Flush EP xmt buffer for physical IN EP 7 */
#define USBDEV_ENDPTFLUSH_FETB6 (1 << 22) /* Bit 22: Flush EP xmt buffer for physical IN EP 6 */
#define USBDEV_ENDPTFLUSH_FETB5 (1 << 21) /* Bit 21: Flush EP xmt buffer for physical IN EP 5 */
#define USBDEV_ENDPTFLUSH_FETB4 (1 << 20) /* Bit 20: Flush EP xmt buffer for physical IN EP 4 */
#define USBDEV_ENDPTFLUSH_FETB3 (1 << 19) /* Bit 19: Flush EP xmt buffer for physical IN EP 3 */
#define USBDEV_ENDPTFLUSH_FETB2 (1 << 18) /* Bit 18: Flush EP xmt buffer for physical IN EP 2 */
#define USBDEV_ENDPTFLUSH_FETB1 (1 << 17) /* Bit 17: Flush EP xmt buffer for physical IN EP 1 */
#define USBDEV_ENDPTFLUSH_FETB0 (1 << 16) /* Bit 16: Flush EP xmt buffer for physical IN EP 0 */
#define USBDEV_ENDPTFLUSH_FERB7 (1 << 7) /* Bit 7: Flush EP recv buffer for physical OUT EP 7 */
#define USBDEV_ENDPTFLUSH_FERB6 (1 << 6) /* Bit 6: Flush EP recv buffer for physical OUT EP 6 */
#define USBDEV_ENDPTFLUSH_FERB5 (1 << 5) /* Bit 5: Flush EP recv buffer for physical OUT EP 5 */
#define USBDEV_ENDPTFLUSH_FERB4 (1 << 4) /* Bit 4: Flush EP recv buffer for physical OUT EP 4 */
#define USBDEV_ENDPTFLUSH_FERB3 (1 << 3) /* Bit 3: Flush EP recv buffer for physical OUT EP 3 */
#define USBDEV_ENDPTFLUSH_FERB2 (1 << 2) /* Bit 2: Flush EP recv buffer for physical OUT EP 2 */
#define USBDEV_ENDPTFLUSH_FERB1 (1 << 1) /* Bit 1: Flush EP recv buffer for physical OUT EP 1 */
#define USBDEV_ENDPTFLUSH_FERB0 (1 << 0) /* Bit 0: Flush EP recv buffer for physical OUT EP 0 */
/* USB Endpoint Status register ENDPTSTATUS */
#define USBDEV_ENDPTSTATUS_ETBR7 (1 << 23) /* Bit 23: EP xmt buffer ready for physical IN EP 7 */
#define USBDEV_ENDPTSTATUS_ETBR6 (1 << 22) /* Bit 22: EP xmt buffer ready for physical IN EP 6 */
#define USBDEV_ENDPTSTATUS_ETBR5 (1 << 21) /* Bit 21: EP xmt buffer ready for physical IN EP 5 */
#define USBDEV_ENDPTSTATUS_ETBR4 (1 << 20) /* Bit 20: EP xmt buffer ready for physical IN EP 4 */
#define USBDEV_ENDPTSTATUS_ETBR3 (1 << 19) /* Bit 19: EP xmt buffer ready for physical IN EP 3 */
#define USBDEV_ENDPTSTATUS_ETBR2 (1 << 18) /* Bit 18: EP xmt buffer ready for physical IN EP 2 */
#define USBDEV_ENDPTSTATUS_ETBR1 (1 << 17) /* Bit 17: EP xmt buffer ready for physical IN EP 1 */
#define USBDEV_ENDPTSTATUS_ETBR0 (1 << 16) /* Bit 16: EP xmt buffer ready for physical IN EP 0 */
#define USBDEV_ENDPTSTATUS_ERBR7 (1 << 7) /* Bit 7: EP recv buffer ready for physical OUT EP 7 */
#define USBDEV_ENDPTSTATUS_ERBR6 (1 << 6) /* Bit 6: EP recv buffer ready for physical OUT EP 6 */
#define USBDEV_ENDPTSTATUS_ERBR5 (1 << 5) /* Bit 5: EP recv buffer ready for physical OUT EP 5 */
#define USBDEV_ENDPTSTATUS_ERBR4 (1 << 4) /* Bit 4: EP recv buffer ready for physical OUT EP 4 */
#define USBDEV_ENDPTSTATUS_ERBR3 (1 << 3) /* Bit 3: EP recv buffer ready for physical OUT EP 3 */
#define USBDEV_ENDPTSTATUS_ERBR2 (1 << 2) /* Bit 2: EP recv buffer ready for physical OUT EP 2 */
#define USBDEV_ENDPTSTATUS_ERBR1 (1 << 1) /* Bit 1: EP recv buffer ready for physical OUT EP 1 */
#define USBDEV_ENDPTSTATUS_ERBR0 (1 << 0) /* Bit 0: EP recv buffer ready for physical OUT EP 0 */
/* USB Endpoint Complete register ENDPTCOMPLETE */
#define USBDEV_ENDPTCOMPLETE_ETCE7 (1 << 23) /* Bit 23: EP xmt complete event for physical IN EP 7 */
#define USBDEV_ENDPTCOMPLETE_ETCE6 (1 << 22) /* Bit 22: EP xmt complete event for physical IN EP 6 */
#define USBDEV_ENDPTCOMPLETE_ETCE5 (1 << 21) /* Bit 21: EP xmt complete event for physical IN EP 5 */
#define USBDEV_ENDPTCOMPLETE_ETCE4 (1 << 20) /* Bit 20: EP xmt complete event for physical IN EP 4 */
#define USBDEV_ENDPTCOMPLETE_ETCE3 (1 << 19) /* Bit 19: EP xmt complete event for physical IN EP 3 */
#define USBDEV_ENDPTCOMPLETE_ETCE2 (1 << 18) /* Bit 18: EP xmt complete event for physical IN EP 2 */
#define USBDEV_ENDPTCOMPLETE_ETCE1 (1 << 17) /* Bit 17: EP xmt complete event for physical IN EP 1 */
#define USBDEV_ENDPTCOMPLETE_ETCE0 (1 << 16) /* Bit 16: EP xmt complete event for physical IN EP 0 */
#define USBDEV_ENDPTCOMPLETE_ERCE7 (1 << 7) /* Bit 7: EP recv complete event for physical OUT EP 7 */
#define USBDEV_ENDPTCOMPLETE_ERCE6 (1 << 6) /* Bit 6: EP recv complete event for physical OUT EP 6 */
#define USBDEV_ENDPTCOMPLETE_ERCE5 (1 << 5) /* Bit 5: EP recv complete event for physical OUT EP 5 */
#define USBDEV_ENDPTCOMPLETE_ERCE4 (1 << 4) /* Bit 4: EP recv complete event for physical OUT EP 4 */
#define USBDEV_ENDPTCOMPLETE_ERCE3 (1 << 3) /* Bit 3: EP recv complete event for physical OUT EP 3 */
#define USBDEV_ENDPTCOMPLETE_ERCE2 (1 << 2) /* Bit 2: EP recv complete event for physical OUT EP 2 */
#define USBDEV_ENDPTCOMPLETE_ERCE1 (1 << 1) /* Bit 1: EP recv complete event for physical OUT EP 1 */
#define USBDEV_ENDPTCOMPLETE_ERCE0 (1 << 0) /* Bit 0: EP recv complete event for physical OUT EP 0 */
/* USB Endpoint 0 Control register ENDPTCTRL0 */
#define USBDEV_ENDPTCTRL0_TXE (1 << 23) /* Bit 23: Tx endpoint enable */
#define USBDEV_ENDPTCTRL0_TXT_SHIFT (18) /* Bits 18-19: Tx endpoint type */
#define USBDEV_ENDPTCTRL0_TXT_MASK (3 << USBDEV_ENDPTCTRL0_TXT_SHIFT)
# define USBDEV_ENDPTCTRL0_TXT_CTRL (0 << USBDEV_ENDPTCTRL0_TXT_SHIFT) /* Control */
#define USBDEV_ENDPTCTRL0_TXS (1 << 16) /* Bit 16: Tx endpoint stall */
#define USBDEV_ENDPTCTRL0_RXE (1 << 7) /* Bit 7: Rx endpoint enable */
#define USBDEV_ENDPTCTRL0_RXT_SHIFT (2) /* Bits 2-3: Endpoint type */
#define USBDEV_ENDPTCTR0L_RXT_MASK (3 << USBDEV_ENDPTCTRL0_RXT_SHIFT)
# define USBDEV_ENDPTCTRL0_RXT_CTRL (0 << USBDEV_ENDPTCTRL0_RXT_SHIFT) /* Control */
#define USBDEV_ENDPTCTRL0_RXS (1 << 0) /* Bit 0: Rx endpoint stall */
/* USB Endpoint 1-7 control registers ENDPTCTRL1-ENDPPTCTRL7 */
#define USBDEV_ENDPTCTRL_TXE (1 << 23) /* Bit 23: Tx endpoint enable */
#define USBDEV_ENDPTCTRL_TXR (1 << 22) /* Bit 22: Tx data toggle reset */
#define USBDEV_ENDPTCTRL_TXI (1 << 21) /* Bit 21: Tx data toggle inhibit */
#define USBDEV_ENDPTCTRL_TXT_SHIFT (18) /* Bits 18-19: Tx endpoint type */
#define USBDEV_ENDPTCTRL_TXT_MASK (3 << USBDEV_ENDPTCTRL_TXT_SHIFT)
# define USBDEV_ENDPTCTRL_TXT_CTRL (0 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Control */
# define USBDEV_ENDPTCTRL_TXT_ISOC (1 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Isochronous */
# define USBDEV_ENDPTCTRL_TXT_BULK (2 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Bulk */
# define USBDEV_ENDPTCTRL_TXT_INTR (3 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Interrupt */
#define USBDEV_ENDPTCTRL_TXS (1 << 16) /* Bit 16: Tx endpoint stall */
#define USBDEV_ENDPTCTRL_RXE (1 << 7) /* Bit 7: Rx endpoint enable */
#define USBDEV_ENDPTCTRL_RXR (1 << 6) /* Bit 6: Rx data toggle reset */
#define USBDEV_ENDPTCTRL_RXI (1 << 5) /* Bit 5: Rx data toggle inhibit */
#define USBDEV_ENDPTCTRL_RXT_SHIFT (2) /* Bits 2-3: Endpoint type */
#define USBDEV_ENDPTCTRL_RXT_MASK (3 << USBDEV_ENDPTCTRL_RXT_SHIFT)
# define USBDEV_ENDPTCTRL_RXT_CTRL (0 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Control */
# define USBDEV_ENDPTCTRL_RXT_ISOC (1 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Isochronous */
# define USBDEV_ENDPTCTRL_RXT_BULK (2 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Bulk */
# define USBDEV_ENDPTCTRL_RXT_INTR (3 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Interrupt */
#define USBDEV_ENDPTCTRL_RXS (1 << 0) /* Bit 0: Rx endpoint stall */
/* Device non-core registers */
/* USB OTG Control register */
/* Bits 0-6:
* Reserved
*/
#define USBNC_OVER_CUR_DIS (1 << 7) /* Bit 7: Disable Over current detection */
#define USBNC_OVER_CUR_POL (1 << 8) /* Bit 8: Polarity of over current */
#define USBNC_PWR_POL (1 << 9) /* Bit 9: Power polarity */
#define USBNC_WIE (1<< 10) /* Bit 10: Wake up interrupt enable */
/* Bit 11-13: Reserved */
#define USBNC_WKUP_SW_EN (1 << 14) /* Bit 14: Software wake up enable */
#define USBNC_WKUP_SW (1 << 15) /* Bit 15: Software wake up */
#define USBNC_WKUP_ID_EN (1 << 16) /* Bit 16: Wakeup on ID change enable */
#define USBNC_WKUP_VBUS_EN (1 << 17) /* Bit 17: Wakeup on VBUS change enable */
/* Bit 18-28: Reserved */
#define USBNC_WKUP_DPDM_EN (1 << 29) /* Bit 29: Wakeup on DPDM change enable */
/* Bit 30: Reserved */
#define USBNC_WIR (1 << 31) /* Bit 31: Wake up interrupt request */
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USBOTG_H */

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/****************************************************************************
* arch/arm/src/imxrt/hardware/imxrt_usbphy.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USB_PHY_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USB_PHY_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imxrt_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IMXRT_USBPHY1_BASE_OFFSET 0x1000 /* USB PHY1 Base */
#define IMXRT_USBPHY2_BASE_OFFSET 0x2000 /* USB PHY2 Base */
#define IMXRT_USBPHY1_BASE (IMXRT_ANATOP_BASE + IMXRT_USBPHY1_BASE_OFFSET) /* USB PHY1 Base */
#define IMXRT_USBPHY2_BASE (IMXRT_ANATOP_BASE + IMXRT_USBPHY2_BASE_OFFSET) /* USB PHY2 Base */
/* Register Offsets *********************************************************/
#define IMXRT_USBPHY1_PWD_OFFSET 0x0000 /* USBPHY1 USB PHY1 Power-Down Register */
#define IMXRT_USBPHY1_PWD_CLR_OFFSET 0x0008 /* USBPHY1 USB PHY1 Power-Down Register Clear */
#define IMXRT_USBPHY1_CTRL_OFFSET 0x0030 /* USBPHY1 USB PHY1 General Control Register */
#define IMXRT_USBPHY1_CTRL_CLR_OFFSET 0x0038 /* USBPHY1 USB PHY1 General Control Register Clear */
#define IMXRT_USBPHY2_PWD_OFFSET 0x0000 /* USBPHY2 USB PHY Power-Down Register */
#define IMXRT_USBPHY2_PWD_CLR_OFFSET 0x0008 /* USBPHY2 USB PHY Power-Down Register Clear */
#define IMXRT_USBPHY2_CTRL_OFFSET 0x0030 /* USBPHY2 USB PHY General Control Register */
#define IMXRT_USBPHY2_CTRL_CLR_OFFSET 0x0038 /* USBPHY2 USB PHY General Control Register Clear */
/* Register addresses *******************************************************/
#define IMXRT_USBPHY1_PWD (IMXRT_USBPHY1_BASE + IMXRT_USBPHY1_PWD_OFFSET) /* USBPHY1 USB PHY1 Power-Down Register */
#define IMXRT_USBPHY1_PWD_CLR (IMXRT_USBPHY1_BASE + IMXRT_USBPHY1_PWD_CLR_OFFSET) /* USBPHY1 USB PHY1 Power-Down Register Clear */
#define IMXRT_USBPHY1_CTRL (IMXRT_USBPHY1_BASE + IMXRT_USBPHY1_CTRL_OFFSET) /* USBPHY1 USB PHY1 General Control Register */
#define IMXRT_USBPHY1_CTRL_CLR (IMXRT_USBPHY1_BASE + IMXRT_USBPHY1_CTRL_CLR_OFFSET) /* USBPHY1 USB PHY1 General Control Register Clear */
#define IMXRT_USBPHY2_PWD (IMXRT_USBPHY2_BASE + IMXRT_USBPHY2_PWD_OFFSET) /* USBPHY2 USB PHY2 Power-Down Register */
#define IMXRT_USBPHY2_PWD_CLR (IMXRT_USBPHY2_BASE + IMXRT_USBPHY2_PWD_CLR_OFFSET) /* USBPHY2 USB PHY2 Power-Down Register Clear */
#define IMXRT_USBPHY2_CTRL (IMXRT_USBPHY2_BASE + IMXRT_USBPHY2_CTRL_OFFSET) /* USBPHY2 USB PHY2 General Control Register */
#define IMXRT_USBPHY2_CTRL_CLR (IMXRT_USBPHY2_BASE + IMXRT_USBPHY2_CTRL_CLR_OFFSET) /* USBPHY2 USB PHY2 General Control Register Clear */
/* Register Bit Definitions *************************************************/
/* USB PHY Power-Down Register */
#define USBPHY_PWD_RXPWDRX (1 << 20) /* Bit 20: Power-down the entire USB PHY receiver block except for the full-speed differential receiver. */
#define USBPHY_PWD_RXPWDDIFF (1 << 19) /* Bit 19: Power-down the USB high-speed differential receiver. */
#define USBPHY_PWD_RXPWD1PT1 (1 << 18) /* Bit 18: Power-down the USB full-speed differential receiver. */
#define USBPHY_PWD_RXPWDENV (1 << 17) /* Bit 17: Power-down the USB high-speed receiver envelope detector (squelch signal). */
#define USBPHY_PWD_TXPWDV2I (1 << 12) /* Bit 12: Power-down the USB PHY transmit V-to-I converter and the current mirror. */
#define USBPHY_PWD_TXPWDIBIAS (1 << 11) /* Bit 11: Power-down the USB PHY current bias block for the transmitter. */
#define USBPHY_PWD_TXPWDFS (1 << 10) /* Bit 10: Power-down the USB full-speed drivers. */
/* USB PHY General Control Register */
#define USBPHY_CTRL_SFTRST (1 << 31) /* Bit 31: Soft-reset */
#define USBPHY_CTRL_CLKGATE (1 << 30) /* Bit 30: Gate UTMI clocks */
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USB_PHY_H */

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/****************************************************************************
* arch/arm/src/imxrt/hardware/rt105x/imxrt105x_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_MEMORYMAP_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* System memory map */
#define IMXRT_ITCM_BASE 0x00000000 /* 512KB ITCM */
/* 0x00080000 512KB ITCM Reserved */
/* 0x00100000 1MB ITCM Reserved */
#define IMXRT_ROMCP_BASE 0x00200000 /* 96KB ROMCP */
/* 0x00218000 416KB ROMCP Reserved */
/* 0x00280000 1536KB Reserved */
/* 0x00400000 124MB Reserved */
#define IMXRT_FLEXSPI_BASE 0x08000000 /* 128MB FlexSPI (Aliased) */
#define IMXRT_SEMCA_BASE 0x10000000 /* 256MB SEMC (Aliased) */
#define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */
/* 0x20080000 512KB DTCM Reserved */
/* 0x20100000 1MB Reserved */
#define IMXRT_OCRAM_BASE 0x20200000 /* 512KB OCRAM */
/* 0x20280000 1536KB OCRAM Reserved */
/* 0x20400000 252MB Reserved */
/* 0x30000000 256MB Reserved */
#define IMXRT_AIPS1_BASE 0x40000000 /* 1MB AIPS-1 */
#define IMXRT_AIPS2_BASE 0x40100000 /* 1MB AIPS-2 */
#define IMXRT_AIPS3_BASE 0x40200000 /* 1MB AIPS-3 */
#define IMXRT_AIPS4_BASE 0x40300000 /* 1MB AIPS-4 */
/* 40400000 12MB Reserved */
#define IMXRT_MAINCNF_BASE 0x41000000 /* 1MB "main" configuration port */
#define IMXRT_MCNF_BASE 0x41100000 /* 1MB "m" configuration port */
/* 41200000 1MB Reserved for "per" GPV */
/* 41300000 1MB Reserved for "ems" GPV */
#define IMXRT_CPUCNF_BASE 0x41400000 /* 1MB "cpu" configuration port */
/* 0x41500000 1MB GPV Reserved */
/* 0x41600000 1MB GPV Reserved */
/* 0x41700000 1MB GPV Reserved */
/* 0x41800000 8MB Reserved */
/* 0x42000000 32MB Reserved */
/* 0x44000000 64MB Reserved */
/* 0x48000000 384MB Reserved */
#define IMXRT_FLEXCIPHER_BASE 0x60000000 /* 504MB FlexSPI/ FlexSPI ciphertext */
#define IMXRT_FLEXSPITX_BASE 0x7f800000 /* 4MB FlexSPI TX FIFO */
#define IMXRT_FLEXSPIRX_BASE 0x7fc00000 /* 4MB FlexSPI RX FIFO */
#define IMXRT_EXTMEM_BASE 0x80000000 /* 1.5GB SEMC external memories shared memory space */
#define IMXRT_CM7_BASE 0xe0000000 /* 1MB CM7 PPB */
/* 0xe0100000 511MB Reserved */
/* AIPS-1 memory map */
/* 0x40000000 256KB Reserved */
/* 0x40040000 240KB Reserved */
#define IMXRT_AIPS1CNF_BASE 0x4007c000 /* 6KB AIPS-1 Configuration */
#define IMXRT_DCDC_BASE 0x40080000 /* 16KB DCDC */
#define IMXRT_PIT_BASE 0x40084000 /* 16KB PIT */
/* 0x40088000 16KB Reserved */
/* 0x4008c000 16KB Reserved */
#define IMXRT_MTR_BASE 0x40090000 /* 16KB MTR */
#define IMXRT_ACMP_BASE 0x40094000 /* 16KB ACMP */
/* 0x40098000 16KB Reserved */
/* 0x4009c000 16KB Reserved */
/* 0x400a0000 16KB Reserved */
#define IMXRT_IOMUXCSNVSGPR_BASE 0x400a4000 /* 16KB IOMUXC_SNVS_GPR */
#define IMXRT_IOMUXCSNVS_BASE 0x400a8000 /* 16KB IOMUXC_SNVS */
#define IMXRT_IOMUXCGPR_BASE 0x400ac000 /* 16KB IOMUXC_GPR */
#define IMXRT_FLEXRAM_BASE 0x400b0000 /* 16KB CM7_MX6RT(FLEXRAM) */
#define IMXRT_EWM_BASE 0x400b4000 /* 16KB EWM */
#define IMXRT_WDOG1_BASE 0x400b8000 /* 16KB WDOG1 */
#define IMXRT_WDOG3_BASE 0x400bc000 /* 16KB WDOG3 */
#define IMXRT_GPIO5_BASE 0x400c0000 /* 16KB GPIO5 */
#define IMXRT_ADC1_BASE 0x400c4000 /* 16KB ADC1 */
#define IMXRT_ADC2_BASE 0x400c8000 /* 16KB ADC2 */
#define IMXRT_TRNG_BASE 0x400cc000 /* 16KB TRNG */
#define IMXRT_WDOG2_BASE 0x400d0000 /* 16KB WDOG2 */
#define IMXRT_SNVSHP_BASE 0x400d4000 /* 16KB SNVS_HP */
#define IMXRT_ANATOP_BASE 0x400d8000 /* 16KB ANATOP */
#define IMXRT_CSU_BASE 0x400dc000 /* 16KB CSU */
/* 0x400e0000 16KB Reserved */
/* 0x400e4000 16KB Reserved */
#define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */
#define IMXRT_DMAMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */
/* 400f0000 16KB Reserved */
#define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */
#define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */
#define IMXRT_CCM_BASE 0x400fc000 /* 16KB CCM */
/* AIPS-2 memory map */
/* 0x40100000 256KB Reserved */
/* 0x40140000 240KB Reserved */
#define IMXRT_AIPS2CNF_BASE 0x4017c000 /* 16KB AIPS-2 Configuration */
#define IMXRT_ROMCPC_BASE 0x40180000 /* 16KB ROMCP controller*/
#define IMXRT_LPUART1_BASE 0x40184000 /* 16KB LPUART1 */
#define IMXRT_LPUART2_BASE 0x40188000 /* 16KB LPUART2 */
#define IMXRT_LPUART3_BASE 0x4018c000 /* 16KB LPUART3 */
#define IMXRT_LPUART4_BASE 0x40190000 /* 16KB LPUART4 */
#define IMXRT_LPUART5_BASE 0x40194000 /* 16KB LPUART5 */
#define IMXRT_LPUART6_BASE 0x40198000 /* 16KB LPUART6 */
#define IMXRT_LPUART7_BASE 0x4019c000 /* 16KB LPUART7 */
#define IMXRT_LPUART8_BASE 0x401a0000 /* 16KB LPUART8 */
/* 0x401a4000 16KB Reserved */
/* 0x401a8000 16KB Reserved */
#define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */
#define IMXRT_FLEXIO2_BASE 0x401b0000 /* 16KB FlexIO2 */
/* 0x401b4000 16KB Reserved */
#define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */
#define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */
#define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */
#define IMXRT_GPIO4_BASE 0x401c4000 /* 16KB GPIO4 */
/* 0x401c8000 16KB Reserved */
/* 0x401cc000 16KB Reserved */
#define IMXRT_CAN1_BASE 0x401d0000 /* 16KB CAN1 */
#define IMXRT_CAN2_BASE 0x401d4000 /* 16KB CAN2 */
/* 0x401d8000 16KB Reserved */
#define IMXRT_QTIMER1_BASE 0x401dc000 /* 16KB QTimer1 */
#define IMXRT_QTIMER2_BASE 0x401e0000 /* 16KB QTimer2 */
#define IMXRT_QTIMER3_BASE 0x401e4000 /* 16KB QTimer3 */
#define IMXRT_QTIMER4_BASE 0x401e8000 /* 16KB QTimer4 */
#define IMXRT_GPT1_BASE 0x401ec000 /* 16KB GPT1 */
#define IMXRT_GPT2_BASE 0x401f0000 /* 16KB GPT2 */
#define IMXRT_OCOTP_BASE 0x401f4000 /* 16KB OCOTP */
#define IMXRT_IOMUXC_BASE 0x401f8000 /* 16KB IOMUXC */
#define IMXRT_KPP_BASE 0x401fc000 /* 16KB KPP */
/* AIPS-3 memory map */
/* 0x40200000 256KB Reserved */
/* 0x40240000 240KB Reserved */
#define IMXRT_AIOS3CNF_BASE 0x4027c000 /* 16KB AIPS-3 Configuration */
/* 0x40280000 16KB Reserved */
/* 0x40284000 16KB Reserved */
/* 0x40288000 16KB Reserved */
/* 0x4028c000 16KB Reserved */
/* 0x40290000 16KB Reserved */
/* 0x40294000 16KB Reserved */
/* 0x40298000 16KB Reserved */
/* 0x4029c000 16KB Reserved */
/* 0x402a0000 16KB Reserved */
/* 0x402a4000 16KB Reserved */
#define IMXRT_FLEXSPIC_BASE 0x402a8000 /* 16KB FlexSPI controller */
/* 0x402ac000 16KB Reserved */
/* 0x402b0000 16KB Reserved */
#define IMXRT_PXP_BASE 0x402b4000 /* 16KB PXP */
#define IMXRT_LCDIF_BASE 0x402b8000 /* 16KB LCDIF */
#define IMXRT_CSI_BASE 0x402bc000 /* 16KB CSI */
#define IMXRT_USDHC1_BASE 0x402c0000 /* 16KB USDHC1 */
#define IMXRT_USDHC2_BASE 0x402c4000 /* 16KB USDHC2 */
/* 0x402c8000 16KB Reserved */
/* 0x402cc000 16KB Reserved */
/* 0x402d0000 16KB Reserved */
/* 0x402d4000 16KB Reserved */
#define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */
#define IMXRT_USBPL301_BASE 0x402dc000 /* 16KB USB(PL301) */
#define IMXRT_USB_BASE 0x402e0200 /* 16KB USB(USB) */
/* 0x402e4000 16KB Reserved */
/* 0x402e8000 16KB Reserved */
/* 0x402ec000 16KB Reserved */
#define IMXRT_SEMC_BASE 0x402f0000 /* 16KB SEMC */
/* 0x402f4000 16KB Reserved */
/* 0x402f8000 16KB Reserved */
#define IMXRT_DCP_BASE 0x402fc000 /* 16KB DCP */
/* AIPS-4 memory map */
/* 0x40300000 256KB Reserved */
/* 0x40340000 240KB Reserved */
#define IMXRT_AIPS4CNF_BASE 0x4037c000 /* 16KB AIPS-4 Configuration */
#define IMXRT_SPDIF_BASE 0x40380000 /* 16KB SPDIF */
#define IMXRT_SAI1_BASE 0x40384000 /* 16KB SAI1 */
#define IMXRT_SAI2_BASE 0x40388000 /* 16KB SAI2 */
#define IMXRT_SAI3_BASE 0x4038c000 /* 16KB SAI3 */
/* 0x40390000 16KB Reserved */
#define IMXRT_LPSPI1_BASE 0x40394000 /* 16KB LPSPI1 */
#define IMXRT_LPSPI2_BASE 0x40398000 /* 16KB LPSPI2 */
#define IMXRT_LPSPI3_BASE 0x4039c000 /* 16KB LPSPI3 */
#define IMXRT_LPSPI4_BASE 0x403a0000 /* 16KB LPSPI4 */
/* 0x403a4000 16KB Reserved */
/* 0x403a8000 16KB Reserved */
/* 0x403ac000 16KB Reserved */
#define IMXRT_ADCETC_BASE 0x403b0000 /* 16KB ADC_ETC */
#define IMXRT_AOI1_BASE 0x403b4000 /* 16KB AOI1 */
#define IMXRT_AOI2_BASE 0x403b8000 /* 16KB AOI2 */
#define IMXRT_XBAR1_BASE 0x403bc000 /* 16KB XBAR1 */
#define IMXRT_XBAR2_BASE 0x403c0000 /* 16KB XBAR2 */
#define IMXRT_XBAR3_BASE 0x403c4000 /* 16KB XBAR3 */
#define IMXRT_ENC1_BASE 0x403c8000 /* 16KB ENC1 */
#define IMXRT_ENC2_BASE 0x403cc000 /* 16KB ENC2 */
#define IMXRT_ENC3_BASE 0x403d0000 /* 16KB ENC3 */
#define IMXRT_ENC4_BASE 0x403d4000 /* 16KB ENC4 */
/* 0x403d8000 16KB Reserved */
#define IMXRT_FLEXPWM1_BASE 0x403dc000 /* 16KB FLEXPWM1 */
#define IMXRT_FLEXPWM2_BASE 0x403e0000 /* 16KB FLEXPWM2 */
#define IMXRT_FLEXPWM3_BASE 0x403e4000 /* 16KB FLEXPWM3 */
#define IMXRT_FLEXPWM4_BASE 0x403e8000 /* 16KB FLEXPWM4 */
#define IMXRT_BEE_BASE 0x403ec000 /* 16KB BEE */
#define IMXRT_LPI2C1_BASE 0x403f0000 /* 16KB */
#define IMXRT_LPI2C2_BASE 0x403f4000 /* 16KB LPI2C2 */
#define IMXRT_LPI2C3_BASE 0x403f8000 /* 16KB LPI2C3 */
#define IMXRT_LPI2C4_BASE 0x403fc000 /* 16KB LPI2C4 */
/* PPB memory map */
#define IMXRT_TPIU_BASE 0xe0040000 /* 4KB TPIU */
#define IMXRT_ETM_BASE 0xe0041000 /* 4KB ETM */
#define IMXRT_CTI_BASE 0xe0042000 /* 4KB CTI */
#define IMXRT_TSGEN_BASE 0xe0043000 /* 4KB TSGEN */
#define IMXRT_PPBRES_BASE 0xe0044000 /* 4KB PPB RES */
/* 0xe0045000 236KB PPB Reserved */
#define IMXRT_MCM_BASE 0xe0080000 /* 4KB MCM */
/* 0xe0081000 444KB PPB Reserved */
/* 0xe00f0000 52KB PPB Reserved */
#define IMXRT_SYSROM_BASE 0xe00fd000 /* 4KB SYS ROM */
#define IMXRT_PROCROM_BASE 0xe00fe000 /* 4KB Processor ROM */
#define IMXRT_PPBROM_BASE 0xe00ff000 /* 4KB PPB ROM */
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_MEMORYMAP_H */

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/****************************************************************************
* arch/arm/src/imxrt/imxrt_clockconfig.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_arch.h"
#include <arch/board/board.h>
#include "hardware/imxrt_ccm.h"
#include "hardware/imxrt_dcdc.h"
#include "imxrt_clockconfig.h"
#include "imxrt_lcd.h"
#include "hardware/imxrt_memorymap.h"
#include "hardware/imxrt_iomuxc.h"
#include <stdlib.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define VIDEO_PLL_MIN_FREQ 650000000
#define OSC24_FREQ 24000000
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_lcd_clockconfig
****************************************************************************/
#ifdef CONFIG_IMXRT_LCD
static void imxrt_lcd_clockconfig(void)
{
uint32_t reg;
uint32_t reg2;
int post;
int pre;
uint32_t numerator;
uint32_t denominator;
uint32_t post_divider;
uint32_t pre_divider;
uint32_t loop_divider;
uint32_t target_freq;
uint32_t freq_error;
target_freq = (CONFIG_IMXRT_LCD_HWIDTH +
CONFIG_IMXRT_LCD_HPULSE +
CONFIG_IMXRT_LCD_HFRONTPORCH +
CONFIG_IMXRT_LCD_HBACKPORCH) *
(CONFIG_IMXRT_LCD_VHEIGHT +
CONFIG_IMXRT_LCD_VPULSE +
CONFIG_IMXRT_LCD_VFRONTPORCH +
CONFIG_IMXRT_LCD_VBACKPORCH) *
CONFIG_IMXRT_LCD_REFRESH_FREQ;
for (post_divider = 1; post_divider < 16; post_divider <<= 1)
{
if (IMXRT_LCD_VIDEO_PLL_FREQ * post_divider >= VIDEO_PLL_MIN_FREQ)
{
break;
}
}
loop_divider = (IMXRT_LCD_VIDEO_PLL_FREQ * post_divider) / OSC24_FREQ;
numerator = (IMXRT_LCD_VIDEO_PLL_FREQ * post_divider) -
(loop_divider * OSC24_FREQ);
denominator = OSC24_FREQ;
/* Bypass PLL first */
modifyreg32(IMXRT_CCM_ANALOG_PLL_VIDEO,
CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK,
CCM_ANALOG_PLL_VIDEO_BYPASS |
CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_REF_24M);
putreg32(CCM_ANALOG_PLL_VIDEO_NUM_A(numerator),
IMXRT_CCM_ANALOG_PLL_VIDEO_NUM);
putreg32(CCM_ANALOG_PLL_VIDEO_DENOM_B(denominator),
IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM);
/* Set post divider:
*
* ------------------------------------------------------------------------
* | config->postDivider | PLL_VIDEO[POST_DIV_SELECT] | MISC2[VIDEO_DIV] |
* ------------------------------------------------------------------------
* | 1 | 2 | 0 |
* ------------------------------------------------------------------------
* | 2 | 1 | 0 |
* ------------------------------------------------------------------------
* | 4 | 2 | 3 |
* ------------------------------------------------------------------------
* | 8 | 1 | 3 |
* ------------------------------------------------------------------------
* | 16 | 0 | 3 |
* ------------------------------------------------------------------------
*/
reg = getreg32(IMXRT_CCM_ANALOG_PLL_VIDEO);
reg &= ~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK |
CCM_ANALOG_PLL_VIDEO_POWERDOWN);
reg |= CCM_ANALOG_PLL_VIDEO_ENABLE |
CCM_ANALOG_PLL_VIDEO_DIV_SELECT(loop_divider);
reg2 = getreg32(IMXRT_CCM_ANALOG_MISC2);
reg2 &= ~CCM_ANALOG_MISC2_VIDEO_DIV_MASK;
switch (post_divider)
{
case 16:
reg |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV4;
reg2 |= CCM_ANALOG_MISC2_VIDEO_DIV(3);
break;
case 8:
reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV2;
reg2 |= CCM_ANALOG_MISC2_VIDEO_DIV(3);
break;
case 4:
reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV1;
reg2 |= CCM_ANALOG_MISC2_VIDEO_DIV(3);
break;
case 2:
reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV2;
reg2 |= 0;
break;
default:
reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV1;
reg2 |= 0;
break;
}
putreg32(reg, IMXRT_CCM_ANALOG_PLL_VIDEO);
putreg32(reg2, IMXRT_CCM_ANALOG_MISC2);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_VIDEO) &
CCM_ANALOG_PLL_VIDEO_LOCK) == 0)
{
}
/* Disable Bypass */
modifyreg32(IMXRT_CCM_ANALOG_PLL_VIDEO,
CCM_ANALOG_PLL_VIDEO_BYPASS,
0);
freq_error = IMXRT_LCD_VIDEO_PLL_FREQ;
pre_divider = 0;
post_divider = 0;
for (post = 0; post < 8; post++)
{
for (pre = 0; pre < 8; pre++)
{
int32_t temp_error;
temp_error = labs((post + 1) * (pre + 1) * target_freq -
IMXRT_LCD_VIDEO_PLL_FREQ);
if (temp_error < freq_error)
{
pre_divider = pre;
post_divider = post;
freq_error = temp_error;
}
}
}
/* Select PLL5 as LCD Clock and set Pre divider. */
modifyreg32(IMXRT_CCM_CSCDR2,
CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK |
CCM_CSCDR2_LCDIF_PRED_MASK,
CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL5 |
CCM_CSCDR2_LCDIF_PRED(pre_divider));
/* Set Post divider. */
modifyreg32(IMXRT_CCM_CBCMR, CCM_CBCMR_LCDIF_PODF_MASK,
CCM_CBCMR_LCDIF_PODF(post_divider));
}
#endif
/****************************************************************************
* Name: imxrt_pllsetup
****************************************************************************/
static void imxrt_pllsetup(void)
{
#ifdef CONFIG_ARCH_FAMILY_IMXRT102x
uint32_t pll2reg;
#endif
uint32_t pll3reg;
uint32_t reg;
#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined (CONFIG_ARCH_FAMILY_IMXRT106x))
/* Init Arm PLL1 */
reg = CCM_ANALOG_PLL_ARM_DIV_SELECT(IMXRT_ARM_PLL_DIV_SELECT) |
CCM_ANALOG_PLL_ARM_ENABLE;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_ARM);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_ARM) & CCM_ANALOG_PLL_ARM_LOCK) == 0)
{
}
/* Init Sys PLL2 */
reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_SELECT) |
CCM_ANALOG_PLL_SYS_ENABLE;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) & CCM_ANALOG_PLL_SYS_LOCK) == 0)
{
}
/* Init USB PLL3 */
/* capture it's original value */
pll3reg = getreg32(IMXRT_CCM_ANALOG_PFD_480);
putreg32(pll3reg |
CCM_ANALOG_PFD_480_PFD0_CLKGATE |
CCM_ANALOG_PFD_480_PFD1_CLKGATE |
CCM_ANALOG_PFD_480_PFD2_CLKGATE |
CCM_ANALOG_PFD_480_PFD3_CLKGATE,
IMXRT_CCM_ANALOG_PFD_480);
reg = IMXRT_USB2_PLL_DIV_SELECT |
CCM_ANALOG_PLL_USB2_ENABLE |
CCM_ANALOG_PLL_USB2_EN_USB_CLKS |
CCM_ANALOG_PLL_USB2_POWER;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_USB2);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_USB2) &
CCM_ANALOG_PLL_USB2_LOCK) == 0)
{
}
putreg32(pll3reg, IMXRT_CCM_ANALOG_PFD_480);
#ifdef CONFIG_IMXRT_LCD
/* Init Video PLL5 */
imxrt_lcd_clockconfig();
#endif
/* Init ENET PLL6 */
reg = CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ |
CCM_ANALOG_PLL_ENET_ENET1_125M_EN |
CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN |
CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN |
CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_ENET);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_ENET) &
CCM_ANALOG_PLL_ENET_LOCK) == 0)
{
}
#elif defined(CONFIG_ARCH_FAMILY_IMXRT102x)
/* Init Sys PLL2 */
/* First reset its fractional dividers */
pll2reg = getreg32(IMXRT_CCM_ANALOG_PFD_528);
putreg32(pll2reg |
CCM_ANALOG_PFD_528_PFD0_CLKGATE |
CCM_ANALOG_PFD_528_PFD1_CLKGATE |
CCM_ANALOG_PFD_528_PFD2_CLKGATE |
CCM_ANALOG_PFD_528_PFD3_CLKGATE,
IMXRT_CCM_ANALOG_PFD_528);
reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_DIV_SELECT) |
CCM_ANALOG_PLL_SYS_ENABLE;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) &
CCM_ANALOG_PLL_SYS_LOCK) == 0)
{
}
putreg32(pll2reg, IMXRT_CCM_ANALOG_PFD_528);
/* Init USB PLL3 */
/* capture it's original value */
pll3reg = getreg32(IMXRT_CCM_ANALOG_PFD_480);
putreg32(pll3reg |
CCM_ANALOG_PFD_480_PFD0_CLKGATE |
CCM_ANALOG_PFD_480_PFD1_CLKGATE |
CCM_ANALOG_PFD_480_PFD2_CLKGATE |
CCM_ANALOG_PFD_480_PFD3_CLKGATE,
IMXRT_CCM_ANALOG_PFD_480);
reg = CCM_ANALOG_PLL_USB2_DIV_SELECT(IMXRT_USB2_PLL_DIV_SELECT) |
CCM_ANALOG_PLL_USB2_ENABLE | CCM_ANALOG_PLL_USB2_EN_USB_CLKS |
CCM_ANALOG_PLL_USB2_POWER;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_USB2);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_USB2) &
CCM_ANALOG_PLL_USB2_LOCK) == 0)
{
}
putreg32(pll3reg, IMXRT_CCM_ANALOG_PFD_480);
/* Init Audio PLL4 */
reg = CCM_ANALOG_PLL_AUDIO_DIV_SELECT(IMXRT_AUDIO_PLL_DIV_SELECT) |
CCM_ANALOG_PLL_AUDIO_ENABLE;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_AUDIO);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_AUDIO) &
CCM_ANALOG_PLL_AUDIO_LOCK) == 0)
{
}
/* Init ENET PLL6 */
reg = CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ |
CCM_ANALOG_PLL_ENET_ENET1_125M_EN |
CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN |
CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_ENET);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_ENET) &
CCM_ANALOG_PLL_ENET_LOCK) == 0)
{
}
#else
# error Unrecognised IMXRT family member for clock config
#endif
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_clockconfig
*
* Description:
* Called to initialize the i.MXRT. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the settings in board.h.
*
****************************************************************************/
void imxrt_clockconfig(void)
{
/* Don't change the current basic clock configuration if we are running
* from SDRAM. In this case, some bootloader logic has already configured
* clocking and SDRAM. We are pretty much committed to using things the
* way that the bootloader has left them.
*
* Note that although this is safe at boot while nothing is using
* the clocks additional caution is required if at some later date
* we want to manipulate the PODFs while the system is running
* (for power minimisation) because changing those is not glitch free.
*/
#ifndef CONFIG_IMXRT_BOOT_SDRAM
uint32_t reg;
/* Set clock mux and dividers */
/* Set PERIPH_CLK2 MUX to OSC */
reg = getreg32(IMXRT_CCM_CBCMR);
reg &= ~CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
reg |= CCM_CBCMR_PERIPH_CLK2_SEL_OSC_CLK;
putreg32(reg, IMXRT_CCM_CBCMR);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) != 0)
{
}
/* Set PERIPH_CLK MUX to PERIPH_CLK2 */
reg = getreg32(IMXRT_CCM_CBCDR);
reg &= ~CCM_CBCDR_PERIPH_CLK_SEL_MASK;
reg |= CCM_CBCDR_PERIPH_CLK_SEL(CCM_CBCDR_PERIPH_CLK_SEL_PERIPH_CLK2);
putreg32(reg, IMXRT_CCM_CBCDR);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) != 0)
{
}
/* Set Soc VDD and wait for it to stablise */
reg = getreg32(IMXRT_DCDC_REG3);
reg &= ~(DCDC_REG3_TRG_MASK);
reg |= DCDC_REG3_TRG(IMXRT_VDD_SOC);
putreg32(reg, IMXRT_DCDC_REG3);
while ((getreg32(IMXRT_DCDC_REG0) & DCDC_REG0_STS_DC_OK) == 0)
{
}
/* OK, now nothing is depending on us, configure the PLLs */
imxrt_pllsetup();
/* Set Dividers */
reg = getreg32(IMXRT_CCM_CACRR);
reg &= ~CCM_CACRR_ARM_PODF_MASK;
reg |= CCM_CACRR_ARM_PODF(CCM_PODF_FROM_DIVISOR(IMXRT_ARM_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CACRR);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_ARM_PODF_BUSY) != 0)
{
}
reg = getreg32(IMXRT_CCM_CBCDR);
reg &= ~CCM_CBCDR_AHB_PODF_MASK;
reg |= CCM_CBCDR_AHB_PODF(CCM_PODF_FROM_DIVISOR(IMXRT_AHB_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CBCDR);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_AHB_PODF_BUSY) != 0)
{
}
/* Adjust IPG and PERCLK PODFs. Consumers of these clocks will need to
* be gated if there are any (there aren't at boot).
*/
reg = getreg32(IMXRT_CCM_CBCDR);
reg &= ~CCM_CBCDR_IPG_PODF_MASK;
reg |= CCM_CBCDR_IPG_PODF(CCM_PODF_FROM_DIVISOR(IMXRT_IPG_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CBCDR);
reg = getreg32(IMXRT_CCM_CSCMR1);
reg &= ~CCM_CSCMR1_PERCLK_PODF_MASK;
reg |= CCM_CSCMR1_PERCLK_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_PERCLK_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CSCMR1);
#ifndef CONFIG_IMXRT_SEMC_INIT_DONE
/* Configure SEMC Clock only if not already done by DCD SDR */
reg = getreg32(IMXRT_CCM_CBCDR);
reg &= ~CCM_CBCDR_SEMC_PODF_MASK;
reg |= CCM_CBCDR_SEMC_PODF(CCM_PODF_FROM_DIVISOR(IMXRT_SEMC_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CBCDR);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_SEMC_PODF_BUSY) != 0)
{
}
#endif
/* Set PRE_PERIPH_CLK to Board Selection */
reg = getreg32(IMXRT_CCM_CBCMR);
reg &= ~CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
reg |= CCM_CBCMR_PRE_PERIPH_CLK_SEL(IMXRT_PRE_PERIPH_CLK_SEL);
putreg32(reg, IMXRT_CCM_CBCMR);
/* Set PERIPH_CLK MUX to Board Selection */
reg = getreg32(IMXRT_CCM_CBCDR);
reg &= ~CCM_CBCDR_PERIPH_CLK_SEL_MASK;
reg |= CCM_CBCDR_PERIPH_CLK_SEL(IMXRT_PERIPH_CLK_SEL);
putreg32(reg, IMXRT_CCM_CBCDR);
/* Wait handshake */
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) != 0)
{
}
/* Set PERCLK_CLK_SEL to Board Selection */
reg = getreg32(IMXRT_CCM_CSCMR1);
reg &= ~CCM_CSCMR1_PERCLK_CLK_SEL_MASK;
reg |= CCM_CSCMR1_PERCLK_CLK_SEL(IMXRT_PERCLK_CLK_SEL);
putreg32(reg, IMXRT_CCM_CSCMR1);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) != 0)
{
}
/* Setup perhiperals. At this point these are not activated so don't
* need to worry too much about switching off the clock feeds.
*/
/* Set UART source to PLL3 80M */
reg = getreg32(IMXRT_CCM_CSCDR1);
reg &= ~CCM_CSCDR1_UART_CLK_SEL;
reg |= CCM_CSCDR1_UART_CLK_SEL_PLL3_80;
putreg32(reg, IMXRT_CCM_CSCDR1);
/* Set UART divider to 1 */
reg = getreg32(IMXRT_CCM_CSCDR1);
reg &= ~CCM_CSCDR1_UART_CLK_PODF_MASK;
reg |= CCM_CSCDR1_UART_CLK_PODF(CCM_PODF_FROM_DIVISOR(1));
putreg32(reg, IMXRT_CCM_CSCDR1);
#ifdef CONFIG_IMXRT_FLEXIO1
#ifdef CONFIG_ARCH_FAMILY_IMXRT102x
/* Set FlEXIO1 source */
reg = getreg32(IMXRT_CCM_CSCMR2);
reg &= ~CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK;
reg |= CCM_CSCMR2_FLEXIO1_CLK_SEL(CONFIG_FLEXIO1_CLK);
putreg32(reg, IMXRT_CCM_CSCMR2);
/* Set FlEXIO1 divider */
reg = getreg32(IMXRT_CCM_CS1CDR);
reg &= ~(CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK | \
CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK);
reg |= CCM_CS1CDR_FLEXIO1_CLK_PODF
(CCM_PODF_FROM_DIVISOR(CONFIG_FLEXIO1_PODF_DIVIDER));
reg |= CCM_CS1CDR_FLEXIO1_CLK_PRED
(CCM_PRED_FROM_DIVISOR(CONFIG_FLEXIO1_PRED_DIVIDER));
putreg32(reg, IMXRT_CCM_CS1CDR);
#elif (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x))
/* Set FlEXIO1 source & divider */
reg = getreg32(IMXRT_CCM_CDCDR);
reg &= ~(CCM_CDCDR_FLEXIO1_CLK_SEL_MASK |
CCM_CDCDR_FLEXIO1_CLK_PODF_MASK |
CCM_CDCDR_FLEXIO1_CLK_PRED_MASK);
reg |= CCM_CDCDR_FLEXIO1_CLK_SEL(CONFIG_FLEXIO1_CLK);
reg |= CCM_CDCDR_FLEXIO1_CLK_PODF
(CCM_PODF_FROM_DIVISOR(CONFIG_FLEXIO1_PODF_DIVIDER));
reg |= CCM_CDCDR_FLEXIO1_CLK_PRED
(CCM_PRED_FROM_DIVISOR(CONFIG_FLEXIO1_PRED_DIVIDER));
putreg32(reg, IMXRT_CCM_CDCDR);
#endif /* CONFIG_ARCH_FAMILY_IMXRT102x */
#endif /* CONFIG_IMXRT_FLEXIO1 */
#if (defined(CONFIG_IMXRT_FLEXIO2) || defined(CONFIG_IMXRT_FLEXIO3))
/* Set FlEXIO2 source */
reg = getreg32(IMXRT_CCM_CSCMR2);
reg &= ~CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK;
reg |= CCM_CSCMR2_FLEXIO2_CLK_SEL(CONFIG_FLEXIO2_CLK);
putreg32(reg, IMXRT_CCM_CSCMR2);
/* Set FlEXIO2 divider */
reg = getreg32(IMXRT_CCM_CS1CDR);
reg &= ~(CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK | \
CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK);
reg |= CCM_CS1CDR_FLEXIO2_CLK_PODF
(CCM_PODF_FROM_DIVISOR(CONFIG_FLEXIO2_PODF_DIVIDER));
reg |= CCM_CS1CDR_FLEXIO2_CLK_PRED
(CCM_PRED_FROM_DIVISOR(CONFIG_FLEXIO2_PRED_DIVIDER));
putreg32(reg, IMXRT_CCM_CS1CDR);
#endif /* CONFIG_IMXRT_FLEXIO2 */
#ifdef CONFIG_IMXRT_LPI2C
/* Set LPI2C source to PLL3 60M */
reg = getreg32(IMXRT_CCM_CSCDR2);
reg &= ~CCM_CSCDR2_LPI2C_CLK_SEL;
reg |= IMXRT_LPI2C_CLK_SELECT;
putreg32(reg, IMXRT_CCM_CSCDR2);
/* Set LPI2C divider to 5 for 12 MHz */
reg = getreg32(IMXRT_CCM_CSCDR2);
reg &= ~CCM_CSCDR2_LPI2C_CLK_PODF_MASK;
reg |= CCM_CSCDR2_LPI2C_CLK_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_LSI2C_PODF_DIVIDER)
);
putreg32(reg, IMXRT_CCM_CSCDR2);
#endif
#ifdef CONFIG_IMXRT_FLEXCAN
/* Set FlexCAN clock source to PLL3 80M */
reg = getreg32(IMXRT_CCM_CSCMR2);
reg &= ~CCM_CSCMR2_CAN_CLK_SEL_MASK;
reg |= IMXRT_CAN_CLK_SELECT;
putreg32(reg, IMXRT_CCM_CSCMR2);
/* Set FlexCAN dividet to 1 for 80 MHz */
reg = getreg32(IMXRT_CCM_CSCMR2);
reg &= ~CCM_CSCMR2_CAN_CLK_PODF_MASK;
reg |= CCM_CSCMR2_CAN_CLK_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_CAN_PODF_DIVIDER)
);
putreg32(reg, IMXRT_CCM_CSCMR2);
#endif
#ifdef CONFIG_IMXRT_LPSPI
/* Set LPSPI clock source to PLL3 PFD0 */
reg = getreg32(IMXRT_CCM_CBCMR);
reg &= ~CCM_CBCMR_LPSPI_CLK_SEL_MASK;
reg |= IMXRT_LPSPI_CLK_SELECT;
putreg32(reg, IMXRT_CCM_CBCMR);
/* Set LPSPI divider to IMXRT_LSPI_PODF_DIVIDER */
reg = getreg32(IMXRT_CCM_CBCMR);
reg &= ~CCM_CBCMR_LPSPI_PODF_MASK;
reg |= CCM_CBCMR_LPSPI_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_LSPI_PODF_DIVIDER)
);
putreg32(reg, IMXRT_CCM_CBCMR);
#endif
#ifdef IMXRT_TRACE_PODF_DIVIDER
/* Set TRACE clock source and speed */
reg = getreg32(IMXRT_CCM_CBCMR);
reg &= ~CCM_CBCMR_TRACE_CLK_SEL_MASK;
reg |= IMXRT_TRACE_CLK_SELECT;
putreg32(reg, IMXRT_CCM_CBCMR);
reg = getreg32(IMXRT_CCM_CSCDR1);
reg &= ~CCM_CSCDR1_TRACE_PODF_MASK;
reg |= CCM_CSCDR1_TRACE_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_TRACE_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CSCDR1);
#endif
#ifdef CONFIG_IMXRT_USDHC
/* Optionally set USDHC1 & 2 to generate clocks
* from IMXRT_USDHC1_CLK_SELECT
*/
reg = getreg32(IMXRT_CCM_CSCMR1);
reg &= ~(CCM_CSCMR1_USDHC1_CLK_SEL | CCM_CSCMR1_USDHC2_CLK_SEL);
#if defined(IMXRT_USDHC1_CLK_SELECT)
reg |= IMXRT_USDHC1_CLK_SELECT;
#endif
#if defined(IMXRT_USDHC2_CLK_SELECT)
reg |= IMXRT_USDHC2_CLK_SELECT;
#endif
putreg32(reg, IMXRT_CCM_CSCMR1);
/* Now divide down clocks by IMXRT_USDHC[1|2]_PODF_DIVIDER */
reg = getreg32(IMXRT_CCM_CSCDR1);
reg &= ~(CCM_CSCDR1_USDHC1_PODF_MASK | CCM_CSCDR1_USDHC2_PODF_MASK);
#if defined(IMXRT_USDHC1_PODF_DIVIDER)
reg |= CCM_CSCDR1_USDHC1_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_USDHC1_PODF_DIVIDER));
#endif
#if defined(IMXRT_USDHC2_PODF_DIVIDER)
reg |= CCM_CSCDR1_USDHC2_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_USDHC2_PODF_DIVIDER));
#endif
putreg32(reg, IMXRT_CCM_CSCDR1);
#endif
/* Ensure platform memory clocks remain enabled in WFI */
reg = getreg32(IMXRT_CCM_CGPR);
reg |= CCM_CGPR_INT_MEM_CLK_LPM;
putreg32(reg, IMXRT_CCM_CGPR);
/* Remain in run mode */
modifyreg32(IMXRT_CCM_CLPCR,
CCM_CLPCR_LPM_MASK,
CCM_CLPCR_LPM_RUN);
#endif
}

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@ -0,0 +1,603 @@
/****************************************************************************
* arch/arm/src/imxrt/imxrt_lowputc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <fixedmath.h>
#include <assert.h>
#include "arm_arch.h"
#include "hardware/imxrt_iomuxc.h"
#include "hardware/imxrt_pinmux.h"
#include "hardware/imxrt_ccm.h"
#include "hardware/imxrt_lpuart.h"
#include "imxrt_config.h"
#include "imxrt_periphclks.h"
#include "imxrt_iomuxc.h"
#include "imxrt_gpio.h"
#include "imxrt_lowputc.h"
#include "arm_internal.h"
#include <arch/board/board.h> /* Include last: has dependencies */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#ifdef HAVE_LPUART_CONSOLE
# if defined(CONFIG_LPUART1_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART1_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART1_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART1_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART1_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART1_2STOP
# elif defined(CONFIG_LPUART2_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART2_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART2_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART2_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART2_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART2_2STOP
# elif defined(CONFIG_LPUART3_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART3_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART3_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART3_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART3_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART3_2STOP
# elif defined(CONFIG_LPUART4_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART4_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART4_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART4_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART4_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART4_2STOP
# elif defined(CONFIG_LPUART5_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART5_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART5_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART5_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART5_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART5_2STOP
# elif defined(CONFIG_LPUART6_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART6_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART6_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART6_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART6_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART6_2STOP
# elif defined(CONFIG_LPUART7_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART7_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART7_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART7_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART7_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART7_2STOP
# elif defined(CONFIG_LPUART8_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART8_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART8_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART8_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART8_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART8_2STOP
# endif
#endif
/* Clocking *****************************************************************/
/* The UART module receives two clocks, a peripheral_clock (ipg_clk) and the
* module_clock (ipg_perclk). The peripheral_clock is used as write clock
* of the TxFIFO, read clock of the RxFIFO and synchronization of the modem
* control input pins. It must always be running when UART is enabled.
*
* The default lpuart1 ipg_clk is 66MHz (max 66.5MHz). ipg_clk is shared
* among many modules and should not be controlled by the UART logic.
*
* The module_clock is for all the state machines, writing RxFIFO, reading
* TxFIFO, etc. It must always be running when UART is sending or receiving
* characters. This clock is used in order to allow frequency scaling on
* peripheral_clock without changing configuration of baud rate.
*
* The default ipg_perclk is 80MHz (max 80MHz). ipg_perclk is gated by
* CCGR5[CG12], lpuart1_clk_enable. The clock generation sequence is:
*
* pll3_sw_clk (480M) -> CCGR5[CG12] -> 3 bit divider cg podf=6 ->
* PLL3_80M (80Mhz) -> CDCDR1: lpuart1_clk_podf ->
* 6 bit divider default=1 -> LPUART1_CLK_ROOT
*
* REVISIT: This logic assumes that all dividers are at the default value
* and that the value of the ipg_perclk is 80MHz.
*/
#define IPG_PERCLK_FREQUENCY 80000000
/* The BRM sub-block receives ref_clk (module_clock clock after divider).
* From this clock, and with integer and non-integer division, BRM generates
* a 16x baud rate clock.
*/
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef HAVE_LPUART_CONSOLE
static const struct uart_config_s g_console_config =
{
.baud = IMXRT_CONSOLE_BAUD, /* Configured baud */
.parity = IMXRT_CONSOLE_PARITY, /* 0=none, 1=odd, 2=even */
.bits = IMXRT_CONSOLE_BITS, /* Number of bits (5-9) */
.stopbits2 = IMXRT_CONSOLE_2STOP, /* true: Configure with 2 stop bits instead of 1 */
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
void imxrt_lpuart_clock_enable (uint32_t base)
{
if (base == IMXRT_LPUART1_BASE)
{
imxrt_clockall_lpuart1();
}
else if (base == IMXRT_LPUART2_BASE)
{
imxrt_clockall_lpuart2();
}
else if (base == IMXRT_LPUART3_BASE)
{
imxrt_clockall_lpuart3();
}
else if (base == IMXRT_LPUART4_BASE)
{
imxrt_clockall_lpuart4();
}
else if (base == IMXRT_LPUART5_BASE)
{
imxrt_clockall_lpuart5();
}
else if (base == IMXRT_LPUART6_BASE)
{
imxrt_clockall_lpuart6();
}
else if (base == IMXRT_LPUART7_BASE)
{
imxrt_clockall_lpuart7();
}
else if (base == IMXRT_LPUART8_BASE)
{
imxrt_clockall_lpuart8();
}
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level
* initialization including setup of the console UART. This UART done
* early so that the serial console is available for debugging very early
* in the boot sequence.
*
****************************************************************************/
void imxrt_lowsetup(void)
{
#ifndef CONFIG_SUPPRESS_LPUART_CONFIG
#ifdef HAVE_LPUART_DEVICE
#ifdef CONFIG_IMXRT_LPUART1
/* Configure LPUART1 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART1_RX);
imxrt_config_gpio(GPIO_LPUART1_TX);
#ifdef CONFIG_LPUART1_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART1_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART1_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART2
/* Configure LPUART2 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART2_RX);
imxrt_config_gpio(GPIO_LPUART2_TX);
#ifdef CONFIG_LPUART2_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART2_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART2_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART3
/* Configure LPUART3 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART3_RX);
imxrt_config_gpio(GPIO_LPUART3_TX);
#ifdef CONFIG_LPUART3_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART3_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART3_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART4
/* Configure LPUART4 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART4_RX);
imxrt_config_gpio(GPIO_LPUART4_TX);
#ifdef CONFIG_LPUART4_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART4_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART4_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART5
/* Configure LPUART5 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART5_RX);
imxrt_config_gpio(GPIO_LPUART5_TX);
#ifdef CONFIG_LPUART5_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART5_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART5_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART6
/* Configure LPUART6 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART6_RX);
imxrt_config_gpio(GPIO_LPUART6_TX);
#ifdef CONFIG_LPUART6_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART6_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART6_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART7
/* Configure LPUART7 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART7_RX);
imxrt_config_gpio(GPIO_LPUART7_TX);
#ifdef CONFIG_LPUART7_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART7_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART7_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART8
/* Configure LPUART8 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART8_RX);
imxrt_config_gpio(GPIO_LPUART8_TX);
#ifdef CONFIG_LPUART8_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART8_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART8_RTS);
#endif
#endif
#ifdef HAVE_LPUART_CONSOLE
/* Configure the serial console for initial, non-interrupt driver mode */
imxrt_lpuart_configure(IMXRT_CONSOLE_BASE, &g_console_config);
#endif
#endif /* HAVE_LPUART_DEVICE */
#endif /* CONFIG_SUPPRESS_LPUART_CONFIG */
}
/****************************************************************************
* Name: imxrt_lpuart_configure
*
* Description:
* Configure a UART for non-interrupt driven operation
*
****************************************************************************/
#ifdef HAVE_LPUART_DEVICE
int imxrt_lpuart_configure(uint32_t base,
FAR const struct uart_config_s *config)
{
uint32_t src_freq = 0;
uint32_t pll3_div = 0;
uint32_t uart_div = 0;
uint32_t lpuart_freq = 0;
uint16_t sbr;
uint16_t temp_sbr;
uint32_t osr;
uint32_t temp_osr;
uint32_t temp_diff;
uint32_t calculated_baud;
uint32_t baud_diff;
uint32_t regval;
uint32_t regval2;
if ((getreg32(IMXRT_CCM_CSCDR1) & CCM_CSCDR1_UART_CLK_SEL) != 0)
{
src_freq = BOARD_XTAL_FREQUENCY;
}
else
{
if ((getreg32(IMXRT_CCM_ANALOG_PLL_USB2) &
CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) != 0)
{
pll3_div = 22;
}
else
{
pll3_div = 20;
}
src_freq = (BOARD_XTAL_FREQUENCY * pll3_div) / 6;
}
uart_div = (getreg32(IMXRT_CCM_CSCDR1) &
CCM_CSCDR1_UART_CLK_PODF_MASK) + 1;
lpuart_freq = src_freq / uart_div;
/* This LPUART instantiation uses a slightly different baud rate
* calculation. The idea is to use the best OSR (over-sampling rate)
* possible.
*
* NOTE: OSR is typically hard-set to 16 in other LPUART instantiations
* loop to find the best OSR value possible, one that generates minimum
* baud_diff iterate through the rest of the supported values of OSR
*/
baud_diff = config->baud;
osr = 0;
sbr = 0;
for (temp_osr = 4; temp_osr <= 32; temp_osr++)
{
/* Calculate the temporary sbr value */
temp_sbr = (lpuart_freq / (config->baud * temp_osr));
/* Set temp_sbr to 1 if the sourceClockInHz can not satisfy the
* desired baud rate.
*/
if (temp_sbr == 0)
{
temp_sbr = 1;
}
/* Calculate the baud rate based on the temporary OSR and SBR values */
calculated_baud = (lpuart_freq / (temp_osr * temp_sbr));
temp_diff = calculated_baud - config->baud;
/* Select the better value between srb and (sbr + 1) */
if (temp_diff > (config->baud -
(lpuart_freq / (temp_osr * (temp_sbr + 1)))))
{
temp_diff = config->baud -
(lpuart_freq / (temp_osr * (temp_sbr + 1)));
temp_sbr++;
}
if (temp_diff <= baud_diff)
{
baud_diff = temp_diff;
osr = temp_osr;
sbr = temp_sbr;
}
}
if (baud_diff > ((config->baud / 100) * 3))
{
/* Unacceptable baud rate difference of more than 3% */
return ERROR;
}
/* Enable lpuart clock */
imxrt_lpuart_clock_enable(base);
/* Reset all internal logic and registers, except the Global Register */
regval = getreg32(base + IMXRT_LPUART_GLOBAL_OFFSET);
regval |= LPUART_GLOBAL_RST;
putreg32(regval, base + IMXRT_LPUART_GLOBAL_OFFSET);
regval &= ~LPUART_GLOBAL_RST;
putreg32(regval, base + IMXRT_LPUART_GLOBAL_OFFSET);
/* Construct MODIR register */
regval = 0;
if (config->userts)
{
regval |= LPUART_MODIR_RXRTSE;
}
else if (config->users485)
{
/* Both TX and RX side can't control RTS, so this gives
* the RX side precedence. This should have been filtered
* in layers above anyway, but it's just a precaution.
*/
regval |= LPUART_MODIR_TXRTSE;
}
if (config->usects)
{
regval |= LPUART_MODIR_TXCTSE;
}
if (config->invrts)
{
regval |= LPUART_MODIR_TXRTSPOL;
}
putreg32(regval, base + IMXRT_LPUART_MODIR_OFFSET);
regval = 0;
if ((osr > 3) && (osr < 8))
{
regval |= LPUART_BAUD_BOTHEDGE;
}
if (config->stopbits2)
{
regval |= LPUART_BAUD_SBNS;
}
regval |= LPUART_BAUD_OSR(osr) | LPUART_BAUD_SBR(sbr);
putreg32(regval, base + IMXRT_LPUART_BAUD_OFFSET);
regval = 0;
if (config->parity == 1)
{
regval |= LPUART_CTRL_PE | LPUART_CTRL_PT_ODD;
}
else if (config->parity == 2)
{
regval |= LPUART_CTRL_PE | LPUART_CTRL_PT_EVEN;
}
if (config->bits == 9 || (config->bits == 8 && config->parity != 0))
{
regval |= LPUART_CTRL_M;
}
else if ((config->bits == 8))
{
regval &= ~LPUART_CTRL_M;
}
else
{
/* Here should be added support of other bit modes. */
#warning missing logic
return ERROR;
}
regval2 = getreg32(base + IMXRT_LPUART_FIFO_OFFSET);
regval2 |= LPUART_FIFO_RXFLUSH | LPUART_FIFO_TXFLUSH |
LPUART_FIFO_RXFE | LPUART_FIFO_RXIDEN_1 | LPUART_FIFO_TXFE;
putreg32(regval2 , base + IMXRT_LPUART_FIFO_OFFSET);
regval |= LPUART_CTRL_RE | LPUART_CTRL_TE;
putreg32(regval, base + IMXRT_LPUART_CTRL_OFFSET);
return OK;
}
#endif /* HAVE_LPUART_DEVICE */
/****************************************************************************
* Name: imxrt_lowputc
*
* Description:
* Output a byte with as few system dependencies as possible. This will
* even work BEFORE the console is initialized if we are booting from U-
* Boot (and the same UART is used for the console, of course.)
*
****************************************************************************/
#if defined(HAVE_LPUART_DEVICE) && defined(CONFIG_DEBUG_FEATURES)
void imxrt_lowputc(int ch)
{
while ((getreg32(IMXRT_CONSOLE_BASE + IMXRT_LPUART_STAT_OFFSET) &
LPUART_STAT_TDRE) == 0)
{
}
/* If the character to output is a newline, then pre-pend a carriage
* return
*/
if (ch == '\n')
{
/* Send the carriage return by writing it into the UART_TXD register. */
putreg32((uint32_t)'\r', IMXRT_CONSOLE_BASE +
IMXRT_LPUART_DATA_OFFSET);
/* Wait for the transmit register to be emptied. When the TXFE bit is
* non-zero, the TX Buffer FIFO is empty.
*/
while ((getreg32(IMXRT_CONSOLE_BASE + IMXRT_LPUART_STAT_OFFSET) &
LPUART_STAT_TDRE) == 0)
{
}
}
/* Send the character by writing it into the UART_TXD register. */
putreg32((uint32_t)ch, IMXRT_CONSOLE_BASE + IMXRT_LPUART_DATA_OFFSET);
}
#endif

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13
Ubiquitous/Nuttx_Fusion_XiUOS/readme.md
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@ -266,23 +266,22 @@ git clone https://git.trustie.net/xuos/kconfig-frontends.git
#### 在Nuttx\app_match_nuttx目录下执行
```shell
chmod +x build.sh
source build.sh
```
#### 执行完毕会跳转到Nuttx\nuttx目录，执行
```shell
sudo ./tools/configure.sh stm32f4discovery:nsh (应用内核一起编译)
./tools/configure.sh stm32f4discovery:nsh (应用内核一起编译)
sudo ./tools/configure.sh stm32f4discovery:kostest (应用内核分开编译)
./tools/configure.sh stm32f4discovery:kostest (应用内核分开编译)
视情况而定，如果需要前面加sudo
```
#### 然后执行
```shell
sudo make menuconfig
make menuconfig
```
##### 开启Nuttx Support CLOCK_MONOTONIC
@ -328,7 +327,9 @@ sudo make menuconfig
#### 在当前目录执行编译
```shell
sudo make -j8
make
或
make -j8
```
make时加上V=1参数可以看到较为详细的编译信息，但是编译过程会比较慢。最后在nuttx下会编译出一个nuttx.bin文件(应用内核一起编译)

4
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/ethernet/enet_ethernetif.c
View File

@ -99,7 +99,7 @@ void ethernetif_clk_init(void)
{
const clock_enet_pll_config_t config = {.enableClkOutput = true, .enableClkOutput25M = false, .loopDivider = 1};
CLOCK_InitEnetPll(&config);
SysTick_Config(USEC_TO_COUNT(1000U, CLOCK_GetFreq(kCLOCK_CoreSysClk)));
SysTick_Config(SystemCoreClock / TICK_PER_SECOND);
}
void ethernetif_gpio_init(void)
@ -109,9 +109,7 @@ void ethernetif_gpio_init(void)
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
GPIO_PinInit(GPIO1, 3, &gpio_config);
GPIO_PinInit(GPIO1, 10, &gpio_config);
/* pull up the ENET_INT before RESET. */
GPIO_WritePinOutput(GPIO1, 10, 1);
GPIO_WritePinOutput(GPIO1, 3, 0);
enet_delay();
GPIO_WritePinOutput(GPIO1, 3, 1);

6
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/uart/connect_uart.c
View File

@ -41,11 +41,9 @@ void LPUART1_IRQHandler(int irqn, void *arg)
{
x_base lock = 0;
// KPrintf("LPUART1_IRQHandler \n");
lock = DISABLE_INTERRUPT();
lock = DisableIRQ(UART1_IRQn);
UartIsr(&serial_bus_1, &serial_driver_1, &serial_device_1);
ENABLE_INTERRUPT(lock);
EnableIRQ(UART1_IRQn);
}
DECLARE_HW_IRQ(UART1_IRQn, LPUART1_IRQHandler, NONE);
#endif

2
Ubiquitous/XiZi/path_kernel.mk
View File

@ -305,7 +305,7 @@ KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/connection/zigbee
endif
ifeq ($(CONFIG_ADAPTER_HFA21_ETHERCAT), y)
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/connection/ethercat #
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/connection/industrial_ethernet/ethercat #
endif
ifeq ($(CONFIG_SUPPORT_KNOWING_FRAMEWORK), y)

8
Ubiquitous/XiZi/resources/ethernet/LwIP/arch/sys_arch.c
View File

@ -184,7 +184,7 @@ sys_sem_free(sys_sem_t *sem)
int sys_sem_valid(sys_sem_t *sem)
{
return (*sem >= SYS_SEM_NULL);
return (*sem > SYS_SEM_NULL);
}
void
@ -212,7 +212,7 @@ u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout)
if(KSemaphoreObtain(*sem, wait_time) == EOK)
return ((CurrentTicksGain()-start_tick)*MS_PER_SYSTICK_F407);
return ((CurrentTicksGain()-start_tick)*MS_PER_SYSTICK);
else
return SYS_ARCH_TIMEOUT;
}
@ -226,7 +226,7 @@ void sys_sem_signal(sys_sem_t *sem)
err_t sys_mutex_new(sys_mutex_t *mutex)
{
*mutex = KMutexCreate();
if(*mutex >= 0)
if(*mutex > SYS_MRTEX_NULL)
return ERR_OK;
else
{
@ -344,7 +344,7 @@ u32_t sys_arch_mbox_fetch(sys_mbox_t *q, void **msg, u32_t timeout)
wait_time = timeout;
if(KMsgQueueRecv(*q, &(*msg), sizeof(void *), wait_time) == EOK)
return ((CurrentTicksGain()-start_tick)*MS_PER_SYSTICK_F407);
return ((CurrentTicksGain()-start_tick)*MS_PER_SYSTICK);
else{
*msg = NULL;
return SYS_ARCH_TIMEOUT;

4
Ubiquitous/XiZi/resources/ethernet/LwIP/arch/sys_arch.h
View File

@ -62,7 +62,7 @@
/* USER CODE END 0 */
#define SYS_MBOX_NULL -1
#define SYS_SEM_NULL 0
#define SYS_SEM_NULL -1
#define SYS_MRTEX_NULL SYS_SEM_NULL
typedef int32 sys_sem_t;
@ -71,7 +71,7 @@ typedef int32 sys_mbox_t;
typedef int32 sys_thread_t;
typedef x_base sys_prot_t;
#define MS_PER_SYSTICK_F407 (1000 / TICK_PER_SECOND)
#define MS_PER_SYSTICK (1000 / TICK_PER_SECOND)
//debug rtos with IRQ
//#define FSL_RTOS_XIUOS

1
Ubiquitous/XiZi/tool/shell/letter-shell/shell.c
View File

@ -1652,7 +1652,6 @@ void shellTask(void *param)
shellHandler(shell, data[i]);
}
}
KPrintf("");
}
}