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add timer and flash and can drivers with test examples for hc32f4a0 in XiZi_IIoT from Wu_zheng 

it is OK
This commit is contained in:
xuedongliang 2023-02-27 12:13:39 +08:00
parent 35dc835d12 918b3663b8
commit 779444f998
49 changed files with 1370 additions and 95 deletions
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26
APP_Framework/Applications/app_test/Kconfig
View File

@ -111,6 +111,9 @@ menu "test app"
default n
if USER_TEST_HWTIMER
if ADD_XIZI_FETURES
config HWTIMER_TIMER_DEV_DRIVER
string "Set pin dev path"
default "/dev/timer0_dev0"
config HWTIMER_PIN_DEV_DRIVER
string "Set pin dev path"
default "/dev/pin_dev"
@ -168,6 +171,18 @@ menu "test app"
endif
endif
menuconfig USER_TEST_CAN
select BSP_USING_CAN
bool "Config test can"
default n
if USER_TEST_CAN
if ADD_XIZI_FETURES
config CAN_DEV_DRIVER
string "Set can dev path"
default "/dev/can2_dev1"
endif
endif
menuconfig USER_TEST_CAMERA
select BSP_USING_CAMERA
select BSP_USING_LCD
@ -210,5 +225,16 @@ menu "test app"
endif
endif
menuconfig USER_TEST_FLASH
bool "Config test w25q128 device"
default n
if USER_TEST_FLASH
if ADD_XIZI_FETURES
config FLASH_DEV_DRIVER
string "Set flash dev path"
default "/dev/qspi_W25Q128"
endif
endif
endif
endmenu

8
APP_Framework/Applications/app_test/Makefile
View File

@ -89,5 +89,13 @@ ifeq ($(CONFIG_ADD_XIZI_FETURES),y)
SRC_FILES += test_ethernet.c
endif
ifeq ($(CONFIG_USER_TEST_FLASH),y)
SRC_FILES += test_flash.c
endif
ifeq ($(CONFIG_USER_TEST_CAN),y)
SRC_FILES += test_can.c
endif
include $(KERNEL_ROOT)/compiler.mk
endif

66
APP_Framework/Applications/app_test/test_can.c Normal file
View File

@ -0,0 +1,66 @@
#include <stdio.h>
#include <string.h>
#include <transform.h>
void TestCAN(void)
{
// config CAN pin(SCL:34.SDA:35) in menuconfig
int can_fd = PrivOpen(CAN_DEV_DRIVER, O_RDWR);
if (can_fd < 0)
{
printf("open can_fd fd error:%d\n", can_fd);
return;
}
printf("CAN open successful!\n");
struct PrivIoctlCfg ioctl_cfg;
ioctl_cfg.ioctl_driver_type = CAN_TYPE;
struct CanDriverConfigure can_config;
can_config.brp = 8U;
can_config.tbs1 = 1U + 8U;
can_config.tbs2 = 4U;
can_config.tsjw = 4U;
can_config.mode = 0U;
ioctl_cfg.args = (void *)&can_config;
if (0 != PrivIoctl(can_fd, OPE_INT, &ioctl_cfg))
{
printf("init can fd error %d\n", can_fd);
PrivClose(can_fd);
return;
}
printf("CAN configure successful!\n");
uint8_t data_buff[64u] = {1,2,3,4,4,3,2,1};
struct CanSendConfigure frame_send;
frame_send.ide=0;
frame_send.stdid = 0x55;
frame_send.rtr=0;
frame_send.data_lenth=8;
frame_send.data = data_buff;
struct CanSendConfigure frame_recv;
uint8_t recv_buff[65U] = {0};
frame_recv.data = recv_buff;
// CAN write
while (1)
{
PrivTaskDelay(500);
PrivWrite(can_fd, &frame_send, NONE);
PrivTaskDelay(500);
PrivRead(can_fd, &frame_recv, NONE);
// if any data has received,Then printf message
if(frame_recv.data_lenth > 0){
printf("ID %08x:%s\n",frame_recv.exdid,frame_recv.data);
}
}
PrivClose(can_fd);
return;
}
PRIV_SHELL_CMD_FUNCTION(TestCAN, a can test sample, PRIV_SHELL_CMD_MAIN_ATTR);

35
APP_Framework/Applications/app_test/test_flash.c Normal file
View File

@ -0,0 +1,35 @@
#include <stdio.h>
#include <string.h>
#include <transform.h>
void TestFlash(void)
{
int fd = open(FLASH_DEV_DRIVER,O_RDWR);
if(fd<0){
printf("fs fd open error:%d\n",fd);
return;
}
struct BusBlockWriteParam flash_writer;
uint8_t read_buff[8] = {1,2,3,4,5,6,7,8};
flash_writer.pos = 0x000000L;
flash_writer.size = 8;
flash_writer.buffer = read_buff;
struct BusBlockReadParam flash_reader;
flash_reader.pos = 0x000000L;
flash_reader.size = 8;
flash_reader.buffer = read_buff;
PrivRead(fd,&flash_reader,NONE);
printf("Read data is:");
for(int i=0;i<flash_writer.size;i++){
printf("%02x ",read_buff[i]);
read_buff[i]++;
}
printf("\n");
PrivWrite(fd,&flash_writer,NONE);
return;
}
PRIV_SHELL_CMD_FUNCTION(TestFlash, a flash test sample, PRIV_SHELL_CMD_MAIN_ATTR);

41
APP_Framework/Applications/app_test/test_hwtimer.c
View File

@ -2,25 +2,22 @@
#include <string.h>
#include <transform.h>
#define BSP_LED_PIN 29
#define BSP_LED_PIN 134
#define NULL_PARAMETER 0
static uint16_t pinval=0;
static uint16_t pin_fd=0;
static struct PinStat pin_led;
void ledflip(void *parameter)
{
struct PinStat pin_led;
pin_led.pin = BSP_LED_PIN;
pin_led.val = !pinval;
pinval = !pinval;
pin_led.val = !pin_led.val;
PrivWrite(pin_fd,&pin_led,NULL_PARAMETER);
// printf("Timer has callback once:%d\n",pinval);
}
void TestHwTimer(void)
{
x_ticks_t period = 100;//uint:10ms
x_ticks_t period = 100000;
pin_fd = PrivOpen(HWTIMER_PIN_DEV_DRIVER, O_RDWR);
if(pin_fd<0){
@ -28,6 +25,12 @@ void TestHwTimer(void)
return;
}
int timer_fd = PrivOpen(HWTIMER_TIMER_DEV_DRIVER, O_RDWR);
if(timer_fd<0){
printf("open timer fd error:%d\n",timer_fd);
return;
}
//config led pin in board
struct PinParam parameter;
parameter.cmd = GPIO_CONFIG_MODE;
@ -44,10 +47,30 @@ void TestHwTimer(void)
return;
}
int32 timer_handle = KCreateTimer("LED on and off by 1s",&ledflip,&pin_fd,period,TIMER_TRIGGER_PERIODIC);
ioctl_cfg.ioctl_driver_type = TIME_TYPE;
ioctl_cfg.args = (void *)&ledflip;
if (0 != PrivIoctl(timer_fd, OPE_INT, &ioctl_cfg)) {
printf("timer pin fd error %d\n", pin_fd);
PrivClose(pin_fd);
return;
}
KTimerStartRun(timer_handle);
ioctl_cfg.args = (void *)&period;
if (0 != PrivIoctl(timer_fd, OPE_CFG, &ioctl_cfg)) {
printf("timer pin fd error %d\n", pin_fd);
PrivClose(pin_fd);
return;
}
while(1){
}
// int32 timer_handle = KCreateTimer("LED on and off by 1s",&ledflip,&pin_fd,period,TIMER_TRIGGER_PERIODIC);
// KTimerStartRun(timer_handle);
PrivClose(pin_fd);
PrivClose(timer_fd);
}
PRIV_SHELL_CMD_FUNCTION(TestHwTimer, a timer test sample, PRIV_SHELL_CMD_MAIN_ATTR);

1
APP_Framework/Applications/app_test/test_touch.c
View File

@ -105,6 +105,7 @@ void TestTouch(void)
graph_param.pixel_info.y_endpos = touch_pixel.y+10;
PrivWrite(lcd_fd, &graph_param, NULL_PARAMETER);
}
PrivClose(lcd_fd);
PrivClose(touch_fd);
}

14
APP_Framework/Applications/knowing_app/Makefile
View File

@ -1,3 +1,15 @@
SRC_DIR := mnist
SRC_DIR :=
ifeq ($(CONFIG_APP_MNIST),y)
SRC_DIR += mnist
endif
ifeq ($(CONFIG_USING_NNOM_DEMOAPP),y)
SRC_DIR += nnom_demo
endif
ifeq ($(CONFIG_USING_CMSIS_5_DEMOAPP),y)
SRC_DIR += cmsis_5_demo
endif
include $(KERNEL_ROOT)/compiler.mk

11
APP_Framework/Applications/knowing_app/cmsis_5_demo/Makefile Executable file
View File

@ -0,0 +1,11 @@
SRC_DIR :=
ifeq ($(CONFIG_USING_CMSIS_5_NN_DEMOAPP),y)
SRC_DIR += cmsisnn-cifar10
endif
ifeq ($(CONFIG_USING_CMSIS_5_NN_DEMOAPP_VEG_CLASSIFY),y)
SRC_DIR += cmsisnn_vegetable_classify
endif
include $(KERNEL_ROOT)/compiler.mk

3
APP_Framework/Applications/knowing_app/cmsis_5_demo/cmsisnn-cifar10/Makefile Executable file
View File

@ -0,0 +1,3 @@
SRC_FILES := demo/cmsisnn_demo.c demo/tjpgd.c model/m4/nn.c
include $(KERNEL_ROOT)/compiler.mk

3
APP_Framework/Applications/knowing_app/cmsis_5_demo/cmsisnn_vegetable_classify/Makefile Executable file
View File

@ -0,0 +1,3 @@
SRC_FILES := cmsisnn_vegetable_classify.c
include $(KERNEL_ROOT)/compiler.mk

4
APP_Framework/Applications/knowing_app/mnist/Makefile
View File

@ -1,7 +1,9 @@
SRC_FILES :=
ifeq ($(CONFIG_APP_MNIST),y)
SRC_FILES := \
main.cpp \
mnistmain.c
CPPPATHS += -I.
endif
include $(KERNEL_ROOT)/compiler.mk

5
APP_Framework/Applications/knowing_app/nnom_demo/Makefile Executable file
View File

@ -0,0 +1,5 @@
ifeq ($(CONFIG_USING_NNOM_DEMOAPP),y)
SRC_DIR := mnist_nnom
endif
include $(KERNEL_ROOT)/compiler.mk

3
APP_Framework/Applications/knowing_app/nnom_demo/mnist_nnom/Makefile Executable file
View File

@ -0,0 +1,3 @@
SRC_FILES := main.c
include $(KERNEL_ROOT)/compiler.mk

4
APP_Framework/Applications/knowing_app/nnom_demo/mnist_nnom/main.c
View File

@ -71,7 +71,9 @@ void mnist_nnom(int argc, char **argv)
printf("Predicted label: %d\n", predic_label);
printf("Probability: %d%%\n", (int)(prob * 100));
}
#ifdef ADD_XIZI_FETURES
PRIV_SHELL_CMD_FUNCTION(mnist_nnom, a mnist_nnom test sample, PRIV_SHELL_CMD_MAIN_ATTR);
#endif
#ifdef __RT_THREAD_H__
MSH_CMD_EXPORT(mnist_nnom, nnom mnist demo and image number should be followed);
#endif

2
APP_Framework/Framework/knowing/Makefile
View File

@ -1,4 +1,4 @@
SRC_DIR := kpu tensorflow-lite
SRC_DIR := cmsis_5 filter image_processing kpu nnom ota tensorflow-lite
include $(KERNEL_ROOT)/compiler.mk

8
APP_Framework/Framework/knowing/cmsis_5/Makefile Normal file
View File

@ -0,0 +1,8 @@
ifeq ($(CONFIG_USING_CMSIS_5),y)
SRC_FILES := $(wildcard NN/Source/ActivationFunctions/*.c) $(wildcard NN/Source/BasicMathFunctions/*.c) $(wildcard NN/Source/ConcatenationFunctions/*.c)\
$(wildcard NN/Source/ConvolutionFunctions/*.c) $(wildcard NN/Source/FullyConnectedFunctions/*.c) $(wildcard NN/Source/NNSupportFunctions/*.c) \
$(wildcard NN/Source/PoolingFunctions/*.c) $(wildcard NN/Source/ReshapeFunctions/*.c) $(wildcard NN/Source/SoftmaxFunctions/*.c) $(wildcard NN/Source/SVDFunctions/*.c)
endif
include $(KERNEL_ROOT)/compiler.mk

6
APP_Framework/Framework/knowing/nnom/Makefile Normal file
View File

@ -0,0 +1,6 @@
SRC_DIR :=
ifeq ($(CONFIG_USING_NNOM),y)
SRC_FILES := $(wildcard src/backends/*.c) $(wildcard src/core/*.c) $(wildcard src/layers/*.c)
endif
include $(KERNEL_ROOT)/compiler.mk

2
APP_Framework/Framework/knowing/nnom/src/layers/nnom_reshape.c
View File

@ -45,7 +45,7 @@ nnom_layer_t *reshape_s(const nnom_reshape_config_t *config)
// config
//nnom_memcpy(layer->dim, config->dim, config->num_dim * sizeof(nnom_shape_data_t));
layer->super.config = config;
layer->super.config = (void*)config;
layer->dim = config->dim; // temporary use the config directly. (not preferable.)
layer->num_dim = config->num_dim;

6
APP_Framework/Framework/knowing/tensorflow-lite/Makefile
View File

@ -1,3 +1,7 @@
SRC_DIR := tensorflow-lite-for-mcu
SRC_DIR :=
ifeq ($(CONFIG_USING_TENSORFLOWLITEMICRO),y)
SRC_DIR += tensorflow-lite-for-mcu
endif
include $(KERNEL_ROOT)/compiler.mk

10
APP_Framework/Framework/sensor/winddirection/qs-fx/qs-fx.c
View File

@ -69,6 +69,7 @@ static int SensorDeviceOpen(struct SensorDevice *sdev)
return result;
}
#ifdef ADD_XIZI_FETURES
static int PinOpen(void){
int pin_fd = PrivOpen(SENSOR_DEVICE_QS_FX_PIN_DEV, O_RDWR);
if (pin_fd < 0) {
@ -95,6 +96,7 @@ static int PinOpen(void){
return pin_fd;
}
#endif
/**
* @description: Read sensor device
@ -104,21 +106,25 @@ static int PinOpen(void){
*/
static int SensorDeviceRead(struct SensorDevice *sdev, size_t len)
{
#ifdef ADD_XIZI_FETURES
int pin_fd=PinOpen();
struct PinStat pin_dir;
pin_dir.pin = SENSOR_DEVICE_QS_FX_PIN_NUMBER;
pin_dir.val = GPIO_HIGH;
if (PrivWrite(pin_fd,&pin_dir,0) < 0) // pull-up pin to configure as tx mode
return -1;
#endif
PrivTaskDelay(20);
if (PrivWrite(sdev->fd, instructions, sizeof(instructions)) < 0)
return -1;
PrivTaskDelay(20);
#ifdef ADD_XIZI_FETURES
pin_dir.val = GPIO_LOW;
if (PrivWrite(pin_fd,&pin_dir,0) < 0) // pull-down pin to configure as rx mode
return -1;
#endif
if (PrivRead(sdev->fd, sdev->buffer, len) < 0)
return -1;

11
APP_Framework/Framework/sensor/windspeed/qs-fs/qs-fs.c
View File

@ -68,7 +68,7 @@ static int SensorDeviceOpen(struct SensorDevice *sdev)
return result;
}
#ifdef ADD_XIZI_FETURES
static int PinOpen(void){
int pin_fd = PrivOpen(SENSOR_DEVICE_QS_FS_PIN_DEV, O_RDWR);
if (pin_fd < 0) {
@ -96,6 +96,8 @@ static int PinOpen(void){
return pin_fd;
}
#endif
/**
* @description: Read sensor device
* @param sdev - sensor device pointer
@ -104,6 +106,7 @@ static int PinOpen(void){
*/
static int SensorDeviceRead(struct SensorDevice *sdev, size_t len)
{
#ifdef ADD_XIZI_FETURES
int pin_fd=PinOpen();
struct PinStat pin_dir;
pin_dir.pin = SENSOR_DEVICE_QS_FS_PIN_NUMBER;
@ -111,15 +114,18 @@ static int SensorDeviceRead(struct SensorDevice *sdev, size_t len)
pin_dir.val = GPIO_HIGH;
if (PrivWrite(pin_fd,&pin_dir,0) < 0) // pull-up pin to configure as tx mode
return -1;
#endif
PrivTaskDelay(20);
if (PrivWrite(sdev->fd, instructions, sizeof(instructions)) < 0)
return -1;
PrivTaskDelay(20);
#ifdef ADD_XIZI_FETURES
pin_dir.val = GPIO_LOW;
if (PrivWrite(pin_fd,&pin_dir,0) < 0) // pull-down pin to configure as rx mode
return -1;
#endif
if (PrivRead(sdev->fd, sdev->buffer, len) < 0)
return -1;
@ -128,6 +134,7 @@ static int SensorDeviceRead(struct SensorDevice *sdev, size_t len)
return 0;
}
static struct SensorDone done =
{
SensorDeviceOpen,

3
APP_Framework/Framework/transform_layer/xizi/transform.c
View File

@ -172,6 +172,9 @@ int PrivIoctl(int fd, int cmd, void *args)
case WDT_TYPE:
case CAMERA_TYPE:
case KPU_TYPE:
case TIME_TYPE:
case FLASH_TYPE:
case CAN_TYPE:
ret = ioctl(fd, cmd, ioctl_cfg->args);
break;
default:

22
APP_Framework/Framework/transform_layer/xizi/transform.h
View File

@ -151,7 +151,10 @@ enum IoctlDriverType
WDT_TYPE,
RTC_TYPE,
CAMERA_TYPE,
CAN_TYPE,
KPU_TYPE,
FLASH_TYPE,
TIME_TYPE,
DEFAULT_TYPE,
};
@ -252,6 +255,25 @@ enum TCP_OPTION {
RECV_DATA,
};
struct CanDriverConfigure
{
uint8 tsjw;
uint8 tbs2 ;
uint8 tbs1;
uint8 mode;
uint16 brp;
};
struct CanSendConfigure
{
uint32 stdid;
uint32 exdid;
uint8 ide;
uint8 rtr;
uint8 data_lenth;
uint8 *data;
};
typedef struct
{
uint8_t *buffer;

60
Ubiquitous/XiZi_IIoT/arch/arm/cortex-m4/hc32f4a0/interrupt_vector.S
View File

@ -77,36 +77,36 @@ InterruptVectors:
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IRQ016_Handler
.long IRQ017_Handler
.long IRQ018_Handler
.long IRQ019_Handler
.long IRQ020_Handler
.long IRQ021_Handler
.long IRQ022_Handler
.long IRQ023_Handler
.long IRQ024_Handler
.long IRQ025_Handler
.long IRQ026_Handler
.long IRQ027_Handler
.long IRQ028_Handler
.long IRQ029_Handler
.long IRQ030_Handler
.long IRQ031_Handler
.long IRQ032_Handler
.long IRQ033_Handler
.long IRQ034_Handler
.long IRQ035_Handler
.long IRQ036_Handler
.long IRQ037_Handler
.long IRQ038_Handler
.long IRQ039_Handler
.long IRQ040_Handler
.long IRQ041_Handler
.long IRQ042_Handler
.long IRQ043_Handler
.long IRQ044_Handler
.long IRQ045_Handler
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IsrEntry
.long IRQ046_Handler
.long IRQ047_Handler
.long IRQ048_Handler

2
Ubiquitous/XiZi_IIoT/board/edu-riscv64/board.c
View File

@ -91,7 +91,7 @@ int MountUsb(void) {
}
#endif
#if defined(FS_VFS) && defined(MOUNT_SDCARD)
#if defined(MOUNT_SDCARD)
#include <iot-vfs.h>
#include <sd_spi.h>
extern SpiSdDeviceType SpiSdInit(struct Bus *bus, const char *dev_name,

4
Ubiquitous/XiZi_IIoT/board/edu-riscv64/third_party_driver/Kconfig
View File

@ -17,11 +17,11 @@ menuconfig BSP_USING_SPI
endif
menuconfig BSP_USING_SOFT_SPI
bool "Using SOFT_SPI device"
bool "Using TFcard device"
default n
select BSP_USING_SPI
select MOUNT_SDCARD
select FS_VFS
select RESOURCES_SPI_SD
if BSP_USING_SOFT_SPI
source "$BSP_DIR/third_party_driver/soft_spi/Kconfig"
endif

15
Ubiquitous/XiZi_IIoT/board/hc32f4a0/board.c
View File

@ -70,9 +70,16 @@ Modification:
#include <connect_wdt.h>
#endif
#ifdef BSP_USING_TIMER
#include <connect_hwtimer.h>
#endif
#ifdef BSP_USING_CAN
#include <connect_can.h>
#endif
extern void entry(void);
extern int HwUsartInit();
extern int HwWdtInit();
/* Peripheral register WE/WP selection */
#define LL_PERIPH_SEL (LL_PERIPH_GPIO | LL_PERIPH_FCG | LL_PERIPH_PWC_CLK_RMU | \
@ -196,6 +203,12 @@ struct InitSequenceDesc _board_init[] =
#endif
#ifdef BSP_USING_WDT
{ "wdt", HwWdtInit },
#endif
#ifdef BSP_USING_TIMER
{ "tmr", HwTimerInit },
#endif
#ifdef BSP_USING_CAN
{ "can", HwCanInit },
#endif
{ " NONE ", NONE },
};

7
Ubiquitous/XiZi_IIoT/board/hc32f4a0/link.lds
View File

@ -87,6 +87,13 @@ SECTIONS
_shell_command_end = .;
. = ALIGN(4);
PROVIDE(__ctors_start__ = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
. = ALIGN(4);
__isrtbl_idx_start = .;
KEEP(*(.isrtbl.idx))
__isrtbl_start = .;

16
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/Kconfig
View File

@ -86,3 +86,19 @@ menuconfig BSP_USING_WDT
if BSP_USING_WDT
source "$BSP_DIR/third_party_driver/watchdog/Kconfig"
endif
menuconfig BSP_USING_TIMER
bool "Using TIMER device"
default n
select RESOURCES_TIMER
if BSP_USING_TIMER
source "$BSP_DIR/third_party_driver/timer/Kconfig"
endif
menuconfig BSP_USING_CAN
bool "Using CAN device"
default n
select RESOURCES_CAN
if BSP_USING_CAN
source "$BSP_DIR/third_party_driver/can/Kconfig"
endif

8
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/Makefile
View File

@ -44,4 +44,12 @@ ifeq ($(CONFIG_BSP_USING_WDT),y)
SRC_DIR += watchdog
endif
ifeq ($(CONFIG_BSP_USING_TIMER),y)
SRC_DIR += timer
endif
ifeq ($(CONFIG_BSP_USING_CAN),y)
SRC_DIR += can
endif
include $(KERNEL_ROOT)/compiler.mk

15
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/can/Kconfig Normal file
View File

@ -0,0 +1,15 @@
config CAN_BUS_NAME_2
string "can bus name"
default "can2"
config CAN_DRIVER_NAME_2
string "can driver name"
default "can2_drv"
config CAN_2_DEVICE_NAME_1
string "can bus 1 device 1 name"
default "can2_dev1"
config CAN_USING_INTERRUPT
bool "can interrupt open"
default n

4
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/can/Makefile Normal file
View File

@ -0,0 +1,4 @@
SRC_FILES := connect_can.c
include $(KERNEL_ROOT)/compiler.mk

297
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/can/connect_can.c Normal file
View File

@ -0,0 +1,297 @@
/*
* Copyright (c) Guangzhou Xingyi Electronic Technology Co., Ltd
*
* Change Logs:
* Date Author Notes
* 2014-7-4 alientek first version
*/
/**
* @file connect_can.c
* @brief support hc32f4a0 can function and register to bus framework
* @version 1.0
* @author AIIT XUOS Lab
* @date 2023-02-20
*/
/*************************************************
File name: connect_can.c
Description: support can configure and spi bus register function for hc32f4a0
Others: connect_can.c for references
*************************************************/
#include "connect_can.h"
#define CAN_X (CM_CAN2)
#define CAN_TX_PORT (GPIO_PORT_D)
#define CAN_TX_PIN (GPIO_PIN_07)
#define CAN_RX_PORT (GPIO_PORT_D)
#define CAN_RX_PIN (GPIO_PIN_06)
#define CAN_TX_PIN_FUNC (GPIO_FUNC_62)
#define CAN_RX_PIN_FUNC (GPIO_FUNC_63)
#define INTSEL_REG ((uint32_t)(&CM_INTC->SEL0))
#define CANX_IRQ_SRC INT_SRC_CAN2_HOST
#define CANX_IRQ_NUM 17
#define IRQ_NUM_OFFSET 16
#define CAN_AF1_ID (0x123UL)
#define CAN_AF1_ID_MSK (0xFFFUL)
#define CAN_AF1_MSK_TYPE CAN_ID_STD
#define CAN_AF2_ID (0x005UL)
#define CAN_AF2_ID_MSK (0x00FUL)
#define CAN_AF2_MSK_TYPE CAN_ID_STD
#define CAN_AF3_ID (0x23UL)
#define CAN_AF3_ID_MSK (0xFFUL)
#define CAN_AF3_MSK_TYPE CAN_ID_STD
#ifdef CAN_USING_INTERRUPT
void CanIrqHandler(int vector, void *param)
{
stc_can_error_info_t err_info;
uint32_t status = CAN_GetStatusValue(CAN_X);
uint32_t error = CAN_GetErrorInfo(CAN_X,&err_info);
KPrintf("Irq entered\n");
CAN_ClearStatus(CAN_X, status);
}
static void CanIrqConfig(void)
{
// register IRQ src in IRQn
__IO uint32_t *INTC_SELx = (__IO uint32_t *)(INTSEL_REG+ 4U * (uint32_t)(CANX_IRQ_NUM));
WRITE_REG32(*INTC_SELx, CANX_IRQ_SRC);
isrManager.done->registerIrq(CANX_IRQ_NUM+IRQ_NUM_OFFSET,CanIrqHandler,NULL);
isrManager.done->enableIrq(CANX_IRQ_NUM);
}
#endif
static void CanInit(struct CanDriverConfigure *can_drv_config)
{
stc_can_init_t stcInit;
stc_can_filter_config_t astcAFCfg[] = { \
{CAN_AF1_ID, CAN_AF1_ID_MSK, CAN_AF1_MSK_TYPE}, \
{CAN_AF2_ID, CAN_AF2_ID_MSK, CAN_AF2_MSK_TYPE}, \
{CAN_AF3_ID, CAN_AF3_ID_MSK, CAN_AF3_MSK_TYPE}, \
};
CLK_SetCANClockSrc(CLK_CAN2,CLK_CANCLK_SYSCLK_DIV4);
/* Set the function of CAN pins. */
GPIO_SetFunc(CAN_TX_PORT, CAN_TX_PIN, CAN_TX_PIN_FUNC);
GPIO_SetFunc(CAN_RX_PORT, CAN_RX_PIN, CAN_RX_PIN_FUNC);
/* Initializes CAN. */
(void)CAN_StructInit(&stcInit);
stcInit.pstcFilter = astcAFCfg;
stcInit.u16FilterSelect = (CAN_FILTER1 | CAN_FILTER2 | CAN_FILTER3);
// Driver's config
stcInit.stcBitCfg.u32SJW = can_drv_config->tsjw;
stcInit.stcBitCfg.u32Prescaler = can_drv_config->brp;
stcInit.stcBitCfg.u32TimeSeg1 = can_drv_config->tbs1;
stcInit.stcBitCfg.u32TimeSeg2 = can_drv_config->tbs2;
stcInit.u8WorkMode = can_drv_config->mode;
#ifdef CAN_USING_FD
stcInit.stcFDCfg.u8TDCSSP = 16U;
stcInit.stcFDCfg.u8CANFDMode = CAN_FD_MODE_ISO_11898;
stcInit.stcFDCfg.stcFBT.u32SEG1 = 16U;
stcInit.stcFDCfg.stcFBT.u32SEG2 = 4U;
stcInit.stcFDCfg.stcFBT.u32SJW = 4U;
stcInit.stcFDCfg.stcFBT.u32Prescaler = 1U;
(void)CAN_FD_Init(APP_CAN_UNIT, &stcInit);
#else
FCG_Fcg1PeriphClockCmd(PWC_FCG1_CAN2, ENABLE);
(void)CAN_Init(CAN_X, &stcInit);
#endif
CAN_ClearStatus(CAN_X, 0xFFFFFFFFU);
#ifdef CAN_USING_INTERRUPT
/* Configures the interrupts if needed. */
CAN_IntCmd(CAN_X, CAN_INT_RX, ENABLE);
CanIrqConfig();
#endif
}
static uint32 CanConfig(void *can_drv_config)
{
x_err_t ret = EOK;
return ret;
}
static uint32 CanDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
{
x_err_t ret = EOK;
NULL_PARAM_CHECK(drv);
NULL_PARAM_CHECK(configure_info);
struct CanDriverConfigure *can_drv_config;
switch (configure_info->configure_cmd)
{
case OPE_INT: // can basic init
can_drv_config = (struct CanDriverConfigure *)configure_info->private_data;
CanInit(can_drv_config);
break;
case OPE_CFG:
CanConfig(configure_info->private_data);
break;
default:
break;
}
return ret;
}
static uint32 CanWriteData(void * dev , struct BusBlockWriteParam *write_param)
{
x_err_t ret=EOK;
NULL_PARAM_CHECK(dev);
NULL_PARAM_CHECK(write_param);
struct CanSendConfigure *p_can_config = (struct CanSendConfigure*)write_param->buffer;
stc_can_tx_frame_t can_frame_obj;
memset(&can_frame_obj,0,sizeof(stc_can_tx_frame_t));
// configure CAN's flag bit
can_frame_obj.IDE = p_can_config->ide;
if(1==p_can_config->ide){
can_frame_obj.u32ID = p_can_config->exdid;
}else{
can_frame_obj.u32ID = p_can_config->stdid;
}
can_frame_obj.RTR = p_can_config->rtr;
memcpy(can_frame_obj.au8Data,p_can_config->data,p_can_config->data_lenth);
can_frame_obj.DLC = p_can_config->data_lenth;
//put frame_buffer in message queue
if(can_frame_obj.DLC){
ret = CAN_FillTxFrame(CAN_X,CAN_TX_BUF_STB,&can_frame_obj);
if(EOK != ret){
KPrintf("CAN fill tx frame failed(CODE:%d)!\n",ret);
return ERROR;
}
CAN_StartTx(CAN_X,CAN_TX_REQ_STB_ONE);
}
return ret;
}
static uint32 CanReadData(void *dev , struct BusBlockReadParam *databuf)
{
NULL_PARAM_CHECK(dev);
NULL_PARAM_CHECK(databuf);
x_err_t ret=EOK;
stc_can_rx_frame_t frame_received;
struct CanSendConfigure *p_can_config = (struct CanSendConfigure*)databuf->buffer;
memset(&frame_received,0,sizeof(stc_can_rx_frame_t));
ret = CAN_GetRxFrame(CAN_X, &frame_received);
if(EOK != ret){
// KPrintf("CAN recv frame failed(CODE:%d)!\n",ret);
p_can_config->data_lenth = 0;
return ERROR;
}
//put message in frame_buffer
p_can_config->ide = frame_received.IDE;
p_can_config->rtr = frame_received.RTR;
if(p_can_config->ide==1){
p_can_config->exdid = frame_received.u32ID ;
}else{
p_can_config->stdid = frame_received.u32ID;
p_can_config->exdid = frame_received.u32ID ;
}
p_can_config->data_lenth = frame_received.DLC;
for(int i=0;i<p_can_config->data_lenth;i++){
p_can_config->data[i] = frame_received.au8Data[i];
}
return frame_received.DLC;
}
static struct CanDevDone can_dev_done =
{
.open = NONE,
.close = NONE,
.write = CanWriteData,
.read = CanReadData
};
static int BoardCanBusInit(struct CanBus *can_bus, struct CanDriver *can_driver)
{
x_err_t ret = EOK;
/*Init the can bus */
ret = CanBusInit(can_bus, CAN_BUS_NAME_2);
if (EOK != ret) {
KPrintf("Board_can_init canBusInit error %d\n", ret);
return ERROR;
}
/*Init the can driver*/
ret = CanDriverInit(can_driver, CAN_DRIVER_NAME_2);
if (EOK != ret) {
KPrintf("Board_can_init canDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the can driver to the can bus*/
ret = CanDriverAttachToBus(CAN_DRIVER_NAME_2, CAN_BUS_NAME_2);
if (EOK != ret) {
KPrintf("Board_can_init CanDriverAttachToBus error %d\n", ret);
return ERROR;
}
return ret;
}
/* Attach the can device to the can bus*/
static int BoardCanDevBend(void)
{
x_err_t ret = EOK;
static struct CanHardwareDevice can_device0;
memset(&can_device0, 0, sizeof(struct CanHardwareDevice));
can_device0.dev_done = &can_dev_done;
ret = CanDeviceRegister(&can_device0, NONE, CAN_2_DEVICE_NAME_1);
if (EOK != ret) {
KPrintf("board_can_init CanDeviceInit device %s error %d\n", CAN_2_DEVICE_NAME_1, ret);
return ERROR;
}
ret = CanDeviceAttachToBus(CAN_2_DEVICE_NAME_1, CAN_BUS_NAME_2);
if (EOK != ret) {
KPrintf("board_can_init CanDeviceAttachToBus device %s error %d\n", CAN_2_DEVICE_NAME_1, ret);
return ERROR;
}
return ret;
}
int HwCanInit(void)
{
x_err_t ret = EOK;
static struct CanBus can_bus;
memset(&can_bus, 0, sizeof(struct CanBus));
static struct CanDriver can_driver;
memset(&can_driver, 0, sizeof(struct CanDriver));
can_driver.configure = &(CanDrvConfigure);
ret = BoardCanBusInit(&can_bus, &can_driver);
if (EOK != ret) {
KPrintf(" can_bus_init %s error ret %u\n", CAN_BUS_NAME_2, ret);
return ERROR;
}
ret = BoardCanDevBend();
if (EOK != ret) {
KPrintf("board_can_init error ret %u\n", ret);
return ERROR;
}
return EOK;
}

8
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/common/hc32_ll_driver/src/Makefile
View File

@ -20,6 +20,10 @@ ifeq ($(CONFIG_BSP_USING_SPI),y)
SRC_FILES += hc32_ll_spi.c
endif
ifeq ($(CONFIG_BSP_USING_QSPI_FLASH),y)
SRC_FILES += hc32_ll_qspi.c
endif
ifeq ($(CONFIG_BSP_USING_I2C),y)
SRC_FILES += hc32_ll_i2c.c
endif
@ -40,4 +44,8 @@ ifeq ($(CONFIG_BSP_USING_WDT),y)
SRC_FILES += hc32_ll_wdt.c
endif
ifeq ($(CONFIG_BSP_USING_CAN),y)
SRC_FILES += hc32_ll_can.c
endif
include $(KERNEL_ROOT)/compiler.mk

3
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/gpio/connect_gpio.c
View File

@ -35,7 +35,6 @@ Modification:
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
#define IRQ_INT(callback)
#define INTSEL_REG (uint32_t)(&CM_INTC->SEL0)
#ifndef HC32_PIN_CONFIG
#define HC32_PIN_CONFIG(pin, callback, config) \
@ -50,6 +49,7 @@ Modification:
#define __HC32_PIN_DEFAULT {-1, 0, 0}
#define MAX_PIN_INDEX 15
#define INT_VECTOR_OFFSET 16
#define INTSEL_REG (uint32_t)(&CM_INTC->SEL0)
struct PinIndex
{
@ -564,7 +564,6 @@ static int32 GpioIrqEnable(x_base pin)
isrManager.done->enableIrq(GpioPinIndex(index->pin));
CriticalAreaUnLock(level);
KPrintf("port%d,pin%04x has enable\n",index->port, index->pin);
return EOK;
}

40
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/include/connect_can.h Normal file
View File

@ -0,0 +1,40 @@
/*
* Copyright (c) 2021 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_can.h
* @brief define hc32f4a0-board can function and struct
* @version 2.0
* @author AIIT XUOS Lab
* @date 2023-02-21
*/
#ifndef CONNECT_CAN_H
#define CONNECT_CAN_H
#include <device.h>
#include <hc32_ll_can.h>
#include <hc32_ll_clk.h>
#include <hc32_ll_gpio.h>
#include <hardware_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
int HwCanInit(void);
#ifdef __cplusplus
}
#endif
#endif

40
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/include/connect_flash.h Normal file
View File

@ -0,0 +1,40 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_flash.h
* @brief define hc32f4a0-board qspi-flash function and struct
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-10-17
*/
#ifndef CONNECT_FLASH_H
#define CONNECT_FLASH_H
#include <device.h>
#include <hardware_irq.h>
#include <flash_spi.h>
#include <hc32_ll_qspi.h>
#include <hc32_ll_gpio.h>
#ifdef __cplusplus
extern "C" {
#endif
int FlashW25qxxSpiDeviceInit(void);
#ifdef __cplusplus
}
#endif
#endif

40
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/include/connect_hwtimer.h Normal file
View File

@ -0,0 +1,40 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_hwtimer.h
* @brief define hc32f4a0-board hwtimer function and struct
* @version 2.0
* @author AIIT XUOS Lab
* @date 2023-02-16
*/
#ifndef CONNECT_HWTIMER_H
#define CONNECT_HWTIMER_H
#include <device.h>
#include <hc32f4a0.h>
#include <hardware_irq.h>
#include <hc32_ll_tmr0.h>
#include <hc32_ll_gpio.h>
#ifdef __cplusplus
extern "C" {
#endif
int HwTimerInit(void);
#ifdef __cplusplus
}
#endif
#endif

19
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/spi/Kconfig
View File

@ -39,4 +39,23 @@ if BSP_USING_SPI
string "spi bus 6 driver name"
default "spi6_drv"
endif
config BSP_USING_QSPI_FLASH
bool "Using qspi and flash"
default n
if BSP_USING_QSPI_FLASH
config QSPI_BUS_NAME
string "qspi bus name"
default "qspi"
config QSPI_DEVICE_NAME_0
string "qspi bus device 0 name"
default "qspi_dev0"
config QSPI_DRV_NAME
string "qspi bus driver name"
default "qspi_drv"
config QSPI_FLASH_DEV_NAME
string "flash dev name"
default "qspi_W25Q128"
endif
endif

4
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/spi/Makefile
View File

@ -5,4 +5,8 @@ ifeq ($(CONFIG_RESOURCES_SPI_LORA),y)
SRC_FILES += connect_lora_spi.c
endif
ifeq ($(CONFIG_BSP_USING_QSPI_FLASH),y)
SRC_FILES += connect_flash.c
endif
include $(KERNEL_ROOT)/compiler.mk

260
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/spi/connect_flash.c Normal file
View File

@ -0,0 +1,260 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_flash.c
* @brief support hc32f4a0-board qspi-flash function and register to bus framework
* @version 2.0
* @author AIIT XUOS Lab
* @date 2023-02-16
*/
#include <connect_flash.h>
#define QSPI_DEVICE_SLAVE_ID_0 (0)
#define QSPI_UNIT (CM_QSPI)
#define QSPI_CS_PORT (GPIO_PORT_C)
#define QSPI_SCK_PORT (GPIO_PORT_C)
#define QSPI_IO0_PORT (GPIO_PORT_D)
#define QSPI_IO1_PORT (GPIO_PORT_D)
#define QSPI_IO2_PORT (GPIO_PORT_D)
#define QSPI_IO3_PORT (GPIO_PORT_D)
#define QSPI_CS_PIN (GPIO_PIN_07)
#define QSPI_SCK_PIN (GPIO_PIN_06)
#define QSPI_IO0_PIN (GPIO_PIN_08)
#define QSPI_IO1_PIN (GPIO_PIN_09)
#define QSPI_IO2_PIN (GPIO_PIN_10)
#define QSPI_IO3_PIN (GPIO_PIN_11)
#define QSPI_PIN_FUNC (GPIO_FUNC_18)
static uint32 QSpiSdkInit(struct SpiDriver *spi_drv)
{
stc_qspi_init_t stcInit;
FCG_Fcg1PeriphClockCmd(PWC_FCG1_QSPI, ENABLE);
(void)QSPI_StructInit(&stcInit);
stcInit.u32ClockDiv = QSPI_CLK_DIV3;
stcInit.u32SpiMode = QSPI_SPI_MD0;
stcInit.u32ReadMode = QSPI_RD_MD_STD_RD;
stcInit.u32DummyCycle = QSPI_DUMMY_CYCLE8;
stcInit.u32AddrWidth = QSPI_ADDR_WIDTH_24BIT;
return QSPI_Init(&stcInit);
}
static void QspiPinConfig(void)
{
stc_gpio_init_t stcGpioInit;
(void)GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinState = PIN_STAT_RST;
stcGpioInit.u16PinDir = PIN_DIR_OUT;
(void)GPIO_Init(QSPI_CS_PORT, QSPI_CS_PIN|QSPI_SCK_PIN, &stcGpioInit);
stcGpioInit.u16PinState = PIN_STAT_SET;
(void)GPIO_Init(QSPI_IO0_PORT, QSPI_IO1_PIN|QSPI_IO2_PIN|QSPI_IO3_PIN, &stcGpioInit);
stcGpioInit.u16PinDir = PIN_DIR_IN;
(void)GPIO_Init(QSPI_IO0_PORT, QSPI_IO0_PIN, &stcGpioInit);
GPIO_ResetPins(QSPI_CS_PORT, QSPI_CS_PIN);
GPIO_SetPins(QSPI_IO0_PORT, QSPI_IO2_PIN|QSPI_IO3_PIN);
GPIO_SetFunc(QSPI_CS_PORT, QSPI_CS_PIN, QSPI_PIN_FUNC);
GPIO_SetFunc(QSPI_SCK_PORT, QSPI_SCK_PIN, QSPI_PIN_FUNC);
GPIO_SetFunc(QSPI_IO0_PORT, QSPI_IO0_PIN, QSPI_PIN_FUNC);
GPIO_SetFunc(QSPI_IO1_PORT, QSPI_IO1_PIN, QSPI_PIN_FUNC);
GPIO_SetFunc(QSPI_IO2_PORT, QSPI_IO2_PIN, QSPI_PIN_FUNC);
GPIO_SetFunc(QSPI_IO3_PORT, QSPI_IO3_PIN, QSPI_PIN_FUNC);
}
static uint32 QSpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg)
{
SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_dev->haldev.private_data);
uint8 cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;
uint8 cs_gpio_port = dev_param->spi_slave_param->spi_cs_gpio_port;
CM_SPI_TypeDef *spi = spi_dev->haldev.owner_bus->private_data;
x_err_t ret = EOK;
if (spi_datacfg->spi_chip_select) {
// GPIO_ResetPins(cs_gpio_port, cs_gpio_pin);
QSPI_EnterDirectCommMode();
}
if(spi_datacfg->length > 0U && spi_datacfg->tx_buff!=NULL){
for(int i=0;i<spi_datacfg->length;i++){
QSPI_WriteDirectCommValue(spi_datacfg->tx_buff[i]);
}
}
if (spi_datacfg->spi_cs_release) {
// GPIO_SetPins(cs_gpio_port, cs_gpio_pin);
QSPI_ExitDirectCommMode();
}
return ret;
}
static uint32 QSpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg)
{
SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_dev->haldev.private_data);
uint8 cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;
uint8 cs_gpio_port = dev_param->spi_slave_param->spi_cs_gpio_port;
CM_SPI_TypeDef *spi = spi_dev->haldev.owner_bus->private_data;
x_err_t ret = EOK;
uint8_t *read_buffer = spi_datacfg->rx_buff;
if (spi_datacfg->spi_chip_select) {
// GPIO_ResetPins(cs_gpio_port, cs_gpio_pin);
QSPI_EnterDirectCommMode();
}
if(spi_datacfg->length > 0U && spi_datacfg->rx_buff!=NULL){
for(int i=0;i<spi_datacfg->length;i++){
read_buffer[i] = (uint8_t)QSPI_ReadDirectCommValue();
}
}
if (spi_datacfg->spi_cs_release) {
// GPIO_SetPins(cs_gpio_port, cs_gpio_pin);
QSPI_ExitDirectCommMode();
}
return ret;
}
static uint32 QSpiDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
{
NULL_PARAM_CHECK(drv);
NULL_PARAM_CHECK(configure_info);
x_err_t ret = EOK;
struct SpiDriver *spi_drv = (struct SpiDriver *)drv;
struct SpiMasterParam *spi_param;
switch (configure_info->configure_cmd)
{
case OPE_INT:
QSpiSdkInit(spi_drv);
QspiPinConfig();
break;
case OPE_CFG:
spi_param = (struct SpiMasterParam *)configure_info->private_data;
break;
default:
break;
}
return ret;
}
/*manage the qspi device operations*/
static const struct SpiDevDone qspi_dev_done =
{
.dev_open = NONE,
.dev_close = NONE,
.dev_write = QSpiWriteData,
.dev_read = QSpiReadData,
};
static int BoardQSpiDevBend(void)
{
x_err_t ret = EOK;
static struct SpiHardwareDevice qspi_device0;
memset(&qspi_device0, 0, sizeof(struct SpiHardwareDevice));
static struct SpiSlaveParam qspi_slaveparam0;
memset(&qspi_slaveparam0, 0, sizeof(struct SpiSlaveParam));
qspi_slaveparam0.spi_slave_id = QSPI_DEVICE_SLAVE_ID_0;
qspi_slaveparam0.spi_cs_gpio_pin = QSPI_CS_PIN;
qspi_slaveparam0.spi_cs_gpio_port = QSPI_CS_PORT;
qspi_device0.spi_param.spi_slave_param = &qspi_slaveparam0;
qspi_device0.spi_dev_done = &(qspi_dev_done);
ret = SpiDeviceRegister(&qspi_device0, (void *)(&qspi_device0.spi_param), QSPI_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("BoardSpiDevBend SpiDeviceRegister device %s error %d\n", QSPI_DEVICE_NAME_0, ret);
return ERROR;
}
ret = SpiDeviceAttachToBus(QSPI_DEVICE_NAME_0, QSPI_BUS_NAME);
if (EOK != ret) {
KPrintf("BoardSpiDevBend SpiDeviceAttachToBus device %s error %d\n", QSPI_DEVICE_NAME_0, ret);
return ERROR;
}
return ret;
}
static int BoardSpiBusInit(struct SpiBus *spi_bus, struct SpiDriver *spi_driver, const char *bus_name, const char *drv_name)
{
x_err_t ret = EOK;
/*Init the spi bus */
ret = SpiBusInit(spi_bus, bus_name);
if (EOK != ret) {
KPrintf("Board_Spi_init SpiBusInit error %d\n", ret);
return ERROR;
}
/*Init the spi driver*/
ret = SpiDriverInit(spi_driver, drv_name);
if (EOK != ret) {
KPrintf("Board_Spi_init SpiDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the spi driver to the spi bus*/
ret = SpiDriverAttachToBus(drv_name, bus_name);
if (EOK != ret) {
KPrintf("Board_Spi_init SpiDriverAttachToBus error %d\n", ret);
return ERROR;
}
return ret;
}
int HwQSpiInit(void)
{
x_err_t ret = EOK;
static struct SpiBus qspi_bus;
memset(&qspi_bus, 0, sizeof(struct SpiBus));
static struct SpiDriver qspi_driver;
memset(&qspi_driver, 0, sizeof(struct SpiDriver));
qspi_bus.private_data = QSPI_UNIT;
qspi_driver.configure = QSpiDrvConfigure;
ret = BoardSpiBusInit(&qspi_bus, &qspi_driver, QSPI_BUS_NAME, QSPI_DRV_NAME);
if (EOK != ret) {
KPrintf("BoardSpiBusInit error ret %u\n", ret);
return ERROR;
}
ret = BoardQSpiDevBend();
if (EOK != ret) {
KPrintf("BoardSpiDevBend error ret %u\n", ret);
return ERROR;
}
return ret;
}
int FlashW25qxxSpiDeviceInit(void)
{
HwQSpiInit();
QSpiSdkInit(NULL);
QspiPinConfig();
if (NONE == SpiFlashInit(QSPI_BUS_NAME, QSPI_DEVICE_NAME_0, QSPI_DRV_NAME, QSPI_FLASH_DEV_NAME)) {
return ERROR;
}
return EOK;
}

8
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/spi/connect_spi.c
View File

@ -465,11 +465,6 @@ int HwSpiInit(void)
return ERROR;
}
ret = BoardSpiDevBend();
if (EOK != ret) {
KPrintf("BoardSpiDevBend error ret %u\n", ret);
return ERROR;
}
#endif
#ifdef BSP_USING_SPI6
@ -488,12 +483,13 @@ int HwSpiInit(void)
return ERROR;
}
#endif
ret = BoardSpiDevBend();
if (EOK != ret) {
KPrintf("BoardSpiDevBend error ret %u\n", ret);
return ERROR;
}
#endif
return ret;
}

16
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/timer/Kconfig Normal file
View File

@ -0,0 +1,16 @@
menuconfig BSP_USING_TIMER_0
bool "Using timer 0"
default n
select RESOURCES_HWTIMER
if BSP_USING_TIMER_0
config HWTIMER_BUS_NAME_0
string "timer 0 bus 0 name"
default "timer0"
config HWTIMER_0_DEVICE_NAME_0
string "timer 0 bus 0 device 0 name"
default "timer0_dev0"
config HWTIMER_DRIVER_NAME_0
string "timer 0 bus 0 driver name"
default "timer0_drv"
endif

3
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/timer/Makefile Normal file
View File

@ -0,0 +1,3 @@
SRC_FILES := connect_hwtimer.c
include $(KERNEL_ROOT)/compiler.mk

189
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/timer/connect_hwtimer.c Normal file
View File

@ -0,0 +1,189 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_hwtimer.c
* @brief support aiit-riscv64-board hwtimer function and register to bus framework
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
#include <connect_hwtimer.h>
#define TMR0_CMP_VAL 1000
#define TMR0x ((CM_TMR0_TypeDef *)CM_TMR0_1_BASE)
#define TMR0_CH_x (TMR0_CH_A)
#define INTSEL_REG ((uint32_t)(&CM_INTC->SEL0))
#define TIMER0_IRQn (18)
void (*callback_function)(void *) ;
static void Timer0Callback(int vector, void *param)
{
TMR0_SetCountValue(TMR0x, TMR0_CH_x, 0);
if (callback_function) {
callback_function(param);
}
}
static uint32 HwtimerOpen(void *dev)
{
struct HwtimerHardwareDevice *hwtimer_dev = dev;
stc_tmr0_init_t stcTmr0Init;
/* Enable timer0 peripheral clock */
FCG_Fcg2PeriphClockCmd(PWC_FCG2_TMR0_1, ENABLE);
/* TIMER0 basetimer function initialize */
(void)TMR0_StructInit(&stcTmr0Init);
stcTmr0Init.u32ClockDiv = TMR0_CLK_DIV128; /* Config clock division */
stcTmr0Init.u32ClockSrc = TMR0_CLK_SRC_INTERN_CLK; /* Chose clock source */
stcTmr0Init.u32Func = TMR0_FUNC_CMP; /* Timer0 compare mode */
stcTmr0Init.u16CompareValue = TMR0_CMP_VAL; /* Set compare register data */
(void)TMR0_Init(TMR0x, TMR0_CH_x, &stcTmr0Init);
// DelayKTask(1);
// /* Set internal hardware capture source */
// TMR0_SetTriggerSrc(EVT_PORT_EIRQ0);
// DelayKTask(1);
return EOK;
}
static uint32 HwtimerClose(void *dev)
{
/* Timer0 interrupt function Disable */
TMR0_IntCmd(TMR0x, TMR0_INT_CMP_A, DISABLE);
return EOK;
}
/*manage the hwtimer device operations*/
static const struct HwtimerDevDone dev_done =
{
.open = HwtimerOpen,
.close = HwtimerClose,
.write = NONE,
.read = NONE,
};
static uint32 HwtimerDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
{
NULL_PARAM_CHECK(drv);
NULL_PARAM_CHECK(configure_info);
x_err_t ret = EOK;
__IO uint32_t *INTC_SELx;
switch (configure_info->configure_cmd)
{
case OPE_INT:
INTC_SELx = (__IO uint32_t *)(INTSEL_REG+ 4U * (uint32_t)(TIMER0_IRQn));
WRITE_REG32(*INTC_SELx, EVT_SRC_TMR0_1_CMP_A);
callback_function = (void (*)(void *param))configure_info->private_data;
isrManager.done->registerIrq(TIMER0_IRQn+16,Timer0Callback,NULL);
isrManager.done->enableIrq(TIMER0_IRQn);
TMR0_IntCmd(TMR0x, TMR0_INT_CMP_A, ENABLE);
break;
case OPE_CFG:
TMR0_ClearStatus(TMR0x, TMR0_FLAG_CMP_A);
TMR0_SetCompareValue(TMR0x, TMR0_CH_x, *((int *)configure_info->private_data) );
/* Timer0 interrupt function Enable */
TMR0_SetCountValue(TMR0x, TMR0_CH_x, 0x0000);
TMR0_Start(TMR0x, TMR0_CH_x);
break;
default:
break;
}
return ret;
}
/*Init hwtimer bus*/
static int BoardHwtimerBusInit(struct HwtimerBus *hwtimer_bus, struct HwtimerDriver *hwtimer_driver)
{
x_err_t ret = EOK;
/*Init the hwtimer bus */
ret = HwtimerBusInit(hwtimer_bus, HWTIMER_BUS_NAME_0);
if (EOK != ret) {
KPrintf("board_hwtimer_init HwtimerBusInit error %d\n", ret);
return ERROR;
}
/*Init the hwtimer driver*/
hwtimer_driver->configure = &(HwtimerDrvConfigure);
ret = HwtimerDriverInit(hwtimer_driver, HWTIMER_DRIVER_NAME_0);
if (EOK != ret) {
KPrintf("board_hwtimer_init HwtimerDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the hwtimer driver to the hwtimer bus*/
ret = HwtimerDriverAttachToBus(HWTIMER_DRIVER_NAME_0, HWTIMER_BUS_NAME_0);
if (EOK != ret) {
KPrintf("board_hwtimer_init USEDriverAttachToBus error %d\n", ret);
return ERROR;
}
return ret;
}
/*Attach the hwtimer device to the hwtimer bus*/
static int BoardHwtimerDevBend(void)
{
x_err_t ret = EOK;
static struct HwtimerHardwareDevice hwtimer_device_0;
memset(&hwtimer_device_0, 0, sizeof(struct HwtimerHardwareDevice));
hwtimer_device_0.dev_done = &dev_done;
ret = HwtimerDeviceRegister(&hwtimer_device_0, NONE, HWTIMER_0_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("BoardHwtimerDevBend HwtimerDeviceRegister device %s error %d\n", HWTIMER_0_DEVICE_NAME_0, ret);
return ERROR;
}
ret = HwtimerDeviceAttachToBus(HWTIMER_0_DEVICE_NAME_0, HWTIMER_BUS_NAME_0);
if (EOK != ret) {
KPrintf("BoardHwtimerDevBend HwtimerDeviceAttachToBus device %s error %d\n", HWTIMER_0_DEVICE_NAME_0, ret);
return ERROR;
}
return ret;
}
/*K210 BOARD HWTIMER INIT*/
int HwTimerInit(void)
{
x_err_t ret = EOK;
static struct HwtimerBus hwtimer_bus;
memset(&hwtimer_bus, 0, sizeof(struct HwtimerBus));
static struct HwtimerDriver hwtimer_driver;
memset(&hwtimer_driver, 0, sizeof(struct HwtimerDriver));
ret = BoardHwtimerBusInit(&hwtimer_bus, &hwtimer_driver);
if (EOK != ret) {
KPrintf("board_hwtimer_Init error ret %u\n", ret);
return ERROR;
}
ret = BoardHwtimerDevBend();
if (EOK != ret) {
KPrintf("board_hwtimer_Init error ret %u\n", ret);
return ERROR;
}
return ret;
}

76
Ubiquitous/XiZi_IIoT/kernel/kernel_test/test_realtime.c
View File

@ -26,15 +26,23 @@ extern unsigned int usleep(unsigned int seconds);
static BusType pin;
#ifdef ARCH_ARM
#include <hardware_gpio.h>
// #include <hardware_gpio.h>
#define GPIO_C13 7
#define GPIO_C2 17
#define GPIO_C11 140
#define GPIO_D1 143
void PinIrqIsr(void *args)
void PinIrqIsr(int vector,void *args)
{
*(volatile unsigned int *)0x40020818 = 0x2000;
/* 将GPIO D1置为高电平 */
asm volatile("LDR r2, =0x40053838"); // 测试代码
asm volatile("MOV r3, #0x0002"); // 测试代码
asm volatile("STR r3, [r2]"); // 测试代码
*(volatile unsigned int *)0x4002081a = 0x2000;
/* 将GPIO D1置为低电平 */
asm volatile("LDR r2, =0x4005383A"); // 测试代码
asm volatile("MOV r3, #0x0002"); // 测试代码
asm volatile("STR r3, [r2]"); // 测试代码
}
int RealtimeIrqTest()
@ -58,23 +66,23 @@ int RealtimeIrqTest()
KPrintf("%s irq test\n",__func__);
/* config test pin 1 as output*/
testpin_1.cmd = GPIO_CONFIG_MODE;
testpin_1.pin = GPIO_C13;
testpin_1.pin = GPIO_D1;
testpin_1.mode = GPIO_CFG_OUTPUT;
ret = BusDrvConfigure(pin->owner_driver, &configure_info_1);
if (ret != EOK) {
KPrintf("config testpin_1 %d failed!\n", GPIO_C13);
KPrintf("config testpin_1 %d failed!\n", GPIO_D1);
return -ERROR;
}
/* set test pin 1 as high*/
testpin_1_stat.pin = GPIO_C13;
testpin_1_stat.pin = GPIO_D1;
testpin_1_stat.val = GPIO_LOW;
BusDevWriteData(pin->owner_haldev, &write_param_1);
/* config test pin 2 as input*/
testpin_2.cmd = GPIO_CONFIG_MODE;
testpin_2.pin = GPIO_C2;
testpin_2.pin = GPIO_C11;
testpin_2.mode = GPIO_CFG_INPUT;
ret = BusDrvConfigure(pin->owner_driver, &configure_info_2);
@ -84,9 +92,9 @@ int RealtimeIrqTest()
}
testpin_2.cmd = GPIO_IRQ_REGISTER;
testpin_2.pin = GPIO_C2;
testpin_2.pin = GPIO_C11;
testpin_2.irq_set.irq_mode = GPIO_IRQ_EDGE_BOTH;
testpin_2.irq_set.hdr = PinIrqIsr;
testpin_2.irq_set.hdr = (void(*)(void *))PinIrqIsr;
testpin_2.irq_set.args = NONE;
ret = BusDrvConfigure(pin->owner_driver, &configure_info_2);
@ -96,7 +104,7 @@ int RealtimeIrqTest()
}
testpin_2.cmd = GPIO_IRQ_ENABLE;
testpin_2.pin = GPIO_C2;
testpin_2.pin = GPIO_C11;
ret = BusDrvConfigure(pin->owner_driver, &configure_info_2);
if (ret != EOK) {
@ -191,14 +199,32 @@ void GpioSpeedTest()
#else
#define GPIO_18 18
#define GPIO_19 19
#define GPIO_34 34
#define GPIO_35 35
void PinIrqIsr(void *args)
{
*(volatile unsigned int *)0x3800100c |= 0x5;
/* 将 GPIO18 置为高电平 */
asm volatile ("lui a5, 0x38001"); // 测试代码
asm volatile ("addi a5, a5, 12"); // 测试代码
asm volatile ("lw a5, 0(a5)"); // 测试代码
asm volatile ("sext.w a4, a5"); // 测试代码
asm volatile ("lui a5, 0x38001"); // 测试代码
asm volatile ("addi a5, a5, 12"); // 测试代码
asm volatile ("ori a4, a4, 5"); // 测试代码
asm volatile ("sext.w a4, a4"); // 测试代码
asm volatile ("sw a4, 0(a5)"); // 测试代码
*(volatile unsigned int *)0x3800100c &= ~0x5;
/* 将GPIO18 置为低电平 */
asm volatile ("lui a5, 0x38001"); // 测试代码
asm volatile ("addi a5, a5, 12"); // 测试代码
asm volatile ("lw a5, 0(a5)"); // 测试代码
asm volatile ("sext.w a4, a5"); // 测试代码
asm volatile ("lui a5, 0x38001"); // 测试代码
asm volatile ("addi a5, a5, 12"); // 测试代码
asm volatile ("andi a4, a4, -6"); // 测试代码
asm volatile ("sext.w a4, a4"); // 测试代码
asm volatile ("sw a4, 0(a5)"); // 测试代码
}
int RealtimeIrqTest()
@ -221,29 +247,29 @@ int RealtimeIrqTest()
KPrintf("%s irq test\n",__func__);
/* config GPIO18 as output and set as low */
testpin_1.cmd = GPIO_CONFIG_MODE;
testpin_1.pin = GPIO_18;
testpin_1.pin = GPIO_34;
testpin_1.mode = GPIO_CFG_OUTPUT;
BusDrvConfigure(pin->owner_driver, &configure_info_1);
testpin_1_stat.pin = GPIO_18;
testpin_1_stat.pin = GPIO_34;
testpin_1_stat.val = GPIO_LOW;
BusDevWriteData(pin->owner_haldev, &write_param_1);
/* config GPIO18 as input */
testpin_2.cmd = GPIO_CONFIG_MODE;
testpin_2.pin = GPIO_19;
testpin_2.pin = GPIO_35;
testpin_2.mode = GPIO_CFG_INPUT;
BusDrvConfigure(pin->owner_driver, &configure_info_2);
testpin_2.cmd = GPIO_IRQ_REGISTER;
testpin_2.pin = GPIO_19;
testpin_2.pin = GPIO_35;
testpin_2.irq_set.irq_mode = GPIO_IRQ_EDGE_RISING;
testpin_2.irq_set.hdr = PinIrqIsr;
testpin_2.irq_set.args = NONE;
BusDrvConfigure(pin->owner_driver, &configure_info_2);
testpin_2.cmd = GPIO_IRQ_ENABLE;
testpin_2.pin = GPIO_19;
testpin_2.pin = GPIO_35;
BusDrvConfigure(pin->owner_driver, &configure_info_2);
return 0;
@ -262,16 +288,16 @@ void RealtimeTaskSwitchTest()
write_param_1.buffer = (void *)&testpin_1_stat;
testpin_1.cmd = GPIO_CONFIG_MODE;
testpin_1.pin = GPIO_18;
testpin_1.pin = GPIO_34;
testpin_1.mode = GPIO_CFG_OUTPUT;
BusDrvConfigure(pin->owner_driver, &configure_info_1);
testpin_1_stat.pin = GPIO_18;
testpin_1_stat.pin = GPIO_34;
testpin_1_stat.val = GPIO_LOW;
BusDevWriteData(pin->owner_haldev, &write_param_1);
while (RET_TRUE) {
DelayKTask(10);
DelayKTask(1);
}
}
@ -288,11 +314,11 @@ void GpioSpeedTest()
write_param_1.buffer = (void *)&testpin_1_stat;
testpin_1.cmd = GPIO_CONFIG_MODE;
testpin_1.pin = GPIO_18;
testpin_1.pin = GPIO_34;
testpin_1.mode = GPIO_CFG_OUTPUT;
BusDrvConfigure(pin->owner_driver, &configure_info_1);
testpin_1_stat.pin = GPIO_18;
testpin_1_stat.pin = GPIO_34;
testpin_1_stat.val = GPIO_LOW;
BusDevWriteData(pin->owner_haldev, &write_param_1);

7
Ubiquitous/XiZi_IIoT/kernel/thread/init.c
View File

@ -33,6 +33,11 @@
#endif
#endif
#ifdef BSP_USING_QSPI_FLASH
#include "connect_flash.h"
extern int FlashW25qxxSpiDeviceInit(void);
#endif
#ifdef KERNEL_USER_MAIN
#ifndef MAIN_KTASK_STACK_SIZE
#define MAIN_KTASK_STACK_SIZE 2048
@ -46,6 +51,8 @@
extern int StartWatchdog(void);
#endif
extern void CreateKServiceKTask(void);
extern int main(void);
void InitBoardHardware(void);

12
Ubiquitous/XiZi_IIoT/path_kernel.mk
View File

@ -475,9 +475,21 @@ KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source/third_party/gemmlowp #
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source/third_party/flatbuffers/include #
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/tensorflow-lite/tensorflow-lite-for-mcu/source/third_party/ruy #
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/kpu/k210_yolov2_detect_procedure #
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/kpu/yolov2 #
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/kpu/yolov2_json #
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/nnom/inc #
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/nnom/inc/layers #
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/nnom/port #
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/cmsis_5/Core/Include #
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/cmsis_5/DSP/Include #
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/cmsis_5/DSP/Include/dsp #
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/knowing/cmsis_5/NN/Include #
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Applications/knowing_app/cmsis_5_demo/cmsisnn-cifar10/model/m4 #
endif
ifeq ($(CONFIG_LIB_LV),y)

2
Ubiquitous/XiZi_IIoT/resources/spi/third_party_spi/SFUD/sfud/src/sfud.c
View File

@ -444,7 +444,7 @@ sfud_err sfud_read(const sfud_flash *flash, uint32_t addr, size_t size, uint8_t
#endif
{
cmd_data[0] = SFUD_CMD_READ_DATA;
make_adress_byte_array(flash, addr, &cmd_data[1]);
make_adress_byte_array(flash, addr, cmd_data+1);
cmd_size = flash->addr_in_4_byte ? 5 : 4;
result = spi->wr(spi, cmd_data, cmd_size, data, size);
}