forked from xuos/xiuos
feat add third_party_driver/spi for hc32f4a0 board, compile OK
This commit is contained in:
Liu_Weichao
parent
37bdc4a33f
commit
700a07bc84
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@ -103,7 +103,7 @@ static x_err_t Stm32SpiInit(struct Stm32Spi *SpiDrv, struct SpiMasterParam *cfg)
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SPI_InitTypeDef *SpiInit = &SpiDrv->init;
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if (cfg->spi_work_mode & DEV_SPI_SLAVE)
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if (cfg->spi_work_mode & SPI_DEV_SLAVE)
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{
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SpiInit->SPI_Mode = SPI_Mode_Slave;
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}
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@ -221,7 +221,7 @@ static uint32 SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiDataStand
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{
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SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_dev->haldev.private_data);
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uint32 spi_read_length = 0;;
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uint32 spi_read_length = 0;
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uint8 device_id = dev_param->spi_slave_param->spi_slave_id;
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uint8 device_master_id = dev_param->spi_dma_param->spi_master_id;
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uint8 cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;
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@ -5,3 +5,11 @@ menuconfig BSP_USING_UART
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if BSP_USING_UART
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source "$BSP_DIR/third_party_driver/usart/Kconfig"
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endif
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menuconfig BSP_USING_SPI
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bool "Using SPI device"
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default y
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select RESOURCES_SPI
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if BSP_USING_SPI
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source "$BSP_DIR/third_party_driver/spi/Kconfig"
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endif
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@ -4,4 +4,8 @@ ifeq ($(CONFIG_BSP_USING_UART),y)
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SRC_DIR += usart
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endif
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ifeq ($(CONFIG_BSP_USING_SPI),y)
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SRC_DIR += spi
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endif
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include $(KERNEL_ROOT)/compiler.mk
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@ -0,0 +1,40 @@
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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/**
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* @file connect_spi.h
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* @brief define hc32f4a0-board spi function and struct
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* @version 2.0
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* @author AIIT XUOS Lab
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* @date 2022-10-17
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*/
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#ifndef CONNECT_SPI_H
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#define CONNECT_SPI_H
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#include <device.h>
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#include <hardware_irq.h>
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#include <hc32_ll_spi.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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int HwSpiInit(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -0,0 +1,33 @@
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if BSP_USING_SPI
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config BSP_USING_SPI1
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bool "Using spi1"
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default y
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if BSP_USING_SPI1
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config SPI_BUS_NAME_1
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string "spi bus 1 name"
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default "spi1"
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config SPI_1_DEVICE_NAME_0
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string "spi bus 1 device 0 name"
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default "spi1_dev0"
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config SPI_1_DRV_NAME
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string "spi bus 1 driver name"
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default "spi1_drv"
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endif
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config BSP_USING_SPI6
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bool "Using spi6"
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default y
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if BSP_USING_SPI6
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config SPI_BUS_NAME_6
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string "spi bus 6 name"
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default "spi6"
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config SPI_6_DEVICE_NAME_0
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string "spi bus 6 device 0 name"
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default "spi6_dev0"
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config SPI_6_DRV_NAME
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string "spi bus 6 driver name"
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default "spi6_drv"
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endif
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endif
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@ -0,0 +1,3 @@
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SRC_FILES := connect_spi.c
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include $(KERNEL_ROOT)/compiler.mk
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@ -0,0 +1,494 @@
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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/**
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* @file connect_spi.c
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* @brief support hc32f4a0-board spi function and register to bus framework
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* @version 2.0
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* @author AIIT XUOS Lab
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* @date 2022-10-17
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*/
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/*************************************************
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File name: connect_spi.c
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Description: support hc32f4a0-board spi function and register to bus framework
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Others:
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History:
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1. Date: 2022-10-17
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Author: AIIT XUOS Lab
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Modification:
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1. support hc32f4a0-board spi configure, write and read
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2. support hc32f4a0-board spi bus device and driver register
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3. SPI1 for LoRa, SPI6 using J12-pin-header to connect
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*************************************************/
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#include <connect_spi.h>
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#define SPI1_MASTER_SLAVE_MODE (SPI_MASTER)
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/* SPI1 definition */
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#define SPI1_UNIT (CM_SPI1)
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#define SPI1_CLK (FCG1_PERIPH_SPI1)
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/* SS = PI01 */
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#define SPI1_SS_PORT (GPIO_PORT_I)
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#define SPI1_SS_PIN (GPIO_PIN_01)
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#define SPI1_SS_FUNC (GPIO_FUNC_47)
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/* SCK = PH14 */
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#define SPI1_SCK_PORT (GPIO_PORT_H)
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#define SPI1_SCK_PIN (GPIO_PIN_14)
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#define SPI1_SCK_FUNC (GPIO_FUNC_40)
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/* MOSI = PI00 */
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#define SPI1_MOSI_PORT (GPIO_PORT_I)
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#define SPI1_MOSI_PIN (GPIO_PIN_00)
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#define SPI1_MOSI_FUNC (GPIO_FUNC_41)
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/* MISO = PH15 */
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#define SPI1_MISO_PORT (GPIO_PORT_H)
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#define SPI1_MISO_PIN (GPIO_PIN_15)
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#define SPI1_MISO_FUNC (GPIO_FUNC_42)
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#define SPI1_DEVICE_SLAVE_ID_0 0
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/* SPI6 definition */
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#define SPI6_UNIT (CM_SPI6)
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#define SPI6_CLK (FCG1_PERIPH_SPI6)
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/* SS = PI01 */
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#define SPI6_SS_PORT (GPIO_PORT_I)
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#define SPI6_SS_PIN (GPIO_PIN_01)
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#define SPI6_SS_FUNC (GPIO_FUNC_47)
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/* SCK = PH14 */
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#define SPI6_SCK_PORT (GPIO_PORT_H)
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#define SPI6_SCK_PIN (GPIO_PIN_14)
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#define SPI6_SCK_FUNC (GPIO_FUNC_40)
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/* MOSI = PI00 */
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#define SPI6_MOSI_PORT (GPIO_PORT_I)
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#define SPI6_MOSI_PIN (GPIO_PIN_00)
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#define SPI6_MOSI_FUNC (GPIO_FUNC_41)
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/* MISO = PH15 */
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#define SPI6_MISO_PORT (GPIO_PORT_H)
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#define SPI6_MISO_PIN (GPIO_PIN_15)
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#define SPI6_MISO_FUNC (GPIO_FUNC_42)
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#define SPI6_DEVICE_SLAVE_ID_0 0
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static void HwSpiEnable(CM_SPI_TypeDef *SPIx)
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{
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/* Check if the SPI is already enabled */
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if (SPI_CR1_SPE != (SPIx->CR1 & SPI_CR1_SPE)) {
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SPI_Cmd(SPIx, ENABLE);
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}
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}
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/*Init the spi sdk intetface */
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static uint32 SpiSdkInit(struct SpiDriver *spi_drv)
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{
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NULL_PARAM_CHECK(spi_drv);
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stc_spi_init_t stcSpiInit;
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SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_drv->driver.private_data);
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//#ifdef BSP_USING_SPI1
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/* Configure Port */
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GPIO_SetFunc(SPI1_SS_PORT, SPI1_SS_PIN, SPI1_SS_FUNC);
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GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC);
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GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC);
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GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC);
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/* Configuration SPI */
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FCG_Fcg1PeriphClockCmd(SPI1_CLK, ENABLE);
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SPI_StructInit(&stcSpiInit);
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stcSpiInit.u32WireMode = SPI_4_WIRE;
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stcSpiInit.u32TransMode = SPI_FULL_DUPLEX;
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stcSpiInit.u32MasterSlave = SPI1_MASTER_SLAVE_MODE;
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stcSpiInit.u32Parity = SPI_PARITY_INVD;
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if (SPI_MODE_0 == dev_param->spi_master_param->spi_work_mode & 0x3) {
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stcSpiInit.u32SpiMode = SPI_MD_0;
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} else if (SPI_MODE_1 == dev_param->spi_master_param->spi_work_mode & 0x3) {
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stcSpiInit.u32SpiMode = SPI_MD_1;
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} else if (SPI_MODE_2 == dev_param->spi_master_param->spi_work_mode & 0x3) {
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stcSpiInit.u32SpiMode = SPI_MD_2;
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} else if (SPI_MODE_3 == dev_param->spi_master_param->spi_work_mode & 0x3) {
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stcSpiInit.u32SpiMode = SPI_MD_3;
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}
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stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV64;
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if (8 == dev_param->spi_master_param->spi_data_bit_width) {
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stcSpiInit.u32DataBits = SPI_DATA_SIZE_8BIT;
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} else if (7 == dev_param->spi_master_param->spi_data_bit_width) {
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stcSpiInit.u32DataBits = SPI_DATA_SIZE_7BIT;
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}
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if (SPI_LSB == dev_param->spi_master_param->spi_work_mode & 0x4) {
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stcSpiInit.u32FirstBit = SPI_FIRST_LSB;
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} else if(SPI_MSB == dev_param->spi_master_param->spi_work_mode & 0x4) {
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stcSpiInit.u32FirstBit = SPI_FIRST_MSB;
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}
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stcSpiInit.u32FrameLevel = SPI_1_FRAME;
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(void)SPI_Init(SPI1_UNIT, &stcSpiInit);
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SPI_Cmd(SPI1_UNIT, ENABLE);
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//#endif
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#ifdef BSP_USING_SPI6
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/* Configure Port */
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GPIO_SetFunc(SPI6_SS_PORT, SPI6_SS_PIN, SPI6_SS_FUNC);
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GPIO_SetFunc(SPI6_SCK_PORT, SPI6_SCK_PIN, SPI6_SCK_FUNC);
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GPIO_SetFunc(SPI6_MOSI_PORT, SPI6_MOSI_PIN, SPI6_MOSI_FUNC);
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GPIO_SetFunc(SPI6_MISO_PORT, SPI6_MISO_PIN, SPI6_MISO_FUNC);
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/* Configuration SPI */
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FCG_Fcg1PeriphClockCmd(SPI6_CLK, ENABLE);
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SPI_StructInit(&stcSpiInit);
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stcSpiInit.u32WireMode = SPI_4_WIRE;
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stcSpiInit.u32TransMode = SPI_FULL_DUPLEX;
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stcSpiInit.u32MasterSlave = SPI1_MASTER_SLAVE_MODE;
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stcSpiInit.u32Parity = SPI_PARITY_INVD;
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if (SPI_MODE_0 == dev_param->spi_master_param->spi_work_mode & 0x3) {
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stcSpiInit.u32SpiMode = SPI_MD_0;
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} else if (SPI_MODE_1 == dev_param->spi_master_param->spi_work_mode & 0x3) {
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stcSpiInit.u32SpiMode = SPI_MD_1;
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} else if (SPI_MODE_2 == dev_param->spi_master_param->spi_work_mode & 0x3) {
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stcSpiInit.u32SpiMode = SPI_MD_2;
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} else if (SPI_MODE_3 == dev_param->spi_master_param->spi_work_mode & 0x3) {
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stcSpiInit.u32SpiMode = SPI_MD_3;
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}
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stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV64;
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if (8 == dev_param->spi_master_param->spi_data_bit_width) {
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stcSpiInit.u32DataBits = SPI_DATA_SIZE_8BIT;
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} else if (7 == dev_param->spi_master_param->spi_data_bit_width) {
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stcSpiInit.u32DataBits = SPI_DATA_SIZE_7BIT;
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}
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if (SPI_LSB == dev_param->spi_master_param->spi_work_mode & 0x4) {
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stcSpiInit.u32FirstBit = SPI_FIRST_LSB;
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} else if(SPI_MSB == dev_param->spi_master_param->spi_work_mode & 0x4) {
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stcSpiInit.u32FirstBit = SPI_FIRST_MSB;
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}
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stcSpiInit.u32FrameLevel = SPI_1_FRAME;
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(void)SPI_Init(SPI6_UNIT, &stcSpiInit);
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SPI_Cmd(SPI6_UNIT, ENABLE);
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#endif
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return EOK;
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}
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static uint32 SpiSdkCfg(struct SpiDriver *spi_drv, struct SpiMasterParam *spi_param)
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{
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NULL_PARAM_CHECK(spi_drv);
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NULL_PARAM_CHECK(spi_param);
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SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_drv->driver.private_data);
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dev_param->spi_master_param = spi_param;
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dev_param->spi_master_param->spi_work_mode = dev_param->spi_master_param->spi_work_mode & SPI_MODE_MASK;
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return EOK;
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}
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/*Configure the spi device param, make sure struct (configure_info->private_data) = (SpiMasterParam)*/
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static uint32 SpiDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
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{
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NULL_PARAM_CHECK(drv);
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NULL_PARAM_CHECK(configure_info);
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x_err_t ret = EOK;
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struct SpiDriver *spi_drv = (struct SpiDriver *)drv;
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struct SpiMasterParam *spi_param;
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switch (configure_info->configure_cmd)
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{
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case OPE_INT:
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ret = SpiSdkInit(spi_drv);
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break;
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case OPE_CFG:
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spi_param = (struct SpiMasterParam *)configure_info->private_data;
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ret = SpiSdkCfg(spi_drv, spi_param);
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break;
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default:
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break;
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}
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return ret;
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}
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static uint32 SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg)
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{
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SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_dev->haldev.private_data);
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uint8 cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;
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uint8 cs_gpio_port = dev_param->spi_slave_param->spi_cs_gpio_port;
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CM_SPI_TypeDef *spi = spi_dev->haldev.owner_bus->private_data;
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int i = 0;
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uint32 ret = EOK;
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int32 spi_write_status = 0;
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while (NONE != spi_datacfg) {
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if (spi_datacfg->spi_chip_select) {
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GPIO_ResetPins(cs_gpio_port, cs_gpio_pin);
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}
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if (spi_datacfg->length) {
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uint8 *tx_buff = x_malloc(spi_datacfg->length);
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if ((spi_datacfg->tx_buff) && (tx_buff)) {
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memset(tx_buff, 0, spi_datacfg->length);
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for (i = 0; i < spi_datacfg->length; i++) {
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tx_buff[i] = ((uint8 *)spi_datacfg->tx_buff)[i];
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}
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HwSpiEnable(spi);
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spi_write_status = SPI_Trans(spi, tx_buff, spi_datacfg->length, 1000);
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while (RESET != SPI_GetStatus(spi, SPI_FLAG_IDLE));
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if (LL_OK == spi_write_status) {
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ret = ERROR;
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}
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}
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if (tx_buff) {
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x_free(tx_buff);
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}
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}
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SPI_ClearStatus(spi, SPI_FLAG_CLR_ALL | SPI_FLAG_RX_BUF_FULL);
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if (spi_datacfg->spi_cs_release) {
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GPIO_SetPins(cs_gpio_port, cs_gpio_pin);
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}
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spi_datacfg = spi_datacfg->next;
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}
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return ret;
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}
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static uint32 SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg)
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{
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SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_dev->haldev.private_data);
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uint8 cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;
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uint8 cs_gpio_port = dev_param->spi_slave_param->spi_cs_gpio_port;
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CM_SPI_TypeDef *spi = spi_dev->haldev.owner_bus->private_data;
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int i = 0;
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int32 spi_read_status = 0;
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uint32 spi_read_length = 0;
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while (NONE != spi_datacfg) {
|
||||
if (spi_datacfg->spi_chip_select) {
|
||||
GPIO_ResetPins(cs_gpio_port, cs_gpio_pin);
|
||||
}
|
||||
|
||||
if (spi_datacfg->length) {
|
||||
uint32_t *rx_buff = x_malloc(spi_datacfg->length * 4);
|
||||
if ((spi_datacfg->rx_buff) && (rx_buff)) {
|
||||
memset(rx_buff, 0xFF, spi_datacfg->length * 4);
|
||||
|
||||
HwSpiEnable(spi);
|
||||
spi_read_status = SPI_Receive(spi, rx_buff, spi_datacfg->length, 1000);
|
||||
|
||||
while (RESET != SPI_GetStatus(spi, SPI_FLAG_IDLE));
|
||||
|
||||
if (LL_OK == spi_read_status) {
|
||||
for (i = 0; i < spi_datacfg->length; i++) {
|
||||
((uint8_t *)spi_datacfg->rx_buff)[i] = (uint8_t)rx_buff[i];
|
||||
}
|
||||
}
|
||||
}
|
||||
if (rx_buff) {
|
||||
x_free(rx_buff);
|
||||
}
|
||||
}
|
||||
|
||||
SPI_ClearStatus(spi, SPI_FLAG_CLR_ALL | SPI_FLAG_RX_BUF_FULL);
|
||||
|
||||
if (spi_datacfg->spi_cs_release) {
|
||||
GPIO_SetPins(cs_gpio_port, cs_gpio_pin);
|
||||
}
|
||||
|
||||
spi_read_length += spi_datacfg->length;
|
||||
spi_datacfg = spi_datacfg->next;
|
||||
}
|
||||
|
||||
return spi_read_length;
|
||||
}
|
||||
|
||||
|
||||
/*manage the spi device operations*/
|
||||
static const struct SpiDevDone spi_dev_done =
|
||||
{
|
||||
.dev_open = NONE,
|
||||
.dev_close = NONE,
|
||||
.dev_write = SpiWriteData,
|
||||
.dev_read = SpiReadData,
|
||||
};
|
||||
|
||||
static int BoardSpiBusInit(struct SpiBus *spi_bus, struct SpiDriver *spi_driver, const char *bus_name, const char *drv_name)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
/*Init the spi bus */
|
||||
ret = SpiBusInit(spi_bus, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("Board_Spi_init SpiBusInit error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/*Init the spi driver*/
|
||||
ret = SpiDriverInit(spi_driver, drv_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("Board_Spi_init SpiDriverInit error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/*Attach the spi driver to the spi bus*/
|
||||
ret = SpiDriverAttachToBus(drv_name, bus_name);
|
||||
if (EOK != ret) {
|
||||
KPrintf("Board_Spi_init SpiDriverAttachToBus error %d\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*Attach the spi device to the spi bus*/
|
||||
static int BoardSpiDevBend(void)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
//#ifdef BSP_SPI1_USING_SS0
|
||||
static struct SpiHardwareDevice spi1_device0;
|
||||
memset(&spi1_device0, 0, sizeof(struct SpiHardwareDevice));
|
||||
|
||||
static struct SpiSlaveParam spi1_slaveparam0;
|
||||
memset(&spi1_slaveparam0, 0, sizeof(struct SpiSlaveParam));
|
||||
|
||||
spi1_slaveparam0.spi_slave_id = SPI1_DEVICE_SLAVE_ID_0;
|
||||
spi1_slaveparam0.spi_cs_gpio_pin = SPI1_SS_PIN;
|
||||
spi1_slaveparam0.spi_cs_gpio_port = SPI1_SS_PORT;
|
||||
|
||||
spi1_device0.spi_param.spi_slave_param = &spi1_slaveparam0;
|
||||
|
||||
spi1_device0.spi_dev_done = &(spi_dev_done);
|
||||
|
||||
ret = SpiDeviceRegister(&spi1_device0, (void *)(&spi1_device0.spi_param), SPI_1_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("BoardSpiDevBend SpiDeviceRegister device %s error %d\n", SPI_1_DEVICE_NAME_0, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = SpiDeviceAttachToBus(SPI_1_DEVICE_NAME_0, SPI_BUS_NAME_1);
|
||||
if (EOK != ret) {
|
||||
KPrintf("BoardSpiDevBend SpiDeviceAttachToBus device %s error %d\n", SPI_1_DEVICE_NAME_0, ret);
|
||||
return ERROR;
|
||||
}
|
||||
//#endif
|
||||
|
||||
#ifdef BSP_SPI6_USING_SS0
|
||||
static struct SpiHardwareDevice spi6_device0;
|
||||
memset(&spi6_device0, 0, sizeof(struct SpiHardwareDevice));
|
||||
|
||||
static struct SpiSlaveParam spi6_slaveparam0;
|
||||
memset(&spi6_slaveparam0, 0, sizeof(struct SpiSlaveParam));
|
||||
|
||||
spi6_slaveparam0.spi_slave_id = SPI1_DEVICE_SLAVE_ID_0;
|
||||
spi6_slaveparam0.spi_cs_gpio_pin = SPI6_SS_PIN;
|
||||
spi6_slaveparam0.spi_cs_gpio_port = SPI6_SS_PORT;
|
||||
|
||||
spi6_device0.spi_param.spi_slave_param = &spi6_slaveparam0;
|
||||
|
||||
spi6_device0.spi_dev_done = &(spi_dev_done);
|
||||
|
||||
ret = SpiDeviceRegister(&spi6_device0, (void *)(&spi6_device0.spi_param), SPI_6_DEVICE_NAME_0);
|
||||
if (EOK != ret) {
|
||||
KPrintf("BoardSpiDevBend SpiDeviceRegister device %s error %d\n", SPI_6_DEVICE_NAME_0, ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = SpiDeviceAttachToBus(SPI_6_DEVICE_NAME_0, SPI_BUS_NAME_6);
|
||||
if (EOK != ret) {
|
||||
KPrintf("BoardSpiDevBend SpiDeviceAttachToBus device %s error %d\n", SPI_6_DEVICE_NAME_0, ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int HwSpiInit(void)
|
||||
{
|
||||
x_err_t ret = EOK;
|
||||
|
||||
//#ifdef BSP_USING_SPI1
|
||||
static struct SpiBus spi1_bus;
|
||||
memset(&spi1_bus, 0, sizeof(struct SpiBus));
|
||||
|
||||
static struct SpiDriver spi1_driver;
|
||||
memset(&spi1_driver, 0, sizeof(struct SpiDriver));
|
||||
|
||||
spi1_bus.private_data = SPI1_UNIT;
|
||||
spi1_driver.configure = SpiDrvConfigure;
|
||||
|
||||
ret = BoardSpiBusInit(&spi1_bus, &spi1_driver, SPI_BUS_NAME_1, SPI_1_DRV_NAME);
|
||||
if (EOK != ret) {
|
||||
KPrintf("BoardSpiBusInit error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSpiDevBend();
|
||||
if (EOK != ret) {
|
||||
KPrintf("BoardSpiDevBend error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
//#endif
|
||||
|
||||
#ifdef BSP_USING_SPI6
|
||||
static struct SpiBus spi6_bus;
|
||||
memset(&spi6_bus, 0, sizeof(struct SpiBus));
|
||||
|
||||
static struct SpiDriver spi6_driver;
|
||||
memset(&spi6_driver, 0, sizeof(struct SpiDriver));
|
||||
|
||||
spi6_bus.private_data = SPI6_UNIT;
|
||||
spi6_driver.configure = SpiDrvConfigure;
|
||||
|
||||
ret = BoardSpiBusInit(&spi6_bus, &spi6_driver, SPI_BUS_NAME_6, SPI_6_DRV_NAME);
|
||||
if (EOK != ret) {
|
||||
KPrintf("BoardSpiBusInit error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
ret = BoardSpiDevBend();
|
||||
if (EOK != ret) {
|
||||
KPrintf("BoardSpiDevBend error ret %u\n", ret);
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -110,7 +110,7 @@ static x_err_t Stm32SpiInit(struct Stm32Spi *spi_drv, struct SpiMasterParam *cfg
|
|||
|
||||
SPI_InitTypeDef *spi_init = &spi_drv->init;
|
||||
|
||||
if (cfg->spi_work_mode & DEV_SPI_SLAVE){
|
||||
if (cfg->spi_work_mode & SPI_DEV_SLAVE){
|
||||
spi_init->SPI_Mode = SPI_Mode_Slave;
|
||||
}
|
||||
else{
|
||||
|
|
|
|||
|
|
@ -28,27 +28,27 @@ extern "C" {
|
|||
#endif
|
||||
|
||||
#define SPI_MAX_CLOCK 40000000
|
||||
#define spi_device_max_num 4
|
||||
#define spi_device_max_num 4
|
||||
|
||||
#define SPI_LINE_CPHA (1<<0)
|
||||
#define SPI_LINE_CPOL (1<<1)
|
||||
#define SPI_LINE_CPHA (1 << 0)
|
||||
#define SPI_LINE_CPOL (1 << 1)
|
||||
|
||||
#define SPI_LSB (0<<2)
|
||||
#define SPI_MSB (1<<2)
|
||||
#define SPI_LSB (0 << 2)
|
||||
#define SPI_MSB (1 << 2)
|
||||
|
||||
#define SPI_MASTER (0<<3)
|
||||
#define DEV_SPI_SLAVE (1<<3)
|
||||
#define SPI_DEV_MASTER (0 << 3)
|
||||
#define SPI_DEV_SLAVE (1 << 3)
|
||||
|
||||
#define SPI_MODE_0 (0 | 0)
|
||||
#define SPI_MODE_1 (0 | SPI_LINE_CPHA)
|
||||
#define SPI_MODE_2 (SPI_LINE_CPOL | 0)
|
||||
#define SPI_MODE_3 (SPI_LINE_CPOL | SPI_LINE_CPHA)
|
||||
#define SPI_MODE_MASK (SPI_LINE_CPHA | SPI_LINE_CPOL | SPI_MSB)
|
||||
#define SPI_MODE_0 (0 | 0)
|
||||
#define SPI_MODE_1 (0 | SPI_LINE_CPHA)
|
||||
#define SPI_MODE_2 (SPI_LINE_CPOL | 0)
|
||||
#define SPI_MODE_3 (SPI_LINE_CPOL | SPI_LINE_CPHA)
|
||||
#define SPI_MODE_MASK (SPI_LINE_CPHA | SPI_LINE_CPOL | SPI_MSB)
|
||||
|
||||
#define SPI_CS_HIGH (1<<4)
|
||||
#define SPI_NO_CS (1<<5)
|
||||
#define SPI_3WIRE (1<<6)
|
||||
#define SPI_READY (1<<7)
|
||||
#define SPI_CS_HIGH (1 << 4)
|
||||
#define SPI_NO_CS (1 << 5)
|
||||
#define SPI_3WIRE (1 << 6)
|
||||
#define SPI_READY (1 << 7)
|
||||
|
||||
struct SpiDataStandard
|
||||
{
|
||||
|
|
@ -83,9 +83,10 @@ struct SpiDmaParam
|
|||
|
||||
struct SpiSlaveParam
|
||||
{
|
||||
uint8 spi_slave_id;
|
||||
uint8 spi_cs_gpio_pin;
|
||||
uint8 spi_cs_select_id;
|
||||
uint32 spi_slave_id;
|
||||
uint32 spi_cs_gpio_pin;
|
||||
uint32 spi_cs_gpio_port;
|
||||
uint32 spi_cs_select_id;
|
||||
};
|
||||
|
||||
typedef struct
|
||||
|
|
|
|||
Loading…
Reference in New Issue