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feat add third_party_driver/spi for hc32f4a0 board, compile OK

This commit is contained in:
Liu_Weichao 2022-10-18 15:03:44 +08:00
parent 37bdc4a33f
commit 700a07bc84
10 changed files with 605 additions and 22 deletions
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2
Ubiquitous/XiZi_IIoT/board/aiit-arm32-board/third_party_driver/spi/connect_spi.c
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@ -103,7 +103,7 @@ static x_err_t Stm32SpiInit(struct Stm32Spi *SpiDrv, struct SpiMasterParam *cfg)
SPI_InitTypeDef *SpiInit = &SpiDrv->init; SPI_InitTypeDef *SpiInit = &SpiDrv->init;
if (cfg->spi_work_mode & DEV_SPI_SLAVE) if (cfg->spi_work_mode & SPI_DEV_SLAVE)
{ {
SpiInit->SPI_Mode = SPI_Mode_Slave; SpiInit->SPI_Mode = SPI_Mode_Slave;
} }

2
Ubiquitous/XiZi_IIoT/board/aiit-riscv64-board/third_party_driver/spi/connect_spi.c
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@ -221,7 +221,7 @@ static uint32 SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiDataStand
{ {
SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_dev->haldev.private_data); SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_dev->haldev.private_data);
uint32 spi_read_length = 0;; uint32 spi_read_length = 0;
uint8 device_id = dev_param->spi_slave_param->spi_slave_id; uint8 device_id = dev_param->spi_slave_param->spi_slave_id;
uint8 device_master_id = dev_param->spi_dma_param->spi_master_id; uint8 device_master_id = dev_param->spi_dma_param->spi_master_id;
uint8 cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin; uint8 cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;

8
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/Kconfig
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@ -5,3 +5,11 @@ menuconfig BSP_USING_UART
if BSP_USING_UART if BSP_USING_UART
source "$BSP_DIR/third_party_driver/usart/Kconfig" source "$BSP_DIR/third_party_driver/usart/Kconfig"
endif endif
menuconfig BSP_USING_SPI
bool "Using SPI device"
default y
select RESOURCES_SPI
if BSP_USING_SPI
source "$BSP_DIR/third_party_driver/spi/Kconfig"
endif

4
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/Makefile
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@ -4,4 +4,8 @@ ifeq ($(CONFIG_BSP_USING_UART),y)
SRC_DIR += usart SRC_DIR += usart
endif endif
ifeq ($(CONFIG_BSP_USING_SPI),y)
SRC_DIR += spi
endif
include $(KERNEL_ROOT)/compiler.mk include $(KERNEL_ROOT)/compiler.mk

40
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/include/connect_spi.h Normal file
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@ -0,0 +1,40 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_spi.h
* @brief define hc32f4a0-board spi function and struct
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-10-17
*/
#ifndef CONNECT_SPI_H
#define CONNECT_SPI_H
#include <device.h>
#include <hardware_irq.h>
#include <hc32_ll_spi.h>
#ifdef __cplusplus
extern "C" {
#endif
int HwSpiInit(void);
#ifdef __cplusplus
}
#endif
#endif

33
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/spi/Kconfig Normal file
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@ -0,0 +1,33 @@
if BSP_USING_SPI
config BSP_USING_SPI1
bool "Using spi1"
default y
if BSP_USING_SPI1
config SPI_BUS_NAME_1
string "spi bus 1 name"
default "spi1"
config SPI_1_DEVICE_NAME_0
string "spi bus 1 device 0 name"
default "spi1_dev0"
config SPI_1_DRV_NAME
string "spi bus 1 driver name"
default "spi1_drv"
endif
config BSP_USING_SPI6
bool "Using spi6"
default y
if BSP_USING_SPI6
config SPI_BUS_NAME_6
string "spi bus 6 name"
default "spi6"
config SPI_6_DEVICE_NAME_0
string "spi bus 6 device 0 name"
default "spi6_dev0"
config SPI_6_DRV_NAME
string "spi bus 6 driver name"
default "spi6_drv"
endif
endif

3
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/spi/Makefile Normal file
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@ -0,0 +1,3 @@
SRC_FILES := connect_spi.c
include $(KERNEL_ROOT)/compiler.mk

494
Ubiquitous/XiZi_IIoT/board/hc32f4a0/third_party_driver/spi/connect_spi.c Normal file
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@ -0,0 +1,494 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_spi.c
* @brief support hc32f4a0-board spi function and register to bus framework
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-10-17
*/
/*************************************************
File name: connect_spi.c
Description: support hc32f4a0-board spi function and register to bus framework
Others:
History:
1. Date: 2022-10-17
Author: AIIT XUOS Lab
Modification:
1. support hc32f4a0-board spi configure, write and read
2. support hc32f4a0-board spi bus device and driver register
3. SPI1 for LoRa, SPI6 using J12-pin-header to connect
*************************************************/
#include <connect_spi.h>
#define SPI1_MASTER_SLAVE_MODE (SPI_MASTER)
/* SPI1 definition */
#define SPI1_UNIT (CM_SPI1)
#define SPI1_CLK (FCG1_PERIPH_SPI1)
/* SS = PI01 */
#define SPI1_SS_PORT (GPIO_PORT_I)
#define SPI1_SS_PIN (GPIO_PIN_01)
#define SPI1_SS_FUNC (GPIO_FUNC_47)
/* SCK = PH14 */
#define SPI1_SCK_PORT (GPIO_PORT_H)
#define SPI1_SCK_PIN (GPIO_PIN_14)
#define SPI1_SCK_FUNC (GPIO_FUNC_40)
/* MOSI = PI00 */
#define SPI1_MOSI_PORT (GPIO_PORT_I)
#define SPI1_MOSI_PIN (GPIO_PIN_00)
#define SPI1_MOSI_FUNC (GPIO_FUNC_41)
/* MISO = PH15 */
#define SPI1_MISO_PORT (GPIO_PORT_H)
#define SPI1_MISO_PIN (GPIO_PIN_15)
#define SPI1_MISO_FUNC (GPIO_FUNC_42)
#define SPI1_DEVICE_SLAVE_ID_0 0
/* SPI6 definition */
#define SPI6_UNIT (CM_SPI6)
#define SPI6_CLK (FCG1_PERIPH_SPI6)
/* SS = PI01 */
#define SPI6_SS_PORT (GPIO_PORT_I)
#define SPI6_SS_PIN (GPIO_PIN_01)
#define SPI6_SS_FUNC (GPIO_FUNC_47)
/* SCK = PH14 */
#define SPI6_SCK_PORT (GPIO_PORT_H)
#define SPI6_SCK_PIN (GPIO_PIN_14)
#define SPI6_SCK_FUNC (GPIO_FUNC_40)
/* MOSI = PI00 */
#define SPI6_MOSI_PORT (GPIO_PORT_I)
#define SPI6_MOSI_PIN (GPIO_PIN_00)
#define SPI6_MOSI_FUNC (GPIO_FUNC_41)
/* MISO = PH15 */
#define SPI6_MISO_PORT (GPIO_PORT_H)
#define SPI6_MISO_PIN (GPIO_PIN_15)
#define SPI6_MISO_FUNC (GPIO_FUNC_42)
#define SPI6_DEVICE_SLAVE_ID_0 0
static void HwSpiEnable(CM_SPI_TypeDef *SPIx)
{
/* Check if the SPI is already enabled */
if (SPI_CR1_SPE != (SPIx->CR1 & SPI_CR1_SPE)) {
SPI_Cmd(SPIx, ENABLE);
}
}
/*Init the spi sdk intetface */
static uint32 SpiSdkInit(struct SpiDriver *spi_drv)
{
NULL_PARAM_CHECK(spi_drv);
stc_spi_init_t stcSpiInit;
SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_drv->driver.private_data);
//#ifdef BSP_USING_SPI1
/* Configure Port */
GPIO_SetFunc(SPI1_SS_PORT, SPI1_SS_PIN, SPI1_SS_FUNC);
GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC);
GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC);
GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC);
/* Configuration SPI */
FCG_Fcg1PeriphClockCmd(SPI1_CLK, ENABLE);
SPI_StructInit(&stcSpiInit);
stcSpiInit.u32WireMode = SPI_4_WIRE;
stcSpiInit.u32TransMode = SPI_FULL_DUPLEX;
stcSpiInit.u32MasterSlave = SPI1_MASTER_SLAVE_MODE;
stcSpiInit.u32Parity = SPI_PARITY_INVD;
if (SPI_MODE_0 == dev_param->spi_master_param->spi_work_mode & 0x3) {
stcSpiInit.u32SpiMode = SPI_MD_0;
} else if (SPI_MODE_1 == dev_param->spi_master_param->spi_work_mode & 0x3) {
stcSpiInit.u32SpiMode = SPI_MD_1;
} else if (SPI_MODE_2 == dev_param->spi_master_param->spi_work_mode & 0x3) {
stcSpiInit.u32SpiMode = SPI_MD_2;
} else if (SPI_MODE_3 == dev_param->spi_master_param->spi_work_mode & 0x3) {
stcSpiInit.u32SpiMode = SPI_MD_3;
}
stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV64;
if (8 == dev_param->spi_master_param->spi_data_bit_width) {
stcSpiInit.u32DataBits = SPI_DATA_SIZE_8BIT;
} else if (7 == dev_param->spi_master_param->spi_data_bit_width) {
stcSpiInit.u32DataBits = SPI_DATA_SIZE_7BIT;
}
if (SPI_LSB == dev_param->spi_master_param->spi_work_mode & 0x4) {
stcSpiInit.u32FirstBit = SPI_FIRST_LSB;
} else if(SPI_MSB == dev_param->spi_master_param->spi_work_mode & 0x4) {
stcSpiInit.u32FirstBit = SPI_FIRST_MSB;
}
stcSpiInit.u32FrameLevel = SPI_1_FRAME;
(void)SPI_Init(SPI1_UNIT, &stcSpiInit);
SPI_Cmd(SPI1_UNIT, ENABLE);
//#endif
#ifdef BSP_USING_SPI6
/* Configure Port */
GPIO_SetFunc(SPI6_SS_PORT, SPI6_SS_PIN, SPI6_SS_FUNC);
GPIO_SetFunc(SPI6_SCK_PORT, SPI6_SCK_PIN, SPI6_SCK_FUNC);
GPIO_SetFunc(SPI6_MOSI_PORT, SPI6_MOSI_PIN, SPI6_MOSI_FUNC);
GPIO_SetFunc(SPI6_MISO_PORT, SPI6_MISO_PIN, SPI6_MISO_FUNC);
/* Configuration SPI */
FCG_Fcg1PeriphClockCmd(SPI6_CLK, ENABLE);
SPI_StructInit(&stcSpiInit);
stcSpiInit.u32WireMode = SPI_4_WIRE;
stcSpiInit.u32TransMode = SPI_FULL_DUPLEX;
stcSpiInit.u32MasterSlave = SPI1_MASTER_SLAVE_MODE;
stcSpiInit.u32Parity = SPI_PARITY_INVD;
if (SPI_MODE_0 == dev_param->spi_master_param->spi_work_mode & 0x3) {
stcSpiInit.u32SpiMode = SPI_MD_0;
} else if (SPI_MODE_1 == dev_param->spi_master_param->spi_work_mode & 0x3) {
stcSpiInit.u32SpiMode = SPI_MD_1;
} else if (SPI_MODE_2 == dev_param->spi_master_param->spi_work_mode & 0x3) {
stcSpiInit.u32SpiMode = SPI_MD_2;
} else if (SPI_MODE_3 == dev_param->spi_master_param->spi_work_mode & 0x3) {
stcSpiInit.u32SpiMode = SPI_MD_3;
}
stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV64;
if (8 == dev_param->spi_master_param->spi_data_bit_width) {
stcSpiInit.u32DataBits = SPI_DATA_SIZE_8BIT;
} else if (7 == dev_param->spi_master_param->spi_data_bit_width) {
stcSpiInit.u32DataBits = SPI_DATA_SIZE_7BIT;
}
if (SPI_LSB == dev_param->spi_master_param->spi_work_mode & 0x4) {
stcSpiInit.u32FirstBit = SPI_FIRST_LSB;
} else if(SPI_MSB == dev_param->spi_master_param->spi_work_mode & 0x4) {
stcSpiInit.u32FirstBit = SPI_FIRST_MSB;
}
stcSpiInit.u32FrameLevel = SPI_1_FRAME;
(void)SPI_Init(SPI6_UNIT, &stcSpiInit);
SPI_Cmd(SPI6_UNIT, ENABLE);
#endif
return EOK;
}
static uint32 SpiSdkCfg(struct SpiDriver *spi_drv, struct SpiMasterParam *spi_param)
{
NULL_PARAM_CHECK(spi_drv);
NULL_PARAM_CHECK(spi_param);
SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_drv->driver.private_data);
dev_param->spi_master_param = spi_param;
dev_param->spi_master_param->spi_work_mode = dev_param->spi_master_param->spi_work_mode & SPI_MODE_MASK;
return EOK;
}
/*Configure the spi device param, make sure struct (configure_info->private_data) = (SpiMasterParam)*/
static uint32 SpiDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
{
NULL_PARAM_CHECK(drv);
NULL_PARAM_CHECK(configure_info);
x_err_t ret = EOK;
struct SpiDriver *spi_drv = (struct SpiDriver *)drv;
struct SpiMasterParam *spi_param;
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = SpiSdkInit(spi_drv);
break;
case OPE_CFG:
spi_param = (struct SpiMasterParam *)configure_info->private_data;
ret = SpiSdkCfg(spi_drv, spi_param);
break;
default:
break;
}
return ret;
}
static uint32 SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg)
{
SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_dev->haldev.private_data);
uint8 cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;
uint8 cs_gpio_port = dev_param->spi_slave_param->spi_cs_gpio_port;
CM_SPI_TypeDef *spi = spi_dev->haldev.owner_bus->private_data;
int i = 0;
uint32 ret = EOK;
int32 spi_write_status = 0;
while (NONE != spi_datacfg) {
if (spi_datacfg->spi_chip_select) {
GPIO_ResetPins(cs_gpio_port, cs_gpio_pin);
}
if (spi_datacfg->length) {
uint8 *tx_buff = x_malloc(spi_datacfg->length);
if ((spi_datacfg->tx_buff) && (tx_buff)) {
memset(tx_buff, 0, spi_datacfg->length);
for (i = 0; i < spi_datacfg->length; i++) {
tx_buff[i] = ((uint8 *)spi_datacfg->tx_buff)[i];
}
HwSpiEnable(spi);
spi_write_status = SPI_Trans(spi, tx_buff, spi_datacfg->length, 1000);
while (RESET != SPI_GetStatus(spi, SPI_FLAG_IDLE));
if (LL_OK == spi_write_status) {
ret = ERROR;
}
}
if (tx_buff) {
x_free(tx_buff);
}
}
SPI_ClearStatus(spi, SPI_FLAG_CLR_ALL | SPI_FLAG_RX_BUF_FULL);
if (spi_datacfg->spi_cs_release) {
GPIO_SetPins(cs_gpio_port, cs_gpio_pin);
}
spi_datacfg = spi_datacfg->next;
}
return ret;
}
static uint32 SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg)
{
SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_dev->haldev.private_data);
uint8 cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;
uint8 cs_gpio_port = dev_param->spi_slave_param->spi_cs_gpio_port;
CM_SPI_TypeDef *spi = spi_dev->haldev.owner_bus->private_data;
int i = 0;
int32 spi_read_status = 0;
uint32 spi_read_length = 0;
while (NONE != spi_datacfg) {
if (spi_datacfg->spi_chip_select) {
GPIO_ResetPins(cs_gpio_port, cs_gpio_pin);
}
if (spi_datacfg->length) {
uint32_t *rx_buff = x_malloc(spi_datacfg->length * 4);
if ((spi_datacfg->rx_buff) && (rx_buff)) {
memset(rx_buff, 0xFF, spi_datacfg->length * 4);
HwSpiEnable(spi);
spi_read_status = SPI_Receive(spi, rx_buff, spi_datacfg->length, 1000);
while (RESET != SPI_GetStatus(spi, SPI_FLAG_IDLE));
if (LL_OK == spi_read_status) {
for (i = 0; i < spi_datacfg->length; i++) {
((uint8_t *)spi_datacfg->rx_buff)[i] = (uint8_t)rx_buff[i];
}
}
}
if (rx_buff) {
x_free(rx_buff);
}
}
SPI_ClearStatus(spi, SPI_FLAG_CLR_ALL | SPI_FLAG_RX_BUF_FULL);
if (spi_datacfg->spi_cs_release) {
GPIO_SetPins(cs_gpio_port, cs_gpio_pin);
}
spi_read_length += spi_datacfg->length;
spi_datacfg = spi_datacfg->next;
}
return spi_read_length;
}
/*manage the spi device operations*/
static const struct SpiDevDone spi_dev_done =
{
.dev_open = NONE,
.dev_close = NONE,
.dev_write = SpiWriteData,
.dev_read = SpiReadData,
};
static int BoardSpiBusInit(struct SpiBus *spi_bus, struct SpiDriver *spi_driver, const char *bus_name, const char *drv_name)
{
x_err_t ret = EOK;
/*Init the spi bus */
ret = SpiBusInit(spi_bus, bus_name);
if (EOK != ret) {
KPrintf("Board_Spi_init SpiBusInit error %d\n", ret);
return ERROR;
}
/*Init the spi driver*/
ret = SpiDriverInit(spi_driver, drv_name);
if (EOK != ret) {
KPrintf("Board_Spi_init SpiDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the spi driver to the spi bus*/
ret = SpiDriverAttachToBus(drv_name, bus_name);
if (EOK != ret) {
KPrintf("Board_Spi_init SpiDriverAttachToBus error %d\n", ret);
return ERROR;
}
return ret;
}
/*Attach the spi device to the spi bus*/
static int BoardSpiDevBend(void)
{
x_err_t ret = EOK;
//#ifdef BSP_SPI1_USING_SS0
static struct SpiHardwareDevice spi1_device0;
memset(&spi1_device0, 0, sizeof(struct SpiHardwareDevice));
static struct SpiSlaveParam spi1_slaveparam0;
memset(&spi1_slaveparam0, 0, sizeof(struct SpiSlaveParam));
spi1_slaveparam0.spi_slave_id = SPI1_DEVICE_SLAVE_ID_0;
spi1_slaveparam0.spi_cs_gpio_pin = SPI1_SS_PIN;
spi1_slaveparam0.spi_cs_gpio_port = SPI1_SS_PORT;
spi1_device0.spi_param.spi_slave_param = &spi1_slaveparam0;
spi1_device0.spi_dev_done = &(spi_dev_done);
ret = SpiDeviceRegister(&spi1_device0, (void *)(&spi1_device0.spi_param), SPI_1_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("BoardSpiDevBend SpiDeviceRegister device %s error %d\n", SPI_1_DEVICE_NAME_0, ret);
return ERROR;
}
ret = SpiDeviceAttachToBus(SPI_1_DEVICE_NAME_0, SPI_BUS_NAME_1);
if (EOK != ret) {
KPrintf("BoardSpiDevBend SpiDeviceAttachToBus device %s error %d\n", SPI_1_DEVICE_NAME_0, ret);
return ERROR;
}
//#endif
#ifdef BSP_SPI6_USING_SS0
static struct SpiHardwareDevice spi6_device0;
memset(&spi6_device0, 0, sizeof(struct SpiHardwareDevice));
static struct SpiSlaveParam spi6_slaveparam0;
memset(&spi6_slaveparam0, 0, sizeof(struct SpiSlaveParam));
spi6_slaveparam0.spi_slave_id = SPI1_DEVICE_SLAVE_ID_0;
spi6_slaveparam0.spi_cs_gpio_pin = SPI6_SS_PIN;
spi6_slaveparam0.spi_cs_gpio_port = SPI6_SS_PORT;
spi6_device0.spi_param.spi_slave_param = &spi6_slaveparam0;
spi6_device0.spi_dev_done = &(spi_dev_done);
ret = SpiDeviceRegister(&spi6_device0, (void *)(&spi6_device0.spi_param), SPI_6_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("BoardSpiDevBend SpiDeviceRegister device %s error %d\n", SPI_6_DEVICE_NAME_0, ret);
return ERROR;
}
ret = SpiDeviceAttachToBus(SPI_6_DEVICE_NAME_0, SPI_BUS_NAME_6);
if (EOK != ret) {
KPrintf("BoardSpiDevBend SpiDeviceAttachToBus device %s error %d\n", SPI_6_DEVICE_NAME_0, ret);
return ERROR;
}
#endif
return ret;
}
int HwSpiInit(void)
{
x_err_t ret = EOK;
//#ifdef BSP_USING_SPI1
static struct SpiBus spi1_bus;
memset(&spi1_bus, 0, sizeof(struct SpiBus));
static struct SpiDriver spi1_driver;
memset(&spi1_driver, 0, sizeof(struct SpiDriver));
spi1_bus.private_data = SPI1_UNIT;
spi1_driver.configure = SpiDrvConfigure;
ret = BoardSpiBusInit(&spi1_bus, &spi1_driver, SPI_BUS_NAME_1, SPI_1_DRV_NAME);
if (EOK != ret) {
KPrintf("BoardSpiBusInit error ret %u\n", ret);
return ERROR;
}
ret = BoardSpiDevBend();
if (EOK != ret) {
KPrintf("BoardSpiDevBend error ret %u\n", ret);
return ERROR;
}
//#endif
#ifdef BSP_USING_SPI6
static struct SpiBus spi6_bus;
memset(&spi6_bus, 0, sizeof(struct SpiBus));
static struct SpiDriver spi6_driver;
memset(&spi6_driver, 0, sizeof(struct SpiDriver));
spi6_bus.private_data = SPI6_UNIT;
spi6_driver.configure = SpiDrvConfigure;
ret = BoardSpiBusInit(&spi6_bus, &spi6_driver, SPI_BUS_NAME_6, SPI_6_DRV_NAME);
if (EOK != ret) {
KPrintf("BoardSpiBusInit error ret %u\n", ret);
return ERROR;
}
ret = BoardSpiDevBend();
if (EOK != ret) {
KPrintf("BoardSpiDevBend error ret %u\n", ret);
return ERROR;
}
#endif
return ret;
}

2
Ubiquitous/XiZi_IIoT/board/stm32f407-st-discovery/third_party_driver/spi/connect_spi.c
View File

@ -110,7 +110,7 @@ static x_err_t Stm32SpiInit(struct Stm32Spi *spi_drv, struct SpiMasterParam *cfg
SPI_InitTypeDef *spi_init = &spi_drv->init; SPI_InitTypeDef *spi_init = &spi_drv->init;
if (cfg->spi_work_mode & DEV_SPI_SLAVE){ if (cfg->spi_work_mode & SPI_DEV_SLAVE){
spi_init->SPI_Mode = SPI_Mode_Slave; spi_init->SPI_Mode = SPI_Mode_Slave;
} }
else{ else{

39
Ubiquitous/XiZi_IIoT/resources/include/dev_spi.h
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@ -28,27 +28,27 @@ extern "C" {
#endif #endif
#define SPI_MAX_CLOCK 40000000 #define SPI_MAX_CLOCK 40000000
#define spi_device_max_num 4 #define spi_device_max_num 4
#define SPI_LINE_CPHA (1<<0) #define SPI_LINE_CPHA (1 << 0)
#define SPI_LINE_CPOL (1<<1) #define SPI_LINE_CPOL (1 << 1)
#define SPI_LSB (0<<2) #define SPI_LSB (0 << 2)
#define SPI_MSB (1<<2) #define SPI_MSB (1 << 2)
#define SPI_MASTER (0<<3) #define SPI_DEV_MASTER (0 << 3)
#define DEV_SPI_SLAVE (1<<3) #define SPI_DEV_SLAVE (1 << 3)
#define SPI_MODE_0 (0 | 0) #define SPI_MODE_0 (0 | 0)
#define SPI_MODE_1 (0 | SPI_LINE_CPHA) #define SPI_MODE_1 (0 | SPI_LINE_CPHA)
#define SPI_MODE_2 (SPI_LINE_CPOL | 0) #define SPI_MODE_2 (SPI_LINE_CPOL | 0)
#define SPI_MODE_3 (SPI_LINE_CPOL | SPI_LINE_CPHA) #define SPI_MODE_3 (SPI_LINE_CPOL | SPI_LINE_CPHA)
#define SPI_MODE_MASK (SPI_LINE_CPHA | SPI_LINE_CPOL | SPI_MSB) #define SPI_MODE_MASK (SPI_LINE_CPHA | SPI_LINE_CPOL | SPI_MSB)
#define SPI_CS_HIGH (1<<4) #define SPI_CS_HIGH (1 << 4)
#define SPI_NO_CS (1<<5) #define SPI_NO_CS (1 << 5)
#define SPI_3WIRE (1<<6) #define SPI_3WIRE (1 << 6)
#define SPI_READY (1<<7) #define SPI_READY (1 << 7)
struct SpiDataStandard struct SpiDataStandard
{ {
@ -83,9 +83,10 @@ struct SpiDmaParam
struct SpiSlaveParam struct SpiSlaveParam
{ {
uint8 spi_slave_id; uint32 spi_slave_id;
uint8 spi_cs_gpio_pin; uint32 spi_cs_gpio_pin;
uint8 spi_cs_select_id; uint32 spi_cs_gpio_port;
uint32 spi_cs_select_id;
}; };
typedef struct typedef struct