From 6b091797aee0369f7aa51918d33fb0a2572f32e3 Mon Sep 17 00:00:00 2001 From: Wang_Weigen Date: Fri, 30 Dec 2022 17:59:41 +0800 Subject: [PATCH] =?UTF-8?q?1=E3=80=81add=20'menuconfig'=20function=20for?= =?UTF-8?q?=20XiZi=5FAIoT=20with=20imx6q-sabrelite=20board;2=E3=80=81add?= =?UTF-8?q?=20compilation=20function=20for=20AIoT=20system=20with=20imx6q-?= =?UTF-8?q?sabrelite=20board;3=E3=80=81add=20newlib=20base=20files;4?= =?UTF-8?q?=E3=80=81add=20startup=20files=20and=20irq=20function=20for=20i?= =?UTF-8?q?mx6q-sabrelite?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Ubiquitous/XiZi_AIoT/Kconfig | 6 + Ubiquitous/XiZi_AIoT/Makefile | 144 ++++++++ Ubiquitous/XiZi_AIoT/compiler.mk | 127 +++++++ Ubiquitous/XiZi_AIoT/hardkernel/Makefile | 3 + .../XiZi_AIoT/hardkernel/abstraction/Makefile | 3 + .../hardkernel/abstraction/interrupt.c | 45 --- .../XiZi_AIoT/hardkernel/abstraction/isr.c | 215 ++++++++++++ .../XiZi_AIoT/hardkernel/abstraction/isr.h | 98 ++++++ Ubiquitous/XiZi_AIoT/hardkernel/arch/Kconfig | 13 + Ubiquitous/XiZi_AIoT/hardkernel/arch/Makefile | 3 + .../XiZi_AIoT/hardkernel/arch/arm/Makefile | 4 + .../hardkernel/arch/arm/armv7-a/Makefile | 8 + .../arch/arm/armv7-a/cortex-a9/Makefile | 3 + .../arm/armv7-a/cortex-a9/arch_interrupt.h | 46 +++ .../arch/arm/armv7-a/cortex-a9/boot.S | 37 +- .../arch/arm/armv7-a/cortex-a9/cortexA9.S | 327 ++++++++++++++++++ .../arch/arm/armv7-a/cortex-a9/cortex_a9.h | 230 ++++++++++++ .../arch/arm/armv7-a/cortex-a9/exception.S | 82 +++-- .../arch/arm/armv7-a/cortex-a9/exception.c | 75 ---- .../arch/arm/armv7-a/cortex-a9/gic.c | 4 +- .../arch/arm/armv7-a/cortex-a9/gic.h | 183 ++++++++++ .../arch/arm/armv7-a/cortex-a9/interrupt.c | 92 +++++ Ubiquitous/XiZi_AIoT/link.mk | 10 + Ubiquitous/XiZi_AIoT/path_kernel.mk | 51 +++ Ubiquitous/XiZi_AIoT/services/Kconfig | 4 + Ubiquitous/XiZi_AIoT/services/Makefile | 6 + Ubiquitous/XiZi_AIoT/services/boards/Makefile | 4 + .../services/boards/imx6q-sabrelite/.config | 18 + .../services/boards/imx6q-sabrelite/Kconfig | 26 ++ .../services/boards/imx6q-sabrelite/Makefile | 8 + .../services/boards/imx6q-sabrelite/board.c | 4 + .../services/boards/imx6q-sabrelite/board.h | 6 + .../services/boards/imx6q-sabrelite/config.mk | 23 ++ .../imx6q-sabrelite/include/asm_defines.h | 94 +++++ .../imx6q-sabrelite/include/sdk_types.h | 125 +++++++ .../services/boards/imx6q-sabrelite/link.lds | 96 +++++ .../third_party_driver/Kconfig} | 0 .../third_party_driver/Makefile | 4 + .../boards/imx6q-sabrelite/xsconfig.h | 18 + Ubiquitous/XiZi_AIoT/services/drivers/Kconfig | 0 .../XiZi_AIoT/services/drivers/Makefile | 4 + Ubiquitous/XiZi_AIoT/services/fs/Kconfig | 0 Ubiquitous/XiZi_AIoT/services/lib/Kconfig | 23 ++ Ubiquitous/XiZi_AIoT/services/lib/Makefile | 14 + .../XiZi_AIoT/services/lib/newlib/Kconfig | 6 + .../XiZi_AIoT/services/lib/newlib/Makefile | 5 + .../services/lib/newlib/fs_syscalls.c | 156 +++++++++ .../services/lib/newlib/include/libc.h | 29 ++ .../services/lib/newlib/mem_syscalls.c | 78 +++++ .../XiZi_AIoT/services/lib/newlib/stdio.c | 156 +++++++++ .../services/lib/newlib/task_syscalls.c | 44 +++ .../services/lib/newlib/time_syscalls.c | 42 +++ .../services/tools/hosttools/xsconfig.sh | 91 +++++ Ubiquitous/XiZi_AIoT/softkernel/Kconfig | 0 Ubiquitous/XiZi_AIoT/softkernel/Makefile | 4 + Ubiquitous/XiZi_AIoT/softkernel/task/Makefile | 3 + Ubiquitous/XiZi_AIoT/support/Kconfig | 0 Ubiquitous/XiZi_AIoT/support/Makefile | 4 + Ubiquitous/XiZi_AIoT/testing/Kconfig | 0 Ubiquitous/XiZi_AIoT/testing/Makefile | 4 + 60 files changed, 2726 insertions(+), 182 deletions(-) create mode 100644 Ubiquitous/XiZi_AIoT/compiler.mk create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/Makefile delete mode 100755 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/interrupt.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/Kconfig create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/arch_interrupt.h create mode 100755 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/cortexA9.S create mode 100755 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/cortex_a9.h delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/exception.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/gic.h create mode 100755 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/interrupt.c create mode 100644 Ubiquitous/XiZi_AIoT/link.mk create mode 100755 Ubiquitous/XiZi_AIoT/path_kernel.mk create mode 100644 Ubiquitous/XiZi_AIoT/services/Kconfig create mode 100644 Ubiquitous/XiZi_AIoT/services/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/.config create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Kconfig create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/board.c create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/board.h create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/config.mk create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/include/asm_defines.h create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/include/sdk_types.h create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/link.lds rename Ubiquitous/XiZi_AIoT/services/{lib/xxx.c => boards/imx6q-sabrelite/third_party_driver/Kconfig} (100%) create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/third_party_driver/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/xsconfig.h create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/Kconfig create mode 100644 Ubiquitous/XiZi_AIoT/services/drivers/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/services/fs/Kconfig create mode 100644 Ubiquitous/XiZi_AIoT/services/lib/Kconfig create mode 100644 Ubiquitous/XiZi_AIoT/services/lib/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/services/lib/newlib/Kconfig create mode 100644 Ubiquitous/XiZi_AIoT/services/lib/newlib/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/services/lib/newlib/fs_syscalls.c create mode 100644 Ubiquitous/XiZi_AIoT/services/lib/newlib/include/libc.h create mode 100644 Ubiquitous/XiZi_AIoT/services/lib/newlib/mem_syscalls.c create mode 100644 Ubiquitous/XiZi_AIoT/services/lib/newlib/stdio.c create mode 100644 Ubiquitous/XiZi_AIoT/services/lib/newlib/task_syscalls.c create mode 100644 Ubiquitous/XiZi_AIoT/services/lib/newlib/time_syscalls.c create mode 100755 Ubiquitous/XiZi_AIoT/services/tools/hosttools/xsconfig.sh create mode 100644 Ubiquitous/XiZi_AIoT/softkernel/Kconfig create mode 100644 Ubiquitous/XiZi_AIoT/softkernel/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/softkernel/task/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/support/Kconfig create mode 100644 Ubiquitous/XiZi_AIoT/support/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/testing/Kconfig create mode 100644 Ubiquitous/XiZi_AIoT/testing/Makefile diff --git a/Ubiquitous/XiZi_AIoT/Kconfig b/Ubiquitous/XiZi_AIoT/Kconfig index e69de29bb..41ca9e96c 100644 --- a/Ubiquitous/XiZi_AIoT/Kconfig +++ b/Ubiquitous/XiZi_AIoT/Kconfig @@ -0,0 +1,6 @@ + +source "$KERNEL_DIR/services/Kconfig" +source "$KERNEL_DIR/softkernel/Kconfig" +source "$KERNEL_DIR/support/Kconfig" +source "$KERNEL_DIR/testing/Kconfig" + diff --git a/Ubiquitous/XiZi_AIoT/Makefile b/Ubiquitous/XiZi_AIoT/Makefile index e69de29bb..dfe98fe0d 100755 --- a/Ubiquitous/XiZi_AIoT/Makefile +++ b/Ubiquitous/XiZi_AIoT/Makefile @@ -0,0 +1,144 @@ +MAKEFLAGS += --no-print-directory + +.PHONY:all clean distclean show_info menuconfig +.PHONY:COMPILE_APP COMPILE_KERNEL + +riscv_support := +arm_support += imx6q-sabrelite +emulator_support += +support := $(riscv_support) $(arm_support) $(emulator_support) +SRC_DIR := + +export BOARD ?=imx6q-sabrelite +# This is the environment variable for kconfig-mconf +export KCONFIG_CONFIG ?= .config + +ifeq ($(filter $(BOARD),$(support)),) +$(warning "You should choose board like this: make BOARD=imx6q-sabrelite") +$(warning "This is what we support:") +$(warning "RISCV EVB: $(riscv_support)") +$(warning "ARM EVB: $(arm_support)") +$(warning "EMULATORS: $(emulator_support)") +# $(warning "$(support)") +$(error "break" ) +endif + +export TARGET +export COMPILE_TYPE +export KERNEL_ROOT ?=$(strip $(shell pwd)) + +MAKEFILES =$(KERNEL_ROOT)/.config +-include $(KERNEL_ROOT)/.config + +export BSP_ROOT ?= $(KERNEL_ROOT)/services/boards/$(BOARD) +export UBIQUITOUS_ROOT ?= .. +include services/boards/$(BOARD)/config.mk +export BSP_BUILD_DIR := boards/$(BOARD) +export HOSTTOOLS_DIR ?= $(KERNEL_ROOT)/services/tools/hosttools +export CONFIG2H_EXE ?= $(HOSTTOOLS_DIR)/xsconfig.sh + +export CPPPATHS +export SRC_APP_DIR := ../../APP_Framework +export SRC_KERNEL_DIR := hardkernel services softkernel support testing +# export SRC_DIR:= $(SRC_APP_DIR) $(SRC_KERNEL_DIR) +export SRC_DIR:= $(SRC_KERNEL_DIR) +export LIBCC +export MUSL_DIR := $(KERNEL_ROOT)/services/lib/musllib + +PART:= + +all: +ifeq ($(CONFIG_COMPILER_APP)_$(CONFIG_COMPILER_KERNEL),y_) +PART += COMPILE_APP + +else ifeq ($(CONFIG_COMPILER_APP)_$(CONFIG_COMPILER_KERNEL),_y) +PART += COMPILE_KERNEL + +else ifeq ($(CONFIG_COMPILER_APP)_$(CONFIG_COMPILER_KERNEL),y_y) +PART := COMPILE_APP COMPILE_KERNEL + +else + +ifeq ($(CONFIG_LIB_MUSLLIB), y) +PART += COMPILE_MUSL +endif + +PART += COMPILE_ALL +endif + + +all: $(PART) + + +COMPILE_ALL: + @for dir in $(SRC_DIR);do \ + $(MAKE) -C $$dir; \ + done + @cp link.mk build/Makefile + @$(MAKE) -C build TARGET=XiZi-$(BOARD).elf LINK_FLAGS=LFLAGS + @rm build/Makefile build/make.obj + +COMPILE_MUSL: + @for dir in $(MUSL_DIR);do \ + $(MAKE) -C $$dir COMPILE_TYPE=$@ CONFIG_RESOURCES_LWIP=n; \ + done + @cp link_libc.mk build/Makefile + @$(MAKE) -C build TARGET=libmusl.a LINK_FLAGS=LFLAGS + @cp build/libmusl.a $(KERNEL_ROOT)/lib/musllib/libmusl.a + @rm build/Makefile build/make.obj + +COMPILE_KERNEL: + @for dir in $(SRC_KERNEL_DIR);do \ + $(MAKE) -C $$dir; \ + done + @cp link.mk build/Makefile + @$(MAKE) -C build COMPILE_TYPE="_kernel" TARGET=XiZi-$(BOARD)_kernel.elf LINK_FLAGS=LFLAGS + @rm build/Makefile build/make.obj + +COMPILE_APP: + @echo $(SRC_APP_DIR) + @for dir in $(SRC_APP_DIR);do \ + $(MAKE) -C $$dir USE_APP_INCLUDEPATH=y; \ + done + @cp link.mk build/Makefile + @$(MAKE) -C build COMPILE_TYPE="_app" TARGET=XiZi-$(BOARD)_app.elf LINK_FLAGS=APPLFLAGS + @rm build/Makefile build/make.obj + +show_info: + @echo "CONFIG_COMPILER_APP is :" $(CONFIG_COMPILER_APP) + @echo "CONFIG_COMPILER_KERNEL is :" $(CONFIG_COMPILER_KERNEL) + @echo "KERNELPATHS is :" $(KERNELPATHS) + @echo "TARGET is :" $(TARGET) + @echo "VPATH is :" $(VPATH) + @echo "BSP_ROOT is :" $(BSP_ROOT) + @echo "KERNEL_ROOT is :" $(KERNEL_ROOT) + @echo "CPPPATHS is :" $(CPPPATHS) + @echo "SRC_DIR is :" $(SRC_DIR) + @echo "BUILD_DIR is :" $(BUILD_DIR) + @echo "BSP_BUILD_DIR is :" $(BSP_BUILD_DIR) + @echo "OBJS is :" $(OBJS) + @for f in $(CPPPATHS); do \ + echo $$f; \ + done + +menuconfig: + @if [ -f "$(BSP_ROOT)/.config" ]; then \ + cp $(BSP_ROOT)/.config $(KERNEL_ROOT)/.config; \ + else if [ -f "$(BSP_ROOT)/.defconfig" ]; then \ + cp $(BSP_ROOT)/.defconfig $(KERNEL_ROOT)/.config ;\ + fi ;fi + @kconfig-mconf $(BSP_ROOT)/Kconfig + @$(CONFIG2H_EXE) .config + @cp $(KERNEL_ROOT)/.config $(BSP_ROOT)/.config + +clean: + @echo Clean target and build_dir + @rm -rf build + @rm -rf temp.txt + +distclean: + @echo Clean all configuration + @make clean + @rm -f .config* + @rm -f $(KERNEL_ROOT)/lib/musllib/libmusl.a + @rm -f $(KERNEL_ROOT)/board/*/.config diff --git a/Ubiquitous/XiZi_AIoT/compiler.mk b/Ubiquitous/XiZi_AIoT/compiler.mk new file mode 100644 index 000000000..f217a06b0 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/compiler.mk @@ -0,0 +1,127 @@ +ifeq ($(COMPILE_TYPE), COMPILE_MUSL) +SRC_DIR_TEMP := $(MUSL_DIR) +else ifeq ($(COMPILE_TYPE), COMPILE_LWIP) +SRC_DIR_TEMP := $(LWIP_DIR) +else +SRC_DIR_TEMP := $(SRC_DIR) +endif + +SRC_DIR := +MUSL_DIR := +LWIP_DIR := + +ifeq ($(USE_APP_INCLUDEPATH), y) + include $(KERNEL_ROOT)/path_app.mk +else + include $(KERNEL_ROOT)/path_kernel.mk +endif +export CPPPATHS := $(KERNELPATHS) + +CUR_DIR :=$(shell pwd) + +CFLAGS += $(CPPPATHS) +AFLAGS += $(CPPPATHS) +CXXFLAGS += $(CPPPATHS) + +CFLAGS += $(DEFINES) +AFLAGS += $(DEFINES) +CXXFLAGS += $(DEFINES) +BUILD_DIR := $(KERNEL_ROOT)/build +APP_DIR := Ubiquitous/XiZi + + +.PHONY:COMPILER +COMPILER: + @if [ "${SRC_DIR_TEMP}" != "" ]; then \ + for dir in $(SRC_DIR_TEMP);do \ + $(MAKE) -C $$dir; \ + done; \ + fi + @/bin/echo -n $(OBJS) " " >> $(KERNEL_ROOT)/build/make.obj + + +################################################ +define add_c_file +$(eval COBJ := $(1:%.c=%.o)) \ +$(eval COBJ := $(subst $(subst $(APP_DIR),,$(KERNEL_ROOT)),,$(COBJ))) \ +$(eval LOCALC := $(addprefix $(BUILD_DIR)/,$(COBJ))) \ +$(eval OBJS += $(LOCALC)) \ +$(if $(strip $(LOCALC)),$(eval $(LOCALC): $(1) + @if [ ! -d $$(@D) ]; then mkdir -p $$(@D); fi + @echo cc $$< + @/bin/echo -n $(dir $(LOCALC)) >>$(KERNEL_ROOT)/build/make.dep + @($(CROSS_COMPILE)gcc -MM $$(CFLAGS) -c $$<) >>$(KERNEL_ROOT)/build/make.dep + @$(CROSS_COMPILE)gcc $$(CFLAGS) -c $$< -o $$@)) +endef + +define add_cpp_file +$(eval COBJ := $(1:%.cpp=%.o)) \ +$(eval COBJ := $(subst $(subst $(APP_DIR),,$(KERNEL_ROOT)),,$(COBJ))) \ +$(eval LOCALCPP := $(addprefix $(BUILD_DIR)/,$(COBJ))) \ +$(eval OBJS += $(LOCALCPP)) \ +$(if $(strip $(LOCALCPP)),$(eval $(LOCALCPP): $(1) + @if [ ! -d $$(@D) ]; then mkdir -p $$(@D); fi + @echo cc $$< + @/bin/echo -n $(dir $(LOCALCPP)) >>$(KERNEL_ROOT)/build/make.dep + @$(CROSS_COMPILE)g++ -MM $$(CXXFLAGS) -c $$< >>$(KERNEL_ROOT)/build/make.dep + @$(CROSS_COMPILE)g++ $$(CXXFLAGS) -c $$< -o $$@)) +endef + +define add_cc_file +$(eval COBJ := $(1:%.cc=%.o)) \ +$(eval COBJ := $(subst $(subst $(APP_DIR),,$(KERNEL_ROOT)),,$(COBJ))) \ +$(eval LOCALCPP := $(addprefix $(BUILD_DIR)/,$(COBJ))) \ +$(eval OBJS += $(LOCALCPP)) \ +$(if $(strip $(LOCALCPP)),$(eval $(LOCALCPP): $(1) + @if [ ! -d $$(@D) ]; then mkdir -p $$(@D); fi + @echo cc $$< + @/bin/echo -n $(dir $(LOCALCPP)) >>$(KERNEL_ROOT)/build/make.dep + @$(CROSS_COMPILE)g++ -MM $$(CXXFLAGS) -c $$< >>$(KERNEL_ROOT)/build/make.dep + @$(CROSS_COMPILE)g++ $$(CXXFLAGS) -c $$< -o $$@)) +endef + +define add_S_file +$(eval SOBJ := $(1:%.S=%.o)) \ +$(eval SOBJ := $(subst $(subst $(APP_DIR),,$(KERNEL_ROOT)),,$(SOBJ))) \ +$(eval LOCALS := $(addprefix $(BUILD_DIR)/,$(SOBJ))) \ +$(eval OBJS += $(LOCALS)) \ +$(if $(strip $(LOCALS)),$(eval $(LOCALS): $(1) + @if [ ! -d $$(@D) ]; then mkdir -p $$(@D); fi + @echo cc $$< + @/bin/echo -n $(dir $(LOCALC)) >>$(KERNEL_ROOT)/build/make.dep + @$(CROSS_COMPILE)gcc -MM $$(CFLAGS) -c $$< >>$(KERNEL_ROOT)/build/make.dep + @$(CROSS_COMPILE)gcc $$(AFLAGS) -c $$< -o $$@)) +endef + +define add_a_file +$(eval SOBJ := $(1:%.a=%.a)) \ +$(eval SOBJ := $(subst $(subst $(APP_DIR),,$(KERNEL_ROOT)),,$(SOBJ))) \ +$(eval LOCALA := $(addprefix $(BUILD_DIR)/,$(SOBJ))) \ +$(eval OBJS += $(LOCALA)) \ +$(if $(strip $(LOCALA)),$(eval $(LOCALA): $(1) + @if [ ! -d $$(@D) ]; then mkdir -p $$(@D); fi + @echo cp $$< + @cp $$< $$@)) +endef + + +SRCS := $(strip $(filter %.c,$(SRC_FILES))) +$(if $(SRCS),$(foreach f,$(SRCS),$(call add_c_file,$(addprefix $(CUR_DIR)/,$(f))))) + +SRCS := $(strip $(filter %.cpp,$(SRC_FILES))) +$(if $(SRCS),$(foreach f,$(SRCS),$(call add_cpp_file,$(addprefix $(CUR_DIR)/,$(f))))) + +SRCS := $(strip $(filter %.cc,$(SRC_FILES))) +$(if $(SRCS),$(foreach f,$(SRCS),$(call add_cc_file,$(addprefix $(CUR_DIR)/,$(f))))) + +SRCS := $(strip $(filter %.S,$(SRC_FILES))) +$(if $(SRCS),$(foreach f,$(SRCS),$(call add_S_file,$(addprefix $(CUR_DIR)/,$(f))))) + +SRCS := $(strip $(filter %.a,$(SRC_FILES))) +$(if $(SRCS),$(foreach f,$(SRCS),$(call add_a_file,$(addprefix $(CUR_DIR)/,$(f))))) + +COMPILER:$(OBJS) + + + +-include $(KERNEL_ROOT)/build/make.dep diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/Makefile new file mode 100644 index 000000000..f4c927675 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/Makefile @@ -0,0 +1,3 @@ +SRC_DIR := arch abstraction + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/Makefile new file mode 100644 index 000000000..262587f99 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := cache.c isr.c mmu.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/interrupt.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/interrupt.c deleted file mode 100755 index 2d44ea94b..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/interrupt.c +++ /dev/null @@ -1,45 +0,0 @@ -extern void _svcall(uintptr_t* contex); - -x_base __attribute__((naked)) DisableLocalInterrupt() -{ - -} - -void __attribute__((naked)) EnableLocalInterrupt(x_base level) -{ - -} - -int32 ArchEnableHwIrq(uint32_t irq_num) -{ - - return EOK; -} - -int32 ArchDisableHwIrq(uint32_t irq_num) -{ - return EOK; -} - -extern void KTaskOsAssignAfterIrq(void *context); - -void IsrEntry() -{ - uint32_t ipsr; - - // __asm__ volatile("MRS %0, IPSR" : "=r"(ipsr)); - - isrManager.done->incCounter(); - isrManager.done->handleIrq(ipsr); - KTaskOsAssignAfterIrq(NONE); - isrManager.done->decCounter(); - -} - -uintptr_t *Svcall(unsigned int ipsr, uintptr_t* contex ) -{ -#ifdef TASK_ISOLATION - _svcall(contex); -#endif - return contex; -} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.c new file mode 100644 index 000000000..54804bfac --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.c @@ -0,0 +1,215 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: isr.c +* @brief: the general management of system isr +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ +#include +#include "isr.h" + +struct InterruptServiceRoutines isrManager = {0} ; + +#ifdef ARCH_SMP +extern int GetCpuId(void); +#endif +/** + * This functionwill get the isr nest level. + * + * @return isr nest level + */ +static uint16_t GetIsrCounter() +{ + uint16_t ret = 0; + +#ifdef ARCH_SMP + ret = isrManager.isr_count[GetCpuId()]; +#else + ret = isrManager.isr_count; +#endif + return ret; +} + +static void IncIsrCounter() +{ +#ifdef ARCH_SMP + isrManager.isr_count[GetCpuId()] ++ ; +#else + isrManager.isr_count ++; +#endif + return ; +} + +static void DecIsrCounter() +{ + +#ifdef ARCH_SMP + isrManager.isr_count[GetCpuId()] -- ; +#else + isrManager.isr_count --; +#endif + return ; +} + +bool IsInIsr() +{ +#ifdef ARCH_SMP + return ( isrManager.isr_count[GetCpuId()] != 0 ? TRUE : FALSE ) ; +#else + return ( isrManager.isr_count != 0 ? TRUE : FALSE ) ; +#endif + +} +/** + * This function will register a new irq. + * + * @param irq_num the number of the irq + * @param handler the callback of the interrupt + * @param arg param of thge callback + * + * @return 0 on success; -1 on failure + */ +static int32_t RegisterHwIrq(uint32_t irq_num, IsrHandlerType handler, void *arg) +{ + if (irq_num >= ARCH_MAX_IRQ_NUM ) + return -1; + + struct IrqDesc *desc = &isrManager.irq_table[irq_num]; + + desc->handler = handler; + desc->param = arg; + + return 0; +} +/** + * This function will free a irq. + * + * @param irq_num the number of the irq + * + * @return 0 on success; -1 on failure + */ +static int32_t FreeHwIrq(uint32_t irq_num) +{ + if (irq_num >= ARCH_MAX_IRQ_NUM ) + return -1; + + memset(&isrManager.irq_table[irq_num], 0, sizeof(struct IrqDesc)); + + return 0; +} + +/** + * This function will enable a irq. + * + * @param irq_num the number of the irq + * + * @return 0 on success; -1 on failure + */ +static int32_t EnableHwIrq(uint32_t irq_num) +{ + if (irq_num >= ARCH_MAX_IRQ_NUM ) + return -1; + + return ArchEnableHwIrq(irq_num); +} +/** + * This function will disable a irq. + * + * @param irq_num the number of the irq + * + * @return 0 on success; -1 on failure + */ + +static int32_t DisableHwIrq(uint32_t irq_num) +{ + if (irq_num >= ARCH_MAX_IRQ_NUM ) + return -1; + + return ArchDisableHwIrq(irq_num); +} + +/* called from arch-specific ISR wrapper */ +static void IsrCommon(uint32_t irq_num) +{ + struct IrqDesc *desc = &isrManager.irq_table[irq_num]; + + if (desc->handler == NULL) { + // SYS_KDEBUG_LOG(KDBG_IRQ, ("Spurious interrupt: IRQ No. %d\n", irq_num)); + while (1) {} + } + desc->handler(irq_num, desc->param); + +} + +static void SetIsrSwitchTrigerFlag() +{ + +#ifdef ARCH_SMP + isrManager.isr_switch_trigger_flag[GetCpuId()] = 1; +#else + isrManager.isr_switch_trigger_flag = 1; +#endif +} + +static void ClearIsrSwitchTrigerFlag() +{ + +#ifdef ARCH_SMP + isrManager.isr_switch_trigger_flag[GetCpuId()] = 0; +#else + isrManager.isr_switch_trigger_flag = 0; +#endif +} + +static uint8_t GetIsrSwitchTrigerFlag() +{ + +#ifdef ARCH_SMP + return isrManager.isr_switch_trigger_flag[GetCpuId()]; +#else + return isrManager.isr_switch_trigger_flag ; +#endif +} + +struct IsrDone isrDone = { + IsInIsr, + RegisterHwIrq , + FreeHwIrq, + EnableHwIrq, + DisableHwIrq, + IsrCommon, + GetIsrCounter, + IncIsrCounter, + DecIsrCounter, + GetIsrSwitchTrigerFlag, + SetIsrSwitchTrigerFlag, + ClearIsrSwitchTrigerFlag +}; + +void SysInitIsrManager() +{ + extern int __isrtbl_idx_start; + extern int __isrtbl_start; + extern int __isrtbl_end; + memset(&isrManager,0,sizeof(struct InterruptServiceRoutines)); + isrManager.done = &isrDone; + + uint32_t *index = (uint32_t *)&__isrtbl_idx_start; + struct IrqDesc *desc = (struct IrqDesc *)&__isrtbl_start; + + while (desc != (struct IrqDesc *)&__isrtbl_end) + isrManager.irq_table[*index++] = *desc++; +} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.h new file mode 100644 index 000000000..edd939952 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.h @@ -0,0 +1,98 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: isr.h +* @brief: function declaration and structure defintion of isr +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/10 +* +*/ + +#ifndef __ISR_H__ +#define __ISR_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#define DECLARE_HW_IRQ(_irq_num, _handler, _arg) \ + const uint32_t __irq_desc_idx_##_handler SECTION(".isrtbl.idx") = _irq_num + ARCH_IRQ_NUM_OFFSET ; \ + const struct IrqDesc __irq_desc_##_handler SECTION(".isrtbl") = { \ + .handler = _handler, \ + .param = _arg, \ + } + +typedef void (*IsrHandlerType)(int vector, void *param); + +struct IrqDesc +{ + IsrHandlerType handler; + void *param; + +#ifdef CONFIG_INTERRUPT_INFO + char name[NAME_NUM_MAX]; + uint32_t counter; +#endif +}; + +struct IsrDone +{ + bool (*isInIsr)(); + int32_t (*registerIrq)(uint32_t irq_num, IsrHandlerType handler, void *arg); + int32_t (*freeIrq)(uint32_t irq_num); + int32_t (*enableIrq)(uint32_t irq_num); + int32_t (*disableIrq)(uint32_t irq_num); + void (*handleIrq)(uint32_t irq_num); + uint16_t (*getCounter)() ; + void (*incCounter)(); + void (*decCounter)(); + uint8_t (*getSwitchTrigerFlag)(); + void (*setSwitchTrigerFlag)(); + void (*clearSwitchTrigerFlag)(); +}; + +struct InterruptServiceRoutines { + +#ifdef ARCH_SMP + volatile uint16_t isr_count[CPU_NUMBERS]; + volatile uint8_t isr_switch_trigger_flag[CPU_NUMBERS]; +#else + volatile uint16_t isr_count ; + volatile uint8_t isr_switch_trigger_flag; +#endif + struct IrqDesc irq_table[ARCH_MAX_IRQ_NUM]; + struct IsrDone *done; +}; + +extern struct InterruptServiceRoutines isrManager ; + +unsigned long DisableLocalInterrupt(); +void EnableLocalInterrupt(unsigned long level); + +#define DISABLE_INTERRUPT DisableLocalInterrupt +#define ENABLE_INTERRUPT EnableLocalInterrupt + +void SysInitIsrManager(); +void InitHwinterrupt(void); + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/Kconfig b/Ubiquitous/XiZi_AIoT/hardkernel/arch/Kconfig new file mode 100644 index 000000000..42e27ec53 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/Kconfig @@ -0,0 +1,13 @@ +config ARCH_CPU_64BIT + bool + +config ARCH_RISCV + bool + +config ARCH_ARM + bool + +config ARCH_RISCV64 + select ARCH_RISCV + select ARCH_CPU_64BIT + bool \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/Makefile new file mode 100644 index 000000000..f629b85ec --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/Makefile @@ -0,0 +1,3 @@ +SRC_DIR := $(ARCH) + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/Makefile new file mode 100644 index 000000000..c064ef38b --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/Makefile @@ -0,0 +1,4 @@ +# The following three platforms support compatiable instructions. +SRC_DIR := $(ARCH_ARMV) + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/Makefile new file mode 100644 index 000000000..ed2a80a34 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/Makefile @@ -0,0 +1,8 @@ +# The following three platforms support compatiable instructions. + +ifeq ($(CONFIG_BOARD_IMX6Q_SABRELITE_EVB),y) +SRC_DIR := cortex-a9 +endif + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/Makefile new file mode 100644 index 000000000..7fc4ffac4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := boot.S cache.S exception.S cortexA9.S gic.c interrupt.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/arch_interrupt.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/arch_interrupt.h new file mode 100644 index 000000000..95233993c --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/arch_interrupt.h @@ -0,0 +1,46 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef ARCH_INTERRUPT_H__ +#define ARCH_INTERRUPT_H__ + +#include +#include +#include "gic.h" + +#define ARCH_MAX_IRQ_NUM PLATFORM_MAX_IRQ_NR + +int32_t ArchEnableHwIrq(uint32_t irq_num); +int32_t ArchDisableHwIrq(uint32_t irq_num); + +struct ExceptionStackRegister +{ + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t r12; + uint32_t r13_sp; + uint32_t r14_lr; + uint32_t r15_pc; + uint32_t cpsr; +}; + +#endif diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/boot.S index 3731ef6b8..a10b5ef7a 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/boot.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/boot.S @@ -1,20 +1,21 @@ -.equ Mode_USR, 0x10 -.equ Mode_FIQ, 0x11 -.equ Mode_IRQ, 0x12 -.equ Mode_SVC, 0x13 -.equ Mode_ABT, 0x17 -.equ Mode_UND, 0x1B -.equ Mode_SYS, 0x1F +@ .equ Mode_USR, 0x10 +@ .equ Mode_FIQ, 0x11 +@ .equ Mode_IRQ, 0x12 +@ .equ Mode_SVC, 0x13 +@ .equ Mode_ABT, 0x17 +@ .equ Mode_UND, 0x1B +@ .equ Mode_SYS, 0x1F +#include -.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled -.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled +@ .equ I_BIT, 0x80 @ when I bit is set, IRQ is disabled +@ .equ F_BIT, 0x40 @ when F bit is set, FIQ is disabled .equ STACK_SIZE, 0x00000100 -.globl _start +.globl _reset -_start: +_reset: /* set the cpu to SVC32 mode and disable interrupt */ mrs r0, cpsr @@ -36,32 +37,32 @@ _start: mov sp, r0 @ Enter Undefined Instruction Mode and set its Stack Pointer - msr cpsr_c, #Mode_UND|I_Bit|F_Bit + msr cpsr_c, #MODE_UND|I_BIT|F_BIT mov sp, r0 sub r0, r0, #STACK_SIZE @ Enter Abort Mode and set its Stack Pointer - msr cpsr_c, #Mode_ABT|I_Bit|F_Bit + msr cpsr_c, #MODE_ABT|I_BIT|F_BIT mov sp, r0 sub r0, r0, #STACK_SIZE @ Enter FIQ Mode and set its Stack Pointer - msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit + msr cpsr_c, #MODE_FIQ|I_BIT|F_BIT mov sp, r0 sub r0, r0, #STACK_SIZE @ Enter IRQ Mode and set its Stack Pointer - msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit + msr cpsr_c, #MODE_IRQ|I_BIT|F_BIT mov sp, r0 sub r0, r0, #STACK_SIZE /* come back to SVC mode */ - msr cpsr_c, #Mode_SVC|I_Bit|F_Bit + msr cpsr_c, #MODE_SVC|I_BIT|F_BIT /* clear .bss */ mov r0, #0 /* get a zero */ - ldr r1,=BSS_START /* bss start */ - ldr r2,=BSS_END /* bss end */ + ldr r1,=__bss_start /* bss start */ + ldr r2,=__bss_end /* bss end */ bss_loop: cmp r1,r2 /* check if data to clear */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/cortexA9.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/cortexA9.S new file mode 100755 index 000000000..ce34242fc --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/cortexA9.S @@ -0,0 +1,327 @@ +/* + * Copyright (c) 2010-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * @file cortexA9.s + * @brief This file contains cortexA9 functions + * + */ + + .code 32 + .section ".text","ax" + +/* + * bool arm_set_interrupt_state(bool enable) + */ + .global arm_set_interrupt_state + .func arm_set_interrupt_state +arm_set_interrupt_state: + mrs r2,CPSR @ read CPSR (Current Program Status Register) + teq r0,#0 + bicne r1,r2,#0xc0 @ disable IRQ and FIQ + orreq r1,r2,#0xc0 @ enable IRQ and FIQ + msr CPSR_c,r1 + tst r2,#0x80 + movne r0,#0 + moveq r0,#1 + bx lr + .endfunc + + .global cpu_get_current + @ int cpu_get_current(void)@ + @ get current CPU ID + .func cpu_get_current +cpu_get_current: + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #3 + BX lr + .endfunc @cpu_get_current()@ + + .global enable_neon_fpu + .func enable_neon_fpu +enable_neon_fpu: + /* set NSACR, both Secure and Non-secure access are allowed to NEON */ + MRC p15, 0, r0, c1, c1, 2 + ORR r0, r0, #(0x3<<10) @ enable fpu/neon + MCR p15, 0, r0, c1, c1, 2 + /* Set the CPACR for access to CP10 and CP11*/ + LDR r0, =0xF00000 + MCR p15, 0, r0, c1, c0, 2 + /* Set the FPEXC EN bit to enable the FPU */ + MOV r3, #0x40000000 + @VMSR FPEXC, r3 + MCR p10, 7, r3, c8, c0, 0 + .endfunc + + .global disable_strict_align_check + .func disable_strict_align_check +disable_strict_align_check: + /*Ray's note: disable strict alignment fault checking. + without disabling this, data abort will happen when accessing + the BPB structure of file system since it is packed.*/ + + push {r0, lr} + + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #(0x1<<1) @clear A bit of SCTLR + mcr p15, 0, r0, c1, c0, 0 + + pop {r0, pc} + .endfunc + + .global disable_L1_cache + .func disable_L1_cache +disable_L1_cache: + push {r0-r6, lr} + + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #(0x1<<12) + bic r0, r0, #(0x1<<11) + bic r0, r0, #(0x1<<2) + bic r0, r0, #(0x1<<0) + mcr p15, 0, r0, c1, c0, 0 + + pop {r0-r6, pc} + + .endfunc + + .global get_arm_private_peripheral_base + @ uint32_t get_arm_private_peripheral_base(void)@ + .func get_arm_private_peripheral_base +get_arm_private_peripheral_base: + + @ Get base address of private perpherial space + mrc p15, 4, r0, c15, c0, 0 @ Read periph base address + bx lr + + .endfunc @get_arm_private_peripheral_base()@ + +@ ------------------------------------------------------------ +@ TLB +@ ------------------------------------------------------------ + + .global arm_unified_tlb_invalidate + @ void arm_unified_tlb_invalidate(void)@ + .func arm_unified_tlb_invalidate +arm_unified_tlb_invalidate: + mov r0, #1 + mcr p15, 0, r0, c8, c7, 0 @ TLBIALL - Invalidate entire unified TLB + dsb + bx lr + .endfunc + + .global arm_unified_tlb_invalidate_is + @ void arm_unified_tlb_invalidate_is(void)@ + .func arm_unified_tlb_invalidate_is +arm_unified_tlb_invalidate_is: + mov r0, #1 + mcr p15, 0, r0, c8, c3, 0 @ TLBIALLIS - Invalidate entire unified TLB Inner Shareable + dsb + bx lr + .endfunc + +@ ------------------------------------------------------------ +@ Branch Prediction +@ ------------------------------------------------------------ + + .global arm_branch_prediction_enable + @ void arm_branch_prediction_enable(void) + .func arm_branch_prediction_enable +arm_branch_prediction_enable: + mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR + orr r0, r0, #(1 << 11) @ Set the Z bit (bit 11) + mcr p15, 0,r0, c1, c0, 0 @ Write SCTLR + bx lr + .endfunc + + .global arm_branch_prediction_disable + @ void arm_branch_prediction_disable(void) + .func arm_branch_prediction_disable +arm_branch_prediction_disable: + mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR + bic r0, r0, #(1 << 11) @ Clear the Z bit (bit 11) + mcr p15, 0,r0, c1, c0, 0 @ Write SCTLR + bx lr + .endfunc + + .global arm_branch_target_cache_invalidate + @ void arm_branch_target_cache_invalidate(void) + .func arm_branch_target_cache_invalidate +arm_branch_target_cache_invalidate: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 6 @ BPIALL - Invalidate entire branch predictor array + bx lr + .endfunc + + .global arm_branch_target_cache_invalidate_is + @ void arm_branch_target_cache_invalidate_is(void) + .func arm_branch_target_cache_invalidate_is +arm_branch_target_cache_invalidate_is: + mov r0, #0 + mcr p15, 0, r0, c7, c1, 6 @ BPIALLIS - Invalidate entire branch predictor array Inner Shareable + bx lr + .endfunc + +@ ------------------------------------------------------------ +@ SCU +@ ------------------------------------------------------------ + + @ SCU offset from base of private peripheral space --> 0x000 + + .global scu_enable + @ void scu_enable(void) + @ Enables the SCU + .func scu_enable +scu_enable: + + mrc p15, 4, r0, c15, c0, 0 @ Read periph base address + + ldr r1, [r0, #0x0] @ Read the SCU Control Register + orr r1, r1, #0x1 @ Set bit 0 (The Enable bit) + str r1, [r0, #0x0] @ Write back modifed value + + bx lr + .endfunc + +@ ------------------------------------------------------------ + + .global scu_join_smp + @ void scu_join_smp(void) + @ Set this CPU as participating in SMP + .func scu_join_smp +scu_join_smp: + + @ SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg + + mrc p15, 0, r0, c1, c0, 1 @ Read ACTLR + orr r0, r0, #0x040 @ Set bit 6 + mcr p15, 0, r0, c1, c0, 1 @ Write ACTLR + + bx lr + .endfunc + +@ ------------------------------------------------------------ + + .global scu_leave_smp + @ void scu_leave_smp(void) + @ Set this CPU as NOT participating in SMP + .func scu_leave_smp +scu_leave_smp: + + @ SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg + + mrc p15, 0, r0, c1, c0, 1 @ Read ACTLR + bic r0, r0, #0x040 @ Clear bit 6 + mcr p15, 0, r0, c1, c0, 1 @ Write ACTLR + + bx lr + .endfunc + +@ ------------------------------------------------------------ + + .global scu_get_cpus_in_smp + @ unsigned int scu_get_cpus_in_smp(void) + @ The return value is 1 bit per core: + @ bit 0 - CPU 0 + @ bit 1 - CPU 1 + @ etc... + .func scu_get_cpus_in_smp +scu_get_cpus_in_smp: + + mrc p15, 4, r0, c15, c0, 0 @ Read periph base address + + ldr r0, [r0, #0x004] @ Read SCU Configuration register + mov r0, r0, lsr #4 @ Bits 7:4 gives the cores in SMP mode, shift then mask + and r0, r0, #0x0F + + bx lr + .endfunc + +@ ------------------------------------------------------------ + + .global scu_enable_maintenance_broadcast + @ void scu_enable_maintenance_broadcast(void) + @ Enable the broadcasting of cache & TLB maintenance operations + @ When enabled AND in SMP, broadcast all "inner sharable" + @ cache and TLM maintenance operations to other SMP cores + .func scu_enable_maintenance_broadcast +scu_enable_maintenance_broadcast: + mrc p15, 0, r0, c1, c0, 1 @ Read Aux Ctrl register + orr r0, r0, #0x01 @ Set the FW bit (bit 0) + mcr p15, 0, r0, c1, c0, 1 @ Write Aux Ctrl register + + bx lr + .endfunc + +@ ------------------------------------------------------------ + + .global scu_disable_maintenance_broadcast + @ void scu_disable_maintenance_broadcast(void) + @ Disable the broadcasting of cache & TLB maintenance operations + .func scu_disable_maintenance_broadcast +scu_disable_maintenance_broadcast: + mrc p15, 0, r0, c1, c0, 1 @ Read Aux Ctrl register + bic r0, r0, #0x01 @ Clear the FW bit (bit 0) + mcr p15, 0, r0, c1, c0, 1 @ Write Aux Ctrl register + + bx lr + .endfunc + +@ ------------------------------------------------------------ + + .global scu_secure_invalidate + @ void scu_secure_invalidate(unsigned int cpu, unsigned int ways) + @ cpu: 0x0=CPU 0 0x1=CPU 1 etc... + @ This function invalidates the SCU copy of the tag rams + @ for the specified core. typically only done at start-up. + @ Possible flow: + @ - Invalidate L1 caches + @ - Invalidate SCU copy of TAG RAMs + @ - Join SMP + .func scu_secure_invalidate +scu_secure_invalidate: + and r0, r0, #0x03 @ Mask off unused bits of CPU ID + mov r0, r0, lsl #2 @ Convert into bit offset (four bits per core) + + and r1, r1, #0x0F @ Mask off unused bits of ways + mov r1, r1, lsl r0 @ Shift ways into the correct CPU field + + mrc p15, 4, r2, c15, c0, 0 @ Read periph base address + + str r1, [r2, #0x0C] @ Write to SCU Invalidate All in Secure State + + bx lr + + .endfunc + +@ ------------------------------------------------------------ +@ End of cortexA9.s +@ ------------------------------------------------------------ + .end diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/cortex_a9.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/cortex_a9.h new file mode 100755 index 000000000..c445e4fb4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/cortex_a9.h @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__CORTEX_A9_H__) +#define __CORTEX_A9_H__ + +#include +#include +#include + +//! @addtogroup cortexa9 +//! @{ + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @name Instruction macros +//@{ +#define _ARM_NOP() asm volatile ("nop\n\t") +#define _ARM_WFI() asm volatile ("wfi\n\t") +#define _ARM_WFE() asm volatile ("wfe\n\t") +#define _ARM_SEV() asm volatile ("sev\n\t") +#define _ARM_DSB() asm volatile ("dsb\n\t") +#define _ARM_ISB() asm volatile ("isb\n\t") + +#define _ARM_MRC(coproc, opcode1, Rt, CRn, CRm, opcode2) \ + asm volatile ("mrc p" #coproc ", " #opcode1 ", %[output], c" #CRn ", c" #CRm ", " #opcode2 "\n" : [output] "=r" (Rt)) + +#define _ARM_MCR(coproc, opcode1, Rt, CRn, CRm, opcode2) \ + asm volatile ("mcr p" #coproc ", " #opcode1 ", %[input], c" #CRn ", c" #CRm ", " #opcode2 "\n" :: [input] "r" (Rt)) +//@} + +//////////////////////////////////////////////////////////////////////////////// +// Code +//////////////////////////////////////////////////////////////////////////////// + +#if defined(__cplusplus) +extern "C" { +#endif + +//! @name Misc +//@{ +//! @brief Enable or disable the IRQ and FIQ state. +bool arm_set_interrupt_state(bool enable); + +//! @brief Get current CPU ID. +int cpu_get_current(void); + +//! @brief Enable the NEON MPE. +void enable_neon_fpu(void); + +//! @brief Disable aborts on unaligned accesses. +void disable_strict_align_check(void); + +//! @brief Get base address of private perpherial space. +//! +//! @return The address of the ARM CPU's private peripherals. +uint32_t get_arm_private_peripheral_base(void); +//@} + + +//! @name Data cache operations +//@{ + +//! @brief Check if dcache is enabled or disabled. +int arm_dcache_state_query(); + +//! @brief Enables data cache at any available cache level. +//! +//! Works only if MMU is enabled! +void arm_dcache_enable(); + +//! @brief Disables the data cache at any available cache level. +void arm_dcache_disable(); + +//! @brief Invalidates the entire data cache. +void arm_dcache_invalidate(); + +//! @brief Invalidate a line of data cache. +void arm_dcache_invalidate_line(const void * addr); + +//! @brief Invalidate a number of lines of data cache. +//! +//! Number of lines depends on length parameter and size of line. +//! Size of line for A9 L1 cache is 32B. +void arm_dcache_invalidate_mlines(const void * addr, size_t length); + +//! @brief Flush (clean) all lines of cache (all sets in all ways). +void arm_dcache_flush(); + +//! @brief Flush (clean) one line of cache. +void arm_dcache_flush_line(const void * addr); + +// @brief Flush (clean) multiple lines of cache. +//! +//! Number of lines depends on length parameter and size of line. +void arm_dcache_flush_mlines(const void * addr, size_t length); +//@} + +//! @name Instrution cache operations +//@{ + +//! @brief Check if icache is enabled or disabled. +int arm_icache_state_query(); + +//! @brief Enables instruction cache at any available cache level. +//! +//! Works without enabled MMU too! +void arm_icache_enable(); + +//! @brief Disables the instruction cache at any available cache level. +void arm_icache_disable(); + +//! @brief Invalidates the entire instruction cache. +void arm_icache_invalidate(); + +//! @brief Invalidates the entire instruction cache inner shareable. +void arm_icache_invalidate_is(); + +//! @brief Invalidate a line of the instruction cache. +void arm_icache_invalidate_line(const void * addr); + +//! @brief Invalidate a number of lines of instruction cache. +//! +//! Number of lines depends on length parameter and size of line. +void arm_icache_invalidate_mlines(const void * addr, size_t length); +//@} + +//! @name TLB operations +//@{ +//! @brief Invalidate entire unified TLB. +void arm_unified_tlb_invalidate(void); + +//! @brief Invalidate entire unified TLB Inner Shareable. +void arm_unified_tlb_invalidate_is(void); +//@} + +//! @name Branch predictor operations +//@{ +//! @brief Enable branch prediction. +void arm_branch_prediction_enable(void); + +//! @brief Disable branch prediction. +void arm_branch_prediction_disable(void); + +//! @brief Invalidate entire branch predictor array. +void arm_branch_target_cache_invalidate(void); + +//! @brief Invalidate entire branch predictor array Inner Shareable +void arm_branch_target_cache_invalidate_is(void); +//@} + +//! @name SCU +//@{ +//! @brief Enables the SCU. +void scu_enable(void); + +//! @brief Set this CPU as participating in SMP. +void scu_join_smp(void); + +//! @brief Set this CPU as not participating in SMP. +void scu_leave_smp(void); + +//! @brief Determine which CPUs are participating in SMP. +//! +//! The return value is 1 bit per core: +//! - bit 0 - CPU 0 +//! - bit 1 - CPU 1 +//! - etc... +unsigned int scu_get_cpus_in_smp(void); + +//! @brief Enable the broadcasting of cache & TLB maintenance operations. +//! +//! When enabled AND in SMP, broadcast all "inner sharable" +//! cache and TLM maintenance operations to other SMP cores +void scu_enable_maintenance_broadcast(void); + +//! @brief Disable the broadcasting of cache & TLB maintenance operations. +void scu_disable_maintenance_broadcast(void); + +//! @brief Invalidates the SCU copy of the tag rams for the specified core. +//! +//! Typically only done at start-up. +//! Possible flow: +//! - Invalidate L1 caches +//! - Invalidate SCU copy of TAG RAMs +//! - Join SMP +//! +//! @param cpu 0x0=CPU 0, 0x1=CPU 1, etc... +//! @param ways The ways to invalidate. Pass 0xf to invalidate all ways. +void scu_secure_invalidate(unsigned int cpu, unsigned int ways); +//@} + +#if defined(__cplusplus) +} +#endif + +//! @} + +#endif // __CORTEX_A9_H__ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/exception.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/exception.S index dc3eb6e2d..e8ee24286 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/exception.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/exception.S @@ -1,3 +1,5 @@ +#include + .section .vectors, "ax" .code 32 @@ -12,7 +14,7 @@ ExceptionVectors: ldr pc, _IrqException ldr pc, _FiqException -.globl _start +.globl _reset .globl UndefInstrExceptionHandle .globl SwiExceptionHandle .globl PrefetchAbortExceptionHandle @@ -22,7 +24,7 @@ ExceptionVectors: .globl FiqExceptionHandle _ResetException: - .word _start + .word _reset _UndefInstrException: .word UndefInstrExceptionHandle _SwiException: @@ -48,7 +50,7 @@ _FiqException: mrs r6, spsr @/* Save CPSR */ str lr, [r0, #15*4] @/* Push PC */ str r6, [r0, #16*4] @/* Push CPSR */ - cps #Mode_SVC + cps #MODE_SVC str sp, [r0, #13*4] @/* Save calling SP */ str lr, [r0, #14*4] @/* Save calling PC */ .endm @@ -63,7 +65,7 @@ UndefInstrExceptionHandle: .globl SwiExceptionHandle SwiExceptionHandle: push_svc_reg - bl rt_hw_trap_swi + bl DoSvcCallProcess b . .align 5 @@ -89,55 +91,51 @@ ResvExceptionHandle: .globl ExceptionIsrEntry ExceptionIsrEntry: - stmfd sp!, {r0-r12,lr} + stmfd sp!, {r0-r12,lr} - bl rt_interrupt_enter - bl rt_hw_trap_irq - bl rt_interrupt_leave + bl DoIrqProcess - @ if rt_thread_switch_interrupt_flag set, jump to - @ rt_hw_context_switch_interrupt_do and don't return - ldr r0, =rt_thread_switch_interrupt_flag - ldr r1, [r0] - cmp r1, #1 - beq rt_hw_context_switch_interrupt_do + @ ldr r0, =rt_thread_switch_interrupt_flag + @ ldr r1, [r0] + @ cmp r1, #1 + @ beq rt_hw_context_switch_interrupt_do - ldmfd sp!, {r0-r12,lr} - subs pc, lr, #4 + ldmfd sp!, {r0-r12,lr} + subs pc, lr, #4 -rt_hw_context_switch_interrupt_do: - mov r1, #0 @ clear flag - str r1, [r0] +@ rt_hw_context_switch_interrupt_do: +@ mov r1, #0 @ clear flag +@ str r1, [r0] - mov r1, sp @ r1 point to {r0-r3} in stack - add sp, sp, #4*4 - ldmfd sp!, {r4-r12,lr}@ reload saved registers - mrs r0, spsr @ get cpsr of interrupt thread - sub r2, lr, #4 @ save old task's pc to r2 +@ mov r1, sp @ r1 point to {r0-r3} in stack +@ add sp, sp, #4*4 +@ ldmfd sp!, {r4-r12,lr}@ reload saved registers +@ mrs r0, spsr @ get cpsr of interrupt thread +@ sub r2, lr, #4 @ save old task's pc to r2 - @ Switch to SVC mode with no interrupt. If the usr mode guest is - @ interrupted, this will just switch to the stack of kernel space. - @ save the registers in kernel space won't trigger data abort. - msr cpsr_c, #I_Bit|F_Bit|Mode_SVC +@ @ Switch to SVC mode with no interrupt. If the usr mode guest is +@ @ interrupted, this will just switch to the stack of kernel space. +@ @ save the registers in kernel space won't trigger data abort. +@ msr cpsr_c, #I_Bit|F_Bit|Mode_SVC - stmfd sp!, {r2} @ push old task's pc - stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 - ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread - stmfd sp!, {r1-r4} @ push old task's r0-r3 - stmfd sp!, {r0} @ push old task's cpsr +@ stmfd sp!, {r2} @ push old task's pc +@ stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 +@ ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread +@ stmfd sp!, {r1-r4} @ push old task's r0-r3 +@ stmfd sp!, {r0} @ push old task's cpsr - ldr r4, =rt_interrupt_from_thread - ldr r5, [r4] - str sp, [r5] @ store sp in preempted tasks's TCB +@ ldr r4, =rt_interrupt_from_thread +@ ldr r5, [r4] +@ str sp, [r5] @ store sp in preempted tasks's TCB - ldr r6, =rt_interrupt_to_thread - ldr r6, [r6] - ldr sp, [r6] @ get new task's stack pointer +@ ldr r6, =rt_interrupt_to_thread +@ ldr r6, [r6] +@ ldr sp, [r6] @ get new task's stack pointer - ldmfd sp!, {r4} @ pop new task's cpsr to spsr - msr spsr_cxsf, r4 +@ ldmfd sp!, {r4} @ pop new task's cpsr to spsr +@ msr spsr_cxsf, r4 - ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr +@ ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr .align 5 diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/exception.c b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/exception.c deleted file mode 100644 index de9a52e32..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/exception.c +++ /dev/null @@ -1,75 +0,0 @@ - -/** - * this function will show registers of CPU - * - * @param regs the registers point - */ -void PrintStackFrame(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); -} - - -/** - * The software interrupt instruction (SWI) is used for entering - * Supervisor mode, usually to request a particular supervisor - * function. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) -{ - -} - -void rt_hw_trap_irq(void) -{ - void *param; - rt_isr_handler_t isr_func; - extern struct rt_irq_desc isr_table[]; - - // vectNum = RESERVED[31:13] | CPUID[12:10] | INTERRUPT_ID[9:0] - // send ack and get ID source - uint32_t vectNum = gic_read_irq_ack(); - - // Check that INT_ID isn't 1023 or 1022 (spurious interrupt) - if (vectNum & 0x0200) - { - gic_write_end_of_irq(vectNum); // send end of irq - } - else - { - // copy the local value to the global image of CPUID - unsigned cpu = (vectNum >> 10) & 0x7; - unsigned irq = vectNum & 0x1FF; - - /* skip warning */ - cpu = cpu; - - // Call the service routine stored in the handlers array. If there isn't - // one for this IRQ, then call the default handler. - /* get interrupt service routine */ - isr_func = isr_table[irq].handler; -#ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; -#endif - if (isr_func) - { - /* Interrupt for myself. */ - param = isr_table[irq].param; - /* turn to interrupt service routine */ - isr_func(irq, param); - } - - // Signal the end of the irq. - gic_write_end_of_irq(vectNum); - } -} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/gic.c b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/gic.c index 5249d76e4..82b337331 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/gic.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/gic.c @@ -28,9 +28,9 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include -#include "core/gic.h" +#include "gic.h" #include "gic_registers.h" -#include "core/cortex_a9.h" +#include "cortex_a9.h" //////////////////////////////////////////////////////////////////////////////// // Prototypes diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/gic.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/gic.h new file mode 100644 index 000000000..f3eee8499 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/gic.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2011-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __GIC_H__ +#define __GIC_H__ + +#include "sdk_types.h" + +//! @addtogroup gic +//! @{ + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @brief Options for sending a software generated interrupt. +//! +//! These options are used for the @a filter_list parameter of the gic_send_sgi() +//! function. They control how to select which CPUs that the interrupt is +//! sent to. +enum _gicd_sgi_filter +{ + //! Forward the interrupt to the CPU interfaces specified in the @a target_list parameter. + kGicSgiFilter_UseTargetList = 0, + + //! Forward the interrupt to all CPU interfaces except that of the processor that requested + //! the interrupt. + kGicSgiFilter_AllOtherCPUs = 1, + + //! Forward the interrupt only to the CPU interface of the processor that requested the + //! interrupt. + kGicSgiFilter_OnlyThisCPU = 2 +}; + +//////////////////////////////////////////////////////////////////////////////// +// API +//////////////////////////////////////////////////////////////////////////////// + +#if defined(__cplusplus) +extern "C" { +#endif + +//! @name Initialization +//@{ +//! @brief Init interrupt handling. +//! +//! This function is intended to be called only by the primary CPU init code, so it will +//! only be called once during system bootup. +//! +//! Also inits the current CPU. You don't need to call gic_init_cpu() separately. +//! +//! @post The interrupt distributor and the current CPU interface are enabled. All interrupts +//! that were pending are cleared, and all interrupts are made secure (group 0). +void gic_init(void); + +//! @brief Init the current CPU's GIC interface. +//! +//! @post Enables the CPU interface and sets the priority mask to 255. Interrupt preemption +//! is disabled by setting the Binary Point to a value of 7. +void gic_init_cpu(void); +//@} + +//! @name GIC Interrupt Distributor Functions +//@{ +//! @brief Enable or disable the GIC Distributor. +//! +//! Enables or disables the GIC distributor passing both secure (group 0) and non-secure +//! (group 1) interrupts to the CPU interfaces. +//! +//! @param enableIt Pass true to enable or false to disable. +void gic_enable(bool enableIt); + +//! @brief Set the security mode for an interrupt. +//! +//! @param irqID The interrupt number. +//! @param isSecure Whether the interrupt is taken to secure mode. +void gic_set_irq_security(uint32_t irqID, bool isSecure); + +//! @brief Enable or disable an interrupt. +//! +//! @param irqID The number of the interrupt to control. +//! @param isEnabled Pass true to enable or false to disable. +void gic_enable_irq(uint32_t irqID, bool isEnabled); + +//! @brief Set whether a CPU will receive a particular interrupt. +//! +//! @param irqID The interrupt number. +//! @param cpuNumber The CPU number. The first CPU core is 0. +//! @param enableIt Whether to send the interrupt to the specified CPU. Pass true to enable +//! or false to disable. +void gic_set_cpu_target(uint32_t irqID, unsigned cpuNumber, bool enableIt); + +//! @brief Set an interrupt's priority. +//! +//! @param irq_id The interrupt number. +//! @param priority The priority for the interrupt. In the range of 0 through 0xff, with +//! 0 being the highest priority. +void gic_set_irq_priority(uint32_t irq_id, uint32_t priority); + +//! @brief Send a software generated interrupt to a specific CPU. +//! +//! @param irq_id The interrupt number to send. +//! @param target_list Each bit indicates a CPU to which the interrupt will be forwarded. +//! Bit 0 is CPU 0, bit 1 is CPU 1, and so on. If the value is 0, then the interrupt +//! will not be forwarded to any CPUs. This parameter is only used if @a filter_list +//! is set to #kGicSgiFilter_UseTargetList. +//! @param filter_list One of the enums of the #_gicd_sgi_filter enumeration. The selected +//! option determines which CPUs the interrupt will be sent to. If the value +//! is #kGicSgiFilter_UseTargetList, then the @a target_list parameter is used. +void gic_send_sgi(uint32_t irq_id, uint32_t target_list, uint32_t filter_list); +//@} + +//! @name GIC CPU Interface Functions +//@{ +//! @brief Enable or disable the interface to the GIC for the current CPU. +//! +//! @param enableIt Pass true to enable or false to disable. +void gic_cpu_enable(bool enableIt); + +//! @brief Set the mask of which interrupt priorities the CPU will receive. +//! +//! @param priority The lowest priority that will be passed to the current CPU. Pass 0xff to +//! allow all priority interrupts to signal the CPU. +void gic_set_cpu_priority_mask(uint32_t priority); + +//! @brief Acknowledge starting of interrupt handling and get the interrupt number. +//! +//! Normally, this function is called at the beginning of the IRQ handler. It tells the GIC +//! that you are starting to handle an interupt, and returns the number of the interrupt you +//! need to handle. After the interrupt is handled, you should call gic_write_end_of_irq() +//! to signal that the interrupt is completely handled. +//! +//! In some cases, a spurious interrupt might happen. One possibility is if another CPU handles +//! the interrupt. When a spurious interrupt occurs, the end of the interrupt should be indicated +//! but nothing else. +//! +//! @return The number for the highest priority interrupt available for the calling CPU. If +//! the return value is 1022 or 1023, a spurious interrupt has occurred. +uint32_t gic_read_irq_ack(void); + +//! @brief Signal the end of handling an interrupt. +//! +//! @param irq_id The number of the interrupt for which handling has finished. +void gic_write_end_of_irq(uint32_t irq_id); +//@} + + +#if defined(__cplusplus) +} +#endif + +//! @} + +#endif // __GIC_H__ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/interrupt.c b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/interrupt.c new file mode 100755 index 000000000..635857aa8 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/interrupt.c @@ -0,0 +1,92 @@ +// extern void _svcall(uintptr_t* contex); +#include +#include +#include + +unsigned long __attribute__((naked)) DisableLocalInterrupt() +{ + +} + +void __attribute__((naked)) EnableLocalInterrupt(unsigned long level) +{ + +} + +int32_t ArchEnableHwIrq(uint32_t irq_num) +{ + + return 0; +} + +int32_t ArchDisableHwIrq(uint32_t irq_num) +{ + return 0; +} + +extern void KTaskOsAssignAfterIrq(void *context); + +void IsrEntry(uint32_t irq_num) +{ + isrManager.done->incCounter(); + isrManager.done->handleIrq(irq_num); + // KTaskOsAssignAfterIrq(NULL); + isrManager.done->decCounter(); + +} + +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void PrintStackFrame(struct ExceptionStackRegister *regs) +{ + // KPrintf("Execption:\n"); + // KPrintf("r0: 0x%08x\n", regs->r0); + // KPrintf("r1: 0x%08x\n", regs->r1); + // KPrintf("r2: 0x%08x\n", regs->r2); + // KPrintf("r3: 0x%08x\n", regs->r3); + // KPrintf("r4: 0x%08x\n", regs->r4); + // KPrintf("r5: 0x%08x\n", regs->r5); + // KPrintf("r6: 0x%08x\n", regs->r6); + // KPrintf("r7: 0x%08x\n", regs->r7); + // KPrintf("r8: 0x%08x\n", regs->r8); + // KPrintf("r9: 0x%08x\n", regs->r9); + // KPrintf("r10: 0x%08x\n", regs->r10); + // KPrintf("r11: 0x%08x\n", regs->r11); + // KPrintf("r12: 0x%08x\n", regs->r12); + // KPrintf("r13_sp: 0x%08x\n", regs->r13_sp); + // KPrintf("r14_lr: 0x%08x\n", regs->r14_lr); + // KPrintf("r15_pc: 0x%08x\n", regs->r15_pc); + // KPrintf("cpsr: 0x%08x\n", regs->cpsr); +} + + +void DoSvcCallProcess(struct ExceptionStackRegister *regs) +{ + +} + +void DoIrqProcess(void) +{ + uint32_t iar = gic_read_irq_ack(); + uint32_t irq_num = iar & 0x3ff; + + if(irq_num >= ARCH_MAX_IRQ_NUM) + { + gic_write_end_of_irq(irq_num); + return; + } + + IsrEntry(irq_num); + + gic_write_end_of_irq(irq_num); +} +// uintptr_t *Svcall(unsigned int ipsr, uintptr_t* contex ) +// { +// #ifdef TASK_ISOLATION +// _svcall(contex); +// #endif +// return contex; +// } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/link.mk b/Ubiquitous/XiZi_AIoT/link.mk new file mode 100644 index 000000000..f0ed846ef --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/link.mk @@ -0,0 +1,10 @@ +OBJS := $(shell cat make.obj) + +$(TARGET): $(OBJS) + @echo ------------------------------------------------ + @echo link $(TARGET) + @$(CROSS_COMPILE)g++ -o $@ $($(LINK_FLAGS)) $(OBJS) $(LINK_MUSLLIB) $(LIBCC) + @echo ------------------------------------------------ + @$(CROSS_COMPILE)objcopy -O binary $@ XiZi-$(BOARD)$(COMPILE_TYPE).bin + @$(CROSS_COMPILE)objcopy -O ihex $@ XiZi-$(BOARD)$(COMPILE_TYPE).hex + @$(CROSS_COMPILE)size $@ \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/path_kernel.mk b/Ubiquitous/XiZi_AIoT/path_kernel.mk new file mode 100755 index 000000000..701bf39a9 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/path_kernel.mk @@ -0,0 +1,51 @@ + +export KERNELPATHS:= -I$(BSP_ROOT) + +ifeq ($(CONFIG_LIB_MUSLLIB), y) +KERNELPATHS += -I$(KERNEL_ROOT)/services/lib/musllib/src/include \ + -I$(KERNEL_ROOT)/services/lib/musllib/include \ + -I$(KERNEL_ROOT)/services/lib/musllib/src/internal # +# chose arch for musl +ifeq ($(ARCH), arm) +KERNELPATHS += -I$(KERNEL_ROOT)/services/lib/musllib/arch/arm +endif +ifeq ($(ARCH), risc-v) +KERNELPATHS += -I$(KERNEL_ROOT)/services/lib/musllib/arch/riscv64 +endif + +endif # end of musl include path + +ifeq ($(CONFIG_LIB_NEWLIB),y) +KERNELPATHS += -I$(KERNEL_ROOT)/services/lib/newlib/include # +endif + +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/services/boards/imx6q-sabrelite) +KERNELPATHS += \ + -I$(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9 \ + -I$(KERNEL_ROOT)/hardkernel/abstraction \ + -I$(KERNEL_ROOT)/include \ + -I$(BSP_ROOT)/include + +ifeq ($(CONFIG_RESOURCES_LWIP),y) +KERNELPATHS += \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/compat \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/netif \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/apps \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/priv \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/prot \ + -I$(KERNEL_ROOT)/resources/ethernet/LwIP/arch +endif +endif + +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Applications/general_functions/list # + +ifeq ($(ARCH), arm) +KERNELPATHS +=-I$(KERNEL_ROOT)/arch/arm/shared \ + -I$(KERNEL_ROOT)/lib/comlibc/common # +endif + +KERNELPATHS += -I$(KERNEL_ROOT)/kernel/include # + diff --git a/Ubiquitous/XiZi_AIoT/services/Kconfig b/Ubiquitous/XiZi_AIoT/services/Kconfig new file mode 100644 index 000000000..ee3478bcb --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/Kconfig @@ -0,0 +1,4 @@ +source "$KERNEL_DIR/services/drivers/Kconfig" +source "$KERNEL_DIR/services/fs/Kconfig" +source "$KERNEL_DIR/services/lib/Kconfig" + diff --git a/Ubiquitous/XiZi_AIoT/services/Makefile b/Ubiquitous/XiZi_AIoT/services/Makefile new file mode 100644 index 000000000..d3d247fa7 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/Makefile @@ -0,0 +1,6 @@ + +SRC_DIR := boards drivers lib + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/services/boards/Makefile b/Ubiquitous/XiZi_AIoT/services/boards/Makefile new file mode 100644 index 000000000..702a453b6 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/Makefile @@ -0,0 +1,4 @@ + +SRC_DIR := $(BOARD) + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/.config b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/.config new file mode 100644 index 000000000..307c2f4c0 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/.config @@ -0,0 +1,18 @@ +# +# Automatically generated file; DO NOT EDIT. +# XiZi_AIoT Project Configuration +# +CONFIG_BOARD_IMX6Q_SABRELITE_EVB=y +CONFIG_ARCH_ARM=y + +# +# imx6q sabrelite feature +# + +# +# Lib +# +CONFIG_LIB=y +CONFIG_LIB_POSIX=y +CONFIG_LIB_NEWLIB=y +# CONFIG_LIB_MUSLLIB is not set diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Kconfig b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Kconfig new file mode 100644 index 000000000..68adb4a56 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Kconfig @@ -0,0 +1,26 @@ +mainmenu "XiZi_AIoT Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_IMX6Q_SABRELITE_EVB + bool + select ARCH_ARM + default y + +source "$KERNEL_DIR/hardkernel/arch/Kconfig" + +menu "imx6q sabrelite feature" + source "$BSP_DIR/third_party_driver/Kconfig" + +endmenu + + +source "$KERNEL_DIR/Kconfig" diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Makefile b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Makefile new file mode 100644 index 000000000..683e42a90 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Makefile @@ -0,0 +1,8 @@ +SRC_FILES := board.c + +SRC_DIR := third_party_driver + + + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/board.c b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/board.c new file mode 100644 index 000000000..6de1c0977 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/board.c @@ -0,0 +1,4 @@ +void start_kernel() +{ + +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/board.h b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/board.h new file mode 100644 index 000000000..db7269dc6 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/board.h @@ -0,0 +1,6 @@ +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#define PLATFORM_MAX_IRQ_NR 160 // imx6q max support 160 irq + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/config.mk b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/config.mk new file mode 100644 index 000000000..ee27915c9 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/config.mk @@ -0,0 +1,23 @@ +export CROSS_COMPILE ?=/usr/bin/arm-none-eabi- +export DEVICE = -march=armv7-a -mtune=cortex-a9 -mfpu=vfpv3-d16 -ftree-vectorize -ffast-math -mfloat-abi=softfp +export CFLAGS := $(DEVICE) -Wall -O0 -g -gdwarf-2 +export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2 +export LFLAGS := $(DEVICE) -Wl,--gc-sections,-Map=XiZi-imx6q-sabrelite.map,-cref,-u,ExceptionVectors -T $(BSP_ROOT)/link.lds +export CXXFLAGS := + +ifeq ($(CONFIG_LIB_MUSLLIB), y) +export LFLAGS += -nostdlib -nostdinc -fno-builtin -nodefaultlibs +export LIBCC := -lgcc +export LINK_MUSLLIB := $(KERNEL_ROOT)/lib/musllib/libmusl.a +endif + +# ifeq ($(CONFIG_RESOURCES_LWIP), y) +# export LINK_LWIP := $(KERNEL_ROOT)/resources/ethernet/LwIP/liblwip.a +# endif + +export DEFINES := -DHAVE_CCONFIG_H -DSTM32F407xx -DUSE_HAL_DRIVER -DHAVE_SIGINFO + +export USING_NEWLIB =1 +export USING_VFS = 1 +export ARCH = arm +export ARCH_ARMV = armv7-a diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/include/asm_defines.h b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/include/asm_defines.h new file mode 100644 index 000000000..beee15cb1 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/include/asm_defines.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2008-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*! + * @file asm_defines.h + * @brief defines for startup assembly code + * + * @ingroup diag_util + */ + +#ifndef _ASM_DEFINES_H_ +#define _ASM_DEFINES_H_ + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @name CPSR fields +//@{ +#define CPSR_N (1 << 31) //!< Negative +#define CPSR_Z (1 << 30) //!< Zero +#define CPSR_C (1 << 29) //!< Carry +#define CPSR_V (1 << 28) //!< Overflow +#define CPSR_Q (1 << 27) //!< Saturation +#define CPSR_E (1 << 9) //!< Endianness +#define CPSR_A (1 << 8) //!< Async abort mask +#define CPSR_I (1 << 7) //!< IRQ mask +#define CPSR_F (1 << 6) //!< FIQ mask +#define CPSR_T (1 << 5) //!< Thumb mode +#define CPSR_MODE (0x1f) //!< Current processor mode +//@} + +//! @name Mode bits in CPSR +//@{ +#define MODE_USR 0x10 //!< User mode +#define MODE_FIQ 0x11 //!< FIQ mode +#define MODE_IRQ 0x12 //!< IRQ mode +#define MODE_SVC 0x13 //!< Supervisor mode +#define MODE_ABT 0x17 //!< Abort exception mode +#define MODE_UND 0x1B //!< Undefined instruction exception mode +#define MODE_SYS 0x1F //!< System mode +//@} + +//! @name Interrupt enable bits in CPSR +//@{ +#define I_BIT 0x80 //!< When I bit is set, IRQ is disabled +#define F_BIT 0x40 //!< When F bit is set, FIQ is disabled +//@} + +//! @name Stack sizes +//@{ + +//! @brief Size of stacks for exceptions. +#define EXCEPTION_STACK_SIZE 2048 + +//! @brief Supervisor mode stack size. +//! +//! This stack is much larger because most application code runs in +//! Supervisor mode. +#define SVC_STACK_SIZE 8192 + +//@} + +#endif /*_ASM_DEFINES_H_ */ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/include/sdk_types.h b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/include/sdk_types.h new file mode 100644 index 000000000..0b7bc4b76 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/include/sdk_types.h @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2008-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __SDK_TYPES_H__ +#define __SDK_TYPES_H__ + +//! @addtogroup sdk_common +//! @{ + +/*! + * @file sdk_types.h + * @brief Basic types used throughout the SDK. + */ + +#include +#include +#include +#include + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @name Alternate Boolean constants +//@{ +#define TRUE 1 +#define FALSE 0 +//@} + +//! @brief +#define NONE_CHAR (0xFF) + +//! @brief A parameter was out of range or otherwise invalid. +#define INVALID_PARAMETER (-1) + +//! @name Min/max macros +//@{ +#if !defined(MIN) + #define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#if !defined(MAX) + #define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif +//@} + +//! @brief Computes the number of elements in an array. +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +//! @brief Debug print utility. +//! +//! This print function will only output text when the @a DEBUG macro is defined. +static inline void debug_printf(const char * format, ...) +{ +#if defined(DEBUG) + va_list args; + va_start(args, format); + vprintf(format, args); + va_end(args); +#endif +} + +//! @name Test results +typedef enum _test_return +{ + TEST_NOT_STARTED = -3, // present in the menu, but not run + TEST_NOT_IMPLEMENTED = -2, // present in the menu, but not functional + TEST_FAILED = -1, + TEST_PASSED = 0, + TEST_BYPASSED = 2, // user elected to exit the test before it was run + TEST_NOT_PRESENT = 3, // not present in the menu. + TEST_CONTINUE = 4 // proceed with the test. opposite of TEST_BYPASSED +} test_return_t; + +//! @name Return codes +//@{ +#define SUCCESS (0) +#define FAIL (1) +#define ERROR_GENERIC (-1) +#define ERROR_OUT_OF_MEMORY (-2) +//@} + +//! @brief Possible types of displays. +enum display_type { + DISP_DEV_NULL = 0, + DISP_DEV_TFTLCD, + DISP_DEV_LVDS, + DISP_DEV_VGA, + DISP_DEV_HDMI, + DISP_DEV_TV, + DISP_DEV_MIPI, +}; + +//! @} + +#endif // __SDK_TYPES_H__ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/link.lds b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/link.lds new file mode 100644 index 000000000..d6e856d1a --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/link.lds @@ -0,0 +1,96 @@ + + +STACK_SIZE = 4096; + +OUTPUT_ARCH(arm) + +SECTIONS +{ + . = 0x80100000; + + __text_start = .; + .text : + { + *(.vectors) + *(.text) + *(.text.*) + + /* section information for finsh shell */ + . = ALIGN(4); + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(4); + } + __text_end = .; + + __rodata_start = .; + .rodata : { *(.rodata) *(.rodata.*) } + __rodata_end = .; + + . = ALIGN(4); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } + + . = ALIGN(16 * 1024); + .l1_page_table : + { + __l1_page_table_start = .; + . += 16K; + } + + . = ALIGN(8); + __data_start = .; + .data : + { + *(.data) + *(.data.*) + } + __data_end = .; + + . = ALIGN(8); + __bss_start = .; + .bss : + { + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + } + . = ALIGN(4); + __bss_end = .; + + .stacks : + { + __stacks_start = .; + . += STACK_SIZE; + __stacks_end = .; + stack_top = .; + } + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + _end = .; +} diff --git a/Ubiquitous/XiZi_AIoT/services/lib/xxx.c b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/third_party_driver/Kconfig similarity index 100% rename from Ubiquitous/XiZi_AIoT/services/lib/xxx.c rename to Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/third_party_driver/Kconfig diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/third_party_driver/Makefile b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/third_party_driver/Makefile new file mode 100644 index 000000000..f11fc06ee --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/third_party_driver/Makefile @@ -0,0 +1,4 @@ + +SRC_DIR := + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/xsconfig.h b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/xsconfig.h new file mode 100644 index 000000000..656db7dbe --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/xsconfig.h @@ -0,0 +1,18 @@ +#ifndef XS_CONFIG_H__ +#define XS_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* XiZi_AIoT Project Configuration */ + +#define BOARD_IMX6Q_SABRELITE_EVB +#define ARCH_ARM + +/* imx6q sabrelite feature */ + +/* Lib */ + +#define LIB +#define LIB_POSIX +#define LIB_NEWLIB + +#endif diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/Kconfig b/Ubiquitous/XiZi_AIoT/services/drivers/Kconfig new file mode 100644 index 000000000..e69de29bb diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/Makefile b/Ubiquitous/XiZi_AIoT/services/drivers/Makefile new file mode 100644 index 000000000..f11fc06ee --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/drivers/Makefile @@ -0,0 +1,4 @@ + +SRC_DIR := + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/services/fs/Kconfig b/Ubiquitous/XiZi_AIoT/services/fs/Kconfig new file mode 100644 index 000000000..e69de29bb diff --git a/Ubiquitous/XiZi_AIoT/services/lib/Kconfig b/Ubiquitous/XiZi_AIoT/services/lib/Kconfig new file mode 100644 index 000000000..0727350e2 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/lib/Kconfig @@ -0,0 +1,23 @@ +menu "Lib" + +menuconfig LIB + bool "Enable libc APIs from toolchain" + default y + + if LIB + config LIB_POSIX + bool "Enable POSIX layer for poll/select, stdin etc" + default y + choice + prompt "select libc" + default LIB_NEWLIB + + config LIB_NEWLIB + bool "use newlib as libc realization." + + config LIB_MUSLLIB + bool "use musllib as libc realization." + endchoice + endif + +endmenu diff --git a/Ubiquitous/XiZi_AIoT/services/lib/Makefile b/Ubiquitous/XiZi_AIoT/services/lib/Makefile new file mode 100644 index 000000000..39648fd33 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/lib/Makefile @@ -0,0 +1,14 @@ +SRC_DIR := +MUSL_DIR := + +ifeq ($(CONFIG_LIB_NEWLIB),y) +SRC_DIR += newlib +endif + +ifeq ($(CONFIG_LIB_MUSLLIB), y) +# SRC_DIR += musllib +# MUSL_DIR += musllib +endif + +include $(KERNEL_ROOT)/compiler.mk + diff --git a/Ubiquitous/XiZi_AIoT/services/lib/newlib/Kconfig b/Ubiquitous/XiZi_AIoT/services/lib/newlib/Kconfig new file mode 100644 index 000000000..c587e3962 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/lib/newlib/Kconfig @@ -0,0 +1,6 @@ +menu LIB_NEWLIB + bool "Enable Newlib " + default y +endmenu + + diff --git a/Ubiquitous/XiZi_AIoT/services/lib/newlib/Makefile b/Ubiquitous/XiZi_AIoT/services/lib/newlib/Makefile new file mode 100644 index 000000000..04e094528 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/lib/newlib/Makefile @@ -0,0 +1,5 @@ +SRC_FILES := fs_syscalls.c time_syscalls.c mem_syscalls.c task_syscalls.c + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/services/lib/newlib/fs_syscalls.c b/Ubiquitous/XiZi_AIoT/services/lib/newlib/fs_syscalls.c new file mode 100644 index 000000000..67bd6c368 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/lib/newlib/fs_syscalls.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +/** +* @file fs_syscalls.c +* @brief support newlib file system +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2020-09-23 +*/ + +/************************************************* +File name: fs_syscalls.c +Description: support newlib file system +Others: take RT-Thread v4.0.2/components/libc/compilers/newlib/syscalls.c for references + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2020-09-23 +Author: AIIT XUOS Lab +Modification: Use file system functions +*************************************************/ + +#include +#include +#include +/* wwg debug here */ +// #include + +int _fstat_r(struct _reent *ptr, int fd, struct stat *pstat) +{ + ptr->_errno = ENOTSUP; + return -1; +} + +int _link_r(struct _reent *ptr, const char *old, const char *new) +{ + ptr->_errno = ENOTSUP; + return -1; +} + +void * _sbrk_r(struct _reent *ptr, ptrdiff_t incr) +{ + return NULL; +} + +int _wait_r(struct _reent *ptr, int *status) +{ + ptr->_errno = ENOTSUP; + return -1; +} + +#ifdef FS_VFS + +#include + +int _close_r(struct _reent *ptr, int fd) +{ + return close(fd); +} + +int _isatty_r(struct _reent *ptr, int fd) +{ + if (fd >=0 && fd < 3) + return 1; + + ptr->_errno = ENOTSUP; + return -1; +} + +_off_t _lseek_r(struct _reent *ptr, int fd, _off_t pos, int whence) +{ + return lseek(fd, pos, whence); +} + +int _open_r(struct _reent *ptr, const char *file, int flags, int mode) +{ + return open(file, flags, mode); +} + +_ssize_t _read_r(struct _reent *ptr, int fd, void *buf, size_t nbytes) +{ + return read(fd, buf, nbytes); +} + +int _stat_r(struct _reent *ptr, const char *file, struct stat *pstat) +{ + return stat(file, pstat); +} + +int _unlink_r(struct _reent *ptr, const char *file) +{ + return unlink(file); +} + +_ssize_t _write_r(struct _reent *ptr, int fd, const void *buf, size_t nbytes) +{ + return write(fd, buf, nbytes); +} + +#else /* FS_VFS */ + +int _close_r(struct _reent *ptr, int fd) +{ + ptr->_errno = ENOTSUP; + return -1; +} + +int _isatty_r(struct _reent *ptr, int fd) +{ + ptr->_errno = ENOTSUP; + return -1; +} + +_off_t _lseek_r(struct _reent *ptr, int fd, _off_t pos, int whence) +{ + ptr->_errno = ENOTSUP; + return -1; +} + +int _open_r(struct _reent *ptr, const char *file, int flags, int mode) +{ + ptr->_errno = ENOTSUP; + return -1; +} + +_ssize_t _read_r(struct _reent *ptr, int fd, void *buf, size_t nbytes) +{ + ptr->_errno = ENOTSUP; + return -1; +} + +int _stat_r(struct _reent *ptr, const char *file, struct stat *pstat) +{ + ptr->_errno = ENOTSUP; + return -1; +} + +int _unlink_r(struct _reent *ptr, const char *file) +{ + ptr->_errno = ENOTSUP; + return -1; +} + +_ssize_t _write_r(struct _reent *ptr, int fd, const void *buf, size_t nbytes) +{ + ptr->_errno = ENOTSUP; + return -1; +} + +#endif /* FS_VFS */ diff --git a/Ubiquitous/XiZi_AIoT/services/lib/newlib/include/libc.h b/Ubiquitous/XiZi_AIoT/services/lib/newlib/include/libc.h new file mode 100644 index 000000000..223bf0f64 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/lib/newlib/include/libc.h @@ -0,0 +1,29 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file libc.h +* @brief using newlib need include +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2020-09-23 +*/ + +#ifndef _LIBC_H__ +#define _LIBC_H__ + +#include +#include +#include + +#endif + diff --git a/Ubiquitous/XiZi_AIoT/services/lib/newlib/mem_syscalls.c b/Ubiquitous/XiZi_AIoT/services/lib/newlib/mem_syscalls.c new file mode 100644 index 000000000..4a82eb6f0 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/lib/newlib/mem_syscalls.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +/** +* @file mem_syscalls.c +* @brief support newlib memory +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2020-09-23 +*/ + +/************************************************* +File name: mem_syscalls.c +Description: support newlib memory +Others: take RT-Thread v4.0.2/components/libc/compilers/newlib/syscalls.c for references + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2020-09-23 +Author: AIIT XUOS Lab +Modification: Use malloc, realloc, calloc and free functions +*************************************************/ +/* wwg debug here */ +// #include +#include + +void *_malloc_r (struct _reent *ptr, size_t size) +{ + /* wwg debug here */ + // void* result = (void*)x_malloc(size); + void* result = NULL; + + if (result == NULL) + { + ptr->_errno = ENOMEM; + } + + return result; +} + +void *_realloc_r (struct _reent *ptr, void *old, size_t newlen) +{ + /* wwg debug here */ + // void* result = (void*)x_realloc(old, newlen); + void* result = NULL; + + if (result == NULL) + { + ptr->_errno = ENOMEM; + } + + return result; +} + +void *_calloc_r (struct _reent *ptr, size_t size, size_t len) +{ + /* wwg debug here */ + // void* result = (void*)x_calloc(size, len); + void* result = NULL; + + if (result == NULL) + { + ptr->_errno = ENOMEM; + } + + return result; +} + +void _free_r (struct _reent *ptr, void *address) +{ + /* wwg debug here */ + // x_free (address); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/lib/newlib/stdio.c b/Ubiquitous/XiZi_AIoT/services/lib/newlib/stdio.c new file mode 100644 index 000000000..6ae393a96 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/lib/newlib/stdio.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017/10/15 bernard the first version + */ + +/** +* @file stdio.c +* @brief support newlib stdio +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2020-09-23 +*/ + +/************************************************* +File name: stdio.c +Description: support newlib stdio +Others: take RT-Thread v4.0.2/components/libc/compilers/newlib/stdio.c for references + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2020-09-23 +Author: AIIT XUOS Lab +Modification: Use set and get console functions +*************************************************/ + +#include +#include +#include +#include + +#define STDIO_DEVICE_NAME_MAX 32 + +static FILE* std_console = NULL; + +/** + * This function will set system console device. + * + * @param device_name the name of device + * @param mode the mode + * + * @return file number on success; or -1 on failure + */ +int LibcStdioSetConsole(const char* device_name, int mode) +{ + FILE *fp; + char name[STDIO_DEVICE_NAME_MAX] = {0}; + char *file_mode; + + snprintf(name, strlen(device_name) + 6, "/dev/%s", device_name); + name[STDIO_DEVICE_NAME_MAX - 1] = '\0'; + + switch (mode) + { + case O_RDWR: + file_mode = "r+"; + break; + + case O_WRONLY: + file_mode = "wb"; + break; + + default: + file_mode = "rb"; + break; + } + + /* try to open file */ + fp = fopen(name, file_mode); + if (fp) + { + /* set the fp buffer */ + setvbuf(fp, NULL, _IONBF, 0); + + if (std_console) + /* try to close console device */ + fclose(std_console); + std_console = fp; + + if (mode == O_RDWR) + { + /* set _stdin as std_console */ + _GLOBAL_REENT->_stdin = std_console; + } + else + { + /* set NULL */ + _GLOBAL_REENT->_stdin = NULL; + } + + if (mode == O_RDONLY) + { + /* set the _stdout as NULL */ + _GLOBAL_REENT->_stdout = NULL; + /* set the _stderr as NULL */ + _GLOBAL_REENT->_stderr = NULL; + } + else + { + /* set the _stdout as std_console */ + _GLOBAL_REENT->_stdout = std_console; + /* set the _stderr as std_console */ + _GLOBAL_REENT->_stderr = std_console; + } + /* set the __sdidinit as 1 */ + _GLOBAL_REENT->__sdidinit = 1; + } + + if (std_console) + /* return the file number */ + return fileno(std_console); + /* failure and return -1 */ + return -1; +} + +/** + * This function will get system console device. + * + * @return file number on success; or -1 on failure + */ +int LibcStdioGetConsole(void) { + if (std_console) + /* return the file number */ + return fileno(std_console); + else + /* failure and return -1 */ + return -1; +} + +/** + * This function will initialize the c library system. + * + * @return 0 + */ +int LibcSystemInit(void) +{ +#if defined(KERNEL_CONSOLE) + HardwareDevType console; + /* try to get console device */ + console = ObtainConsole(); + if (console) + { +#if defined(LIB_POSIX) + /* set console device mode */ + LibcStdioSetConsole(console->dev_name, O_RDWR); +#else + /* set console device mode */ + LibcStdioSetConsole(console->dev_name, O_WRONLY); +#endif + } +#endif + return 0; +} diff --git a/Ubiquitous/XiZi_AIoT/services/lib/newlib/task_syscalls.c b/Ubiquitous/XiZi_AIoT/services/lib/newlib/task_syscalls.c new file mode 100644 index 000000000..14011491e --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/lib/newlib/task_syscalls.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +/** +* @file task_syscalls.c +* @brief support newlib abort +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2020-09-23 +*/ + +/************************************************* +File name: task_syscalls.c +Description: support newlib abort +Others: take RT-Thread v4.0.2/components/libc/compilers/newlib/syscalls.c for references + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2020-09-23 +Author: AIIT XUOS Lab +Modification: Use abort function +*************************************************/ +/* wwg debug here */ +// #include + +void abort(void) +{ + // KTaskDescriptorType current = GetKTaskDescriptor(); + // if (current) + // { + // KPrintf("Task:%-8.*s will be aborted!\n", NAME_NUM_MAX, current->task_base_info.name); + // /* pend current task */ + // SuspendKTask(current->id.id); + // /* schedule */ + // DO_KTASK_ASSIGN; + // } + + while (1); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/lib/newlib/time_syscalls.c b/Ubiquitous/XiZi_AIoT/services/lib/newlib/time_syscalls.c new file mode 100644 index 000000000..2696d108b --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/lib/newlib/time_syscalls.c @@ -0,0 +1,42 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#include +// #include +// #include + +// time_t time(time_t *t) +// { +// NULL_PARAM_CHECK(t); +// time_t current = 0; + +// #ifdef RESOURCES_RTC +// struct RtcSetParam rtc_set_param; +// rtc_set_param.rtc_set_cmd = OPER_RTC_GET_TIME; +// rtc_set_param.time = ¤t; + +// RtcDrvSetFunction(RTC_DRV_NAME, &rtc_set_param); +// #endif + +// *t = current; + +// return current; +// } + +time_t time(time_t *t) +{ + time_t current = 0; + + *t = current; + + return current; +} diff --git a/Ubiquitous/XiZi_AIoT/services/tools/hosttools/xsconfig.sh b/Ubiquitous/XiZi_AIoT/services/tools/hosttools/xsconfig.sh new file mode 100755 index 000000000..b51a159aa --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/tools/hosttools/xsconfig.sh @@ -0,0 +1,91 @@ +#!/bin/bash +# Tring to create rtcnofig.h from .config +HEADER_STR=XS_CONFIG_H__ + + +function is_pkg_special_config() +{ + echo -ne $1 | egrep '^PKG_|_PATH$|_VER$' >/dev/null 2>/dev/null +} + +function is_config() +{ + echo -ne $1 | egrep '^XS_' >/dev/null 2>/dev/null +} + +function make_config_h() +{ + local CONFIG_NAME=${1} + + # destination file using file descriptor 8 + exec 8>${2} + + echo -ne "#ifndef ${HEADER_STR}\n" >&8 + echo -ne "#define ${HEADER_STR}\n\n" >&8 + + EMPTY_LINE='true' + + while read LN + do + LINE=`echo $LN | sed 's/[ \t\r\n]*$//g'` + + if [ -z "$LINE" ]; then + continue + fi + + if [ '#' = ${LINE:0:1} ]; then + if [ ${#LINE} -eq 1 ]; then + if $EMPTY_LINE; then + continue + fi + echo >&8 + EMPTY_LINE='true' + continue + fi + + if echo -ne "$LINE" | egrep '^# CONFIG_' >/dev/null 2>/dev/null; then + LINE=`printf ' %s' ${LINE:9}` + else + LINE=${LINE:1} + echo -ne "/* ${LINE} */\n" >&8 + fi + + EMPTY_LINE='false' + else + EMPTY_LINE='false' + + OLD_IFS="$IFS" + IFS='=' + SETTINGS=($LINE) + IFS="$OLD_IFS" + + if [ ${#SETTINGS[@]} -ge 2 ]; then + if echo -ne "$SETTINGS[0]" | egrep '^CONFIG_' >/dev/null 2>/dev/null; then + SETTINGS[0]="${SETTINGS[0]:7}" + fi + + if is_pkg_special_config "${SETTINGS[0]}"; then + continue + fi + +# echo "DBG---: ${SETTINGS[@]}, ${SETTINGS[*]}" + if [ "${SETTINGS[1]}" = 'y' ]; then + echo -ne "#define ${SETTINGS[0]}\n" >&8 + else + echo -ne "#define ${SETTINGS[0]} ${LINE#*=}\n" >&8 + fi + fi + fi + + done < $CONFIG_NAME + + if [ -f xsconfig_project.h ]; then + echo -ne "#include \"xsconfig_project.h\"\n" >&8 + fi + + echo -ne "\n#endif\n" >&8 + exec 8<&- +} + +make_config_h $1 $BSP_ROOT/xsconfig.h + diff --git a/Ubiquitous/XiZi_AIoT/softkernel/Kconfig b/Ubiquitous/XiZi_AIoT/softkernel/Kconfig new file mode 100644 index 000000000..e69de29bb diff --git a/Ubiquitous/XiZi_AIoT/softkernel/Makefile b/Ubiquitous/XiZi_AIoT/softkernel/Makefile new file mode 100644 index 000000000..77a92fa1d --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/softkernel/Makefile @@ -0,0 +1,4 @@ + +SRC_DIR := task + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/softkernel/task/Makefile b/Ubiquitous/XiZi_AIoT/softkernel/task/Makefile new file mode 100644 index 000000000..4ca20e597 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/softkernel/task/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := task.c schedule.c ipc.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/support/Kconfig b/Ubiquitous/XiZi_AIoT/support/Kconfig new file mode 100644 index 000000000..e69de29bb diff --git a/Ubiquitous/XiZi_AIoT/support/Makefile b/Ubiquitous/XiZi_AIoT/support/Makefile new file mode 100644 index 000000000..f11fc06ee --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/support/Makefile @@ -0,0 +1,4 @@ + +SRC_DIR := + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/testing/Kconfig b/Ubiquitous/XiZi_AIoT/testing/Kconfig new file mode 100644 index 000000000..e69de29bb diff --git a/Ubiquitous/XiZi_AIoT/testing/Makefile b/Ubiquitous/XiZi_AIoT/testing/Makefile new file mode 100644 index 000000000..f11fc06ee --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/testing/Makefile @@ -0,0 +1,4 @@ + +SRC_DIR := + +include $(KERNEL_ROOT)/compiler.mk