forked from xuos/xiuos
1、feat add link-bootloader.lds[start from 0x60000000] and link-application.lds[start from 0x60040000];
2、support BSP_USING_OTA MCUBOOT_BOOTLOADER and MCUBOOT_APPLICATION in xidatong-arm32/Kconfig; 3、support compile XiZi-xidatong-arm32-boot.bin when enable MCUBOOT_BOOTLOADER and XiZi-xidatong-arm32-app.bin when enable MCUBOOT_APPLICATION; 4、add QSPIFlash function for xidatong-arm32。
This commit is contained in:
wgzAIIT
+949
-35
File diff suppressed because it is too large
Load Diff
+18
-1
@@ -223,6 +223,12 @@
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#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
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/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
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#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
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/* @brief Channel IRQ entry shared offset. */
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#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (16)
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/* @brief If 8 bytes transfer supported. */
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#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1)
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/* @brief If 16 bytes transfer supported. */
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#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (0)
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/* DMAMUX module features */
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@@ -279,6 +285,8 @@
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#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001)
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/* @brief Reset value of the FLEXIO_PARAM register */
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#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200404)
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/* @brief Flexio DMA request base channel */
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#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0)
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/* FLEXRAM module features */
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@@ -489,7 +497,10 @@
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/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
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#define FSL_FEATURE_SAI_FIFO_COUNT (32)
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/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
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#define FSL_FEATURE_SAI_CHANNEL_COUNT (4)
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#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \
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(((x) == SAI1) ? (4) : \
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(((x) == SAI2) ? (1) : \
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(((x) == SAI3) ? (1) : (-1))))
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/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
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#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
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/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
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@@ -514,6 +525,10 @@
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#define FSL_FEATURE_SAI_HAS_MDR (0)
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/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
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#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0)
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/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */
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#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0)
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/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
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#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1)
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/* SEMC module features */
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@@ -623,5 +638,7 @@
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/* @brief DMA_CH_MUX_REQ_95. */
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#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 (1)
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#define FSL_FEATURE_XBARA_INTERRUPT_COUNT (4)
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#endif /* _MIMXRT1052_FEATURES_H_ */
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@@ -0,0 +1,32 @@
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/*
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* Copyright 2018-2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/**
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* @file flash.h
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* @brief support flexspi norflash function
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* @version 2.0
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* @author AIIT XUOS Lab
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* @date 2023-04-03
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*/
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#ifndef __FLASH_H__
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#define __FLASH_H__
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#include <stdint.h>
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#include "fsl_romapi.h"
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void FLASH_Init(void);
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void FLASH_DeInit(void);
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uint32_t FLASH_GetSectorSize(void);
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status_t FLASH_WritePage(uint32_t addr, const uint8_t *buf, uint32_t len);
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status_t FLASH_EraseSector(uint32_t addr);
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status_t FLASH_Read(uint32_t addr, const uint8_t *buf, uint32_t len);
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uint32_t FLASH_Test(uint32_t startAddr, uint32_t len);
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uint32_t FLASH_GetProgramCmd(void);
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#endif
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@@ -1,5 +1,5 @@
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/*
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* Copyright 2017 - 2019 NXP
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* Copyright 2017 - 2020, NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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@@ -47,8 +47,8 @@
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/*! @name Driver version */
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/*@{*/
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/*! @brief CLOCK driver version 2.2.0. */
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#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
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/*! @brief CLOCK driver version 2.4.0. */
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#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
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/* Definition for delay API in clock driver, users can redefine it to the real application. */
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#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
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@@ -56,8 +56,8 @@
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#endif
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/* analog pll definition */
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#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
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#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
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#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
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/*@}*/
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@@ -65,48 +65,56 @@
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/*!
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* @brief CCM registers offset.
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*/
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#define CCSR_OFFSET 0x0C
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#define CBCDR_OFFSET 0x14
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#define CBCMR_OFFSET 0x18
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#define CCSR_OFFSET 0x0C
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#define CBCDR_OFFSET 0x14
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#define CBCMR_OFFSET 0x18
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#define CSCMR1_OFFSET 0x1C
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#define CSCMR2_OFFSET 0x20
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#define CSCDR1_OFFSET 0x24
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#define CDCDR_OFFSET 0x30
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#define CDCDR_OFFSET 0x30
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#define CSCDR2_OFFSET 0x38
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#define CSCDR3_OFFSET 0x3C
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#define CACRR_OFFSET 0x10
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#define CACRR_OFFSET 0x10
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#define CS1CDR_OFFSET 0x28
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#define CS2CDR_OFFSET 0x2C
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/*!
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* @brief CCM Analog registers offset.
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*/
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#define PLL_ARM_OFFSET 0x00
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#define PLL_SYS_OFFSET 0x30
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#define PLL_USB1_OFFSET 0x10
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#define PLL_ARM_OFFSET 0x00
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#define PLL_SYS_OFFSET 0x30
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#define PLL_USB1_OFFSET 0x10
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#define PLL_AUDIO_OFFSET 0x70
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#define PLL_VIDEO_OFFSET 0xA0
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#define PLL_ENET_OFFSET 0xE0
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#define PLL_USB2_OFFSET 0x20
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#define PLL_ENET_OFFSET 0xE0
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#define PLL_USB2_OFFSET 0x20
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#define CCM_TUPLE(reg, shift, mask, busyShift) \
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(int)((reg & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
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#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU))))
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#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU)
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#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))
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#define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU)
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(int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
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#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFU))))
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#define CCM_TUPLE_SHIFT(tuple) ((((uint32_t)tuple) >> 8U) & 0x1FU)
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#define CCM_TUPLE_MASK(tuple) \
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((uint32_t)((((uint32_t)(tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))
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#define CCM_TUPLE_BUSY_SHIFT(tuple) ((((uint32_t)tuple) >> 26U) & 0x3FU)
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#define CCM_NO_BUSY_WAIT (0x20U)
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/*!
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* @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
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*/
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#define CCM_ANALOG_TUPLE(reg, shift) (((reg & 0xFFFU) << 16U) | (shift))
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#define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFU) << 16U) | (shift))
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#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)
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#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
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(*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off)))
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(*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))
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#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
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/* Definition for ERRATA 50235 check */
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#if (defined(FSL_FEATURE_CCM_HAS_ERRATA_50235) && FSL_FEATURE_CCM_HAS_ERRATA_50235)
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#define CAN_CLOCK_CHECK_NO_AFFECTS \
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((CCM_CSCMR2_CAN_CLK_SEL(2U) != (CCM->CSCMR2 & CCM_CSCMR2_CAN_CLK_SEL_MASK)) || \
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(CCM_CCGR5_CG12(0) != (CCM->CCGR5 & CCM_CCGR5_CG12_MASK)))
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#endif /* FSL_FEATURE_CCM_HAS_ERRATA_50235 */
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/*!
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* @brief clock1PN frequency.
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*/
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@@ -118,8 +126,8 @@
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* function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
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* if XTAL is 24MHz,
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* @code
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* CLOCK_InitExternalClk(false); // Setup the 24M OSC/SYSOSC
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* CLOCK_SetXtalFreq(240000000); // Set the XTAL value to clock driver.
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* CLOCK_InitExternalClk(false);
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* CLOCK_SetXtalFreq(240000000);
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* @endcode
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*/
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extern volatile uint32_t g_xtalFreq;
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@@ -132,7 +140,7 @@ extern volatile uint32_t g_xtalFreq;
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extern volatile uint32_t g_rtcXtalFreq;
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/* For compatible with other platforms */
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#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
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#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
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#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq
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/*! @brief Clock ip name array for ADC. */
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@@ -400,6 +408,65 @@ extern volatile uint32_t g_rtcXtalFreq;
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kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
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}
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#define CLOCK_SOURCE_NONE (0xFFU)
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#define CLOCK_ROOT_SOUCE \
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{ \
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{kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \
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kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC1 Clock Root. */ \
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{kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \
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kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC2 Clock Root. */ \
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{kCLOCK_SemcClk, kCLOCK_Usb1SwClk, kCLOCK_SysPllPfd2Clk, \
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kCLOCK_Usb1PllPfd0Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXSPI Clock Root. */ \
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{kCLOCK_OscClk, kCLOCK_SysPllPfd2Clk, kCLOCK_Usb1Sw120MClk, \
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kCLOCK_Usb1PllPfd1Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* CSI Clock Root. */ \
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{kCLOCK_Usb1PllPfd1Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_SysPllClk, \
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kCLOCK_SysPllPfd2Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPSPI Clock Root. */ \
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{kCLOCK_SysPllClk, kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, \
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kCLOCK_SysPllPfd1Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* TRACE Clock Root */ \
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{kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
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kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI1 Clock Root */ \
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{kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
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kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI2 Clock Root */ \
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{kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
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kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI3 Clock Root */ \
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{kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_NoneName, \
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kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPI2C Clock Root */ \
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{kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_Usb1Sw80MClk, \
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kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* CAN Clock Root. */ \
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{kCLOCK_Usb1Sw80MClk, kCLOCK_OscClk, kCLOCK_NoneName, \
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kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* UART Clock Root */ \
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{kCLOCK_SysPllClk, kCLOCK_Usb1PllPfd3Clk, kCLOCK_VideoPllClk, \
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kCLOCK_SysPllPfd0Clk, kCLOCK_SysPllPfd1Clk, kCLOCK_Usb1PllPfd1Clk}, /* LCDIF Clock Root */ \
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{kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
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kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* SPDIF0 Clock Root */ \
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{kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
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kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO1 Clock Root */ \
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{kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
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kCLOCK_Usb1PllClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO2 Clock ROOT */ \
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}
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#define CLOCK_ROOT_MUX_TUPLE \
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{ \
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kCLOCK_Usdhc1Mux, kCLOCK_Usdhc2Mux, kCLOCK_FlexspiMux, kCLOCK_CsiMux, kCLOCK_LpspiMux, kCLOCK_TraceMux, \
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kCLOCK_Sai1Mux, kCLOCK_Sai2Mux, kCLOCK_Sai3Mux, kCLOCK_Lpi2cMux, kCLOCK_CanMux, kCLOCK_UartMux, \
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kCLOCK_LcdifPreMux, kCLOCK_SpdifMux, kCLOCK_Flexio1Mux, kCLOCK_Flexio2Mux, \
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}
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#define CLOCK_ROOT_NONE_PRE_DIV 0UL
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#define CLOCK_ROOT_DIV_TUPLE \
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{ \
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{kCLOCK_NonePreDiv, kCLOCK_Usdhc1Div}, {kCLOCK_NonePreDiv, kCLOCK_Usdhc2Div}, \
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{kCLOCK_NonePreDiv, kCLOCK_FlexspiDiv}, {kCLOCK_NonePreDiv, kCLOCK_CsiDiv}, \
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{kCLOCK_NonePreDiv, kCLOCK_LpspiDiv}, {kCLOCK_NonePreDiv, kCLOCK_TraceDiv}, \
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{kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div}, {kCLOCK_Sai2PreDiv, kCLOCK_Sai2Div}, \
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{kCLOCK_Sai3PreDiv, kCLOCK_Sai3Div}, {kCLOCK_NonePreDiv, kCLOCK_Lpi2cDiv}, \
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{kCLOCK_NonePreDiv, kCLOCK_CanDiv}, {kCLOCK_NonePreDiv, kCLOCK_UartDiv}, \
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{kCLOCK_LcdifPreDiv, kCLOCK_LcdifDiv}, {kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div}, \
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{kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div}, {kCLOCK_Flexio2PreDiv, kCLOCK_Flexio2Div}, \
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}
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/*! @brief Clock name used to get clock frequency. */
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typedef enum _clock_name
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{
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@@ -414,11 +481,15 @@ typedef enum _clock_name
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kCLOCK_ArmPllClk = 0x7U, /*!< ARMPLLCLK. */
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kCLOCK_Usb1PllClk = 0x8U, /*!< USB1PLLCLK. */
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kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */
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kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */
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kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */
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kCLOCK_Usb1PllPfd3Clk = 0xCU, /*!< USB1PLLPFD3CLK. */
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kCLOCK_Usb1PllClk = 0x8U, /*!< USB1PLLCLK. */
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kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */
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kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */
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kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */
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kCLOCK_Usb1PllPfd3Clk = 0xCU, /*!< USB1PLLPFD3CLK. */
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kCLOCK_Usb1SwClk = 0x17U, /*!< USB1PLLSWCLK */
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kCLOCK_Usb1Sw120MClk = 0x18U, /*!< USB1PLLSw120MCLK */
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kCLOCK_Usb1Sw60MClk = 0x19U, /*!< USB1PLLSw60MCLK */
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kCLOCK_Usb1Sw80MClk = 0x1AU, /*!< USB1PLLSw80MCLK */
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kCLOCK_Usb2PllClk = 0xDU, /*!< USB2PLLCLK. */
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@@ -431,11 +502,12 @@ typedef enum _clock_name
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kCLOCK_EnetPll0Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll0. */
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kCLOCK_EnetPll1Clk = 0x14U, /*!< Enet PLLCLK ref_enetpll1. */
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kCLOCK_AudioPllClk = 0x15U, /*!< Audio PLLCLK. */
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kCLOCK_VideoPllClk = 0x16U, /*!< Video PLLCLK. */
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kCLOCK_AudioPllClk = 0x15U, /*!< Audio PLLCLK. */
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kCLOCK_VideoPllClk = 0x16U, /*!< Video PLLCLK. */
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kCLOCK_NoneName = CLOCK_SOURCE_NONE, /*!< None Clock Name. */
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} clock_name_t;
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#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */
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#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */
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#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */
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/*!
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@@ -835,6 +907,8 @@ typedef enum _clock_div
|
||||
|
||||
kCLOCK_CsiDiv = CCM_TUPLE(
|
||||
CSCDR3_OFFSET, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */
|
||||
|
||||
kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV, /*!< None Pre div. */
|
||||
} clock_div_t;
|
||||
|
||||
/*! @brief USB clock source definition. */
|
||||
@@ -952,6 +1026,83 @@ typedef enum _clock_pfd
|
||||
kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
|
||||
} clock_pfd_t;
|
||||
|
||||
/*!
|
||||
* @brief The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.
|
||||
*/
|
||||
typedef enum _clock_output1_selection
|
||||
{
|
||||
kCLOCK_OutputPllUsb1 = 0U, /*!< Selects USB1 PLL clock(Divided by 2) output. */
|
||||
kCLOCK_OutputPllSys = 1U, /*!< Selects SYS PLL clock(Divided by 2) output. */
|
||||
kCLOCK_OutputPllVideo = 3U, /*!< Selects Video PLL clock(Divided by 2) output. */
|
||||
kCLOCK_OutputSemcClk = 5U, /*!< Selects semc clock root output. */
|
||||
kCLOCK_OutputLcdifPixClk = 0xAU, /*!< Selects Lcdif pix clock root output. */
|
||||
kCLOCK_OutputAhbClk = 0xBU, /*!< Selects AHB clock root output. */
|
||||
kCLOCK_OutputIpgClk = 0xCU, /*!< Selects IPG clock root output. */
|
||||
kCLOCK_OutputPerClk = 0xDU, /*!< Selects PERCLK clock root output. */
|
||||
kCLOCK_OutputCkilSyncClk = 0xEU, /*!< Selects Ckil clock root output. */
|
||||
kCLOCK_OutputPll4MainClk = 0xFU, /*!< Selects PLL4 main clock output. */
|
||||
kCLOCK_DisableClockOutput1 = 0x10U, /*!< Disables CLKO1. */
|
||||
} clock_output1_selection_t;
|
||||
|
||||
/*!
|
||||
* @brief The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on.
|
||||
*
|
||||
*/
|
||||
typedef enum _clock_output2_selection
|
||||
{
|
||||
kCLOCK_OutputUsdhc1Clk = 3U, /*!< Selects USDHC1 clock root output. */
|
||||
kCLOCK_OutputLpi2cClk = 6U, /*!< Selects LPI2C clock root output. */
|
||||
kCLOCK_OutputCsiClk = 0xBU, /*!< Selects CSI clock root output. */
|
||||
kCLOCK_OutputOscClk = 0xEU, /*!< Selects OSC output. */
|
||||
kCLOCK_OutputUsdhc2Clk = 0x11U, /*!< Selects USDHC2 clock root output. */
|
||||
kCLOCK_OutputSai1Clk = 0x12U, /*!< Selects SAI1 clock root output. */
|
||||
kCLOCK_OutputSai2Clk = 0x13U, /*!< Selects SAI2 clock root output. */
|
||||
kCLOCK_OutputSai3Clk = 0x14U, /*!< Selects SAI3 clock root output. */
|
||||
kCLOCK_OutputCanClk = 0x17U, /*!< Selects CAN clock root output. */
|
||||
kCLOCK_OutputFlexspiClk = 0x1BU, /*!< Selects FLEXSPI clock root output. */
|
||||
kCLOCK_OutputUartClk = 0x1CU, /*!< Selects UART clock root output. */
|
||||
kCLOCK_OutputSpdif0Clk = 0x1DU, /*!< Selects SPDIF0 clock root output. */
|
||||
kCLOCK_DisableClockOutput2 = 0x1FU, /*!< Disables CLKO2. */
|
||||
} clock_output2_selection_t;
|
||||
|
||||
/*!
|
||||
* @brief The enumerator of clock output's divider.
|
||||
*/
|
||||
typedef enum _clock_output_divider
|
||||
{
|
||||
kCLOCK_DivideBy1 = 0U, /*!< Output clock divided by 1. */
|
||||
kCLOCK_DivideBy2, /*!< Output clock divided by 2. */
|
||||
kCLOCK_DivideBy3, /*!< Output clock divided by 3. */
|
||||
kCLOCK_DivideBy4, /*!< Output clock divided by 4. */
|
||||
kCLOCK_DivideBy5, /*!< Output clock divided by 5. */
|
||||
kCLOCK_DivideBy6, /*!< Output clock divided by 6. */
|
||||
kCLOCK_DivideBy7, /*!< Output clock divided by 7. */
|
||||
kCLOCK_DivideBy8, /*!< Output clock divided by 8. */
|
||||
} clock_output_divider_t;
|
||||
|
||||
/*!
|
||||
* @brief The enumerator of clock root.
|
||||
*/
|
||||
typedef enum _clock_root
|
||||
{
|
||||
kCLOCK_Usdhc1ClkRoot = 0U, /*!< USDHC1 clock root. */
|
||||
kCLOCK_Usdhc2ClkRoot, /*!< USDHC2 clock root. */
|
||||
kCLOCK_FlexspiClkRoot, /*!< FLEXSPI clock root. */
|
||||
kCLOCK_CsiClkRoot, /*!< CSI clock root. */
|
||||
kCLOCK_LpspiClkRoot, /*!< LPSPI clock root. */
|
||||
kCLOCK_TraceClkRoot, /*!< Trace clock root. */
|
||||
kCLOCK_Sai1ClkRoot, /*!< SAI1 clock root. */
|
||||
kCLOCK_Sai2ClkRoot, /*!< SAI2 clock root. */
|
||||
kCLOCK_Sai3ClkRoot, /*!< SAI3 clock root. */
|
||||
kCLOCK_Lpi2cClkRoot, /*!< LPI2C clock root. */
|
||||
kCLOCK_CanClkRoot, /*!< CAN clock root. */
|
||||
kCLOCK_UartClkRoot, /*!< UART clock root. */
|
||||
kCLOCK_LcdifClkRoot, /*!< LCD clock root. */
|
||||
kCLOCK_SpdifClkRoot, /*!< SPDIF clock root. */
|
||||
kCLOCK_Flexio1ClkRoot, /*!< FLEXIO1 clock root. */
|
||||
kCLOCK_Flexio2ClkRoot, /*!< FLEXIO2 clock root. */
|
||||
} clock_root_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
@@ -970,7 +1121,7 @@ static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
|
||||
{
|
||||
uint32_t busyShift;
|
||||
|
||||
busyShift = CCM_TUPLE_BUSY_SHIFT(mux);
|
||||
busyShift = (uint32_t)CCM_TUPLE_BUSY_SHIFT(mux);
|
||||
CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |
|
||||
(((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
|
||||
|
||||
@@ -980,7 +1131,7 @@ static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
|
||||
if (CCM_NO_BUSY_WAIT != busyShift)
|
||||
{
|
||||
/* Wait until CCM internal handshake finish. */
|
||||
while (CCM->CDHIPR & (1U << busyShift))
|
||||
while ((CCM->CDHIPR & ((1UL << busyShift))) != 0UL)
|
||||
{
|
||||
}
|
||||
}
|
||||
@@ -994,7 +1145,7 @@ static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
|
||||
*/
|
||||
static inline uint32_t CLOCK_GetMux(clock_mux_t mux)
|
||||
{
|
||||
return (CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux)) >> CCM_TUPLE_SHIFT(mux);
|
||||
return (((uint32_t)(CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux))) >> CCM_TUPLE_SHIFT(mux));
|
||||
}
|
||||
|
||||
/*!
|
||||
@@ -1017,7 +1168,7 @@ static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
|
||||
if (CCM_NO_BUSY_WAIT != busyShift)
|
||||
{
|
||||
/* Wait until CCM internal handshake finish. */
|
||||
while (CCM->CDHIPR & (1U << busyShift))
|
||||
while ((CCM->CDHIPR & ((uint32_t)(1UL << busyShift))) != 0UL)
|
||||
{
|
||||
}
|
||||
}
|
||||
@@ -1030,7 +1181,7 @@ static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
|
||||
*/
|
||||
static inline uint32_t CLOCK_GetDiv(clock_div_t divider)
|
||||
{
|
||||
return ((CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider));
|
||||
return ((uint32_t)(CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider));
|
||||
}
|
||||
|
||||
/*!
|
||||
@@ -1045,10 +1196,10 @@ static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t va
|
||||
uint32_t shift = ((uint32_t)name) & 0x1FU;
|
||||
volatile uint32_t *reg;
|
||||
|
||||
assert(index <= 6);
|
||||
assert(index <= 6UL);
|
||||
|
||||
reg = ((volatile uint32_t *)&CCM->CCGR0) + index;
|
||||
*reg = ((*reg) & ~(3U << shift)) | (((uint32_t)value) << shift);
|
||||
reg = (volatile uint32_t *)(&(((volatile uint32_t *)&CCM->CCGR0)[index]));
|
||||
*reg = ((*reg) & ~((uint32_t)(3UL << shift))) | (((uint32_t)value) << shift);
|
||||
}
|
||||
|
||||
/*!
|
||||
@@ -1087,13 +1238,11 @@ static inline void CLOCK_SetMode(clock_mode_t mode)
|
||||
* This function will return the external XTAL OSC frequency if it is selected as the source of OSC,
|
||||
* otherwise internal 24MHz RC OSC frequency will be returned.
|
||||
*
|
||||
* @param osc OSC type to get frequency.
|
||||
*
|
||||
* @return Clock frequency; If the clock is invalid, returns 0.
|
||||
*/
|
||||
static inline uint32_t CLOCK_GetOscFreq(void)
|
||||
{
|
||||
return (XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) ? 24000000UL : g_xtalFreq;
|
||||
return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_xtalFreq;
|
||||
}
|
||||
|
||||
/*!
|
||||
@@ -1130,7 +1279,7 @@ uint32_t CLOCK_GetPerClkFreq(void);
|
||||
* This function checks the current clock configurations and then calculates
|
||||
* the clock frequency for a specific clock name defined in clock_name_t.
|
||||
*
|
||||
* @param clockName Clock names defined in clock_name_t
|
||||
* @param name Clock names defined in clock_name_t
|
||||
* @return Clock frequency value in hertz
|
||||
*/
|
||||
uint32_t CLOCK_GetFreq(clock_name_t name);
|
||||
@@ -1145,6 +1294,14 @@ static inline uint32_t CLOCK_GetCpuClkFreq(void)
|
||||
return CLOCK_GetFreq(kCLOCK_CpuClk);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the frequency of selected clock root.
|
||||
*
|
||||
* @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
|
||||
* @return The frequency of selected clock root.
|
||||
*/
|
||||
uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot);
|
||||
|
||||
/*!
|
||||
* @name OSC operations
|
||||
* @{
|
||||
@@ -1157,7 +1314,7 @@ static inline uint32_t CLOCK_GetCpuClkFreq(void)
|
||||
* 1. Use external crystal oscillator.
|
||||
* 2. Bypass the external crystal oscillator, using input source clock directly.
|
||||
*
|
||||
* After this function, please call @ref CLOCK_SetXtal0Freq to inform clock driver
|
||||
* After this function, please call CLOCK_SetXtal0Freq to inform clock driver
|
||||
* the external clock frequency.
|
||||
*
|
||||
* @param bypassXtalOsc Pass in true to bypass the external crystal oscillator.
|
||||
@@ -1171,7 +1328,7 @@ void CLOCK_InitExternalClk(bool bypassXtalOsc);
|
||||
*
|
||||
* This function disables the external 24MHz clock.
|
||||
*
|
||||
* After this function, please call @ref CLOCK_SetXtal0Freq to set external clock
|
||||
* After this function, please call CLOCK_SetXtal0Freq to set external clock
|
||||
* frequency to 0.
|
||||
*/
|
||||
void CLOCK_DeinitExternalClk(void);
|
||||
@@ -1229,7 +1386,7 @@ void CLOCK_DeinitRcOsc24M(void);
|
||||
/*! @brief Enable USB HS clock.
|
||||
*
|
||||
* This function only enables the access to USB HS prepheral, upper layer
|
||||
* should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
|
||||
* should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
|
||||
* clock to use USB HS.
|
||||
*
|
||||
* @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
|
||||
@@ -1242,7 +1399,7 @@ bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
|
||||
/*! @brief Enable USB HS clock.
|
||||
*
|
||||
* This function only enables the access to USB HS prepheral, upper layer
|
||||
* should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
|
||||
* should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
|
||||
* clock to use USB HS.
|
||||
*
|
||||
* @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
|
||||
@@ -1252,12 +1409,6 @@ bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
|
||||
*/
|
||||
bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq);
|
||||
|
||||
/*! @brief Disable USB HS PHY PLL clock.
|
||||
*
|
||||
* This function disables USB HS PHY PLL clock.
|
||||
*/
|
||||
void CLOCK_DisableUsbhs1PhyPllClock(void);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
@@ -1277,11 +1428,11 @@ static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bo
|
||||
{
|
||||
if (bypass)
|
||||
{
|
||||
CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT;
|
||||
CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
|
||||
}
|
||||
else
|
||||
{
|
||||
CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT;
|
||||
CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1296,7 +1447,7 @@ static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bo
|
||||
*/
|
||||
static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll)
|
||||
{
|
||||
return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_PLL_BYPASS_SHIFT));
|
||||
return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_PLL_BYPASS_SHIFT));
|
||||
}
|
||||
|
||||
/*!
|
||||
@@ -1310,7 +1461,7 @@ static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll)
|
||||
*/
|
||||
static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll)
|
||||
{
|
||||
return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_TUPLE_SHIFT(pll)));
|
||||
return ((CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pll))) != 0U);
|
||||
}
|
||||
|
||||
/*!
|
||||
@@ -1337,7 +1488,7 @@ static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_
|
||||
static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll)
|
||||
{
|
||||
return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >>
|
||||
CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == kCLOCK_PllClkSrc24M) ?
|
||||
CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == (uint32_t)kCLOCK_PllClkSrc24M) ?
|
||||
CLOCK_GetOscFreq() :
|
||||
CLKPN_FREQ;
|
||||
}
|
||||
@@ -1547,18 +1698,45 @@ bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
|
||||
*/
|
||||
void CLOCK_DisableUsbhs1PhyPllClock(void);
|
||||
|
||||
/*!
|
||||
* @brief Use DWT to delay at least for some time.
|
||||
* Please note that, this API will calculate the microsecond period with the maximum
|
||||
* supported CPU frequency, so this API will only delay for at least the given microseconds, if precise
|
||||
* delay count was needed, please implement a new timer count to achieve this function.
|
||||
*
|
||||
* @param delay_us Delay time in unit of microsecond.
|
||||
*/
|
||||
void SDK_DelayAtLeastUs(uint32_t delay_us);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Clock Output Inferfaces
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Set the clock source and the divider of the clock output1.
|
||||
*
|
||||
* @param selection The clock source to be output, please refer to @ref clock_output1_selection_t.
|
||||
* @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
|
||||
*/
|
||||
void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider);
|
||||
|
||||
/*!
|
||||
* @brief Set the clock source and the divider of the clock output2.
|
||||
*
|
||||
* @param selection The clock source to be output, please refer to @ref clock_output2_selection_t.
|
||||
* @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
|
||||
*/
|
||||
void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider);
|
||||
|
||||
/*!
|
||||
* @brief Get the frequency of clock output1 clock signal.
|
||||
*
|
||||
* @return The frequency of clock output1 clock signal.
|
||||
*/
|
||||
uint32_t CLOCK_GetClockOutCLKO1Freq(void);
|
||||
|
||||
/*!
|
||||
* @brief Get the frequency of clock output2 clock signal.
|
||||
*
|
||||
* @return The frequency of clock output2 clock signal.
|
||||
*/
|
||||
uint32_t CLOCK_GetClockOutClkO2Freq(void);
|
||||
|
||||
/*! @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
@@ -47,7 +47,7 @@
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief common driver version 2.0.1. */
|
||||
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
|
||||
/*@}*/
|
||||
|
||||
/* Debug console type definition. */
|
||||
@@ -131,6 +131,7 @@ enum _status_groups
|
||||
kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
|
||||
kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */
|
||||
kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */
|
||||
kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */
|
||||
kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */
|
||||
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
|
||||
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
|
||||
@@ -157,6 +158,9 @@ enum _status_groups
|
||||
kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */
|
||||
kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */
|
||||
kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */
|
||||
kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */
|
||||
kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/
|
||||
kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */
|
||||
};
|
||||
|
||||
/*! @brief Generic status return codes. */
|
||||
@@ -174,20 +178,6 @@ enum _generic_status
|
||||
/*! @brief Type used for all status and error return values. */
|
||||
typedef int32_t status_t;
|
||||
|
||||
/*
|
||||
* The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
|
||||
* defined in previous of this file.
|
||||
*/
|
||||
#include "fsl_clock.h"
|
||||
|
||||
/*
|
||||
* Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
|
||||
*/
|
||||
#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
|
||||
(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
|
||||
#include "fsl_reset.h"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Macro guard for whether to use default weak IRQ implementation in drivers
|
||||
*/
|
||||
@@ -198,11 +188,11 @@ typedef int32_t status_t;
|
||||
/*! @name Min/max macros */
|
||||
/* @{ */
|
||||
#if !defined(MIN)
|
||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
#if !defined(MAX)
|
||||
#define MAX(a, b) ((a) > (b) ? (a) : (b))
|
||||
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
@@ -394,6 +384,21 @@ _Pragma("diag_suppress=Pm120")
|
||||
#error Toolchain not supported.
|
||||
#endif /* defined(__ICCARM__) */
|
||||
/* @} */
|
||||
|
||||
/*
|
||||
* The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
|
||||
* defined in previous of this file.
|
||||
*/
|
||||
#include "fsl_clock.h"
|
||||
|
||||
/*
|
||||
* Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
|
||||
*/
|
||||
#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
|
||||
(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
|
||||
#include "fsl_reset.h"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
@@ -489,6 +494,9 @@ _Pragma("diag_suppress=Pm120")
|
||||
*/
|
||||
static inline uint32_t DisableGlobalIRQ(void)
|
||||
{
|
||||
#if defined (__XCC__)
|
||||
return 0;
|
||||
#else
|
||||
#if defined(CPSR_I_Msk)
|
||||
uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
|
||||
|
||||
@@ -501,6 +509,7 @@ _Pragma("diag_suppress=Pm120")
|
||||
__disable_irq();
|
||||
|
||||
return regPrimask;
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -516,10 +525,13 @@ _Pragma("diag_suppress=Pm120")
|
||||
*/
|
||||
static inline void EnableGlobalIRQ(uint32_t primask)
|
||||
{
|
||||
#if defined (__XCC__)
|
||||
#else
|
||||
#if defined(CPSR_I_Msk)
|
||||
__set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
|
||||
#else
|
||||
__set_PRIMASK(primask);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@@ -30,8 +30,8 @@
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief GPIO driver version 2.0.1. */
|
||||
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||
/*! @brief GPIO driver version 2.0.2. */
|
||||
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief GPIO direction definition. */
|
||||
|
||||
@@ -30,8 +30,8 @@
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief LPUART driver version 2.2.6. */
|
||||
#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 6))
|
||||
/*! @brief LPUART driver version 2.2.7. */
|
||||
#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 7))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief Error codes for the LPUART driver. */
|
||||
@@ -166,9 +166,8 @@ enum _lpuart_flags
|
||||
(LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */
|
||||
kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */
|
||||
#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
|
||||
kLPUART_LinBreakFlag =
|
||||
(int)(LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char
|
||||
detected and LIN circuit enabled */
|
||||
kLPUART_LinBreakFlag = (int)(LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break
|
||||
char detected and LIN circuit enabled */
|
||||
#endif
|
||||
kLPUART_RxActiveEdgeFlag =
|
||||
(LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */
|
||||
@@ -624,7 +623,7 @@ static inline uint8_t LPUART_ReadByte(LPUART_Type *base)
|
||||
return base->DATA;
|
||||
}
|
||||
#else
|
||||
return base->DATA;
|
||||
return (uint8_t)(base->DATA);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,570 @@
|
||||
/*
|
||||
* Copyright 2017-2020 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file fsl_romapi.h
|
||||
* @brief support flexspi norflash function
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2023-04-03
|
||||
*/
|
||||
|
||||
#ifndef _FSL_ROMAPI_H_
|
||||
#define _FSL_ROMAPI_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup romapi
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @brief ROMAPI version 1.1.1. */
|
||||
#define FSL_ROM_ROMAPI_VERSION (MAKE_VERSION(1U, 1U, 1U))
|
||||
/*! @brief ROM FLEXSPI NOR driver version 1.4.0. */
|
||||
#define FSL_ROM_FLEXSPINOR_DRIVER_VERSION (MAKE_VERSION(1U, 4U, 0U))
|
||||
|
||||
/*!
|
||||
* @name Common ROMAPI fearures info defines
|
||||
* @{
|
||||
*/
|
||||
/* @brief ROM has FLEXSPI NOR API. */
|
||||
#define FSL_ROM_HAS_FLEXSPINOR_API (1)
|
||||
/* @brief ROM has run bootloader API. */
|
||||
#define FSL_ROM_HAS_RUNBOOTLOADER_API (0)
|
||||
/* @brief ROM has FLEXSPI NOR get config API. */
|
||||
#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_GET_CONFIG (0)
|
||||
/* @brief ROM has flash init API. */
|
||||
#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_FLASH_INIT (1)
|
||||
/* @brief ROM has erase API. */
|
||||
#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE (1)
|
||||
/* @brief ROM has erase sector API. */
|
||||
#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR (1)
|
||||
/* @brief ROM has erase block API. */
|
||||
#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK (0)
|
||||
/* @brief ROM has erase all API. */
|
||||
#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL (1)
|
||||
/* @brief ROM has page program API. */
|
||||
#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_PAGE_PROGRAM (1)
|
||||
/* @brief ROM has update lut API. */
|
||||
#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT (1)
|
||||
/* @brief ROM has FLEXSPI command API. */
|
||||
#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER (1)
|
||||
|
||||
/*@}*/
|
||||
|
||||
#define kROM_StatusGroup_FLEXSPI 60U /*!< ROM FLEXSPI status group number.*/
|
||||
#define kROM_StatusGroup_FLEXSPINOR 200U /*!< ROM FLEXSPI NOR status group number.*/
|
||||
|
||||
#define FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||
|
||||
/*! @brief Generate bit mask */
|
||||
#define FSL_ROM_FLEXSPI_BITMASK(bit_offset) (1U << (bit_offset))
|
||||
|
||||
/*! @brief FLEXSPI memory config block related defintions */
|
||||
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) /*!< ascii "FCFB" Big Endian */
|
||||
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) /*!< V1.4.0 */
|
||||
|
||||
#define CMD_SDR 0x01U
|
||||
#define CMD_DDR 0x21U
|
||||
#define RADDR_SDR 0x02U
|
||||
#define RADDR_DDR 0x22U
|
||||
#define CADDR_SDR 0x03U
|
||||
#define CADDR_DDR 0x23U
|
||||
#define MODE1_SDR 0x04U
|
||||
#define MODE1_DDR 0x24U
|
||||
#define MODE2_SDR 0x05U
|
||||
#define MODE2_DDR 0x25U
|
||||
#define MODE4_SDR 0x06U
|
||||
#define MODE4_DDR 0x26U
|
||||
#define MODE8_SDR 0x07U
|
||||
#define MODE8_DDR 0x27U
|
||||
#define WRITE_SDR 0x08U
|
||||
#define WRITE_DDR 0x28U
|
||||
#define READ_SDR 0x09U
|
||||
#define READ_DDR 0x29U
|
||||
#define LEARN_SDR 0x0AU
|
||||
#define LEARN_DDR 0x2AU
|
||||
#define DATSZ_SDR 0x0BU
|
||||
#define DATSZ_DDR 0x2BU
|
||||
#define DUMMY_SDR 0x0CU
|
||||
#define DUMMY_DDR 0x2CU
|
||||
#define DUMMY_RWDS_SDR 0x0DU
|
||||
#define DUMMY_RWDS_DDR 0x2DU
|
||||
#define JMP_ON_CS 0x1FU
|
||||
#define STOP 0U
|
||||
|
||||
#define FLEXSPI_1PAD 0U
|
||||
#define FLEXSPI_2PAD 1U
|
||||
#define FLEXSPI_4PAD 2U
|
||||
#define FLEXSPI_8PAD 3U
|
||||
|
||||
/* Lookup table related defintions */
|
||||
#define NOR_CMD_INDEX_READ 0U
|
||||
#define NOR_CMD_INDEX_READSTATUS 1U
|
||||
#define NOR_CMD_INDEX_WRITEENABLE 2U
|
||||
#define NOR_CMD_INDEX_ERASESECTOR 3U
|
||||
#define NOR_CMD_INDEX_PAGEPROGRAM 4U
|
||||
#define NOR_CMD_INDEX_CHIPERASE 5U
|
||||
#define NOR_CMD_INDEX_DUMMY 6U
|
||||
#define NOR_CMD_INDEX_ERASEBLOCK 7U
|
||||
|
||||
/*!
|
||||
* NOR LUT sequence index used for default LUT assignment
|
||||
* NOTE:
|
||||
* The will take effect if the lut sequences are not customized.
|
||||
*/
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ 0U /*!< READ LUT sequence id in lookupTable stored in config block */
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1U /*!< Read Status LUT sequence id in lookupTable stored in config block */
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
|
||||
2U /*!< Read status DPI/QPI/OPI sequence id in lookupTable stored in config block */
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3U /*!< Write Enable sequence id in lookupTable stored in config block */
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
|
||||
4U /*!< Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block */
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5U /*!< Erase Sector sequence id in lookupTable stored in config block */
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8U /*!< Erase Block sequence id in lookupTable stored in config block */
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9U /*!< Program sequence id in lookupTable stored in config block */
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11U /*!< Chip Erase sequence in lookupTable id stored in config block */
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13U /*!< Read SFDP sequence in lookupTable id stored in config block */
|
||||
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
|
||||
14U /*!< Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block */
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
|
||||
15U /*!< Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk */
|
||||
|
||||
/*!
|
||||
* @name Support for init FLEXSPI NOR configuration
|
||||
* @{
|
||||
*/
|
||||
/*! @brief Flash Pad Definitions */
|
||||
enum
|
||||
{
|
||||
kSerialFlash_1Pad = 1U,
|
||||
kSerialFlash_2Pads = 2U,
|
||||
kSerialFlash_4Pads = 4U,
|
||||
kSerialFlash_8Pads = 8U,
|
||||
};
|
||||
|
||||
/*! @brief FLEXSPI clock configuration type */
|
||||
enum
|
||||
{
|
||||
kFLEXSPIClk_SDR, /*!< Clock configure for SDR mode */
|
||||
kFLEXSPIClk_DDR, /*!< Clock configurat for DDR mode */
|
||||
};
|
||||
|
||||
/*! @brief FLEXSPI Read Sample Clock Source definition */
|
||||
enum _flexspi_read_sample_clk
|
||||
{
|
||||
kFLEXSPIReadSampleClk_LoopbackInternally = 0U,
|
||||
kFLEXSPIReadSampleClk_LoopbackFromDqsPad = 1U,
|
||||
kFLEXSPIReadSampleClk_LoopbackFromSckPad = 2U,
|
||||
kFLEXSPIReadSampleClk_ExternalInputFromDqsPad = 3U,
|
||||
};
|
||||
|
||||
/*! @brief Flash Type Definition */
|
||||
enum
|
||||
{
|
||||
kFLEXSPIDeviceType_SerialNOR = 1U, /*!< Flash device is Serial NOR */
|
||||
};
|
||||
|
||||
/*! @brief Flash Configuration Command Type */
|
||||
enum
|
||||
{
|
||||
kDeviceConfigCmdType_Generic, /*!< Generic command, for example: configure dummy cycles, drive strength, etc */
|
||||
kDeviceConfigCmdType_QuadEnable, /*!< Quad Enable command */
|
||||
kDeviceConfigCmdType_Spi2Xpi, /*!< Switch from SPI to DPI/QPI/OPI mode */
|
||||
kDeviceConfigCmdType_Xpi2Spi, /*!< Switch from DPI/QPI/OPI to SPI mode */
|
||||
kDeviceConfigCmdType_Spi2NoCmd, /*!< Switch to 0-4-4/0-8-8 mode */
|
||||
kDeviceConfigCmdType_Reset, /*!< Reset device command */
|
||||
};
|
||||
|
||||
/*! @brief Defintions for FLEXSPI Serial Clock Frequency */
|
||||
enum _flexspi_serial_clk_freq
|
||||
{
|
||||
kFLEXSPISerialClk_NoChange = 0U,
|
||||
kFLEXSPISerialClk_30MHz = 1U,
|
||||
kFLEXSPISerialClk_50MHz = 2U,
|
||||
kFLEXSPISerialClk_60MHz = 3U,
|
||||
kFLEXSPISerialClk_75MHz = 4U,
|
||||
kFLEXSPISerialClk_80MHz = 5U,
|
||||
kFLEXSPISerialClk_100MHz = 6U,
|
||||
kFLEXSPISerialClk_133MHz = 7U,
|
||||
kFLEXSPISerialClk_166MHz = 8U,
|
||||
kFLEXSPISerialClk_200MHz = 9U,
|
||||
};
|
||||
|
||||
/*! @brief Misc feature bit definitions */
|
||||
enum
|
||||
{
|
||||
kFLEXSPIMiscOffset_DiffClkEnable = 0U, /*!< Bit for Differential clock enable */
|
||||
kFLEXSPIMiscOffset_Ck2Enable = 1U, /*!< Bit for CK2 enable */
|
||||
kFLEXSPIMiscOffset_ParallelEnable = 2U, /*!< Bit for Parallel mode enable */
|
||||
kFLEXSPIMiscOffset_WordAddressableEnable = 3U, /*!< Bit for Word Addressable enable */
|
||||
kFLEXSPIMiscOffset_SafeConfigFreqEnable = 4U, /*!< Bit for Safe Configuration Frequency enable */
|
||||
kFLEXSPIMiscOffset_PadSettingOverrideEnable = 5U, /*!< Bit for Pad setting override enable */
|
||||
kFLEXSPIMiscOffset_DdrModeEnable = 6U, /*!< Bit for DDR clock confiuration indication. */
|
||||
kFLEXSPIMiscOffset_UseValidTimeForAllFreq = 7U, /*!< Bit for DLLCR settings under all modes */
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
kSerialNorType_StandardSPI, /*!< Device that support Standard SPI and Extended SPI mode */
|
||||
kSerialNorType_HyperBus, /*!< Device that supports HyperBus only */
|
||||
kSerialNorType_XPI, /*!< Device that works under DPI, QPI or OPI mode */
|
||||
kSerialNorType_NoCmd, /*!< Device that works under No command mode (XIP mode/Performance Enhance
|
||||
mode/continous read mode) */
|
||||
};
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name FLEXSPI NOR Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @brief FLEXSPI LUT Sequence structure */
|
||||
typedef struct _flexspi_lut_seq
|
||||
{
|
||||
uint8_t seqNum; /*!< Sequence Number, valid number: 1-16 */
|
||||
uint8_t seqId; /*!< Sequence Index, valid number: 0-15 */
|
||||
uint16_t reserved;
|
||||
} flexspi_lut_seq_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t time_100ps; /*!< Data valid time, in terms of 100ps */
|
||||
uint8_t delay_cells; /*!< Data valid time, in terms of delay cells */
|
||||
} flexspi_dll_time_t;
|
||||
|
||||
/*! @brief FLEXSPI Memory Configuration Block */
|
||||
typedef struct _flexspi_mem_config
|
||||
{
|
||||
uint32_t tag; /*!< [0x000-0x003] Tag, fixed value 0x42464346UL */
|
||||
uint32_t version; /*!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */
|
||||
uint32_t reserved0; /*!< [0x008-0x00b] Reserved for future use */
|
||||
uint8_t readSampleClkSrc; /*!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */
|
||||
uint8_t csHoldTime; /*!< [0x00d-0x00d] Data hold time, default value: 3 */
|
||||
uint8_t csSetupTime; /*!< [0x00e-0x00e] Date setup time, default value: 3 */
|
||||
uint8_t columnAddressWidth; /*!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||
Serial NAND, need to refer to datasheet */
|
||||
uint8_t deviceModeCfgEnable; /*!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */
|
||||
uint8_t deviceModeType; /*!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||
Generic configuration, etc. */
|
||||
uint16_t waitTimeCfgCommands; /*!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||
DPI/QPI/OPI switch or reset command */
|
||||
flexspi_lut_seq_t deviceModeSeq; /*!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
|
||||
sequence number, [31:16] Reserved */
|
||||
uint32_t deviceModeArg; /*!< [0x018-0x01b] Argument/Parameter for device configuration */
|
||||
uint8_t configCmdEnable; /*!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */
|
||||
uint8_t configModeType[3]; /*!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */
|
||||
flexspi_lut_seq_t
|
||||
configCmdSeqs[3]; /*!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq */
|
||||
uint32_t reserved1; /*!< [0x02c-0x02f] Reserved for future use */
|
||||
uint32_t configCmdArgs[3]; /*!< [0x030-0x03b] Arguments/Parameters for device Configuration commands */
|
||||
uint32_t reserved2; /*!< [0x03c-0x03f] Reserved for future use */
|
||||
uint32_t controllerMiscOption; /*!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
|
||||
details */
|
||||
uint8_t deviceType; /*!< [0x044-0x044] Device Type: See Flash Type Definition for more details */
|
||||
uint8_t sflashPadType; /*!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */
|
||||
uint8_t serialClkFreq; /*!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
|
||||
Chapter for more details */
|
||||
uint8_t
|
||||
lutCustomSeqEnable; /*!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||
be done using 1 LUT sequence, currently, only applicable to HyperFLASH */
|
||||
uint32_t reserved3[2]; /*!< [0x048-0x04f] Reserved for future use */
|
||||
uint32_t sflashA1Size; /*!< [0x050-0x053] Size of Flash connected to A1 */
|
||||
uint32_t sflashA2Size; /*!< [0x054-0x057] Size of Flash connected to A2 */
|
||||
uint32_t sflashB1Size; /*!< [0x058-0x05b] Size of Flash connected to B1 */
|
||||
uint32_t sflashB2Size; /*!< [0x05c-0x05f] Size of Flash connected to B2 */
|
||||
uint32_t csPadSettingOverride; /*!< [0x060-0x063] CS pad setting override value */
|
||||
uint32_t sclkPadSettingOverride; /*!< [0x064-0x067] SCK pad setting override value */
|
||||
uint32_t dataPadSettingOverride; /*!< [0x068-0x06b] data pad setting override value */
|
||||
uint32_t dqsPadSettingOverride; /*!< [0x06c-0x06f] DQS pad setting override value */
|
||||
uint32_t timeoutInMs; /*!< [0x070-0x073] Timeout threshold for read status command */
|
||||
uint32_t commandInterval; /*!< [0x074-0x077] CS deselect interval between two commands */
|
||||
flexspi_dll_time_t dataValidTime[2]; /*!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B */
|
||||
uint16_t busyOffset; /*!< [0x07c-0x07d] Busy offset, valid value: 0-31 */
|
||||
uint16_t busyBitPolarity; /*!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||
busy flag is 0 when flash device is busy */
|
||||
uint32_t lookupTable[64]; /*!< [0x080-0x17f] Lookup table holds Flash command sequences */
|
||||
flexspi_lut_seq_t lutCustomSeq[12]; /*!< [0x180-0x1af] Customizable LUT Sequences */
|
||||
uint32_t reserved4[4]; /*!< [0x1b0-0x1bf] Reserved for future use */
|
||||
} flexspi_mem_config_t;
|
||||
|
||||
/*! @brief Serial NOR configuration block */
|
||||
typedef struct _flexspi_nor_config
|
||||
{
|
||||
flexspi_mem_config_t memConfig; /*!< Common memory configuration info via FLEXSPI */
|
||||
uint32_t pageSize; /*!< Page size of Serial NOR */
|
||||
uint32_t sectorSize; /*!< Sector size of Serial NOR */
|
||||
uint8_t ipcmdSerialClkFreq; /*!< Clock frequency for IP command */
|
||||
uint8_t isUniformBlockSize; /*!< Sector/Block size is the same */
|
||||
uint8_t isDataOrderSwapped; /*!< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */
|
||||
uint8_t reserved0[1]; /*!< Reserved for future use */
|
||||
uint8_t serialNorType; /*!< Serial NOR Flash type: 0/1/2/3 */
|
||||
uint8_t needExitNoCmdMode; /*!< Need to exit NoCmd mode before other IP command */
|
||||
uint8_t halfClkForNonReadCmd; /*!< Half the Serial Clock for non-read command: true/false */
|
||||
uint8_t needRestoreNoCmdMode; /*!< Need to Restore NoCmd mode after IP commmand execution */
|
||||
uint32_t blockSize; /*!< Block size */
|
||||
uint32_t reserve2[11]; /*!< Reserved for future use */
|
||||
} flexspi_nor_config_t;
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*! @brief Manufacturer ID */
|
||||
enum
|
||||
{
|
||||
kSerialFlash_ISSI_ManufacturerID = 0x9DU, /*!< Manufacturer ID of the ISSI serial flash */
|
||||
kSerialFlash_Adesto_ManufacturerID = 0x1F, /*!< Manufacturer ID of the Adesto Technologies serial flash*/
|
||||
kSerialFlash_Winbond_ManufacturerID = 0xEFU, /*!< Manufacturer ID of the Winbond serial flash */
|
||||
kSerialFlash_Cypress_ManufacturerID = 0x01U, /*!< Manufacturer ID for Cypress */
|
||||
};
|
||||
|
||||
/*! @brief ROM FLEXSPI NOR flash status */
|
||||
enum _flexspi_nor_status
|
||||
{
|
||||
kStatus_ROM_FLEXSPI_SequenceExecutionTimeout =
|
||||
MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 0), /*!< Status for Sequence Execution timeout */
|
||||
kStatus_ROM_FLEXSPI_InvalidSequence = MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 1), /*!< Status for Invalid Sequence */
|
||||
kStatus_ROM_FLEXSPI_DeviceTimeout = MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 2), /*!< Status for Device timeout */
|
||||
kStatus_FLEXSPINOR_DTRRead_DummyProbeFailed =
|
||||
MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 10), /*!< Status for DDR Read dummy probe failure */
|
||||
kStatus_ROM_FLEXSPINOR_SFDP_NotFound =
|
||||
MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 7), /*!< Status for SFDP read failure */
|
||||
kStatus_ROM_FLEXSPINOR_Flash_NotFound =
|
||||
MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 9), /*!< Status for Flash detection failure */
|
||||
};
|
||||
|
||||
typedef enum _flexspi_operation
|
||||
{
|
||||
kFLEXSPIOperation_Command, /*!< FLEXSPI operation: Only command, both TX and RX buffer are ignored. */
|
||||
kFLEXSPIOperation_Config, /*!< FLEXSPI operation: Configure device mode, the TX FIFO size is fixed in LUT. */
|
||||
kFLEXSPIOperation_Write, /*!< FLEXSPI operation: Write, only TX buffer is effective */
|
||||
kFLEXSPIOperation_Read, /*!< FLEXSPI operation: Read, only Rx Buffer is effective. */
|
||||
kFLEXSPIOperation_End = kFLEXSPIOperation_Read,
|
||||
} flexspi_operation_t;
|
||||
|
||||
/*! @brief FLEXSPI Transfer Context */
|
||||
typedef struct _flexspi_xfer
|
||||
{
|
||||
flexspi_operation_t operation; /*!< FLEXSPI operation */
|
||||
uint32_t baseAddress; /*!< FLEXSPI operation base address */
|
||||
uint32_t seqId; /*!< Sequence Id */
|
||||
uint32_t seqNum; /*!< Sequence Number */
|
||||
bool isParallelModeEnable; /*!< Is a parallel transfer */
|
||||
uint32_t *txBuffer; /*!< Tx buffer */
|
||||
uint32_t txSize; /*!< Tx size in bytes */
|
||||
uint32_t *rxBuffer; /*!< Rx buffer */
|
||||
uint32_t rxSize; /*!< Rx size in bytes */
|
||||
} flexspi_xfer_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/*!
|
||||
* @name Initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initialize Serial NOR flash via FLEXSPI
|
||||
*
|
||||
* This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs.
|
||||
*
|
||||
* @param instance storge the instance of FLEXSPI.
|
||||
* @param config A pointer to the storage for the driver runtime state.
|
||||
*
|
||||
* @retval kStatus_Success Api was executed succesfuly.
|
||||
* @retval kStatus_InvalidArgument A invalid argument is provided.
|
||||
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
|
||||
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
|
||||
* @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
|
||||
*/
|
||||
status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config);
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Programming
|
||||
* @{
|
||||
*/
|
||||
/*!
|
||||
* @brief Program data to Serial NOR flash via FLEXSPI.
|
||||
*
|
||||
* This function programs the NOR flash memory with the dest address for a given
|
||||
* flash area as determined by the dst address and the length.
|
||||
*
|
||||
* @param instance storge the instance of FLEXSPI.
|
||||
* @param config A pointer to the storage for the driver runtime state.
|
||||
* @param dstAddr A pointer to the desired flash memory to be programmed.
|
||||
* NOTE:
|
||||
* It is recommended that use page aligned access;
|
||||
* If the dstAddr is not aligned to page,the driver automatically
|
||||
* aligns address down with the page address.
|
||||
* @param src A pointer to the source buffer of data that is to be programmed
|
||||
* into the NOR flash.
|
||||
*
|
||||
* @retval kStatus_Success Api was executed succesfuly.
|
||||
* @retval kStatus_InvalidArgument A invalid argument is provided.
|
||||
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
|
||||
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
|
||||
* @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
|
||||
*/
|
||||
status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance,
|
||||
flexspi_nor_config_t *config,
|
||||
uint32_t dstAddr,
|
||||
const uint32_t *src);
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Erasing
|
||||
* @{
|
||||
*/
|
||||
#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR
|
||||
/*!
|
||||
* @brief Erase one sector specified by address
|
||||
*
|
||||
* This function erases one of NOR flash sectors based on the desired address.
|
||||
*
|
||||
* @param instance storge the index of FLEXSPI.
|
||||
* @param config A pointer to the storage for the driver runtime state.
|
||||
* @param address The start address of the desired NOR flash memory to be erased.
|
||||
* NOTE:
|
||||
* It is recommended that use sector-aligned access nor device;
|
||||
* If dstAddr is not aligned with the sector,The driver automatically
|
||||
* aligns address down with the sector address.
|
||||
*
|
||||
* @retval kStatus_Success Api was executed succesfuly.
|
||||
* @retval kStatus_InvalidArgument A invalid argument is provided.
|
||||
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
|
||||
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
|
||||
* @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
|
||||
*/
|
||||
status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
|
||||
#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR */
|
||||
|
||||
#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL
|
||||
/*!
|
||||
* @brief Erase all the Serial NOR flash connected on FLEXSPI.
|
||||
*
|
||||
* @param instance storge the instance of FLEXSPI.
|
||||
* @param config A pointer to the storage for the driver runtime state.
|
||||
*
|
||||
* @retval kStatus_Success Api was executed succesfuly.
|
||||
* @retval kStatus_InvalidArgument A invalid argument is provided.
|
||||
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
|
||||
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
|
||||
* @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
|
||||
*/
|
||||
status_t ROM_FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config);
|
||||
#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL */
|
||||
|
||||
/*!
|
||||
* @brief Erase Flash Region specified by address and length
|
||||
*
|
||||
* This function erases the appropriate number of flash sectors based on the
|
||||
* desired start address and length.
|
||||
*
|
||||
* @param instance storge the index of FLEXSPI.
|
||||
* @param config A pointer to the storage for the driver runtime state.
|
||||
* @param start The start address of the desired NOR flash memory to be erased.
|
||||
* NOTE:
|
||||
* It is recommended that use sector-aligned access NOR flash;
|
||||
* If dstAddr is not aligned with the sector,the driver automatically
|
||||
* aligns address down with the sector address.
|
||||
* @param length The length, given in bytes to be erased.
|
||||
* NOTE:
|
||||
* It is recommended that use sector-aligned access NOR flash;
|
||||
* If length is not aligned with the sector,the driver automatically
|
||||
* aligns up with the sector.
|
||||
* @retval kStatus_Success Api was executed succesfuly.
|
||||
* @retval kStatus_InvalidArgument A invalid argument is provided.
|
||||
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
|
||||
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
|
||||
* @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
|
||||
*/
|
||||
status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length);
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name Command
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER
|
||||
/*!
|
||||
* @brief FLEXSPI command
|
||||
*
|
||||
* This function is used to perform the command write sequence to the NOR flash.
|
||||
*
|
||||
* @param instance storge the index of FLEXSPI.
|
||||
* @param xfer A pointer to the storage FLEXSPI Transfer Context.
|
||||
*
|
||||
* @retval kStatus_Success Api was executed succesfuly.
|
||||
* @retval kStatus_InvalidArgument A invalid argument is provided.
|
||||
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
|
||||
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
|
||||
*/
|
||||
status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer);
|
||||
#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name UpdateLut
|
||||
* @{
|
||||
*/
|
||||
#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT
|
||||
/*!
|
||||
* @brief Configure FLEXSPI Lookup table
|
||||
*
|
||||
* @param instance storge the index of FLEXSPI.
|
||||
* @param seqIndex storge the sequence Id.
|
||||
* @param lutBase A pointer to the look-up-table for command sequences.
|
||||
* @param seqNumber storge sequence number.
|
||||
*
|
||||
* @retval kStatus_Success Api was executed succesfuly.
|
||||
* @retval kStatus_InvalidArgument A invalid argument is provided.
|
||||
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
|
||||
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
|
||||
*/
|
||||
status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance,
|
||||
uint32_t seqIndex,
|
||||
const uint32_t *lutBase,
|
||||
uint32_t seqNumber);
|
||||
#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name ClearCache
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Software reset for the FLEXSPI logic.
|
||||
*
|
||||
* This function sets the software reset flags for both AHB and buffer domain and
|
||||
* resets both AHB buffer and also IP FIFOs.
|
||||
*
|
||||
* @param instance storge the index of FLEXSPI.
|
||||
*/
|
||||
void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance);
|
||||
|
||||
/*@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_ROMAPI_H_ */
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright 2018-2020 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file mcuboot.h
|
||||
* @brief support bootloader function
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2023-04-03
|
||||
*/
|
||||
|
||||
#ifndef __MCUBOOT_H__
|
||||
#define __MCUBOOT_H__
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "board.h"
|
||||
#include "pin_mux.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "fsl_lpuart.h"
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user