diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_zynq7000-zc702/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_zynq7000-zc702/boot.S
index afe0c13a2..e2b2b5ca1 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_zynq7000-zc702/boot.S
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_zynq7000-zc702/boot.S
@@ -140,7 +140,7 @@ OKToRun:
 	mcr	p15, 0, r0, c8, c7, 0		/* invalidate TLBs */
 	mcr	p15, 0, r0, c7, c5, 0		/* invalidate icache */
 	mcr	p15, 0, r0, c7, c5, 6		/* Invalidate branch predictor array */
-	bl	invalidate_dcache		/* invalidate dcache */
+	bl	boot_invalidate_dcache		/* invalidate dcache */
 
 	/* Disable MMU, if enabled */
 	mrc	p15, 0, r0, c1, c0, 0		/* read CP15 register 1 */
@@ -193,14 +193,14 @@ OKToRun:
 /*
  *************************************************************************
  *
- * invalidate_dcache - invalidate the entire d-cache by set/way
+ * boot_invalidate_dcache - invalidate the entire d-cache by set/way
  *
  * Note: for Cortex-A9, there is no cp instruction for invalidating
  * the whole D-cache. Need to invalidate each line.
  *
  *************************************************************************
  */
-invalidate_dcache:
+boot_invalidate_dcache:
 	mrc	p15, 1, r0, c0, c0, 1		/* read CLIDR */
 	ands	r3, r0, #0x7000000
 	mov	r3, r3, lsr #23			/* cache level value (naturally aligned) */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_zynq7000-zc702/zynq7000-zc702.lds b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_zynq7000-zc702/zynq7000-zc702.lds
index b2658b6f5..e7293cbfe 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_zynq7000-zc702/zynq7000-zc702.lds
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_zynq7000-zc702/zynq7000-zc702.lds
@@ -36,8 +36,6 @@ SECTIONS
 	.start_sec : {
 		. = ALIGN(0x1000);
 
-		*(.vectors)
-
 		/* read only area. */
 		boot.o(.text)
 		xil-crt0.o(.text .text.*)
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/xil_uart.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/xil_uart.c
index 86a853184..3f462a337 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/xil_uart.c
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/xil_uart.c
@@ -50,6 +50,7 @@
  *****************************************************************************/
 
 /***************************** Include Files ********************************/
+#include "xparameters.h"
 #include "xuartps_hw.h"
 
 #include "mmio_access.h"
@@ -176,8 +177,6 @@ void XUartPs_ResetHw(u32 BaseAddress)
         ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS | (u32)XUARTPS_CR_STOPBRK));
 }
 
-#define STDIN_BASEADDRESS 0xE0001000
-#define STDOUT_BASEADDRESS 0xE0001000
 void UartPutChar(uint8_t ch)
 {
     if (ch == '\n') {
diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable.c
index f80a9712a..0ad42a9e3 100644
--- a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable.c
+++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable.c
@@ -288,7 +288,6 @@ void load_kern_pgdir(struct TraceTag* mmu_driver_tag, struct TraceTag* intr_driv
     uintptr_t dev_attr = 0;
     _p_pgtbl_mmu_access->MmuDevPteAttr(&dev_attr);
 
-    _map_pages((uintptr_t*)kern_pgdir.pd_addr, PHY_MEM_BASE, PHY_MEM_BASE, (PHY_MEM_STOP - PHY_MEM_BASE), kern_attr);
     // kern mem
     _map_pages((uintptr_t*)kern_pgdir.pd_addr, KERN_MEM_BASE, PHY_MEM_BASE, (PHY_MEM_STOP - PHY_MEM_BASE), kern_attr);
     // dev mem
diff --git a/Ubiquitous/XiZi_AIoT/softkernel/task/task.c b/Ubiquitous/XiZi_AIoT/softkernel/task/task.c
index 57827b03b..b90cc944e 100644
--- a/Ubiquitous/XiZi_AIoT/softkernel/task/task.c
+++ b/Ubiquitous/XiZi_AIoT/softkernel/task/task.c
@@ -198,9 +198,7 @@ static void _scheduler(struct SchedulerRightGroup right_group)
 
         struct CPU* cpu = cur_cpu();
         cpu->task = next_task;
-        // DEBUG("%s %d\n", __func__, __LINE__);
         context_switch(&cpu->scheduler, next_task->main_thread.context);
-        // DEBUG("%s %d\n", __func__, __LINE__);
     }
 }