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Support armv8.(TODO: fix clock)

This commit is contained in:
TXuian 2024-05-28 10:54:21 +08:00
parent 71cf0c667c
commit 6114b4618f
32 changed files with 148 additions and 464 deletions
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134
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/boot.S
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@ -11,125 +11,6 @@
.global _boot_start
.global primary_cpu_init
//_entry:
// mrs x1, mpidr_el1
// and x1, x1, #0x3
// cbz x1, entry // primary
# b entryothers // secondary
//entry:
// clear .bss
// adrp x1, __bss_start__
// ldr w2, =bss_size
// 1:
// // cbz w2, 2f
// str xzr, [x1], #8
// sub w2, w2, #1
// b 1b
// 2:
// // set up entry pagetable
// //
// // Phase 1.
// // map the kernel code identically.
// // map [0x40000000,PA(end)) to [0x40000000,PA(end))
// // memory type is normal
// //
// // Phase 2.
// // map the kernel code.
// // map [0xffffff8040000000,VA(end)) to [0x40000000,PA(end))
// // memory type is normal.
// // Phase 1
// // map [0x40000000,PA(end)) to [0x40000000,PA(end))
// adrp x0, l2entrypgt
// mov x1, #0x00000000
// ldr x2, =V2P_WO(end)-1
// lsr x3, x1, #PXSHIFT(2)
// and x3, x3, #PXMASK // PX(2, x1)
// lsr x4, x2, #PXSHIFT(2)
// and x4, x4, #PXMASK // PX(2, x2)
// mov x5, #(PTE_AF | PTE_INDX(AI_NORMAL_NC_IDX) | PTE_VALID) // entry attr
// orr x6, x1, x5 // block entry
// l2epgt_loop:
// str x6, [x0, x3, lsl #3] // l2entrypgt[l2idx] = block entry
// add x3, x3, #1 // next index
// add x6, x6, #0x200000 // next block, block size is 2MB
// cmp x3, x4
// b.ls l2epgt_loop // if start va idx <= end va idx
// adrp x0, l1entrypgt
// lsr x3, x1, #PXSHIFT(1)
// and x3, x3, #PXMASK // start va level1 index
// mov x4, #(PTE_TABLE | PTE_VALID) // entry attr
// adrp x5, l2entrypgt
// orr x6, x4, x5 // table entry
// str x6, [x0, x3, lsl #3] // l1entrypgt[l1idx] = table entry
// // Phase 2
// // map [0xffffff8040000000,VA(end)) to [0x40000000,PA(end))
// adrp x0, l2kpgt
// mov x1, #0x00000000 // start pa
// ldr x2, =V2P_WO(end)-1 // end pa
// mov x3, #KERN_MEM_BASE
// add x4, x1, x3 // start va
// add x5, x2, x3 // end va
// lsr x6, x4, #PXSHIFT(2)
// and x6, x6, #PXMASK // x6 = PX(2,x4)
// lsr x7, x5, #PXSHIFT(2)
// and x7, x7, #PXMASK // x7 = PX(2,x5)
// mov x8, #(PTE_AF | PTE_INDX(AI_NORMAL_NC_IDX) | PTE_VALID) // entry attr
// orr x9, x1, x8 // block entry
// l2kpgt_loop:
// str x9, [x0, x6, lsl #3] // l2entrypgt[l2idx] = block entry
// add x6, x6, #1 // next index
// add x9, x9, #0x200000 // next block, block size is 2MB
// cmp x6, x7
// b.ls l2kpgt_loop // if start va idx <= end va idx
// adrp x0, l1kpgt
// lsr x5, x4, #PXSHIFT(1)
// and x5, x5, #PXMASK // x5 = PX(1,x4)
// mov x6, #(PTE_TABLE | PTE_VALID) // entry attr
// adrp x7, l2kpgt
// orr x8, x6, x7 // table entry
// str x8, [x0, x5, lsl #3] // l1kpgt[l1idx] = table entry
// entryothers: // secondary CPU starts here
// // load pagetable
// adrp x0, l1entrypgt
// adrp x1, l1kpgt
// msr ttbr0_el1, x0
// msr ttbr1_el1, x1
// // setup tcr
// ldr x0, =(TCR_T0SZ(25)|TCR_T1SZ(25)|TCR_TG0(0)|TCR_TG1(2)|TCR_IPS(0))
// msr tcr_el1, x0
// // setup mair
// ldr x1, =((MT_DEVICE_nGnRnE<<(8*AI_DEVICE_nGnRnE_IDX)) | (MT_NORMAL_NC<<(8*AI_NORMAL_NC_IDX)))
// msr mair_el1, x1
// ISB
// ldr x1, =_start // x1 = VA(_start)
// // enable paging
// mrs x0, sctlr_el1
// orr x0, x0, #1
// msr sctlr_el1, x0
// br x1 // jump to higher address (0xffffff8000000000~)
_boot_start:
// set up a stack for C.
// stack0 is declared in start.c,
@ -138,7 +19,8 @@ _boot_start:
// cpuid = mpidr_el1 & 0xff
// save r0 for cores 1-3, r0 arg field passed by ROM
// r0 is a function pointer for secondary cpus
mov x4, x0
// mov x4, x0
mrs x0, spsr_el1 /* Enter EL1 (Exception Level 1) */
bic x0, x0, #0x1f
@ -153,11 +35,6 @@ _boot_start:
MSR CPACR_EL1, X1
ISB
/* Clear A bit of SCTLR */
MRS x0, SCTLR_EL1
BIC x0, x0, #0x2
MSR SCTLR_EL1, x0
// clear some registers
msr elr_el1, XZR
@ -171,7 +48,7 @@ _boot_start:
mul x3, x2, x1
sub x0, x0, x3
MOV X2, #ARM_MODE_EL1_h | DIS_INT
MOV X2, #ARM_MODE_EL1_h | DIS_INT
MSR SPSR_EL1, X2
mov sp, x0
SUB x0, x0,x1
@ -199,11 +76,6 @@ primary_cpu_init:
mov x1, #0 // argv
mov x2, #0 // env
// jump to main()
//b main
//b . // spin
bl bootmain
.end

6
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/config.mk
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@ -1,11 +1,7 @@
export CROSS_COMPILE ?= aarch64-none-elf-
# export DEVICE = -march=armv8-a -mtune=cortex-a72 -ffreestanding -fno-common -nostdlib
export DEVICE = -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie
# export CFLAGS := $(DEVICE) -Wall -Werror -O0 -g -fno-omit-frame-pointer -fPIC
export CFLAGS := $(DEVICE) -O0 -g -fno-omit-frame-pointer -fPIC
export CFLAGS := $(DEVICE) -Wall -Werror -O0 -g -fno-omit-frame-pointer -fPIC
# export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2
# export LFLAGS := $(DEVICE) -Wl,-Map=XiZi-imx6q-sabrelite.map,-cref,-u,_boot_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_imx6q-sabrelite/nxp_imx6q_sabrelite.lds
# export LFLAGS := $(DEVICE) -mcmodel=large -Wl,-Map=XiZi-ok1028a-c.map,-cref,-u,_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds -Wl,--start-group,-lgcc,-lc,--end-group
export LFLAGS := $(DEVICE) -Wl,-T -Wl,$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds -Wl,--start-group,-lgcc,-lc,--end-group
export CXXFLAGS :=

11
Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/include/registers.h
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@ -1,3 +1,14 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#ifndef INC_SYSREGS_H_
#define INC_SYSREGS_H_

20
Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a72/ok1028a-c/clock.c
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@ -9,13 +9,14 @@
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include "actracer.h"
#include "core.h"
#include "generic_timer.h"
#include "clock_common_op.h"
#include "log.h"
// armv8 generic timer driver
#define CNTV_CTL_ENABLE (1 << 0)
@ -24,26 +25,23 @@
static void enable_timer()
{
uint64_t c = r_cntv_ctl_el0();
c |= CNTV_CTL_ENABLE;
c &= ~CNTV_CTL_IMASK;
uint32_t c = r_cntv_ctl_el0();
c = CNTV_CTL_ENABLE;
w_cntv_ctl_el0(c);
}
static void disable_timer()
{
uint64_t c = r_cntv_ctl_el0();
c &= ~CNTV_CTL_ENABLE;
c |= CNTV_CTL_IMASK;
uint32_t c = r_cntv_ctl_el0();
c = CNTV_CTL_IMASK;
w_cntv_ctl_el0(c);
}
static void reload_timer()
{
// interval 100ms
uint64_t interval = 100000;
uint64_t interval_clk = interval * (r_cntfrq_el0() / 1000000);
uint32_t interval = 100000;
uint32_t interval_clk = interval * (r_cntfrq_el0() / 1000000);
w_cntv_tval_el0(interval_clk);
}
@ -61,7 +59,7 @@ static uint32_t _get_clock_int()
static uint64_t _get_tick()
{
return 0;
return r_cntvct_el0();
}
static uint64_t _get_second()

16
Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv8-a/cortex-a72/ok1028a-c/include/generic_timer.h
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@ -15,26 +15,26 @@
#include <stdint.h>
// armv8 generic timer
static inline uint64_t r_cntv_ctl_el0()
static inline uint32_t r_cntv_ctl_el0()
{
uint64_t x;
uint32_t x;
__asm__ volatile("mrs %0, cntv_ctl_el0" : "=r"(x));
return x;
}
static inline void w_cntv_ctl_el0(uint64_t x)
static inline void w_cntv_ctl_el0(uint32_t x)
{
__asm__ volatile("msr cntv_ctl_el0, %0" : : "r"(x));
}
static inline uint64_t r_cntv_tval_el0()
static inline uint32_t r_cntv_tval_el0()
{
uint64_t x;
uint32_t x;
__asm__ volatile("mrs %0, cntv_tval_el0" : "=r"(x));
return x;
}
static inline void w_cntv_tval_el0(uint64_t x)
static inline void w_cntv_tval_el0(uint32_t x)
{
__asm__ volatile("msr cntv_tval_el0, %0" : : "r"(x));
}
@ -46,9 +46,9 @@ static inline uint64_t r_cntvct_el0()
return x;
}
static inline uint64_t r_cntfrq_el0()
static inline uint32_t r_cntfrq_el0()
{
uint64_t x;
uint32_t x;
__asm__ volatile("mrs %0, cntfrq_el0" : "=r"(x));
return x;
}

2
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/Makefile
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@ -1,3 +1,3 @@
SRC_FILES := gicv3.c gicv3_distributer.c
SRC_FILES := gicv3.c
include $(KERNEL_ROOT)/compiler.mk

63
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3.c
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@ -1,3 +1,14 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file gicv3.c
* @brief gicv3 operation
@ -25,47 +36,30 @@ static struct {
char* rdist_addrs[NR_CPU];
} gicv3;
static inline uint32_t
icc_igrpen1_el1()
static inline uint32_t icc_igrpen1_el1()
{
uint32_t x;
__asm__ volatile("mrs %0, S3_0_C12_C12_7" : "=r"(x));
return x;
}
static inline void
w_icc_igrpen1_el1(uint32_t x)
static inline void w_icc_igrpen1_el1(uint32_t x)
{
__asm__ volatile("msr S3_0_C12_C12_7, %0" : : "r"(x));
}
static inline uint32_t
icc_pmr_el1()
static inline uint32_t icc_pmr_el1()
{
uint32_t x;
__asm__ volatile("mrs %0, S3_0_C4_C6_0" : "=r"(x));
return x;
}
static inline void
w_icc_pmr_el1(uint32_t x)
static inline void w_icc_pmr_el1(uint32_t x)
{
__asm__ volatile("msr S3_0_C4_C6_0, %0" : : "r"(x));
}
// static inline uint32_t
// icc_iar1_el1()
// {
// uint32_t x;
// __asm__ volatile("mrs %0, S3_0_C12_C12_0" : "=r"(x));
// return x;
// }
// static inline void
// w_icc_eoir1_el1(uint32_t x)
// {
// __asm__ volatile("msr S3_0_C12_C12_1, %0" : : "r"(x));
// }
inline uint32_t gic_read_irq_ack()
{
uint32_t x;
@ -79,53 +73,45 @@ gic_write_end_of_irq(uint32_t x)
__asm__ volatile("msr S3_0_C12_C12_1, %0" : : "r"(x));
}
static inline uint32_t
icc_sre_el1()
static inline uint32_t icc_sre_el1()
{
uint32_t x;
__asm__ volatile("mrs %0, S3_0_C12_C12_5" : "=r"(x));
return x;
}
static inline void
w_icc_sre_el1(uint32_t x)
static inline void w_icc_sre_el1(uint32_t x)
{
__asm__ volatile("msr S3_0_C12_C12_5, %0" : : "r"(x));
}
static void
gicd_write(uint32_t off, uint32_t val)
static void gicd_write(uint32_t off, uint32_t val)
{
*(volatile uint32_t*)(gicv3.gicd + off) = val;
}
static uint32_t
gicd_read(uint32_t off)
static uint32_t gicd_read(uint32_t off)
{
return *(volatile uint32_t*)(gicv3.gicd + off);
}
static void
gicr_write(uint32_t cpuid, uint32_t off, uint32_t val)
static void gicr_write(uint32_t cpuid, uint32_t off, uint32_t val)
{
*(volatile uint32_t*)(gicv3.rdist_addrs[cpuid] + off) = val;
}
static uint32_t
gicr_read(uint32_t cpuid, uint32_t off)
static uint32_t gicr_read(uint32_t cpuid, uint32_t off)
{
return *(volatile uint32_t*)(gicv3.rdist_addrs[cpuid] + off);
}
static void
giccinit()
static void giccinit()
{
w_icc_igrpen1_el1(0);
w_icc_pmr_el1(0xff);
}
static void
gicdinit()
static void gicdinit()
{
gicd_write(D_CTLR, 0);
@ -136,8 +122,7 @@ gicdinit()
gicd_write(D_IGROUPR(i), ~0);
}
static void
gicrinit(uint32_t cpuid)
static void gicrinit(uint32_t cpuid)
{
gicr_write(cpuid, R_CTLR, 0);

64
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3_common_opa.h
View File

@ -32,59 +32,6 @@ Modification:
#include <mmio_access.h>
//! @addtogroup gic
//! @{
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//! @brief Options for sending a software generated interrupt.
//!
//! These options are used for the @a filter_list parameter of the gic_send_sgi()
//! function. They control how to select which CPUs that the interrupt is
//! sent to.
enum _gicd_sgi_filter {
//! Forward the interrupt to the CPU interfaces specified in the @a target_list parameter.
kGicSgiFilter_UseTargetList = 0,
//! Forward the interrupt to all CPU interfaces except that of the processor that requested
//! the interrupt.
kGicSgiFilter_AllOtherCPUs = 1,
//! Forward the interrupt only to the CPU interface of the processor that requested the
//! interrupt.
kGicSgiFilter_OnlyThisCPU = 2
};
////////////////////////////////////////////////////////////////////////////////
// API
////////////////////////////////////////////////////////////////////////////////
#if defined(__cplusplus)
extern "C" {
#endif
__attribute__((__always_inline__)) static inline uint32_t get_arm_private_peripheral_base()
{
return MMIO_P2V(0x00A00000);
}
__attribute__((__always_inline__)) static inline uint32_t irq_get_register_offset(uint32_t irqID)
{
return irqID / 32;
}
__attribute__((__always_inline__)) static inline uint32_t irq_get_bit_offset(uint32_t irqID)
{
return irqID & 0x1f;
}
__attribute__((__always_inline__)) static inline uint32_t irq_get_bit_mask(uint32_t irqID)
{
return 1 << irq_get_bit_offset(irqID);
}
//! @name Initialization
//@{
//! @brief Init interrupt handling.
@ -98,13 +45,6 @@ __attribute__((__always_inline__)) static inline uint32_t irq_get_bit_mask(uint3
//! that were pending are cleared, and all interrupts are made secure (group 0).
void gic_init(void);
//! @brief Init the current CPU's GIC interface.
//!
//! @post Enables the CPU interface and sets the priority mask to 255. Interrupt preemption
//! is disabled by setting the Binary Point to a value of 7.
void gic_init_cpu(void);
//@}
//! @name GIC Interrupt Distributor Functions
//@{
//! @brief Enable or disable the GIC Distributor.
@ -192,10 +132,6 @@ uint32_t gic_read_irq_ack(void);
void gic_write_end_of_irq(uint32_t irq_id);
//@}
#if defined(__cplusplus)
}
#endif
//! @}
////////////////////////////////////////////////////////////////////////////////

77
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3_distributer.c
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@ -1,77 +0,0 @@
/**
* @file gicv3_distributer.c
* @brief gicv3_distributer
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024.05.10
*/
/*************************************************
File name: gicv3_distributer.c
Description: gicv3_distributer operation
Others:
History:
Author: AIIT XUOS Lab
Modification:
*************************************************/
#include "string.h"
#include "gicv3_common_opa.h"
#include "gicv3_registers.h"
static inline gicd_t* gic_get_gicd(void)
{
uint64_t base = get_arm_private_peripheral_base() + kGICDBaseOffset;
return (gicd_t*)base;
}
void gic_set_cpu_target(uint32_t irqID, unsigned cpuNumber, bool enableIt)
{
// Make sure the CPU number is valid.
gicd_t* gicd = gic_get_gicd();
uint8_t cpuMask = 1 << cpuNumber;
if (enableIt) {
gicd->ITARGETSRn[irqID] |= (cpuMask & 0xff);
} else {
gicd->ITARGETSRn[irqID] &= ~(cpuMask & 0xff);
}
}
void gic_set_irq_security(uint32_t irqID, bool isSecure)
{
gicd_t* gicd = gic_get_gicd();
uint32_t reg = irq_get_register_offset(irqID);
uint32_t mask = irq_get_bit_mask(irqID);
uint32_t value = gicd->IGROUPRn[reg];
if (!isSecure) {
value &= ~mask;
} else {
value |= mask;
}
gicd->IGROUPRn[reg] = value;
}
void gic_enable_irq(uint32_t irqID, bool isEnabled)
{
gicd_t* gicd = gic_get_gicd();
uint32_t reg = irq_get_register_offset(irqID);
uint32_t mask = irq_get_bit_mask(irqID);
// Select set-enable or clear-enable register based on enable flag.
if (isEnabled) {
gicd->ISENABLERn[reg] = mask;
} else {
gicd->ICENABLERn[reg] = mask;
}
}
void gic_set_irq_priority(uint32_t ID, uint32_t priority)
{
gicd_t* gicd = gic_get_gicd();
gicd->IPRIORITYRn[ID] = priority & 0xff;
}

68
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3_registers.h
View File

@ -24,15 +24,14 @@ Modification:
1. Rename the file
*************************************************/
#ifndef __LINUX_IRQCHIP_ARM_GIC_H
#define __LINUX_IRQCHIP_ARM_GIC_H
#pragma once
#include "memlayout.h"
// clang-format off
// interrupt controller GICv3
#define GICV3 (DEV_VRTMEM_BASE + 0x08000000L)
#define GICV3_REDIST (DEV_VRTMEM_BASE + 0x080a0000L)
#define GICV3 MMIO_P2V_WO(0x08000000ULL)
#define GICV3_REDIST MMIO_P2V_WO(0x080a0000ULL)
#define D_CTLR 0x0
#define D_TYPER 0x4
@ -57,65 +56,4 @@ Modification:
#define R_ICFGR0 (SGI_BASE + 0xc00)
#define R_ICFGR1 (SGI_BASE + 0xc04)
#define R_IGRPMODR0 (SGI_BASE + 0xd00)
// clang-format on
#endif
#include <stdint.h>
enum _gic_base_offsets {
kGICDBaseOffset = 0x10000, //!< GIC distributor offset.
kGICCBaseOffset = 0x100 //!< GIC CPU interface offset.
};
//! @brief GIC distributor registers.
//!
//! Uses the GICv2 register names, but does not include GICv2 registers.
//!
//! The IPRIORITYRn and ITARGETSRn registers are byte accessible, so their types are uint8_t
//! instead of uint32_t to reflect this. These members are indexed directly with the interrupt
//! number.
struct _gicd_registers {
uint32_t CTLR; //!< Distributor Control Register.
uint32_t TYPER; //!< Interrupt Controller Type Register.
uint32_t IIDR; //!< Distributor Implementer Identification Register.
uint32_t _reserved0[29];
uint32_t IGROUPRn[8]; //!< Interrupt Group Registers.
uint32_t _reserved1[24];
uint32_t ISENABLERn[32]; //!< Interrupt Set-Enable Registers.
uint32_t ICENABLERn[32]; //!< Interrupt Clear-Enable Registers.
uint32_t ISPENDRn[32]; //!< Interrupt Set-Pending Registers.
uint32_t ICPENDRn[32]; //!< Interrupt Clear-Pending Registers.
uint32_t ICDABRn[32]; //!< Active Bit Registers.
uint32_t _reserved2[32];
uint8_t IPRIORITYRn[255 * sizeof(uint32_t)]; //!< Interrupt Priority Registers. (Byte accessible)
uint32_t _reserved3;
uint8_t ITARGETSRn[255 * sizeof(uint32_t)]; //!< Interrupt Processor Targets Registers. (Byte accessible)
uint32_t _reserved4;
uint32_t ICFGRn[64]; //!< Interrupt Configuration Registers.
uint32_t _reserved5[128];
uint32_t SGIR; //!< Software Generated Interrupt Register
};
//! @brief Bitfields constants for the GICD_CTLR register.
enum _gicd_ctlr_fields {
kBM_GICD_CTLR_EnableGrp1 = (1 << 1),
kBM_GICD_CTLR_EnableGrp0 = (1 << 0)
};
enum _gicd_sgir_fields {
kBP_GICD_SGIR_TargetListFilter = 24,
kBM_GICD_SGIR_TargetListFilter = (0x3 << kBP_GICD_SGIR_TargetListFilter),
kBP_GICD_SGIR_CPUTargetList = 16,
kBM_GICD_SGIR_CPUTargetList = (0xff << kBP_GICD_SGIR_CPUTargetList),
kBP_GICD_SGIR_NSATT = 15,
kBM_GICD_SGIR_NSATT = (1 << kBP_GICD_SGIR_NSATT),
kBP_GICD_SGIR_SGIINTID = 0,
kBM_GICD_SGIR_SGIINTID = 0xf
};
typedef volatile struct _gicd_registers gicd_t;

11
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/exception_registers.h
View File

@ -1,3 +1,14 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file exception_registers.h
* @brief exception registers

37
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/trap.c
View File

@ -41,18 +41,20 @@ extern void iabort_handler(struct trapframe* r);
void kernel_abort_handler(struct trapframe* tf)
{
uint64_t esr = r_esr_el1();
switch ((esr >> 26) & 0x3F) {
switch ((esr >> 0x1A) & 0x3F) {
case 0b100100:
case 0b100101:
dabort_handler(tf);
break;
case 0b100000:
case 0b100001:
iabort_handler(tf);
break;
default:
uint64_t ec = (esr >> 26) & 0x3f;
uint64_t iss = esr & 0x1ffffff;
ERROR("esr %p %p %p\n", esr, ec, iss);
ERROR("elr = %p far = %p\n", r_elr_el1(), r_far_el1());
ERROR("esr: %016lx %016lx %016lx\n", esr, ec, iss);
ERROR("elr = %016lx far = %016lx\n", r_elr_el1(), r_far_el1());
ERROR("Current Task: %s.\n", cur_cpu()->task->name);
panic("Unimplemented Error Occured.\n");
}
@ -67,11 +69,30 @@ void kernel_intr_handler(struct trapframe* tf)
extern void context_switch(struct context**, struct context*);
void syscall_arch_handler(struct trapframe* tf)
{
uint64_t ec = (r_esr_el1() >> 0x1A) & 0x3F;
if (ec == 0b010101) {
w_esr_el1(0);
uint64_t esr = r_esr_el1();
uint64_t ec = (esr >> 0x1A) & 0x3F;
w_esr_el1(0);
switch (ec) {
case 0B010101:
software_irq_dispatch(tf);
} else {
kernel_abort_handler(tf);
break;
case 0b100100:
case 0b100101:
dabort_handler(tf);
break;
case 0b100000:
case 0b100001:
iabort_handler(tf);
break;
default:
printf("USYSCALL: unexpected ec: %016lx", esr);
printf(" elr = %016lx far = %016lx\n", r_elr_el1(), r_far_el1());
// kill error task
xizi_enter_kernel();
assert(cur_cpu()->task != NULL);
sys_exit(cur_cpu()->task);
context_switch(&cur_cpu()->task->thread_context.context, cur_cpu()->scheduler);
panic("dabort end should never be reashed.\n");
}
}

16
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/trap_common.c
View File

@ -37,13 +37,6 @@ Modification:
#include "log.h"
#include "multicores.h"
extern void init_stack(uint64_t, uint64_t);
extern void user_trap_swi_enter(void);
extern void trap_iabort(void);
extern void trap_dabort(void);
extern void trap_irq_enter(void);
extern void trap_undefined_instruction(void);
static struct XiziTrapDriver xizi_trap_driver;
void panic(char* s)
@ -53,13 +46,6 @@ void panic(char* s)
;
}
/* stack for different mode*/
static char mode_stack_pages[NR_CPU][NR_MODE_STACKS][MODE_STACK_SIZE];
extern uint64_t _vector_jumper;
extern uint64_t _vector_start;
extern uint64_t _vector_end;
extern void alltraps();
static void _sys_irq_init(int cpu_id)
{
@ -84,7 +70,7 @@ static void _cpu_irq_disable(void)
static void _single_irq_enable(int irq, int cpu, int prio)
{
gic_setup_spi(cpu, irq);
gic_setup_spi((uint32_t)cpu, (uint32_t)irq);
}
static void _single_irq_disable(int irq, int cpu)

16
Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/trampoline.S
View File

@ -33,7 +33,6 @@ Modification:
#include "core.h"
.macro savereg
msr daifset, #0xf
// make room to save registers.
sub sp, sp, #272
@ -183,6 +182,7 @@ alltraps:
b .
el1sync:
msr daifset, #0xf
savereg
mov x0, sp
@ -190,12 +190,16 @@ el1sync:
b .
el1irq:
savereg
msr daifset, #0xf
usavereg
mov x0, sp
# this should never happen by design
bl kernel_intr_handler
b .
bl intr_irq_dispatch
urestorereg
msr daifclr, #0xf
eret
el0sync:
msr daifset, #0xf

27
Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/bootmmu.c
View File

@ -30,6 +30,7 @@ Modification:
#include "memlayout.h"
#include "mmio_access.h"
#include "mmu.h"
#include "pagetable.h"
#include "registers.h"
#include <stdint.h>
@ -38,20 +39,20 @@ Modification:
extern uint64_t kernel_data_end[];
extern uint64_t kernel_data_begin[];
#define NR_PDE_ENTRIES (1 << 9)
// clang-format off
#define L2_TYPE_TAB 2
#define L2_PTE_VALID 1
#define L2_TYPE_TAB 2
#define L2_PTE_VALID 1
#define L3_TYPE_TAB 2
#define L3_PTE_VALID 1
#define L3_TYPE_TAB 2
#define L3_PTE_VALID 1
#define L4_TYPE_PAGE (3 << 0)
#define L4_PTE_DEV ((0b00) << 2) // Device memory
#define L4_PTE_AF (1 << 10) // Data Access Permissions
#define L4_TYPE_PAGE (3 << 0)
#define L4_PTE_DEV ((0b00) << 2) // Device memory
#define L4_PTE_AF (1 << 10) // Data Access Permissions
#define IDX_MASK (0b111111111)
#define L3_PDE_INDEX(idx) ((idx << LEVEL3_PDE_SHIFT) & L3_IDX_MASK)
#define IDX_MASK (0b111111111)
#define L3_PDE_INDEX(idx) ((idx << LEVEL3_PDE_SHIFT) & L3_IDX_MASK)
// clang-format on
uint64_t boot_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x1000))) = { 0 };
@ -70,7 +71,7 @@ static void build_boot_pgdir()
boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
uint64_t cur_mem_paddr = (uint64_t)DEV_PHYMEM_BASE & ((uint64_t)IDX_MASK << (uint64_t)LEVEL2_PDE_SHIFT);
uint64_t cur_mem_paddr = ALIGNDOWN((uint64_t)DEV_PHYMEM_BASE, PAGE_SIZE);
for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
boot_dev_l3pgdir[i] = (uint64_t)boot_dev_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;
@ -85,7 +86,7 @@ static void build_boot_pgdir()
boot_l2pgdir[(PHY_MEM_BASE >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
boot_l2pgdir[(P2V_WO(PHY_MEM_BASE) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID;
cur_mem_paddr = (uint64_t)PHY_MEM_BASE & ((uint64_t)IDX_MASK << (uint64_t)LEVEL2_PDE_SHIFT);
cur_mem_paddr = ALIGNDOWN((uint64_t)PHY_MEM_BASE, PAGE_SIZE);
for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) {
boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID;

4
Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/ok1028a-c/memlayout.h
View File

@ -35,7 +35,7 @@ Modification:
/* A72 physical memory layout */
#define PHY_MEM_BASE (0x0000000040000000ULL)
#define PHY_USER_FREEMEM_BASE (0x0000000044000000ULL)
#define PHY_USER_FREEMEM_BASE (0x0000000046000000ULL)
#define PHY_USER_FREEMEM_TOP (0x0000000048000000ULL)
#define PHY_MEM_STOP (0x0000000048000000ULL)
@ -71,7 +71,7 @@ Modification:
#define USER_MEM_TOP DEV_VRTMEM_BASE
#define USER_IPC_SPACE_BASE (0x0000003000000000ULL)
#define USER_IPC_USE_ALLOCATOR_WATERMARK (0x0000003000010000ULL)
#define USER_IPC_SPACE_TOP (USER_MEM_TOP - USER_STACK_SIZE)
#define USER_IPC_SPACE_TOP (USER_IPC_SPACE_BASE + 0x10000000ULL)
/* Kernel memory layout */
#define KERN_MEM_BASE (0x0000006040000000ULL) // First kernel virtual address

2
Ubiquitous/XiZi_AIoT/services/app/Makefile
View File

@ -13,7 +13,7 @@ endif
ifeq ($(BOARD), ok1028a-c)
toolchain ?= aarch64-none-elf-
user_ldflags = -N -Ttext 0
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie -nostdlib -static -fno-builtin -nodefaultlibs -Wno-unused
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
board_specs = stub.o
endif

2
Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Makefile
View File

@ -11,7 +11,7 @@ endif
ifeq ($(BOARD), ok1028a-c)
toolchain ?= aarch64-none-elf-
user_ldflags = -N -Ttext 0
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie -nostdlib -static -fno-builtin -nodefaultlibs -Wno-unused
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
cc = ${toolchain}gcc

2
Ubiquitous/XiZi_AIoT/services/boards/ok1028a-c/Makefile
View File

@ -11,7 +11,7 @@ endif
ifeq ($(BOARD), ok1028a-c)
toolchain ?= aarch64-none-elf-
user_ldflags = -N -Ttext 0
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie -nostdlib -static -fno-builtin -nodefaultlibs -Wno-unused
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
cc = ${toolchain}gcc

2
Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/Makefile
View File

@ -12,7 +12,7 @@ endif
ifeq ($(BOARD), ok1028a-c)
toolchain ?= aarch64-none-elf-
user_ldflags = -N -Ttext 0
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie -nostdlib -static -fno-builtin -nodefaultlibs -Wno-unused
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
cc = ${toolchain}gcc

2
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/clock/Makefile
View File

@ -11,7 +11,7 @@ endif
ifeq ($(BOARD), ok1028a-c)
toolchain ?= aarch64-none-elf-
user_ldflags = -N -Ttext 0
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie -nostdlib -static -fno-builtin -nodefaultlibs -Wno-unused
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
cc = ${toolchain}gcc
ld = ${toolchain}g++

2
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/gpio/Makefile
View File

@ -11,7 +11,7 @@ endif
ifeq ($(BOARD), ok1028a-c)
toolchain ?= aarch64-none-elf-
user_ldflags = -N -Ttext 0
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie -nostdlib -static -fno-builtin -nodefaultlibs -Wno-unused
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
cc = ${toolchain}gcc

2
Ubiquitous/XiZi_AIoT/services/drivers/imx6q-sabrelite/lib/Makefile
View File

@ -11,7 +11,7 @@ endif
ifeq ($(BOARD), ok1028a-c)
toolchain ?= aarch64-none-elf-
user_ldflags = -N -Ttext 0
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie -nostdlib -static -fno-builtin -nodefaultlibs -Wno-unused
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
cc = ${toolchain}gcc

2
Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile
View File

@ -12,7 +12,7 @@ endif
ifeq ($(BOARD), ok1028a-c)
toolchain ?= aarch64-none-elf-
user_ldflags = -N
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie -nostdlib -static -fno-builtin -nodefaultlibs -Wno-unused
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
cc = ${toolchain}gcc

2
Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile
View File

@ -11,7 +11,7 @@ endif
ifeq ($(BOARD), ok1028a-c)
toolchain ?= aarch64-none-elf-
user_ldflags = -N
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie -nostdlib -static -fno-builtin -nodefaultlibs -Wno-unused
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
cc = ${toolchain}gcc

2
Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile
View File

@ -12,7 +12,7 @@ endif
ifeq ($(BOARD), ok1028a-c)
toolchain ?= aarch64-none-elf-
user_ldflags = -N -Ttext 0
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie -nostdlib -static -fno-builtin -nodefaultlibs -Wno-unused
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
cc = ${toolchain}gcc

2
Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile
View File

@ -11,7 +11,7 @@ endif
ifeq ($(BOARD), ok1028a-c)
toolchain ?= aarch64-none-elf-
user_ldflags = -N -Ttext 0
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie -nostdlib -static -fno-builtin -nodefaultlibs -Wno-unused
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
cc = ${toolchain}gcc

2
Ubiquitous/XiZi_AIoT/services/lib/serial/Makefile
View File

@ -11,7 +11,7 @@ endif
ifeq ($(BOARD), ok1028a-c)
toolchain ?= aarch64-none-elf-
user_ldflags = -N -Ttext 0
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie -nostdlib -static -fno-builtin -nodefaultlibs -Wno-unused
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
cc = ${toolchain}gcc

2
Ubiquitous/XiZi_AIoT/services/lib/usyscall/Makefile
View File

@ -11,7 +11,7 @@ endif
ifeq ($(BOARD), ok1028a-c)
toolchain ?= aarch64-none-elf-
user_ldflags = -N -Ttext 0
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie -nostdlib -static -fno-builtin -nodefaultlibs -Wno-unused
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
cc = ${toolchain}gcc

2
Ubiquitous/XiZi_AIoT/services/semaphore/Makefile
View File

@ -12,7 +12,7 @@ endif
ifeq ($(BOARD), ok1028a-c)
toolchain ?= aarch64-none-elf-
user_ldflags = -N -Ttext 0
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie -nostdlib -static -fno-builtin -nodefaultlibs -Wno-unused
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
cc = ${toolchain}gcc

2
Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile
View File

@ -11,7 +11,7 @@ endif
ifeq ($(BOARD), ok1028a-c)
toolchain ?= aarch64-none-elf-
user_ldflags = -N -Ttext 0
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -ffreestanding -fno-common -fno-stack-protector -fno-pie -no-pie -nostdlib -static -fno-builtin -nodefaultlibs -Wno-unused
cflags = -Wall -g -std=c11 -mtune=cortex-a72 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
endif
cc = ${toolchain}gcc

10
Ubiquitous/XiZi_AIoT/services/shell/letter-shell/shell.h
View File

@ -12,6 +12,8 @@
#ifndef __SHELL_H__
#define __SHELL_H__
#include <stdint.h>
#include "shell_cfg.h"
#define SHELL_VERSION "3.2.3" /**< 版本号 */
@ -125,10 +127,10 @@
* @param _func 被代理的函数
* @param ... 代理参数
*/
#define SHELL_AGENCY_FUNC(_func, ...) \
void SHELL_AGENCY_FUNC_NAME(_func)(int p1, int p2, int p3, int p4, int p5, int p6, int p7) \
{ \
_func(__VA_ARGS__); \
#define SHELL_AGENCY_FUNC(_func, ...) \
void SHELL_AGENCY_FUNC_NAME(_func)(intptr_t p1, intptr_t p2, intptr_t p3, intptr_t p4, intptr_t p5, intptr_t p6, intptr_t p7) \
{ \
_func(__VA_ARGS__); \
}
#if SHELL_USING_CMD_EXPORT == 1