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Merge branch 'prepare_for_master' of https://git.trustie.net/xuos/xiuos into develop

This commit is contained in:
Wang_Weigen 2022-11-01 17:10:33 +08:00
parent d2192a0cb1 8e5c61c487
commit 5d0c0f944e
136 changed files with 86099 additions and 467 deletions
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54
APP_Framework/Applications/app_test/Makefile
View File

@ -1,29 +1,37 @@
SRC_FILES := test_shell.c
ifeq ($(CONFIG_USER_TEST_ADC),y)
SRC_FILES += test_adc.c
endif
ifeq ($(CONFIG_USER_TEST_DAC),y)
SRC_FILES += test_dac.c
endif
ifeq ($(CONFIG_USER_TEST_SEMC),y)
SRC_FILES += test_extsram.c
endif
ifeq ($(CONFIG_USER_TEST_LCD),y)
SRC_FILES +=
endif
ifeq ($(CONFIG_ADD_XIZI_FETURES),y)
include $(KERNEL_ROOT)/compiler.mk
endif
include $(KERNEL_ROOT)/.config
ifeq ($(CONFIG_ADD_NUTTX_FETURES),y)
include $(APPDIR)/Make.defs
CSRCS += test_extsram.c test_lcd.c
ifeq ($(CONFIG_USER_TEST_SEMC),y)
CSRCS += test_extsram.c
endif
ifeq ($(CONFIG_USER_TEST_LCD),y)
CSRCS += test_lcd.c
endif
include $(APPDIR)/Application.mk
endif
ifeq ($(CONFIG_ADD_XIZI_FETURES),y)
SRC_FILES := test_shell.c
ifeq ($(CONFIG_USER_TEST_ADC),y)
SRC_FILES += test_adc.c
endif
ifeq ($(CONFIG_USER_TEST_DAC),y)
SRC_FILES += test_dac.c
endif
ifeq ($(CONFIG_USER_TEST_SEMC),y)
SRC_FILES += test_extsram.c
endif
ifeq ($(CONFIG_USER_TEST_LCD),y)
SRC_FILES +=
endif
include $(KERNEL_ROOT)/compiler.mk
endif

20
APP_Framework/Applications/app_test/test_lcd.c
View File

@ -22,17 +22,11 @@
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <transform.h>
#ifdef ADD_NUTTX_FETURES
#ifdef CONFIG_K210_LCD
#include "nuttx/arch.h"
#include "nuttx/lcd/lt768.h"
#include "nuttx/lcd/lt768_lib.h"
#include "nuttx/lcd/k210_lcd.h"
void LcdDemo(void)
{
int x1 = 50, y1 = 50, x2 = LCD_XSIZE_TFT - 50, y2 = LCD_YSIZE_TFT - 50;
@ -72,18 +66,6 @@ void LcdDemo(void)
}
#else
#include <sys/ioctl.h>
#include <sys/mman.h>
#include <unistd.h>
#include <stdlib.h>
#include <stdio.h>
#include <fcntl.h>
#include <errno.h>
#include <nuttx/video/fb.h>
#include <nuttx/video/rgbcolors.h>
/****************************************************************************
* Preprocessor Definitions
****************************************************************************/

8
APP_Framework/Framework/connection/wifi/Kconfig
View File

@ -8,6 +8,14 @@ if ADAPTER_HFA21_WIFI
source "$APP_DIR/Framework/connection/wifi/hfa21_wifi/Kconfig"
endif
config ADAPTER_ESP8285_WIFI
bool "Using wifi adapter device esp8285"
default n
if ADAPTER_ESP8285_WIFI
source "$APP_DIR/Framework/connection/wifi/esp8285_wifi/Kconfig"
endif
config ADAPTER_ESP07S_WIFI
bool "Using wifi adapter device esp07s"
default n

21
APP_Framework/Framework/connection/wifi/adapter_wifi.c
View File

@ -28,6 +28,10 @@ extern AdapterProductInfoType Hfa21WifiAttach(struct Adapter *adapter);
extern AdapterProductInfoType Esp07sWifiAttach(struct Adapter *adapter);
#endif
#ifdef ADAPTER_ESP8285_WIFI
extern AdapterProductInfoType Esp8285WifiAttach(struct Adapter *adapter);
#endif
static int AdapterWifiRegister(struct Adapter *adapter)
{
int ret = 0;
@ -91,11 +95,27 @@ int AdapterWifiInit(void)
adapter->info = product_info;
adapter->done = product_info->model_done;
#endif
#ifdef ADAPTER_ESP8285_WIFI
AdapterProductInfoType product_info = Esp8285WifiAttach(adapter);
if (!product_info) {
printf("AdapterWifiInit ESP8285 attach error\n");
PrivFree(adapter);
return -1;
}
adapter->product_info_flag = 1;
adapter->info = product_info;
adapter->done = product_info->model_done;
#endif
return ret;
}
/******************wifi TEST*********************/
int AdapterWifiTest(void)
{
@ -364,7 +384,6 @@ int AdapterWifiTestWithParam(int argc, char *argv[])
strcpy(apt_param->wifi_ssid, wifi_param[APT_WIFI_PARAM_SSID]);
strcpy(apt_param->wifi_pwd, wifi_param[APT_WIFI_PARAM_PWD]);
printf("2022-10-14 Mr. Wang commit Wifi\n");
printf("apt %p ssid %p %s\n", apt_param, apt_param->wifi_ssid);
CHECK_RET(AdapterDeviceOpen(adapter));

10
APP_Framework/Framework/connection/wifi/esp8285_wifi/Kconfig Normal file
View File

@ -0,0 +1,10 @@
config ADAPTER_WIFI_ESP8285
string "ESP8285 WIFI adapter name"
default "esp8285_wifi"
if ADD_NUTTX_FETURES
config ADAPTER_ESP8285_DRIVER
string "ESP8285 device uart driver path"
default "/dev/ttyS1"
endif

6
APP_Framework/Framework/connection/wifi/esp8285_wifi/Make.defs Normal file
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@ -0,0 +1,6 @@
############################################################################
# APP_Framework/Framework/connection/wifi/esp8285/Make.defs
############################################################################
ifneq ($(CONFIG_ADAPTER_ESP8285_WIFI),)
CONFIGURED_APPS += $(APPDIR)/../../../APP_Framework/Framework/connection/wifi/esp8285_wifi
endif

7
APP_Framework/Framework/connection/wifi/esp8285_wifi/Makefile Normal file
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@ -0,0 +1,7 @@
include $(KERNEL_ROOT)/.config
ifeq ($(CONFIG_ADD_NUTTX_FETURES),y)
include $(APPDIR)/Make.defs
CSRCS += esp8285_wifi.c
include $(APPDIR)/Application.mk
endif

589
APP_Framework/Framework/connection/wifi/esp8285_wifi/esp8285_wifi.c Normal file
View File

@ -0,0 +1,589 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file esp07_wifi.c
* @brief Implement the connection wifi adapter function, using ESP8285 device
* @version 1.1
* @author AIIT XUOS Lab
* @date 2022.04.08
*/
#include <adapter.h>
#include <at_agent.h>
#include "../adapter_wifi.h"
#include <stdlib.h>
#define LEN_PARA_BUF 128
static int Esp8285WifiSetDown(struct Adapter *adapter_at);
/**
* @description: check AT startup status
* @param at_agent - wifi device agent pointer
* @return success: EOK
*/
static int Esp8285WifiTestAtCmd(ATAgentType at_agent)
{
int ret = 0;
ret = AtCmdConfigAndCheck(at_agent, "ATE0\r\n", "OK"); ///< close echo function
if(ret < 0) {
printf("%s %d cmd[ATE0] config failed!\n",__func__,__LINE__);
ret = -1;
}
PrivTaskDelay(2000);
ret = AtCmdConfigAndCheck(at_agent, "AT\r\n", "OK");
if(ret < 0) {
printf("%s %d cmd[AT] config failed!\n",__func__,__LINE__);
ret = -1;
}
return ret;
}
static int Esp8285UartOpen(struct Adapter *adapter)
{
if (NULL == adapter) {
return -1;
}
/* Open device in read-write mode */
adapter->fd = PrivOpen(ADAPTER_ESP8285_DRIVER, O_RDWR);
if (adapter->fd < 0) {
printf("Esp8285WifiOpen get serial %s fd error\n", ADAPTER_ESP8285_DRIVER);
return -1;
}
/* set serial config, serial_baud_rate = 115200 */
struct SerialDataCfg cfg;
memset(&cfg, 0 ,sizeof(struct SerialDataCfg));
cfg.serial_baud_rate = BAUD_RATE_115200;
cfg.serial_data_bits = DATA_BITS_8;
cfg.serial_stop_bits = STOP_BITS_1;
cfg.serial_parity_mode = PARITY_NONE;
cfg.serial_bit_order = BIT_ORDER_LSB;
cfg.serial_invert_mode = NRZ_NORMAL;
cfg.serial_buffer_size = SERIAL_RB_BUFSZ;
cfg.is_ext_uart = 0;
#ifdef ADAPTER_ESP8285_DRIVER_EXT_PORT
cfg.is_ext_uart = 1;
cfg.ext_uart_no = ADAPTER_ESP8285_DRIVER_EXT_PORT;
cfg.port_configure = PORT_CFG_INIT;
#endif
struct PrivIoctlCfg ioctl_cfg;
ioctl_cfg.ioctl_driver_type = SERIAL_TYPE;
ioctl_cfg.args = &cfg;
PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg);
PrivTaskDelay(1000);
printf("esp8285 uart config ready\n");
return 0;
}
/**
* @description: Open wifi
* @param adapter - wifi device pointer
* @return success: EOK, failure: ENOMEMORY
*/
static int Esp8285WifiOpen(struct Adapter *adapter)
{
/*step1: open esp8285 serial port*/
Esp8285UartOpen(adapter);
/*step2: init AT agent*/
if (!adapter->agent) {
char *agent_name = "wifi_uart_client";
if (EOK != InitATAgent(agent_name, adapter->fd, 512)) {
printf("at agent init failed !\n");
return -1;
}
ATAgentType at_agent = GetATAgent(agent_name);
adapter->agent = at_agent;
}
AtSetReplyEndChar(adapter->agent,'O','K');
ADAPTER_DEBUG("Esp8285Wifi open done\n");
return 0;
}
/**
* @description: Close wifi
* @param adapter - wifi device pointer
* @return success: EOK
*/
static int Esp8285WifiClose(struct Adapter *adapter)
{
Esp8285WifiSetDown(adapter);
PrivClose(adapter->fd);
return 0;
}
/**
* @description: send data to adapter
* @param adapter - wifi device pointer
* @param data - data buffer
* @param data - data length
* @return success: EOK
*/
static int Esp8285WifiSend(struct Adapter *adapter, const void *data, size_t len)
{
x_err_t result = EOK;
if (adapter->agent) {
EntmSend(adapter->agent, (const char *)data, len);
}else {
printf("Esp8285WifiSend can not find agent!\n");
}
return result;
}
/**
* @description: receive data from adapter
* @param adapter - wifi device pointer
* @param data - data buffer
* @param data - data length
* @return success: EOK
*/
static int Esp8285WifiReceive(struct Adapter *adapter, void *rev_buffer, size_t buffer_len)
{
x_err_t result = EOK;
printf("esp8285 receive waiting ... \n");
if (adapter->agent) {
return EntmRecv(adapter->agent, (char *)rev_buffer, buffer_len, 40);
} else {
printf("Esp8285WifiReceive can not find agent!\n");
}
return result;
}
/**
* @description: connnect wifi to internet
* @param adapter - wifi device pointer
* @return success: EOK
*/
static int Esp8285WifiSetUp(struct Adapter *adapter)
{
char cmd[LEN_PARA_BUF];
int ret = 0;
char *result = NULL;
struct WifiParam *param = (struct WifiParam *)adapter->adapter_param;
struct ATAgent *agent = adapter->agent;
PrivTaskDelay(2000);
if(Esp8285WifiTestAtCmd(agent) < 0)
{
printf("wifi at cmd startup failed.\n");
return -1;
}
PrivTaskDelay(2000);
/* config as softAP+station mode */
ret = AtCmdConfigAndCheck(agent, "AT+CWMODE=3\r\n", "OK");
if(ret < 0) {
printf("%s %d cmd[AT+CWMODE=3] config failed!\n",__func__,__LINE__);
return -1;
}
PrivTaskDelay(2000);
/* connect the router */
memset(cmd,0,sizeof(cmd));
strncpy(cmd,"AT+CWJAP=",strlen("AT+CWJAP="));
strncat(cmd,"\"",1);
strncat(cmd,param->wifi_ssid,strlen(param->wifi_ssid));
strncat(cmd,"\"",1);
strncat(cmd,",",1);
strncat(cmd,"\"",1);
strncat(cmd,param->wifi_pwd,strlen(param->wifi_pwd));
strncat(cmd,"\"",1);
strcat(cmd,"\r\n");
ret = AtCmdConfigAndCheck(agent, cmd, "OK");
if(ret < 0) {
printf("%s %d cmd[%s] connect[%s] failed!\n",__func__,__LINE__,cmd,param->wifi_ssid);
return -1;
}
/* check the wifi ip address */
ATReplyType reply = CreateATReply(256);
if (NULL == reply) {
printf("%s %d at_create_resp failed!\n",__func__,__LINE__);
return -1;
}
ret = ATOrderSend(agent, REPLY_TIME_OUT, reply, "AT+CIFSR\r\n");
if(ret < 0){
printf("%s %d ATOrderSend AT+CIFSR failed.\n",__func__,__LINE__);
ret = -1;
goto __exit;
}
result = GetReplyText(reply);
if (!result) {
printf("%s %d get reply failed.\n",__func__,__LINE__);
ret = -1;
goto __exit;
}
printf("[%s]\n", result);
__exit:
DeleteATReply(reply);
return ret;
}
/**
* @description: disconnnect wifi from internet
* @param adapter - wifi device pointer
* @return success: EOK
*/
static int Esp8285WifiSetDown(struct Adapter *adapter)
{
ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+RESTORE\r\n");
PrivTaskDelay(2000);
return 0;
}
/**
* @description: set wifi ip/gateway/netmask address(in sta mode)
* @param adapter - wifi device pointer
* @param ip - ip address
* @param gateway - gateway address
* @param netmask - netmask address
* @return success: EOK, failure: ENOMEMORY
*/
static int Esp8285WifiSetAddr(struct Adapter *adapter, const char *ip, const char *gateway, const char *netmask)
{
int ret = 0;
char cmd[LEN_PARA_BUF];
/* e.g. AT+CIPSTA_DEF="192.168.6.100","192.168.6.1","255.255.255.0" */
memset(cmd,0,sizeof(cmd));
strncpy(cmd,"AT+CIPAP_DEF=",strlen(" AT+CIPAP_DEF="));
strncat(cmd,"\"",1);
strncat(cmd,ip,strlen(ip));
strncat(cmd,"\"",1);
strncat(cmd,",",1);
strncat(cmd,"\"",1);
strncat(cmd,gateway,strlen(gateway));
strncat(cmd,"\"",1);
strncat(cmd,",",1);
strncat(cmd,"\"",1);
strncat(cmd,netmask,strlen(netmask));
strncat(cmd,"\"",1);
strcat(cmd,"\r\n");
ret = AtCmdConfigAndCheck(adapter->agent, cmd, "OK");
if(ret < 0) {
printf("%s %d cmd[%s] config ip failed!\n",__func__,__LINE__,cmd);
return -1;
}
return 0;
}
/**
* @description: wifi ping function
* @param adapter - wifi device pointer
* @param destination - domain name or ip address
* @return success: EOK, failure: ENOMEMORY
*/
static int Esp8285WifiPing(struct Adapter *adapter, const char *destination)
{
char cmd[LEN_PARA_BUF];
int ret = 0;
memset(cmd,0,sizeof(cmd));
strncpy(cmd,"AT+PING=",strlen("AT+PING="));
strncat(cmd,"\"",1);
strncat(cmd,destination,strlen(destination));
strncat(cmd,"\"",1);
strcat(cmd,"\r\n");
ret = AtCmdConfigAndCheck(adapter->agent, cmd, "OK"); ///< config as softAP+station mode
if(ret < 0) {
printf("%s %d ping [%s] failed!\n",__func__,__LINE__,destination);
return -1;
}
printf("ping [%s] ok\n", destination);
return 0;
}
/**
* @description: display wifi network configuration
* @param adapter - wifi device pointer
* @return success: EOK, failure: ENOMEMORY
*/
static int Esp8285WifiNetstat(struct Adapter *adapter)
{
int ret = 0;
char *result = NULL;
/* check the wifi ip address */
ATReplyType reply = CreateATReply(256);
if (NULL == reply) {
printf("%s %d at_create_resp failed!\n",__func__,__LINE__);
return -1;
}
ret = ATOrderSend(adapter->agent, REPLY_TIME_OUT, reply, "AT+CIFSR\r\n");
if(ret < 0){
printf("%s %d ATOrderSend AT+CIFSR failed.\n",__func__,__LINE__);
ret = -1;
goto __exit;
}
result = GetReplyText(reply);
if (!result) {
printf("%s %d get reply failed.\n",__func__,__LINE__);
ret = -1;
goto __exit;
}
printf("[%s]\n", result);
__exit:
DeleteATReply(reply);
return ret;
}
/**
* @description: wifi connect function
* @param adapter - wifi device pointer
* @param net_role - net role, CLIENT or SERVER
* @param ip - ip address
* @param port - port num
* @param ip_type - ip type, IPV4 or IPV6
* @return success: 0, failure: -1
*/
static int Esp8285WifiConnect(struct Adapter *adapter, enum NetRoleType net_role, const char *ip, const char *port, enum IpType ip_type)
{
int ret = EOK;
char cmd[LEN_PARA_BUF];
struct ATAgent *agent = adapter->agent;
memset(cmd,0,sizeof(cmd));
if(adapter->socket.protocal == SOCKET_PROTOCOL_TCP && net_role == CLIENT) //esp8285 as tcp client to connect server
{
//e.g. AT+CIPSTART="TCP","192.168.3.116",8080 protocol, server IP and port
strncpy(cmd,"AT+CIPSTART=",strlen("AT+CIPSTART="));
strncat(cmd,"\"",1);
strncat(cmd,"TCP",strlen("TCP"));
strncat(cmd,"\"",1);
strncat(cmd, ",", 1);
strncat(cmd,"\"",1);
strncat(cmd, ip, strlen(ip));
strncat(cmd, "\"", 1);
strncat(cmd, ",", 1);
strncat(cmd, port, strlen(port));
strcat(cmd,"\r\n");
ret = AtCmdConfigAndCheck(agent, cmd, "OK");
if(ret < 0) {
printf("%s %d tcp connect [%s] failed!\n",__func__,__LINE__,ip);
return -1;
}
}
else if(adapter->socket.protocal == SOCKET_PROTOCOL_UDP)
{
//e.g. AT+CIPSTART="UDP","192.168.3.116",8080,2233,0 UDP protocol, server IP, port,local port,udp mode
strncpy(cmd,"AT+CIPSTART=",strlen("AT+CIPSTART="));
strncat(cmd,"\"",1);
strncat(cmd,"UDP",strlen("UDP"));
strncat(cmd,"\"",1);
strncat(cmd, ",", 1);
strncat(cmd,"\"",1);
strncat(cmd, ip, strlen(ip));
strncat(cmd, "\"", 1);
strncat(cmd, ",", 1);
strncat(cmd, port, strlen(port));
strncat(cmd, ",", 1);
strncat(cmd, "2233", strlen("2233")); ///< local port
strncat(cmd, ",", 1);
strncat(cmd, "0", 1); ///< udp transparent transmission mode must be 0
strcat(cmd,"\r\n");
ret = AtCmdConfigAndCheck(agent, cmd, "OK");
if(ret < 0) {
printf("%s %d udp connect [%s] failed!\n",__func__,__LINE__,ip);
return -1;
}
}
ret = AtCmdConfigAndCheck(agent, "AT+CIPMODE=1\r\n", "OK"); ///< config as transparent transmission
if(ret < 0) {
printf("%s %d cmd[%s] config as transparent transmission failed!\n",__func__,__LINE__,cmd);
return -1;
}
ATOrderSend(agent, REPLY_TIME_OUT, NULL, "AT+CIPSEND\r\n");
printf("[%s] connection config as transparent transmission\n",adapter->socket.protocal == SOCKET_PROTOCOL_UDP ? "udp" : "tcp");
adapter->net_role = net_role;
return 0;
}
/**
* @description: wifi disconnect function
* @param adapter - wifi device pointer
* @return success: 0, failure: -1
*/
static int Esp8285WifiDisconnect(struct Adapter *adapter)
{
int ret = EOK;
char cmd[LEN_PARA_BUF];
struct ATAgent *agent = adapter->agent;
memset(cmd,0,sizeof(cmd));
/* step1: stop transparent transmission mode */
ATOrderSend(agent, REPLY_TIME_OUT, NULL, "+++\r\n");
/* step2: exit transparent transmission mode */
ret = AtCmdConfigAndCheck(agent, "AT+CIPMODE=0\r\n", "OK");
if(ret < 0) {
printf("%s %d cmd[AT+CIPMODE=0] exit failed!\n",__func__,__LINE__);
return -1;
}
/* step3: disconnect */
ret = AtCmdConfigAndCheck(agent, "AT+CIPCLOSE\r\n", "OK");
if(ret < 0) {
printf("%s %d cmd [AT+CIPCLOSE] disconnect failed!\n",__func__,__LINE__);
return -1;
}
return 0;
}
static int Esp8285WifiIoctl(struct Adapter *adapter, int cmd, void *args)
{
int32_t ret = 0;
char baud_str[LEN_PARA_BUF];
struct SerialDataCfg cfg;
char at_cmd[LEN_PARA_BUF];
uint32_t baud_rate = 0 ;
switch (cmd)
{
case CONFIG_WIFI_RESET: /* reset wifi */
ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+RST\r\n");
break;
case CONFIG_WIFI_RESTORE: /* resore wifi */
ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+RESTORE\r\n");
break;
case CONFIG_WIFI_BAUDRATE:
/* step1: config mcu uart*/
baud_rate = *((uint32_t *)args);
memset(at_cmd, 0, sizeof(at_cmd));
memset(baud_str, 0, sizeof(baud_str));
memset(&cfg, 0 ,sizeof(struct SerialDataCfg));
cfg.serial_baud_rate = baud_rate;
cfg.serial_data_bits = DATA_BITS_8;
cfg.serial_stop_bits = STOP_BITS_1;
cfg.serial_parity_mode = PARITY_NONE;
cfg.serial_bit_order = BIT_ORDER_LSB;
cfg.serial_invert_mode = NRZ_NORMAL;
cfg.serial_buffer_size = SERIAL_RB_BUFSZ;
cfg.is_ext_uart = 0;
#ifdef ADAPTER_ESP8285_DRIVER_EXT_PORT
cfg.is_ext_uart = 1;
cfg.ext_uart_no = ADAPTER_ESP8285_DRIVER_EXT_PORT;
cfg.port_configure = PORT_CFG_INIT;
#endif
struct PrivIoctlCfg ioctl_cfg;
ioctl_cfg.ioctl_driver_type = SERIAL_TYPE;
ioctl_cfg.args = &cfg;
PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg);
/* step2: config wifi uart*/
itoa(baud_rate, baud_str, 10);
strncpy(at_cmd, "AT+UART_DEF=", strlen("AT+UART_DEF="));
strncat(at_cmd, baud_str, strlen(baud_str));
strncat(at_cmd, ",", 1);
strncat(at_cmd, "8", 1);
strncat(at_cmd, ",", 1);
strncat(at_cmd, "1", 1);
strncat(at_cmd, ",", 1);
strncat(at_cmd, "0", 1);
strncat(at_cmd, ",", 1);
strncat(at_cmd, "3", 1);
strcat(at_cmd,"\r\n");
ret = AtCmdConfigAndCheck(adapter->agent, at_cmd, "OK");
if(ret < 0) {
printf("%s %d cmd [%s] config uart failed!\n",__func__,__LINE__,at_cmd);
ret = -1;
}
break;
default:
ret = -1;
break;
}
return ret;
}
static const struct IpProtocolDone esp8285_wifi_done =
{
.open = Esp8285WifiOpen,
.close = Esp8285WifiClose,
.ioctl = Esp8285WifiIoctl,
.setup = Esp8285WifiSetUp,
.setdown = Esp8285WifiSetDown,
.setaddr = Esp8285WifiSetAddr,
.setdns = NULL,
.setdhcp = NULL,
.ping = Esp8285WifiPing,
.netstat = Esp8285WifiNetstat,
.connect = Esp8285WifiConnect,
.send = Esp8285WifiSend,
.recv = Esp8285WifiReceive,
.disconnect = Esp8285WifiDisconnect,
};
/**
* @description: Register wifi device esp8285
* @return success: EOK, failure: ERROR
*/
AdapterProductInfoType Esp8285WifiAttach(struct Adapter *adapter)
{
struct AdapterProductInfo *product_info = PrivMalloc(sizeof(struct AdapterProductInfo));
if (!product_info)
{
printf("Esp8285WifiAttach Attach malloc product_info error\n");
PrivFree(product_info);
return NULL;
}
strncpy(product_info->model_name, ADAPTER_WIFI_ESP8285, strlen(ADAPTER_WIFI_ESP8285));
product_info->model_done = (void *)&esp8285_wifi_done;
return product_info;
}

20
APP_Framework/Framework/transform_layer/nuttx/transform.c
View File

@ -139,10 +139,30 @@ static int PrivSerialIoctl(int fd, int cmd, void *args)
{
struct SerialDataCfg *serial_cfg = (struct SerialDataCfg *)args;
unsigned long serial_baud_rate = (unsigned long)serial_cfg->serial_baud_rate;
struct termios term;
/* Extended serial port */
if(serial_cfg->is_ext_uart == 1)
{
return ioctl(fd, OPE_INT, serial_baud_rate);
}
/* Standard serial port,only the baud rate is set */
else if(serial_cfg->is_ext_uart == 0)
{
if(ioctl(fd, TCGETS, (unsigned long)&term) < 0)
{
return -1;
}
if ((cfsetispeed(&term, serial_baud_rate) < 0) ||(cfsetospeed(&term, serial_baud_rate) < 0))
{
return -1;
}
if(ioctl(fd, TCSETS, (unsigned long)&term) < 0)
{
return -1;
}
}
return 0;
}

24
APP_Framework/Framework/transform_layer/nuttx/transform.h
View File

@ -25,11 +25,33 @@
#include <nuttx/pthread.h>
#include <nuttx/semaphore.h>
#include <nuttx/time.h>
#include <sys/ioctl.h>
#include <stddef.h>
#include <stdint.h>
#include <nuttx/wireless/lpwan/sx127x.h>
#include <unistd.h>
#include <stdlib.h>
#include <stdio.h>
#include <fcntl.h>
#include <errno.h>
#include <nuttx/ioexpander/gpio.h>
#include <termios.h>
#include <nuttx/arch.h>
#ifdef CONFIG_ADAPTER_SX1278
#include <nuttx/wireless/lpwan/sx127x.h>
#endif
#ifdef CONFIG_USER_TEST_LCD
#ifdef CONFIG_K210_LCD
# include "nuttx/lcd/lt768.h"
# include "nuttx/lcd/lt768_lib.h"
# include "nuttx/lcd/if_port.h"
#else
# include <sys/mman.h>
# include <nuttx/video/fb.h>
# include <nuttx/video/rgbcolors.h>
#endif
#endif
typedef uint8_t uint8;
typedef uint16_t uint16;

14
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/Kconfig Executable file
View File

@ -0,0 +1,14 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_BOARD_HC32F4A0
config HC32F4A0_BOARD
bool "HDSC HC32F4A0 base board"
default n
---help---
Select if you are using the HC32F4A0 base board with the HC32F4A0.
endif

28
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/README.txt Executable file
View File

@ -0,0 +1,28 @@
README
======
This README discusses issues unique to NuttX configurations for the
HC32F4A0 development board featuring the HC32F4A0 MCU.
The board features:
NOTE: This port was developed on the original board
ways:
Contents
========
- UARTs
- HC32F4A0-specific Configuration Options
- BASIC
- Testing LLVM LIBC++ with NuttX
- Configurations
UARTs
=====
UART/USART PINS
---------------
Default USART/UART Configuration
--------------------------------

54
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/configs/nsh/defconfig Executable file
View File

@ -0,0 +1,54 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_ARCH_FPU is not set
# CONFIG_NSH_ARGCAT is not set
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
# CONFIG_NSH_CMDPARMS is not set
CONFIG_ADD_NUTTX_FETURES=y
CONFIG_ARCH="arm"
CONFIG_ARCH_ARMV7M=y
CONFIG_ARCH_CORTEXM4=y
CONFIG_ARCH_FAMILY="armv7-m"
CONFIG_ARM_THUMB=y
CONFIG_ARCH_BOARD="hc32f4a0"
CONFIG_ARCH_BOARD_HC32F4A0=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP="hc32"
CONFIG_ARCH_CHIP_HC32=y
CONFIG_ARCH_CHIP_HC32F4A0=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH_TOOLCHAIN_GNU=y
CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
CONFIG_HC32F4A0_BOARD=y
CONFIG_BOARD_LATE_INITIALIZE=y
CONFIG_BUILTIN=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_FS_PROCFS=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_INTELHEX_BINARY=y
CONFIG_MM_REGIONS=1
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_START_DAY=6
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2011
CONFIG_SYSTEM_NSH=y
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_USART6_SERIAL_CONSOLE=y
CONFIG_HC32_UART6=y
CONFIG_HC32_UART6_SERIALDRIVER=y
CONFIG_UART6_SERIAL_CONSOLE=y

94
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/include/board.h Executable file
View File

@ -0,0 +1,94 @@
/****************************************************************************
* boards/arm/hc32/hc32f4a0/include/board.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file board.h
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-10-10
*/
#ifndef __BOARDS_ARM_HC32_HC32F4A0_INCLUDE_BOARD_H
#define __BOARDS_ARM_HC32_HC32F4A0_INCLUDE_BOARD_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
# include <stdbool.h>
#endif
/* Do not include HC32-specific header files here */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define LED_GREEN_PORT (GPIO_PORT_I)
#define LED_GREEN_PIN (GPIO_PIN_03)
/* Key port&pin definition */
#define KEY_PORT (GPIO_PORT_I)
#define KEY_PIN (GPIO_PIN_07)
/* for lowputc device output */
/* UART RX/TX Port/Pin definition */
#define LP_RX_PORT (GPIO_PORT_H) /* PH6: USART6_RX */
#define LP_RX_PIN (GPIO_PIN_06)
#define LP_RX_GPIO_FUNC (GPIO_FUNC_37_USART6_RX)
#define LP_TX_PORT (GPIO_PORT_E) /* PE6: USART6_TX */
#define LP_TX_PIN (GPIO_PIN_06)
#define LP_TX_GPIO_FUNC (GPIO_FUNC_36_USART6_TX)
/* UART unit definition */
#define LP_UNIT (M4_USART6)
#define LP_FUNCTION_CLK_GATE (PWC_FCG3_USART6)
/* UART unit interrupt definition */
#define LP_UNIT_ERR_INT_SRC (INT_USART6_EI)
#define LP_UNIT_ERR_INT_IRQn (Int015_IRQn + HC32_IRQ_FIRST)
#define LP_UNIT_RX_INT_SRC (INT_USART6_RI)
#define LP_UNIT_RX_INT_IRQn (Int103_IRQn + HC32_IRQ_FIRST)
#define LP_UNIT_TX_INT_SRC (INT_USART6_TI)
#define LP_UNIT_TX_INT_IRQn (Int102_IRQn + HC32_IRQ_FIRST)
#define LP_UNIT_TCI_INT_SRC (INT_USART6_TCI)
#define LP_UNIT_TCI_INT_IRQn (Int099_IRQn + HC32_IRQ_FIRST)
/* printf device s*/
#define BSP_PRINTF_DEVICE LP_UNIT
#define BSP_PRINTF_BAUDRATE (115200)
#define BSP_PRINTF_PORT LP_TX_PORT
#define BSP_PRINTF_PIN LP_TX_PIN
#define BSP_PRINTF_PORT_FUNC LP_TX_GPIO_FUNC
#endif /* __BOARDS_ARM_HC32_HC32F4A0_INCLUDE_BOARD_H */

92
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/kernel/Makefile Executable file
View File

@ -0,0 +1,92 @@
############################################################################
# boards/arm/hc32/hc32f4a0/kernel/Makefile
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/Make.defs
# The entry point name (if none is provided in the .config file)
CONFIG_INIT_ENTRYPOINT ?= user_start
ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT))
# Get the paths to the libraries and the links script path in format that
# is appropriate for the host OS
USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS)))))
USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld)
USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld)
USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex)
USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec)
USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin)
USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT)
USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS))))
USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}"
# Source files
CSRCS = stm32_userspace.c
COBJS = $(CSRCS:.c=$(OBJEXT))
OBJS = $(COBJS)
# Targets:
all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map
.PHONY: nuttx_user.elf depend clean distclean
$(COBJS): %$(OBJEXT): %.c
$(call COMPILE, $<, $@)
# Create the nuttx_user.elf file containing all of the user-mode code
nuttx_user.elf: $(OBJS)
$(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) $(USER_LIBGCC) --end-group
$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf
@echo "LD: nuttx_user.elf"
$(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf
ifeq ($(CONFIG_INTELHEX_BINARY),y)
@echo "CP: nuttx_user.hex"
$(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE)
endif
ifeq ($(CONFIG_MOTOROLA_SREC),y)
@echo "CP: nuttx_user.srec"
$(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE)
endif
ifeq ($(CONFIG_RAW_BINARY),y)
@echo "CP: nuttx_user.bin"
$(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE)
endif
$(TOPDIR)$(DELIM)User.map: nuttx_user.elf
@echo "MK: User.map"
$(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map
$(Q) $(CROSSDEV)size nuttx_user.elf
.depend:
depend: .depend
clean:
$(call DELFILE, nuttx_user.elf)
$(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*")
$(call DELFILE, "$(TOPDIR)$(DELIM)User.map")
$(call CLEAN)
distclean: clean

123
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/kernel/hc32_userspace.c Executable file
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@ -0,0 +1,123 @@
/****************************************************************************
* boards/arm/hc32/hc32f4a0/kernel/hc32_userspace.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file hc32_userspace.c
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-17
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdlib.h>
#include <nuttx/arch.h>
#include <nuttx/mm/mm.h>
#include <nuttx/wqueue.h>
#include <nuttx/userspace.h>
#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#ifndef CONFIG_NUTTX_USERSPACE
# error "CONFIG_NUTTX_USERSPACE not defined"
#endif
#if CONFIG_NUTTX_USERSPACE != 0x20060000
# error "CONFIG_NUTTX_USERSPACE must be 0x20060000 to match memory.ld"
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* These 'addresses' of these values are setup by the linker script. They are
* not actual uint32_t storage locations! They are only used meaningfully in
* the following way:
*
* - The linker script defines, for example, the symbol_sdata.
* - The declaration extern uint32_t _sdata; makes C happy. C will believe
* that the value _sdata is the address of a uint32_t variable _data (it
* is not!).
* - We can recover the linker value then by simply taking the address of
* of _data. like: uint32_t *pdata = &_sdata;
*/
extern uint32_t _stext; /* Start of .text */
extern uint32_t _etext; /* End_1 of .text + .rodata */
extern const uint32_t _eronly; /* End+1 of read only section (.text + .rodata) */
extern uint32_t _sdata; /* Start of .data */
extern uint32_t _edata; /* End+1 of .data */
extern uint32_t _sbss; /* Start of .bss */
extern uint32_t _ebss; /* End+1 of .bss */
/* This is the user space entry point */
int CONFIG_INIT_ENTRYPOINT(int argc, char *argv[]);
const struct userspace_s userspace locate_data(".userspace") =
{
/* General memory map */
.us_entrypoint = (main_t)CONFIG_INIT_ENTRYPOINT,
.us_textstart = (uintptr_t)&_stext,
.us_textend = (uintptr_t)&_etext,
.us_datasource = (uintptr_t)&_eronly,
.us_datastart = (uintptr_t)&_sdata,
.us_dataend = (uintptr_t)&_edata,
.us_bssstart = (uintptr_t)&_sbss,
.us_bssend = (uintptr_t)&_ebss,
/* Memory manager heap structure */
.us_heap = &g_mmheap,
/* Task/thread startup routines */
.task_startup = nxtask_startup,
/* Signal handler trampoline */
.signal_handler = up_signal_handler,
/* User-space work queue support (declared in include/nuttx/wqueue.h) */
#ifdef CONFIG_LIBC_USRWORK
.work_usrstart = work_usrstart,
#endif
};
/****************************************************************************
* Public Functions
****************************************************************************/
#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */

86
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/Make.defs Executable file
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@ -0,0 +1,86 @@
############################################################################
# boards/arm/hc32/hc32f4a0/scripts/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/.config
include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
LDSCRIPT = ld.script
ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
ARCHOPTIMIZATION = -g
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing
endif
ARCHCFLAGS = -fno-common -ffunction-sections -fdata-sections
ARCHCXXFLAGS = -fno-common -ffunction-sections -fdata-sections
ifneq ($(CONFIG_CXX_EXCEPTION),y)
ARCHCXXFLAGS = -fno-exceptions -fcheck-new
endif
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
ifeq ($(CONFIG_ARMV7M_TOOLCHAIN_CLANGL),y)
ARCHCFLAGS += -nostdlib -ffreestanding
ARCHCXXFLAGS += -nostdlib -ffreestanding
else
ARCHCFLAGS += -funwind-tables
ARCHCXXFLAGS += -fno-rtti -funwind-tables
endif
CFLAGS := $(APPPATHS) $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
NXFLATLDFLAGS1 = -r -d -warn-common
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
LDNXFLATFLAGS = -e main -s 2048
LDFLAGS += --gc-sections
# Loadable module definitions
CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs
LDMODULEFLAGS = -r -e module_initialize
LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld)
# ELF module definitions
CELFFLAGS = $(CFLAGS) -mlong-calls # --target1-abs
CXXELFFLAGS = $(CXXFLAGS) -mlong-calls # --target1-abs
LDELFFLAGS = -r -e main
LDELFFLAGS += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)gnu-elf.ld)
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
LDFLAGS += -g
endif

126
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/gnu-elf.ld Executable file
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@ -0,0 +1,126 @@
/****************************************************************************
* boards/arm/stm32/aiit-arm32-board/scripts/gnu-elf.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
SECTIONS
{
.text 0x00000000 :
{
_stext = . ;
*(.text)
*(.text.*)
*(.gnu.warning)
*(.stub)
*(.glue_7)
*(.glue_7t)
*(.jcr)
/* C++ support: The .init and .fini sections contain specific logic
* to manage static constructors and destructors.
*/
*(.gnu.linkonce.t.*)
*(.init) /* Old ABI */
*(.fini) /* Old ABI */
_etext = . ;
}
.ARM.extab :
{
*(.ARM.extab*)
}
.ARM.exidx :
{
*(.ARM.exidx*)
}
.rodata :
{
_srodata = . ;
*(.rodata)
*(.rodata1)
*(.rodata.*)
*(.gnu.linkonce.r*)
_erodata = . ;
}
.data :
{
_sdata = . ;
*(.data)
*(.data1)
*(.data.*)
*(.gnu.linkonce.d*)
. = ALIGN(4);
_edata = . ;
}
/* C++ support. For each global and static local C++ object,
* GCC creates a small subroutine to construct the object. Pointers
* to these routines (not the routines themselves) are stored as
* simple, linear arrays in the .ctors section of the object file.
* Similarly, pointers to global/static destructor routines are
* stored in .dtors.
*/
.ctors :
{
_sctors = . ;
*(.ctors) /* Old ABI: Unallocated */
*(.init_array) /* New ABI: Allocated */
_edtors = . ;
}
.dtors :
{
_sdtors = . ;
*(.dtors) /* Old ABI: Unallocated */
*(.fini_array) /* New ABI: Allocated */
_edtors = . ;
}
.bss :
{
_sbss = . ;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.b*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
}
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

96
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/kernel-space.ld Executable file
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@ -0,0 +1,96 @@
/****************************************************************************
* boards/arm/stm32/aiit-arm32-board/scripts/kernel-space.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* NOTE: This depends on the memory.ld script having been included prior to
* this script.
*/
OUTPUT_ARCH(arm)
ENTRY(_stext)
SECTIONS
{
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > kflash
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > kflash
.ARM.extab : {
*(.ARM.extab*)
} > kflash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > kflash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
. = ALIGN(4);
_edata = ABSOLUTE(.);
} > ksram AT > kflash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > ksram
/* Stabs debugging sections */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

123
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/ld.script Executable file
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@ -0,0 +1,123 @@
/****************************************************************************
* boards/arm/hc32/hc32f4a0/scripts/ld.script
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and
* 192Kb of SRAM. SRAM is split up into three blocks:
*
* 1) 112Kb of SRAM beginning at address 0x2000:0000
* 2) 16Kb of SRAM beginning at address 0x2001:c000
* 3) 64Kb of CCM SRAM beginning at address 0x1000:0000
*
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
* where the code expects to begin execution by jumping to the entry point in
* the 0x0800:0000 address
* range.
*/
MEMORY
{
flash (rx) : ORIGIN = 0x00000000, LENGTH = 2M
sram (rwx) : ORIGIN = 0x1FFE0000, LENGTH = 512K
}
OUTPUT_ARCH(arm)
ENTRY(_stext)
EXTERN(_vectors)
SECTIONS
{
.text : {
_stext = ABSOLUTE(.);
*(.vectors)
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
.init_section : ALIGN(4) {
_sinit = ABSOLUTE(.);
KEEP(*(.init_array .init_array.*))
_einit = ABSOLUTE(.);
} > flash
.ARM.extab : ALIGN(4) {
*(.ARM.extab*)
} > flash
.ARM.exidx : ALIGN(4) {
__exidx_start = ABSOLUTE(.);
*(.ARM.exidx*)
__exidx_end = ABSOLUTE(.);
} > flash
.tdata : {
_stdata = ABSOLUTE(.);
*(.tdata .tdata.* .gnu.linkonce.td.*);
_etdata = ABSOLUTE(.);
} > flash
.tbss : {
_stbss = ABSOLUTE(.);
*(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon);
_etbss = ABSOLUTE(.);
} > flash
_eronly = ABSOLUTE(.);
.data : ALIGN(4) {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
. = ALIGN(4);
_edata = ABSOLUTE(.);
} > sram AT > flash
.bss : ALIGN(4) {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > sram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

85
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/memory.ld Executable file
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@ -0,0 +1,85 @@
/****************************************************************************
* boards/arm/hc32/hc32f4a0/scripts/memory.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and
* 192Kb of SRAM. SRAM is split up into three blocks:
*
* 1) 112KB of SRAM beginning at address 0x2000:0000
* 2) 16KB of SRAM beginning at address 0x2001:c000
* 3) 64KB of CCM SRAM beginning at address 0x1000:0000
*
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
* where the code expects to begin execution by jumping to the entry point in
* the 0x0800:0000 address range.
*
* For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of
* FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which
* should fit into 64KB and, of course, can be optimized as needed (See
* also boards/arm/stm32/aiit-arm32-board/scripts/kernel-space.ld). Allowing the
* additional does permit addition debug instrumentation to be added to the
* kernel space without overflowing the partition.
*
* Alignment of the user space FLASH partition is also a critical factor:
* The user space FLASH partition will be spanned with a single region of
* size 2**n bytes. The alignment of the user-space region must be the same.
* As a consequence, as the user-space increases in size, the alignment
* requirement also increases.
*
* This alignment requirement means that the largest user space FLASH region
* you can have will be 512KB at it would have to be positioned at
* 0x08800000. If you change this address, don't forget to change the
* CONFIG_NUTTX_USERSPACE configuration setting to match and to modify
* the check in kernel/userspace.c.
*
* For the same reasons, the maximum size of the SRAM mapping is limited to
* 4KB. Both of these alignment limitations could be reduced by using
* multiple regions to map the FLASH/SDRAM range or perhaps with some
* clever use of subregions.
*
* A detailed memory map for the 112KB SRAM region is as follows:
*
* 0x20000 0000: Kernel .data region. Typical size: 0.1KB
* ------- ---- Kernel .bss region. Typical size: 1.8KB
* 0x20000 0800: Kernel IDLE thread stack (approximate). Size is
* determined by CONFIG_IDLETHREAD_STACKSIZE and
* adjustments for alignment. Typical is 1KB.
* ------- ---- Padded to 4KB
* 0x20000 1000: User .data region. Size is variable.
* ------- ---- User .bss region Size is variable.
* 0x20000 2000: Beginning of kernel heap. Size determined by
* CONFIG_MM_KERNEL_HEAPSIZE.
* ------- ---- Beginning of user heap. Can vary with other settings.
* 0x20001 c000: End+1 of CPU RAM
*/
MEMORY
{
/* 2Mb FLASH */
kflash (rx) : ORIGIN = 0x00000000, LENGTH = 2M
uflash (rx) : ORIGIN = 0x00200000, LENGTH = 128K
xflash (rx) : ORIGIN = 0x00220000, LENGTH = 768K
/* 512Kb of contiguous SRAM */
ksram (rwx) : ORIGIN = 0x1FFE0000, LENGTH = 512K
usram (rwx) : ORIGIN = 0x20060000, LENGTH = 4K
xsram (rwx) : ORIGIN = 0x20062000, LENGTH = 4K
}

98
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/scripts/user-space.ld Executable file
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@ -0,0 +1,98 @@
/****************************************************************************
* boards/arm/hc32/hc32f4a0/scripts/user-space.ld
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* NOTE: This depends on the memory.ld script having been included prior to
* this script.
*/
OUTPUT_ARCH(arm)
SECTIONS
{
.userspace : {
*(.userspace)
} > uflash
.text : {
_stext = ABSOLUTE(.);
*(.text .text.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > uflash
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > kflash
.ARM.extab : {
*(.ARM.extab*)
} > kflash
__exidx_start = ABSOLUTE(.);
.ARM.exidx : {
*(.ARM.exidx*)
} > kflash
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
.data : {
_sdata = ABSOLUTE(.);
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
. = ALIGN(4);
_edata = ABSOLUTE(.);
} > ksram AT > kflash
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > ksram
/* Stabs debugging sections */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

0
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/.depend Executable file
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32
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/Make.defs Executable file
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@ -0,0 +1,32 @@
############################################################################
# boards/arm/hc32/hc32f4a0/src/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/Make.defs
CSRCS = hc32_bringup.c hc32_appinit.c hc32_boot.c
ifeq ($(CONFIG_ARCH_LEDS),y)
CSRCS +=
endif
DEPPATH += --dep-path board
VPATH += :board
CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board)

115
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/Make.dep Executable file
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@ -0,0 +1,115 @@
hc32_boot.o: hc32_boot.c \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/config.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/debug.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/compiler.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/syslog.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stdint.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/types.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/inttypes.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/limits.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/limits.h \
/usr/local/arm/gcc-arm-none-eabi-6-2017-q1-update/lib/gcc/arm-none-eabi/6.3.1/include/stdarg.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stdbool.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/sys/uio.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/sys/types.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/board.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/board/board.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/common/arm_internal.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/arch.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/arch.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/pgalloc.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/addrenv.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/cache.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/sched.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/queue.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/sched.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/strings.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/string.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stddef.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/time.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/queue.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/signal.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/semaphore.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/clock.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/irq.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/irq.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/chip/irq.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/armv7-m/irq.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/armv7-m/nvicpri.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/chip/chip.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/armv7-m/irq_cmnvector.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/tls.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/pthread.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/unistd.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/wdog.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/mm/shm.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/mm/gran.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/fs/fs.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/semaphore.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/errno.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/net/net.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/armv7-m/nvic.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/armv7-m/itm.h
hc32_appinit.o: hc32_appinit.c \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/config.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/board.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stdint.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/compiler.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/types.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/inttypes.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/limits.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/limits.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stdbool.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/chip/hc32f4a0.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/chip/core_cm4.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/armv7-m/itm.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/chip/cmsis_version.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/chip/cmsis_compiler.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/chip/cmsis_gcc.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/arch/arm/src/chip/mpu_armv7.h
hc32_bringup.o: hc32_bringup.c \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/config.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stdbool.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/compiler.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stdint.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/types.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/inttypes.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/limits.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/limits.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stdio.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/sys/types.h \
/usr/local/arm/gcc-arm-none-eabi-6-2017-q1-update/lib/gcc/arm-none-eabi/6.3.1/include/stdarg.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/time.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/fs/fs.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/semaphore.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/errno.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/semaphore.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/clock.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/sched.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/queue.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/sched.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/strings.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/string.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/stddef.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/queue.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/signal.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/irq.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/irq.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/chip/irq.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/armv7-m/irq.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/armv7-m/nvicpri.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/chip/chip.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/armv7-m/irq_cmnvector.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/tls.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/pthread.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/unistd.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/wdog.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/mm/shm.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/mm/gran.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/net/net.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/arch/arch.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/pgalloc.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/nuttx/addrenv.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/debug.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/syslog.h \
/home/hz/nuttx/xiuos/Ubiquitous/Nuttx_Fusion_XiUOS/nuttx/include/sys/uio.h

25
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/Makefile Executable file
View File

@ -0,0 +1,25 @@
############################################################################
# boards/arm/imxrt/xidatong-arm32/src/Makefile
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/Make.defs
CSRCS = hc32_boot.c hc32_appinit.c hc32_bringup.c
include $(TOPDIR)/boards/Board.mk

79
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_appinit.c Executable file
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@ -0,0 +1,79 @@
/****************************************************************************
* boards/arm/hc32/hc32f4a0/src/hc32_appinit.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/board.h>
#include "hc32f4a0.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef OK
# define OK 0
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_app_initialize
*
* Description:
* Perform application specific initialization. This function is never
* called directly from application code, but only indirectly via the
* (non-standard) boardctl() interface using the command BOARDIOC_INIT.
*
* Input Parameters:
* arg - The boardctl() argument is passed to the board_app_initialize()
* implementation without modification. The argument has no
* meaning to NuttX; the meaning of the argument is a contract
* between the board-specific initialization logic and the
* matching application logic. The value could be such things as a
* mode enumeration value, a set of DIP switch switch settings, a
* pointer to configuration data read from a file or serial FLASH,
* or whatever you would like to do with it. Every implementation
* should accept zero/NULL as a default configuration.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure to indicate the nature of the failure.
*
****************************************************************************/
int board_app_initialize(uintptr_t arg)
{
#ifdef CONFIG_BOARD_LATE_INITIALIZE
/* Board initialization already performed by board_late_initialize() */
return OK;
#else
/* Perform board-specific initialization */
return hc32_bringup();
#endif
}

128
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_boot.c Executable file
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@ -0,0 +1,128 @@
/****************************************************************************
* boards/arm/hc32/hc32f4a0/src/hc32_boot.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "nvic.h"
#include "itm.h"
/****************************************************************************
* Public Functions
****************************************************************************/
extern int hc32_bringup(void);
/****************************************************************************
* Name: hc32_boardinitialize
*
* Description:
* All HC32 architectures must provide the following entry point. This
* entry point is called early in the initialization -- after all memory
* has been configured and mapped but before any devices have been
* initialized.
*
****************************************************************************/
void hc32_boardinitialize(void)
{
//#ifdef CONFIG_SCHED_CRITMONITOR
// /* Enable ITM and DWT resources, if not left enabled by debugger. */
//
// modifyreg32(NVIC_DEMCR, 0, NVIC_DEMCR_TRCENA);
//
// /* Make sure the high speed cycle counter is running. It will be started
// * automatically only if a debugger is connected.
// */
//
// putreg32(0xc5acce55, ITM_LAR);
// modifyreg32(DWT_CTRL, 0, DWT_CTRL_CYCCNTENA_MASK);
//#endif
//
//#if defined(CONFIG_HC32_SPI1) || defined(CONFIG_HC32_SPI2) || defined(CONFIG_HC32_SPI3)
// /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak
// * function hc32_spidev_initialize() has been brought into the link.
// */
//
// if (hc32_spidev_initialize)
// {
// hc32_spidev_initialize();
// }
//#endif
//
//#ifdef CONFIG_HC32_OTGFS
// /* Initialize USB if the 1) OTG FS controller is in the configuration and
// * 2) disabled, and 3) the weak function hc32_usbinitialize() has been
// * brought into the build. Presumably either CONFIG_USBDEV or
// * CONFIG_USBHOST is also selected.
// */
//
// if (hc32_usbinitialize)
// {
// hc32_usbinitialize();
// }
//#endif
//
//#ifdef HAVE_NETMONITOR
// /* Configure board resources to support networking. */
//
// if (hc32_netinitialize)
// {
// hc32_netinitialize();
// }
//#endif
//
//#ifdef CONFIG_ARCH_LEDS
// /* Configure on-board LEDs if LED support has been selected. */
//
// board_autoled_initialize();
//#endif
}
/****************************************************************************
* Name: board_late_initialize
*
* Description:
* If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
* initialization call will be performed in the boot-up sequence to a
* function called board_late_initialize(). board_late_initialize() will be
* called immediately after up_initialize() is called and just before the
* initial application is started. This additional initialization phase
* may be used, for example, to initialize board-specific device drivers.
*
****************************************************************************/
#ifdef CONFIG_BOARD_LATE_INITIALIZE
void board_late_initialize(void)
{
/* Perform board-specific initialization */
hc32_bringup();
}
#endif

53
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/hc32f4a0/src/hc32_bringup.c Executable file
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@ -0,0 +1,53 @@
/****************************************************************************
* boards/arm/hc32/hc32f4a0/src/hc32f4a0_bringup.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdio.h>
#include <debug.h>
#include <errno.h>
#include <nuttx/fs/fs.h>
/****************************************************************************
* Name: hc32_bringup
*
* Description:
* Perform architecture-specific initialization
*
* CONFIG_BOARD_LATE_INITIALIZE=y :
* Called from board_late_initialize().
*
* CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y :
* Called from the NSH library
*
****************************************************************************/
int hc32_bringup(void)
{
int ret = 0;
printf("start %s\n", __func__);
return ret;
}

34
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/Kconfig
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@ -5,6 +5,40 @@
if ARCH_BOARD_XIDATONG_RISCV64
menuconfig BSP_USING_CH376
bool "Using CH376 device"
default n
select K210_16550_UART
select K210_16550_UART3
if BSP_USING_CH376
choice
prompt "select ch376 function."
default CH376_USB_FUNCTION
config CH376_USB_FUNCTION
bool "select ch376 usb function"
config CH376_SD_FUNCTION
bool "select ch376 sd function"
endchoice
config CH376_WORK_MODE
hex "ch376 work mode set:0x03 sd,0x06 u-disk"
default 0x03 if CH376_SD_FUNCTION
default 0x06 if CH376_USB_FUNCTION
endif # BSP_USING_CH376
menuconfig BSP_USING_ENET
bool "Using ENET device"
default n
menuconfig BSP_USING_TOUCH
bool "Using touch device"
default n
menuconfig BSP_USING_CH438
bool "Using CH438 device"
default n

77
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/4gnsh/defconfig Normal file
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@ -0,0 +1,77 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_NSH_DISABLE_LOSMART is not set
# CONFIG_STANDARD_SERIAL is not set
CONFIG_ADD_NUTTX_FETURES=y
CONFIG_ARCH="risc-v"
CONFIG_ARCH_BOARD="xidatong-riscv64"
CONFIG_ARCH_BOARD_XIDATONG_RISCV64=y
CONFIG_ARCH_CHIP="k210"
CONFIG_ARCH_CHIP_K210=y
CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BINFMT_DISABLE=y
CONFIG_BOARD_LOOPSPERMSEC=46000
CONFIG_BUILTIN=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INIT_STACKSIZE=3072
CONFIG_INTELHEX_BINARY=y
CONFIG_LIBC_PERROR_STDOUT=y
CONFIG_LIBC_STRERROR=y
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_DISABLE_MKDIR=y
CONFIG_NSH_DISABLE_RM=y
CONFIG_NSH_DISABLE_RMDIR=y
CONFIG_NSH_DISABLE_UMOUNT=y
CONFIG_NSH_READLINE=y
CONFIG_NSH_STRERROR=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=2097152
CONFIG_RAM_START=0x80400000
CONFIG_RAW_BINARY=y
CONFIG_READLINE_CMD_HISTORY=y
CONFIG_READLINE_CMD_HISTORY_LEN=100
CONFIG_READLINE_CMD_HISTORY_LINELEN=120
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_START_DAY=28
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2019
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=20
CONFIG_TESTING_GETPRIME=y
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_READLINE_TABCOMPLETION=y
CONFIG_SCHED_HPWORK=y
CONFIG_DEV_GPIO=y
CONFIG_BOARDCTL_RESET=y
CONFIG_K210_16550_UART=y
CONFIG_K210_16550_UART2=y
CONFIG_K210_16550_UART2_BASE=0x50220000
CONFIG_K210_16550_UART2_CLOCK=195000000
CONFIG_K210_16550_UART2_IRQ=39
CONFIG_K210_16550_UART2_BAUD=115200
CONFIG_K210_16550_UART2_PARITY=0
CONFIG_K210_16550_UART2_BITS=8
CONFIG_K210_16550_UART2_2STOP=0
CONFIG_K210_16550_UART2_RXBUFSIZE=128
CONFIG_K210_16550_UART2_TXBUFSIZE=128
CONFIG_SUPPORT_CONNECTION_FRAMEWORK=y
CONFIG_CONNECTION_FRAMEWORK_DEBUG=y
CONFIG_CONNECTION_ADAPTER_4G=y
CONFIG_ADAPTER_EC200T=y
CONFIG_ADAPTER_4G_EC200T="ec200t"
CONFIG_ADAPTER_EC200T_DRIVER="/dev/ttyS2"

63
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/ch376nsh/defconfig Normal file
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@ -0,0 +1,63 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_NSH_DISABLE_LOSMART is not set
# CONFIG_STANDARD_SERIAL is not set
CONFIG_ADD_NUTTX_FETURES=y
CONFIG_ARCH="risc-v"
CONFIG_ARCH_BOARD="xidatong-riscv64"
CONFIG_ARCH_BOARD_XIDATONG_RISCV64=y
CONFIG_ARCH_CHIP="k210"
CONFIG_ARCH_CHIP_K210=y
CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BINFMT_DISABLE=y
CONFIG_BOARD_LOOPSPERMSEC=46000
CONFIG_BUILTIN=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INIT_STACKSIZE=3072
CONFIG_INTELHEX_BINARY=y
CONFIG_LIBC_PERROR_STDOUT=y
CONFIG_LIBC_STRERROR=y
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_DISABLE_MKDIR=y
CONFIG_NSH_DISABLE_RM=y
CONFIG_NSH_DISABLE_RMDIR=y
CONFIG_NSH_DISABLE_UMOUNT=y
CONFIG_NSH_READLINE=y
CONFIG_NSH_STRERROR=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=2097152
CONFIG_RAM_START=0x80400000
CONFIG_RAW_BINARY=y
CONFIG_READLINE_CMD_HISTORY=y
CONFIG_READLINE_CMD_HISTORY_LEN=100
CONFIG_READLINE_CMD_HISTORY_LINELEN=120
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_START_DAY=28
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2019
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=20
CONFIG_TESTING_GETPRIME=y
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_READLINE_TABCOMPLETION=y
CONFIG_SCHED_HPWORK=y
CONFIG_DEV_GPIO=y
CONFIG_BOARDCTL_RESET=y
CONFIG_BSP_USING_CH376=y
CONFIG_CH376_USB_FUNCTION=y
CONFIG_CH376_WORK_MODE=0x06

1
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/lcdnsh/defconfig
View File

@ -63,6 +63,5 @@ CONFIG_K210_LCD=y
CONFIG_K210_LCD_BACKLIGHT=y
CONFIG_LCD=y
CONFIG_LCD_LT768=y
CONFIG_USER_TEST=y
CONFIG_USER_TEST_LCD=y

63
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/touchnsh/defconfig Normal file
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@ -0,0 +1,63 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_NSH_DISABLE_LOSMART is not set
# CONFIG_STANDARD_SERIAL is not set
CONFIG_ADD_NUTTX_FETURES=y
CONFIG_ARCH="risc-v"
CONFIG_ARCH_BOARD="xidatong-riscv64"
CONFIG_ARCH_BOARD_XIDATONG_RISCV64=y
CONFIG_ARCH_CHIP="k210"
CONFIG_ARCH_CHIP_K210=y
CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BINFMT_DISABLE=y
CONFIG_BOARD_LOOPSPERMSEC=46000
CONFIG_BUILTIN=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INIT_STACKSIZE=3072
CONFIG_INTELHEX_BINARY=y
CONFIG_LIBC_PERROR_STDOUT=y
CONFIG_LIBC_STRERROR=y
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_DISABLE_MKDIR=y
CONFIG_NSH_DISABLE_RM=y
CONFIG_NSH_DISABLE_RMDIR=y
CONFIG_NSH_DISABLE_UMOUNT=y
CONFIG_NSH_READLINE=y
CONFIG_NSH_STRERROR=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=2097152
CONFIG_RAM_START=0x80400000
CONFIG_RAW_BINARY=y
CONFIG_READLINE_CMD_HISTORY=y
CONFIG_READLINE_CMD_HISTORY_LEN=100
CONFIG_READLINE_CMD_HISTORY_LINELEN=120
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_START_DAY=28
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2019
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=20
CONFIG_TESTING_GETPRIME=y
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_READLINE_TABCOMPLETION=y
CONFIG_SCHED_HPWORK=y
CONFIG_DEV_GPIO=y
CONFIG_BOARDCTL_RESET=y
CONFIG_K210_16550_UART=y
CONFIG_K210_16550_UART3=y
CONFIG_BSP_USING_TOUCH=y

61
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/w5500nsh/defconfig Normal file
View File

@ -0,0 +1,61 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_NSH_DISABLE_LOSMART is not set
# CONFIG_STANDARD_SERIAL is not set
CONFIG_ADD_NUTTX_FETURES=y
CONFIG_ARCH="risc-v"
CONFIG_ARCH_BOARD="xidatong-riscv64"
CONFIG_ARCH_BOARD_XIDATONG_RISCV64=y
CONFIG_ARCH_CHIP="k210"
CONFIG_ARCH_CHIP_K210=y
CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BINFMT_DISABLE=y
CONFIG_BOARD_LOOPSPERMSEC=46000
CONFIG_BUILTIN=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INIT_STACKSIZE=3072
CONFIG_INTELHEX_BINARY=y
CONFIG_LIBC_PERROR_STDOUT=y
CONFIG_LIBC_STRERROR=y
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_DISABLE_MKDIR=y
CONFIG_NSH_DISABLE_RM=y
CONFIG_NSH_DISABLE_RMDIR=y
CONFIG_NSH_DISABLE_UMOUNT=y
CONFIG_NSH_READLINE=y
CONFIG_NSH_STRERROR=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=2097152
CONFIG_RAM_START=0x80400000
CONFIG_RAW_BINARY=y
CONFIG_READLINE_CMD_HISTORY=y
CONFIG_READLINE_CMD_HISTORY_LEN=100
CONFIG_READLINE_CMD_HISTORY_LINELEN=120
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_START_DAY=28
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2019
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=20
CONFIG_TESTING_GETPRIME=y
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_READLINE_TABCOMPLETION=y
CONFIG_SCHED_HPWORK=y
CONFIG_DEV_GPIO=y
CONFIG_BOARDCTL_RESET=y
CONFIG_BSP_USING_ENET=y

77
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/configs/wifinsh/defconfig Normal file
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@ -0,0 +1,77 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_NSH_DISABLE_LOSMART is not set
# CONFIG_STANDARD_SERIAL is not set
CONFIG_ADD_NUTTX_FETURES=y
CONFIG_ARCH="risc-v"
CONFIG_ARCH_BOARD="xidatong-riscv64"
CONFIG_ARCH_BOARD_XIDATONG_RISCV64=y
CONFIG_ARCH_CHIP="k210"
CONFIG_ARCH_CHIP_K210=y
CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BINFMT_DISABLE=y
CONFIG_BOARD_LOOPSPERMSEC=46000
CONFIG_BUILTIN=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INIT_STACKSIZE=3072
CONFIG_INTELHEX_BINARY=y
CONFIG_LIBC_PERROR_STDOUT=y
CONFIG_LIBC_STRERROR=y
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_DISABLE_MKDIR=y
CONFIG_NSH_DISABLE_RM=y
CONFIG_NSH_DISABLE_RMDIR=y
CONFIG_NSH_DISABLE_UMOUNT=y
CONFIG_NSH_READLINE=y
CONFIG_NSH_STRERROR=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=2097152
CONFIG_RAM_START=0x80400000
CONFIG_RAW_BINARY=y
CONFIG_READLINE_CMD_HISTORY=y
CONFIG_READLINE_CMD_HISTORY_LEN=100
CONFIG_READLINE_CMD_HISTORY_LINELEN=120
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_STACK_COLORATION=y
CONFIG_START_DAY=28
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2019
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=20
CONFIG_TESTING_GETPRIME=y
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_READLINE_TABCOMPLETION=y
CONFIG_SCHED_HPWORK=y
CONFIG_DEV_GPIO=y
CONFIG_BOARDCTL_RESET=y
CONFIG_K210_16550_UART=y
CONFIG_K210_16550_UART1=y
CONFIG_K210_16550_UART1_BASE=0x50210000
CONFIG_K210_16550_UART1_CLOCK=195000000
CONFIG_K210_16550_UART1_IRQ=38
CONFIG_K210_16550_UART1_BAUD=115200
CONFIG_K210_16550_UART1_PARITY=0
CONFIG_K210_16550_UART1_BITS=8
CONFIG_K210_16550_UART1_2STOP=0
CONFIG_K210_16550_UART1_RXBUFSIZE=128
CONFIG_K210_16550_UART1_TXBUFSIZE=128
CONFIG_SUPPORT_CONNECTION_FRAMEWORK=y
CONFIG_CONNECTION_FRAMEWORK_DEBUG=y
CONFIG_CONNECTION_ADAPTER_WIFI=y
CONFIG_ADAPTER_ESP8285_WIFI=y
CONFIG_ADAPTER_WIFI_ESP8285="esp8285_wifi"
CONFIG_ADAPTER_ESP8285_DRIVER="/dev/ttyS1"

115
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/include/board.h
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@ -39,12 +39,10 @@
* Pre-processor Definitions
****************************************************************************/
#define BOARD_LED_PAD 14 /* Connected to red led */
/* Map pad 14 to gpiohs io 0 */
#define BOARD_LED_IO_FUNC K210_IO_FUNC_GPIOHS0
#define BOARD_LED_IO 0
#define LED_STARTED 0 /* N/C */
#define LED_HEAPALLOCATE 1 /* N/C */
@ -57,7 +55,7 @@
/* GPIO pins used by the GPIO Subsystem */
#define BOARD_NGPIOOUT 3 /* Amount of GPIO Output pins */
#define BOARD_NGPIOOUT 3 /* Amount of register GPIO Output pins */
#define BOARD_NGPIOINT 0 /* Amount of GPIO Input */
/****************************************************************************
@ -79,6 +77,115 @@ extern "C"
#define EXTERN extern
#endif
/*************************** GPIO define ***************************/
/* Connected to red led */
#define BOARD_LED_PAD 14
/* UART IO */
#define GPIO_WIFI_RXD 7
#define GPIO_WIFI_TXD 6
#define GPIO_EC200T_RXD 21
#define GPIO_EC200T_TXD 20
#define GPIO_CH376T_RXD 22
#define GPIO_CH376T_TXD 23
/* ch438 IO */
#define CH438_ALE_PIN 24
#define CH438_NWR_PIN 25
#define CH438_NRD_PIN 26
#define CH438_D0_PIN 27
#define CH438_D1_PIN 28
#define CH438_D2_PIN 29
#define CH438_D3_PIN 30
#define CH438_D4_PIN 31
#define CH438_D5_PIN 32
#define CH438_D6_PIN 33
#define CH438_D7_PIN 34
#define CH438_INT_PIN 35
/* w5500 IO */
#define BSP_ENET_SCLK 9
#define BSP_ENET_MISO 10
#define BSP_ENET_MOSI 11
#define BSP_ENET_NCS 12
#define BSP_ENET_NRST 13
#define BSP_ENET_NINT 14
/* LCD IO */
#define BSP_LCD_NRST 37
#define BSP_LCD_SCLK 38
#define BSP_LCD_MOSI 39
#define BSP_LCD_MISO 40
#define BSP_LCD_NCS 41
#define BSP_LCD_BL_PIN 47
/* I2C */
#define BSP_IIC_SDA 15
#define BSP_IIC_SCL 17
/* other mode io */
#define GPIO_E220_M0 44
#define GPIO_E220_M1 45
#define GPIO_E18_MODE 46
#define GPIO_WIFI_EN 8
/************************** end GPIO define **************************/
/*************************** FPIOA define ***************************/
#define BOARD_LED_IO 0
/* UART FPOA */
#define FPOA_USART1_RX K210_IO_FUNC_UART1_RX
#define FPOA_USART1_TX K210_IO_FUNC_UART1_TX
#define FPOA_USART2_RX K210_IO_FUNC_UART2_RX
#define FPOA_USART2_TX K210_IO_FUNC_UART2_TX
#define FPOA_USART3_RX K210_IO_FUNC_UART3_RX
#define FPOA_USART3_TX K210_IO_FUNC_UART3_TX
/* ch438 FPIOA */
#define FPIOA_CH438_ALE 11
#define FPIOA_CH438_NWR 12
#define FPIOA_CH438_NRD 13
#define FPIOA_CH438_D0 14
#define FPIOA_CH438_D1 15
#define FPIOA_CH438_D2 16
#define FPIOA_CH438_D3 17
#define FPIOA_CH438_D4 18
#define FPIOA_CH438_D5 29
#define FPIOA_CH438_D6 20
#define FPIOA_CH438_D7 31
#define FPIOA_CH438_INT 22
/* w5500 FPIOA */
#define FPIOA_ENET_NRST 0
#define FPIOA_ENET_NINT 9
#define FPIOA_ENET_SCLK 28
#define FPIOA_ENET_MISO 29
#define FPIOA_ENET_MOSI 23
#define FPIOA_ENET_NCS 31
/* LCD FPIOA */
#define FPIOA_LCD_NRST 0
#define FPIOA_LCD_BL 9
#define FPIOA_LCD_SCLK 28
#define FPIOA_LCD_MOSI 29
#define FPIOA_LCD_MISO 23
#define FPIOA_LCD_NCS 31
/* I2C */
#define FPIOA_IIC_SDA 7
#define FPIOA_IIC_SCL 8
/* other mode FPIOA */
#define FPIOA_E220_M0 1
#define FPIOA_E220_M1 2
#define FPIOA_E18_MODE 3
#define FPIOA_WIFI_EN 4
/************************** end FPIOA define **************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/

14
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/Makefile
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@ -35,7 +35,7 @@ CSRCS += k210_leds.c
endif
ifeq ($(CONFIG_K210_LCD),y)
CSRCS += k210_lcd.c lcd_demo.c
CSRCS += k210_lcd.c
endif
ifeq ($(CONFIG_DEV_GPIO),y)
@ -46,4 +46,16 @@ ifeq ($(CONFIG_BSP_USING_CH438),y)
CSRCS += k210_ch438.c ch438_demo.c
endif
ifeq ($(CONFIG_BSP_USING_CH376),y)
CSRCS += k210_ch376.c ch376_demo.c
endif
ifeq ($(CONFIG_BSP_USING_ENET),y)
CSRCS += k210_w5500.c
endif
ifeq ($(CONFIG_BSP_USING_TOUCH),y)
CSRCS += k210_touch.c
endif
include $(TOPDIR)/boards/Board.mk

70
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/ch376_demo.c Normal file
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@ -0,0 +1,70 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file ch376_demo.c
* @brief xidatong-riscv64 ch376_demo.c
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.10.11
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include "k210_ch376.h"
uint8_t buf[64];
void CH376Demo(void)
{
uint8_t s;
s = mInitCH376Host();
printf ("ch376 init stat=0x%02x\n",(uint16_t)s);
#ifdef CONFIG_CH376_USB_FUNCTION
printf( "Wait Udisk/SD\n" );
while ( CH376DiskConnect( ) != USB_INT_SUCCESS )
{
up_mdelay( 100 );
}
#endif
for ( s = 0; s < 10; s ++ )
{
up_mdelay( 50 );
printf( "Ready ?\n" );
if ( CH376DiskMount( ) == USB_INT_SUCCESS ) break;
}
s = CH376ReadBlock( buf );
if ( s == sizeof( INQUIRY_DATA ) )
{
buf[ s ] = 0;
printf( "UdiskInfo: %s\n", ((P_INQUIRY_DATA)buf) -> VendorIdStr );
}
printf( "Create /YEAR2022/DEMO2022.TXT \n" );
s = CH376DirCreate((PUINT8)"/YEAR2022" );
printf("CH376DirCreate:0x%02x\n",(uint16_t)s );
s = CH376FileCreatePath((PUINT8)"/YEAR2022/DEMO2022.TXT" );
printf( "CH376FileCreatePath:0x%02x\n",(uint16_t)s );
printf( "Write some data to file\n" );
strcpy( (char *)buf, "This is 演示数据\xd\xa" );
s = CH376ByteWrite(buf, strlen((char *)buf), NULL );
printf( "CH376ByteWrite:0x%02x\n",(uint16_t)s );
printf( "Close\n" );
s = CH376FileClose( TRUE );
printf( "CH376FileClose:0x%02x\n",(uint16_t)s );
}

584
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/ch376inc.h Normal file
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@ -0,0 +1,584 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file ch376inc.h
* @brief xidatong-riscv64 ch376inc.h
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.10.10
*/
#ifndef __CH376INC_H__
#define __CH376INC_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Common types and constant definitions */
#ifndef TRUE
#define TRUE 1
#define FALSE 0
#endif
#ifndef NULL
#define NULL 0
#endif
#ifndef UINT8
typedef unsigned char UINT8;
#endif
#ifndef UINT16
typedef unsigned short UINT16;
#endif
#ifndef UINT32
typedef unsigned long UINT32;
#endif
#ifndef PUINT8
typedef unsigned char *PUINT8;
#endif
#ifndef PUINT16
typedef unsigned short *PUINT16;
#endif
#ifndef PUINT32
typedef unsigned long *PUINT32;
#endif
#ifndef UINT8V
typedef unsigned char volatile UINT8V;
#endif
#ifndef PUINT8V
typedef unsigned char volatile *PUINT8V;
#endif
#define CH376_DAT_BLOCK_LEN 0x40
#define CMD01_GET_IC_VER 0x01
#define CMD21_SET_BAUDRATE 0x02
#define CMD00_ENTER_SLEEP 0x03
#define CMD00_RESET_ALL 0x05
#define CMD11_CHECK_EXIST 0x06
#define CMD20_CHK_SUSPEND 0x0B
#define CMD20_SET_SDO_INT 0x0B
#define CMD14_GET_FILE_SIZE 0x0C
#define CMD50_SET_FILE_SIZE 0x0D
#define CMD11_SET_USB_MODE 0x15
#define CMD01_GET_STATUS 0x22
#define CMD00_UNLOCK_USB 0x23
#define CMD01_RD_USB_DATA0 0x27
#define CMD01_RD_USB_DATA 0x28
#define CMD10_WR_USB_DATA7 0x2B
#define CMD10_WR_HOST_DATA 0x2C
#define CMD01_WR_REQ_DATA 0x2D
#define CMD20_WR_OFS_DATA 0x2E
#define CMD10_SET_FILE_NAME 0x2F
#define CMD0H_DISK_CONNECT 0x30
#define CMD0H_DISK_MOUNT 0x31
#define CMD0H_FILE_OPEN 0x32
#define CMD0H_FILE_ENUM_GO 0x33
#define CMD0H_FILE_CREATE 0x34
#define CMD0H_FILE_ERASE 0x35
#define CMD1H_FILE_CLOSE 0x36
#define CMD1H_DIR_INFO_READ 0x37
#define CMD0H_DIR_INFO_SAVE 0x38
#define CMD4H_BYTE_LOCATE 0x39
#define CMD2H_BYTE_READ 0x3A
#define CMD0H_BYTE_RD_GO 0x3B
#define CMD2H_BYTE_WRITE 0x3C
#define CMD0H_BYTE_WR_GO 0x3D
#define CMD0H_DISK_CAPACITY 0x3E
#define CMD0H_DISK_QUERY 0x3F
#define CMD0H_DIR_CREATE 0x40
#define CMD4H_SEC_LOCATE 0x4A
#define CMD1H_SEC_READ 0x4B
#define CMD1H_SEC_WRITE 0x4C
#define CMD0H_DISK_BOC_CMD 0x50
#define CMD5H_DISK_READ 0x54
#define CMD0H_DISK_RD_GO 0x55
#define CMD5H_DISK_WRITE 0x56
#define CMD0H_DISK_WR_GO 0x57
#define CMD10_SET_USB_SPEED 0x04
#define CMD11_GET_DEV_RATE 0x0A
#define CMD11_GET_TOGGLE 0x0A
#define CMD11_READ_VAR8 0x0A
#define CMD20_SET_RETRY 0x0B
#define CMD20_WRITE_VAR8 0x0B
#define CMD14_READ_VAR32 0x0C
#define CMD50_WRITE_VAR32 0x0D
#define CMD01_DELAY_100US 0x0F
#define CMD40_SET_USB_ID 0x12
#define CMD10_SET_USB_ADDR 0x13
#define CMD01_TEST_CONNECT 0x16
#define CMD00_ABORT_NAK 0x17
#define CMD10_SET_ENDP2 0x18
#define CMD10_SET_ENDP3 0x19
#define CMD10_SET_ENDP4 0x1A
#define CMD10_SET_ENDP5 0x1B
#define CMD10_SET_ENDP6 0x1C
#define CMD10_SET_ENDP7 0x1D
#define CMD00_DIRTY_BUFFER 0x25
#define CMD10_WR_USB_DATA3 0x29
#define CMD10_WR_USB_DATA5 0x2A
#define CMD1H_CLR_STALL 0x41
#define CMD1H_SET_ADDRESS 0x45
#define CMD1H_GET_DESCR 0x46
#define CMD1H_SET_CONFIG 0x49
#define CMD0H_AUTO_SETUP 0x4D
#define CMD2H_ISSUE_TKN_X 0x4E
#define CMD1H_ISSUE_TOKEN 0x4F
#define CMD0H_DISK_INIT 0x51
#define CMD0H_DISK_RESET 0x52
#define CMD0H_DISK_SIZE 0x53
#define CMD0H_DISK_INQUIRY 0x58
#define CMD0H_DISK_READY 0x59
#define CMD0H_DISK_R_SENSE 0x5A
#define CMD0H_RD_DISK_SEC 0x5B
#define CMD0H_WR_DISK_SEC 0x5C
#define CMD0H_DISK_MAX_LUN 0x5D
/* The following definitions are only for compatibility with the command name format in the INCLUDE file of CH375 */
#ifndef _NO_CH375_COMPATIBLE_
#define CMD_GET_IC_VER CMD01_GET_IC_VER
#define CMD_SET_BAUDRATE CMD21_SET_BAUDRATE
#define CMD_ENTER_SLEEP CMD00_ENTER_SLEEP
#define CMD_RESET_ALL CMD00_RESET_ALL
#define CMD_CHECK_EXIST CMD11_CHECK_EXIST
#define CMD_CHK_SUSPEND CMD20_CHK_SUSPEND
#define CMD_SET_SDO_INT CMD20_SET_SDO_INT
#define CMD_GET_FILE_SIZE CMD14_GET_FILE_SIZE
#define CMD_SET_FILE_SIZE CMD50_SET_FILE_SIZE
#define CMD_SET_USB_MODE CMD11_SET_USB_MODE
#define CMD_GET_STATUS CMD01_GET_STATUS
#define CMD_UNLOCK_USB CMD00_UNLOCK_USB
#define CMD_RD_USB_DATA0 CMD01_RD_USB_DATA0
#define CMD_RD_USB_DATA CMD01_RD_USB_DATA
#define CMD_WR_USB_DATA7 CMD10_WR_USB_DATA7
#define CMD_WR_HOST_DATA CMD10_WR_HOST_DATA
#define CMD_WR_REQ_DATA CMD01_WR_REQ_DATA
#define CMD_WR_OFS_DATA CMD20_WR_OFS_DATA
#define CMD_SET_FILE_NAME CMD10_SET_FILE_NAME
#define CMD_DISK_CONNECT CMD0H_DISK_CONNECT
#define CMD_DISK_MOUNT CMD0H_DISK_MOUNT
#define CMD_FILE_OPEN CMD0H_FILE_OPEN
#define CMD_FILE_ENUM_GO CMD0H_FILE_ENUM_GO
#define CMD_FILE_CREATE CMD0H_FILE_CREATE
#define CMD_FILE_ERASE CMD0H_FILE_ERASE
#define CMD_FILE_CLOSE CMD1H_FILE_CLOSE
#define CMD_DIR_INFO_READ CMD1H_DIR_INFO_READ
#define CMD_DIR_INFO_SAVE CMD0H_DIR_INFO_SAVE
#define CMD_BYTE_LOCATE CMD4H_BYTE_LOCATE
#define CMD_BYTE_READ CMD2H_BYTE_READ
#define CMD_BYTE_RD_GO CMD0H_BYTE_RD_GO
#define CMD_BYTE_WRITE CMD2H_BYTE_WRITE
#define CMD_BYTE_WR_GO CMD0H_BYTE_WR_GO
#define CMD_DISK_CAPACITY CMD0H_DISK_CAPACITY
#define CMD_DISK_QUERY CMD0H_DISK_QUERY
#define CMD_DIR_CREATE CMD0H_DIR_CREATE
#define CMD_SEC_LOCATE CMD4H_SEC_LOCATE
#define CMD_SEC_READ CMD1H_SEC_READ
#define CMD_SEC_WRITE CMD1H_SEC_WRITE
#define CMD_DISK_BOC_CMD CMD0H_DISK_BOC_CMD
#define CMD_DISK_READ CMD5H_DISK_READ
#define CMD_DISK_RD_GO CMD0H_DISK_RD_GO
#define CMD_DISK_WRITE CMD5H_DISK_WRITE
#define CMD_DISK_WR_GO CMD0H_DISK_WR_GO
#define CMD_SET_USB_SPEED CMD10_SET_USB_SPEED
#define CMD_GET_DEV_RATE CMD11_GET_DEV_RATE
#define CMD_GET_TOGGLE CMD11_GET_TOGGLE
#define CMD_READ_VAR8 CMD11_READ_VAR8
#define CMD_SET_RETRY CMD20_SET_RETRY
#define CMD_WRITE_VAR8 CMD20_WRITE_VAR8
#define CMD_READ_VAR32 CMD14_READ_VAR32
#define CMD_WRITE_VAR32 CMD50_WRITE_VAR32
#define CMD_DELAY_100US CMD01_DELAY_100US
#define CMD_SET_USB_ID CMD40_SET_USB_ID
#define CMD_SET_USB_ADDR CMD10_SET_USB_ADDR
#define CMD_TEST_CONNECT CMD01_TEST_CONNECT
#define CMD_ABORT_NAK CMD00_ABORT_NAK
#define CMD_SET_ENDP2 CMD10_SET_ENDP2
#define CMD_SET_ENDP3 CMD10_SET_ENDP3
#define CMD_SET_ENDP4 CMD10_SET_ENDP4
#define CMD_SET_ENDP5 CMD10_SET_ENDP5
#define CMD_SET_ENDP6 CMD10_SET_ENDP6
#define CMD_SET_ENDP7 CMD10_SET_ENDP7
#define CMD_DIRTY_BUFFER CMD00_DIRTY_BUFFER
#define CMD_WR_USB_DATA3 CMD10_WR_USB_DATA3
#define CMD_WR_USB_DATA5 CMD10_WR_USB_DATA5
#define CMD_CLR_STALL CMD1H_CLR_STALL
#define CMD_SET_ADDRESS CMD1H_SET_ADDRESS
#define CMD_GET_DESCR CMD1H_GET_DESCR
#define CMD_SET_CONFIG CMD1H_SET_CONFIG
#define CMD_AUTO_SETUP CMD0H_AUTO_SETUP
#define CMD_ISSUE_TKN_X CMD2H_ISSUE_TKN_X
#define CMD_ISSUE_TOKEN CMD1H_ISSUE_TOKEN
#define CMD_DISK_INIT CMD0H_DISK_INIT
#define CMD_DISK_RESET CMD0H_DISK_RESET
#define CMD_DISK_SIZE CMD0H_DISK_SIZE
#define CMD_DISK_INQUIRY CMD0H_DISK_INQUIRY
#define CMD_DISK_READY CMD0H_DISK_READY
#define CMD_DISK_R_SENSE CMD0H_DISK_R_SENSE
#define CMD_RD_DISK_SEC CMD0H_RD_DISK_SEC
#define CMD_WR_DISK_SEC CMD0H_WR_DISK_SEC
#define CMD_DISK_MAX_LUN CMD0H_DISK_MAX_LUN
#endif
/* ********************************************************************************************************************* */
#ifndef PARA_STATE_INTB
#define PARA_STATE_INTB 0x80
#define PARA_STATE_BUSY 0x10
#endif
#ifndef SER_CMD_TIMEOUT
#define SER_CMD_TIMEOUT 32
#define SER_SYNC_CODE1 0x57
#define SER_SYNC_CODE2 0xAB
#endif
#ifndef CMD_RET_SUCCESS
#define CMD_RET_SUCCESS 0x51
#define CMD_RET_ABORT 0x5F
#endif
/***********************************************************************************************************************/
#ifndef USB_INT_EP0_SETUP
#define USB_INT_USB_SUSPEND 0x05
#define USB_INT_WAKE_UP 0x06
#define USB_INT_EP0_SETUP 0x0C
#define USB_INT_EP0_OUT 0x00
#define USB_INT_EP0_IN 0x08
#define USB_INT_EP1_OUT 0x01
#define USB_INT_EP1_IN 0x09
#define USB_INT_EP2_OUT 0x02
#define USB_INT_EP2_IN 0x0A
#define USB_INT_BUS_RESET1 0x03
#define USB_INT_BUS_RESET2 0x07
#define USB_INT_BUS_RESET3 0x0B
#define USB_INT_BUS_RESET4 0x0F
#endif
#ifndef USB_INT_SUCCESS
#define USB_INT_SUCCESS 0x14
#define USB_INT_CONNECT 0x15
#define USB_INT_DISCONNECT 0x16
#define USB_INT_BUF_OVER 0x17
#define USB_INT_USB_READY 0x18
#define USB_INT_DISK_READ 0x1D
#define USB_INT_DISK_WRITE 0x1E
#define USB_INT_DISK_ERR 0x1F
#endif
#ifndef ERR_DISK_DISCON
#define ERR_DISK_DISCON 0x82
#define ERR_LARGE_SECTOR 0x84
#define ERR_TYPE_ERROR 0x92
#define ERR_BPB_ERROR 0xA1
#define ERR_DISK_FULL 0xB1
#define ERR_FDT_OVER 0xB2
#define ERR_FILE_CLOSE 0xB4
#define ERR_OPEN_DIR 0x41
#define ERR_MISS_FILE 0x42
#define ERR_FOUND_NAME 0x43
#define ERR_MISS_DIR 0xB3
#define ERR_LONG_BUF_OVER 0x48
#define ERR_LONG_NAME_ERR 0x49
#define ERR_NAME_EXIST 0x4A
#endif
/* ******************************************************************************************************************** */
#ifndef DEF_DISK_UNKNOWN
#define DEF_DISK_UNKNOWN 0x00
#define DEF_DISK_DISCONN 0x01
#define DEF_DISK_CONNECT 0x02
#define DEF_DISK_MOUNTED 0x03
#define DEF_DISK_READY 0x10
#define DEF_DISK_OPEN_ROOT 0x12
#define DEF_DISK_OPEN_DIR 0x13
#define DEF_DISK_OPEN_FILE 0x14
#endif
/* **********************************************************************************************************************/
#ifndef DEF_SECTOR_SIZE
#define DEF_SECTOR_SIZE 512
#endif
#ifndef DEF_WILDCARD_CHAR
#define DEF_WILDCARD_CHAR 0x2A
#define DEF_SEPAR_CHAR1 0x5C
#define DEF_SEPAR_CHAR2 0x2F
#define DEF_FILE_YEAR 2004
#define DEF_FILE_MONTH 1
#define DEF_FILE_DATE 1
#endif
#ifndef ATTR_DIRECTORY
typedef struct _FAT_DIR_INFO {
UINT8 DIR_Name[11];
UINT8 DIR_Attr;
UINT8 DIR_NTRes;
UINT8 DIR_CrtTimeTenth;
UINT16 DIR_CrtTime;
UINT16 DIR_CrtDate;
UINT16 DIR_LstAccDate;
UINT16 DIR_FstClusHI;
UINT16 DIR_WrtTime;
UINT16 DIR_WrtDate;
UINT16 DIR_FstClusLO;
UINT32 DIR_FileSize;
} FAT_DIR_INFO, *P_FAT_DIR_INFO;
#define ATTR_READ_ONLY 0x01
#define ATTR_HIDDEN 0x02
#define ATTR_SYSTEM 0x04
#define ATTR_VOLUME_ID 0x08
#define ATTR_DIRECTORY 0x10
#define ATTR_ARCHIVE 0x20
#define ATTR_LONG_NAME (ATTR_READ_ONLY | ATTR_HIDDEN | ATTR_SYSTEM | ATTR_VOLUME_ID)
#define ATTR_LONG_NAME_MASK (ATTR_LONG_NAME | ATTR_DIRECTORY | ATTR_ARCHIVE)
#define MAKE_FILE_TIME( h, m, s ) ( (h<<11) + (m<<5) + (s>>1) )
#define MAKE_FILE_DATE( y, m, d ) ( ((y-1980)<<9) + (m<<5) + d )
#define LONE_NAME_MAX_CHAR (255*2)
#define LONG_NAME_PER_DIR (13*2)
#endif
/* ********************************************************************************************************************* */
#ifndef SPC_CMD_INQUIRY
#define SPC_CMD_INQUIRY 0x12
#define SPC_CMD_READ_CAPACITY 0x25
#define SPC_CMD_READ10 0x28
#define SPC_CMD_WRITE10 0x2A
#define SPC_CMD_TEST_READY 0x00
#define SPC_CMD_REQUEST_SENSE 0x03
#define SPC_CMD_MODESENSE6 0x1A
#define SPC_CMD_MODESENSE10 0x5A
#define SPC_CMD_START_STOP 0x1B
typedef struct _BULK_ONLY_CBW {
UINT32 CBW_Sig;
UINT32 CBW_Tag;
UINT8 CBW_DataLen0;
UINT8 CBW_DataLen1;
UINT16 CBW_DataLen2;
UINT8 CBW_Flag;
UINT8 CBW_LUN;
UINT8 CBW_CB_Len;
UINT8 CBW_CB_Buf[16];
} BULK_ONLY_CBW, *P_BULK_ONLY_CBW;
typedef struct _INQUIRY_DATA {
UINT8 DeviceType;
UINT8 RemovableMedia;
UINT8 Versions;
UINT8 DataFormatAndEtc;
UINT8 AdditionalLength;
UINT8 Reserved1;
UINT8 Reserved2;
UINT8 MiscFlag;
UINT8 VendorIdStr[8];
UINT8 ProductIdStr[16];
UINT8 ProductRevStr[4];
} INQUIRY_DATA, *P_INQUIRY_DATA;
typedef struct _SENSE_DATA {
UINT8 ErrorCode;
UINT8 SegmentNumber;
UINT8 SenseKeyAndEtc;
UINT8 Information0;
UINT8 Information1;
UINT8 Information2;
UINT8 Information3;
UINT8 AdditSenseLen;
UINT8 CmdSpecInfo[4];
UINT8 AdditSenseCode;
UINT8 AddSenCodeQual;
UINT8 FieldReplaUnit;
UINT8 SenseKeySpec[3];
} SENSE_DATA, *P_SENSE_DATA;
#endif
/* ********************************************************************************************************************* */
#ifndef MAX_FILE_NAME_LEN
#define MAX_FILE_NAME_LEN (13+1)
typedef union _CH376_CMD_DATA {
struct {
UINT8 mBuffer[ MAX_FILE_NAME_LEN ];
} Default;
INQUIRY_DATA DiskMountInq;
FAT_DIR_INFO OpenDirInfo;
FAT_DIR_INFO EnumDirInfo;
struct {
UINT8 mUpdateFileSz;
} FileCLose;
struct {
UINT8 mDirInfoIndex;
} DirInfoRead;
union {
UINT32 mByteOffset;
UINT32 mSectorLba;
} ByteLocate;
struct {
UINT16 mByteCount;
} ByteRead;
struct {
UINT16 mByteCount;
} ByteWrite;
union {
UINT32 mSectorOffset;
UINT32 mSectorLba;
} SectorLocate;
struct {
UINT8 mSectorCount;
UINT8 mReserved1;
UINT8 mReserved2;
UINT8 mReserved3;
UINT32 mStartSector;
} SectorRead;
struct {
UINT8 mSectorCount;
UINT8 mReserved1;
UINT8 mReserved2;
UINT8 mReserved3;
UINT32 mStartSector;
} SectorWrite;
struct {
UINT32 mDiskSizeSec;
} DiskCapacity;
struct {
UINT32 mTotalSector;
UINT32 mFreeSector;
UINT8 mDiskFat;
} DiskQuery;
BULK_ONLY_CBW DiskBocCbw;
struct {
UINT8 mMaxLogicUnit;
} DiskMaxLun;
INQUIRY_DATA DiskInitInq;
INQUIRY_DATA DiskInqData;
SENSE_DATA ReqSenseData;
struct {
UINT32 mDiskSizeSec;
} DiskSize;
struct {
UINT32 mStartSector;
UINT8 mSectorCount;
} DiskRead;
struct {
UINT32 mStartSector;
UINT8 mSectorCount;
} DiskWrite;
} CH376_CMD_DATA, *P_CH376_CMD_DATA;
#endif
/* ********************************************************************************************************************* */
#ifndef VAR_FILE_SIZE
#define VAR_SYS_BASE_INFO 0x20
#define VAR_RETRY_TIMES 0x25
#define VAR_FILE_BIT_FLAG 0x26
#define VAR_DISK_STATUS 0x2B
#define VAR_SD_BIT_FLAG 0x30
#define VAR_UDISK_TOGGLE 0x31
#define VAR_UDISK_LUN 0x34
#define VAR_SEC_PER_CLUS 0x38
#define VAR_FILE_DIR_INDEX 0x3B
#define VAR_CLUS_SEC_OFS 0x3C
#define VAR_DISK_ROOT 0x44
#define VAR_DSK_TOTAL_CLUS 0x48
#define VAR_DSK_START_LBA 0x4C
#define VAR_DSK_DAT_START 0x50
#define VAR_LBA_BUFFER 0x54
#define VAR_LBA_CURRENT 0x58
#define VAR_FAT_DIR_LBA 0x5C
#define VAR_START_CLUSTER 0x60
#define VAR_CURRENT_CLUST 0x64
#define VAR_FILE_SIZE 0x68
#define VAR_CURRENT_OFFSET 0x6C
#endif
/* ********************************************************************************************************************* */
#ifndef DEF_USB_PID_SETUP
#define DEF_USB_PID_NULL 0x00
#define DEF_USB_PID_SOF 0x05
#define DEF_USB_PID_SETUP 0x0D
#define DEF_USB_PID_IN 0x09
#define DEF_USB_PID_OUT 0x01
#define DEF_USB_PID_ACK 0x02
#define DEF_USB_PID_NAK 0x0A
#define DEF_USB_PID_STALL 0x0E
#define DEF_USB_PID_DATA0 0x03
#define DEF_USB_PID_DATA1 0x0B
#define DEF_USB_PID_PRE 0x0C
#endif
#ifndef DEF_USB_REQ_TYPE
#define DEF_USB_REQ_READ 0x80
#define DEF_USB_REQ_WRITE 0x00
#define DEF_USB_REQ_TYPE 0x60
#define DEF_USB_REQ_STAND 0x00
#define DEF_USB_REQ_CLASS 0x20
#define DEF_USB_REQ_VENDOR 0x40
#define DEF_USB_REQ_RESERVE 0x60
#endif
#ifndef DEF_USB_GET_DESCR
#define DEF_USB_CLR_FEATURE 0x01
#define DEF_USB_SET_FEATURE 0x03
#define DEF_USB_GET_STATUS 0x00
#define DEF_USB_SET_ADDRESS 0x05
#define DEF_USB_GET_DESCR 0x06
#define DEF_USB_SET_DESCR 0x07
#define DEF_USB_GET_CONFIG 0x08
#define DEF_USB_SET_CONFIG 0x09
#define DEF_USB_GET_INTERF 0x0A
#define DEF_USB_SET_INTERF 0x0B
#define DEF_USB_SYNC_FRAME 0x0C
#endif
/* ********************************************************************************************************************* */
#ifdef __cplusplus
}
#endif
#endif

40
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_bringup.c
View File

@ -32,10 +32,16 @@
#include <nuttx/board.h>
#include <nuttx/fs/fs.h>
#include <nuttx/arch.h>
#include "k210.h"
#include "k210_clockconfig.h"
#include "xidatong-riscv64.h"
#include <arch/board/board.h>
#include "k210_sysctl.h"
#include "k210_fpioa.h"
#include "k210_gpiohs.h"
#include "k210_gpio_common.h"
#ifdef CONFIG_BSP_USING_CH438
# include "k210_ch438.h"
@ -78,11 +84,35 @@ int k210_bringup(void)
#ifdef CONFIG_K210_LCD
k210_sysctl_init();
ret = board_lcd_initialize();
if (ret < 0)
{
syslog(LOG_NOTICE, "board lcd initialize %d\n", ret);
}
board_lcd_initialize();
#endif
#ifdef CONFIG_K210_16550_UART1
sysctl_clock_enable(SYSCTL_CLOCK_UART1);
sysctl_reset(SYSCTL_RESET_UART1);
fpioa_set_function(GPIO_WIFI_TXD, FPOA_USART1_RX);
fpioa_set_function(GPIO_WIFI_RXD, FPOA_USART1_TX);
fpioa_set_function(GPIO_WIFI_EN, K210_IO_FUNC_GPIOHS0 + GPIO_WIFI_EN);
k210_gpiohs_set_direction(GPIO_WIFI_EN, GPIO_DM_OUTPUT);
k210_gpiohs_set_value(GPIO_WIFI_EN, GPIO_PV_LOW);
up_mdelay(50);
k210_gpiohs_set_value(GPIO_WIFI_EN, GPIO_PV_HIGH);
#endif
#ifdef CONFIG_K210_16550_UART2
sysctl_clock_enable(SYSCTL_CLOCK_UART2);
sysctl_reset(SYSCTL_RESET_UART2);
fpioa_set_function(GPIO_EC200T_RXD, FPOA_USART2_RX);
fpioa_set_function(GPIO_EC200T_TXD, FPOA_USART2_TX);
#endif
#ifdef CONFIG_K210_16550_UART3
sysctl_clock_enable(SYSCTL_CLOCK_UART3);
sysctl_reset(SYSCTL_RESET_UART3);
fpioa_set_function(GPIO_CH376T_RXD, FPOA_USART3_RX);
fpioa_set_function(GPIO_CH376T_TXD, FPOA_USART3_TX);
#endif
return ret;

960
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ch376.c Normal file
View File

@ -0,0 +1,960 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file k210_ch376.c
* @brief xidatong-riscv64 k210_ch376.c
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.10.10
*/
#if 0
#define DEF_IC_V43_U 1
#endif
#include "k210_ch376.h"
/****************************************************************************
* Private Data
****************************************************************************/
static int fd;
/* Serial port mode is not used */
void xEndCH376Cmd(void)
{
}
void xWriteCH376Cmd(UINT8 cmd)
{
UINT8 temp[3];
temp[0] = 0x57;
temp[1] = 0xab;
temp[2] = cmd;
up_udelay(5);
write(fd, temp, 3);
}
void xWriteCH376Data(UINT8 dat)
{
UINT8 tmp = dat;
write(fd, &tmp, 1);
up_udelay(2);
}
UINT8 xReadCH376Data(void)
{
UINT32 i;
UINT8 data;
int res;
for(i=0;i<500000;i++)
{
res = read(fd, &data, 1);
if(res == 1)
{
return ((UINT8)data);
}
up_udelay(1);
}
return ERR_USB_UNKNOWN;
}
UINT8 CH376ReadBlock(PUINT8 buf)
{
UINT8 s, l;
xWriteCH376Cmd( CMD01_RD_USB_DATA0 );
s = l = xReadCH376Data( );
if ( l ) {
do {
*buf = xReadCH376Data( );
buf ++;
} while ( -- l );
}
xEndCH376Cmd( );
return( s );
}
UINT8 Query376Interrupt(void)
{
//When an interrupt occurs, the serial port will receive a data, read it directly, and discard it
if(xReadCH376Data() == ERR_USB_UNKNOWN) return FALSE ;
else return TRUE ;
}
/* CH376 INIT */
UINT8 mInitCH376Host(void)
{
UINT8 res;
/* After power on, delay operation for at least 50ms */
up_mdelay(50);
fd = open("/dev/ttyS3", O_RDWR);
up_mdelay(600);
/* Test the communication interface between SCM and CH376 */
xWriteCH376Cmd(CMD11_CHECK_EXIST);
xWriteCH376Data(0x65);
res = xReadCH376Data();
xEndCH376Cmd();
if ( res != 0x9A ) return( ERR_USB_UNKNOWN );
xWriteCH376Cmd(CMD11_SET_USB_MODE); /* SET USB MODE */
xWriteCH376Data(CONFIG_CH376_WORK_MODE);
up_udelay(20);
res = xReadCH376Data();
xEndCH376Cmd();
if (res == CMD_RET_SUCCESS) return(USB_INT_SUCCESS);
else return(ERR_USB_UNKNOWN); /* SET MODE ERROR */
}
/* Write the requested data block to the internally specified buffer, and return the length */
UINT8 CH376WriteReqBlock(PUINT8 buf)
{
UINT8 s, l;
xWriteCH376Cmd( CMD01_WR_REQ_DATA );
s = l = xReadCH376Data();
if ( l ) {
do {
xWriteCH376Data( *buf );
buf ++;
} while ( -- l );
}
xEndCH376Cmd( );
return( s );
}
/* Write data block to the send buffer of USB host endpoint */
void CH376WriteHostBlock(PUINT8 buf, UINT8 len)
{
xWriteCH376Cmd( CMD10_WR_HOST_DATA );
xWriteCH376Data( len );
if ( len ) {
do {
xWriteCH376Data( *buf );
buf ++;
} while ( -- len );
}
xEndCH376Cmd( );
}
/* Specify offset address to write data block to internal buffer */
void CH376WriteOfsBlock( PUINT8 buf, UINT8 ofs, UINT8 len )
{
xWriteCH376Cmd( CMD20_WR_OFS_DATA );
xWriteCH376Data( ofs ); /* Offset address */
xWriteCH376Data( len ); /* length */
if ( len ) {
do {
xWriteCH376Data( *buf );
buf ++;
} while ( -- len );
}
xEndCH376Cmd( );
}
/* Set the file name of the file to be operated on */
void CH376SetFileName( PUINT8 name )
{
UINT8 c;
#ifndef DEF_IC_V43_U
UINT8 s;
xWriteCH376Cmd( CMD01_GET_IC_VER );
if ( xReadCH376Data( ) < 0x43 ) {
if ( CH376ReadVar8( VAR_DISK_STATUS ) < DEF_DISK_READY ) {
xWriteCH376Cmd( CMD10_SET_FILE_NAME );
xWriteCH376Data( 0 );
s = CH376SendCmdWaitInt( CMD0H_FILE_OPEN );
if ( s == USB_INT_SUCCESS ) {
s = CH376ReadVar8( 0xCF );
if ( s ) {
CH376WriteVar32( 0x4C, CH376ReadVar32( 0x4C ) + ( (UINT16)s << 8 ) );
CH376WriteVar32( 0x50, CH376ReadVar32( 0x50 ) + ( (UINT16)s << 8 ) );
CH376WriteVar32( 0x70, 0 );
}
}
}
}
#endif
xWriteCH376Cmd( CMD10_SET_FILE_NAME );
c = *name;
xWriteCH376Data( c );
while ( c ) {
name ++;
c = *name;
/* Force the file name to expire */
if ( c == DEF_SEPAR_CHAR1 || c == DEF_SEPAR_CHAR2 ) c = 0;
xWriteCH376Data( c );
}
xEndCH376Cmd( );
}
/* Read 32-bit data from CH376 chip and end the command */
UINT32 CH376Read32bitDat( void )
{
UINT8 c0, c1, c2, c3;
c0 = xReadCH376Data( );
c1 = xReadCH376Data( );
c2 = xReadCH376Data( );
c3 = xReadCH376Data( );
xEndCH376Cmd( );
return( c0 | (UINT16)c1 << 8 | (UINT32)c2 << 16 | (UINT32)c3 << 24 );
}
UINT8 CH376ReadVar8( UINT8 var )
{
UINT8 c0;
xWriteCH376Cmd( CMD11_READ_VAR8 );
xWriteCH376Data( var );
c0 = xReadCH376Data( );
xEndCH376Cmd( );
return( c0 );
}
void CH376WriteVar8( UINT8 var, UINT8 dat )
{
xWriteCH376Cmd( CMD20_WRITE_VAR8 );
xWriteCH376Data( var );
xWriteCH376Data( dat );
xEndCH376Cmd( );
}
UINT32 CH376ReadVar32( UINT8 var )
{
xWriteCH376Cmd( CMD14_READ_VAR32 );
xWriteCH376Data( var );
return( CH376Read32bitDat( ) );
}
void CH376WriteVar32( UINT8 var, UINT32 dat )
{
xWriteCH376Cmd( CMD50_WRITE_VAR32 );
xWriteCH376Data( var );
xWriteCH376Data( (UINT8)dat );
xWriteCH376Data( (UINT8)( (UINT16)dat >> 8 ) );
xWriteCH376Data( (UINT8)( dat >> 16 ) );
xWriteCH376Data( (UINT8)( dat >> 24 ) );
xEndCH376Cmd( );
}
void CH376EndDirInfo( void )
{
CH376WriteVar8( 0x0D, 0x00 );
}
UINT32 CH376GetFileSize( void )
{
return( CH376ReadVar32( VAR_FILE_SIZE ) );
}
UINT8 CH376GetDiskStatus( void )
{
return( CH376ReadVar8( VAR_DISK_STATUS ) );
}
UINT8 CH376GetIntStatus( void )
{
UINT8 s;
xWriteCH376Cmd( CMD01_GET_STATUS );
s = xReadCH376Data( );
xEndCH376Cmd( );
return( s );
}
#ifndef NO_DEFAULT_CH376_INT
UINT8 Wait376Interrupt( void )
{
#ifdef DEF_INT_TIMEOUT
#if DEF_INT_TIMEOUT < 1
while ( Query376Interrupt( ) == FALSE );
return( CH376GetIntStatus( ) );
#else
UINT32 i;
for ( i = 0; i < DEF_INT_TIMEOUT; i ++ ) {
if ( Query376Interrupt( ) ) return( CH376GetIntStatus( ) );
}
return( ERR_USB_UNKNOWN );
#endif
#else
UINT32 i;
for ( i = 0; i < 5000000; i ++ ) {
if ( Query376Interrupt( ) ) return( CH376GetIntStatus( ) );
}
return( ERR_USB_UNKNOWN );
#endif
}
#endif
UINT8 CH376SendCmdWaitInt( UINT8 mCmd )
{
xWriteCH376Cmd( mCmd );
xEndCH376Cmd( );
return( Wait376Interrupt( ) );
}
UINT8 CH376SendCmdDatWaitInt( UINT8 mCmd, UINT8 mDat )
{
xWriteCH376Cmd( mCmd );
xWriteCH376Data( mDat );
xEndCH376Cmd( );
return(Wait376Interrupt());
}
UINT8 CH376DiskReqSense( void )
{
UINT8 s;
up_mdelay( 5 );
s = CH376SendCmdWaitInt( CMD0H_DISK_R_SENSE );
up_mdelay( 5 );
return( s );
}
UINT8 CH376DiskConnect( void )
{
if ( Query376Interrupt( ) ) CH376GetIntStatus( );
return( CH376SendCmdWaitInt( CMD0H_DISK_CONNECT ) );
}
UINT8 CH376DiskMount( void )
{
return( CH376SendCmdWaitInt( CMD0H_DISK_MOUNT ) );
}
UINT8 CH376FileOpen( PUINT8 name )
{
CH376SetFileName( name );
#ifndef DEF_IC_V43_U
if ( name[0] == DEF_SEPAR_CHAR1 || name[0] == DEF_SEPAR_CHAR2 ) CH376WriteVar32( VAR_CURRENT_CLUST, 0 );
#endif
return( CH376SendCmdWaitInt( CMD0H_FILE_OPEN ) );
}
UINT8 CH376FileCreate( PUINT8 name )
{
if ( name ) CH376SetFileName( name );
return( CH376SendCmdWaitInt( CMD0H_FILE_CREATE ) );
}
UINT8 CH376DirCreate( PUINT8 name )
{
CH376SetFileName( name );
#ifndef DEF_IC_V43_U
if ( name[0] == DEF_SEPAR_CHAR1 || name[0] == DEF_SEPAR_CHAR2 ) CH376WriteVar32( VAR_CURRENT_CLUST, 0 );
#endif
return( CH376SendCmdWaitInt( CMD0H_DIR_CREATE ) );
}
UINT8 CH376SeparatePath( PUINT8 path )
{
PUINT8 pName;
for ( pName = path; *pName != 0; ++ pName );
while ( *pName != DEF_SEPAR_CHAR1 && *pName != DEF_SEPAR_CHAR2 && pName != path ) pName --;
if ( pName != path ) pName ++;
return( pName - path );
}
UINT8 CH376FileOpenDir( PUINT8 PathName, UINT8 StopName )
{
UINT8 i, s;
s = 0;
i = 1;
while ( 1 ) {
while ( PathName[i] != DEF_SEPAR_CHAR1 && PathName[i] != DEF_SEPAR_CHAR2 && PathName[i] != 0 ) ++ i;
if ( PathName[i] ) i ++;
else i = 0;
s = CH376FileOpen( &PathName[s] );
if ( i && i != StopName ) {
if ( s != ERR_OPEN_DIR ) {
if ( s == USB_INT_SUCCESS ) return( ERR_FOUND_NAME );
else if ( s == ERR_MISS_FILE ) return( ERR_MISS_DIR );
else return( s );
}
s = i;
}
else return( s );
}
}
UINT8 CH376FileOpenPath( PUINT8 PathName )
{
return( CH376FileOpenDir( PathName, 0xFF ) );
}
UINT8 CH376FileCreatePath( PUINT8 PathName )
{
UINT8 s;
UINT8 Name;
Name = CH376SeparatePath( PathName );
if ( Name ) {
s = CH376FileOpenDir( PathName, Name );
if ( s != ERR_OPEN_DIR ) {
if ( s == USB_INT_SUCCESS ) return( ERR_FOUND_NAME );
else if ( s == ERR_MISS_FILE ) return( ERR_MISS_DIR );
else return( s );
}
}
return( CH376FileCreate( &PathName[Name] ) );
}
#ifdef EN_DIR_CREATE
UINT8 CH376DirCreatePath( PUINT8 PathName )
{
UINT8 s;
UINT8 Name;
UINT8 ClustBuf[4];
Name = CH376SeparatePath( PathName );
if ( Name ) {
s = CH376FileOpenDir( PathName, Name );
if ( s != ERR_OPEN_DIR ) {
if ( s == USB_INT_SUCCESS ) return( ERR_FOUND_NAME );
else if ( s == ERR_MISS_FILE ) return( ERR_MISS_DIR );
else return( s );
}
xWriteCH376Cmd( CMD14_READ_VAR32 );
xWriteCH376Data( VAR_START_CLUSTER );
for ( s = 0; s != 4; s ++ ) ClustBuf[ s ] = xReadCH376Data( );
xEndCH376Cmd( );
s = CH376DirCreate( &PathName[Name] );
if ( s != USB_INT_SUCCESS ) return( s );
CH376WriteVar32( VAR_FILE_SIZE, sizeof(FAT_DIR_INFO) * 2 );
s = CH376ByteLocate( sizeof(FAT_DIR_INFO) + STRUCT_OFFSET( FAT_DIR_INFO, DIR_FstClusHI ) );
if ( s != USB_INT_SUCCESS ) return( s );
s = CH376ByteWrite( &ClustBuf[2], 2, NULL );
if ( s != USB_INT_SUCCESS ) return( s );
s = CH376ByteLocate( sizeof(FAT_DIR_INFO) + STRUCT_OFFSET( FAT_DIR_INFO, DIR_FstClusLO ) );
if ( s != USB_INT_SUCCESS ) return( s );
s = CH376ByteWrite( ClustBuf, 2, NULL );
if ( s != USB_INT_SUCCESS ) return( s );
s = CH376ByteLocate( 0 );
if ( s != USB_INT_SUCCESS ) return( s );
CH376WriteVar32( VAR_FILE_SIZE, 0 );
return( s );
}
else {
if ( PathName[0] == DEF_SEPAR_CHAR1 || PathName[0] == DEF_SEPAR_CHAR2 ) return( CH376DirCreate( PathName ) );
else return( ERR_MISS_DIR );
}
}
#endif
UINT8 CH376FileErase( PUINT8 PathName )
{
UINT8 s;
if ( PathName ) {
for ( s = 1; PathName[s] != DEF_SEPAR_CHAR1 && PathName[s] != DEF_SEPAR_CHAR2 && PathName[s] != 0; ++ s );
if ( PathName[s] ) {
s = CH376FileOpenPath( PathName );
if ( s != USB_INT_SUCCESS && s != ERR_OPEN_DIR ) return( s );
}
else CH376SetFileName( PathName );
}
return( CH376SendCmdWaitInt( CMD0H_FILE_ERASE ) );
}
UINT8 CH376FileClose( UINT8 UpdateSz )
{
return( CH376SendCmdDatWaitInt( CMD1H_FILE_CLOSE, UpdateSz ) );
}
UINT8 CH376DirInfoRead( void )
{
return( CH376SendCmdDatWaitInt( CMD1H_DIR_INFO_READ, 0xFF ) );
}
UINT8 CH376DirInfoSave( void )
{
return( CH376SendCmdWaitInt( CMD0H_DIR_INFO_SAVE ) );
}
UINT8 CH376ByteLocate( UINT32 offset )
{
xWriteCH376Cmd( CMD4H_BYTE_LOCATE );
xWriteCH376Data( (UINT8)offset );
xWriteCH376Data( (UINT8)((UINT16)offset>>8) );
xWriteCH376Data( (UINT8)(offset>>16) );
xWriteCH376Data( (UINT8)(offset>>24) );
xEndCH376Cmd( );
return( Wait376Interrupt( ) );
}
UINT8 CH376ByteRead( PUINT8 buf, UINT16 ReqCount, PUINT16 RealCount )
{
UINT8 s;
xWriteCH376Cmd( CMD2H_BYTE_READ );
xWriteCH376Data( (UINT8)ReqCount );
xWriteCH376Data( (UINT8)(ReqCount>>8) );
xEndCH376Cmd( );
if ( RealCount ) *RealCount = 0;
while ( 1 ) {
s = Wait376Interrupt( );
if ( s == USB_INT_DISK_READ ) {
s = CH376ReadBlock( buf );
xWriteCH376Cmd( CMD0H_BYTE_RD_GO );
xEndCH376Cmd( );
buf += s;
if ( RealCount ) *RealCount += s;
}
else return( s );
}
}
UINT8 CH376ByteWrite( PUINT8 buf, UINT16 ReqCount, PUINT16 RealCount )
{
UINT8 s;
xWriteCH376Cmd( CMD2H_BYTE_WRITE );
xWriteCH376Data( (UINT8)ReqCount );
xWriteCH376Data( (UINT8)(ReqCount>>8) );
xEndCH376Cmd( );
if ( RealCount ) *RealCount = 0;
while ( 1 ) {
s = Wait376Interrupt( );
if ( s == USB_INT_DISK_WRITE ) {
s = CH376WriteReqBlock( buf );
xWriteCH376Cmd( CMD0H_BYTE_WR_GO );
xEndCH376Cmd( );
buf += s;
if ( RealCount ) *RealCount += s;
}
else return( s );
}
}
#ifdef EN_DISK_QUERY
UINT8 CH376DiskCapacity( PUINT32 DiskCap )
{
UINT8 s;
s = CH376SendCmdWaitInt( CMD0H_DISK_CAPACITY );
if ( s == USB_INT_SUCCESS ) {
xWriteCH376Cmd( CMD01_RD_USB_DATA0 );
xReadCH376Data( );
*DiskCap = CH376Read32bitDat( );
}
else *DiskCap = 0;
return( s );
}
UINT8 CH376DiskQuery( PUINT32 DiskFre )
{
UINT8 s;
UINT8 c0, c1, c2, c3;
#ifndef DEF_IC_V43_U
xWriteCH376Cmd( CMD01_GET_IC_VER );
if ( xReadCH376Data( ) < 0x43 ) {
if ( CH376ReadVar8( VAR_DISK_STATUS ) >= DEF_DISK_READY ) CH376WriteVar8( VAR_DISK_STATUS, DEF_DISK_MOUNTED );
}
#endif
s = CH376SendCmdWaitInt( CMD0H_DISK_QUERY );
if ( s == USB_INT_SUCCESS ) {
xWriteCH376Cmd( CMD01_RD_USB_DATA0 );
xReadCH376Data( );
xReadCH376Data( );
xReadCH376Data( );
xReadCH376Data( );
xReadCH376Data( );
c0 = xReadCH376Data( );
c1 = xReadCH376Data( );
c2 = xReadCH376Data( );
c3 = xReadCH376Data( );
*DiskFre = c0 | (UINT16)c1 << 8 | (UINT32)c2 << 16 | (UINT32)c3 << 24;
xReadCH376Data( );
xEndCH376Cmd( );
}
else *DiskFre = 0;
return( s );
}
#endif
UINT8 CH376SecLocate( UINT32 offset )
{
xWriteCH376Cmd( CMD4H_SEC_LOCATE );
xWriteCH376Data( (UINT8)offset );
xWriteCH376Data( (UINT8)((UINT16)offset>>8) );
xWriteCH376Data( (UINT8)(offset>>16) );
xWriteCH376Data( 0 );
xEndCH376Cmd( );
return( Wait376Interrupt( ) );
}
#ifdef EN_SECTOR_ACCESS
UINT8 CH376DiskReadSec( PUINT8 buf, UINT32 iLbaStart, UINT8 iSectorCount )
{
UINT8 s, err;
UINT16 mBlockCount;
for ( err = 0; err != 3; ++ err ) {
xWriteCH376Cmd( CMD5H_DISK_READ );
xWriteCH376Data( (UINT8)iLbaStart );
xWriteCH376Data( (UINT8)( (UINT16)iLbaStart >> 8 ) );
xWriteCH376Data( (UINT8)( iLbaStart >> 16 ) );
xWriteCH376Data( (UINT8)( iLbaStart >> 24 ) );
xWriteCH376Data( iSectorCount );
xEndCH376Cmd( );
for ( mBlockCount = iSectorCount * DEF_SECTOR_SIZE / CH376_DAT_BLOCK_LEN; mBlockCount != 0; -- mBlockCount ) {
s = Wait376Interrupt( );
if ( s == USB_INT_DISK_READ ) {
s = CH376ReadBlock( buf );
xWriteCH376Cmd( CMD0H_DISK_RD_GO );
xEndCH376Cmd( );
buf += s;
}
else break;
}
if ( mBlockCount == 0 ) {
s = Wait376Interrupt( );
if ( s == USB_INT_SUCCESS ) return( USB_INT_SUCCESS );
}
if ( s == USB_INT_DISCONNECT ) return( s );
CH376DiskReqSense( );
}
return( s );
}
UINT8 CH376DiskWriteSec( PUINT8 buf, UINT32 iLbaStart, UINT8 iSectorCount )
{
UINT8 s, err;
UINT16 mBlockCount;
for ( err = 0; err != 3; ++ err ) {
xWriteCH376Cmd( CMD5H_DISK_WRITE );
xWriteCH376Data( (UINT8)iLbaStart );
xWriteCH376Data( (UINT8)( (UINT16)iLbaStart >> 8 ) );
xWriteCH376Data( (UINT8)( iLbaStart >> 16 ) );
xWriteCH376Data( (UINT8)( iLbaStart >> 24 ) );
xWriteCH376Data( iSectorCount );
xEndCH376Cmd( );
for ( mBlockCount = iSectorCount * DEF_SECTOR_SIZE / CH376_DAT_BLOCK_LEN; mBlockCount != 0; -- mBlockCount ) {
s = Wait376Interrupt( );
if ( s == USB_INT_DISK_WRITE ) {
CH376WriteHostBlock( buf, CH376_DAT_BLOCK_LEN );
xWriteCH376Cmd( CMD0H_DISK_WR_GO );
xEndCH376Cmd( );
buf += CH376_DAT_BLOCK_LEN;
}
else break;
}
if ( mBlockCount == 0 ) {
s = Wait376Interrupt( );
if ( s == USB_INT_SUCCESS ) return( USB_INT_SUCCESS );
}
if ( s == USB_INT_DISCONNECT ) return( s );
CH376DiskReqSense( );
}
return( s );
}
UINT8 CH376SecRead( PUINT8 buf, UINT8 ReqCount, PUINT8 RealCount )
{
UINT8 s;
UINT8 cnt;
UINT32 StaSec;
#ifndef DEF_IC_V43_U
UINT32 fsz, fofs;
#endif
if ( RealCount ) *RealCount = 0;
do {
#ifndef DEF_IC_V43_U
xWriteCH376Cmd( CMD01_GET_IC_VER );
cnt = xReadCH376Data( );
if ( cnt == 0x41 ) {
xWriteCH376Cmd( CMD14_READ_VAR32 );
xWriteCH376Data( VAR_FILE_SIZE );
xReadCH376Data( );
fsz = xReadCH376Data( );
fsz |= (UINT16)(xReadCH376Data( )) << 8;
cnt = xReadCH376Data( );
fsz |= (UINT32)cnt << 16;
xWriteCH376Cmd( CMD14_READ_VAR32 );
xWriteCH376Data( VAR_CURRENT_OFFSET );
xReadCH376Data( );
fofs = xReadCH376Data( );
fofs |= (UINT16)(xReadCH376Data( )) << 8;
fofs |= (UINT32)(xReadCH376Data( )) << 16;
if ( fsz >= fofs + 510 ) CH376WriteVar8( VAR_FILE_SIZE + 3, 0xFF );
else cnt = 0xFF;
}
else cnt = 0xFF;
#endif
xWriteCH376Cmd( CMD1H_SEC_READ );
xWriteCH376Data( ReqCount );
xEndCH376Cmd( );
s = Wait376Interrupt( );
#ifndef DEF_IC_V43_U
if ( cnt != 0xFF ) CH376WriteVar8( VAR_FILE_SIZE + 3, cnt );
#endif
if ( s != USB_INT_SUCCESS ) return( s );
xWriteCH376Cmd( CMD01_RD_USB_DATA0 );
xReadCH376Data( );
cnt = xReadCH376Data( );
xReadCH376Data( );
xReadCH376Data( );
xReadCH376Data( );
StaSec = CH376Read32bitDat( );
if ( cnt == 0 ) break;
s = CH376DiskReadSec( buf, StaSec, cnt );
if ( s != USB_INT_SUCCESS ) return( s );
buf += cnt * DEF_SECTOR_SIZE;
if ( RealCount ) *RealCount += cnt;
ReqCount -= cnt;
} while ( ReqCount );
return( s );
}
UINT8 CH376SecWrite( PUINT8 buf, UINT8 ReqCount, PUINT8 RealCount )
{
UINT8 s;
UINT8 cnt;
UINT32 StaSec;
if ( RealCount ) *RealCount = 0;
do {
xWriteCH376Cmd( CMD1H_SEC_WRITE );
xWriteCH376Data( ReqCount );
xEndCH376Cmd( );
s = Wait376Interrupt( );
if ( s != USB_INT_SUCCESS ) return( s );
xWriteCH376Cmd( CMD01_RD_USB_DATA0 );
xReadCH376Data( );
cnt = xReadCH376Data( );
xReadCH376Data( );
xReadCH376Data( );
xReadCH376Data( );
StaSec = CH376Read32bitDat( );
if ( cnt == 0 ) break;
s = CH376DiskWriteSec( buf, StaSec, cnt );
if ( s != USB_INT_SUCCESS ) return( s );
buf += cnt * DEF_SECTOR_SIZE;
if ( RealCount ) *RealCount += cnt;
ReqCount -= cnt;
} while ( ReqCount );
return( s );
}
#endif
#ifdef EN_LONG_NAME
UINT8 CH376LongNameWrite( PUINT8 buf, UINT16 ReqCount )
{
UINT8 s;
#ifndef DEF_IC_V43_U
UINT8 c;
c = CH376ReadVar8( VAR_DISK_STATUS );
if ( c == DEF_DISK_OPEN_ROOT ) CH376WriteVar8( VAR_DISK_STATUS, DEF_DISK_OPEN_DIR );
#endif
xWriteCH376Cmd( CMD2H_BYTE_WRITE );
xWriteCH376Data( (UINT8)ReqCount );
xWriteCH376Data( (UINT8)(ReqCount>>8) );
xEndCH376Cmd( );
while ( 1 ) {
s = Wait376Interrupt( );
if ( s == USB_INT_DISK_WRITE ) {
if ( buf ) buf += CH376WriteReqBlock( buf );
else {
xWriteCH376Cmd( CMD01_WR_REQ_DATA );
s = xReadCH376Data( );
while ( s -- ) xWriteCH376Data( 0 );
}
xWriteCH376Cmd( CMD0H_BYTE_WR_GO );
xEndCH376Cmd( );
}
else {
#ifndef DEF_IC_V43_U
if ( c == DEF_DISK_OPEN_ROOT ) CH376WriteVar8( VAR_DISK_STATUS, c );
#endif
return( s );
}
}
}
UINT8 CH376CheckNameSum( PUINT8 DirName )
{
UINT8 NameLen;
UINT8 CheckSum;
CheckSum = 0;
for ( NameLen = 0; NameLen != 11; NameLen ++ ) CheckSum = ( CheckSum & 1 ? 0x80 : 0x00 ) + ( CheckSum >> 1 ) + *DirName++;
return( CheckSum );
}
UINT8 CH376LocateInUpDir( PUINT8 PathName )
{
UINT8 s;
xWriteCH376Cmd( CMD14_READ_VAR32 );
xWriteCH376Data( VAR_FAT_DIR_LBA );
for ( s = 4; s != 8; s ++ ) GlobalBuf[ s ] = xReadCH376Data( );
xEndCH376Cmd( );
s = CH376SeparatePath( PathName );
if ( s ) s = CH376FileOpenDir( PathName, s );
else s = CH376FileOpen( "/" );
if ( s != ERR_OPEN_DIR ) return( s );
*(PUINT32)(&GlobalBuf[0]) = 0;
while ( 1 ) {
s = CH376SecLocate( *(PUINT32)(&GlobalBuf[0]) );
if ( s != USB_INT_SUCCESS ) return( s );
CH376ReadBlock( &GlobalBuf[8] );
if ( *(PUINT32)(&GlobalBuf[8]) == *(PUINT32)(&GlobalBuf[4]) ) return( USB_INT_SUCCESS );
xWriteCH376Cmd( CMD50_WRITE_VAR32 );
xWriteCH376Data( VAR_FAT_DIR_LBA );
for ( s = 8; s != 12; s ++ ) xWriteCH376Data( GlobalBuf[ s ] );
xEndCH376Cmd( );
++ *(PUINT32)(&GlobalBuf[0]);
}
}
UINT8 CH376GetLongName( PUINT8 PathName, PUINT8 LongName )
{
UINT8 s;
UINT16 NameCount;
s = CH376FileOpenPath( PathName );
if ( s != USB_INT_SUCCESS && s != ERR_OPEN_DIR ) return( s );
s = CH376DirInfoRead( );
if ( s != USB_INT_SUCCESS ) return( s );
CH376ReadBlock( GlobalBuf );
CH376EndDirInfo( );
GlobalBuf[32] = CH376CheckNameSum( GlobalBuf );
GlobalBuf[33] = CH376ReadVar8( VAR_FILE_DIR_INDEX );
NameCount = 0;
while ( 1 ) {
if ( GlobalBuf[33] == 0 ) {
s = CH376LocateInUpDir( PathName );
if ( s != USB_INT_SUCCESS ) break;
if ( CH376ReadVar32( VAR_CURRENT_OFFSET ) == 0 ) {
s = ERR_LONG_NAME_ERR;
break;
}
GlobalBuf[33] = DEF_SECTOR_SIZE / sizeof( FAT_DIR_INFO );
}
GlobalBuf[33] --;
s = CH376SendCmdDatWaitInt( CMD1H_DIR_INFO_READ, GlobalBuf[33] );
if ( s != USB_INT_SUCCESS ) break;
CH376ReadBlock( GlobalBuf );
CH376EndDirInfo( );
if ( ( GlobalBuf[11] & ATTR_LONG_NAME_MASK ) != ATTR_LONG_NAME || GlobalBuf[13] != GlobalBuf[32] ) {
s = ERR_LONG_NAME_ERR;
break;
}
for ( s = 1; s < sizeof( FAT_DIR_INFO ); s += 2 ) {
if ( s == 1 + 5 * 2 ) s = 14;
else if ( s == 14 + 6 * 2 ) s = 28;
LongName[ NameCount++ ] = GlobalBuf[ s ];
LongName[ NameCount++ ] = GlobalBuf[ s + 1 ];
if ( GlobalBuf[ s ] == 0 && GlobalBuf[ s + 1 ] == 0 ) break;
if ( NameCount >= LONG_NAME_BUF_LEN ) {
s = ERR_LONG_BUF_OVER;
goto CH376GetLongNameE;
}
}
if ( GlobalBuf[0] & 0x40 ) {
if ( s >= sizeof( FAT_DIR_INFO ) ) *(PUINT16)( &LongName[ NameCount ] ) = 0x0000;
s = USB_INT_SUCCESS;
break;
}
}
CH376GetLongNameE:
CH376FileClose( FALSE );
return( s );
}
UINT8 CH376CreateLongName( PUINT8 PathName, PUINT8 LongName )
{
UINT8 s, i;
UINT8 DirBlockCnt;
UINT16 count;
UINT16 NameCount;
UINT32 NewFileLoc;
for ( count = 0; count < LONG_NAME_BUF_LEN; count += 2 ) if ( *(PUINT16)(&LongName[count]) == 0 ) break;
if ( count == 0 || count >= LONG_NAME_BUF_LEN || count > LONE_NAME_MAX_CHAR ) return( ERR_LONG_NAME_ERR );
DirBlockCnt = count / LONG_NAME_PER_DIR;
i = count - DirBlockCnt * LONG_NAME_PER_DIR;
if ( i ) {
if ( ++ DirBlockCnt * LONG_NAME_PER_DIR > LONG_NAME_BUF_LEN ) return( ERR_LONG_BUF_OVER );
count += 2;
i += 2;
if ( i < LONG_NAME_PER_DIR ) {
while ( i++ < LONG_NAME_PER_DIR ) LongName[count++] = 0xFF;
}
}
s = CH376FileOpenPath( PathName );
if ( s == USB_INT_SUCCESS ) {
s = ERR_NAME_EXIST;
goto CH376CreateLongNameE;
}
if ( s != ERR_MISS_FILE ) return( s );
s = CH376FileCreatePath( PathName );
if ( s != USB_INT_SUCCESS ) return( s );
i = CH376ReadVar8( VAR_FILE_DIR_INDEX );
s = CH376LocateInUpDir( PathName );
if ( s != USB_INT_SUCCESS ) goto CH376CreateLongNameE;
NewFileLoc = CH376ReadVar32( VAR_CURRENT_OFFSET ) + i * sizeof(FAT_DIR_INFO);
s = CH376ByteLocate( NewFileLoc );
if ( s != USB_INT_SUCCESS ) goto CH376CreateLongNameE;
s = CH376ByteRead( &GlobalBuf[ sizeof(FAT_DIR_INFO) ], sizeof(FAT_DIR_INFO), NULL );
if ( s != USB_INT_SUCCESS ) goto CH376CreateLongNameE;
for ( i = DirBlockCnt; i != 0; -- i ) {
s = CH376ByteRead( GlobalBuf, sizeof(FAT_DIR_INFO), &count );
if ( s != USB_INT_SUCCESS ) goto CH376CreateLongNameE;
if ( count == 0 ) break;
if ( GlobalBuf[0] && GlobalBuf[0] != 0xE5 ) {
s = CH376ByteLocate( NewFileLoc );
if ( s != USB_INT_SUCCESS ) goto CH376CreateLongNameE;
GlobalBuf[ 0 ] = 0xE5;
for ( s = 1; s != sizeof(FAT_DIR_INFO); s ++ ) GlobalBuf[ s ] = GlobalBuf[ sizeof(FAT_DIR_INFO) + s ];
s = CH376LongNameWrite( GlobalBuf, sizeof(FAT_DIR_INFO) );
if ( s != USB_INT_SUCCESS ) goto CH376CreateLongNameE;
do {
s = CH376ByteRead( GlobalBuf, sizeof(FAT_DIR_INFO), &count );
if ( s != USB_INT_SUCCESS ) goto CH376CreateLongNameE;
} while ( count && GlobalBuf[0] );
NewFileLoc = CH376ReadVar32( VAR_CURRENT_OFFSET );
i = DirBlockCnt + 1;
if ( count == 0 ) break;
NewFileLoc -= sizeof(FAT_DIR_INFO);
}
}
if ( i ) {
s = CH376ReadVar8( VAR_SEC_PER_CLUS );
if ( s == 128 ) {
s = ERR_FDT_OVER;
goto CH376CreateLongNameE;
}
count = s * DEF_SECTOR_SIZE;
if ( count < i * sizeof(FAT_DIR_INFO) ) count <<= 1;
s = CH376LongNameWrite( NULL, count );
if ( s != USB_INT_SUCCESS ) goto CH376CreateLongNameE;
}
s = CH376ByteLocate( NewFileLoc );
if ( s != USB_INT_SUCCESS ) goto CH376CreateLongNameE;
GlobalBuf[11] = ATTR_LONG_NAME;
GlobalBuf[12] = 0x00;
GlobalBuf[13] = CH376CheckNameSum( &GlobalBuf[ sizeof(FAT_DIR_INFO) ] );
GlobalBuf[26] = 0x00;
GlobalBuf[27] = 0x00;
for ( s = 0; DirBlockCnt != 0; ) {
GlobalBuf[0] = s ? DirBlockCnt : DirBlockCnt | 0x40;
DirBlockCnt --;
NameCount = DirBlockCnt * LONG_NAME_PER_DIR;
for ( s = 1; s < sizeof( FAT_DIR_INFO ); s += 2 ) {
if ( s == 1 + 5 * 2 ) s = 14;
else if ( s == 14 + 6 * 2 ) s = 28;
GlobalBuf[ s ] = LongName[ NameCount++ ];
GlobalBuf[ s + 1 ] = LongName[ NameCount++ ];
}
s = CH376LongNameWrite( GlobalBuf, sizeof(FAT_DIR_INFO) );
if ( s != USB_INT_SUCCESS ) goto CH376CreateLongNameE;
}
s = CH376LongNameWrite( &GlobalBuf[ sizeof(FAT_DIR_INFO) ], sizeof(FAT_DIR_INFO) );
CH376CreateLongNameE:
CH376FileClose( FALSE );
return( s );
}
#endif

124
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ch376.h Normal file
View File

@ -0,0 +1,124 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file k210_ch376.h
* @brief xidatong-riscv64 k210_ch376.h
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.10.10
* */
#ifndef __CH376_FS_H__
#define __CH376_FS_H__
#include "ch376inc.h"
#include <nuttx/config.h>
#include <sys/ioctl.h>
#include <nuttx/time.h>
#include <nuttx/fs/fs.h>
#include <nuttx/fs/ioctl.h>
#include <nuttx/arch.h>
#include <stdint.h>
#include <stdio.h>
#include <unistd.h>
#include <stdbool.h>
#include <debug.h>
#include <assert.h>
#include <fcntl.h>
#include <nuttx/ioexpander/gpio.h>
#include "k210_uart_16550.h"
#define ERR_USB_UNKNOWN 0xFA
void xEndCH376Cmd( void );
void xWriteCH376Cmd( UINT8 mCmd );
void xWriteCH376Data( UINT8 mData );
UINT8 xReadCH376Data( void );
UINT8 Query376Interrupt( void );
UINT8 mInitCH376Host( void );
#define STRUCT_OFFSET( s, m ) ( (UINT8)( & ((s *)0) -> m ) )
#ifdef EN_LONG_NAME
#ifndef LONG_NAME_BUF_LEN
#define LONG_NAME_BUF_LEN ( LONG_NAME_PER_DIR * 20 )
#endif
#endif
UINT8 CH376ReadBlock( PUINT8 buf );
UINT8 CH376WriteReqBlock( PUINT8 buf );
void CH376WriteHostBlock( PUINT8 buf, UINT8 len );
void CH376WriteOfsBlock( PUINT8 buf, UINT8 ofs, UINT8 len );
void CH376SetFileName( PUINT8 name );
UINT32 CH376Read32bitDat( void );
UINT8 CH376ReadVar8( UINT8 var );
void CH376WriteVar8( UINT8 var, UINT8 dat );
UINT32 CH376ReadVar32( UINT8 var );
void CH376WriteVar32( UINT8 var, UINT32 dat );
void CH376EndDirInfo( void );
UINT32 CH376GetFileSize( void );
UINT8 CH376GetDiskStatus( void );
UINT8 CH376GetIntStatus( void );
#ifndef NO_DEFAULT_CH376_INT
UINT8 Wait376Interrupt( void );
#endif
UINT8 CH376SendCmdWaitInt( UINT8 mCmd );
UINT8 CH376SendCmdDatWaitInt( UINT8 mCmd, UINT8 mDat );
UINT8 CH376DiskReqSense( void );
UINT8 CH376DiskConnect( void );
UINT8 CH376DiskMount( void );
UINT8 CH376FileOpen( PUINT8 name );
UINT8 CH376FileCreate( PUINT8 name );
UINT8 CH376DirCreate( PUINT8 name );
UINT8 CH376SeparatePath( PUINT8 path );
UINT8 CH376FileOpenDir( PUINT8 PathName, UINT8 StopName );
UINT8 CH376FileOpenPath( PUINT8 PathName );
UINT8 CH376FileCreatePath( PUINT8 PathName );
#ifdef EN_DIR_CREATE
UINT8 CH376DirCreatePath( PUINT8 PathName );
#endif
UINT8 CH376FileErase( PUINT8 PathName );
UINT8 CH376FileClose( UINT8 UpdateSz );
UINT8 CH376DirInfoRead( void );
UINT8 CH376DirInfoSave( void );
UINT8 CH376ByteLocate( UINT32 offset );
UINT8 CH376ByteRead( PUINT8 buf, UINT16 ReqCount, PUINT16 RealCount );
UINT8 CH376ByteWrite( PUINT8 buf, UINT16 ReqCount, PUINT16 RealCount );
#ifdef EN_DISK_QUERY
UINT8 CH376DiskCapacity( PUINT32 DiskCap );
UINT8 CH376DiskQuery( PUINT32 DiskFre );
#endif
UINT8 CH376SecLocate( UINT32 offset );
#ifdef EN_SECTOR_ACCESS
UINT8 CH376DiskReadSec( PUINT8 buf, UINT32 iLbaStart, UINT8 iSectorCount );
UINT8 CH376DiskWriteSec( PUINT8 buf, UINT32 iLbaStart, UINT8 iSectorCount );
UINT8 CH376SecRead( PUINT8 buf, UINT8 ReqCount, PUINT8 RealCount );
UINT8 CH376SecWrite( PUINT8 buf, UINT8 ReqCount, PUINT8 RealCount );
#endif
#ifdef EN_LONG_NAME
UINT8 CH376LongNameWrite( PUINT8 buf, UINT16 ReqCount );
UINT8 CH376CheckNameSum( PUINT8 DirName );
UINT8 CH376LocateInUpDir( PUINT8 PathName );
UINT8 CH376GetLongName( PUINT8 PathName, PUINT8 LongName );
UINT8 CH376CreateLongName( PUINT8 PathName, PUINT8 LongName );
#endif
#endif

34
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_ch438.h
View File

@ -53,6 +53,7 @@
#include <stdlib.h>
#include <fcntl.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "riscv_internal.h"
@ -289,39 +290,6 @@
#define Fpclk 1843200 /* Define the internal clock frequency*/
/* Define CH438 PIN NUM */
#define CH438_ALE_PIN 24
#define CH438_NWR_PIN 25
#define CH438_NRD_PIN 26
#define CH438_D0_PIN 27
#define CH438_D1_PIN 28
#define CH438_D2_PIN 29
#define CH438_D3_PIN 30
#define CH438_D4_PIN 31
#define CH438_D5_PIN 32
#define CH438_D6_PIN 33
#define CH438_D7_PIN 34
#define CH438_INT_PIN 35
/* Define ch438 FPIOA NUMBER */
#define FPIOA_CH438_ALE 11
#define FPIOA_CH438_NWR 12
#define FPIOA_CH438_NRD 13
#define FPIOA_CH438_D0 14
#define FPIOA_CH438_D1 15
#define FPIOA_CH438_D2 16
#define FPIOA_CH438_D3 17
#define FPIOA_CH438_D4 18
#define FPIOA_CH438_D5 29
#define FPIOA_CH438_D6 20
#define FPIOA_CH438_D7 31
#define FPIOA_CH438_INT 22
/* ch438 debug */
#ifdef CONFIG_DEBUG_CH438_ERROR
# define ch438err _err

9
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_gpio.c
View File

@ -34,7 +34,7 @@
#include <arch/irq.h>
#include <nuttx/ioexpander/gpio.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "k210_fpioa.h"
@ -48,13 +48,7 @@
/* Pin 1 and 2 are used for this example as GPIO outputs. */
#define GPIO_E220_M0 44
#define GPIO_E220_M1 45
#define GPIO_E18_MODE 46
#define FPIOA_E220_M0 1
#define FPIOA_E220_M1 2
#define FPIOA_E18_MODE 3
/****************************************************************************
* Private Types
@ -177,7 +171,6 @@ int k210_gpio_init(void)
(K210_IO_FUNC_GPIOHS0 + g_fpioa[i]) | K210_IOFLAG_GPIOHS);
k210_gpiohs_set_direction(g_fpioa[i], GPIO_DM_OUTPUT);
k210_gpiohs_set_value(g_fpioa[i], false);
pincount++;
}
#endif

65
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_lcd.c
View File

@ -28,24 +28,24 @@
#include "nuttx/arch.h"
#include "nuttx/lcd/lt768.h"
#include "nuttx/lcd/lt768_lib.h"
#include "nuttx/lcd/k210_lcd.h"
#include "nuttx/lcd/if_port.h"
#include <nuttx/board.h>
#include <arch/board/board.h>
#ifdef CONFIG_LCD_LCDDRV_SPIIF
#include "nuttx/lcd/lcddrv_spiif.h"
#endif
#define NCS_H() k210_gpiohs_set_value(FPIOA_LCD_NCS, GPIO_PV_HIGH); up_udelay(20)
#define NCS_L() k210_gpiohs_set_value(FPIOA_LCD_NCS, GPIO_PV_LOW); up_udelay(20)
#define CLK_H() k210_gpiohs_set_value(FPIOA_LCD_SCLK, GPIO_PV_HIGH); up_udelay(20)
#define CLK_L() k210_gpiohs_set_value(FPIOA_LCD_SCLK, GPIO_PV_LOW); up_udelay(20)
#define MOSI_H() k210_gpiohs_set_value(FPIOA_LCD_MOSI, GPIO_PV_HIGH)
#define MOSI_L() k210_gpiohs_set_value(FPIOA_LCD_MOSI, GPIO_PV_LOW)
/****************************************************************************
* Public Functions
****************************************************************************/
void test_delay(void)
{
volatile uint32_t i = 0;
for (i = 0; i < 200; ++i)
{
__asm("NOP"); /* delay */
}
}
void lcd_pin_init(void)
{
k210_fpioa_config(BSP_LCD_NRST, HS_GPIO(FPIOA_LCD_NRST) | K210_IOFLAG_GPIOHS);
@ -60,9 +60,9 @@ void lcd_pin_init(void)
k210_gpiohs_set_direction(FPIOA_LCD_MOSI, GPIO_DM_OUTPUT);
k210_gpiohs_set_direction(FPIOA_LCD_NCS, GPIO_DM_OUTPUT);
lcd_set_pin(FPIOA_LCD_SCLK, GPIO_PV_HIGH);
lcd_set_pin(FPIOA_LCD_NCS, GPIO_PV_HIGH);
lcd_set_pin(FPIOA_LCD_NRST, GPIO_PV_HIGH);
k210_gpiohs_set_value(FPIOA_LCD_SCLK, GPIO_PV_HIGH);
k210_gpiohs_set_value(FPIOA_LCD_NCS, GPIO_PV_HIGH);
k210_gpiohs_set_value(FPIOA_LCD_NRST, GPIO_PV_HIGH);
}
void lcd_backlight_init(bool enable)
@ -86,74 +86,74 @@ uint8_t lcd_transfer_byte(uint8_t dat)
for(i = 0; i < 8; i++)
{
CLK_H;
CLK_H();
// MOSI during falling edge
if((dat << i) & 0x80)
{
MOSI_H;
MOSI_H();
}
else
{
MOSI_L;
MOSI_L();
}
CLK_L;
CLK_L();
// MISO during rising edge
rx_data <<= 1;
if(lcd_get_pin(FPIOA_LCD_MISO))
if(k210_gpiohs_get_value(FPIOA_LCD_MISO))
rx_data ++;
}
CLK_H;
CLK_H();
return rx_data;
}
void LCD_CmdWrite(uint8_t cmd)
{
NCS_L;
NCS_L();
lcd_transfer_byte(0x00);
lcd_transfer_byte(cmd);
NCS_H;
NCS_H();
}
void LCD_DataWrite(uint8_t data)
{
NCS_L;
NCS_L();
lcd_transfer_byte(0x80);
lcd_transfer_byte(data);
NCS_H;
NCS_H();
}
void LCD_DataWrite_Pixel(uint8_t data)
{
NCS_L;
NCS_L();
lcd_transfer_byte(0x80);
lcd_transfer_byte(data);
NCS_H;
NCS_L;
NCS_H();
NCS_L();
lcd_transfer_byte(0x80);
lcd_transfer_byte(data >> 8);
NCS_H;
NCS_H();
}
uint8_t LCD_StatusRead(void)
{
uint8_t temp = 0;
NCS_L;
NCS_L();
lcd_transfer_byte(0x40);
temp = lcd_transfer_byte(0xff);
NCS_H;
NCS_H();
return temp;
}
uint8_t LCD_DataRead(void)
{
uint8_t temp = 0;
NCS_L;
NCS_L();
lcd_transfer_byte(0xc0);
temp = lcd_transfer_byte(0xff);
NCS_H;
NCS_H();
return temp;
}
@ -195,11 +195,12 @@ void lcd_drv_init(void)
*
****************************************************************************/
void board_lcd_initialize(void)
int board_lcd_initialize(void)
{
/* Configure the LCD backlight (and turn the backlight off) */
lcd_backlight_init(true);
lcd_drv_init();
return 0;
}
/****************************************************************************

1
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_leds.c
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@ -25,7 +25,6 @@
#include <nuttx/config.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "k210_fpioa.h"

409
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_touch.c Normal file
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@ -0,0 +1,409 @@
/*
* Copyright (c) 2022 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file k210_touch.c
* @brief gt911 touch driver
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.10.25
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include "k210_touch.h"
/****************************************************************************
* Name: IIC_Init
* Description: i2c pin mode configure
* input: None
* output: None
* return:none
****************************************************************************/
void IIC_Init(void)
{
/* config simluate IIC bus */
k210_fpioa_config(BSP_IIC_SDA, GT911_FUNC_GPIO(FPIOA_IIC_SDA));
k210_fpioa_config(BSP_IIC_SCL, GT911_FUNC_GPIO(FPIOA_IIC_SCL));
k210_gpiohs_set_direction(FPIOA_IIC_SDA, GPIO_DM_OUTPUT);
k210_gpiohs_set_direction(FPIOA_IIC_SCL, GPIO_DM_OUTPUT);
}
/****************************************************************************
* Name: SDA_IN
* Description: set sda input mode
* input: None
* output: None
* return:none
****************************************************************************/
void SDA_IN(void)
{
k210_gpiohs_set_direction(FPIOA_IIC_SDA, GPIO_DM_INPUT_PULL_UP);
}
/****************************************************************************
* Name: SDA_OUT
* Description: set sda output mode
* input: None
* output: None
* return:none
****************************************************************************/
void SDA_OUT(void)
{
k210_gpiohs_set_direction(FPIOA_IIC_SDA, GPIO_DM_OUTPUT);
}
/****************************************************************************
* Name: READ_SDA
* Description: read sda value
* input: None
* output: None
* return: sda pin value
****************************************************************************/
uint8_t READ_SDA(void)
{
return k210_gpiohs_get_value(FPIOA_IIC_SDA);
}
/****************************************************************************
* Name: IIC_SCL
* Description: set the value of scl
* input: val:the value to be set
* output: None
* return: None
****************************************************************************/
void IIC_SCL(uint8_t val)
{
if (val)
k210_gpiohs_set_value(FPIOA_IIC_SCL,GPIO_PV_HIGH);
else
{
k210_gpiohs_set_value(FPIOA_IIC_SCL,GPIO_PV_LOW);
}
}
/****************************************************************************
* Name: IIC_SDA
* Description: set the value of sda
* input: val:the value to be set
* output: None
* return: None
****************************************************************************/
void IIC_SDA(uint8_t val)
{
if (val)
k210_gpiohs_set_value(FPIOA_IIC_SDA,GPIO_PV_HIGH);
else
{
k210_gpiohs_set_value(FPIOA_IIC_SDA,GPIO_PV_LOW);
}
}
/****************************************************************************
* Name: IIC_Start
* Description: Generate i2c start signal
* input: None
* output: None
* return: None
****************************************************************************/
void IIC_Start(void)
{
SDA_OUT();
IIC_SDA(1);
IIC_SCL(1);
up_mdelay(30);
IIC_SDA(0);
up_mdelay(2);
IIC_SCL(0);
}
/****************************************************************************
* Name: IIC_Start
* Description: Generate i2c stop signal
* input: None
* output: None
* return: None
****************************************************************************/
void IIC_Stop(void)
{
SDA_OUT();
IIC_SCL(1);
up_mdelay(30);
IIC_SDA(0);
up_mdelay(2);
IIC_SDA(1);
}
/*******************************************************************************************
* Name: IIC_Wait_Ack
* Description: Wait for the reply signal to arrive
* input: None
* output: None
* return: Return value: 1:failed to receive response,0:the received response is successful.
********************************************************************************************/
uint8_t IIC_Wait_Ack(void)
{
uint16_t ucErrTime=0;
SDA_IN();
IIC_SDA(1);
IIC_SCL(1);
up_mdelay(2);
while(READ_SDA())
{
ucErrTime++;
if(ucErrTime>2500)
{
IIC_Stop();
return 1;
}
up_mdelay(2);
}
IIC_SCL(0);
return 0;
}
/****************************************************************************
* Name: IIC_Ack
* Description: generate ack response
* input: None
* output: None
* return: None
****************************************************************************/
void IIC_Ack(void)
{
IIC_SCL(0);
SDA_OUT();
up_mdelay(2);
IIC_SDA(0);
up_mdelay(2);
IIC_SCL(1);
up_mdelay(2);
IIC_SCL(0);
}
/****************************************************************************
* Name: IIC_NAck
* Description: No ACK response is generated
* input: None
* output: None
* return: None
****************************************************************************/
void IIC_NAck(void)
{
IIC_SCL(0);
SDA_OUT();
up_mdelay(2);
IIC_SDA(1);
up_mdelay(2);
IIC_SCL(1);
up_mdelay(2);
IIC_SCL(0);
}
/****************************************************************************
* Name: IIC_Send_Byte
* Description: IIC sends a byte,Return whether the slave has a response
* input: None
* output: None
* return: 1:there is a response,0:no response
****************************************************************************/
void IIC_Send_Byte(uint8_t txd)
{
uint8_t t;
SDA_OUT();
IIC_SCL(0);
up_mdelay(2);
for(t=0;t<8;t++)
{
IIC_SDA((txd&0x80)>>7);
txd<<=1;
IIC_SCL(1);
up_mdelay(2);
IIC_SCL(0);
up_mdelay(2);
}
}
/****************************************************************************
* Name: IIC_Read_Byte
* Description: Read 1 byte, when ack=1, send ACK, when ack=0, send nACK
* input: None
* output: None
* return: Returns one byte of data read
****************************************************************************/
uint8_t IIC_Read_Byte(uint8_t ack)
{
uint8_t i,receive=0;
SDA_IN();
up_mdelay(30);
for(i=0;i<8;i++ )
{
IIC_SCL(0);
up_mdelay(2);
IIC_SCL(1);
up_udelay(1);
receive<<=1;
if(READ_SDA())receive++;
up_udelay(1);
}
if (!ack)
IIC_NAck();
else
IIC_Ack();
return receive;
}
/***********************************************************************************
* Name: GT911_WR_Reg
* Description: Write data to GT911 once
* input: reg: start register address,buf: data cache area,len: write data length
* output: None
* return: Return value: 0, success; 1, failure.
***********************************************************************************/
static uint8_t GT911_WR_Reg(uint16_t reg,uint8_t *buf,uint8_t len)
{
uint8_t i;
uint8_t ret=0;
IIC_Start();
IIC_Send_Byte(CT_CMD_WR);
IIC_Wait_Ack();
IIC_Send_Byte(reg>>8);
IIC_Wait_Ack();
IIC_Send_Byte(reg&0XFF);
IIC_Wait_Ack();
for(i=0;i<len;i++)
{
IIC_Send_Byte(buf[i]);
ret=IIC_Wait_Ack();
if(ret)break;
}
IIC_Stop();
return ret;
}
/***********************************************************************************
* Name: GT911_RD_Reg
* Description: Read data from GT911 once
* input: reg: start register address,buf: data cache area,len: read data length
* output: None
* return: None
***********************************************************************************/
static void GT911_RD_Reg(uint16_t reg,uint8_t *buf,uint8_t len)
{
uint8_t i;
IIC_Start();
IIC_Send_Byte(CT_CMD_WR);
IIC_Wait_Ack();
IIC_Send_Byte(reg>>8);
IIC_Wait_Ack();
IIC_Send_Byte(reg&0XFF);
IIC_Wait_Ack();
IIC_Stop();
IIC_Start();
IIC_Send_Byte(CT_CMD_RD);
IIC_Wait_Ack();
for(i=0;i<len;i++)
{
buf[i]=IIC_Read_Byte(i==(len-1)?0:1);
}
IIC_Stop();
}
/***********************************************************************************
* Name: GT911_ReadFirmwareVersion
* Description: Get firmware version number
* input: None
* output: None
* return: version number
***********************************************************************************/
static uint16_t GT911_ReadFirmwareVersion(void)
{
uint8_t buf[2];
GT911_RD_Reg(GT911_FIRMWARE_VERSION_REG, buf, 2);
return ((uint16_t)buf[1] << 8) + buf[0];
}
/***********************************************************************************
* Name: GT911_Scan
* Description: point:structure to store coordinates
* input: None
* output: None
* return: Returns true for touch, false for no touch
***********************************************************************************/
bool GT911_Scan(POINT* point)
{
GT911_Dev Dev_Now;
uint8_t Clearbuf = 0;
uint8_t buf[41];
GT911_RD_Reg(GT911_READ_XY_REG, buf, 1);
if ((buf[0]&0x80) == 0x00)
{
GT911_WR_Reg(GT911_READ_XY_REG, (uint8_t *)&Clearbuf, 1);
return false;
}
else
{
Dev_Now.TouchCount = buf[0] & 0x0f;
if((Dev_Now.TouchCount > 5) || (Dev_Now.TouchCount == 0) )
{
GT911_WR_Reg(GT911_READ_XY_REG, (uint8_t *)&Clearbuf, 1);
return false;
}
GT911_RD_Reg(GT911_READ_XY_REG + 1, &buf[1], Dev_Now.TouchCount*8);
GT911_WR_Reg(GT911_READ_XY_REG, (uint8_t *)&Clearbuf, 1);
for (uint8_t i = 0;i < Dev_Now.TouchCount; i++)
{
Dev_Now.Touchkeytrackid[i] = buf[1+(8*i)];
Dev_Now.X[i] = ((uint16_t)buf[3+(8*i)] << 8) + buf[2+(8*i)];
Dev_Now.Y[i] = ((uint16_t)buf[5+(8*i)] << 8) + buf[4+(8*i)];
Dev_Now.S[i] = ((uint16_t)buf[7+(8*i)] << 8) + buf[6+(8*i)];
if(Dev_Now.Y[i] < 20) Dev_Now.Y[i] = 20;
if(Dev_Now.Y[i] > GT911_MAX_HEIGHT -20) Dev_Now.Y[i]=GT911_MAX_HEIGHT - 20;
if(Dev_Now.X[i] < 20) Dev_Now.X[i] = 20;
if(Dev_Now.X[i] > GT911_MAX_WIDTH-20) Dev_Now.X[i] = GT911_MAX_WIDTH - 20;
point->X = Dev_Now.X[i];
point->Y = Dev_Now.Y[i];
}
}
return true;
}
/***********************************************************************************
* Name: GT911_test
* Description: gt911 test code
* input: None
* output: None
* return: Returns true for touch, false for no touch
***********************************************************************************/
void GT911_test(void)
{
uint16_t res;
POINT point = {0, 0};
IIC_Init();
res = GT911_ReadFirmwareVersion();
printf("FirmwareVersion:%2x\n",res);
while(1)
{
if(GT911_Scan(&point))
{
printf("Now touch point:(%d,%d)\n",point.X,point.Y);
}
}
}

88
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_touch.h Normal file
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@ -0,0 +1,88 @@
/*
* Copyright (c) 2022 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file k210_touch.h
* @brief gt911 touch driver
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.10.25
*/
#ifndef _K210_TOUCH_H_
#define _K210_TOUCH_H_
#include <nuttx/config.h>
#include <nuttx/kmalloc.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include <nuttx/time.h>
#include <errno.h>
#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <debug.h>
#include <assert.h>
#include <nuttx/time.h>
#include <nuttx/fs/fs.h>
#include "k210_config.h"
#include "k210_fpioa.h"
#include "k210_gpiohs.h"
#include "nuttx/arch.h"
#include "k210_gpio_common.h"
#define GT911_FUNC_GPIO(n) ((K210_IO_FUNC_GPIOHS0 + n) | K210_IOFLAG_GPIOHS)
#define GT911_MAX_WIDTH (uint16_t)800
#define GT911_MAX_HEIGHT (uint16_t)480
#define CT_CMD_WR (uint8_t)0XBA
#define CT_CMD_RD (uint8_t)0XBB
#define CT_MAX_TOUCH (uint8_t)5
#define GT911_COMMAND_REG (uint16_t)0x8040
#define GT911_CONFIG_REG (uint16_t)0x8047
#define GT911_PRODUCT_ID_REG (uint16_t)0x8140
#define GT911_FIRMWARE_VERSION_REG (uint16_t)0x8144
#define GT911_READ_XY_REG (uint16_t)0x814E
typedef struct
{
uint8_t TouchCount;
uint8_t Touchkeytrackid[CT_MAX_TOUCH];
uint16_t X[CT_MAX_TOUCH];
uint16_t Y[CT_MAX_TOUCH];
uint16_t S[CT_MAX_TOUCH];
}GT911_Dev;
typedef struct
{
uint16_t X;
uint16_t Y;
}POINT;
void IIC_Init(void);
void SDA_IN(void);
void SDA_OUT(void);
uint8_t READ_SDA(void);
void IIC_SCL(uint8_t val);
void IIC_SDA(uint8_t val);
void IIC_Start(void);
void IIC_Stop(void);
uint8_t IIC_Wait_Ack(void);
void IIC_Ack(void);
void IIC_NAck(void);
void IIC_Send_Byte(uint8_t txd);
uint8_t IIC_Read_Byte(uint8_t ack);
bool GT911_Scan(POINT* point);
void GT911_test(void);
#endif

840
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/k210_w5500.c Normal file
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@ -0,0 +1,840 @@
/*
* Copyright (c) 2022 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file k210_w5500.c
* @brief w5500 driver based on simulated SPI
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-9-14
*/
#include "nuttx/arch.h"
#include "k210_w5500.h"
#include "k210_gpio_common.h"
/****************************************************************************
* Private Data
****************************************************************************/
w5500_param_t w5500_param;
static uint8_t rx_buf[256];
static uint8_t tx_buf[256];
static uint8_t config_ip_addr[] = {10, 0, 30, 50};
static uint8_t config_ip_mask[] = {255, 255, 255, 0};
static uint8_t config_gw_addr[] = {10, 0, 30, 1};
static uint8_t config_mac_addr[] = {0x0C, 0x29, 0xAB, 0x7C, 0x00, 0x01};
static uint8_t config_dst_ip[] = {10, 0, 30, 57};
static uint16_t config_local_port = 5000;
static uint16_t config_dst_port = 6000;
static uint8_t config_mode = SOCK_TCP_CLI;
/****************************************************************************
* Name: spi_read_byte
* Description: Read one byte spi data returned
* input: None
* output: None
* return:Read register data
****************************************************************************/
static uint8_t spi_read_byte(void)
{
uint8_t i, dat = 0;
SCLK_L();
for(i = 0; i < 8; i++)
{
SCLK_H();
dat <<= 1;
dat |= k210_gpiohs_get_value(FPIOA_ENET_MISO);
up_udelay(1);
SCLK_L();
}
return dat;
}
/****************************************************************************
* Name: spi_write_byte
* Description: send 1 byte to spi
* input: data
* output: None
* return: None
****************************************************************************/
static void spi_write_byte(uint8_t dat)
{
uint8_t i;
for(i = 0; i < 8; i++)
{
SCLK_L();
if((dat << i) & 0x80)
{
MOSI_H();
}
else
{
MOSI_L();
}
SCLK_H();
}
SCLK_L();
}
/****************************************************************************
* Name: spi_write_short
* Description: send 2 bytes to spi
* input: data
* output: None
* return: None
****************************************************************************/
static void spi_write_short(uint16_t dat)
{
spi_write_byte((uint8_t)(dat / 256));
spi_write_byte(dat);
}
/****************************************************************************
* Name: w5500_write_byte
*Description: Write 1 byte data to the specified address register through SPI
*Input: reg: 16 bit register address, dat: data to be written
* output: None
* return: None
****************************************************************************/
static void w5500_write_byte(uint16_t reg, uint8_t dat)
{
NCS_L();
spi_write_short(reg);
spi_write_byte(FDM1 | RWB_WRITE | COMMON_R);
spi_write_byte(dat);
NCS_H();
}
/****************************************************************************
* Name: w5500_write_short
* Description: Write 2 bytes data to the specified address register through SPI
* Input: reg: 16 bit register address, dat: data to be written
* output: None
* return: None
****************************************************************************/
static void w5500_write_short(uint16_t reg, uint16_t dat)
{
NCS_L();
spi_write_short(reg);
spi_write_byte(FDM2 | RWB_WRITE | COMMON_R);
spi_write_short(dat);
NCS_H();
}
/****************************************************************************
* Name: w5500_write_bytes
* Description: Write n bytes data to the specified address register through SPI
* Input: reg: 16 bit register address, dat: data to be written,size:Length of data to be written
* output: None
* return: None
****************************************************************************/
static void w5500_write_bytes(uint16_t reg, uint8_t *dat, uint16_t size)
{
uint16_t i;
NCS_L();
spi_write_short(reg);
spi_write_byte(VDM | RWB_WRITE | COMMON_R);
for(i = 0; i < size; i++)
{
spi_write_byte(*dat++);
}
NCS_H();
}
/****************************************************************************
* Name: w5500_write_sock_byte
* Description: Write 1 byte data to the specified port register through SPI
* Input: sock: port number, reg: 16 bit register address, dat: data to be written
* Output: None
* return: None
****************************************************************************/
void w5500_write_sock_byte(socket_t sock, uint16_t reg, uint8_t dat)
{
NCS_L();
spi_write_short(reg);
spi_write_byte(FDM1 | RWB_WRITE | (sock * 0x20 + 0x08));
spi_write_byte(dat);
NCS_H();
}
/****************************************************************************
* Name: w5500_write_sock_short
* Description: Write 2 bytes data to the specified port register through SPI
* Input: sock: port number, reg: 16 bit register address, dat: data to be written
* Output: None
* return: None
****************************************************************************/
void w5500_write_sock_short(socket_t sock, uint16_t reg, uint16_t dat)
{
NCS_L();
spi_write_short(reg);
spi_write_byte(FDM2 | RWB_WRITE | (sock * 0x20 + 0x08));
spi_write_short(dat);
NCS_H();
}
/****************************************************************************
* Name: w5500_write_sock_long
* Description: Write 4 bytes data to the specified port register through SPI
* Input: sock: port number, reg: 16 bit register address, dat: 4 byte buffer pointers to be written
* Output: None
* return: None
****************************************************************************/
void w5500_write_sock_long(socket_t sock, uint16_t reg, uint8_t *dat)
{
NCS_L();
spi_write_short(reg);
spi_write_byte(FDM4 | RWB_WRITE | (sock * 0x20 + 0x08));
spi_write_byte(*dat++);
spi_write_byte(*dat++);
spi_write_byte(*dat++);
spi_write_byte(*dat++);
NCS_H();
}
/*******************************************************************************
*Function name: w5500_read_byte
*Description: Read 1 byte data of W5500 specified address register
*Input: reg: 16 bit register address
*Output: None
*Return : 1 byte data read from the register
*******************************************************************************/
uint8_t w5500_read_byte(uint16_t reg)
{
uint8_t val;
NCS_L();
spi_write_short(reg);
spi_write_byte(FDM1 | RWB_READ | COMMON_R);
val = spi_read_byte();
NCS_H();
return val;
}
/*******************************************************************************
*Function name: w5500_read_sock_byte
*Description: Read 1 byte data of W5500 specified port register
*Input: sock: port number, reg: 16 bit register address
*Output: None
*Return: 1 byte data read from the register
*Description: None
*******************************************************************************/
uint8_t w5500_read_sock_byte(socket_t sock, uint16_t reg)
{
uint8_t val;
NCS_L();
spi_write_short(reg);
spi_write_byte(FDM1 | RWB_READ | (sock * 0x20 + 0x08));
val = spi_read_byte();
NCS_H();
return val;
}
/*******************************************************************************
*Function name: w5500_read_sock_short
*Description: Read 2 bytes of W5500 specified port register
*Input: sock: port number, reg: 16 bit register address
*Output: None
*Return: read 2 bytes of data from the register (16 bits)
*******************************************************************************/
uint16_t w5500_read_sock_short(socket_t sock, uint16_t reg)
{
uint16_t val;
NCS_L();
spi_write_short(reg);
spi_write_byte(FDM2 | RWB_READ |(sock * 0x20 + 0x08));
val = spi_read_byte();
val *= 256;
val |= spi_read_byte();
NCS_H();
return val;
}
/*******************************************************************************
*Function name: w5500_read_sock_bytes
*Description: Read data from W5500 receive data buffer
*Input: sock: port number, * dat: data saving buffer pointer
*Output: None
*Return: read data length
*******************************************************************************/
uint16_t w5500_read_sock_bytes(socket_t sock, uint8_t *dat)
{
uint16_t recv_size, write_addr;
uint16_t recv_addr;
uint16_t i;
uint8_t val;
recv_size = w5500_read_sock_short(sock, W5500_SN_RX_RSR_REG);
/* no receive data */
if(recv_size == 0)
{
return 0;
}
if(recv_size > W5500_MAX_PACK_SIZE)
{
recv_size = W5500_MAX_PACK_SIZE;
}
recv_addr = w5500_read_sock_short(sock, W5500_SN_RX_RD_REG);
write_addr = recv_addr;
/* calculate physical address */
recv_addr &= (SOCK_RECV_SIZE - 1);
NCS_L();
spi_write_short(recv_addr);
spi_write_byte(VDM | RWB_READ | (sock * 0x20 + 0x18));
if((recv_addr + recv_size) < SOCK_RECV_SIZE)
{
for(i = 0; i < recv_size; i++)
{
val = spi_read_byte();
*dat = val;
dat++;
}
}
else
{
recv_addr = SOCK_RECV_SIZE - recv_addr;
for(i = 0; i < recv_addr; i++)
{
val = spi_read_byte();
*dat = val;
dat++;
}
NCS_H();
NCS_L();
spi_write_short(0x00);
spi_write_byte(VDM | RWB_READ | (sock * 0x20 + 0x18));
for(; i < recv_size; i++)
{
val= spi_read_byte();
*dat = val;
dat++;
}
}
NCS_H();
write_addr += recv_size;
w5500_write_sock_short(sock, W5500_SN_RX_RD_REG, write_addr);
/* start receive */
w5500_write_sock_byte(sock, W5500_SN_CR_REG, SN_CR_RECV);
return recv_size;
}
/*******************************************************************************
*Function name: w5500_write_sock_bytes
*Description: Write data to the data sending buffer of W5500
*Input: sock: port number, dat: data storage buffer pointer, size: length of data to be written
*Output: None
*Return: None
*******************************************************************************/
void w5500_write_sock_bytes(socket_t sock, uint8_t *dat, uint16_t size)
{
uint16_t recv_addr, write_addr;
uint16_t i;
/* if udp mode, set ip and port */
if(w5500_read_sock_byte(sock, W5500_SN_MR_REG) != SOCK_UDP)
{
w5500_write_sock_long(sock, W5500_SN_DIPR_REG, w5500_param.udp_ip);
w5500_write_sock_short(sock, W5500_SN_DPORTR_REG, w5500_param.udp_port);
}
recv_addr = w5500_read_sock_short(sock, W5500_SN_TX_WR_REG);
write_addr = recv_addr;
recv_addr &= (SOCK_SEND_SIZE - 1);
NCS_L();
spi_write_short(recv_addr);
spi_write_byte(VDM | RWB_WRITE | (sock * 0x20 + 0x10));
if((recv_addr + size) < SOCK_SEND_SIZE)
{
for(i = 0; i < size; i++)
{
spi_write_byte(*dat++);
}
}
else
{
recv_addr = SOCK_SEND_SIZE - recv_addr;
for(i = 0; i < recv_addr; i++)
{
spi_write_byte(*dat++);
}
NCS_H();
NCS_L();
spi_write_short(0x00);
spi_write_byte(VDM | RWB_WRITE | (sock * 0x20 + 0x10));
for(; i < size; i++)
{
spi_write_byte(*dat++);
}
}
NCS_H();
write_addr += size;
w5500_write_sock_short(sock, W5500_SN_TX_WR_REG, write_addr);
w5500_write_sock_byte(sock, W5500_SN_CR_REG, SN_CR_SEND);
}
/*******************************************************************************
*Function name: w5500_reset
*Description: Hardware reset W5500
*Input: None
*Output: None
*Return value: None
*Note: The reset pin of the W5500 can be encircled only when the low level is at least 500us
*******************************************************************************/
void w5500_reset(void)
{
uint8_t dat = 0;
RST_L();
RST_H();
/* wait connect ok */
while((dat & LINK) == 0)
{
up_mdelay(500);
dat = w5500_read_byte(W5500_PHYCFGR_REG);
}
}
/*******************************************************************************
*Function name: w5500_config_init
*Description: Initialize W5500 register functions
*Input: None
*Output: None
*Return value: None
*Note: Before using W5500, initialize W5500
*******************************************************************************/
void w5500_config_init(void)
{
uint8_t i = 0;
/* software reset, set 1 and auto clear 0 */
w5500_write_byte(W5500_MR_REG, MR_RST);
up_mdelay(100);
w5500_write_bytes(W5500_GAR_REG, w5500_param.gw_addr, 4);
w5500_write_bytes(W5500_SUBR_REG, w5500_param.ip_mask, 4);
w5500_write_bytes(W5500_SHAR_REG, w5500_param.mac_addr, 6);
w5500_write_bytes(W5500_SIPR_REG, w5500_param.ip_addr, 4);
/* set socket rx and tx memory size 2k */
for(i = 0; i < 8; i++)
{
w5500_write_sock_byte(i, W5500_SN_RXBUF_SIZE_REG, 0x02);
w5500_write_sock_byte(i, W5500_SN_TXBUF_SIZE_REG, 0x02);
}
/* set retry time 200ms (0x07d0 = 2000) */
w5500_write_short(W5500_RTR_REG, 0x07d0);
/* retry time with 8, when exceed it, produce overtime interrupt, set W5500_SN_IR_REG(TIMEOUT) */
w5500_write_byte(W5500_RCR_REG, 8);
}
/*******************************************************************************
*Function name: Detect_Gateway
*Description: Check the gateway server
*Input: None
*Output: None
*Return value: TRUE (0xFF) for success, FALSE (0x00) for failure
*******************************************************************************/
uint8_t w5500_detect_gateway(void)
{
uint8_t ip_addr[4] = {w5500_param.ip_addr[0] + 1, w5500_param.ip_addr[1] + 1, w5500_param.ip_addr[2] + 1, w5500_param.ip_addr[3] + 1};
/* check gateway and get gateway phyiscal address */
w5500_write_sock_long(0, W5500_SN_DIPR_REG, ip_addr);
w5500_write_sock_byte(0, W5500_SN_MR_REG, SN_MR_TCP);
w5500_write_sock_byte(0, W5500_SN_CR_REG, SN_CR_OPEN);
up_mdelay(5);
if(w5500_read_sock_byte(0, W5500_SN_SR_REG) != SOCK_INIT)
{
w5500_write_sock_byte(0, W5500_SN_CR_REG, SN_CR_CLOSE);
return FALSE;
}
/* set socket connection mode */
w5500_write_sock_byte(0, W5500_SN_CR_REG, SN_CR_CONNECT);
do
{
uint8_t val = 0;
/* read socket0 interrupt register */
val = w5500_read_sock_byte(0, W5500_SN_IR_REG);
if(val != 0)
{
w5500_write_sock_byte(0, W5500_SN_IR_REG, val);
}
up_mdelay(5);
if((val & IR_TIMEOUT) == IR_TIMEOUT)
{
return FALSE;
}
else if(w5500_read_sock_byte(0, W5500_SN_DHAR_REG) != 0xff)
{
/* close socket */
w5500_write_sock_byte(0, W5500_SN_CR_REG, SN_CR_CLOSE);
return TRUE;
}
} while(1);
return TRUE;
}
/*******************************************************************************
*Function name: w5500_socket_init
*Description: Specify Socket (0~7) initialization
*Input: sock: port to be initialized
*Output: None
*Return value: None
*******************************************************************************/
void w5500_socket_init(socket_t sock)
{
/* max partition bytes = 30 */
w5500_write_sock_short(0, W5500_SN_MSSR_REG, 30);
switch(sock)
{
case 0:
w5500_write_sock_short(0, W5500_SN_PORT_REG, w5500_param.sock.local_port);
w5500_write_sock_short(0, W5500_SN_DPORTR_REG, w5500_param.sock.dst_port);
w5500_write_sock_long(0, W5500_SN_DIPR_REG, w5500_param.sock.dst_ip);
break;
default:
break;
}
}
/*******************************************************************************
*Function name: w5500_socket_connect
*Description: Set the specified Socket (0~7) as the client to connect with the remote server
*Input: sock: port to be set
*Output: None
*Return value: TRUE (0xFF) for success, FALSE (0x00) for failure
*******************************************************************************/
uint8_t w5500_socket_connect(socket_t sock)
{
w5500_write_sock_byte(sock, W5500_SN_MR_REG, SN_MR_TCP);
w5500_write_sock_byte(sock, W5500_SN_CR_REG, SN_CR_OPEN);
up_mdelay(5);
if(w5500_read_sock_byte(sock, W5500_SN_SR_REG) != SOCK_INIT)
{
w5500_write_sock_byte(sock, W5500_SN_CR_REG, SN_CR_CLOSE);
return FALSE;
}
w5500_write_sock_byte(sock, W5500_SN_CR_REG, SN_CR_CONNECT);
return TRUE;
}
/*******************************************************************************
*Function name: w5500_socket_listen
*Description: Set the specified Socket (0~7) as the server to wait for the connection of the remote host
*Input: sock: port to be set
*Output: None
*Return value: TRUE (0xFF) for success, FALSE (0x00) for failure
*******************************************************************************/
uint8_t w5500_socket_listen(socket_t sock)
{
w5500_write_sock_byte(sock, W5500_SN_MR_REG, SN_MR_TCP);
w5500_write_sock_byte(sock, W5500_SN_CR_REG, SN_CR_OPEN);
up_mdelay(5);
if(w5500_read_sock_byte(sock, W5500_SN_SR_REG) != SOCK_INIT)
{
w5500_write_sock_byte(sock, W5500_SN_CR_REG, SN_CR_CLOSE);
return FALSE;
}
w5500_write_sock_byte(sock, W5500_SN_CR_REG, SN_CR_LISTEN);
up_mdelay(5);
if(w5500_read_sock_byte(sock, W5500_SN_SR_REG) != SOCK_LISTEN)
{
w5500_write_sock_byte(sock, W5500_SN_CR_REG, SN_CR_CLOSE);
return FALSE;
}
return TRUE;
}
/*******************************************************************************
*Function name: w5500_socket_set_udp
*Description: Set the specified Socket (0~7) to UDP mode
*Input: sock: port to be set
*Output: None
*Return value: TRUE (0xFF) for success, FALSE (0x00) for failure
*******************************************************************************/
uint8_t w5500_socket_set_udp(socket_t sock)
{
w5500_write_sock_byte(sock, W5500_SN_MR_REG, SN_MR_UDP);
w5500_write_sock_byte(sock, W5500_SN_CR_REG, SN_CR_OPEN);
up_mdelay(5);
if(w5500_read_sock_byte(sock, W5500_SN_SR_REG) != SOCK_UDP)
{
w5500_write_sock_byte(sock, W5500_SN_CR_REG, SN_CR_CLOSE);
return FALSE;
}
return TRUE;
}
/*******************************************************************************
*Function name: w5500_irq_process
*Description: W5500 interrupt handler framework
*Input: None
*Output: None
*Return value: None
*Description: None
*******************************************************************************/
void w5500_irq_process(void)
{
uint8_t ir_flag, sn_flag;
ir_flag = w5500_read_byte(W5500_SIR_REG);
do
{
/* handle socket0 event */
if((ir_flag & S0_INT) == S0_INT)
{
sn_flag = w5500_read_sock_byte(0, W5500_SN_IR_REG);
w5500_write_sock_byte(0, W5500_SN_IR_REG, sn_flag);
if(sn_flag & IR_CON)
{
/* socket connection finished */
w5500_param.sock.flag |= SOCK_FLAG_CONN;
}
if(sn_flag & IR_DISCON)
{
/* disconnect state */
w5500_write_sock_byte(0, W5500_SN_CR_REG, SN_CR_CLOSE);
w5500_socket_init(0);
w5500_param.sock.flag = 0;
}
if(sn_flag & IR_SEND_OK)
{
/* send one package ok */
w5500_param.sock.state |= SOCK_STAT_SEND;
}
if(sn_flag & IR_RECV)
{
w5500_param.sock.state |= SOCK_STAT_RECV;
}
if(sn_flag & IR_TIMEOUT)
{
/* close socket, connection failed */
w5500_write_sock_byte(0, W5500_SN_CR_REG, SN_CR_CLOSE);
w5500_param.sock.flag = 0;
}
}
ir_flag = w5500_read_byte(W5500_SIR_REG);
}while(ir_flag);
}
/*******************************************************************************
*Function name: w5500_intialization
*Description: W5500 initial configuration
*Input: None
*Output: None
*Return value: None
*******************************************************************************/
void w5500_intialization(void)
{
w5500_config_init();
w5500_detect_gateway();
w5500_socket_init(0);
}
/*******************************************************************************
*Function name: w5500_load_param
*Description: load param to w5500_param
*Input: None
*Output: None
*Return value: None
*******************************************************************************/
void w5500_load_param(void)
{
w5500_param_t *param = &w5500_param;
memcpy(param->ip_addr, config_ip_addr, sizeof(config_ip_addr));
memcpy(param->ip_mask, config_ip_mask, sizeof(config_ip_mask));
memcpy(param->gw_addr, config_gw_addr, sizeof(config_gw_addr));
memcpy(param->mac_addr, config_mac_addr, sizeof(config_mac_addr));
memcpy(param->sock.dst_ip, config_dst_ip, sizeof(config_dst_ip));
param->sock.local_port = config_local_port;
param->sock.dst_port = config_dst_port;
param->sock.mode = config_mode;
}
/*******************************************************************************
*Function name: w5500_socket_config
*Description: W5500 port initialization configuration
*Input: None
*Output: None
*Return value: None
*******************************************************************************/
void w5500_socket_config(void)
{
if(w5500_param.sock.flag == 0)
{
/* TCP Sever */
if(w5500_param.sock.mode == SOCK_TCP_SVR)
{
if(w5500_socket_listen(0) == TRUE)
w5500_param.sock.flag = SOCK_FLAG_INIT;
else
w5500_param.sock.flag = 0;
}
/* TCP Client */
else if(w5500_param.sock.mode == SOCK_TCP_CLI)
{
if(w5500_socket_connect(0) == TRUE)
w5500_param.sock.flag = SOCK_FLAG_INIT;
else
w5500_param.sock.flag = 0;
}
/* UDP */
else
{
if(w5500_socket_set_udp(0) == TRUE)
w5500_param.sock.flag = SOCK_FLAG_INIT|SOCK_FLAG_CONN;
else
w5500_param.sock.flag = 0;
}
}
}
/*******************************************************************************
*Function name: Process_Socket_Data
*Description: W5500 receives and sends the received data
*Input: sock: port number
*Output: None
*Return value: receive data length
*******************************************************************************/
uint16_t Process_Socket_Data(socket_t sock)
{
uint16_t size;
size = w5500_read_sock_bytes(sock, rx_buf);
memcpy(tx_buf, rx_buf, size);
w5500_write_sock_bytes(sock, tx_buf, size);
return size;
}
/****************************************************************************
* Name: SPI_Configuration
* Description: spi pin mode configure
* input: None
* output: None
* return:none
****************************************************************************/
void SPI_Configuration(void)
{
/* config simluate SPI bus */
k210_fpioa_config(BSP_ENET_SCLK, HS_GPIO(FPIOA_ENET_SCLK) | K210_IOFLAG_GPIOHS);
k210_fpioa_config(BSP_ENET_NRST, HS_GPIO(FPIOA_ENET_NRST) | K210_IOFLAG_GPIOHS);
k210_fpioa_config(BSP_ENET_MOSI, HS_GPIO(FPIOA_ENET_MOSI) | K210_IOFLAG_GPIOHS);
k210_fpioa_config(BSP_ENET_MISO, HS_GPIO(FPIOA_ENET_MISO) | K210_IOFLAG_GPIOHS);
k210_fpioa_config(BSP_ENET_NCS, HS_GPIO(FPIOA_ENET_NCS) | K210_IOFLAG_GPIOHS);
k210_fpioa_config(BSP_ENET_NINT, HS_GPIO(FPIOA_ENET_NINT) | K210_IOFLAG_GPIOHS);
k210_gpiohs_set_direction(FPIOA_ENET_MISO, GPIO_DM_INPUT);
k210_gpiohs_set_direction(FPIOA_ENET_NRST, GPIO_DM_OUTPUT);
k210_gpiohs_set_direction(FPIOA_ENET_SCLK, GPIO_DM_OUTPUT);
k210_gpiohs_set_direction(FPIOA_ENET_MOSI, GPIO_DM_OUTPUT);
k210_gpiohs_set_direction(FPIOA_ENET_NCS, GPIO_DM_OUTPUT);
k210_gpiohs_set_direction(FPIOA_ENET_NINT, GPIO_DM_INPUT);
k210_gpiohs_set_value(FPIOA_ENET_SCLK, GPIO_PV_HIGH);
k210_gpiohs_set_value(FPIOA_ENET_MOSI, GPIO_PV_HIGH);
k210_gpiohs_set_value(FPIOA_ENET_NCS, GPIO_PV_LOW);
k210_gpiohs_set_value(FPIOA_ENET_NRST, GPIO_PV_HIGH);
}
void w5500_test(void)
{
uint8_t cnt = 0;
uint8_t length = 0;
SPI_Configuration();
w5500_load_param();
w5500_reset();
w5500_intialization();
while(1)
{
w5500_socket_config();
w5500_irq_process();
/* If Socket0 receives data */
if((w5500_param.sock.state & SOCK_STAT_RECV) == SOCK_STAT_RECV)
{
w5500_param.sock.state &= ~SOCK_STAT_RECV;
length = Process_Socket_Data(0);
printf("w5500 receive: ");
for(int i = 0; i < length; i++)
{
printf("%x ", rx_buf[i]);
}
printf("\n");
}
/* Otherwise, send data regularly */
else if(cnt >= 5)
{
if(w5500_param.sock.flag == (SOCK_FLAG_INIT|SOCK_FLAG_CONN))
{
w5500_param.sock.state &= ~SOCK_STAT_SEND;
memcpy(tx_buf, "\r\nWelcome To internet!\r\n", 21);
w5500_write_sock_bytes(0, tx_buf, 21);
}
cnt = 0;
}
up_mdelay(100);
cnt++;
}
}

319
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/*
* Copyright (c) 2022 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file k210_w5500.h
* @brief w5500 driver
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-9-15
*/
#ifndef _K210_W5500_H_
#define _K210_W5500_H_
#include <nuttx/config.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include <errno.h>
#include <stddef.h>
#include <stdint.h>
#include <stdio.h>
#include <debug.h>
#include <assert.h>
#include <nuttx/time.h>
#include <nuttx/fs/fs.h>
#include "k210_config.h"
#include "k210_fpioa.h"
#include "k210_gpiohs.h"
#include "nuttx/arch.h"
#include "k210_gpio_common.h"
/***************** Common Register *****************/
#define W5500_MR_REG 0x0000
#define MR_RST 0x80
#define MR_WOL 0x20
#define MR_PB 0x10
#define MR_PPP 0x08
#define MR_FARP 0x02
#define W5500_GAR_REG 0x0001
#define W5500_SUBR_REG 0x0005
#define W5500_SHAR_REG 0x0009
#define W5500_SIPR_REG 0x000f
#define W5500_INT_REG 0x0013
#define W5500_IR_REG 0x0015
#define IR_CONFLICT 0x80
#define IR_UNREACH 0x40
#define IR_PPPOE 0x20
#define IR_MP 0x10
#define W5500_IMR_REG 0x0016
#define IMR_IR7 0x80
#define IMR_IR6 0x40
#define IMR_IR5 0x20
#define IMR_IR4 0x10
#define W5500_SIR_REG 0x0017
#define S7_INT 0x80
#define S6_INT 0x40
#define S5_INT 0x20
#define S4_INT 0x10
#define S3_INT 0x08
#define S2_INT 0x04
#define S1_INT 0x02
#define S0_INT 0x01
#define W5500_SIMR_REG 0x0018
#define S7_IMR 0x80
#define S6_IMR 0x40
#define S5_IMR 0x20
#define S4_IMR 0x10
#define S3_IMR 0x08
#define S2_IMR 0x04
#define S1_IMR 0x02
#define S0_IMR 0x01
#define W5500_RTR_REG 0x0019
#define W5500_RCR_REG 0x001B
#define W5500_PTIMER_REG 0x001C
#define W5500_PMAGIC_REG 0x001D
#define W5500_PHA_REG 0x001E
#define W5500_PSID_REG 0x0024
#define W5500_PMRU_REG 0x0026
#define W5500_UIPR_REG 0x0028
#define W5500_UPORT_REG 0x002C
#define W5500_PHYCFGR_REG 0x002E
#define RST_PHY 0x80
#define OPMODE 0x40
#define DPX 0x04
#define SPD 0x02
#define LINK 0x01
#define W5500_VER_REG 0x0039
/********************* Socket Register *******************/
#define W5500_SN_MR_REG 0x0000
#define SN_MR_MULTI_MFEN 0x80
#define SN_MR_BCASTB 0x40
#define SN_MR_ND_MC_MMB 0x20
#define SN_MR_UCASTB_MIP6B 0x10
#define SN_MR_CLOSE 0x00
#define SN_MR_TCP 0x01
#define SN_MR_UDP 0x02
#define SN_MR_MACRAW 0x04
#define W5500_SN_CR_REG 0x0001
#define SN_CR_OPEN 0x01
#define SN_CR_LISTEN 0x02
#define SN_CR_CONNECT 0x04
#define SN_CR_DISCON 0x08
#define SN_CR_CLOSE 0x10
#define SN_CR_SEND 0x20
#define SN_CR_SEND_MAC 0x21
#define SN_CR_SEND_KEEP 0x22
#define SN_CR_RECV 0x40
#define W5500_SN_IR_REG 0x0002
#define IR_SEND_OK 0x10
#define IR_TIMEOUT 0x08
#define IR_RECV 0x04
#define IR_DISCON 0x02
#define IR_CON 0x01
#define W5500_SN_SR_REG 0x0003
#define SOCK_CLOSED 0x00
#define SOCK_INIT 0x13
#define SOCK_LISTEN 0x14
#define SOCK_ESTABLISHED 0x17
#define SOCK_CLOSE_WAIT 0x1C
#define SOCK_UDP 0x22
#define SOCK_MACRAW 0x02
#define SOCK_SYNSEND 0x15
#define SOCK_SYNRECV 0x16
#define SOCK_FIN_WAI 0x18
#define SOCK_CLOSING 0x1A
#define SOCK_TIME_WAIT 0x1B
#define SOCK_LAST_ACK 0x1D
#define W5500_SN_PORT_REG 0x0004
#define W5500_SN_DHAR_REG 0x0006
#define W5500_SN_DIPR_REG 0x000C
#define W5500_SN_DPORTR_REG 0x0010
#define W5500_SN_MSSR_REG 0x0012
#define W5500_SN_TOS_REG 0x0015
#define W5500_SN_TTL_REG 0x0016
#define W5500_SN_RXBUF_SIZE_REG 0x001E
#define W5500_SN_TXBUF_SIZE_REG 0x001F
#define W5500_SN_TX_FSR_REG 0x0020
#define W5500_SN_TX_RD_REG 0x0022
#define W5500_SN_TX_WR_REG 0x0024
#define W5500_SN_RX_RSR_REG 0x0026
#define W5500_SN_RX_RD_REG 0x0028
#define W5500_SN_RX_WR_REG 0x002A
#define W5500_SN_IMR_REG 0x002C
#define IMR_SENDOK 0x10
#define IMR_TIMEOUT 0x08
#define IMR_RECV 0x04
#define IMR_DISCON 0x02
#define IMR_CON 0x01
#define W5500_SN_FRAG_REG 0x002D
#define W5500_SN_KPALVTR_REG 0x002F
/************************ SPI Control Data *************************/
/* Operation mode bits */
#define VDM 0x00
#define FDM1 0x01
#define FDM2 0x02
#define FDM4 0x03
/* Read_Write control bit */
#define RWB_READ 0x00
#define RWB_WRITE 0x04
/* Block select bits */
#define COMMON_R 0x00
/* Socket 0 */
#define S0_REG 0x08
#define S0_TX_BUF 0x10
#define S0_RX_BUF 0x18
/* Socket 1 */
#define S1_REG 0x28
#define S1_TX_BUF 0x30
#define S1_RX_BUF 0x38
/* Socket 2 */
#define S2_REG 0x48
#define S2_TX_BUF 0x50
#define S2_RX_BUF 0x58
/* Socket 3 */
#define S3_REG 0x68
#define S3_TX_BUF 0x70
#define S3_RX_BUF 0x78
/* Socket 4 */
#define S4_REG 0x88
#define S4_TX_BUF 0x90
#define S4_RX_BUF 0x98
/* Socket 5 */
#define S5_REG 0xa8
#define S5_TX_BUF 0xb0
#define S5_RX_BUF 0xb8
/* Socket 6 */
#define S6_REG 0xc8
#define S6_TX_BUF 0xd0
#define S6_RX_BUF 0xd8
/* Socket 7 */
#define S7_REG 0xe8
#define S7_TX_BUF 0xf0
#define S7_RX_BUF 0xf8
// socket receive buffer size based on RMSR
#define SOCK_RECV_SIZE 2048
// socket send buffer size based on RMSR
#define SOCK_SEND_SIZE 2048
#define W5500_IP_ADDR_LEN 4
#define W5500_IP_MASK_LEN 4
#define W5500_GW_ADDR_LEN 4
#define W5500_MAC_ADDR_LEN 6
//for every socket
// socket mode
#define SOCK_TCP_SVR 0 //server mode
#define SOCK_TCP_CLI 1 //client mode
#define SOCK_UDP_MOD 2 //udp mode
// socket flag
#define SOCK_FLAG_INIT 1
#define SOCK_FLAG_CONN 2
// socket data state
#define SOCK_STAT_RECV 1
#define SOCK_STAT_SEND 2
typedef struct w5500_socket_s
{
uint16_t local_port;
uint8_t dst_ip[W5500_IP_ADDR_LEN];
uint16_t dst_port;
uint8_t mode; // 0: TCP Server; 1: TCP client; 2: UDP
uint8_t flag; // 1: init ok; 2: connected
uint8_t state; // 1: receive one; 2: send ok
}w5500_socket_t;
typedef struct
{
uint8_t ip_addr[W5500_IP_ADDR_LEN];
uint8_t ip_mask[W5500_IP_MASK_LEN];
uint8_t gw_addr[W5500_GW_ADDR_LEN];
uint8_t mac_addr[W5500_MAC_ADDR_LEN];
uint8_t udp_ip[4];
uint16_t udp_port;
w5500_socket_t sock;
}w5500_param_t;
#define W5500_MAX_PACK_SIZE 1460
typedef unsigned char socket_t;
#define NCS_L() k210_gpiohs_set_value(FPIOA_ENET_NCS, GPIO_PV_LOW); up_udelay(1);
#define NCS_H() k210_gpiohs_set_value(FPIOA_ENET_NCS, GPIO_PV_HIGH); up_udelay(1);
#define SCLK_L() k210_gpiohs_set_value(FPIOA_ENET_SCLK, GPIO_PV_LOW); up_udelay(1);
#define SCLK_H() k210_gpiohs_set_value(FPIOA_ENET_SCLK, GPIO_PV_HIGH); up_udelay(1);
#define MOSI_L() k210_gpiohs_set_value(FPIOA_ENET_MOSI, GPIO_PV_LOW); up_udelay(1);
#define MOSI_H() k210_gpiohs_set_value(FPIOA_ENET_MOSI, GPIO_PV_HIGH); up_udelay(1);
#define RST_L() k210_gpiohs_set_value(FPIOA_ENET_NRST, GPIO_PV_LOW); up_mdelay(200);
#define RST_H() k210_gpiohs_set_value(FPIOA_ENET_NRST, GPIO_PV_HIGH); up_mdelay(200);
void w5500_write_sock_byte(socket_t sock, uint16_t reg, uint8_t dat);
void w5500_write_sock_short(socket_t sock, uint16_t reg, uint16_t dat);
void w5500_write_sock_long(socket_t sock, uint16_t reg, uint8_t *dat);
uint8_t w5500_read_byte(uint16_t reg);
uint8_t w5500_read_sock_byte(socket_t sock, uint16_t reg);
uint16_t w5500_read_sock_short(socket_t sock, uint16_t reg);
void w5500_write_sock_bytes(socket_t sock, uint8_t *dat, uint16_t size);
void w5500_reset(void);
void w5500_config_init(void);
uint8_t w5500_detect_gateway(void);
void w5500_socket_init(socket_t sock);
uint8_t w5500_socket_connect(socket_t sock);
uint8_t w5500_socket_listen(socket_t sock);
uint8_t w5500_socket_set_udp(socket_t sock);
void w5500_irq_process(void);
void w5500_intialization(void);
void w5500_load_param(void);
void w5500_socket_config(void);
uint16_t Process_Socket_Data(socket_t sock);
void SPI_Configuration(void);
void w5500_test(void);
#endif

12
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/Kconfig
View File

@ -547,6 +547,18 @@ config NSH_DISABLE_XD
bool "Disable xd"
default DEFAULT_SMALL
config NSH_DISABLE_CH376
bool "Disable the ch376 demo."
default n
config NSH_DISABLE_W5500
bool "Disable the w5500 demo."
default n
config NSH_DISABLE_TOUCH
bool "Disable the gt911 touch screen demo."
default n
config NSH_DISABLE_CH438
bool "Disable the ch438 demo."
default n

14
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh.h
View File

@ -1450,6 +1450,18 @@ int nsh_foreach_var(FAR struct nsh_vtbl_s *vtbl, nsh_foreach_var_t cb,
FAR void *arg);
#endif
#if defined(CONFIG_BSP_USING_CH376) && !defined(CONFIG_NSH_DISABLE_CH376)
int cmd_Ch376(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv);
#endif
#if defined(CONFIG_BSP_USING_ENET) && !defined(CONFIG_NSH_DISABLE_W5500)
int cmd_w5500(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv);
#endif
#if defined(CONFIG_BSP_USING_TOUCH) && !defined(CONFIG_NSH_DISABLE_TOUCH)
int cmd_Touch(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv);
#endif
#if defined(CONFIG_BSP_USING_CH438) && !defined(CONFIG_NSH_DISABLE_CH438)
int cmd_Ch438(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv);
#endif
@ -1567,7 +1579,7 @@ int nsh_foreach_var(FAR struct nsh_vtbl_s *vtbl, nsh_foreach_var_t cb,
int cmd_AdapterBlueToothTest(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv);
#endif
#if defined(CONFIG_ADAPTER_ESP07S_WIFI) && !defined(CONFIG_NSH_DISABLE_ADAPTER_WIFI_TEST)
#if (defined(CONFIG_ADAPTER_ESP07S_WIFI) || defined(CONFIG_ADAPTER_ESP8285_WIFI)) && !defined(CONFIG_NSH_DISABLE_ADAPTER_WIFI_TEST)
int cmd_AdapterWifiTest(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv);
#endif

41
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_Applicationscmd.c
View File

@ -38,6 +38,45 @@
extern int FrameworkInit(void);
/****************************************************************************
* Name: cmd_Ch376
****************************************************************************/
#if defined(CONFIG_BSP_USING_CH376) && !defined(CONFIG_NSH_DISABLE_CH376)
extern void CH376Demo(void);
int cmd_Ch376(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv)
{
nsh_output(vtbl, "Hello, world!\n");
CH376Demo();
return OK;
}
#endif
/****************************************************************************
* Name: cmd_w5500
****************************************************************************/
#if defined(CONFIG_BSP_USING_ENET) && !defined(CONFIG_NSH_DISABLE_W5500)
extern void w5500_test(void);
int cmd_w5500(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv)
{
nsh_output(vtbl, "Hello, world!\n");
w5500_test();
return OK;
}
#endif
/****************************************************************************
* Name: cmd_Touch
****************************************************************************/
#if defined(CONFIG_BSP_USING_TOUCH) && !defined(CONFIG_NSH_DISABLE_TOUCH)
extern void GT911_test(void);
int cmd_Touch(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv)
{
nsh_output(vtbl, "Hello, world!\n");
GT911_test();
return OK;
}
#endif
/****************************************************************************
* Name: cmd_Ch438
****************************************************************************/
@ -363,7 +402,7 @@ int cmd_recvzigbee(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv)
}
#endif
#if defined(CONFIG_ADAPTER_ESP07S_WIFI) && !defined(CONFIG_NSH_DISABLE_ADAPTER_WIFI_TEST)
#if (defined(CONFIG_ADAPTER_ESP07S_WIFI) || defined(CONFIG_ADAPTER_ESP8285_WIFI)) && !defined(CONFIG_NSH_DISABLE_ADAPTER_WIFI_TEST)
extern int AdapterWifiTestWithParam(int argc, char *argv[]);
int cmd_AdapterWifiTest(FAR struct nsh_vtbl_s *vtbl, int argc, char **argv)
{

14
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/apps/nshlib/nsh_command.c
View File

@ -596,6 +596,18 @@ static const struct cmdmap_s g_cmdmap[] =
{ "xd", cmd_xd, 3, 3, "<hex-address> <byte-count>" },
#endif
#if defined(CONFIG_BSP_USING_CH376) && !defined(CONFIG_NSH_DISABLE_CH376)
{ "ch376", cmd_Ch376, 1, 1, "[ch376 demo cmd.]" },
#endif
#if defined(CONFIG_BSP_USING_ENET) && !defined(CONFIG_NSH_DISABLE_W5500)
{ "w5500", cmd_w5500, 1, 1, "[w5500 demo cmd.]" },
#endif
#if defined(CONFIG_BSP_USING_TOUCH) && !defined(CONFIG_NSH_DISABLE_TOUCH)
{ "touch", cmd_Touch, 1, 1, "[gt911 touch screen demo cmd.]" },
#endif
#if defined(CONFIG_BSP_USING_CH438) && !defined(CONFIG_NSH_DISABLE_CH438)
{ "ch438", cmd_Ch438, 1, 1, "[ch438 demo cmd.]" },
#endif
@ -712,7 +724,7 @@ static const struct cmdmap_s g_cmdmap[] =
{ "AdapterBlueToothTest", cmd_AdapterBlueToothTest, 1, 1, "[BlueTooth hc08 test.]" },
#endif
#if defined(CONFIG_ADAPTER_ESP07S_WIFI) && !defined(CONFIG_NSH_DISABLE_ADAPTER_WIFI_TEST)
#if (defined(CONFIG_ADAPTER_ESP07S_WIFI) || defined(CONFIG_ADAPTER_ESP8285_WIFI)) && !defined(CONFIG_NSH_DISABLE_ADAPTER_WIFI_TEST)
{ "wifitest", cmd_AdapterWifiTest, 1, 8, "[WIFI test.]" },
#endif

1
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/build.sh
View File

@ -19,5 +19,6 @@ cp -rf $nuttx/aiit_board/aiit-arm32-board $nuttx/nuttx/boards/arm/stm32
cp -rf $nuttx/aiit_board/aiit-riscv64-board $nuttx/nuttx/boards/risc-v/k210
cp -rf $nuttx/aiit_board/xidatong-riscv64 $nuttx/nuttx/boards/risc-v/k210
cp -rf $nuttx/aiit_board/xidatong-arm32 $nuttx/nuttx/boards/arm/imxrt
cp -rf $nuttx/aiit_board/hc32f4a0 $nuttx/nuttx/boards/arm/hc32
cd ../nuttx

1229
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/Kconfig Executable file
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File diff suppressed because it is too large Load Diff

30
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/include/hc32/chip.h Executable file
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@ -0,0 +1,30 @@
/****************************************************************************
* arch/arm/include/stm32f7/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_HC32F4A0_CHIP_H
#define __ARCH_ARM_INCLUDE_HC32F4A0_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#endif /* __ARCH_ARM_INCLUDE_HC32F4A0_CHIP_H */

102
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/include/hc32/irq.h Executable file
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@ -0,0 +1,102 @@
/****************************************************************************
* arch/arm/include/HC32F4A0/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_HC32F4A0_IRQ_H
#define __ARCH_ARM_INCLUDE_HC32F4A0_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/* Processor Exceptions (vectors 0-15) */
#define HC32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define HC32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define HC32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define HC32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define HC32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define HC32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define HC32_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define HC32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define HC32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define HC32_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16).
* These definitions are chip-specific
*/
#define HC32_IRQ_FIRST (16) /* Vector number of the first external interrupt */
#define NR_IRQS (144 + 15)
#define NVIC_SYSH_PRIORITY_MIN 0xf0
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80
#define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_PRIORITY_DEFAULT
#define ARMV7M_PERIPHERAL_INTERRUPTS NR_IRQS
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_HC32F4A0_IRQ_H */

174
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/Kconfig Executable file
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@ -0,0 +1,174 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
comment "HC32 Configuration Options"
choice
prompt "HC32 Chip Selection"
default HC32F4A0_CHIP
config HC32F4A0_CHIP
bool "HC32F4A0"
---help---
endchoice
menu "HC32 U[S]ART Selection"
config HC32_UART1
bool "UART1"
default n
select UART_SERIALDRIVER
select UART1_SERIALDRIVER
select HC32_UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
select HC32_UART
config HC32_UART2
bool "UART2"
default n
select HC32_UART2_SERIALDRIVER
select UART_SERIALDRIVER
select UART2_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
select HC32_UART
config HC32_UART3
bool "UART3"
default n
select ARCH_HAVE_SERIAL_TERMIOS
select UART_SERIALDRIVER
select UART3_SERIALDRIVER
select HC32_UART3_SERIALDRIVER
select HC32_UART
config HC32_UART4
bool "UART4"
default n
select ARCH_HAVE_SERIAL_TERMIOS
select UART_SERIALDRIVER
select UART4_SERIALDRIVER
select HC32_UART4_SERIALDRIVER
select HC32_UART
config HC32_UART5
bool "UART5"
default n
select ARCH_HAVE_SERIAL_TERMIOS
select UART_SERIALDRIVER
select UART5_SERIALDRIVER
select HC32_UART5_SERIALDRIVER
select HC32_UART
config HC32_UART6
bool "UART6"
default n
select ARCH_HAVE_SERIAL_TERMIOS
select UART_SERIALDRIVER
select UART6_SERIALDRIVER
select HC32_UART6_SERIALDRIVER
select HC32_UART
config HC32_UART6_SERIALDRIVER
bool "UART6SERIAL"
default n
if HC32_UART6
menu "UART6 Configuration"
depends on UART6_SERIALDRIVER
config UART6_RXBUFSIZE
int "Receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config UART6_TXBUFSIZE
int "Transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config UART6_BAUD
int "BAUD rate"
default 115200
---help---
The configured BAUD of the UART.
config UART6_BITS
int "Character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config UART6_PARITY
int "Parity setting"
range 0 2
default 0
---help---
0=no parity, 1=odd parity, 2=even parity
config UART6_2STOP
int "use 2 stop bits"
default 0
---help---
1=Two stop bits
config UART6_IFLOWCONTROL
bool "UART6 RTS flow control"
default n
select SERIAL_IFLOWCONTROL
---help---
Enable UART6 RTS flow control
config UART6_OFLOWCONTROL
bool "UART6 CTS flow control"
default n
select SERIAL_OFLOWCONTROL
---help---
Enable UART6 CTS flow control
config UART6_RXDMA
bool "UART6 Rx DMA support"
default n
select SERIAL_RXDMA
---help---
Enable Rx DMA transfers on UART6
config UART6_TXDMA
bool "UART6 Tx DMA support"
default n
select SERIAL_TXDMA
---help---
Enable Tx DMA transfers on UART6
endmenu
endif
config HC32_UART7
bool "UART7"
default n
select ARCH_HAVE_SERIAL_TERMIOS
select UART_SERIALDRIVER
select UART7_SERIALDRIVER
select HC32_UART7_SERIALDRIVER
select HC32_UART
config HC32_UART8
bool "UART8"
default n
select ARCH_HAVE_SERIAL_TERMIOS
select UART_SERIALDRIVER
select UART8_SERIALDRIVER
select HC32_UART8_SERIALDRIVER
select HC32_UART
endmenu # HC32 U[S]ART Selection

88
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/Make.defs Executable file
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@ -0,0 +1,88 @@
############################################################################
# arch/arm/src/hc32/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S
CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_copyfullstate.c arm_createstack.c
CMN_CSRCS += arm_exit.c arm_hardfault.c arm_initialize.c arm_initialstate.c
CMN_CSRCS += arm_interruptcontext.c arm_memfault.c arm_modifyreg8.c arm_mdelay.c
CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_releasepending.c
CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_stackframe.c arm_svcall.c arm_systemreset.c
CMN_CSRCS += arm_trigger_irq.c arm_unblocktask.c arm_udelay.c arm_usestack.c
CMN_CSRCS += arm_doirq.c arm_vfork.c arm_switchcontext.c arm_puts.c
CMN_CSRCS += arm_tcbinfo.c
ifeq ($(CONFIG_HC32_TICKLESS_SYSTICK),y)
CMN_CSRCS += arm_systick.c
endif
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += arm_lazyexception.S
else
CMN_ASRCS += arm_exception.S
endif
CMN_CSRCS += arm_vectors.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifneq ($(filter y,$(CONFIG_ARM_MPU) $(CONFIG_ARM_MPU_EARLY_RESET)),)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_copyarmstate.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
CMN_CSRCS += arm_itm_syslog.c
endif
ifeq ($(CONFIG_SCHED_THREAD_LOCAL),y)
CMN_CSRCS += arm_tls.c
endif
CHIP_CSRCS = hc32_allocateheap.c hc32_gpio.c
CHIP_CSRCS += hc32_irq.c hc32_idle.c hc32_mpuinit.c
CHIP_CSRCS += hc32_rcc.c hc32_start.c hc32_serial.c
CHIP_CSRCS += hc32_pm.c hc32_timerisr.c hc32_lowputc.c
CHIP_CSRCS += hc32f4a0_clk.c hc32f4a0_efm.c hc32f4a0_gpio.c
CHIP_CSRCS += hc32f4a0_interrupts.c hc32f4a0_usart.c hc32f4a0_utility.c
CHIP_CSRCS += hc32f4a0_sram.c hc32f4a0_pwc.c

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Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/chip.h Executable file
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/****************************************************************************
* arch/arm/src/hc32/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_HC32_CHIP_H
#define __ARCH_ARM_SRC_HC32_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Include the chip capabilities file */
#include <arch/hc32/chip.h>
/* Include the chip interrupt definition file */
#include <arch/hc32/irq.h>
/* Include the chip memory map */
//#include "hardware/hc32_memorymap.h"
/* Include the chip pinmap */
//#include "hardware/hc32_pinmap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Provide the required number of peripheral interrupt vector definitions as
* well. The definition HC32_IRQ_NEXTINT simply comes from the chip-specific
* IRQ header file included by arch/hc32/irq.h.
*/
//#define ARMV7M_PERIPHERAL_INTERRUPTS HC32_IRQ_NEXTINT
#endif /* __ARCH_ARM_SRC_HC32_CHIP_H */

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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.7
* @date 19. June 2018
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2018 IAR Systems
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/cmsis_version.h Executable file
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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/core_cm4.h Executable file
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214
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/ddl_config.h Executable file
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/**
*******************************************************************************
* @file usart/uart_int/source/ddl_config.h
* @brief This file contains HC32 Series Device Driver Library usage management.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __DDL_CONFIG_H__
#define __DDL_CONFIG_H__
/*******************************************************************************
* Include files
******************************************************************************/
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/* Chip module on-off define */
#define DDL_ON (1U)
#define DDL_OFF (0U)
/**
* @brief This is the list of modules to be used in the Device Driver Library.
* Select the modules you need to use to DDL_ON.
* @note DDL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
* properly.
* @note DDL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
* Library.
* @note DDL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
*/
#define DDL_ICG_ENABLE (DDL_ON)
#define DDL_UTILITY_ENABLE (DDL_ON)
#define DDL_PRINT_ENABLE (DDL_ON)
#define DDL_ADC_ENABLE (DDL_OFF)
#define DDL_AES_ENABLE (DDL_OFF)
#define DDL_CAN_ENABLE (DDL_OFF)
#define DDL_CLK_ENABLE (DDL_ON)
#define DDL_CMP_ENABLE (DDL_OFF)
#define DDL_CRC_ENABLE (DDL_OFF)
#define DDL_CTC_ENABLE (DDL_OFF)
#define DDL_DAC_ENABLE (DDL_OFF)
#define DDL_DCU_ENABLE (DDL_OFF)
#define DDL_DMA_ENABLE (DDL_OFF)
#define DDL_DMC_ENABLE (DDL_OFF)
#define DDL_DVP_ENABLE (DDL_OFF)
#define DDL_EFM_ENABLE (DDL_ON)
#define DDL_EMB_ENABLE (DDL_OFF)
#define DDL_ETH_ENABLE (DDL_OFF)
#define DDL_EVENT_PORT_ENABLE (DDL_OFF)
#define DDL_FCM_ENABLE (DDL_OFF)
#define DDL_FMAC_ENABLE (DDL_OFF)
#define DDL_GPIO_ENABLE (DDL_ON)
#define DDL_HASH_ENABLE (DDL_OFF)
#define DDL_HRPWM_ENABLE (DDL_OFF)
#define DDL_I2C_ENABLE (DDL_ON)
#define DDL_I2S_ENABLE (DDL_OFF)
#define DDL_INTERRUPTS_ENABLE (DDL_ON)
#define DDL_KEYSCAN_ENABLE (DDL_ON)
#define DDL_MAU_ENABLE (DDL_OFF)
#define DDL_MPU_ENABLE (DDL_OFF)
#define DDL_NFC_ENABLE (DDL_OFF)
#define DDL_OTS_ENABLE (DDL_OFF)
#define DDL_PWC_ENABLE (DDL_ON)
#define DDL_QSPI_ENABLE (DDL_OFF)
#define DDL_RMU_ENABLE (DDL_OFF)
#define DDL_RTC_ENABLE (DDL_OFF)
#define DDL_SDIOC_ENABLE (DDL_OFF)
#define DDL_SMC_ENABLE (DDL_OFF)
#define DDL_SPI_ENABLE (DDL_OFF)
#define DDL_SRAM_ENABLE (DDL_ON)
#define DDL_SWDT_ENABLE (DDL_OFF)
#define DDL_TMR0_ENABLE (DDL_OFF)
#define DDL_TMR2_ENABLE (DDL_OFF)
#define DDL_TMR4_ENABLE (DDL_OFF)
#define DDL_TMR6_ENABLE (DDL_OFF)
#define DDL_TMRA_ENABLE (DDL_OFF)
#define DDL_TRNG_ENABLE (DDL_OFF)
#define DDL_USART_ENABLE (DDL_ON)
#define DDL_USBFS_ENABLE (DDL_OFF)
#define DDL_USBHS_ENABLE (DDL_OFF)
#define DDL_WDT_ENABLE (DDL_OFF)
/* BSP on-off define */
#define BSP_ON (1U)
#define BSP_OFF (0U)
/**
* @brief The following is a list of currently supported BSP boards.
*/
#define BSP_EV_HC32F4A0_LQFP176 (1U)
#define BSP_MS_HC32F4A0_LQFP176_050_MEM (2U)
/**
* @brief The macro BSP_EV_HC32F4A0 is used to specify the BSP board currently
* in use.
* The value should be set to one of the list of currently supported BSP boards.
* @note If there is no supported BSP board or the BSP function is not used,
* the value needs to be set to BSP_EV_HC32F4A0.
*/
#define BSP_EV_HC32F4A0 (BSP_EV_HC32F4A0_LQFP176)
/**
* @brief This is the list of BSP components to be used.
* Select the components you need to use to BSP_ON.
*/
#define BSP_CY62167EV30LL_ENABLE (BSP_OFF)
#define BSP_IS42S16400J7TLI_ENABLE (BSP_OFF)
#define BSP_IS62WV51216_ENABLE (BSP_OFF)
#define BSP_MT29F2G08AB_ENABLE (BSP_OFF)
#define BSP_NT35510_ENABLE (BSP_OFF)
#define BSP_OV5640_ENABLE (BSP_OFF)
#define BSP_S29GL064N90TFI03_ENABLE (BSP_OFF)
#define BSP_TCA9539_ENABLE (BSP_OFF)
#define BSP_W25QXX_ENABLE (BSP_ON)
#define BSP_WM8731_ENABLE (BSP_OFF)
/**
* @brief Ethernet and PHY Configuration.
* @note PHY delay these values are based on a 1 ms Systick interrupt.
*/
/* MAC ADDRESS */
#define ETH_MAC_ADDR0 (2U)
#define ETH_MAC_ADDR1 (0U)
#define ETH_MAC_ADDR2 (0U)
#define ETH_MAC_ADDR3 (0U)
#define ETH_MAC_ADDR4 (0U)
#define ETH_MAC_ADDR5 (0U)
/* Ethernet driver buffers size and count */
#define ETH_TXBUF_SIZE (ETH_PACKET_MAX_SIZE) /* Buffer size for receive */
#define ETH_RXBUF_SIZE (ETH_PACKET_MAX_SIZE) /* Buffer size for transmit */
#define ETH_TXBUF_NUMBER (4UL) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_RXBUF_NUMBER (4UL) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* PHY Address*/
#define PHY_ADDRESS (0x00U) /* RTL8201F */
/* PHY Configuration delay */
#define PHY_HW_RESET_DELAY (0x0000003FUL)
#define PHY_RESET_DELAY (0x0000007FUL)
#define PHY_CONFIG_DELAY (0x0000003FUL)
#define PHY_READ_TIMEOUT (0x00000005UL)
#define PHY_WRITE_TIMEOUT (0x00000005UL)
/* Common PHY Registers */
#define PHY_BCR (0x00U) /*!< Basic Control Register */
#define PHY_BSR (0x01U) /*!< Basic Status Register */
#define PHY_SOFT_RESET (0x8000U) /*!< PHY Soft Reset */
#define PHY_LOOPBACK (0x4000U) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M (0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M (0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M (0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M (0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION (0x1000U) /*!< Enable auto-negotiation function */
#define PHY_POWERDOWN (0x0800U) /*!< Select the power down mode */
#define PHY_ISOLATE (0x0400U) /*!< Isolate PHY from MII */
#define PHY_RESTART_AUTONEGOTIATION (0x0200U) /*!< Restart auto-negotiation function */
#define PHY_100BASE_TX_FD (0x4000U) /*!< 100Base-TX full duplex support */
#define PHY_100BASE_TX_HD (0x2000U) /*!< 100Base-TX half duplex support */
#define PHY_10BASE_T_FD (0x1000U) /*!< 10Base-T full duplex support */
#define PHY_10BASE_T_HD (0x0800U) /*!< 10Base-T half duplex support */
#define PHY_AUTONEGO_COMPLETE (0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_LINK_STATUS (0x0004U) /*!< Valid link established */
#define PHY_JABBER_DETECTION (0x0002U) /*!< Jabber condition detected */
/**
* @brief External clock source for I2S peripheral
*/
#ifndef I2S_EXT_CLK_FREQ
#define I2S_EXT_CLK_FREQ (12288000UL) /*!< Value of the external oscillator */
#endif /* I2S_EXT_CLK_FREQ */
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* __DDL_CONFIG_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/****************************************************************************
* arch/arm/src/hc32/hc32_allocateheap.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <string.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/kmalloc.h>
#include <nuttx/userspace.h>
#include <arch/board/board.h>
#include "chip.h"
#include "mpu.h"
#include "arm_internal.h"
#include "hc32_mpuinit.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Internal SRAM is available in all members of the HC32 family. The
* following definitions must be provided to specify the size and
* location of internal(system) SRAM:
*
* CONFIG_RAM_END : End address (+1) of SRAM (F1 family only, the
* : F4 family uses the a priori end of SRAM)
*
* The F4 family also contains internal CCM SRAM. This SRAM is different
* because it cannot be used for DMA. So if DMA needed, then the following
* should be defined to exclude CCM SRAM from the heap:
*
* CONFIG_HC32_CCMEXCLUDE : Exclude CCM SRAM from the HEAP
*
* In addition to internal SRAM, external RAM may also be available through
* the FMC/FSMC. To use external RAM, the following things need to be present
* in the NuttX configuration file:
*
* CONFIG_HC32_FSMC=y : Enables the FSMC
* CONFIG_HC32_FMC=y : Enables the FMC
* CONFIG_HC32_EXTERNAL_RAM=y : Indicates external RAM is available via the
* FMC/FSMC (as opposed to an LCD or FLASH).
* CONFIG_HEAP2_BASE : The base address of the external RAM
* CONFIG_HEAP2_SIZE : The size of the external RAM
* CONFIG_MM_REGIONS : Must be set to a large enough value to
* include the external RAM (as determined by
* the rules provided below)
*/
#if !defined(CONFIG_HC32_FSMC) && !defined(CONFIG_HC32_FMC)
# undef CONFIG_HC32_EXTERNAL_RAM
#endif
//#if defined(CONFIG_HC32_HC32F4A0)
/* The HC32 F4A0 have no CCM SRAM */
# if defined(CONFIG_HC32_HC32F4A0)
# undef CONFIG_HC32_CCMEXCLUDE
# define CONFIG_HC32_CCMEXCLUDE 1
# endif
/* Set the end of system SRAM */
#define SRAM1_END 0x20073880
/* Set the range of CCM SRAM as well (although we may not use it) */
#define SRAM2_START 0x1FE00000
#define SRAM2_END 0x20073880
/* There are 4 possible SRAM configurations:
*
* Configuration 1. System SRAM (only)
* CONFIG_MM_REGIONS == 1
* CONFIG_HC32_EXTERNAL_RAM NOT defined
* CONFIG_HC32_CCMEXCLUDE defined
* Configuration 2. System SRAM and CCM SRAM
* CONFIG_MM_REGIONS == 2
* CONFIG_HC32_EXTERNAL_RAM NOT defined
* CONFIG_HC32_CCMEXCLUDE NOT defined
* Configuration 3. System SRAM and FSMC SRAM
* CONFIG_MM_REGIONS == 2
* CONFIG_HC32_EXTERNAL_RAM defined
* CONFIG_HC32_CCMEXCLUDE defined
* Configuration 4. System SRAM, CCM SRAM, and FSMC SRAM
* CONFIG_MM_REGIONS == 3
* CONFIG_HC32_EXTERNAL_RAM defined
* CONFIG_HC32_CCMEXCLUDE NOT defined
*
* Let's make sure that all definitions are consistent before doing
* anything else
*/
# if defined(CONFIG_HC32_EXTERNAL_RAM)
/* Configuration 3 or 4. External SRAM is available. CONFIG_MM_REGIONS
* should be at least 2.
*/
# if CONFIG_MM_REGIONS < 2
/* Only one memory region. Force Configuration 1 */
# warning "FSMC SRAM (and CCM SRAM) excluded from the heap"
# undef CONFIG_HC32_EXTERNAL_RAM
# undef CONFIG_HC32_CCMEXCLUDE
# define CONFIG_HC32_CCMEXCLUDE 1
/* CONFIG_MM_REGIONS may be 3 if CCM SRAM is included in the head */
# elif CONFIG_MM_REGIONS > 2
/* More than two memory regions. This is okay if CCM SRAM is not
* disabled.
*/
# if defined(CONFIG_HC32_CCMEXCLUDE)
/* Configuration 3: CONFIG_MM_REGIONS should have been 2 */
# error "CONFIG_MM_REGIONS > 2 but I don't know what some of the region(s) are"
# undef CONFIG_MM_REGIONS
# define CONFIG_MM_REGIONS 2
# else
/* Configuration 4: DMA should be disabled and CONFIG_MM_REGIONS
* should be 3.
*/
# ifdef CONFIG_ARCH_DMA
# warning "CCM SRAM is included in the heap AND DMA is enabled"
# endif
# if CONFIG_MM_REGIONS != 3
# error "CONFIG_MM_REGIONS > 3 but I don't know what some of the region(s) are"
# undef CONFIG_MM_REGIONS
# define CONFIG_MM_REGIONS 3
# endif
# endif
/* CONFIG_MM_REGIONS is exactly 2. We cannot support both CCM SRAM and
* FSMC SRAM.
*/
# elif !defined(CONFIG_HC32_CCMEXCLUDE)
# error "CONFIG_MM_REGIONS == 2, cannot support both CCM SRAM and FSMC SRAM"
# undef CONFIG_HC32_CCMEXCLUDE
# define CONFIG_HC32_CCMEXCLUDE 1
# endif
# elif !defined(CONFIG_HC32_CCMEXCLUDE)
/* Configuration 2: FSMC SRAM is not used, but CCM SRAM is requested.
* DMA should be disabled and CONFIG_MM_REGIONS should be 2.
*/
# ifdef CONFIG_ARCH_DMA
# warning "CCM SRAM is included in the heap AND DMA is enabled"
# endif
# if CONFIG_MM_REGIONS < 2
# ifdef CONFIG_HC32_HAVE_CCM
# error "CCM SRAM excluded from the heap because CONFIG_MM_REGIONS < 2"
# endif
# undef CONFIG_HC32_CCMEXCLUDE
# define CONFIG_HC32_CCMEXCLUDE 1
# elif CONFIG_MM_REGIONS > 2
# error "CONFIG_MM_REGIONS > 2 but I don't know what some of the region(s) are"
# undef CONFIG_MM_REGIONS
# define CONFIG_MM_REGIONS 2
# endif
# endif
/* There are 4 possible SRAM configurations:
*
* Configuration 1. System SRAM (only)
* CONFIG_MM_REGIONS == 1
* CONFIG_HC32_EXTERNAL_RAM NOT defined
* CONFIG_HC32_CCMEXCLUDE defined
* Configuration 2. System SRAM and CCM SRAM
* CONFIG_MM_REGIONS == 2
* CONFIG_HC32_EXTERNAL_RAM NOT defined
* CONFIG_HC32_CCMEXCLUDE NOT defined
* Configuration 3. System SRAM and FSMC SRAM
* CONFIG_MM_REGIONS == 2
* CONFIG_HC32_EXTERNAL_RAM defined
* CONFIG_HC32_CCMEXCLUDE defined
* Configuration 4. System SRAM, CCM SRAM, and FSMC SRAM
* CONFIG_MM_REGIONS == 3
* CONFIG_HC32_EXTERNAL_RAM defined
* CONFIG_HC32_CCMEXCLUDE NOT defined
*
* Let's make sure that all definitions are consistent before doing
* anything else
*/
# if defined(CONFIG_HC32_EXTERNAL_RAM)
# if (CONFIG_MM_REGIONS == 2)
/* OK: This is Configuration 3: SRAM and FSMC */
# elif (CONFIG_MM_REGIONS == 3)
/* OK: This is Configuration 3: SRAM, CCM, and FSMC */
# else
# error "Expected CONFIG_MM_REGIONS to be either 2 (SRAM + FSMC) or 3 (SRAM + CCM + FSMC)!"
# endif
# else
# if (CONFIG_MM_REGIONS == 1)
/* OK: Configuration 1: SRAM only. */
# elif (CONFIG_MM_REGIONS == 2)
/* OK: Configuration 2: SRAM and CCM SRAM. */
# else
# error "Expected CONFIG_MM_REGIONS to be either 1 (SRAM) or 2 (SRAM + CCM)!"
# endif
# endif
/* If FSMC SRAM is going to be used as heap, then verify that the starting
* address and size of the external SRAM region has been provided in the
* configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE).
*/
#ifdef CONFIG_HC32_EXTERNAL_RAM
# if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE)
# error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided"
# undef CONFIG_HC32_EXTERNAL_RAM
# endif
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_heap_color
*
* Description:
* Set heap memory to a known, non-zero state to checking heap usage.
*
****************************************************************************/
#ifdef CONFIG_HEAP_COLORATION
static inline void up_heap_color(FAR void *start, size_t size)
{
memset(start, HEAP_COLOR, size);
}
#else
# define up_heap_color(start,size)
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_heap
*
* Description:
* This function will be called to dynamically set aside the heap region.
*
* For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
* size of the unprotected, user-space heap.
*
* If a protected kernel-space heap is provided, the kernel heap must be
* allocated (and protected) by an analogous up_allocate_kheap().
*
* The following memory map is assumed for the flat build:
*
* .data region. Size determined at link time.
* .bss region Size determined at link time.
* IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
* Heap. Extends to the end of SRAM.
*
* The following memory map is assumed for the kernel build:
*
* Kernel .data region Size determined at link time
* Kernel .bss region Size determined at link time
* Kernel IDLE thread stack Size determined by
* CONFIG_IDLETHREAD_STACKSIZE
* Padding for alignment
* User .data region Size determined at link time
* User .bss region Size determined at link time
* Kernel heap Size determined by
* CONFIG_MM_KERNEL_HEAPSIZE
* User heap Extends to the end of SRAM
*
****************************************************************************/
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = SRAM1_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)SRAM1_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the SRAM1_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
usize = (1 << log2);
ubase = SRAM1_END - usize;
/* Return the user-space heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
/* Colorize the heap for debug */
up_heap_color((FAR void *)ubase, usize);
/* Allow user-mode access to the user heap memory */
hc32_mpu_uheap((uintptr_t)ubase, usize);
#else
/* Return the heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = SRAM1_END - g_idle_topstack;
/* Colorize the heap for debug */
up_heap_color(*heap_start, *heap_size);
#endif
}
/****************************************************************************
* Name: up_allocate_kheap
*
* Description:
* For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates
* (and protects) the kernel-space heap.
*
****************************************************************************/
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
{
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = SRAM1_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)SRAM1_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the SRAM1_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
usize = (1 << log2);
ubase = SRAM1_END - usize;
/* Return the kernel heap settings (i.e., the part of the heap region
* that was not dedicated to the user heap).
*/
*heap_start = (FAR void *)USERSPACE->us_bssend;
*heap_size = ubase - (uintptr_t)USERSPACE->us_bssend;
}
#endif
/****************************************************************************
* Name: arm_addregion
*
* Description:
* Memory may be added in non-contiguous chunks. Additional chunks are
* added by calling this function.
*
****************************************************************************/
#if CONFIG_MM_REGIONS > 1
void arm_addregion(void)
{
#ifndef CONFIG_HC32_CCMEXCLUDE
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the HC32F40xxx CCM SRAM heap */
hc32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START);
#endif
/* Colorize the heap for debug */
up_heap_color((FAR void *)SRAM2_START, SRAM2_END - SRAM2_START);
/* Add the HC32F40xxx CCM SRAM user heap region. */
kumm_addregion((FAR void *)SRAM2_START, SRAM2_END - SRAM2_START);
#endif
#ifdef CONFIG_HC32_EXTERNAL_RAM
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the FSMC SRAM user heap memory */
hc32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
#endif
/* Colorize the heap for debug */
up_heap_color((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
/* Add the external FSMC SRAM user heap region. */
kumm_addregion((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
#endif
}
#endif

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/**
*******************************************************************************
* @file hc32_common.h
* @brief This file contains the common part of the HC32 series.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
2020-09-07 Yangjp Add the precompiled configuration of ARM compiler V6
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_COMMON_H__
#define __HC32_COMMON_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include <stddef.h>
#include <string.h>
//configure the hc32 nuttx adapter
#define HC32F4A0 1
#define USE_DDL_DRIVER 1
#define getreg32(a) (*(volatile uint32_t *)(a))
#define putreg32(v,a) (*(volatile uint32_t *)(a) = (v))
#define getreg16(a) (*(volatile uint16_t *)(a))
#define putreg16(v,a) (*(volatile uint16_t *)(a) = (v))
extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */
extern uint32_t HRC_VALUE; /*!< HRC frequency */
/**
* @brief Clock setup macro definition
*/
#define CLOCK_SETTING_NONE 0U /*!< User provides own clock setting in application */
#define CLOCK_SETTING_CMSIS 1U
#define HRC_FREQ_MON() (*((volatile unsigned int*)(0x40010684UL)))
/**
* @addtogroup HC32F4A0_System_Clock_Source
* @{
*/
#if !defined (HRC_16MHz_VALUE)
#define HRC_16MHz_VALUE ((uint32_t)16000000UL) /*!< Internal high speed RC freq.(16MHz) */
#endif
#if !defined (HRC_20MHz_VALUE)
#define HRC_20MHz_VALUE ((uint32_t)20000000UL) /*!< Internal high speed RC freq.(20MHz) */
#endif
#if !defined (MRC_VALUE)
#define MRC_VALUE ((uint32_t)8000000UL) /*!< Internal middle speed RC freq.(8MHz) */
#endif
#if !defined (LRC_VALUE)
#define LRC_VALUE ((uint32_t)32768UL) /*!< Internal low speed RC freq.(32.768KHz) */
#endif
#if !defined (RTCLRC_VALUE)
#define RTCLRC_VALUE ((uint32_t)32768UL) /*!< Internal RTC low speed RC freq.(32.768KHz) */
#endif
#if !defined (SWDTLRC_VALUE)
#define SWDTLRC_VALUE ((uint32_t)10000UL) /*!< External low speed OSC freq.(10KHz) */
#endif
#if !defined (XTAL_VALUE)
#define XTAL_VALUE ((uint32_t)8000000UL) /*!< External high speed OSC freq.(8MHz) */
#endif
#if !defined (XTAL32_VALUE)
#define XTAL32_VALUE ((uint32_t)32768UL) /*!< External low speed OSC freq.(32.768KHz) */
#endif
#if !defined (HCLK_VALUE)
extern uint32_t SystemCoreClock;
#define HCLK_VALUE (SystemCoreClock >> ((M4_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS))
#endif
#define HC32_SYSCLK_FREQUENCY SystemCoreClock
#define HC32_HCLK_FREQUENCY HCLK_VALUE
/**
* @addtogroup CMSIS
* @{
*/
/**
* @addtogroup HC32_Common_Part
* @{
*/
/**
* @brief HC32 Common Device Include
*/
#include "hc32f4a0.h"
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup HC32_Common_Global_Types HC32 Common Global Types
* @{
*/
/**
* @brief Single precision floating point number (4 byte)
*/
typedef float float32_t;
/**
* @brief Double precision floating point number (8 byte)
*/
typedef double float64_t;
/**
* @brief Function pointer type to void/void function
*/
typedef void (*func_ptr_t)(void);
/**
* @brief Function pointer type to void/uint8_t function
*/
typedef void (*func_ptr_arg1_t)(uint8_t);
/**
* @brief Functional state
*/
typedef enum
{
Disable = 0U,
Enable = 1U,
} en_functional_state_t;
/* Check if it is a functional state */
#define IS_FUNCTIONAL_STATE(state) (((state) == Disable) || ((state) == Enable))
/**
* @brief Flag status
*/
typedef enum
{
Reset = 0U,
Set = 1U,
} en_flag_status_t, en_int_status_t;
/**
* @brief Generic error codes
*/
typedef enum
{
Ok = 0U, /*!< No error */
Error = 1U, /*!< Non-specific error code */
ErrorAddressAlignment = 2U, /*!< Address alignment does not match */
ErrorAccessRights = 3U, /*!< Wrong mode (e.g. user/system) mode is set */
ErrorInvalidParameter = 4U, /*!< Provided parameter is not valid */
ErrorOperationInProgress = 5U, /*!< A conflicting or requested operation is still in progress */
ErrorInvalidMode = 6U, /*!< Operation not allowed in current mode */
ErrorUninitialized = 7U, /*!< Module (or part of it) was not initialized properly */
ErrorBufferEmpty = 8U, /*!< Circular buffer can not be read because the buffer is empty */
ErrorBufferFull = 9U, /*!< Circular buffer can not be written because the buffer is full */
ErrorTimeout = 10U, /*!< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) */
ErrorNotReady = 11U, /*!< A requested final state is not reached */
OperationInProgress = 12U, /*!< Indicator for operation in progress (e.g. ADC conversion not finished, DMA channel used, etc.) */
} en_result_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup HC32_Common_Global_Macros HC32 Common Global Macros
* @{
*/
/**
* @brief Compiler Macro Definitions
*/
#ifndef __UNUSED
#define __UNUSED __attribute__((unused))
#endif /* __UNUSED */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#ifndef __WEAKDEF
#define __WEAKDEF __attribute__((weak))
#endif /* __WEAKDEF */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN __attribute__((aligned(4)))
#endif /* __ALIGN_BEGIN */
#ifndef __NOINLINE
#define __NOINLINE __attribute__((noinline))
#endif /* __NOINLINE */
#ifndef __RAM_FUNC
#define __RAM_FUNC __attribute__((long_call, section(".ramfunc")))
/* Usage: void __RAM_FUNC foo(void) */
#endif /* __RAM_FUNC */
#ifndef __NO_INIT
#define __NO_INIT
#endif /* __NO_INIT */
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /*!< GNU Compiler */
#ifndef __WEAKDEF
#define __WEAKDEF __attribute__((weak))
#endif /* __WEAKDEF */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN __attribute__((aligned (4)))
#endif /* __ALIGN_BEGIN */
#ifndef __NOINLINE
#define __NOINLINE __attribute__((noinline))
#endif /* __NOINLINE */
#ifndef __RAM_FUNC
#define __RAM_FUNC __attribute__((long_call, section(".ramfunc")))
/* Usage: void __RAM_FUNC foo(void) */
#endif /* __RAM_FUNC */
#ifndef __NO_INIT
#define __NO_INIT __attribute__((section(".noinit")))
#endif /* __NO_INIT */
#elif defined (__ICCARM__) /*!< IAR Compiler */
#ifndef __WEAKDEF
#define __WEAKDEF __weak
#endif /* __WEAKDEF */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN _Pragma("data_alignment=4")
#endif /* __ALIGN_BEGIN */
#ifndef __NOINLINE
#define __NOINLINE _Pragma("optimize = no_inline")
#endif /* __NOINLINE */
#ifndef __RAM_FUNC
#define __RAM_FUNC __ramfunc
#endif /* __RAM_FUNC */
#ifndef __NO_INIT
#define __NO_INIT __no_init
#endif /* __NO_INIT */
#elif defined (__CC_ARM) /*!< ARM Compiler */
#ifndef __WEAKDEF
#define __WEAKDEF __attribute__((weak))
#endif /* __WEAKDEF */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN __align(4)
#endif /* __ALIGN_BEGIN */
#ifndef __NOINLINE
#define __NOINLINE __attribute__((noinline))
#endif /* __NOINLINE */
#ifndef __NO_INIT
#define __NO_INIT
#endif /* __NO_INIT */
/* RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM. */
#define __RAM_FUNC
#else
#error "unsupported compiler!!"
#endif
/**
* @defgroup Extend_Macro_Definitions Extend Macro Definitions
* @{
*/
/* Decimal to BCD */
#define DEC2BCD(x) ((((x) / 10U) << 4U) + ((x) % 10U))
/* BCD to decimal */
#define BCD2DEC(x) ((((x) >> 4U) * 10U) + ((x) & 0x0FU))
/* Returns the minimum value out of two values */
#define MIN(x, y) ((x) < (y) ? (x) : (y))
/* Returns the maximum value out of two values */
#define MAX(x, y) ((x) > (y) ? (x) : (y))
/* Returns the dimension of an array */
#define ARRAY_SZ(x) ((sizeof(x)) / (sizeof((x)[0])))
/**
* @}
*/
/**
* @defgroup Address_Align Address Align
* @{
*/
#define IS_ADDRESS_ALIGN(addr, align) (0UL == (((uint32_t)(addr)) & (((uint32_t)(align)) - 1UL)))
#define IS_ADDRESS_ALIGN_HALFWORD(addr) (0UL == (((uint32_t)(addr)) & 0x1UL))
#define IS_ADDRESS_ALIGN_WORD(addr) (0UL == (((uint32_t)(addr)) & 0x3UL))
/**
* @}
*/
/**
* @defgroup Register_Macro_Definitions Register Macro Definitions
* @{
*/
#define RW_MEM8(addr) (*(volatile uint8_t *)(addr))
#define RW_MEM16(addr) (*(volatile uint16_t *)(addr))
#define RW_MEM32(addr) (*(volatile uint32_t *)(addr))
#define SET_REG8_BIT(REG, BIT) ((REG) |= ((uint8_t)(BIT)))
#define SET_REG16_BIT(REG, BIT) ((REG) |= ((uint16_t)(BIT)))
#define SET_REG32_BIT(REG, BIT) ((REG) |= ((uint32_t)(BIT)))
#define CLEAR_REG8_BIT(REG, BIT) ((REG) &= ((uint8_t)(~((uint8_t)(BIT)))))
#define CLEAR_REG16_BIT(REG, BIT) ((REG) &= ((uint16_t)(~((uint16_t)(BIT)))))
#define CLEAR_REG32_BIT(REG, BIT) ((REG) &= ((uint32_t)(~((uint32_t)(BIT)))))
#define READ_REG8_BIT(REG, BIT) ((REG) & ((uint8_t)(BIT)))
#define READ_REG16_BIT(REG, BIT) ((REG) & ((uint16_t)(BIT)))
#define READ_REG32_BIT(REG, BIT) ((REG) & ((uint32_t)(BIT)))
#define CLEAR_REG8(REG) ((REG) = ((uint8_t)(0U)))
#define CLEAR_REG16(REG) ((REG) = ((uint16_t)(0U)))
#define CLEAR_REG32(REG) ((REG) = ((uint32_t)(0UL)))
#define WRITE_REG8(REG, VAL) ((REG) = ((uint8_t)(VAL)))
#define WRITE_REG16(REG, VAL) ((REG) = ((uint16_t)(VAL)))
#define WRITE_REG32(REG, VAL) ((REG) = ((uint32_t)(VAL)))
#define READ_REG8(REG) (REG)
#define READ_REG16(REG) (REG)
#define READ_REG32(REG) (REG)
#define MODIFY_REG8(REGS, CLEARMASK, SETMASK) (WRITE_REG8((REGS), (((READ_REG8((REGS))) & ((uint8_t)(~((uint8_t)(CLEARMASK))))) | ((uint8_t)(SETMASK) & (uint8_t)(CLEARMASK)))))
#define MODIFY_REG16(REGS, CLEARMASK, SETMASK) (WRITE_REG16((REGS), (((READ_REG16((REGS))) & ((uint16_t)(~((uint16_t)(CLEARMASK))))) | ((uint16_t)(SETMASK) & (uint16_t)(CLEARMASK)))))
#define MODIFY_REG32(REGS, CLEARMASK, SETMASK) (WRITE_REG32((REGS), (((READ_REG32((REGS))) & ((uint32_t)(~((uint32_t)(CLEARMASK))))) | ((uint32_t)(SETMASK) & (uint32_t)(CLEARMASK)))))
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_COMMON_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/**
*******************************************************************************
* @file hc32_ddl.h
* @brief This file contains HC32 Series Device Driver Library file call
* management.
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Yangjp First version
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32_DDL_H__
#define __HC32_DDL_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/* Defined use Device Driver Library */
#if !defined (USE_DDL_DRIVER)
/**
* @brief Comment the line below if you will not use the Device Driver Library.
* In this case, the application code will be based on direct access to
* peripherals registers.
*/
/* #define USE_DDL_DRIVER */
#endif /* USE_DDL_DRIVER */
/**
* @brief HC32 Series Device Driver Library version number
*/
#define HC32_DDL_VERSION_MAIN 0x01U /*!< [31:24] main version */
#define HC32_DDL_VERSION_SUB1 0x04U /*!< [23:16] sub1 version */
#define HC32_DDL_VERSION_SUB2 0x00U /*!< [15:8] sub2 version */
#define HC32_DDL_VERSION_RC 0x00U /*!< [7:0] release candidate */
#define HC32_DDL_VERSION ((HC32_DDL_VERSION_MAIN << 24) | \
(HC32_DDL_VERSION_SUB1 << 16) | \
(HC32_DDL_VERSION_SUB2 << 8 ) | \
(HC32_DDL_VERSION_RC))
/* Use Device Driver Library */
#if defined (USE_DDL_DRIVER)
/**
* @brief Include peripheral module's header file
*/
#if (DDL_ADC_ENABLE == DDL_ON)
#include "hc32f4a0_adc.h"
#endif /* DDL_ADC_ENABLE */
#if (DDL_AES_ENABLE == DDL_ON)
#include "hc32f4a0_aes.h"
#endif /* DDL_AES_ENABLE */
#if (DDL_CAN_ENABLE == DDL_ON)
#include "hc32f4a0_can.h"
#endif /* DDL_CAN_ENABLE */
#if (DDL_CLK_ENABLE == DDL_ON)
#include "hc32f4a0_clk.h"
#endif /* DDL_CLK_ENABLE */
#if (DDL_CMP_ENABLE == DDL_ON)
#include "hc32f4a0_cmp.h"
#endif /* DDL_CMP_ENABLE */
#if (DDL_CRC_ENABLE == DDL_ON)
#include "hc32f4a0_crc.h"
#endif /* DDL_CRC_ENABLE */
#if (DDL_CTC_ENABLE == DDL_ON)
#include "hc32f4a0_ctc.h"
#endif /* DDL_CTC_ENABLE */
#if (DDL_DAC_ENABLE == DDL_ON)
#include "hc32f4a0_dac.h"
#endif /* DDL_DAC_ENABLE */
#if (DDL_DCU_ENABLE == DDL_ON)
#include "hc32f4a0_dcu.h"
#endif /* DDL_DCU_ENABLE */
#if (DDL_DMA_ENABLE == DDL_ON)
#include "hc32f4a0_dma.h"
#endif /* DDL_DMA_ENABLE */
#if (DDL_DMC_ENABLE == DDL_ON)
#include "hc32f4a0_dmc.h"
#endif /* DDL_DMC_ENABLE */
#if (DDL_DVP_ENABLE == DDL_ON)
#include "hc32f4a0_dvp.h"
#endif /* DDL_DVP_ENABLE */
#if (DDL_EFM_ENABLE == DDL_ON)
#include "hc32f4a0_efm.h"
#endif /* DDL_EFM_ENABLE */
#if (DDL_EMB_ENABLE == DDL_ON)
#include "hc32f4a0_emb.h"
#endif /* DDL_EMB_ENABLE */
#if (DDL_ETH_ENABLE == DDL_ON)
#include "hc32f4a0_eth.h"
#endif /* DDL_ETH_ENABLE */
#if (DDL_EVENT_PORT_ENABLE == DDL_ON)
#include "hc32f4a0_event_port.h"
#endif /* DDL_EVENT_PORT_ENABLE */
#if (DDL_FCM_ENABLE == DDL_ON)
#include "hc32f4a0_fcm.h"
#endif /* DDL_FCM_ENABLE */
#if (DDL_FMAC_ENABLE == DDL_ON)
#include "hc32f4a0_fmac.h"
#endif /* DDL_FMAC_ENABLE */
#if (DDL_GPIO_ENABLE == DDL_ON)
#include "hc32f4a0_gpio.h"
#endif /* DDL_GPIO_ENABLE */
#if (DDL_HASH_ENABLE == DDL_ON)
#include "hc32f4a0_hash.h"
#endif /* DDL_HASH_ENABLE */
#if (DDL_I2C_ENABLE == DDL_ON)
#include "hc32f4a0_i2c.h"
#endif /* DDL_I2C_ENABLE */
#if (DDL_I2S_ENABLE == DDL_ON)
#include "hc32f4a0_i2s.h"
#endif /* DDL_I2S_ENABLE */
#if (DDL_ICG_ENABLE == DDL_ON)
#include "hc32f4a0_icg.h"
#endif /* DDL_ICG_ENABLE */
#if (DDL_INTERRUPTS_ENABLE == DDL_ON)
#include "hc32f4a0_interrupts.h"
#endif /* DDL_INTERRUPTS_ENABLE */
#if (DDL_KEYSCAN_ENABLE == DDL_ON)
#include "hc32f4a0_keyscan.h"
#endif /* DDL_KEYSCAN_ENABLE */
#if (DDL_MAU_ENABLE == DDL_ON)
#include "hc32f4a0_mau.h"
#endif /* DDL_MAU_ENABLE */
#if (DDL_MPU_ENABLE == DDL_ON)
#include "hc32f4a0_mpu.h"
#endif /* DDL_MPU_ENABLE */
#if (DDL_NFC_ENABLE == DDL_ON)
#include "hc32f4a0_nfc.h"
#endif /* DDL_NFC_ENABLE */
#if (DDL_OTS_ENABLE == DDL_ON)
#include "hc32f4a0_ots.h"
#endif /* DDL_OTS_ENABLE */
#if (DDL_PWC_ENABLE == DDL_ON)
#include "hc32f4a0_pwc.h"
#endif /* DDL_PWC_ENABLE */
#if (DDL_QSPI_ENABLE == DDL_ON)
#include "hc32f4a0_qspi.h"
#endif /* DDL_QSPI_ENABLE */
#if (DDL_RMU_ENABLE == DDL_ON)
#include "hc32f4a0_rmu.h"
#endif /* DDL_RMU_ENABLE */
#if (DDL_RTC_ENABLE == DDL_ON)
#include "hc32f4a0_rtc.h"
#endif /* DDL_RTC_ENABLE */
#if (DDL_SDIOC_ENABLE == DDL_ON)
#include "hc32f4a0_sdioc.h"
#endif /* DDL_SDIOC_ENABLE */
#if (DDL_SMC_ENABLE == DDL_ON)
#include "hc32f4a0_smc.h"
#endif /* DDL_SMC_ENABLE */
#if (DDL_SPI_ENABLE == DDL_ON)
#include "hc32f4a0_spi.h"
#endif /* DDL_SPI_ENABLE */
#if (DDL_SRAM_ENABLE == DDL_ON)
#include "hc32f4a0_sram.h"
#endif /* DDL_SRAM_ENABLE */
#if (DDL_SWDT_ENABLE == DDL_ON)
#include "hc32f4a0_swdt.h"
#endif /* DDL_SWDT_ENABLE */
#if (DDL_TMR0_ENABLE == DDL_ON)
#include "hc32f4a0_tmr0.h"
#endif /* DDL_TMR0_ENABLE */
#if (DDL_TMR2_ENABLE == DDL_ON)
#include "hc32f4a0_tmr2.h"
#endif /* DDL_TMR2_ENABLE */
#if (DDL_TMR4_ENABLE == DDL_ON)
#include "hc32f4a0_tmr4.h"
#endif /* DDL_TMR4_ENABLE */
#if (DDL_TMR6_ENABLE == DDL_ON)
#include "hc32f4a0_tmr6.h"
#endif /* DDL_TMR6_ENABLE */
#if (DDL_TMRA_ENABLE == DDL_ON)
#include "hc32f4a0_tmra.h"
#endif /* DDL_TMRA_ENABLE */
#if (DDL_TRNG_ENABLE == DDL_ON)
#include "hc32f4a0_trng.h"
#endif /* DDL_TRNG_ENABLE */
#if (DDL_USART_ENABLE == DDL_ON)
#include "hc32f4a0_usart.h"
#endif /* DDL_USART_ENABLE */
#if (DDL_USBFS_ENABLE == DDL_ON)
#include "hc32f4a0_usbfs.h"
#endif /* DDL_USBFS_ENABLE */
#if (DDL_USBHS_ENABLE == DDL_ON)
#include "hc32f4a0_usbhs.h"
#endif /* DDL_USBHS_ENABLE */
#if (DDL_UTILITY_ENABLE == DDL_ON)
#include "hc32f4a0_utility.h"
#endif /* DDL_UTILITY_ENABLE */
#if (DDL_WDT_ENABLE == DDL_ON)
#include "hc32f4a0_wdt.h"
#endif /* DDL_WDT_ENABLE */
#if (DDL_HRPWM_ENABLE == DDL_ON)
#include "hc32f4a0_hrpwm.h"
#endif /* DDL_HRPWM_ENABLE */
/**
* @brief Include BSP board's header file
*/
/**
* @brief Include BSP device component's header file
*/
#if (BSP_CY62167EV30LL_ENABLE == BSP_ON)
#include "cy62167ev30ll.h"
#endif /* BSP_CY62167EV30LL_ENABLE */
#if (BSP_IS42S16400J7TLI_ENABLE == BSP_ON)
#include "is42s16400j7tli.h"
#endif /* BSP_IS42S16400J7TLI_ENABLE */
#if (BSP_IS62WV51216_ENABLE == BSP_ON)
#include "is62wv51216.h"
#endif /* BSP_IS62WV51216_ENABLE */
#if (BSP_MT29F2G08AB_ENABLE == BSP_ON)
#include "mt29f2g08ab.h"
#endif /* BSP_MT29F2G08AB_ENABLE */
#if (BSP_NT35510_ENABLE == BSP_ON)
#include "nt35510.h"
#endif /* BSP_NT35510_ENABLE */
#if (BSP_OV5640_ENABLE == BSP_ON)
#include "ov5640.h"
#endif /* BSP_OV5640_ENABLE */
#if (BSP_S29GL064N90TFI03_ENABLE == BSP_ON)
#include "s29gl064n90tfi03.h"
#endif /* BSP_S29GL064N90TFI03_ENABLE */
//#if (BSP_TCA9539_ENABLE == BSP_ON)
// #include "ev_hc32f4a0_lqfp176_tca9539.h"
// #include "tca9539.h"
//#endif /* BSP_TCA9539_ENABLE */
#if (BSP_W25QXX_ENABLE == BSP_ON)
#include "w25qxx.h"
#endif /* BSP_W25QXX_ENABLE */
#if (BSP_WM8731_ENABLE == BSP_ON)
#include "wm8731.h"
#endif /* BSP_WM8731_ENABLE */
#endif /* USE_DDL_DRIVER */
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* __HC32_DDL_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/****************************************************************************
* arch/arm/src/hc32/hc32_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include "arm_internal.h"
#include "chip.h"
#include <arch/board/board.h>
#include "hc32_gpio.h"
#include "hc32f4a0_gpio.h"
#include "hc32f4a0_utility.h"
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
void hc32_gpio_flick(void)
{
uint32_t pinset = (GPIO_PINSET(LED_GREEN_PORT, LED_GREEN_PIN) | GPIO_OUTPUT_SET);
hc32_configgpio(pinset);
for(int i = 0; i < 3; i++)
{
hc32_gpiowrite(pinset, true);
DDL_DelayMS(200UL);
hc32_gpiowrite(pinset, false);
DDL_DelayMS(200UL);
}
}
/****************************************************************************
* Function: hc32_gpioremap
*
* Description:
*
* Based on configuration within the .config file, this function will
* remaps positions of alternative functions.
*
****************************************************************************/
static inline void hc32_gpioremap(void)
{
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: hc32_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from hc32_start().
*
* Assumptions:
* This function is called early in the initialization sequence so that
* no mutual exclusion is necessary.
*
****************************************************************************/
void hc32_gpioinit(void)
{
/* Remap according to the configuration within .config file */
hc32_gpioremap();
hc32_gpio_flick();
}
/****************************************************************************
* Name: hc32_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with hc32_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
* Returned Value:
* OK on success
* A negated errno value on invalid port, or when pin is locked as ALT
* function.
*
* To-Do: Auto Power Enable
****************************************************************************/
/****************************************************************************
* Name: hc32_configgpio (for the HC32F10xxx family)
****************************************************************************/
int hc32_configgpio(uint32_t cfgset)
{
unsigned int port;
unsigned int pin;
irqstate_t flags;
stc_gpio_init_t stcGpioInit;
/* Verify that this hardware supports the select GPIO port */
port = (cfgset >> GPIO_PORT_SHIFT) & GPIO_PORT_MASK;
if (port > GPIO_PORT_MASK)
{
return -EINVAL;
}
/* Get the pin number and select the port configuration register for that pin */
pin = (cfgset >> GPIO_PIN_SHIFT) & GPIO_PIN_MASK;
/* Interrupts must be disabled from here on out so that we have mutually
* exclusive access to all of the GPIO configuration registers.
*/
flags = enter_critical_section();
/* If it is an output... set the pin to the correct initial state.
* If it is pull-down or pull up, then we need to set the ODR
* appropriately for that function.
*/
GPIO_Unlock();
/* LED initialize */
(void)GPIO_StructInit(&stcGpioInit);
(void)GPIO_Init(port, pin, &stcGpioInit);
GPIO_Lock();
/* Register write protected for some required peripherals. */
if ((cfgset & GPIO_OUTPUT_SET) != 0)
{
/* "Turn off" LED before set to output */
GPIO_ResetPins(port, pin);
GPIO_OE(port, pin, Enable);
}
else
{
GPIO_OE(port, pin, Disable);
}
leave_critical_section(flags);
return OK;
}
/****************************************************************************
* Name: hc32_unconfiggpio
*
* Description:
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
* it into default HiZ state (and possibly mark it's unused) and unlock it
* whether it was previously selected as an alternative function
* (GPIO_ALT | GPIO_CNF_AFPP | ...).
*
* This is a safety function and prevents hardware from shocks, as
* unexpected write to the Timer Channel Output GPIO to fixed '1' or '0'
* while it should operate in PWM mode could produce excessive on-board
* currents and trigger over-current/alarm function.
*
* Returned Value:
* OK on success
* A negated errno value on invalid port
*
* To-Do: Auto Power Disable
****************************************************************************/
int hc32_unconfiggpio(uint32_t cfgset)
{
/* Reuse port and pin number and set it to default HiZ INPUT */
cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK;
cfgset |= GPIO_INPUT;
return hc32_configgpio(cfgset);
}
/****************************************************************************
* Name: hc32_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void hc32_gpiowrite(uint32_t pinset, bool value)
{
unsigned int port;
unsigned int pin;
port = (pinset >> GPIO_PORT_SHIFT) & GPIO_PORT_MASK;
if (port < GPIO_PORT_MASK)
{
/* Get the pin number */
pin = (pinset >> GPIO_PIN_SHIFT) & GPIO_PIN_MASK;
/* Set or clear the output on the pin */
if (value)
{
GPIO_SetPins(port, pin);
}
else
{
GPIO_ResetPins(port, pin);
}
}
}
/****************************************************************************
* Name: hc32_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool hc32_gpioread(uint32_t pinset)
{
unsigned int port;
unsigned int pin;
port = (pinset >> GPIO_PORT_SHIFT) & GPIO_PORT_MASK;
if (port < GPIO_PORT_MASK)
{
/* Get the pin number and return the input state of that pin */
pin = (pinset >> GPIO_PIN_SHIFT) & GPIO_PIN_MASK;
return (GPIO_ReadInputPins(port, pin) == Pin_Set);
}
return 0;
}
/****************************************************************************
* Name: hc32_iocompensation
*
* Description:
* Enable I/O compensation.
*
* By default the I/O compensation cell is not used. However when the I/O
* output buffer speed is configured in 50 MHz or 100 MHz mode, it is
* recommended to use the compensation cell for slew rate control on I/O
* tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power
* supply.
*
* The I/O compensation cell can be used only when the supply voltage
* ranges from 2.4 to 3.6 V.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_HC32_HAVE_IOCOMPENSATION
void hc32_iocompensation(void)
{
#ifdef HC32_SYSCFG_CMPCR
/* Enable I/O Compensation. Writing '1' to the CMPCR power-down bit
* enables the I/O compensation cell.
*/
#endif
}
#endif

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/****************************************************************************
* arch/arm/src/hc32/hc32_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_HC32_HC32_GPIO_H
#define __ARCH_ARM_SRC_HC32_HC32_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
# include <stdbool.h>
#endif
#include <nuttx/irq.h>
#include "chip.h"
/****************************************************************************
* Pre-Processor Declarations
****************************************************************************/
#define GPIO_OUTPUT_SET (1 << 25) /* Bit 8: If output, initial value of output */
#define GPIO_OUTPUT_CLEAR (0)
#define GPIO_MODE_SHIFT (18) /* Bits 18-19: GPIO port mode */
#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode */
# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* General purpose output mode */
# define GPIO_ALT (2 << GPIO_MODE_SHIFT) /* Alternate function mode */
# define GPIO_ANALOG (3 << GPIO_MODE_SHIFT) /* Analog mode */
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: hc32_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with hc32_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
* Returned Value:
* OK on success
* ERROR on invalid port, or when pin is locked as ALT function.
*
****************************************************************************/
int hc32_configgpio(uint32_t cfgset);
/****************************************************************************
* Name: hc32_unconfiggpio
*
* Description:
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
* it into default HiZ state (and possibly mark it's unused) and unlock it
* whether it was previously selected as alternative function
* (GPIO_ALT|GPIO_CNF_AFPP|...).
*
* This is a safety function and prevents hardware from shocks, as
* unexpected write to the Timer Channel Output GPIO to fixed '1' or '0'
* while it should operate in PWM mode could produce excessive on-board
* currents and trigger over-current/alarm function.
*
* Returned Value:
* OK on success
* ERROR on invalid port
*
****************************************************************************/
int hc32_unconfiggpio(uint32_t cfgset);
/****************************************************************************
* Name: hc32_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void hc32_gpiowrite(uint32_t pinset, bool value);
/****************************************************************************
* Name: hc32_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool hc32_gpioread(uint32_t pinset);
/****************************************************************************
* Name: hc32_iocompensation
*
* Description:
* Enable I/O compensation.
*
* By default the I/O compensation cell is not used. However when the I/O
* output buffer speed is configured in 50 MHz or 100 MHz mode, it is
* recommended to use the compensation cell for slew rate control on I/O
* tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power
* supply.
*
* The I/O compensation cell can be used only when the supply voltage
* ranges from 2.4 to 3.6 V.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_HC32_HAVE_IOCOMPENSATION
void hc32_iocompensation(void);
#endif
/****************************************************************************
* Function: hc32_dumpgpio
*
* Description:
* Dump all GPIO registers associated with the provided base address
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
int hc32_dumpgpio(uint32_t pinset, const char *msg);
#else
# define hc32_dumpgpio(p,m)
#endif
/****************************************************************************
* Function: hc32_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from hc32_start().
*
****************************************************************************/
void hc32_gpioinit(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_HC32_HC32_GPIO_H */

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/****************************************************************************
* arch/arm/src/hc32/hc32_idle.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/board/board.h>
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/power/pm.h>
#include <nuttx/irq.h>
#include "chip.h"
#include "hc32_pm.h"
#include "arm_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Does the board support an IDLE LED to indicate that the board is in the
* IDLE state?
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
#endif
#define PM_IDLE_DOMAIN 0 /* Revisit */
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_idlepm
*
* Description:
* Perform IDLE state power management.
*
****************************************************************************/
#ifdef CONFIG_PM
static void up_idlepm(void)
{
static enum pm_state_e oldstate = PM_NORMAL;
enum pm_state_e newstate;
irqstate_t flags;
int ret;
/* Decide, which power saving level can be obtained */
newstate = pm_checkstate(PM_IDLE_DOMAIN);
/* Check for state changes */
if (newstate != oldstate)
{
flags = enter_critical_section();
/* Perform board-specific, state-dependent logic here */
_info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
ret = pm_changestate(PM_IDLE_DOMAIN, newstate);
if (ret < 0)
{
/* The new state change failed, revert to the preceding state */
pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
/* Save the new state */
oldstate = newstate;
}
/* MCU-specific power management logic */
switch (newstate)
{
case PM_NORMAL:
break;
case PM_IDLE:
break;
case PM_STANDBY:
// hc32_pmstop(true);
break;
case PM_SLEEP:
// hc32_pmstandby();
break;
default:
break;
}
leave_critical_section(flags);
}
}
#else
# define up_idlepm()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when there is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
nxsched_process_timer();
#else
/* Perform IDLE mode power management */
up_idlepm();
/* Sleep until an interrupt occurs to save power.
*
* NOTE: There is an HC32F107 errata that is fixed by the following
* workaround:
*
* "2.17.11 Ethernet DMA not working after WFI/WFE instruction
* Description
* If a WFI/WFE instruction is executed to put the system in sleep mode
* while the Ethernet MAC master clock on the AHB bus matrix is ON and
* all remaining masters clocks are OFF, the Ethernet DMA will be not
* able to perform any AHB master accesses during sleep mode."
*
* Workaround
* Enable DMA1 or DMA2 clocks in the RCC_AHBENR register before
* executing the WFI/WFE instruction."
*
* Here the workaround is just to avoid SLEEP mode for the connectivity
* line parts if Ethernet is enabled. The errate recommends a more
* general solution: Enabling DMA1/2 clocking in hc32f10xx_rcc.c if the
* HC32107 Ethernet peripheral is enabled.
*/
#if !defined(CONFIG_HC32_CONNECTIVITYLINE) || !defined(CONFIG_HC32_ETHMAC)
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_HC32_DISABLE_IDLE_SLEEP_DURING_DEBUG))
BEGIN_IDLE();
asm("WFI");
END_IDLE();
#endif
#endif
#endif
}

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/****************************************************************************
* arch/arm/src/hc32/hc32_irq.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <inttypes.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv7-m/nvicpri.h>
#include "nvic.h"
#ifdef CONFIG_ARCH_RAMVECTORS
# include "ram_vectors.h"
#endif
#include "arm_internal.h"
#include "hc32f4a0.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Get a 32-bit version of the default priority */
#define DEFPRIORITY32 \
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | \
NVIC_SYSH_PRIORITY_DEFAULT)
/* Given the address of a NVIC ENABLE register, this is the offset to
* the corresponding CLEAR ENABLE register.
*/
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Public Data
****************************************************************************/
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
volatile uint32_t *g_current_regs[1];
/* This is the address of the exception vector table (determined by the
* linker script).
*/
#if defined(__ICCARM__)
/* _vectors replaced on __vector_table for IAR C-SPY Simulator */
extern uint32_t __vector_table[];
#else
extern uint32_t _vectors[];
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: hc32_dumpnvic
*
* Description:
* Dump some interesting NVIC registers
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void hc32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x "
"SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA),
getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA),
getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE),
getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY),
getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY),
getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY),
getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY),
getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY),
getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY),
getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY),
getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY),
getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY),
getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
leave_critical_section(flags);
}
#else
# define hc32_dumpnvic(msg, irq)
#endif
/****************************************************************************
* Name: hc32_nmi, hc32_busfault, hc32_usagefault, hc32_pendsv,
* hc32_dbgmonitor, hc32_pendsv, hc32_reserved
*
* Description:
* Handlers for various exceptions. None are handled and all are fatal
* error conditions. The only advantage these provided over the default
* unexpected interrupt handler is that they provide a diagnostic output.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
static int hc32_nmi(int irq, FAR void *context, FAR void *arg)
{
up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
static int hc32_busfault(int irq, FAR void *context, FAR void *arg)
{
up_irq_save();
_err("PANIC!!! Bus fault received: %08" PRIx32 "\n",
getreg32(NVIC_CFAULTS));
PANIC();
return 0;
}
static int hc32_usagefault(int irq, FAR void *context, FAR void *arg)
{
up_irq_save();
_err("PANIC!!! Usage fault received: %08" PRIx32 "\n",
getreg32(NVIC_CFAULTS));
PANIC();
return 0;
}
static int hc32_pendsv(int irq, FAR void *context, FAR void *arg)
{
up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
static int hc32_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
}
static int hc32_reserved(int irq, FAR void *context, FAR void *arg)
{
up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
#endif
/****************************************************************************
* Name: hc32_prioritize_syscall
*
* Description:
* Set the priority of an exception. This function may be needed
* internally even if support for prioritized interrupts is not enabled.
*
****************************************************************************/
#ifdef CONFIG_ARMV7M_USEBASEPRI
static inline void hc32_prioritize_syscall(int priority)
{
uint32_t regval;
/* SVCALL is system handler 11 */
regval = getreg32(NVIC_SYSH8_11_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK;
regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
putreg32(regval, NVIC_SYSH8_11_PRIORITY);
}
#endif
/****************************************************************************
* Name: hc32_irqinfo
*
* Description:
* Given an IRQ number, provide the register and bit setting to enable or
* disable the irq.
*
****************************************************************************/
static int hc32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
int n;
DEBUGASSERT(irq >= HC32_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= HC32_IRQ_FIRST)
{
n = irq - HC32_IRQ_FIRST;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
*bit = (uint32_t)1 << (n & 0x1f);
}
/* Handle processor exceptions. Only a few can be disabled */
else
{
*regaddr = NVIC_SYSHCON;
if (irq == HC32_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
else if (irq == HC32_IRQ_BUSFAULT)
{
*bit = NVIC_SYSHCON_BUSFAULTENA;
}
else if (irq == HC32_IRQ_USAGEFAULT)
{
*bit = NVIC_SYSHCON_USGFAULTENA;
}
else if (irq == HC32_IRQ_SYSTICK)
{
*regaddr = NVIC_SYSTICK_CTRL;
*bit = NVIC_SYSTICK_CTRL_ENABLE;
}
else
{
return ERROR; /* Invalid or unsupported exception */
}
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
uint32_t regaddr;
int num_priority_registers;
int i;
/* Disable all interrupts */
for (i = 0; i < NR_IRQS - HC32_IRQ_FIRST; i += 32)
{
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
/* The standard location for the vector table is at the beginning of FLASH
* at address 0x0800:0000. If we are using the STMicro DFU bootloader,
* then the vector table will be offset to a different location in FLASH
* and we will need to set the NVIC vector location to this alternative
* location.
*/
#if defined(__ICCARM__)
putreg32((uint32_t)__vector_table, NVIC_VECTAB);
#else
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#endif
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
arm_ramvec_initialize();
#endif
/* Set all interrupts (and exceptions) to the default priority */
putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
/* The NVIC ICTR register (bits 0-4) holds the number of interrupt
* lines that the NVIC supports:
*
* 0 -> 32 interrupt lines, 8 priority registers
* 1 -> 64 " " " ", 16 priority registers
* 2 -> 96 " " " ", 32 priority registers
* ...
*/
num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8;
/* Now set all of the interrupt lines to the default priority */
regaddr = NVIC_IRQ0_3_PRIORITY;
while (num_priority_registers--)
{
putreg32(DEFPRIORITY32, regaddr);
regaddr += 4;
}
/* currents_regs is non-NULL only while processing an interrupt */
CURRENT_REGS = NULL;
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
* exception is used for performing context switches; The Hard Fault
* must also be caught because a SVCall may show up as a Hard Fault
* under certain conditions.
*/
irq_attach(HC32_IRQ_SVCALL, arm_svcall, NULL);
irq_attach(HC32_IRQ_HARDFAULT, arm_hardfault, NULL);
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(HC32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
hc32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
#endif
/* If the MPU is enabled, then attach and enable the Memory Management
* Fault handler.
*/
#ifdef CONFIG_ARM_MPU
irq_attach(HC32_IRQ_MEMFAULT, arm_memfault, NULL);
up_enable_irq(HC32_IRQ_MEMFAULT);
#endif
#if defined(CONFIG_RTC) && !defined(CONFIG_RTC_EXTERNAL)
/* RTC was initialized earlier but IRQs weren't ready at that time */
hc32_rtc_irqinitialize();
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG_FEATURES
irq_attach(HC32_IRQ_NMI, hc32_nmi, NULL);
#ifndef CONFIG_ARM_MPU
irq_attach(HC32_IRQ_MEMFAULT, arm_memfault, NULL);
#endif
irq_attach(HC32_IRQ_BUSFAULT, hc32_busfault, NULL);
irq_attach(HC32_IRQ_USAGEFAULT, hc32_usagefault, NULL);
irq_attach(HC32_IRQ_PENDSV, hc32_pendsv, NULL);
irq_attach(HC32_IRQ_DBGMONITOR, hc32_dbgmonitor, NULL);
irq_attach(HC32_IRQ_RESERVED, hc32_reserved, NULL);
#endif
hc32_dumpnvic("initial", NR_IRQS);
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts */
up_irq_enable();
#endif
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
****************************************************************************/
void up_disable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (hc32_irqinfo(irq, &regaddr, &bit, NVIC_CLRENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to disable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Clear Enable register. For other exceptions, we need to
* clear the bit in the System Handler Control and State Register.
*/
if (irq >= HC32_IRQ_FIRST)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval &= ~bit;
putreg32(regval, regaddr);
}
}
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'
*
****************************************************************************/
void up_enable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (hc32_irqinfo(irq, &regaddr, &bit, NVIC_ENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to enable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Set Enable register. For other exceptions, we need to
* set the bit in the System Handler Control and State Register.
*/
if (irq >= HC32_IRQ_FIRST)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval |= bit;
putreg32(regval, regaddr);
}
}
}
/****************************************************************************
* Name: arm_ack_irq
*
* Description:
* Acknowledge the IRQ
*
****************************************************************************/
void arm_ack_irq(int irq)
{
}
/****************************************************************************
* Name: up_prioritize_irq
*
* Description:
* Set the priority of an IRQ.
*
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
****************************************************************************/
#ifdef CONFIG_ARCH_IRQPRIO
int up_prioritize_irq(int irq, int priority)
{
uint32_t regaddr;
uint32_t regval;
int shift;
DEBUGASSERT(irq >= HC32_IRQ_MEMFAULT && irq < NR_IRQS &&
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < HC32_IRQ_FIRST)
{
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
* registers (0-3 are invalid)
*/
regaddr = NVIC_SYSH_PRIORITY(irq);
irq -= 4;
}
else
{
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
irq -= HC32_IRQ_FIRST;
regaddr = NVIC_IRQ_PRIORITY(irq);
}
regval = getreg32(regaddr);
shift = ((irq & 3) << 3);
regval &= ~(0xff << shift);
regval |= (priority << shift);
putreg32(regval, regaddr);
hc32_dumpnvic("prioritize", irq);
return OK;
}
#endif

421
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_lowputc.c Executable file
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@ -0,0 +1,421 @@
/****************************************************************************
* arch/arm/src/hc32/hc32_lowputc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "chip.h"
#include "hc32_rcc.h"
#include "hc32_gpio.h"
#include "hc32_uart.h"
#include "hc32_lowputc.h"
#include "hc32f4a0_usart.h"
#include "hc32_ddl.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* UART multiple processor ID definition */
#define UART_MASTER_STATION_ID (0x20U)
#define UART_SLAVE_STATION_ID (0x21U)
/* Ring buffer size */
#define IS_RING_BUFFER_EMPTY(x) (0U == ((x)->u16UsedSize))
/* Multi-processor silence mode */
#define LP_UART_NORMAL_MODE (0U)
#define LP_UART_SILENCE_MODE (1U)
/**
* @brief Ring buffer structure definition
*/
typedef struct
{
uint16_t u16Capacity;
__IO uint16_t u16UsedSize;
uint16_t u16InIdx;
uint16_t u16OutIdx;
uint8_t au8Buf[50];
} stc_ring_buffer_t;
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
static uint8_t m_u8UartSilenceMode = LP_UART_NORMAL_MODE;
static stc_ring_buffer_t m_stcRingBuf = {
.u16InIdx = 0U,
.u16OutIdx = 0U,
.u16UsedSize = 0U,
.u16Capacity = sizeof (m_stcRingBuf.au8Buf),
};
/****************************************************************************
* Private Functions
****************************************************************************/
/**
* @brief Set silence mode.
* @param [in] u8Mode Silence mode
* This parameter can be one of the following values:
* @arg LP_UART_SILENCE_MODE: UART silence mode
* @arg LP_UART_NORMAL_MODE: UART normal mode
* @retval None
*/
static void UsartSetSilenceMode(uint8_t u8Mode)
{
m_u8UartSilenceMode = u8Mode;
}
/**
* @brief Get silence mode.
* @param [in] None
* @retval Returned value can be one of the following values:
* @arg LP_UART_SILENCE_MODE: UART silence mode
* @arg LP_UART_NORMAL_MODE: UART normal mode
*/
static uint8_t UsartGetSilenceMode(void)
{
return m_u8UartSilenceMode;
}
/**
* @brief Instal IRQ handler.
* @param [in] pstcConfig Pointer to struct @ref stc_irq_signin_config_t
* @param [in] u32Priority Interrupt priority
* @retval None
*/
static void InstalIrqHandler(const stc_irq_signin_config_t *pstcConfig,
uint32_t u32Priority)
{
if (NULL != pstcConfig)
{
(void)INTC_IrqSignIn(pstcConfig);
NVIC_ClearPendingIRQ(pstcConfig->enIRQn);
NVIC_SetPriority(pstcConfig->enIRQn, u32Priority);
NVIC_EnableIRQ(pstcConfig->enIRQn);
}
}
/**
* @brief Write ring buffer.
* @param [in] pstcBuffer Pointer to a @ref stc_ring_buffer_t structure
* @param [in] pu8Data Pointer to data buffer to read
* @retval An en_result_t enumeration value:
* - Ok: Write success.
* - ErrorNotReady: Buffer is empty.
*/
static en_result_t RingBufRead(stc_ring_buffer_t *pstcBuffer, uint8_t *pu8Data)
{
en_result_t enRet = Ok;
if (pstcBuffer->u16UsedSize == 0U)
{
enRet = ErrorNotReady;
}
else
{
*pu8Data = pstcBuffer->au8Buf[pstcBuffer->u16OutIdx++];
pstcBuffer->u16OutIdx %= pstcBuffer->u16Capacity;
pstcBuffer->u16UsedSize--;
}
return enRet;
}
/**
* @brief UART TX Empty IRQ callback.
* @param None
* @retval None
*/
static void USART_TxEmpty_IrqCallback(void)
{
uint8_t u8Data = 0U;
en_flag_status_t enFlag = USART_GetStatus(LP_UNIT, USART_FLAG_TXE);
en_functional_state_t enState = USART_GetFuncState(LP_UNIT, USART_INT_TXE);
if ((Set == enFlag) && (Enable == enState))
{
USART_SendId(LP_UNIT, UART_SLAVE_STATION_ID);
while (Reset == USART_GetStatus(LP_UNIT, USART_FLAG_TC)) /* Wait Tx data register empty */
{
}
if (Ok == RingBufRead(&m_stcRingBuf, &u8Data))
{
USART_SendData(LP_UNIT, (uint16_t)u8Data);
}
if (IS_RING_BUFFER_EMPTY(&m_stcRingBuf))
{
USART_FuncCmd(LP_UNIT, USART_INT_TXE, Disable);
USART_FuncCmd(LP_UNIT, USART_INT_TC, Enable);
}
}
}
/**
* @brief UART TX Complete IRQ callback.
* @param None
* @retval None
*/
static void USART_TxComplete_IrqCallback(void)
{
en_flag_status_t enFlag = USART_GetStatus(LP_UNIT, USART_FLAG_TC);
en_functional_state_t enState = USART_GetFuncState(LP_UNIT, USART_INT_TC);
if ((Set == enFlag) && (Enable == enState))
{
/* Disable TX function */
USART_FuncCmd(LP_UNIT, (USART_TX | USART_RX | USART_INT_TC), Disable);
/* Enable RX function */
USART_FuncCmd(LP_UNIT, (USART_RX | USART_INT_RX), Enable);
}
}
/**
* @brief Write ring buffer.
* @param [in] pstcBuffer Pointer to a @ref stc_ring_buffer_t structure
* @param [in] u8Data Data to write
* @retval An en_result_t enumeration value:
* - Ok: Write success.
* - ErrorBufferFull: Buffer is full.
*/
static en_result_t write_ring_buf(stc_ring_buffer_t *pstcBuffer, uint8_t u8Data)
{
en_result_t enRet = Ok;
if (pstcBuffer->u16UsedSize >= pstcBuffer->u16Capacity)
{
enRet = ErrorBufferFull;
}
else
{
pstcBuffer->au8Buf[pstcBuffer->u16InIdx++] = u8Data;
pstcBuffer->u16InIdx %= pstcBuffer->u16Capacity;
pstcBuffer->u16UsedSize++;
}
return enRet;
}
/**
* @brief UART RX IRQ callback.
* @param None
* @retval None
*/
static void USART_Rx_IrqCallback(void)
{
uint8_t u8RxData;
en_flag_status_t enFlag = USART_GetStatus(LP_UNIT, USART_FLAG_RXNE);
en_functional_state_t enState = USART_GetFuncState(LP_UNIT, USART_INT_RX);
if ((Set == enFlag) && (Enable == enState))
{
u8RxData = (uint8_t)USART_RecData(LP_UNIT);
if ((Reset == USART_GetStatus(LP_UNIT, USART_FLAG_MPB)) &&
(LP_UART_NORMAL_MODE == UsartGetSilenceMode()))
{
write_ring_buf(&m_stcRingBuf, u8RxData);
}
else
{
if (UART_MASTER_STATION_ID != u8RxData)
{
USART_SilenceCmd(LP_UNIT, Enable);
UsartSetSilenceMode(LP_UART_SILENCE_MODE);
}
else
{
UsartSetSilenceMode(LP_UART_NORMAL_MODE);
}
}
}
}
/**
* @brief UART RX Error IRQ callback.
* @param None
* @retval None
*/
static void USART_RxErr_IrqCallback(void)
{
USART_ClearStatus(LP_UNIT, (USART_CLEAR_FLAG_FE | USART_CLEAR_FLAG_PE | USART_CLEAR_FLAG_ORE));
}
void hc32_unlock(void)
{
/* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */
GPIO_Unlock();
/* Unlock PWC register: FCG0 */
PWC_FCG0_Unlock();
/* Unlock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */
PWC_Unlock(PWC_UNLOCK_CODE_0);
/* Unlock SRAM register: WTCR */
SRAM_WTCR_Unlock();
/* Unlock SRAM register: CKCR */
// SRAM_CKCR_Unlock();
/* Unlock all EFM registers */
EFM_Unlock();
}
void hc32_lock(void)
{
/* Lock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */
GPIO_Lock();
/* Lock PWC register: FCG0 */
PWC_FCG0_Lock();
/* Lock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */
PWC_Lock(PWC_UNLOCK_CODE_0);
/* Lock SRAM register: WTCR */
SRAM_WTCR_Lock();
/* Lock SRAM register: CKCR */
// SRAM_CKCR_Lock();
/* Lock EFM OTP write protect registers */
// EFM_OTP_WP_Lock();
/* Lock EFM register: FWMC */
// EFM_FWMC_Lock();
/* Lock all EFM registers */
EFM_Lock();
}
void hc32_print_portinit(void)
{
GPIO_SetFunc(BSP_PRINTF_PORT, BSP_PRINTF_PIN, BSP_PRINTF_PORT_FUNC, PIN_SUBFUNC_DISABLE);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_lowputc
*
* Description:
* Output one byte on the serial console
*
****************************************************************************/
void arm_lowputc(char ch)
{
while(Set != USART_GetStatus(LP_UNIT, USART_FLAG_TXE));
USART_SendData(LP_UNIT, ch);
}
/****************************************************************************
* Name: hc32_lowsetup
*
* Description:
* This performs basic initialization of the USART used for the serial
* console. Its purpose is to get the console output available as soon
* as possible.
*
****************************************************************************/
void hc32_lowsetup(void)
{
stc_irq_signin_config_t stcIrqSigninCfg;
const stc_usart_multiprocessor_init_t stcUartMultiProcessorInit = {
.u32Baudrate = 115200UL,
.u32BitDirection = USART_LSB,
.u32StopBit = USART_STOPBIT_1BIT,
.u32DataWidth = USART_DATA_LENGTH_8BIT,
.u32ClkMode = USART_INTERNCLK_NONE_OUTPUT,
.u32PclkDiv = USART_PCLK_DIV64,
.u32OversamplingBits = USART_OVERSAMPLING_8BIT,
.u32NoiseFilterState = USART_NOISE_FILTER_DISABLE,
.u32SbDetectPolarity = USART_SB_DETECT_FALLING,
};
hc32_unlock();
hc32_clk_config();
/* Initialize UART for debug print function. */
DDL_PrintfInit(BSP_PRINTF_DEVICE, BSP_PRINTF_BAUDRATE, hc32_print_portinit);
/* Configure USART RX/TX pin. */
GPIO_SetFunc(LP_RX_PORT, LP_RX_PIN, LP_RX_GPIO_FUNC, PIN_SUBFUNC_DISABLE);
GPIO_SetFunc(LP_TX_PORT, LP_TX_PIN, LP_TX_GPIO_FUNC, PIN_SUBFUNC_DISABLE);
hc32_lock();
/* Enable peripheral clock */
PWC_Fcg3PeriphClockCmd(LP_FUNCTION_CLK_GATE, Enable);
/* Set silence mode */
UsartSetSilenceMode(LP_UART_SILENCE_MODE);
/* Initialize UART function. */
(void)USART_MultiProcessorInit(LP_UNIT, &stcUartMultiProcessorInit);
/* Register error IRQ handler && configure NVIC. */
stcIrqSigninCfg.enIRQn = LP_UNIT_ERR_INT_IRQn;
stcIrqSigninCfg.enIntSrc = LP_UNIT_ERR_INT_SRC;
stcIrqSigninCfg.pfnCallback = &USART_RxErr_IrqCallback;
InstalIrqHandler(&stcIrqSigninCfg, DDL_IRQ_PRIORITY_DEFAULT);
/* Register RX IRQ handler && configure NVIC. */
stcIrqSigninCfg.enIRQn = LP_UNIT_RX_INT_IRQn;
stcIrqSigninCfg.enIntSrc = LP_UNIT_RX_INT_SRC;
stcIrqSigninCfg.pfnCallback = &USART_Rx_IrqCallback;
InstalIrqHandler(&stcIrqSigninCfg, DDL_IRQ_PRIORITY_00);
/* Register TX IRQ handler && configure NVIC. */
stcIrqSigninCfg.enIRQn = LP_UNIT_TX_INT_IRQn;
stcIrqSigninCfg.enIntSrc = LP_UNIT_TX_INT_SRC;
stcIrqSigninCfg.pfnCallback = &USART_TxEmpty_IrqCallback;
InstalIrqHandler(&stcIrqSigninCfg, DDL_IRQ_PRIORITY_DEFAULT);
/* Register TC IRQ handler && configure NVIC. */
stcIrqSigninCfg.enIRQn = LP_UNIT_TCI_INT_IRQn;
stcIrqSigninCfg.enIntSrc = LP_UNIT_TCI_INT_SRC;
stcIrqSigninCfg.pfnCallback = &USART_TxComplete_IrqCallback;
InstalIrqHandler(&stcIrqSigninCfg, DDL_IRQ_PRIORITY_DEFAULT);
}

71
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-riscv64/src/lcd_demo.c → Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_lowputc.h
View File

@ -1,5 +1,5 @@
/****************************************************************************
* lcd_demo.c
* arch/arm/src/hc32/hc32_lowputc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -18,47 +18,50 @@
*
****************************************************************************/
/**
* @file lcd_demo.c
* @brief
* @version 1.0.0
* @author AIIT XUOS Lab
* @date 2022-07-21
*/
#ifndef __ARCH_ARM_SRC_HC32_HC32_LOWPUTC_H
#define __ARCH_ARM_SRC_HC32_HC32_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "nuttx/arch.h"
#include "nuttx/lcd/lt768.h"
#include "nuttx/lcd/lt768_lib.h"
#include "nuttx/lcd/k210_lcd.h"
#include <nuttx/config.h>
void LcdDemo(void)
#include "chip.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
// int x1 = 0, y1 = 0, x2 = LCD_XSIZE_TFT, y2 = LCD_YSIZE_TFT;
int x1 = 100, y1 = 100, x2 = 200, y2 = 200;
#else
#define EXTERN extern
#endif
Main_Image_Start_Address(LCD_START_ADDR);
Main_Image_Width(LCD_XSIZE_TFT);
Main_Window_Start_XY(0, 0);
Canvas_Image_Start_address(LCD_START_ADDR);
Canvas_image_width(LCD_XSIZE_TFT);
Active_Window_XY(0, 0);
Active_Window_WH(LCD_XSIZE_TFT, LCD_YSIZE_TFT);
up_mdelay(10);
Canvas_Image_Start_address(LCD_START_ADDR);
/****************************************************************************
* Name: hc32_lowsetup
*
* Description:
* Called at the very beginning of _start.
* Performs low level initialization of serial console.
*
****************************************************************************/
for(int i = 0; i < 3; i++)
{
syslog(LOG_NOTICE, "Disp_demo %d\n", i);
LT768_DrawSquare_Fill(x1, y1, x2, y2, Red);
up_mdelay(2000);
LT768_DrawSquare_Fill(x1, y1, x2, y2, Green);
up_mdelay(2000);
LT768_DrawSquare_Fill(x1, y1, x2, y2, Blue);
up_mdelay(2000);
}
void hc32_lowsetup(void);
void hc32_unlock(void);
void hc32_lock(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_HC32_HC32_LOWPUTC_H */

112
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_mpuinit.c Executable file
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@ -0,0 +1,112 @@
/****************************************************************************
* arch/arm/src/hc32/hc32_mpuinit.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <assert.h>
#include <nuttx/userspace.h>
#include "mpu.h"
#include "hc32_mpuinit.h"
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef MAX
# define MAX(a,b) a > b ? a : b
#endif
#ifndef MIN
# define MIN(a,b) a < b ? a : b
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: hc32_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only restricted SAM3U
* resources.
*
****************************************************************************/
void hc32_mpuinitialize(void)
{
uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart);
uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend);
DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart &&
dataend >= datastart);
/* Show MPU information */
mpu_showtype();
/* Reset MPU if enabled */
mpu_reset();
/* Configure user flash and SRAM space */
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_user_intsram(datastart, dataend - datastart);
/* Then enable the MPU */
mpu_control(true, false, true);
}
/****************************************************************************
* Name: hc32_mpu_uheap
*
* Description:
* Map the user-heap region.
*
* This logic may need an extension to handle external SDRAM).
*
****************************************************************************/
void hc32_mpu_uheap(uintptr_t start, size_t size)
{
mpu_user_intsram(start, size);
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARM_MPU */

75
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/hc32/hc32_mpuinit.h Executable file
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@ -0,0 +1,75 @@
/****************************************************************************
* arch/arm/src/hc32/hc32_mpuinit.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_HC32_HC32_MPUINIT_H
#define __ARCH_ARM_SRC_HC32_HC32_MPUINIT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: hc32_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only unrestricted MCU
* resources.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void hc32_mpuinitialize(void);
#else
# define hc32_mpuinitialize()
#endif
/****************************************************************************
* Name: hc32_mpu_uheap
*
* Description:
* Map the user heap region.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void hc32_mpu_uheap(uintptr_t start, size_t size);
#else
# define hc32_mpu_uheap(start,size)
#endif
#endif /* __ARCH_ARM_SRC_HC32_HC32_MPUINIT_H */

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/****************************************************************************
* arch/arm/src/hc32/hc32_pminitialize.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_internal.h"
#include "hc32_pm.h"
#ifdef CONFIG_PM
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_pminitialize
*
* Description:
* This function is called by MCU-specific logic at power-on reset in
* order to provide one-time initialization the power management subsystem.
* This function must be called *very* early in the initialization sequence
* *before* any other device drivers are initialized (since they may
* attempt to register with the power management subsystem).
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void arm_pminitialize(void)
{
}
#endif /* CONFIG_PM */

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/****************************************************************************
* arch/arm/src/hc32/hc32_pm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_HC32_HC32_PM_H
#define __ARCH_ARM_SRC_HC32_HC32_PM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include "chip.h"
#include "arm_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: hc32_pmstop
*
* Description:
* Enter STOP mode.
*
* Input Parameters:
* lpds - true: To further reduce power consumption in Stop mode, put the
* internal voltage regulator in low-power mode using the LPDS bit
* of the Power control register (PWR_CR).
*
* Returned Value:
* Zero means that the STOP was successfully entered and the system has
* been re-awakened. The internal voltage regulator is back to its
* original state. Otherwise, STOP mode did not occur and a negated
* errno value is returned to indicate the cause of the failure.
*
****************************************************************************/
int hc32_pmstop(bool lpds);
/****************************************************************************
* Name: hc32_pmstandby
*
* Description:
* Enter STANDBY mode.
*
* Input Parameters:
* None
*
* Returned Value:
* On success, this function will not return (STANDBY mode can only be
* terminated with a reset event). Otherwise, STANDBY mode did not occur
* and a negated errno value is returned to indicate the cause of the
* failure.
*
****************************************************************************/
int hc32_pmstandby(void);
/****************************************************************************
* Name: hc32_pmsleep
*
* Description:
* Enter SLEEP mode.
*
* Input Parameters:
* sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is
* executed, the MCU enters Sleep mode as soon as it
* exits the lowest priority ISR.
* - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep
* mode as soon as WFI or WFE instruction is executed.
* Returned Value:
* None
*
****************************************************************************/
void hc32_pmsleep(bool sleeponexit);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_HC32_HC32_PM_H */

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/****************************************************************************
* arch/arm/src/hc32/hc32_rcc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdio.h>
#include <assert.h>
#include <debug.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "chip.h"
#include "hc32_rcc.h"
#include "hc32f4a0_clk.h"
#include "hc32f4a0_sram.h"
#include "hc32f4a0_efm.h"
#include "hc32f4a0_pwc.h"
#include "hc32f4a0_gpio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Allow up to 100 milliseconds for the high speed clock to become ready.
* that is a very long delay, but if the clock does not become ready we are
* hosed anyway.
*/
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
/*!< System clock frequency (Core clock) */
__NO_INIT uint32_t SystemCoreClock;
/*!< High speed RC frequency (HCR clock) */
__NO_INIT uint32_t HRC_VALUE;
/****************************************************************************
* Included Files
****************************************************************************/
/* Include chip-specific clocking initialization logic */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/**
* @brief Setup the microcontroller system. Initialize the System and update
* the SystemCoreClock variable.
* @param None
* @retval None
*/
void hc32_sysclk_init(void)
{
/* FPU settings */
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
hc32_sysclk_update();
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* @param None
* @retval None
*/
void hc32_sysclk_update(void)
{
uint8_t tmp;
uint32_t plln;
uint32_t pllp;
uint32_t pllm;
/* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */
/* ICG1.HRCFREQSEL = '0' represent HRC_VALUE = 20000000UL */
/* ICG1.HRCFREQSEL = '1' represent HRC_VALUE = 16000000UL */
if (1UL == (HRC_FREQ_MON() & 1UL))
{
HRC_VALUE = HRC_16MHz_VALUE;
}
else
{
HRC_VALUE = HRC_20MHz_VALUE;
}
tmp = M4_CMU->CKSWR & CMU_CKSWR_CKSW;
switch(tmp)
{
case 0x00U: /* use internal high speed RC */
SystemCoreClock = HRC_VALUE;
break;
case 0x01U: /* use internal middle speed RC */
SystemCoreClock = MRC_VALUE;
break;
case 0x02U: /* use internal low speed RC */
SystemCoreClock = LRC_VALUE;
break;
case 0x03U: /* use external high speed OSC */
SystemCoreClock = XTAL_VALUE;
break;
case 0x04U: /* use external low speed OSC */
SystemCoreClock = XTAL32_VALUE;
break;
case 0x05U: /* use PLLH */
/* PLLCLK = ((pllsrc / pllm) * plln) / pllp */
pllp = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHP_POS) & 0x0FUL);
plln = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHN_POS) & 0xFFUL);
pllm = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHM_POS) & 0x03UL);
/* use external high speed OSC as PLL source */
if (0UL == bM4_CMU->PLLHCFGR_b.PLLSRC)
{
SystemCoreClock = (XTAL_VALUE) / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL);
}
/* use internal high RC as PLL source */
else
{
SystemCoreClock = (HRC_VALUE) / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL);
}
break;
default:
break;
}
}
/**
* @brief BSP clock initialize.
* Set board system clock to PLLH@240MHz
* Flash: 5 wait
* SRAM_HS: 1 wait
* SRAM1_2_3_4_B: 2 wait
* PCLK0: 240MHz
* PCLK1: 120MHz
* PCLK2: 60MHz
* PCLK3: 60MHz
* PCLK4: 120MHz
* EXCLK: 120MHz
* HCLK: 240MHz
* @param None
* @retval None
*/
void hc32_clk_config(void)
{
stc_clk_xtal_init_t stcXtalInit;
stc_clk_pllh_init_t stcPLLHInit;
/* PCLK0, HCLK Max 240MHz */
/* PCLK1, PCLK4 Max 120MHz */
/* PCLK2, PCLK3 Max 60MHz */
/* EX BUS Max 120MHz */
CLK_ClkDiv(CLK_CATE_ALL, \
(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \
CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \
CLK_HCLK_DIV1));
CLK_XtalStructInit(&stcXtalInit);
/* Config Xtal and enable Xtal */
stcXtalInit.u8XtalMode = CLK_XTALMODE_OSC;
stcXtalInit.u8XtalDrv = CLK_XTALDRV_LOW;
stcXtalInit.u8XtalState = CLK_XTAL_ON;
stcXtalInit.u8XtalStb = CLK_XTALSTB_2MS;
CLK_XtalInit(&stcXtalInit);
(void)CLK_PLLHStructInit(&stcPLLHInit);
/* VCO = (8/1)*120 = 960MHz*/
stcPLLHInit.u8PLLState = CLK_PLLH_ON;
stcPLLHInit.PLLCFGR = 0UL;
stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLLSRC_XTAL;
(void)CLK_PLLHInit(&stcPLLHInit);
/* Highspeed SRAM set to 1 Read/Write wait cycle */
SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE_1, SRAM_WAIT_CYCLE_1);
/* SRAM1_2_3_4_backup set to 2 Read/Write wait cycle */
SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE_2, SRAM_WAIT_CYCLE_2);
/* 0-wait @ 40MHz */
EFM_SetWaitCycle(EFM_WAIT_CYCLE_5);
/* 4 cycles for 200 ~ 250MHz */
GPIO_SetReadWaitCycle(GPIO_READ_WAIT_4);
CLK_SetSysClkSrc(CLK_SYSCLKSOURCE_PLLH);
}
/****************************************************************************
* Name: rcc_resetbkp
*
* Description:
* The RTC needs to reset the Backup Domain to change RTCSEL and resetting
* the Backup Domain renders to disabling the LSE as consequence.
* In order to avoid resetting the Backup Domain when we already
* configured LSE we will reset the Backup Domain early (here).
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#if defined(CONFIG_HC32_RTC) && defined(CONFIG_HC32_PWR)
static inline void rcc_resetbkp(void)
{
uint32_t regval;
/* Check if the RTC is already configured */
// hc32_pwr_initbkp(false);
regval = getreg32(RTC_MAGIC_REG);
if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET)
{
hc32_pwr_enablebkp(true);
/* We might be changing RTCSEL - to ensure such changes work, we must
* reset the backup domain (having backed up the RTC_MAGIC token)
*/
modifyreg32(HC32_RCC_XXX, 0, RCC_XXX_YYYRST);
modifyreg32(HC32_RCC_XXX, RCC_XXX_YYYRST, 0);
hc32_pwr_enablebkp(false);
}
}
#else
# define rcc_resetbkp()
#endif
/****************************************************************************
* Name: rcc_reset
*
* Description:
* Reset the RCC clock configuration to the default reset state
*
****************************************************************************/
static inline void rcc_reset(void)
{
}
static inline void rcc_enableperipherals(void)
{
}
#ifndef CONFIG_ARCH_BOARD_HC32_CUSTOM_CLOCKCONFIG
static void hc32_stdclockconfig(void)
{
}
#endif
void hc32_clk_init(void)
{
hc32_sysclk_init();
/* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */
GPIO_Unlock();
/* Unlock PWC register: FCG0 */
// PWC_FCG0_Unlock();
// /* Unlock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */
// PWC_Unlock(PWC_UNLOCK_CODE_0);
/* Unlock SRAM register: WTCR */
SRAM_WTCR_Unlock();
/* Unlock SRAM register: CKCR */
// SRAM_CKCR_Unlock();
/* Unlock all EFM registers */
EFM_Unlock();
hc32_clk_config();
/* Lock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */
GPIO_Lock();
/* Lock PWC register: FCG0 */
PWC_FCG0_Lock();
/* Lock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */
PWC_Lock(PWC_UNLOCK_CODE_0);
/* Lock SRAM register: WTCR */
SRAM_WTCR_Lock();
/* Lock SRAM register: CKCR */
// SRAM_CKCR_Lock();
/* Lock EFM OTP write protect registers */
// EFM_OTP_WP_Lock();
/* Lock EFM register: FWMC */
// EFM_FWMC_Lock();
/* Lock all EFM registers */
EFM_Lock();
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: hc32_clockconfig
*
* Description:
* Called to establish the clock settings based on the values in board.h.
* This function (by default) will reset most everything, enable the PLL,
* and enable peripheral clocking for all peripherals enabled in the NuttX
* configuration file.
*
* If CONFIG_ARCH_BOARD_HC32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called hc32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void hc32_clockconfig(void)
{
/* Make sure that we are starting in the reset state */
rcc_reset();
/* Reset backup domain if appropriate */
rcc_resetbkp();
#if defined(CONFIG_ARCH_BOARD_HC32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
hc32_board_clockconfig();
#else
/* Invoke standard, fixed clock configuration based on definitions
* in board.h
*/
hc32_stdclockconfig();
#endif
/* Enable peripheral clocking */
rcc_enableperipherals();
#ifdef CONFIG_HC32_SYSCFG_IOCOMPENSATION
/* Enable I/O Compensation */
hc32_iocompensation();
#endif
hc32_clk_init();
}
/****************************************************************************
* Name: hc32_clockenable
*
* Description:
* Re-enable the clock and restore the clock settings based on settings
* in board.h. This function is only available to support low-power
* modes of operation: When re-awakening from deep-sleep modes, it is
* necessary to re-enable/re-start the PLL
*
* This functional performs a subset of the operations performed by
* hc32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_HC32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called hc32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_PM
void hc32_clockenable(void)
{
#if defined(CONFIG_ARCH_BOARD_HC32_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
hc32_board_clockconfig();
#else
/* Invoke standard, fixed clock configuration based on definitions
* in board.h
*/
hc32_stdclockconfig();
#endif
}
#endif

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/****************************************************************************
* arch/arm/src/hc32/hc32_rcc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_HC32_HC32_RCC_H
#define __ARCH_ARM_SRC_HC32_HC32_RCC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_internal.h"
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* This symbol references the Cortex-M3/4 vector table (as positioned by the
* linker script, ld.script or ld.script.dfu. The standard location for the
* vector table is at the beginning of FLASH at address 0x0800:0000. If we
* are using the STMicro DFU bootloader, then the vector table will be offset
* to a different location in FLASH and we will need to set the NVIC vector
* location to this alternative location.
*/
#if defined(__ICCARM__)
/* _vectors replaced on __vector_table for IAR C-SPY Simulator */
extern uint32_t __vector_table[];
#else
extern uint32_t _vectors[];
#endif
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: hc32_clockconfig
*
* Description:
* Called to establish the clock settings based on the values in board.h.
* This function (by default) will reset most everything, enable the PLL,
* and enable peripheral clocking for all periperipherals enabled in the
* NuttX configuration file.
*
* If CONFIG_ARCH_BOARD_HC32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called hc32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void hc32_clockconfig(void);
/****************************************************************************
* Name: hc32_board_clockconfig
*
* Description:
* Any HC32 board may replace the "standard" board clock configuration
* logic with its own, custom clock configuration logic.
*
****************************************************************************/
#ifdef CONFIG_ARCH_BOARD_HC32_CUSTOM_CLOCKCONFIG
void hc32_board_clockconfig(void);
#endif
/****************************************************************************
* Name: hc32_clockenable
*
* Description:
* Re-enable the clock and restore the clock settings based on settings in
* board.h.
* This function is only available to support low-power modes of operation:
* When re-awakening from deep-sleep modes, it is necessary to re-enable/
* re-start the PLL
*
* This functional performs a subset of the operations performed by
* hc32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_HC32_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called hc32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_PM
void hc32_clockenable(void);
#endif
/****************************************************************************
* Name: hc32_rcc_enablelse
*
* Description:
* Enable the External Low-Speed (LSE) Oscillator.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void hc32_rcc_enablelse(void);
/****************************************************************************
* Name: hc32_rcc_enablelsi
*
* Description:
* Enable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void hc32_rcc_enablelsi(void);
/****************************************************************************
* Name: hc32_rcc_disablelsi
*
* Description:
* Disable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void hc32_rcc_disablelsi(void);
void hc32_clk_init(void);
void hc32_clk_config(void);
void hc32_sysclk_init(void); /*!< Initialize the system */
void hc32_sysclk_update(void); /*!< Update SystemCoreClock variable */
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_HC32_HC32_RCC_H */

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/****************************************************************************
* arch/arm/src/stm32/stm32_rtc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32_RTC_H
#define __ARCH_ARM_SRC_STM32_STM32_RTC_H
#include <nuttx/config.h>
#include "chip.h"
/* The STM32 F1 has a simple battery-backed counter for its RTC and has a
* separate block for the BKP registers.
*/
#if defined(CONFIG_STM32_STM32F10XX)
# include "hardware/stm32_rtc.h"
# include "hardware/stm32_bkp.h"
/* The other families use a more traditional Realtime Clock/Calendar (RTCC)
* with broken-out data/time in BCD format. The backup registers are
* integrated into the RTCC in these families.
*/
#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F4XXX)
# include "hardware/stm32_rtcc.h"
#endif
/* Alarm function differs from part to part */
#if defined(CONFIG_STM32_STM32F4XXX)
# include "stm32f40xxx_alarm.h"
#elif defined(CONFIG_STM32_STM32L15XX)
# include "stm32l15xxx_alarm.h"
#else
# include "stm32_alarm.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a
* second base */
#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */
#if defined(CONFIG_STM32_STM32F10XX)
/* RTC is only a counter, store RTC data in backup domain register DR1 (if
* CONFIG_RTC_HIRES) and DR2 (state).
*/
#if !defined(CONFIG_STM32_RTC_MAGIC)
# define CONFIG_STM32_RTC_MAGIC (0xface) /* only 16 bit */
#endif
#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET)
# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00d)
#endif
#define RTC_MAGIC_REG STM32_BKP_DR2
#else /* !CONFIG_STM32_STM32F10XX */
#if !defined(CONFIG_STM32_RTC_MAGIC)
# define CONFIG_STM32_RTC_MAGIC (0xfacefeed)
#endif
#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET)
# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface)
#endif
#if !defined(CONFIG_STM32_RTC_MAGIC_REG)
# define CONFIG_STM32_RTC_MAGIC_REG (0)
#endif
#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG)
#endif /* CONFIG_STM32_STM32F10XX */
#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC
#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_rtc_irqinitialize
*
* Description:
* Initialize IRQs for RTC, not possible during up_rtc_initialize because
* up_irqinitialize is called later.
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int stm32_rtc_irqinitialize(void);
/****************************************************************************
* Name: stm32_rtc_getdatetime_with_subseconds
*
* Description:
* Get the current date and time from the date/time RTC. This interface
* is only supported by the date/time RTC hardware implementation.
* It is used to replace the system timer. It is only used by the RTOS
* during initialization to set up the system time when CONFIG_RTC and
* CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not).
*
* NOTE: Some date/time RTC hardware is capability of sub-second accuracy.
* Thatsub-second accuracy is returned through 'nsec'.
*
* Input Parameters:
* tp - The location to return the high resolution time value.
* nsec - The location to return the subsecond time value.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
int stm32_rtc_getdatetime_with_subseconds(FAR struct tm *tp, FAR long *nsec);
#endif
/****************************************************************************
* Name: stm32_rtc_setdatetime
*
* Description:
* Set the RTC to the provided time. RTC implementations which provide
* up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide
* this function.
*
* Input Parameters:
* tp - the time to use
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_RTC_DATETIME
struct tm;
int stm32_rtc_setdatetime(FAR const struct tm *tp);
#endif
/****************************************************************************
* Name: stm32_rtc_lowerhalf
*
* Description:
* Instantiate the RTC lower half driver for the STM32. General usage:
*
* #include <nuttx/timers/rtc.h>
* #include "stm32_rtc.h"
*
* struct rtc_lowerhalf_s *lower;
* lower = stm32_rtc_lowerhalf();
* rtc_initialize(0, lower);
*
* Input Parameters:
* None
*
* Returned Value:
* On success, a non-NULL RTC lower interface is returned. NULL is
* returned on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_DRIVER
struct rtc_lowerhalf_s;
FAR struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32_STM32_RTC_H */

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/****************************************************************************
* arch/arm/src/hc32/hc32_start.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/init.h>
#include "arm_internal.h"
#include "nvic.h"
#include "mpu.h"
#include "hc32_rcc.h"
#include "hc32_lowputc.h"
#include "hc32_gpio.h"
#include "hc32_uart.h"
#include "hc32_start.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* .data is positioned first in the primary RAM followed immediately by .bss.
* The IDLE thread stack lies just after .bss and has size give by
* CONFIG_IDLETHREAD_STACKSIZE; The heap then begins just after the IDLE.
* ARM EABI requires 64 bit stack alignment.
*/
#define HEAP_BASE ((uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE)
/****************************************************************************
* Public Data
****************************************************************************/
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
* linker script. _ebss lies at the end of the BSS region. The idle task
* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
* The IDLE thread is the thread that the system boots on and, eventually,
* becomes the IDLE, do nothing task that runs only when there is nothing
* else to run. The heap continues from there until the end of memory.
* g_idle_topstack is a read-only variable the provides this computed
* address.
*/
const uintptr_t g_idle_topstack = HEAP_BASE;
/****************************************************************************
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void hc32_fpuconfig(void);
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: showprogress
*
* Description:
* Print a character on the UART to show boot status.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) arm_lowputc(c)
#else
# define showprogress(c)
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
#ifdef CONFIG_ARMV7M_STACKCHECK
/* we need to get r10 set before we can allow instrumentation calls */
void __start(void) noinstrument_function;
#endif
/****************************************************************************
* Name: hc32_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void hc32_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void hc32_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define hc32_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: _start
*
* Description:
* This is the reset entry point.
*
****************************************************************************/
void __start(void)
{
const uint32_t *src;
uint32_t *dest;
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile("sub r10, sp, %0" : :
"r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* If enabled reset the MPU */
mpu_early_reset();
/* Configure the UART so that we can get debug output as soon as possible */
hc32_clockconfig();
hc32_fpuconfig();
hc32_lowsetup();
hc32_gpioinit();
showprogress('A');
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables.
*/
for (dest = _START_BSS; dest < _END_BSS; )
{
*dest++ = 0;
}
showprogress('B');
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
*/
for (src = _DATA_INIT, dest = _START_DATA; dest < _END_DATA; )
{
*dest++ = *src++;
}
showprogress('C');
#ifdef CONFIG_ARMV7M_ITMSYSLOG
/* Perform ARMv7-M ITM SYSLOG initialization */
itm_syslog_initialize();
#endif
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT
arm_earlyserialinit();
#endif
showprogress('D');
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*/
#ifdef CONFIG_BUILD_PROTECTED
hc32_userspace();
showprogress('E');
#endif
/* Initialize onboard resources */
hc32_boardinitialize();
showprogress('F');
hc32_print("nuttx start ...\n");
/* Then start NuttX */
showprogress('\r');
showprogress('\n');
nx_start();
/* Shouldn't get here */
for (; ; );
}

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/****************************************************************************
* arch/arm/src/hc32/hc32_start.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_HC32_HC32_START_H
#define __ARCH_ARM_SRC_HC32_HC32_START_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: hc32_boardinitialize
*
* Description:
* All HC32 architectures must provide the following entry point.
* This entry point is called early in the initialization -- after
* clocking and memory have been configured but before caches have been
* enabled and before any devices have been initialized.
*
****************************************************************************/
void hc32_boardinitialize(void);
#endif /* __ARCH_ARM_SRC_HC32_HC32_START_H */

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/****************************************************************************
* arch/arm/src/hc32/hc32_timerisr.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/timers/arch_timer.h>
#include <arch/board/board.h>
#include "nvic.h"
#include "clock/clock.h"
#include "arm_internal.h"
#include "systick.h"
#include "chip.h"
#include "hc32f4a0.h"
#include "hc32_common.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The desired timer interrupt frequency is provided by the definition
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
* system clock ticks per second. That value is a user configurable setting
* that defaults to 100 (100 ticks per second = 10 MS interval).
*
* The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK)
* divided by 8. The SysTick can work either with this clock or with the
* Cortex clock (HCLK), configurable in the SysTick Control and Status
* register.
*/
#undef CONFIG_HC32_SYSTICK_HCLKd8 /* Power up default is HCLK, not HCLK/8 */
/* And I don't know now to re-configure it yet */
#ifdef CONFIG_HC32_SYSTICK_HCLKd8
# define SYSTICK_RELOAD ((HC32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
#else
# define SYSTICK_RELOAD ((HC32_HCLK_FREQUENCY / CLK_TCK) - 1)
#endif
/* The size of the reload field is 24 bits. Verify that the reload value
* will fit in the reload register.
*/
//#if SYSTICK_RELOAD > 0x00ffffff
//# error SYSTICK_RELOAD exceeds the range of the RELOAD register
//#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: hc32_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
****************************************************************************/
#if !defined(CONFIG_ARMV7M_SYSTICK) && !defined(CONFIG_TIMER_ARCH)
static int hc32_timerisr(int irq, uint32_t *regs, void *arg)
{
/* Process timer interrupt */
nxsched_process_timer();
return 0;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: up_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void up_timer_initialize(void)
{
uint32_t regval;
/* Set the SysTick interrupt to the default priority */
regval = getreg32(NVIC_SYSH12_15_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
putreg32(regval, NVIC_SYSH12_15_PRIORITY);
/* Make sure that the SYSTICK clock source is set correctly */
#if 0 /* Does not work. Comes up with HCLK source and I can't change it */
regval = getreg32(NVIC_SYSTICK_CTRL);
#ifdef CONFIG_HC32_SYSTICK_HCLKd8
regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
#else
regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
#endif
putreg32(regval, NVIC_SYSTICK_CTRL);
#endif
#if defined(CONFIG_ARMV7M_SYSTICK) && defined(CONFIG_TIMER_ARCH)
up_timer_set_lowerhalf(systick_initialize(true, HC32_HCLK_FREQUENCY, -1));
#else
/* Configure SysTick to interrupt at the requested rate */
putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
/* Attach the timer interrupt vector */
irq_attach(HC32_IRQ_SYSTICK, (xcpt_t)hc32_timerisr, NULL);
/* Enable SysTick interrupts */
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
/* And enable the timer interrupt */
up_enable_irq(HC32_IRQ_SYSTICK);
#endif
}

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/****************************************************************************
* arch/arm/src/hc32/hc32_uart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_STC_HC32_HC32_UART_H
#define __ARCH_ARM_STC_HC32_HC32_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/serial/serial.h>
#include "chip.h"
#define CONSOLE_UART 6
#define HC32_NUSART 6
#ifndef USE_SERIALDRIVER
#define USE_SERIALDRIVER 1
#endif
#ifndef HAVE_SERIALDRIVER
#define HAVE_SERIALDRIVER 1
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Make sure that we have not enabled more U[S]ARTs than are supported by the
* device.
*/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Name: hc32_serial_get_uart
*
* Description:
* Get serial driver structure for HC32 UART
*
****************************************************************************/
FAR uart_dev_t *hc32_serial_get_uart(int uart_num);
void hc32_print(const char *fmt, ...);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_STC_HC32_HC32_UART_H */

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/**
*******************************************************************************
* @file hc32f4a0_gpio.c
* @brief This file provides firmware functions to manage the General Purpose
* Input/Output(GPIO).
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Zhangxl First version
2020-09-18 Zhangxl Optimize GPIO_DeInit() API
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32f4a0_gpio.h"
#include "hc32f4a0_utility.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @defgroup DDL_GPIO GPIO
* @brief GPIO Driver Library
* @{
*/
#if (DDL_GPIO_ENABLE == DDL_ON)
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup GPIO_Local_Macros GPIO Local Macros
* @{
*/
/**
* @defgroup GPIO_Registers_Reset_Value GPIO Registers Reset Value
* @{
*/
#define GPIO_PSPCR_RESET_VALUE (0x001FU)
#define GPIO_PCCR_RESET_VALUE (0x1000U)
#define GPIO_PINAER_RESET_VALUE (0x0000U)
/**
* @}
*/
/**
* @defgroup GPIO_Check_Parameters_Validity GPIO Check Parameters Validity
* @{
*/
/*! Parameter validity check for pin state. */
#define IS_GPIO_PIN_STATE(state) \
( ((state) == PIN_STATE_RESET) || \
((state) == PIN_STATE_SET))
/*! Parameter validity check for pin direction. */
#define IS_GPIO_DIR(dir) \
( ((dir) == PIN_DIR_IN) || \
((dir) == PIN_DIR_OUT))
/*! Parameter validity check for pin output type. */
#define IS_GPIO_OTYPE(otype) \
( ((otype) == PIN_OTYPE_CMOS) || \
((otype) == PIN_OTYPE_NMOS))
/*! Parameter validity check for pin driver capacity. */
#define IS_GPIO_PIN_DRV(drv) \
( ((drv) == PIN_DRV_LOW) || \
((drv) == PIN_DRV_MID) || \
((drv) == PIN_DRV_HIGH))
/*! Parameter validity check for pin latch function. */
#define IS_GPIO_LATCH(latch) \
( ((latch) == PIN_LATCH_OFF) || \
((latch) == PIN_LATCH_ON))
/*! Parameter validity check for internal pull-up resistor. */
#define IS_GPIO_PIN_PU(pu) \
( ((pu) == PIN_PU_OFF) || \
((pu) == PIN_PU_ON))
/*! Parameter validity check for pin state invert. */
#define IS_GPIO_PIN_INVERT(invert) \
( ((invert) == PIN_INVERT_OFF) || \
((invert) == PIN_INVERT_ON))
/*! Parameter validity check for pin input type. */
#define IS_GPIO_ITYPE(itype) \
( ((itype) == PIN_ITYPE_SMT) || \
((itype) == PIN_ITYPE_CMOS))
/*! Parameter validity check for external interrupt function. */
#define IS_GPIO_EXINT(exint) \
( ((exint) == PIN_EXINT_OFF) || \
((exint) == PIN_EXINT_ON))
/*! Parameter validity check for pin attribute. */
#define IS_GPIO_ATTR(attr) \
( ((attr) == PIN_ATTR_DIGITAL) || \
((attr) == PIN_ATTR_ANALOG))
/*! Parameter validity check for pin number. */
#define IS_GPIO_PIN(pin) (((pin) & GPIO_PIN_MASK ) != 0x0000U)
/*! Parameter validity check for port source. */
#define IS_GPIO_PORT(port) \
( ((port) != 0x00U) && \
(((port) | GPIO_PORT_MASK) == GPIO_PORT_MASK))
/*! Parameter validity check for port source. */
#define IS_GPIO_PORT_SOURCE(port) \
( ((port) == GPIO_PORT_A) || \
((port) == GPIO_PORT_B) || \
((port) == GPIO_PORT_C) || \
((port) == GPIO_PORT_D) || \
((port) == GPIO_PORT_E) || \
((port) == GPIO_PORT_F) || \
((port) == GPIO_PORT_G) || \
((port) == GPIO_PORT_H) || \
((port) == GPIO_PORT_I))
/*! Parameter validity check for pin function. */
#define IS_GPIO_FUNC(func) \
( ((func) <= GPIO_FUNC_20) || \
(((func) >= GPIO_FUNC_32) && ((func) <= GPIO_FUNC_63)))
/*! Parameter validity check for debug pin definition. */
#define IS_GPIO_DEBUG_PORT(port) \
( ((port) != 0x00U) && \
(((port) | GPIO_PIN_DEBUG_JTAG) == GPIO_PIN_DEBUG_JTAG))
/*! Parameter validity check for pin sub-function setting. */
#define IS_GPIO_PIN_BFE(bfe) \
( ((bfe) == PIN_SUBFUNC_ENABLE) || \
((bfe) == PIN_SUBFUNC_DISABLE))
/*! Parameter validity check for pin read wait cycle. */
#define IS_GPIO_READ_WAIT(wait) \
( ((wait) == GPIO_READ_WAIT_0) || \
((wait) == GPIO_READ_WAIT_1) || \
((wait) == GPIO_READ_WAIT_2) || \
((wait) == GPIO_READ_WAIT_3) || \
((wait) == GPIO_READ_WAIT_4) || \
((wait) == GPIO_READ_WAIT_5) || \
((wait) == GPIO_READ_WAIT_6) || \
((wait) == GPIO_READ_WAIT_7))
/* Check GPIO register lock status. */
#define IS_GPIO_UNLOCKED() (GPIO_PWPR_WE == (M4_GPIO->PWPR & GPIO_PWPR_WE))
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @defgroup GPIO_Global_Functions GPIO Global Functions
* @{
*/
/**
* @brief Initialize GPIO.
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index
* @param [in] pstcGpioInit: Pointer to a stc_gpio_init_t structure that
* contains configuration information.
* @retval Ok: GPIO initialize successful
* ErrorInvalidParameter: NULL pointer
*/
en_result_t GPIO_Init(uint8_t u8Port, uint16_t u16Pin, const stc_gpio_init_t *pstcGpioInit)
{
__IO uint16_t *PCRx;
uint16_t u16PinPos;
uint16_t u16PCRVal;
en_result_t enRet = Ok;
/* Check if pointer is NULL */
if (NULL == pstcGpioInit)
{
enRet = ErrorInvalidParameter;
}
else
{
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
DDL_ASSERT(IS_GPIO_PIN(u16Pin));
DDL_ASSERT(IS_GPIO_PIN_STATE(pstcGpioInit->u16PinState));
DDL_ASSERT(IS_GPIO_DIR(pstcGpioInit->u16PinDir));
DDL_ASSERT(IS_GPIO_OTYPE(pstcGpioInit->u16PinOType));
DDL_ASSERT(IS_GPIO_PIN_DRV(pstcGpioInit->u16PinDrv));
DDL_ASSERT(IS_GPIO_LATCH(pstcGpioInit->u16Latch));
DDL_ASSERT(IS_GPIO_PIN_PU(pstcGpioInit->u16PullUp));
DDL_ASSERT(IS_GPIO_PIN_INVERT(pstcGpioInit->u16Invert));
DDL_ASSERT(IS_GPIO_ITYPE(pstcGpioInit->u16PinIType));
DDL_ASSERT(IS_GPIO_EXINT(pstcGpioInit->u16ExInt));
DDL_ASSERT(IS_GPIO_UNLOCKED());
for (u16PinPos = 0U; u16PinPos < 16U; u16PinPos++)
{
if ((u16Pin & (1UL<<u16PinPos)) != 0U)
{
PCRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PCRA0) + \
((uint32_t)(u8Port) * 0x40UL) + u16PinPos * 4UL);
u16PCRVal = pstcGpioInit->u16ExInt | pstcGpioInit->u16PinIType | \
pstcGpioInit->u16Invert | pstcGpioInit->u16PullUp | \
pstcGpioInit->u16Latch | pstcGpioInit->u16PinDrv | \
pstcGpioInit->u16PinOType | pstcGpioInit->u16PinState | \
pstcGpioInit->u16PinDir | pstcGpioInit->u16PinAttr;
WRITE_REG16(*PCRx, u16PCRVal);
}
}
}
return enRet;
}
/**
* @brief De-init GPIO register to default value
* @param None
* @retval None
*/
void GPIO_DeInit(void)
{
stc_gpio_init_t stcGpioInit;
DDL_ASSERT(IS_GPIO_UNLOCKED());
(void)GPIO_StructInit(&stcGpioInit);
/* PORTA reset */
(void)GPIO_Init(GPIO_PORT_A, GPIO_PIN_ALL, &stcGpioInit);
/* PORTB reset */
(void)GPIO_Init(GPIO_PORT_B, GPIO_PIN_ALL, &stcGpioInit);
/* PORTC reset */
(void)GPIO_Init(GPIO_PORT_C, GPIO_PIN_ALL, &stcGpioInit);
/* PORTD reset */
(void)GPIO_Init(GPIO_PORT_D, GPIO_PIN_ALL, &stcGpioInit);
/* PORTE reset */
(void)GPIO_Init(GPIO_PORT_E, GPIO_PIN_ALL, &stcGpioInit);
/* PORTF reset */
(void)GPIO_Init(GPIO_PORT_F, GPIO_PIN_ALL, &stcGpioInit);
/* PORTG reset */
(void)GPIO_Init(GPIO_PORT_G, GPIO_PIN_ALL, &stcGpioInit);
/* PORTH reset */
(void)GPIO_Init(GPIO_PORT_H, GPIO_PIN_ALL, &stcGpioInit);
/* PORTI reset */
(void)GPIO_Init(GPIO_PORT_I, (GPIO_PIN_00 | GPIO_PIN_01 | GPIO_PIN_02 | \
GPIO_PIN_03 | GPIO_PIN_04 | GPIO_PIN_05 | \
GPIO_PIN_06 | GPIO_PIN_07 | GPIO_PIN_08 | \
GPIO_PIN_09 | GPIO_PIN_10 | GPIO_PIN_11 | \
GPIO_PIN_12 | GPIO_PIN_13), &stcGpioInit);
/* PORT global register reset */
WRITE_REG16(M4_GPIO->PSPCR, GPIO_PSPCR_RESET_VALUE);
WRITE_REG16(M4_GPIO->PCCR, GPIO_PCCR_RESET_VALUE);
WRITE_REG16(M4_GPIO->PINAER, GPIO_PINAER_RESET_VALUE);
}
/**
* @brief Initialize GPIO config structure. Fill each pstcGpioInit with default value
* @param [in] pstcGpioInit: Pointer to a stc_gpio_init_t structure that
* contains configuration information.
* @retval Ok: GPIO structure initialize successful
* ErrorInvalidParameter: NULL pointer
*/
en_result_t GPIO_StructInit(stc_gpio_init_t *pstcGpioInit)
{
en_result_t enRet = Ok;
/* Check if pointer is NULL */
if (NULL == pstcGpioInit)
{
enRet = ErrorInvalidParameter;
}
else
{
/* Reset GPIO init structure parameters values */
pstcGpioInit->u16PinState = PIN_STATE_RESET;
pstcGpioInit->u16PinDir = PIN_DIR_IN;
pstcGpioInit->u16PinOType = PIN_OTYPE_CMOS;
pstcGpioInit->u16PinDrv = PIN_DRV_LOW;
pstcGpioInit->u16Latch = PIN_LATCH_OFF;
pstcGpioInit->u16PullUp = PIN_PU_OFF;
pstcGpioInit->u16Invert = PIN_INVERT_OFF;
pstcGpioInit->u16PinIType = PIN_ITYPE_SMT;
pstcGpioInit->u16ExInt = PIN_EXINT_OFF;
pstcGpioInit->u16PinAttr = PIN_ATTR_DIGITAL;
}
return enRet;
}
/**
* @brief GPIO debug port configure. Set debug pins to GPIO
* @param [in] u8DebugPort
* @arg GPIO_PIN_SWDIO
* @arg GPIO_PIN_SWCLK
* @arg GPIO_PIN_SWO
* @arg GPIO_PIN_DEBUG_SWD
* @arg GPIO_PIN_TCK
* @arg GPIO_PIN_TMS
* @arg GPIO_PIN_TDO
* @arg GPIO_PIN_TDI
* @arg GPIO_PIN_TRST
* @arg GPIO_PIN_DEBUG_JTAG
* @param [in] enNewState
* @arg Enable: set to debug port (SWD/JTAG)
* @arg Disable: set to GPIO
* @retval None
*/
void GPIO_SetDebugPort(uint8_t u8DebugPort, en_functional_state_t enNewState)
{
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_DEBUG_PORT(u8DebugPort));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
DDL_ASSERT(IS_GPIO_UNLOCKED());
if (Enable == enNewState)
{
SET_REG16_BIT(M4_GPIO->PSPCR, ((uint16_t)u8DebugPort & GPIO_PSPCR_SPFE));
}
else
{
CLEAR_REG16_BIT(M4_GPIO->PSPCR, ((uint16_t)u8DebugPort & GPIO_PSPCR_SPFE));
}
}
/**
* @brief Set specified Port Pin function , and turn ON/OFF its sub-function
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index
* @param [in] u8Func: GPIO_FUNC_x, x can be selected from GPIO function definitions
* @param [in] u16BFE: GPIO Sub-function enable setting
* @arg PIN_SUBFUNC_ENABLE
* @arg PIN_SUBFUNC_DISABLE
* @retval None
*/
void GPIO_SetFunc(uint8_t u8Port, uint16_t u16Pin, uint8_t u8Func, uint16_t u16BFE)
{
__IO uint16_t *PFSRx;
uint8_t u8PinPos;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
DDL_ASSERT(IS_GPIO_PIN(u16Pin));
DDL_ASSERT(IS_GPIO_FUNC(u8Func));
DDL_ASSERT(IS_GPIO_PIN_BFE(u16BFE));
DDL_ASSERT(IS_GPIO_UNLOCKED());
for (u8PinPos = 0U; u8PinPos < 16U; u8PinPos++)
{
if ((u16Pin & (uint16_t)(1UL << u8PinPos)) != 0U)
{
PFSRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PFSRA0) + \
(uint32_t)(u8Port * 0x40UL) + u8PinPos * 4UL);
WRITE_REG16(*PFSRx, (u16BFE | (uint16_t)u8Func));
}
}
}
/**
* @brief Set the sub-function, it's a global configuration
* @param [in] u8Func: GPIO_FUNC_x, x can be selected from GPIO function definitions
* @retval None
*/
void GPIO_SetSubFunc(uint8_t u8Func)
{
DDL_ASSERT(IS_GPIO_FUNC(u8Func));
DDL_ASSERT(IS_GPIO_UNLOCKED());
MODIFY_REG16(M4_GPIO->PCCR, GPIO_PCCR_BFSEL, u8Func);
}
/**
* @brief Initialize GPIO.
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index
* @param [in] enNewState
* @arg Enable: set specified pin output enable
* @arg Disable: set specified pin output disable
* @retval None
*/
void GPIO_OE(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState)
{
__IO uint16_t *POERx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
DDL_ASSERT(IS_GPIO_PIN(u16Pin));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
POERx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->POERA) + 0x10UL * u8Port);
if (Enable == enNewState)
{
SET_REG16_BIT(*POERx, u16Pin);
}
else
{
CLEAR_REG16_BIT(*POERx, u16Pin);
}
}
/**
* @brief GPIO read wait cycle configure.
* @param [in] u16ReadWait
* @arg GPIO_READ_WAIT_0: ~ 50MHz
* @arg GPIO_READ_WAIT_1: 50 ~ 100MHz
* @arg GPIO_READ_WAIT_2: 100 ~ 150MHz
* @arg GPIO_READ_WAIT_3: 150 ~ 200MHz
* @arg GPIO_READ_WAIT_4: 200 ~ 250MHz
* @arg GPIO_READ_WAIT_5: 250MHz above
* @arg GPIO_READ_WAIT_6: 250MHz above
* @arg GPIO_READ_WAIT_7: 250MHz above
* @retval None
*/
void GPIO_SetReadWaitCycle(uint16_t u16ReadWait)
{
DDL_ASSERT(IS_GPIO_READ_WAIT(u16ReadWait));
DDL_ASSERT(IS_GPIO_UNLOCKED());
MODIFY_REG16(M4_GPIO->PCCR, GPIO_PCCR_RDWT, u16ReadWait);
}
/**
* @brief GPIO input MOS always ON configure.
* @param [in] u16PortIdx: Port index
* @arg GPIO_PORTA_IDX
* @arg GPIO_PORTB_IDX
* @arg GPIO_PORTC_IDX
* @arg GPIO_PORTD_IDX
* @arg GPIO_PORTE_IDX
* @arg GPIO_PORTF_IDX
* @arg GPIO_PORTG_IDX
* @arg GPIO_PORTH_IDX
* @arg GPIO_PORTI_IDX
* @arg GPIO_PORT_ALL
* @param [in] enNewState
* @arg Enable: set input MOS always ON
* @arg Disable: set input MOS turns on while read operation
* @retval None
*/
void GPIO_InMOSCmd(uint16_t u16PortIdx, en_functional_state_t enNewState)
{
DDL_ASSERT(IS_GPIO_PORT(u16PortIdx));
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
DDL_ASSERT(IS_GPIO_UNLOCKED());
if (Enable == enNewState)
{
SET_REG16_BIT(M4_GPIO->PINAER, u16PortIdx);
}
else
{
CLEAR_REG16_BIT(M4_GPIO->PINAER, u16PortIdx);
}
}
/**
* @brief Read specified GPIO input data port pins
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index
* @retval Specified GPIO port pin input value
*/
en_pin_state_t GPIO_ReadInputPins(uint8_t u8Port, uint16_t u16Pin)
{
__IO uint16_t *PIDRx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
DDL_ASSERT(IS_GPIO_PIN(u16Pin));
PIDRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PIDRA) + 0x10UL * u8Port);
return ((READ_REG16(*PIDRx) & (u16Pin)) != 0U) ? Pin_Set : Pin_Reset;
}
/**
* @brief Read specified GPIO input data port
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @retval Specified GPIO port input value
*/
uint16_t GPIO_ReadInputPort(uint8_t u8Port)
{
__IO uint16_t *PIDRx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
PIDRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PIDRA) + 0x10UL * u8Port);
return READ_REG16(*PIDRx);
}
/**
* @brief Read specified GPIO output data port pins
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index
* @retval Specified GPIO port pin output value
*/
en_pin_state_t GPIO_ReadOutputPins(uint8_t u8Port, uint16_t u16Pin)
{
__IO uint16_t *PODRx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
DDL_ASSERT(IS_GPIO_PIN(u16Pin));
PODRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PODRA) + 0x10UL * u8Port);
return ((*PODRx & (u16Pin)) != 0U) ? Pin_Set : Pin_Reset;
}
/**
* @brief Read specified GPIO output data port
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @retval Specified GPIO port output value
*/
uint16_t GPIO_ReadOutputPort(uint8_t u8Port)
{
__IO uint16_t *PODRx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
PODRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PODRA) + 0x10UL * u8Port);
return READ_REG16(*PODRx);
}
/**
* @brief Set specified GPIO output data port pins
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index
* @retval None
*/
void GPIO_SetPins(uint8_t u8Port, uint16_t u16Pin)
{
__IO uint16_t *POSRx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
DDL_ASSERT(IS_GPIO_PIN(u16Pin));
POSRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->POSRA) + 0x10UL * u8Port);
SET_REG16_BIT(*POSRx, u16Pin);
}
/**
* @brief Reset specified GPIO output data port pins
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index
* @retval None
*/
void GPIO_ResetPins(uint8_t u8Port, uint16_t u16Pin)
{
__IO uint16_t *PORRx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
DDL_ASSERT(IS_GPIO_PIN(u16Pin));
PORRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PORRA) + 0x10UL * u8Port);
SET_REG16_BIT(*PORRx, u16Pin);
}
/**
* @brief Write specified GPIO data port
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16PortVal: Pin output value
* @retval None
*/
void GPIO_WritePort(uint8_t u8Port, uint16_t u16PortVal)
{
__IO uint16_t *PODRx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
PODRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PODRA) + 0x10UL * u8Port);
WRITE_REG16(*PODRx, u16PortVal);
}
/**
* @brief Toggle specified GPIO output data port pin
* @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral
* @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index
* @retval None
*/
void GPIO_TogglePins(uint8_t u8Port, uint16_t u16Pin)
{
__IO uint16_t *POTRx;
/* Parameter validity checking */
DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port));
DDL_ASSERT(IS_GPIO_PIN(u16Pin));
POTRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->POTRA) + 0x10UL * u8Port);
SET_REG16_BIT(*POTRx, u16Pin);
}
/**
* @}
*/
#endif /* DDL_GPIO_ENABLE */
/**
* @}
*/
/**
* @}
*/
/******************************************************************************
* EOF (not truncated)
*****************************************************************************/

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/**
*******************************************************************************
* @file hc32f4a0_i2c.h
* @brief This file contains all the functions prototypes of the Inter-Integrated
* Circuit(I2C).
@verbatim
Change Logs:
Date Author Notes
2020-06-12 Hexiao First version
2020-07-15 Hexiao Modify I2C_SmBusCmd to I2C_SetMode
2020-08-31 Hexiao Remove invalid clock division value
2020-10-30 Hexiao Optimize data transfer api,etc.
@endverbatim
*******************************************************************************
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by HDSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4A0_I2C_H__
#define __HC32F4A0_I2C_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include "hc32_common.h"
#include "ddl_config.h"
/**
* @addtogroup HC32F4A0_DDL_Driver
* @{
*/
/**
* @addtogroup DDL_I2C
* @{
*/
#if (DDL_I2C_ENABLE == DDL_ON)
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/**
* @defgroup I2C_Global_Types I2C Global Types
* @{
*/
/**
* @brief I2c configuration structure
*/
typedef struct
{
uint32_t u32ClkDiv; /*!< I2C clock division for pclk3*/
uint32_t u32Baudrate; /*!< I2C baudrate config*/
uint32_t u32SclTime; /*!< The SCL rising and falling time, count of T(pclk3)*/
}stc_i2c_init_t;
/**
* @}
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @defgroup I2C_Global_Macros I2C Global Macros
* @{
*/
/** @defgroup I2C_Buadrate_Max I2C baudrate max value
* @{
*/
#define I2C_BAUDRATE_MAX (400000UL)
/**
* @}
*/
/** @defgroup I2C_Mode Peripheral Mode
* @{
*/
#define I2C_MODE_I2C (0UL)
#define I2C_MODE_SMBUS (2UL)
/**
* @}
*/
/** @defgroup I2C_Transfer_Direction I2C transfer direction
* @{
*/
#define I2C_DIR_TX (0x0U)
#define I2C_DIR_RX (0x1U)
/**
* @}
*/
/** @defgroup I2C_Addr_Config I2C address configuration
* @{
*/
#define I2C_ADDR_MODE_7BIT (0x0U)
#define I2C_ADDR_MODE_10BIT (I2C_SLR0_ADDRMOD0)
/**
* @}
*/
/** @defgroup I2C_Clock_division I2C clock division
* @{
*/
#define I2C_CLK_DIV1 (0UL)
#define I2C_CLK_DIV2 (1UL)
#define I2C_CLK_DIV4 (2UL)
#define I2C_CLK_DIV8 (3UL)
#define I2C_CLK_DIV16 (4UL)
#define I2C_CLK_DIV32 (5UL)
#define I2C_CLK_DIV64 (6UL)
#define I2C_CLK_DIV128 (7UL)
/**
* @}
*/
/** @defgroup I2C_Address_Num I2C address number
* @{
*/
#define I2C_ADDR_0 (0UL)
#define I2C_ADDR_1 (1UL)
/**
* @}
*/
/** @defgroup I2C_Ack_Type I2C ack type
* @{
*/
#define I2C_ACK (0UL)
#define I2C_NACK (I2C_CR1_ACK)
/**
* @}
*/
/** @defgroup I2C_Smbus_Match_Cfg I2C smbus address match configuration
* @{
*/
#define I2C_SMBUS_MATCH_ALRT (I2C_CR1_SMBALRTEN)
#define I2C_SMBUS_MATCH_DEFAULT (I2C_CR1_SMBDEFAULTEN)
#define I2C_SMBUS_MATCH_HOST (I2C_CR1_SMBHOSTEN)
/**
* @}
*/
/** @defgroup I2C_Smbus_clear_mask I2C smbus clear mask
* @{
*/
#define I2C_SMBUS_CONFIG_CLEARMASK (I2C_CR1_SMBALRTEN|I2C_CR1_SMBDEFAULTEN|I2C_CR1_SMBHOSTEN)
/**
* @}
*/
/** @defgroup I2C_Digital_Filter_mode I2C digital filter mode
* @{
*/
#define I2C_DIG_FILTMODE_1CYCLE (0UL << I2C_FLTR_DNF_POS)
#define I2C_DIG_FILTMODE_2CYCLE (1UL << I2C_FLTR_DNF_POS)
#define I2C_DIG_FILTMODE_3CYCLE (2UL << I2C_FLTR_DNF_POS)
#define I2C_DIG_FILTMODE_4CYCLE (3UL << I2C_FLTR_DNF_POS)
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup I2C_Global_Functions
* @{
*/
/* Initialization and Configuration **********************************/
void I2C_DeInit(M4_I2C_TypeDef* I2Cx);
en_result_t I2C_StructInit(stc_i2c_init_t* pstcI2C_InitStruct);
en_result_t I2C_Init(M4_I2C_TypeDef* I2Cx, const stc_i2c_init_t *pstcI2C_InitStruct, float32_t *pf32Err);
en_result_t I2C_BaudrateConfig(M4_I2C_TypeDef* I2Cx, const stc_i2c_init_t *pstcI2C_InitStruct, float32_t *pf32Err);
void I2C_SlaveAddrCmd(M4_I2C_TypeDef* I2Cx, uint32_t u32AddrNum, en_functional_state_t enNewState);
void I2C_SlaveAddrConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32Addr);
void I2C_SetMode(M4_I2C_TypeDef* I2Cx, uint32_t u32Mode);
void I2C_Cmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_FastAckCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_BusWaitCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_SoftwareResetCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_IntCmd(M4_I2C_TypeDef* I2Cx, uint32_t u32IntEn, en_functional_state_t enNewState);
void I2C_ClkHighTimeoutConfig(M4_I2C_TypeDef* I2Cx, uint16_t u16TimeoutH);
void I2C_ClkLowTimeoutConfig(M4_I2C_TypeDef* I2Cx, uint16_t u16TimeoutL);
void I2C_ClkHighTimeoutCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_ClkLowTimeoutCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_ClkTimeoutCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_SmbusConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32SmbusConfig, en_functional_state_t enNewState);
void I2C_DigitalFilterConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32DigFilterMode);
void I2C_DigitalFilterCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_AnalogFilterCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
void I2C_GeneralCallCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState);
/* Start/Restart/Stop ************************************************/
void I2C_GenerateStart(M4_I2C_TypeDef* I2Cx);
void I2C_GenerateReStart(M4_I2C_TypeDef* I2Cx);
void I2C_GenerateStop(M4_I2C_TypeDef* I2Cx);
/* Status management *************************************************/
en_flag_status_t I2C_GetStatus(const M4_I2C_TypeDef *I2Cx, uint32_t u32StatusBit);
void I2C_ClearStatus(M4_I2C_TypeDef* I2Cx, uint32_t u32StatusBit);
/* Data transfer *****************************************************/
void I2C_WriteDataReg(M4_I2C_TypeDef* I2Cx, uint8_t u8Data);
uint8_t I2C_ReadDataReg(const M4_I2C_TypeDef *I2Cx);
void I2C_AckConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32AckConfig);
/* High level functions for reference ********************************/
en_result_t I2C_Start(M4_I2C_TypeDef* I2Cx, uint32_t u32Timeout);
en_result_t I2C_Restart(M4_I2C_TypeDef* I2Cx, uint32_t u32Timeout);
en_result_t I2C_TransAddr(M4_I2C_TypeDef* I2Cx, uint8_t u8Addr, uint8_t u8Dir, uint32_t u32Timeout);
en_result_t I2C_Trans10BitAddr(M4_I2C_TypeDef* I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout);
en_result_t I2C_TransData(M4_I2C_TypeDef* I2Cx, uint8_t const pau8TxData[], uint32_t u32Size, uint32_t u32Timeout);
en_result_t I2C_Receive(M4_I2C_TypeDef* I2Cx, uint8_t pau8RxData[], uint32_t u32Size, uint32_t u32Timeout);
en_result_t I2C_Stop(M4_I2C_TypeDef* I2Cx, uint32_t u32Timeout);
en_result_t I2C_MasterReceiveAndStop(M4_I2C_TypeDef* I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout);
/**
* @}
*/
#endif /* DDL_I2C_ENABLE */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4A0_I2C_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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