replace file 'fsl_phy.c' to support LAN8720a

Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/Makefile

@@ -1,3 +1,3 @@
 SRC_FILES := enet_ethernetif.c enet_ethernetif_kinetis.c fsl_enet.c
-SRC_DIR := ksz8081
+SRC_DIR := lan8720
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/fsl_phy.c

@@ -1,28 +1,44 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2017 NXP
  * All rights reserved.
  * 
- * SPDX-License-Identifier: BSD-3-Clause
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/**
- * @file fsl_phy.c
- * @brief phy drivers for ksz8081
- * @version 1.0
- * @author AIIT XUOS Lab
- * @date 2021.11.11
- */
-
-#include "lwipopts.h"
 #include "fsl_phy.h"
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @brief Defines the timeout macro. */
-#define PHY_TIMEOUT_COUNT 100000
+#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
 
 /*******************************************************************************
  * Prototypes
@@ -57,7 +73,6 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
     status_t result = kStatus_Success;
     uint32_t instance = ENET_GetInstance(base);
     uint32_t timeDelay;
-    uint32_t ctlReg = 0;
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Set SMI first. */
@@ -82,19 +97,6 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
     result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
     if (result == kStatus_Success)
     {  
-#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE)
-        uint32_t data = 0;
-        result        = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
-        if (result != kStatus_Success)
-        {
-            return result;
-        }
-        result = PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK));
-        if (result != kStatus_Success)
-        {
-            return result;
-        }
-#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */
         
         /* Set the negotiation. */
         result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
@@ -102,8 +104,8 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
                             PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
         if (result == kStatus_Success)
         {
-            result =
+            result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG,
-                PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
+                               (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
             if (result == kStatus_Success)
             {
                 /* Check auto negotiation complete. */
@@ -112,8 +114,7 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
                     result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
                     if ( result == kStatus_Success)
                     {
-                        PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
+                        if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0)
-                        if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctlReg & PHY_LINK_READY_MASK))
                         {
                             /* Wait a moment for Phy status stable. */
                             for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++)
@@ -226,10 +227,10 @@ status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode,
         else
         {
             /* First read the current status in control register. */
-            result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
+            result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &data);
             if (result == kStatus_Success)
             {
-                return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK));
+                return PHY_Write(base, phyAddr, PHY_CONTROL1_REG, (data | PHY_CTL1_REMOTELOOP_MASK));
             }
         }
     }
@@ -249,10 +250,10 @@ status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode,
         else
         {
             /* First read the current status in control one register. */
-            result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
+            result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &data);
             if (result == kStatus_Success)
             {
-                return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK));
+                return PHY_Write(base, phyAddr, PHY_CONTROL1_REG, (data & ~PHY_CTL1_REMOTELOOP_MASK));
             }
         }
     }
@@ -291,7 +292,6 @@ status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *
     status_t result = kStatus_Success;
     uint32_t data, ctlReg;
 
-
     /* Read the control two register. */
     result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
     if (result == kStatus_Success)

Ubiquitous/XiZi/board/xidatong/third_party_driver/ethernet/lan8720/fsl_phy.h

@@ -1,19 +1,36 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
  * All rights reserved.
  * 
- * SPDX-License-Identifier: BSD-3-Clause
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
-
-/**
- * @file fsl_phy.h
- * @brief phy drivers for ksz8081
- * @version 1.0
- * @author AIIT XUOS Lab
- * @date 2021.11.11
- */
-
 #ifndef _FSL_PHY_H_
 #define _FSL_PHY_H_
 
@@ -37,10 +54,9 @@
 #define PHY_ID1_REG 0x02U               /*!< The PHY ID one register. */
 #define PHY_ID2_REG 0x03U               /*!< The PHY ID two register. */
 #define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
-#define PHY_CONTROL1_REG 0x1EU          /*!< The PHY control one register. */
+#define PHY_CONTROL1_REG 0x1FU          /*!< The PHY control one register. */
-#define PHY_CONTROL2_REG 0x1FU          /*!< The PHY control two register. */
 
-#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/
+#define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/
 
 /*! @brief Defines the mask flag in basic control register. */
 #define PHY_BCTL_DUPLEX_MASK 0x0100U          /*!< The PHY duplex bit mask. */
@@ -52,13 +68,13 @@
 #define PHY_BCTL_SPEED_100M_MASK  0x2000U     /*!< The PHY 100M speed mask. */
 
 /*!@brief Defines the mask flag of operation mode in control two register*/
-#define PHY_CTL2_REMOTELOOP_MASK 0x0004U    /*!< The PHY remote loopback mask. */
+#define PHY_CTL1_REMOTELOOP_MASK 0x0004U    /*!< The PHY remote loopback mask. */
-#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */
+//#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ 
-#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U  /*!< The PHY 10M half duplex mask. */
+#define PHY_CTL1_10HALFDUPLEX_MASK 0x0004U  /*!< The PHY 10M half duplex mask. */
-#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */
+#define PHY_CTL1_100HALFDUPLEX_MASK 0x0008U /*!< The PHY 100M half duplex mask. */
-#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U  /*!< The PHY 10M full duplex mask. */
+#define PHY_CTL1_10FULLDUPLEX_MASK 0x0014U  /*!< The PHY 10M full duplex mask. */
-#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */
+#define PHY_CTL1_100FULLDUPLEX_MASK 0x0018U /*!< The PHY 100M full duplex mask. */
-#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U     /*!< The PHY speed and duplex mask. */
+#define PHY_CTL1_SPEEDUPLX_MASK 0x001CU     /*!< The PHY speed and duplex mask. */
 #define PHY_CTL1_ENERGYDETECT_MASK 0x10U    /*!< The PHY signal present on rx differential pair. */
 #define PHY_CTL1_LINKUP_MASK 0x100U         /*!< The PHY link up. */        
 #define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)

Ubiquitous/XiZi/path_kernel.mk

@@ -14,7 +14,7 @@ KERNELPATHS :=-I$(BSP_ROOT) \
 	-I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/osa \
 	-I$(BSP_ROOT)/third_party_driver/usb/nxp_usb_driver/phy \
 	-I$(BSP_ROOT)/third_party_driver/ethernet \
-	-I$(BSP_ROOT)/third_party_driver/ethernet/ksz8081 \
+	-I$(BSP_ROOT)/third_party_driver/ethernet/lan8720 \
 	-I$(BSP_ROOT)/third_party_driver/MIMXRT1052 \
 	-I$(BSP_ROOT)/third_party_driver/MIMXRT1052/drivers \
 	-I$(BSP_ROOT)/third_party_driver/CMSIS/Include \