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feat modify XiUOS_Kernel dir from Ubiquitous/XiUOS to Ubiquitous/XiZi

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This commit is contained in:
Liu_Weichao
2022-03-01 14:15:01 +08:00
parent f45477ab2a
commit 5078ff66cc
2178 changed files with 431 additions and 434 deletions
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Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/Kconfig
Executable
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menuconfig BSP_USING_GPIO
bool "Using GPIO device"
default y
select RESOURCES_PIN
if BSP_USING_GPIO
source "$BSP_DIR/third_party_driver/gpio/Kconfig"
endif
menuconfig BSP_USING_SYSCLOCK
bool "Using SYSCLOCK device"
default y
if BSP_USING_SYSCLOCK
source "$BSP_DIR/third_party_driver/sys_clock/Kconfig"
endif
menuconfig BSP_USING_UART
bool "Using UART device"
default y
select RESOURCES_SERIAL
if BSP_USING_UART
source "$BSP_DIR/third_party_driver/uart/Kconfig"
endif
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/Makefile
Executable
+17
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@@ -0,0 +1,17 @@
SRC_FILES := fsl_intmux.c fsl_clock.c
SRC_DIR :=
ifeq ($(CONFIG_BSP_USING_GPIO),y)
SRC_DIR += gpio
endif
ifeq ($(CONFIG_BSP_USING_SYSCLOCK),y)
SRC_DIR += sys_clock
endif
ifeq ($(CONFIG_BSP_USING_UART),y)
SRC_DIR += uart
endif
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/fsl_clock.c
+805
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@@ -0,0 +1,805 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright (c) 2016 - 2017 , NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*************************************************
File name: fsl_clock
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#include "fsl_clock.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define SCG_SIRC_LOW_RANGE_FREQ 2000000U /* Slow IRC low range clock frequency. */
#define SCG_SIRC_HIGH_RANGE_FREQ 8000000U /* Slow IRC high range clock frequency. */
#define SCG_FIRC_FREQ0 48000000U /* Fast IRC trimed clock frequency(48MHz). */
#define SCG_FIRC_FREQ1 52000000U /* Fast IRC trimed clock frequency(52MHz). */
#define SCG_FIRC_FREQ2 56000000U /* Fast IRC trimed clock frequency(56MHz). */
#define SCG_FIRC_FREQ3 60000000U /* Fast IRC trimed clock frequency(60MHz). */
#define SCG_LPFLL_FREQ0 48000000U /* LPFLL trimed clock frequency(48MHz). */
#define SCG_LPFLL_FREQ1 72000000U /* LPFLL trimed clock frequency(72MHz). */
#define SCG_LPFLL_FREQ2 96000000U /* LPFLL trimed clock frequency(96MHz). */
#define SCG_LPFLL_FREQ3 120000000U /* LPFLL trimed clock frequency(120MHz). */
#define SCG_CSR_SCS_VAL ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT)
#define SCG_SOSCDIV_SOSCDIV1_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV1_MASK) >> SCG_SOSCDIV_SOSCDIV1_SHIFT)
#define SCG_SOSCDIV_SOSCDIV2_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV2_MASK) >> SCG_SOSCDIV_SOSCDIV2_SHIFT)
#define SCG_SOSCDIV_SOSCDIV3_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV3_MASK) >> SCG_SOSCDIV_SOSCDIV3_SHIFT)
#define SCG_SIRCDIV_SIRCDIV1_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV1_MASK) >> SCG_SIRCDIV_SIRCDIV1_SHIFT)
#define SCG_SIRCDIV_SIRCDIV2_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV2_SHIFT)
#define SCG_SIRCDIV_SIRCDIV3_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV3_MASK) >> SCG_SIRCDIV_SIRCDIV3_SHIFT)
#define SCG_FIRCDIV_FIRCDIV1_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV1_MASK) >> SCG_FIRCDIV_FIRCDIV1_SHIFT)
#define SCG_FIRCDIV_FIRCDIV2_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV2_MASK) >> SCG_FIRCDIV_FIRCDIV2_SHIFT)
#define SCG_FIRCDIV_FIRCDIV3_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV3_MASK) >> SCG_FIRCDIV_FIRCDIV3_SHIFT)
#define SCG_LPFLLDIV_LPFLLDIV1_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV1_MASK) >> SCG_LPFLLDIV_LPFLLDIV1_SHIFT)
#define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_LPFLLDIV2_SHIFT)
#define SCG_LPFLLDIV_LPFLLDIV3_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV3_MASK) >> SCG_LPFLLDIV_LPFLLDIV3_SHIFT)
#define SCG_SIRCCFG_RANGE_VAL ((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT)
#define SCG_FIRCCFG_RANGE_VAL ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT)
#define SCG_LPFLLCFG_FSEL_VAL ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT)
/* Get the value of each field in PCC register. */
#define PCC_PCS_VAL(reg) ((reg & PCC_CLKCFG_PCS_MASK) >> PCC_CLKCFG_PCS_SHIFT)
#define PCC_FRAC_VAL(reg) ((reg & PCC_CLKCFG_FRAC_MASK) >> PCC_CLKCFG_FRAC_SHIFT)
#define PCC_PCD_VAL(reg) ((reg & PCC_CLKCFG_PCD_MASK) >> PCC_CLKCFG_PCD_SHIFT)
/*******************************************************************************
* Variables
******************************************************************************/
/* External XTAL0 (OSC0) clock frequency. */
uint32_t g_xtal0Freq;
/* External XTAL32K clock frequency. */
uint32_t g_xtal32Freq;
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
uint32_t CLOCK_GetOsc32kClkFreq(void)
{
assert(g_xtal32Freq);
return g_xtal32Freq;
}
uint32_t CLOCK_GetFlashClkFreq(void)
{
return CLOCK_GetSysClkFreq(kSCG_SysClkSlow);
}
uint32_t CLOCK_GetBusClkFreq(void)
{
return CLOCK_GetSysClkFreq(kSCG_SysClkSlow);
}
uint32_t CLOCK_GetPlatClkFreq(void)
{
return CLOCK_GetSysClkFreq(kSCG_SysClkCore);
}
uint32_t CLOCK_GetCoreSysClkFreq(void)
{
return CLOCK_GetSysClkFreq(kSCG_SysClkCore);
}
uint32_t CLOCK_GetExtClkFreq(void)
{
return CLOCK_GetSysClkFreq(kSCG_SysClkExt);
}
uint32_t CLOCK_GetFreq(clock_name_t clockName)
{
uint32_t freq;
switch (clockName)
{
/* System layer clock. */
case kCLOCK_CoreSysClk:
case kCLOCK_PlatClk:
freq = CLOCK_GetSysClkFreq(kSCG_SysClkCore);
break;
case kCLOCK_BusClk:
freq = CLOCK_GetSysClkFreq(kSCG_SysClkBus);
break;
case kCLOCK_FlashClk:
freq = CLOCK_GetSysClkFreq(kSCG_SysClkSlow);
break;
case kCLOCK_ExtClk:
freq = CLOCK_GetSysClkFreq(kSCG_SysClkExt);
break;
/* Original clock source. */
case kCLOCK_ScgSysOscClk:
freq = CLOCK_GetSysOscFreq();
break;
case kCLOCK_ScgSircClk:
freq = CLOCK_GetSircFreq();
break;
case kCLOCK_ScgFircClk:
freq = CLOCK_GetFircFreq();
break;
case kCLOCK_ScgLpFllClk:
freq = CLOCK_GetLpFllFreq();
break;
/* SOSC div clock. */
case kCLOCK_ScgSysOscAsyncDiv1Clk:
freq = CLOCK_GetSysOscAsyncFreq(kSCG_AsyncDiv1Clk);
break;
case kCLOCK_ScgSysOscAsyncDiv2Clk:
freq = CLOCK_GetSysOscAsyncFreq(kSCG_AsyncDiv2Clk);
break;
case kCLOCK_ScgSysOscAsyncDiv3Clk:
freq = CLOCK_GetSysOscAsyncFreq(kSCG_AsyncDiv3Clk);
break;
/* SIRC div clock. */
case kCLOCK_ScgSircAsyncDiv1Clk:
freq = CLOCK_GetSircAsyncFreq(kSCG_AsyncDiv1Clk);
break;
case kCLOCK_ScgSircAsyncDiv2Clk:
freq = CLOCK_GetSircAsyncFreq(kSCG_AsyncDiv2Clk);
break;
case kCLOCK_ScgSircAsyncDiv3Clk:
freq = CLOCK_GetSircAsyncFreq(kSCG_AsyncDiv3Clk);
break;
/* FIRC div clock. */
case kCLOCK_ScgFircAsyncDiv1Clk:
freq = CLOCK_GetFircAsyncFreq(kSCG_AsyncDiv1Clk);
break;
case kCLOCK_ScgFircAsyncDiv2Clk:
freq = CLOCK_GetFircAsyncFreq(kSCG_AsyncDiv2Clk);
break;
case kCLOCK_ScgFircAsyncDiv3Clk:
freq = CLOCK_GetFircAsyncFreq(kSCG_AsyncDiv3Clk);
break;
/* LPFLL div clock. */
case kCLOCK_ScgSysLpFllAsyncDiv1Clk:
freq = CLOCK_GetLpFllAsyncFreq(kSCG_AsyncDiv1Clk);
break;
case kCLOCK_ScgSysLpFllAsyncDiv2Clk:
freq = CLOCK_GetLpFllAsyncFreq(kSCG_AsyncDiv2Clk);
break;
case kCLOCK_ScgSysLpFllAsyncDiv3Clk:
freq = CLOCK_GetLpFllAsyncFreq(kSCG_AsyncDiv3Clk);
break;
/* Other clocks. */
case kCLOCK_LpoClk:
freq = CLOCK_GetLpoClkFreq();
break;
case kCLOCK_Osc32kClk:
freq = CLOCK_GetOsc32kClkFreq();
break;
default:
freq = 0U;
break;
}
return freq;
}
uint32_t CLOCK_GetIpFreq(clock_ip_name_t name)
{
uint32_t reg = (*(volatile uint32_t *)name);
scg_async_clk_t asycClk;
uint32_t freq;
assert(reg & PCC_CLKCFG_PR_MASK);
switch (name)
{
case kCLOCK_Lpit0:
case kCLOCK_Lpit1:
asycClk = kSCG_AsyncDiv3Clk;
break;
case kCLOCK_Sdhc0:
case kCLOCK_Usb0:
asycClk = kSCG_AsyncDiv1Clk;
break;
default:
asycClk = kSCG_AsyncDiv2Clk;
break;
}
switch (PCC_PCS_VAL(reg))
{
case kCLOCK_IpSrcSysOscAsync:
freq = CLOCK_GetSysOscAsyncFreq(asycClk);
break;
case kCLOCK_IpSrcSircAsync:
freq = CLOCK_GetSircAsyncFreq(asycClk);
break;
case kCLOCK_IpSrcFircAsync:
freq = CLOCK_GetFircAsyncFreq(asycClk);
break;
case kCLOCK_IpSrcLpFllAsync:
freq = CLOCK_GetLpFllAsyncFreq(asycClk);
break;
default: /* kCLOCK_IpSrcNoneOrExt. */
freq = 0U;
break;
}
if (0U != (reg & (PCC_CLKCFG_PCD_MASK | PCC_CLKCFG_FRAC_MASK)))
{
return freq * (PCC_FRAC_VAL(reg) + 1U) / (PCC_PCD_VAL(reg) + 1U);
}
else
{
return freq;
}
}
bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
{
bool ret = true;
CLOCK_SetIpSrc(kCLOCK_Usb0, kCLOCK_IpSrcFircAsync);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable clock gate. */
CLOCK_EnableClock(kCLOCK_Usb0);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
USBVREG->CTRL |= USBVREG_CTRL_EN_MASK;
USB0->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;
if (kCLOCK_UsbSrcIrc48M == src)
{
USB0->CLK_RECOVER_IRC_EN = 0x03U;
USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
USB0->CLK_RECOVER_INT_EN = 0x00U;
}
return ret;
}
uint32_t CLOCK_GetSysClkFreq(scg_sys_clk_t type)
{
uint32_t freq;
scg_sys_clk_config_t sysClkConfig;
CLOCK_GetCurSysClkConfig(&sysClkConfig); /* Get the main clock for SoC platform. */
switch (sysClkConfig.src)
{
case kSCG_SysClkSrcSysOsc:
freq = CLOCK_GetSysOscFreq();
break;
case kSCG_SysClkSrcSirc:
freq = CLOCK_GetSircFreq();
break;
case kSCG_SysClkSrcFirc:
freq = CLOCK_GetFircFreq();
break;
case kSCG_SysClkSrcRosc:
freq = CLOCK_GetRtcOscFreq();
break;
case kSCG_SysClkSrcLpFll:
freq = CLOCK_GetLpFllFreq();
break;
default:
freq = 0U;
break;
}
freq /= (sysClkConfig.divCore + 1U); /* divided by the DIVCORE firstly. */
if (kSCG_SysClkSlow == type)
{
freq /= (sysClkConfig.divSlow + 1U);
}
else if (kSCG_SysClkBus == type)
{
freq /= (sysClkConfig.divBus + 1U);
}
else if (kSCG_SysClkExt == type)
{
freq /= (sysClkConfig.divExt + 1U);
}
else
{
}
return freq;
}
status_t CLOCK_InitSysOsc(const scg_sosc_config_t *config)
{
assert(config);
status_t status;
uint8_t tmp8;
/* De-init the SOSC first. */
status = CLOCK_DeinitSysOsc();
if (kStatus_Success != status)
{
return status;
}
/* Now start to set up OSC clock. */
/* Step 1. Setup dividers. */
SCG->SOSCDIV =
SCG_SOSCDIV_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2) | SCG_SOSCDIV_SOSCDIV3(config->div3);
/* Step 2. Set OSC configuration. */
/* Step 3. Enable clock. */
/* SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK | (config->enableMode); */
tmp8 = config->enableMode;
tmp8 |= SCG_SOSCCSR_SOSCEN_MASK;
SCG->SOSCCSR = tmp8;
/* Step 4. Wait for OSC clock to be valid. */
while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK))
{
}
/* Step 5. Enabe monitor. */
SCG->SOSCCSR |= (uint32_t)config->monitorMode;
return kStatus_Success;
}
status_t CLOCK_DeinitSysOsc(void)
{
uint32_t reg = SCG->SOSCCSR;
/* If clock is used by system, return error. */
if (reg & SCG_SOSCCSR_SOSCSEL_MASK)
{
return kStatus_SCG_Busy;
}
/* If configure register is locked, return error. */
if (reg & SCG_SOSCCSR_LK_MASK)
{
return kStatus_ReadOnly;
}
SCG->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK;
return kStatus_Success;
}
uint32_t CLOCK_GetSysOscFreq(void)
{
if (SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) /* System OSC clock is valid. */
{
/* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
assert(g_xtal0Freq);
return g_xtal0Freq;
}
else
{
return 0U;
}
}
uint32_t CLOCK_GetSysOscAsyncFreq(scg_async_clk_t type)
{
uint32_t oscFreq = CLOCK_GetSysOscFreq();
uint32_t divider = 0U;
/* Get divider. */
if (oscFreq)
{
switch (type)
{
case kSCG_AsyncDiv3Clk: /* SOSCDIV3_CLK. */
divider = SCG_SOSCDIV_SOSCDIV3_VAL;
break;
case kSCG_AsyncDiv2Clk: /* SOSCDIV2_CLK. */
divider = SCG_SOSCDIV_SOSCDIV2_VAL;
break;
case kSCG_AsyncDiv1Clk: /* SOSCDIV1_CLK. */
divider = SCG_SOSCDIV_SOSCDIV1_VAL;
break;
default:
break;
}
}
if (divider)
{
return oscFreq >> (divider - 1U);
}
else /* Output disabled. */
{
return 0U;
}
}
status_t CLOCK_InitSirc(const scg_sirc_config_t *config)
{
assert(config);
status_t status;
/* De-init the SIRC first. */
status = CLOCK_DeinitSirc();
if (kStatus_Success != status)
{
return status;
}
/* Now start to set up SIRC clock. */
/* Step 1. Setup dividers. */
SCG->SIRCDIV =
SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | SCG_SIRCDIV_SIRCDIV3(config->div3);
/* Step 2. Set SIRC configuration. */
SCG->SIRCCFG = SCG_SIRCCFG_RANGE(config->range);
/* Step 3. Enable clock. */
SCG->SIRCCSR = SCG_SIRCCSR_SIRCEN_MASK | config->enableMode;
/* Step 4. Wait for SIRC clock to be valid. */
while (!(SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK))
{
}
return kStatus_Success;
}
status_t CLOCK_DeinitSirc(void)
{
uint32_t reg = SCG->SIRCCSR;
/* If clock is used by system, return error. */
if (reg & SCG_SIRCCSR_SIRCSEL_MASK)
{
return kStatus_SCG_Busy;
}
/* If configure register is locked, return error. */
if (reg & SCG_SIRCCSR_LK_MASK)
{
return kStatus_ReadOnly;
}
SCG->SIRCCSR = 0U;
return kStatus_Success;
}
uint32_t CLOCK_GetSircFreq(void)
{
static const uint32_t sircFreq[] = {SCG_SIRC_LOW_RANGE_FREQ, SCG_SIRC_HIGH_RANGE_FREQ};
if (SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) /* SIRC is valid. */
{
return sircFreq[SCG_SIRCCFG_RANGE_VAL];
}
else
{
return 0U;
}
}
uint32_t CLOCK_GetSircAsyncFreq(scg_async_clk_t type)
{
uint32_t sircFreq = CLOCK_GetSircFreq();
uint32_t divider = 0U;
/* Get divider. */
if (sircFreq)
{
switch (type)
{
case kSCG_AsyncDiv3Clk: /* SIRCDIV3_CLK. */
divider = SCG_SIRCDIV_SIRCDIV3_VAL;
break;
case kSCG_AsyncDiv2Clk: /* SIRCDIV2_CLK. */
divider = SCG_SIRCDIV_SIRCDIV2_VAL;
break;
case kSCG_AsyncDiv1Clk: /* SIRCDIV2_CLK. */
divider = SCG_SIRCDIV_SIRCDIV1_VAL;
break;
default:
break;
}
}
if (divider)
{
return sircFreq >> (divider - 1U);
}
else /* Output disabled. */
{
return 0U;
}
}
status_t CLOCK_InitFirc(const scg_firc_config_t *config)
{
assert(config);
status_t status;
/* De-init the FIRC first. */
status = CLOCK_DeinitFirc();
if (kStatus_Success != status)
{
return status;
}
/* Now start to set up FIRC clock. */
/* Step 1. Setup dividers. */
SCG->FIRCDIV =
SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(config->div3);
/* Step 2. Set FIRC configuration. */
SCG->FIRCCFG = SCG_FIRCCFG_RANGE(config->range);
/* Step 3. Set trimming configuration. */
if (config->trimConfig)
{
SCG->FIRCTCFG =
SCG_FIRCTCFG_TRIMDIV(config->trimConfig->trimDiv) | SCG_FIRCTCFG_TRIMSRC(config->trimConfig->trimSrc);
/* TODO: Write FIRCSTAT cause bus error: TKT266932. */
if (kSCG_FircTrimNonUpdate == config->trimConfig->trimMode)
{
SCG->FIRCSTAT = SCG_FIRCSTAT_TRIMCOAR(config->trimConfig->trimCoar) |
SCG_FIRCSTAT_TRIMFINE(config->trimConfig->trimFine);
}
/* trim mode. */
SCG->FIRCCSR = config->trimConfig->trimMode;
if (SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK)
{
return kStatus_Fail;
}
}
/* Step 4. Enable clock. */
SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | SCG_FIRCCSR_FIRCTREN_MASK | config->enableMode);
/* Step 5. Wait for FIRC clock to be valid. */
while (!(SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK))
{
}
return kStatus_Success;
}
status_t CLOCK_DeinitFirc(void)
{
uint32_t reg = SCG->FIRCCSR;
/* If clock is used by system, return error. */
if (reg & SCG_FIRCCSR_FIRCSEL_MASK)
{
return kStatus_SCG_Busy;
}
/* If configure register is locked, return error. */
if (reg & SCG_FIRCCSR_LK_MASK)
{
return kStatus_ReadOnly;
}
SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK;
return kStatus_Success;
}
uint32_t CLOCK_GetFircFreq(void)
{
static const uint32_t fircFreq[] = {
SCG_FIRC_FREQ0, SCG_FIRC_FREQ1, SCG_FIRC_FREQ2, SCG_FIRC_FREQ3,
};
if (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) /* FIRC is valid. */
{
return fircFreq[SCG_FIRCCFG_RANGE_VAL];
}
else
{
return 0U;
}
}
uint32_t CLOCK_GetFircAsyncFreq(scg_async_clk_t type)
{
uint32_t fircFreq = CLOCK_GetFircFreq();
uint32_t divider = 0U;
/* Get divider. */
if (fircFreq)
{
switch (type)
{
case kSCG_AsyncDiv3Clk: /* FIRCDIV3_CLK. */
divider = SCG_FIRCDIV_FIRCDIV3_VAL;
break;
case kSCG_AsyncDiv2Clk: /* FIRCDIV2_CLK. */
divider = SCG_FIRCDIV_FIRCDIV2_VAL;
break;
case kSCG_AsyncDiv1Clk: /* FIRCDIV1_CLK. */
divider = SCG_FIRCDIV_FIRCDIV1_VAL;
break;
default:
break;
}
}
if (divider)
{
return fircFreq >> (divider - 1U);
}
else /* Output disabled. */
{
return 0U;
}
}
uint32_t CLOCK_GetRtcOscFreq(void)
{
if (SCG->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK) /* RTC OSC clock is valid. */
{
/* Please call CLOCK_SetXtal32Freq base on board setting before using RTC OSC clock. */
assert(g_xtal32Freq);
return g_xtal32Freq;
}
else
{
return 0U;
}
}
status_t CLOCK_InitLpFll(const scg_lpfll_config_t *config)
{
assert(config);
status_t status;
/* De-init the LPFLL first. */
status = CLOCK_DeinitLpFll();
if (kStatus_Success != status)
{
return status;
}
/* Now start to set up LPFLL clock. */
/* Step 1. Setup dividers. */
SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV1(config->div1) | SCG_LPFLLDIV_LPFLLDIV2(config->div2) |
SCG_LPFLLDIV_LPFLLDIV3(config->div3);
/* Step 2. Set LPFLL configuration. */
SCG->LPFLLCFG = SCG_LPFLLCFG_FSEL(config->range);
/* Step 3. Set trimming configuration. */
if (config->trimConfig)
{
SCG->LPFLLTCFG = SCG_LPFLLTCFG_TRIMDIV(config->trimConfig->trimDiv) |
SCG_LPFLLTCFG_TRIMSRC(config->trimConfig->trimSrc) |
SCG_LPFLLTCFG_LOCKW2LSB(config->trimConfig->lockMode);
if (kSCG_LpFllTrimNonUpdate == config->trimConfig->trimMode)
{
SCG->LPFLLSTAT = config->trimConfig->trimValue;
}
/* Trim mode. */
SCG->LPFLLCSR = config->trimConfig->trimMode;
if (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK)
{
return kStatus_Fail;
}
}
/* Step 4. Enable clock. */
SCG->LPFLLCSR |= (SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode);
/* Step 5. Wait for LPFLL clock to be valid. */
while (!(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK))
{
}
/* Step 6. Wait for LPFLL trim lock. */
if ((config->trimConfig) && (kSCG_LpFllTrimUpdate == config->trimConfig->trimMode))
{
while (!(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK))
{
}
}
return kStatus_Success;
}
status_t CLOCK_DeinitLpFll(void)
{
uint32_t reg = SCG->LPFLLCSR;
/* If clock is used by system, return error. */
if (reg & SCG_LPFLLCSR_LPFLLSEL_MASK)
{
return kStatus_SCG_Busy;
}
/* If configure register is locked, return error. */
if (reg & SCG_LPFLLCSR_LK_MASK)
{
return kStatus_ReadOnly;
}
SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK;
return kStatus_Success;
}
uint32_t CLOCK_GetLpFllFreq(void)
{
static const uint32_t lpfllFreq[] = {
SCG_LPFLL_FREQ0, SCG_LPFLL_FREQ1, SCG_LPFLL_FREQ2, SCG_LPFLL_FREQ3,
};
if (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) /* LPFLL is valid. */
{
return lpfllFreq[SCG_LPFLLCFG_FSEL_VAL];
}
else
{
return 0U;
}
}
uint32_t CLOCK_GetLpFllAsyncFreq(scg_async_clk_t type)
{
uint32_t lpfllFreq = CLOCK_GetLpFllFreq();
uint32_t divider = 0U;
/* Get divider. */
if (lpfllFreq)
{
switch (type)
{
case kSCG_AsyncDiv2Clk: /* LPFLLDIV2_CLK. */
divider = SCG_LPFLLDIV_LPFLLDIV2_VAL;
break;
case kSCG_AsyncDiv1Clk: /* LPFLLDIV1_CLK. */
divider = SCG_LPFLLDIV_LPFLLDIV1_VAL;
break;
default:
break;
}
}
if (divider)
{
return lpfllFreq >> (divider - 1U);
}
else /* Output disabled. */
{
return 0U;
}
}
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/fsl_common.c
+126
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@@ -0,0 +1,126 @@
/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*************************************************
File name: fsl_common
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#include "fsl_common.h"
// #include "fsl_debug_console.h"
#ifndef NDEBUG
#if (defined(__CC_ARM)) || (defined(__ICCARM__))
void __aeabi_assert(const char *failedExpr, const char *file, int line)
{
PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
for (;;)
{
__BKPT(0);
}
}
#elif(defined(__GNUC__))
void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
{
PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
for (;;)
{
__BKPT(0);
}
}
#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */
#endif /* NDEBUG */
#ifndef __GIC_PRIO_BITS
#ifndef __riscv
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
{
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
#if defined(__CC_ARM)
extern uint32_t Image$$VECTOR_ROM$$Base[];
extern uint32_t Image$$VECTOR_RAM$$Base[];
extern uint32_t Image$$RW_m_data$$Base[];
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
#elif defined(__ICCARM__)
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
#elif defined(__GNUC__)
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
#endif /* defined(__CC_ARM) */
uint32_t n;
uint32_t ret;
uint32_t irqMaskValue;
irqMaskValue = DisableGlobalIRQ();
if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
{
/* Copy the vector table from ROM to RAM */
for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
{
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
}
/* Point the VTOR to the position of vector table */
SCB->VTOR = (uint32_t)__VECTOR_RAM;
}
ret = __VECTOR_RAM[irq + 16];
/* make sure the __VECTOR_RAM is noncachable */
__VECTOR_RAM[irq + 16] = irqHandler;
EnableGlobalIRQ(irqMaskValue);
return ret;
}
#endif
#endif
#ifndef QN908XC_SERIES
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
void EnableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t index = 0;
uint32_t intNumber = (uint32_t)interrupt;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
SYSCON->STARTERSET[index] = 1u << intNumber;
EnableIRQ(interrupt); /* also enable interrupt at NVIC */
}
void DisableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t index = 0;
uint32_t intNumber = (uint32_t)interrupt;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
DisableIRQ(interrupt); /* also disable interrupt at NVIC */
SYSCON->STARTERCLR[index] = 1u << intNumber;
}
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
#endif /* QN908XC_SERIES */
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/fsl_intmux.c
+235
View File
@@ -0,0 +1,235 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*************************************************
File name: fsl_intmux
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#include "fsl_intmux.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get instance number for INTMUX.
*
* @param base INTMUX peripheral base address.
*/
static uint32_t INTMUX_GetInstance(INTMUX_Type *base);
#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT)
/*!
* @brief Handle INTMUX all channels IRQ.
*
* The handler reads the INTMUX channel's active vector register. This returns the offset
* from the start of the vector table to the vector for the INTMUX channel's highest priority
* pending source interrupt. After a check for spurious interrupts (an offset of 0), the
* function address at the vector offset is read and jumped to.
*
* @param base INTMUX peripheral base address.
* @param channel INTMUX channel number.
*/
static void INTMUX_CommonIRQHandler(INTMUX_Type *intmuxBase, uint32_t channel);
#endif
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Array to map INTMUX instance number to base pointer. */
static INTMUX_Type *const s_intmuxBases[] = INTMUX_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Array to map INTMUX instance number to clock name. */
static const clock_ip_name_t s_intmuxClockName[] = INTMUX_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT)
/*! @brief Array to map INTMUX instance number to IRQ number. */
static const IRQn_Type s_intmuxIRQNumber[][FSL_FEATURE_INTMUX_CHANNEL_COUNT] = INTMUX_IRQS;
#endif /* FSL_FEATURE_INTMUX_DIRECTION_OUT */
/*******************************************************************************
* Code
******************************************************************************/
static uint32_t INTMUX_GetInstance(INTMUX_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_intmuxBases); instance++)
{
if (s_intmuxBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_intmuxBases));
return instance;
}
#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT)
static void INTMUX_CommonIRQHandler(INTMUX_Type *intmuxBase, uint32_t channel)
{
uint32_t pendingIrqOffset;
pendingIrqOffset = intmuxBase->CHANNEL[channel].CHn_VEC;
if (pendingIrqOffset)
{
#if defined(__riscv)
extern uint32_t __user_vector[];
uint32_t isr = __user_vector[pendingIrqOffset / 4 - 48 + 32];
#else
uint32_t isr = *(uint32_t *)(SCB->VTOR + pendingIrqOffset);
#endif
((void (*)(void))isr)();
}
}
#endif /* FSL_FEATURE_INTMUX_DIRECTION_OUT */
void INTMUX_Init(INTMUX_Type *base)
{
uint32_t channel;
uint32_t instance = INTMUX_GetInstance(base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable clock gate. */
CLOCK_EnableClock(s_intmuxClockName[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Reset all channels and enable NVIC vectors for all INTMUX channels. */
for (channel = 0; channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT; channel++)
{
INTMUX_ResetChannel(base, channel);
#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT)
EnableIRQ(s_intmuxIRQNumber[instance][channel]);
#endif /* FSL_FEATURE_INTMUX_DIRECTION_OUT */
}
}
void INTMUX_Deinit(INTMUX_Type *base)
{
uint32_t channel;
uint32_t instance = INTMUX_GetInstance(base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disable clock gate. */
CLOCK_DisableClock(s_intmuxClockName[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Disable NVIC vectors for all of the INTMUX channels. */
for (channel = 0; channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT; channel++)
{
#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT)
DisableIRQ(s_intmuxIRQNumber[instance][channel]);
#endif /* FSL_FEATURE_INTMUX_DIRECTION_OUT */
}
}
#if !(defined(FSL_FEATURE_INTMUX_DIRECTION_OUT) && FSL_FEATURE_INTMUX_DIRECTION_OUT)
#if defined(INTMUX0)
void INTMUX0_0_DriverIRQHandler(void)
{
INTMUX_CommonIRQHandler(INTMUX0, 0);
}
void INTMUX0_1_DriverIRQHandler(void)
{
INTMUX_CommonIRQHandler(INTMUX0, 1);
}
void INTMUX0_2_DriverIRQHandler(void)
{
INTMUX_CommonIRQHandler(INTMUX0, 2);
}
void INTMUX0_3_DriverIRQHandler(void)
{
INTMUX_CommonIRQHandler(INTMUX0, 3);
}
#if defined(FSL_FEATURE_INTMUX_CHANNEL_COUNT) && (FSL_FEATURE_INTMUX_CHANNEL_COUNT > 4U)
void INTMUX0_4_DriverIRQHandler(void)
{
INTMUX_CommonIRQHandler(INTMUX0, 4);
}
void INTMUX0_5_DriverIRQHandler(void)
{
INTMUX_CommonIRQHandler(INTMUX0, 5);
}
void INTMUX0_6_DriverIRQHandler(void)
{
INTMUX_CommonIRQHandler(INTMUX0, 6);
}
void INTMUX0_7_DriverIRQHandler(void)
{
INTMUX_CommonIRQHandler(INTMUX0, 7);
}
#endif /* FSL_FEATURE_INTMUX_CHANNEL_COUNT */
#endif
#if defined(INTMUX1)
void INTMUX1_0_DriverIRQHandler(void)
{
INTMUX_CommonIRQHandler(INTMUX1, 0);
}
void INTMUX1_1_DriverIRQHandler(void)
{
INTMUX_CommonIRQHandler(INTMUX1, 1);
}
void INTMUX1_2_DriverIRQHandler(void)
{
INTMUX_CommonIRQHandler(INTMUX1, 2);
}
void INTMUX1_3_DriverIRQHandler(void)
{
INTMUX_CommonIRQHandler(INTMUX1, 3);
}
#if defined(FSL_FEATURE_INTMUX_CHANNEL_COUNT) && (FSL_FEATURE_INTMUX_CHANNEL_COUNT > 4U)
void INTMUX1_4_DriverIRQHandler(void)
{
INTMUX_CommonIRQHandler(INTMUX1, 4);
}
void INTMUX1_5_DriverIRQHandler(void)
{
INTMUX_CommonIRQHandler(INTMUX1, 5);
}
void INTMUX1_6_DriverIRQHandler(void)
{
INTMUX_CommonIRQHandler(INTMUX1, 6);
}
void INTMUX1_7_DriverIRQHandler(void)
{
INTMUX_CommonIRQHandler(INTMUX1, 7);
}
#endif /* FSL_FEATURE_INTMUX_CHANNEL_COUNT */
#endif /* INTMUX1 */
#endif /* FSL_FEATURE_INTMUX_DIRECTION_OUT */
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/gpio/Kconfig
Executable
+11
View File
@@ -0,0 +1,11 @@
config PIN_BUS_NAME
string "pin bus name"
default "pin"
config PIN_DRIVER_NAME
string "pin driver name"
default "pin_drv"
config PIN_DEVICE_NAME
string "pin device name"
default "pin_dev"
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/gpio/Makefile
Executable
+3
View File
@@ -0,0 +1,3 @@
SRC_FILES := pin_mux.c
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/gpio/pin_mux.c
+176
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@@ -0,0 +1,176 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v3.0
processor: RV32M1
package_id: RV32M1
mcu_data: ksdk2_0
processor_version: 0.0.0
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/*************************************************
File name: pin_mux
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#include "fsl_common.h"
#include "fsl_port.h"
#include "pin_mux.h"
/*FUNCTION**********************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
*END**************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
}
#define PIN6_IDX 6u /*!< Pin number for pin 6 in a port */
#define PIN7_IDX 7u /*!< Pin number for pin 7 in a port */
#define PIN8_IDX 8u /*!< Pin number for pin 8 in a port */
#define PIN9_IDX 9u /*!< Pin number for pin 9 in a port */
#define PIN10_IDX 10u /*!< Pin number for pin 10 in a port */
#define PIN11_IDX 11u /*!< Pin number for pin 11 in a port */
#define PIN22_IDX 22u /*!< Pin number for pin 22 in a port */
#define PIN23_IDX 23u /*!< Pin number for pin 23 in a port */
#define PIN24_IDX 24u /*!< Pin number for pin 24 in a port */
#define PIN25_IDX 25u /*!< Pin number for pin 25 in a port */
#define PIN26_IDX 26u /*!< Pin number for pin 26 in a port */
#define PIN27_IDX 27u /*!< Pin number for pin 27 in a port */
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: cm4, enableClock: 'true'}
- pin_list:
- {pin_num: N2, peripheral: LPUART0, signal: RX, pin_signal: LPCMP0_IN0/PTC7/LLWU_P15/LPSPI0_PCS3/LPUART0_RX/LPI2C1_HREQ/TPM0_CH0/LPTMR1_ALT1}
- {pin_num: P3, peripheral: LPUART0, signal: TX, pin_signal: LPCMP0_IN1/PTC8/LPSPI0_SCK/LPUART0_TX/LPI2C0_HREQ/TPM0_CH1}
- {pin_num: B5, peripheral: LPUART1, signal: RX, pin_signal: PTA25/LPUART1_RX/LPSPI3_SOUT/LPI2C2_SDAS/FB_AD31}
- {pin_num: A5, peripheral: LPUART1, signal: TX, pin_signal: PTA26/LPUART1_TX/LPSPI3_PCS2/LPI2C2_SCLS/FB_AD30}
- {pin_num: U11, peripheral: SDHC0, signal: CMD, pin_signal: ADC0_SE12/PTD9/SDHC0_CMD/LPSPI2_SIN/LPI2C1_SCLS/TRACE_DATA0/TPM2_CH2/FXIO0_D29, slew_rate: fast, open_drain: disable,
drive_strength: low, pull_select: up, pull_enable: enable}
- {pin_num: P10, peripheral: SDHC0, signal: 'DATA, 0', pin_signal: ADC0_SE10/PTD7/SDHC0_D0/LPSPI2_SOUT/EMVSIM0_PD/TRACE_DATA2/TPM2_CH4/FXIO0_D27, slew_rate: fast,
open_drain: disable, pull_select: up, pull_enable: enable}
- {pin_num: U9, peripheral: SDHC0, signal: 'DATA, 1', pin_signal: ADC0_SE9/PTD6/SDHC0_D1/LPSPI2_SCK/EMVSIM0_IO/TRACE_DATA3/TPM2_CH5/FXIO0_D26, slew_rate: fast,
open_drain: disable, pull_select: up, pull_enable: enable}
- {pin_num: R11, peripheral: SDHC0, signal: 'DATA, 2', pin_signal: ADC0_SE14/PTD11/SDHC0_D2/USB0_SOF_OUT/LPI2C1_SCL/CLKOUT/TPM2_CH0/FXIO0_D31, slew_rate: fast,
open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable}
- {pin_num: P11, peripheral: SDHC0, signal: 'DATA, 3', pin_signal: ADC0_SE13/PTD10/LLWU_P20/SDHC0_D3/LPSPI2_PCS0/LPI2C1_SDA/TRACE_CLK_OUT/TPM2_CH1/FXIO0_D30, slew_rate: fast,
open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable}
- {pin_num: T9, peripheral: SDHC0, signal: DCLK, pin_signal: ADC0_SE11/PTD8/LLWU_P19/SDHC0_DCLK/LPSPI2_PCS2/LPI2C1_SDAS/TRACE_DATA1/TPM2_CH3/FXIO0_D28, slew_rate: fast,
open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable}
- {pin_num: P6, peripheral: GPIOC, signal: 'GPIO, 27', pin_signal: PTC27/TPM0_CH4, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/*FUNCTION**********************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
*END**************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_PortA); /* Clock Gate Control: 0x01u */
CLOCK_EnableClock(kCLOCK_PortC); /* Clock Gate Control: 0x01u */
CLOCK_EnableClock(kCLOCK_PortD); /* Clock Gate Control: 0x01u */
const port_pin_config_t portc27_pinP6_config = {
kPORT_PullDisable, /* Internal pull-up/down resistor is disabled */
kPORT_FastSlewRate, /* Fast slew rate is configured */
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
kPORT_OpenDrainDisable, /* Open drain is disabled */
kPORT_LowDriveStrength, /* Low drive strength is configured */
kPORT_MuxAsGpio, /* Pin is configured as PTC27 */
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
};
PORT_SetPinConfig(PORTC, PIN27_IDX, &portc27_pinP6_config); /* PORTC27 (pin P6) is configured as PTC27 */
PORT_SetPinMux(PORTC, PIN7_IDX, kPORT_MuxAlt3); /* PORTC7 (pin N2) is configured as LPUART0_RX */
PORT_SetPinMux(PORTC, PIN8_IDX, kPORT_MuxAlt3); /* PORTC8 (pin P3) is configured as LPUART0_TX */
const port_pin_config_t portd10_pinP11_config = {
kPORT_PullUp, /* Internal pull-up resistor is enabled */
kPORT_FastSlewRate, /* Fast slew rate is configured */
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
kPORT_OpenDrainDisable, /* Open drain is disabled */
kPORT_LowDriveStrength, /* Low drive strength is configured */
kPORT_MuxAlt2, /* Pin is configured as SDHC0_D3 */
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
};
PORT_SetPinConfig(PORTD, PIN10_IDX, &portd10_pinP11_config); /* PORTD10 (pin P11) is configured as SDHC0_D3 */
const port_pin_config_t portd11_pinR11_config = {
kPORT_PullUp, /* Internal pull-up resistor is enabled */
kPORT_FastSlewRate, /* Fast slew rate is configured */
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
kPORT_OpenDrainDisable, /* Open drain is disabled */
kPORT_LowDriveStrength, /* Low drive strength is configured */
kPORT_MuxAlt2, /* Pin is configured as SDHC0_D2 */
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
};
PORT_SetPinConfig(PORTD, PIN11_IDX, &portd11_pinR11_config); /* PORTD11 (pin R11) is configured as SDHC0_D2 */
const port_pin_config_t portd6_pinU9_config = {
kPORT_PullUp, /* Internal pull-up resistor is enabled */
kPORT_FastSlewRate, /* Fast slew rate is configured */
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
kPORT_OpenDrainDisable, /* Open drain is disabled */
kPORT_LowDriveStrength, /* Low drive strength is configured */
kPORT_MuxAlt2, /* Pin is configured as SDHC0_D1 */
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
};
PORT_SetPinConfig(PORTD, PIN6_IDX, &portd6_pinU9_config); /* PORTD6 (pin U9) is configured as SDHC0_D1 */
const port_pin_config_t portd7_pinP10_config = {
kPORT_PullUp, /* Internal pull-up resistor is enabled */
kPORT_FastSlewRate, /* Fast slew rate is configured */
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
kPORT_OpenDrainDisable, /* Open drain is disabled */
kPORT_LowDriveStrength, /* Low drive strength is configured */
kPORT_MuxAlt2, /* Pin is configured as SDHC0_D0 */
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
};
PORT_SetPinConfig(PORTD, PIN7_IDX, &portd7_pinP10_config); /* PORTD7 (pin P10) is configured as SDHC0_D0 */
const port_pin_config_t portd8_pinT9_config = {
kPORT_PullUp, /* Internal pull-up resistor is enabled */
kPORT_FastSlewRate, /* Fast slew rate is configured */
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
kPORT_OpenDrainDisable, /* Open drain is disabled */
kPORT_LowDriveStrength, /* Low drive strength is configured */
kPORT_MuxAlt2, /* Pin is configured as SDHC0_DCLK */
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
};
PORT_SetPinConfig(PORTD, PIN8_IDX, &portd8_pinT9_config); /* PORTD8 (pin T9) is configured as SDHC0_DCLK */
const port_pin_config_t portd9_pinU11_config = {
kPORT_PullUp, /* Internal pull-up resistor is enabled */
kPORT_FastSlewRate, /* Fast slew rate is configured */
kPORT_PassiveFilterDisable, /* Passive filter is disabled */
kPORT_OpenDrainDisable, /* Open drain is disabled */
kPORT_LowDriveStrength, /* Low drive strength is configured */
kPORT_MuxAlt2, /* Pin is configured as SDHC0_CMD */
kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
};
PORT_SetPinConfig(PORTD, PIN9_IDX, &portd9_pinU11_config); /* PORTD9 (pin U11) is configured as SDHC0_CMD */
PORT_SetPinMux(PORTA, PIN22_IDX, kPORT_MuxAsGpio); /* PORTA22 (pin D6) is configured as PTA24 */
PORT_SetPinMux(PORTA, PIN23_IDX, kPORT_MuxAsGpio); /* PORTA23 (pin D6) is configured as PTA24 */
PORT_SetPinMux(PORTA, PIN24_IDX, kPORT_MuxAsGpio); /* PORTA24 (pin D6) is configured as PTA24 */
PORT_SetPinMux(PORTA, PIN25_IDX, kPORT_MuxAlt2); /* PORTA25 (pin B5) is configured as LPUART1_RX */
PORT_SetPinMux(PORTA, PIN26_IDX, kPORT_MuxAlt2); /* PORTA26 (pin A5) is configured as LPUART1_TX */
}
/*******************************************************************************
* EOF
******************************************************************************/
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/include/clock_config.h
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/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*************************************************
File name: clock_config
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
/*! @brief SCG set for BOARD_BootClockRUN configuration.
*/
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN;
/*! @brief System OSC set for BOARD_BootClockRUN configuration.
*/
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN;
/*! @brief SIRC set for BOARD_BootClockRUN configuration.
*/
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
/*! @brief FIRC set for BOARD_BootClockRUN configuration.
*/
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockRUN;
/*! @brief Low Power FLL set for BOARD_BootClockRUN configuration.
*/
extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************* Configuration BOARD_BootClockHSRUN **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockHSRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 72000000U /*!< Core clock frequency: 72000000Hz */
/*! @brief SCG set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN;
/*! @brief System OSC set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN;
/*! @brief SIRC set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
/*! @brief FIRC set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockHSRUN;
/*! @brief Low Power FLL set for BOARD_BootClockHSRUN configuration.
*/
extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockHSRUN;
/*******************************************************************************
* API for BOARD_BootClockHSRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockHSRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************* Configuration BOARD_BootClockVLPR ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockVLPR configuration
******************************************************************************/
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 4000000U /*!< Core clock frequency: 4000000Hz */
/*! @brief SCG set for BOARD_BootClockVLPR configuration.
*/
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR;
/*! @brief System OSC set for BOARD_BootClockVLPR configuration.
*/
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR;
/*! @brief SIRC set for BOARD_BootClockVLPR configuration.
*/
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
/*! @brief FIRC set for BOARD_BootClockVLPR configuration.
*/
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockVLPR;
/*! @brief Low Power FLL set for BOARD_BootClockVLPR configuration.
*/
extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockVLPR;
/*******************************************************************************
* API for BOARD_BootClockVLPR configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockVLPR(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/include/connect_uart.h
Executable
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_uart.h
* @brief define vega uart function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-02-16
*/
#ifndef CONNECT_UART_H
#define CONNECT_UART_H
#include <device.h>
#ifdef __cplusplus
extern "C" {
#endif
int InitHwUart(void);
#ifdef __cplusplus
}
#endif
#endif
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/include/fsl_clock.h
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Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/include/fsl_common.h
+494
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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*************************************************
File name: fsl_common
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#ifndef _FSL_COMMON_H_
#define _FSL_COMMON_H_
#include <assert.h>
#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#if defined(__ICCARM__)
#include <stddef.h>
#endif
#include "fsl_device_registers.h"
/*!
* @addtogroup ksdk_common
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Construct a status code value from a group and code number. */
#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
/*! @brief Construct the version number for drivers. */
#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
/*! @name Driver version */
/*@{*/
/*! @brief common driver version 2.0.0. */
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/* Debug console type definition. */
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */
/*! @brief Status group numbers. */
enum _status_groups
{
kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */
kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */
};
/*! @brief Generic status return codes. */
enum _generic_status
{
kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
};
/*! @brief Type used for all status and error return values. */
typedef int32_t status_t;
/*
* The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
* defined in previous of this file.
*/
#include "fsl_clock.h"
/*
* Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
*/
#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
#include "fsl_reset.h"
#endif
/*! @name Min/max macros */
/* @{ */
#if !defined(MIN)
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#endif
#if !defined(MAX)
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#endif
/* @} */
/*! @brief Computes the number of elements in an array. */
#if !defined(ARRAY_SIZE)
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#endif
/*! @name UINT16_MAX/UINT32_MAX value */
/* @{ */
#if !defined(UINT16_MAX)
#define UINT16_MAX ((uint16_t)-1)
#endif
#if !defined(UINT32_MAX)
#define UINT32_MAX ((uint32_t)-1)
#endif
/* @} */
/*! @name Timer utilities */
/* @{ */
/*! Macro to convert a microsecond period to raw count value */
#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
/*! Macro to convert a raw count value to microsecond */
#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
/*! Macro to convert a millisecond period to raw count value */
#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
/*! Macro to convert a raw count value to millisecond */
#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
/* @} */
/*! @name Alignment variable definition macros */
/* @{ */
#if (defined(__ICCARM__))
/**
* Workaround to disable MISRA C message suppress warnings for IAR compiler.
* http://supp.iar.com/Support/?note=24725
*/
_Pragma("diag_suppress=Pm120")
#define SDK_PRAGMA(x) _Pragma(#x)
_Pragma("diag_error=Pm120")
/*! Macro to define a variable with alignbytes alignment */
#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
/*! Macro to define a variable with L1 d-cache line size alignment */
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
#endif
/*! Macro to define a variable with L2 cache line size alignment */
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
#endif
#elif defined(__CC_ARM)
/*! Macro to define a variable with alignbytes alignment */
#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
/*! Macro to define a variable with L1 d-cache line size alignment */
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
#endif
/*! Macro to define a variable with L2 cache line size alignment */
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
#endif
#elif defined(__GNUC__)
/*! Macro to define a variable with alignbytes alignment */
#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
/*! Macro to define a variable with L1 d-cache line size alignment */
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
#endif
/*! Macro to define a variable with L2 cache line size alignment */
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
#endif
#else
#error Toolchain not supported
#define SDK_ALIGN(var, alignbytes) var
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
#define SDK_L1DCACHE_ALIGN(var) var
#endif
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
#define SDK_L2CACHE_ALIGN(var) var
#endif
#endif
/*! Macro to change a value to a given size aligned value */
#define SDK_SIZEALIGN(var, alignbytes) \
((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
/* @} */
/*! @name Non-cacheable region definition macros */
/* @{ */
#if (defined(__ICCARM__))
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
#else
#define AT_NONCACHEABLE_SECTION(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
#endif
#elif(defined(__CC_ARM))
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
__attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
#else
#define AT_NONCACHEABLE_SECTION(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
#endif
#elif(defined(__GNUC__))
/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
*/
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
__attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes)))
#else
#define AT_NONCACHEABLE_SECTION(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
#endif
#else
#error Toolchain not supported.
#define AT_NONCACHEABLE_SECTION(var) var
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
#endif
/* @} */
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Enable specific interrupt.
*
* Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
* levels. For example, there are NVIC and intmux. Here the interrupts connected
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
* to NVIC first then routed to core.
*
* This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
*
* @param interrupt The IRQ number.
* @retval kStatus_Success Interrupt enabled successfully
* @retval kStatus_Fail Failed to enable the interrupt
*/
static inline status_t EnableIRQ(IRQn_Type interrupt)
{
if (NotAvail_IRQn == interrupt)
{
return kStatus_Fail;
}
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
{
return kStatus_Fail;
}
#endif
#if defined(FSL_FEATURE_SOC_EVENT_COUNT) && (FSL_FEATURE_SOC_EVENT_COUNT > 0)
EVENT_UNIT->INTPTEN |= (uint32_t)(1 << interrupt);
/* Read back to make sure write finished. */
(void)EVENT_UNIT->INTPTEN;
#else
#if defined(__GIC_PRIO_BITS)
GIC_EnableIRQ(interrupt);
#else
NVIC_EnableIRQ(interrupt);
#endif
#endif
return kStatus_Success;
}
/*!
* @brief Disable specific interrupt.
*
* Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
* levels. For example, there are NVIC and intmux. Here the interrupts connected
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
* to NVIC first then routed to core.
*
* This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
*
* @param interrupt The IRQ number.
* @retval kStatus_Success Interrupt disabled successfully
* @retval kStatus_Fail Failed to disable the interrupt
*/
static inline status_t DisableIRQ(IRQn_Type interrupt)
{
if (NotAvail_IRQn == interrupt)
{
return kStatus_Fail;
}
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
{
return kStatus_Fail;
}
#endif
#if defined(FSL_FEATURE_SOC_EVENT_COUNT) && (FSL_FEATURE_SOC_EVENT_COUNT > 0)
EVENT_UNIT->INTPTEN &= ~(uint32_t)(1 << interrupt);
/* Read back to make sure write finished. */
(void)EVENT_UNIT->INTPTEN;
#else
#if defined(__GIC_PRIO_BITS)
GIC_DisableIRQ(interrupt);
#else
NVIC_DisableIRQ(interrupt);
#endif
#endif
return kStatus_Success;
}
/*!
* @brief Disable the global IRQ
*
* Disable the global interrupt and return the current primask register. User is required to provided the primask
* register for the EnableGlobalIRQ().
*
* @return Current primask value.
*/
static inline uint32_t DisableGlobalIRQ(void)
{
#ifndef __riscv
#if defined(CPSR_I_Msk)
uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
__disable_irq();
return cpsr;
#else
uint32_t regPrimask = __get_PRIMASK();
__disable_irq();
return regPrimask;
#endif
#else
uint32_t mstatus;
__ASM volatile ("csrrci %0, mstatus, 8" : "=r"(mstatus));
return mstatus;
#endif
}
/*!
* @brief Enaable the global IRQ
*
* Set the primask register with the provided primask value but not just enable the primask. The idea is for the
* convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
* use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
*
* @param primask value of primask register to be restored. The primask value is supposed to be provided by the
* DisableGlobalIRQ().
*/
static inline void EnableGlobalIRQ(uint32_t primask)
{
#ifndef __riscv
#if defined(CPSR_I_Msk)
__set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
#else
__set_PRIMASK(primask);
#endif
#else
__ASM volatile ("csrw mstatus, %0" : : "r"(primask));
#endif
}
/*!
* @brief install IRQ handler
*
* @param irq IRQ number
* @param irqHandler IRQ handler address
* @return The old IRQ handler address
*/
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
/*!
* @brief Enable specific interrupt for wake-up from deep-sleep mode.
*
* Enable the interrupt for wake-up from deep sleep mode.
* Some interrupts are typically used in sleep mode only and will not occur during
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
* those clocks (significantly increasing power consumption in the reduced power mode),
* making these wake-ups possible.
*
* @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
*
* @param interrupt The IRQ number.
*/
void EnableDeepSleepIRQ(IRQn_Type interrupt);
/*!
* @brief Disable specific interrupt for wake-up from deep-sleep mode.
*
* Disable the interrupt for wake-up from deep sleep mode.
* Some interrupts are typically used in sleep mode only and will not occur during
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
* those clocks (significantly increasing power consumption in the reduced power mode),
* making these wake-ups possible.
*
* @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
*
* @param interrupt The IRQ number.
*/
void DisableDeepSleepIRQ(IRQn_Type interrupt);
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
#if defined(__cplusplus)
}
#endif
/*! @} */
#endif /* _FSL_COMMON_H_ */
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/include/fsl_intmux.h
+173
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@@ -0,0 +1,173 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*************************************************
File name: fsl_intmux
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#ifndef _FSL_INTMUX_H_
#define _FSL_INTMUX_H_
#include "fsl_common.h"
/*!
* @addtogroup intmux
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*!< Version 2.0.1. */
#define FSL_INTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
/*! @brief INTMUX channel logic mode. */
typedef enum _intmux_channel_logic_mode
{
kINTMUX_ChannelLogicOR = 0x0U, /*!< Logic OR all enabled interrupt inputs */
kINTMUX_ChannelLogicAND, /*!< Logic AND all enabled interrupt inputs */
} intmux_channel_logic_mode_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*! @name Initialization and deinitialization */
/*@{*/
/*!
* @brief Initializes the INTMUX module.
*
* This function enables the clock gate for the specified INTMUX. It then resets all channels, so that no
* interrupt sources are routed and the logic mode is set to default of #kINTMUX_ChannelLogicOR.
* Finally, the NVIC vectors for all the INTMUX output channels are enabled.
*
* @param base INTMUX peripheral base address.
*/
void INTMUX_Init(INTMUX_Type *base);
/*!
* @brief Deinitializes an INTMUX instance for operation.
*
* The clock gate for the specified INTMUX is disabled and the NVIC vectors for all channels are disabled.
*
* @param base INTMUX peripheral base address.
*/
void INTMUX_Deinit(INTMUX_Type *base);
/*!
* @brief Resets an INTMUX channel.
*
* Sets all register values in the specified channel to their reset value. This function disables all interrupt
* sources for the channel.
*
* @param base INTMUX peripheral base address.
* @param channel The INTMUX channel number.
*/
static inline void INTMUX_ResetChannel(INTMUX_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
base->CHANNEL[channel].CHn_CSR |= INTMUX_CHn_CSR_RST_MASK;
}
/*!
* @brief Sets the logic mode for an INTMUX channel.
*
* INTMUX channels can be configured to use one of the two logic modes that control how pending interrupt sources
* on the channel trigger the output interrupt.
* - #kINTMUX_ChannelLogicOR means any source pending triggers the output interrupt.
* - #kINTMUX_ChannelLogicAND means all selected sources on the channel must be pending before the channel
* output interrupt triggers.
*
* @param base INTMUX peripheral base address.
* @param channel The INTMUX channel number.
* @param logic The INTMUX channel logic mode.
*/
static inline void INTMUX_SetChannelMode(INTMUX_Type *base, uint32_t channel, intmux_channel_logic_mode_t logic)
{
assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
base->CHANNEL[channel].CHn_CSR = INTMUX_CHn_CSR_AND(logic);
}
/*@}*/
/*! @name Sources */
/*@{*/
/*!
* @brief Enables an interrupt source on an INTMUX channel.
*
* @param base INTMUX peripheral base address.
* @param channel Index of the INTMUX channel on which the specified interrupt is enabled.
* @param irq Interrupt to route to the specified INTMUX channel. The interrupt must be an INTMUX source.
*/
static inline void INTMUX_EnableInterrupt(INTMUX_Type *base, uint32_t channel, IRQn_Type irq)
{
assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
assert(irq >= FSL_FEATURE_INTMUX_IRQ_START_INDEX);
base->CHANNEL[channel].CHn_IER_31_0 |= (1U << ((uint32_t)irq - FSL_FEATURE_INTMUX_IRQ_START_INDEX));
}
/*!
* @brief Disables an interrupt source on an INTMUX channel.
*
* @param base INTMUX peripheral base address.
* @param channel Index of the INTMUX channel on which the specified interrupt is disabled.
* @param irq Interrupt number. The interrupt must be an INTMUX source.
*/
static inline void INTMUX_DisableInterrupt(INTMUX_Type *base, uint32_t channel, IRQn_Type irq)
{
assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
assert(irq >= FSL_FEATURE_INTMUX_IRQ_START_INDEX);
base->CHANNEL[channel].CHn_IER_31_0 &= ~(1U << ((uint32_t)irq - FSL_FEATURE_INTMUX_IRQ_START_INDEX));
}
/*@}*/
/*! @name Status */
/*@{*/
/*!
* @brief Gets INTMUX pending interrupt sources for a specific channel.
*
* @param base INTMUX peripheral base address.
* @param channel The INTMUX channel number.
* @return The mask of pending interrupt bits. Bit[n] set means INTMUX source n is pending.
*/
static inline uint32_t INTMUX_GetChannelPendingSources(INTMUX_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT);
return base->CHANNEL[channel].CHn_IPR_31_0;
}
/*@}*/
#if defined(__cplusplus)
}
#endif
/*! @} */
#endif /* _FSL_INTMUX_H_ */
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/include/fsl_lpuart.h
+853
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@@ -0,0 +1,853 @@
/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*************************************************
File name: fsl_lpuart
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#ifndef _FSL_LPUART_H_
#define _FSL_LPUART_H_
#include "fsl_common.h"
/*!
* @addtogroup lpuart_driver
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief LPUART driver version 2.2.3. */
#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 4))
/*@}*/
/*! @brief Error codes for the LPUART driver. */
enum _lpuart_status
{
kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */
kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */
kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */
kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */
kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */
kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */
kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */
kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */
kStatus_LPUART_RxRingBufferOverrun =
MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */
kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */
kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */
kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */
kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */
kStatus_LPUART_BaudrateNotSupport =
MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */
kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */
};
/*! @brief LPUART parity mode. */
typedef enum _lpuart_parity_mode
{
kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */
kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */
} lpuart_parity_mode_t;
/*! @brief LPUART data bits count. */
typedef enum _lpuart_data_bits
{
kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */
#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */
#endif
} lpuart_data_bits_t;
/*! @brief LPUART stop bit count. */
typedef enum _lpuart_stop_bit_count
{
kLPUART_OneStopBit = 0U, /*!< One stop bit */
kLPUART_TwoStopBit = 1U, /*!< Two stop bits */
} lpuart_stop_bit_count_t;
#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
/*! @brief LPUART transmit CTS source. */
typedef enum _lpuart_transmit_cts_source
{
kLPUART_CtsSourcePin = 0U, /*!< CTS resource is the LPUART_CTS pin. */
kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */
} lpuart_transmit_cts_source_t;
/*! @brief LPUART transmit CTS configure. */
typedef enum _lpuart_transmit_cts_config
{
kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */
kLPUART_CtsSampleAtIdle = 1U, /*!< CTS input is sampled when the transmitter is idle */
} lpuart_transmit_cts_config_t;
#endif
/*! @brief LPUART idle flag type defines when the receiver starts counting. */
typedef enum _lpuart_idle_type_select
{
kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */
kLPUART_IdleTypeStopBit = 1U, /*!< Start conuting after a stop bit. */
} lpuart_idle_type_select_t;
/*! @brief LPUART idle detected configuration.
* This structure defines the number of idle characters that must be received before
* the IDLE flag is set.
*/
typedef enum _lpuart_idle_config
{
kLPUART_IdleCharacter1 = 0U, /*!< the number of idle characters. */
kLPUART_IdleCharacter2 = 1U, /*!< the number of idle characters. */
kLPUART_IdleCharacter4 = 2U, /*!< the number of idle characters. */
kLPUART_IdleCharacter8 = 3U, /*!< the number of idle characters. */
kLPUART_IdleCharacter16 = 4U, /*!< the number of idle characters. */
kLPUART_IdleCharacter32 = 5U, /*!< the number of idle characters. */
kLPUART_IdleCharacter64 = 6U, /*!< the number of idle characters. */
kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */
} lpuart_idle_config_t;
/*!
* @brief LPUART interrupt configuration structure, default settings all disabled.
*
* This structure contains the settings for all LPUART interrupt configurations.
*/
enum _lpuart_interrupt_enable
{
#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */
#endif
kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */
kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. */
kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */
kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. */
kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. */
kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. */
kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. */
kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. */
kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. */
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */
kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */
#endif
};
/*!
* @brief LPUART status flags.
*
* This provides constants for the LPUART status flags for use in the LPUART functions.
*/
enum _lpuart_flags
{
kLPUART_TxDataRegEmptyFlag =
(LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */
kLPUART_TransmissionCompleteFlag =
(LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */
kLPUART_RxDataRegFullFlag =
(LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */
kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */
kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is
read from receive register */
kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these
samples differ, noise flag sets */
kLPUART_FramingErrorFlag =
(LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */
kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */
#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char
detected and LIN circuit enabled */
#endif
kLPUART_RxActiveEdgeFlag =
(LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */
kLPUART_RxActiveFlag =
(LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */
#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/
kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/
#endif
#if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS
kLPUART_NoiseErrorInRxDataRegFlag =
(LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */
kLPUART_ParityErrorInRxDataRegFlag =
(LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITYE bit, sets if noise detected in current data word */
#endif
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */
kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */
kLPUART_TxFifoOverflowFlag =
(LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */
kLPUART_RxFifoUnderflowFlag =
(LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */
#endif
};
/*! @brief LPUART configuration structure. */
typedef struct _lpuart_config
{
uint32_t baudRate_Bps; /*!< LPUART baud rate */
lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */
bool isMsb; /*!< Data bits order, LSB (default), MSB */
#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
#endif
#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
uint8_t txFifoWatermark; /*!< TX FIFO watermark */
uint8_t rxFifoWatermark; /*!< RX FIFO watermark */
#endif
#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
bool enableRxRTS; /*!< RX RTS enable */
bool enableTxCTS; /*!< TX CTS enable */
lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */
lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */
#endif
lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */
lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */
bool enableTx; /*!< Enable TX */
bool enableRx; /*!< Enable RX */
} lpuart_config_t;
/*! @brief LPUART transfer structure. */
typedef struct _lpuart_transfer
{
uint8_t *data; /*!< The buffer of data to be transfer.*/
size_t dataSize; /*!< The byte count to be transfer. */
} lpuart_transfer_t;
/* Forward declaration of the handle typedef. */
typedef struct _lpuart_handle lpuart_handle_t;
/*! @brief LPUART transfer callback function. */
typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData);
/*! @brief LPUART handle structure. */
struct _lpuart_handle
{
uint8_t *volatile txData; /*!< Address of remaining data to send. */
volatile size_t txDataSize; /*!< Size of the remaining data to send. */
size_t txDataSizeAll; /*!< Size of the data to send out. */
uint8_t *volatile rxData; /*!< Address of remaining data to receive. */
volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
size_t rxDataSizeAll; /*!< Size of the data to receive. */
uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */
size_t rxRingBufferSize; /*!< Size of the ring buffer. */
volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
lpuart_transfer_callback_t callback; /*!< Callback function. */
void *userData; /*!< LPUART callback function parameter.*/
volatile uint8_t txState; /*!< TX transfer state. */
volatile uint8_t rxState; /*!< RX transfer state. */
#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
bool isSevenDataBits; /*!< Seven data bits flag. */
#endif
};
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* _cplusplus */
#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL
/*!
* @name Software Reset
* @{
*/
/*!
* @brief Resets the LPUART using software.
*
* This function resets all internal logic and registers except the Global Register.
* Remains set until cleared by software.
*
* @param base LPUART peripheral base address.
*/
static inline void LPUART_SoftwareReset(LPUART_Type *base)
{
base->GLOBAL |= LPUART_GLOBAL_RST_MASK;
base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
}
/* @} */
#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/
/*!
* @name Initialization and deinitialization
* @{
*/
/*!
* @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
*
* This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function
* to configure the configuration structure and get the default configuration.
* The example below shows how to use this API to configure the LPUART.
* @code
* lpuart_config_t lpuartConfig;
* lpuartConfig.baudRate_Bps = 115200U;
* lpuartConfig.parityMode = kLPUART_ParityDisabled;
* lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
* lpuartConfig.isMsb = false;
* lpuartConfig.stopBitCount = kLPUART_OneStopBit;
* lpuartConfig.txFifoWatermark = 0;
* lpuartConfig.rxFifoWatermark = 1;
* LPUART_Init(LPUART1, &lpuartConfig, 20000000U);
* @endcode
*
* @param base LPUART peripheral base address.
* @param config Pointer to a user-defined configuration structure.
* @param srcClock_Hz LPUART clock source frequency in HZ.
* @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source.
* @retval kStatus_Success LPUART initialize succeed
*/
status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz);
/*!
* @brief Deinitializes a LPUART instance.
*
* This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.
*
* @param base LPUART peripheral base address.
*/
void LPUART_Deinit(LPUART_Type *base);
/*!
* @brief Gets the default configuration structure.
*
* This function initializes the LPUART configuration structure to a default value. The default
* values are:
* lpuartConfig->baudRate_Bps = 115200U;
* lpuartConfig->parityMode = kLPUART_ParityDisabled;
* lpuartConfig->dataBitsCount = kLPUART_EightDataBits;
* lpuartConfig->isMsb = false;
* lpuartConfig->stopBitCount = kLPUART_OneStopBit;
* lpuartConfig->txFifoWatermark = 0;
* lpuartConfig->rxFifoWatermark = 1;
* lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit;
* lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1;
* lpuartConfig->enableTx = false;
* lpuartConfig->enableRx = false;
*
* @param config Pointer to a configuration structure.
*/
void LPUART_GetDefaultConfig(lpuart_config_t *config);
/*!
* @brief Sets the LPUART instance baudrate.
*
* This function configures the LPUART module baudrate. This function is used to update
* the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init.
* @code
* LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);
* @endcode
*
* @param base LPUART peripheral base address.
* @param baudRate_Bps LPUART baudrate to be set.
* @param srcClock_Hz LPUART clock source frequency in HZ.
* @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source.
* @retval kStatus_Success Set baudrate succeeded.
*/
status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
/* @} */
/*!
* @name Status
* @{
*/
/*!
* @brief Gets LPUART status flags.
*
* This function gets all LPUART status flags. The flags are returned as the logical
* OR value of the enumerators @ref _lpuart_flags. To check for a specific status,
* compare the return value with enumerators in the @ref _lpuart_flags.
* For example, to check whether the TX is empty:
* @code
* if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
* {
* ...
* }
* @endcode
*
* @param base LPUART peripheral base address.
* @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags.
*/
uint32_t LPUART_GetStatusFlags(LPUART_Type *base);
/*!
* @brief Clears status flags with a provided mask.
*
* This function clears LPUART status flags with a provided mask. Automatically cleared flags
* can't be cleared by this function.
* Flags that can only cleared or set by hardware are:
* kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag,
* kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
* kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag
* Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
*
* @param base LPUART peripheral base address.
* @param mask the status flags to be cleared. The user can use the enumerators in the
* _lpuart_status_flag_t to do the OR operation and get the mask.
* @return 0 succeed, others failed.
* @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but
* it is cleared automatically by hardware.
* @retval kStatus_Success Status in the mask are cleared.
*/
status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask);
/* @} */
/*!
* @name Interrupts
* @{
*/
/*!
* @brief Enables LPUART interrupts according to a provided mask.
*
* This function enables the LPUART interrupts according to a provided mask. The mask
* is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable.
* This examples shows how to enable TX empty interrupt and RX full interrupt:
* @code
* LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
* @endcode
*
* @param base LPUART peripheral base address.
* @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable.
*/
void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask);
/*!
* @brief Disables LPUART interrupts according to a provided mask.
*
* This function disables the LPUART interrupts according to a provided mask. The mask
* is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable.
* This example shows how to disable the TX empty interrupt and RX full interrupt:
* @code
* LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
* @endcode
*
* @param base LPUART peripheral base address.
* @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable.
*/
void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask);
/*!
* @brief Gets enabled LPUART interrupts.
*
* This function gets the enabled LPUART interrupts. The enabled interrupts are returned
* as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check
* a specific interrupt enable status, compare the return value with enumerators
* in @ref _lpuart_interrupt_enable.
* For example, to check whether the TX empty interrupt is enabled:
* @code
* uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);
*
* if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
* {
* ...
* }
* @endcode
*
* @param base LPUART peripheral base address.
* @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable.
*/
uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base);
#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE
/*!
* @brief Gets the LPUART data register address.
*
* This function returns the LPUART data register address, which is mainly used by the DMA/eDMA.
*
* @param base LPUART peripheral base address.
* @return LPUART data register addresses which are used both by the transmitter and receiver.
*/
static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base)
{
return (uint32_t) & (base->DATA);
}
/*!
* @brief Enables or disables the LPUART transmitter DMA request.
*
* This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests.
*
* @param base LPUART peripheral base address.
* @param enable True to enable, false to disable.
*/
static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable)
{
if (enable)
{
base->BAUD |= LPUART_BAUD_TDMAE_MASK;
base->CTRL |= LPUART_CTRL_TIE_MASK;
}
else
{
base->BAUD &= ~LPUART_BAUD_TDMAE_MASK;
base->CTRL &= ~LPUART_CTRL_TIE_MASK;
}
}
/*!
* @brief Enables or disables the LPUART receiver DMA.
*
* This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests.
*
* @param base LPUART peripheral base address.
* @param enable True to enable, false to disable.
*/
static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)
{
if (enable)
{
base->BAUD |= LPUART_BAUD_RDMAE_MASK;
base->CTRL |= LPUART_CTRL_RIE_MASK;
}
else
{
base->BAUD &= ~LPUART_BAUD_RDMAE_MASK;
base->CTRL &= ~LPUART_CTRL_RIE_MASK;
}
}
/* @} */
#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */
/*!
* @name Bus Operations
* @{
*/
/*!
* @brief Enables or disables the LPUART transmitter.
*
* This function enables or disables the LPUART transmitter.
*
* @param base LPUART peripheral base address.
* @param enable True to enable, false to disable.
*/
static inline void LPUART_EnableTx(LPUART_Type *base, bool enable)
{
if (enable)
{
base->CTRL |= LPUART_CTRL_TE_MASK;
}
else
{
base->CTRL &= ~LPUART_CTRL_TE_MASK;
}
}
/*!
* @brief Enables or disables the LPUART receiver.
*
* This function enables or disables the LPUART receiver.
*
* @param base LPUART peripheral base address.
* @param enable True to enable, false to disable.
*/
static inline void LPUART_EnableRx(LPUART_Type *base, bool enable)
{
if (enable)
{
base->CTRL |= LPUART_CTRL_RE_MASK;
}
else
{
base->CTRL &= ~LPUART_CTRL_RE_MASK;
}
}
/*!
* @brief Writes to the transmitter register.
*
* This function writes data to the transmitter register directly. The upper layer must
* ensure that the TX register is empty or that the TX FIFO has room before calling this function.
*
* @param base LPUART peripheral base address.
* @param data Data write to the TX register.
*/
static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data)
{
base->DATA = data;
}
/*!
* @brief Reads the receiver register.
*
* This function reads data from the receiver register directly. The upper layer must
* ensure that the receiver register is full or that the RX FIFO has data before calling this function.
*
* @param base LPUART peripheral base address.
* @return Data read from data register.
*/
static inline uint8_t LPUART_ReadByte(LPUART_Type *base)
{
#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
uint32_t ctrl = base->CTRL;
bool isSevenDataBits =
((ctrl & LPUART_CTRL_M7_MASK) ||
((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
if (isSevenDataBits)
{
return (base->DATA & 0x7F);
}
else
{
return base->DATA;
}
#else
return base->DATA;
#endif
}
/*!
* @brief Writes to the transmitter register using a blocking method.
*
* This function polls the transmitter register, waits for the register to be empty or for TX FIFO to have
* room, and writes data to the transmitter buffer.
*
* @note This function does not check whether all data has been sent out to the bus.
* Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is
* finished.
*
* @param base LPUART peripheral base address.
* @param data Start address of the data to write.
* @param length Size of the data to write.
*/
void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
/*!
* @brief Reads the receiver data register using a blocking method.
*
* This function polls the receiver register, waits for the receiver register full or receiver FIFO
* has data, and reads data from the TX register.
*
* @param base LPUART peripheral base address.
* @param data Start address of the buffer to store the received data.
* @param length Size of the buffer.
* @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
* @retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
* @retval kStatus_LPUART_FramingError Framing error happened while receiving data.
* @retval kStatus_LPUART_ParityError Parity error happened while receiving data.
* @retval kStatus_Success Successfully received all data.
*/
status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length);
/* @} */
/*!
* @name Transactional
* @{
*/
/*!
* @brief Initializes the LPUART handle.
*
* This function initializes the LPUART handle, which can be used for other LPUART
* transactional APIs. Usually, for a specified LPUART instance,
* call this API once to get the initialized handle.
*
* The LPUART driver supports the "background" receiving, which means that user can set up
* an RX ring buffer optionally. Data received is stored into the ring buffer even when the
* user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received
* in the ring buffer, the user can get the received data from the ring buffer directly.
* The ring buffer is disabled if passing NULL as @p ringBuffer.
*
* @param base LPUART peripheral base address.
* @param handle LPUART handle pointer.
* @param callback Callback function.
* @param userData User data.
*/
void LPUART_TransferCreateHandle(LPUART_Type *base,
lpuart_handle_t *handle,
lpuart_transfer_callback_t callback,
void *userData);
/*!
* @brief Transmits a buffer of data using the interrupt method.
*
* This function send data using an interrupt method. This is a non-blocking function, which
* returns directly without waiting for all data written to the transmitter register. When
* all data is written to the TX register in the ISR, the LPUART driver calls the callback
* function and passes the @ref kStatus_LPUART_TxIdle as status parameter.
*
* @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written
* to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX,
* check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.
*
* @param base LPUART peripheral base address.
* @param handle LPUART handle pointer.
* @param xfer LPUART transfer structure, see #lpuart_transfer_t.
* @retval kStatus_Success Successfully start the data transmission.
* @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register.
* @retval kStatus_InvalidArgument Invalid argument.
*/
status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer);
/*!
* @brief Sets up the RX ring buffer.
*
* This function sets up the RX ring buffer to a specific UART handle.
*
* When the RX ring buffer is used, data received is stored into the ring buffer even when
* the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
* in the ring buffer, the user can get the received data from the ring buffer directly.
*
* @note When using RX ring buffer, one byte is reserved for internal use. In other
* words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
*
* @param base LPUART peripheral base address.
* @param handle LPUART handle pointer.
* @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
* @param ringBufferSize size of the ring buffer.
*/
void LPUART_TransferStartRingBuffer(LPUART_Type *base,
lpuart_handle_t *handle,
uint8_t *ringBuffer,
size_t ringBufferSize);
/*!
* @brief Aborts the background transfer and uninstalls the ring buffer.
*
* This function aborts the background transfer and uninstalls the ring buffer.
*
* @param base LPUART peripheral base address.
* @param handle LPUART handle pointer.
*/
void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle);
/*!
* @brief Aborts the interrupt-driven data transmit.
*
* This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
* how many bytes are not sent out.
*
* @param base LPUART peripheral base address.
* @param handle LPUART handle pointer.
*/
void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle);
/*!
* @brief Gets the number of bytes that have been written to the LPUART transmitter register.
*
* This function gets the number of bytes that have been written to LPUART TX
* register by an interrupt method.
*
* @param base LPUART peripheral base address.
* @param handle LPUART handle pointer.
* @param count Send bytes count.
* @retval kStatus_NoTransferInProgress No send in progress.
* @retval kStatus_InvalidArgument Parameter is invalid.
* @retval kStatus_Success Get successfully through the parameter \p count;
*/
status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
/*!
* @brief Receives a buffer of data using the interrupt method.
*
* This function receives data using an interrupt method. This is a non-blocking function
* which returns without waiting to ensure that all data are received.
* If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
* the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
* After copying, if the data in the ring buffer is not enough for read, the receive
* request is saved by the LPUART driver. When the new data arrives, the receive request
* is serviced first. When all data is received, the LPUART driver notifies the upper layer
* through a callback function and passes a status parameter @ref kStatus_UART_RxIdle.
* For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer.
* The 5 bytes are copied to xfer->data, which returns with the
* parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is
* saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer.
* If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
* to receive data to xfer->data. When all data is received, the upper layer is notified.
*
* @param base LPUART peripheral base address.
* @param handle LPUART handle pointer.
* @param xfer LPUART transfer structure, see #uart_transfer_t.
* @param receivedBytes Bytes received from the ring buffer directly.
* @retval kStatus_Success Successfully queue the transfer into the transmit queue.
* @retval kStatus_LPUART_RxBusy Previous receive request is not finished.
* @retval kStatus_InvalidArgument Invalid argument.
*/
status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
lpuart_handle_t *handle,
lpuart_transfer_t *xfer,
size_t *receivedBytes);
/*!
* @brief Aborts the interrupt-driven data receiving.
*
* This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
* how many bytes not received yet.
*
* @param base LPUART peripheral base address.
* @param handle LPUART handle pointer.
*/
void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle);
/*!
* @brief Gets the number of bytes that have been received.
*
* This function gets the number of bytes that have been received.
*
* @param base LPUART peripheral base address.
* @param handle LPUART handle pointer.
* @param count Receive bytes count.
* @retval kStatus_NoTransferInProgress No receive in progress.
* @retval kStatus_InvalidArgument Parameter is invalid.
* @retval kStatus_Success Get successfully through the parameter \p count;
*/
status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
/*!
* @brief LPUART IRQ handle function.
*
* This function handles the LPUART transmit and receive IRQ request.
*
* @param base LPUART peripheral base address.
* @param handle LPUART handle pointer.
*/
void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle);
/*!
* @brief LPUART Error IRQ handle function.
*
* This function handles the LPUART error IRQ request.
*
* @param base LPUART peripheral base address.
* @param handle LPUART handle pointer.
*/
void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle);
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_LPUART_H_ */
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/include/fsl_msmc.h
+712
View File
@@ -0,0 +1,712 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*************************************************
File name: fsl_msmc
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#ifndef _FSL_MSMC_H_
#define _FSL_MSMC_H_
#include "fsl_common.h"
/*! @addtogroup msmc */
/*! @{*/
/*! @file */
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief MSMC driver version 2.1.0. */
#define FSL_MSMC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
/*@}*/
/*!
* @brief Power Modes Protection
*/
typedef enum _smc_power_mode_protection
{
kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-Low-Leakage Stop Mode. */
kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-Leakage Stop Mode. */
kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-Power Mode. */
kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High Speed Run mode. */
kSMC_AllowPowerModeAll = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK |
SMC_PMPROT_AHSRUN_MASK /*!< Allow all power mode. */
} smc_power_mode_protection_t;
/*!
* @brief Power Modes in PMSTAT
*/
typedef enum _smc_power_state
{
kSMC_PowerStateRun = 1U, /*!< 0000_0001 - Current power mode is RUN */
kSMC_PowerStateStop = 1U << 1U, /*!< 0000_0010 - Current power mode is any STOP mode */
kSMC_PowerStateVlpr = 1U << 2U, /*!< 0000_0100 - Current power mode is VLPR */
kSMC_PowerStateHsrun = 1U << 7U /*!< 1000_0000 - Current power mode is HSRUN */
} smc_power_state_t;
/*!
* @brief Power Stop Entry Status in PMSTAT
*/
typedef enum _smc_power_stop_entry_status
{
kSMC_PowerStopEntryAlt0 = 1U, /*!< Indicates a Stop mode entry since this field was last cleared. */
kSMC_PowerStopEntryAlt1 = 1U << 1, /*!< Indicates the system bus masters acknowledged the Stop mode entry. */
kSMC_PowerStopEntryAlt2 = 1U << 2, /*!< Indicates the system clock peripherals acknowledged the Stop mode entry. */
kSMC_PowerStopEntryAlt3 = 1U << 3, /*!< Indicates the bus clock peripherals acknowledged the Stop mode entry. */
kSMC_PowerStopEntryAlt4 = 1U << 4, /*!< Indicates the slow clock peripherals acknowledged the Stop mode entry. */
kSMC_PowerStopEntryAlt5 = 1U << 5, /*!< Indicates Stop mode entry completed. */
} smc_power_stop_entry_status_t;
/*!
* @brief Run mode definition
*/
typedef enum _smc_run_mode
{
kSMC_RunNormal = 0U, /*!< normal RUN mode. */
kSMC_RunVlpr = 2U, /*!< Very-Low-Power RUN mode. */
kSMC_Hsrun = 3U /*!< High Speed Run mode (HSRUN). */
} smc_run_mode_t;
/*!
* @brief Stop mode definition
*/
typedef enum _smc_stop_mode
{
kSMC_StopNormal = 0U, /*!< Normal STOP mode. */
kSMC_StopVlps = 2U, /*!< Very-Low-Power STOP mode. */
kSMC_StopLls = 3U, /*!< Low-Leakage Stop mode. */
#if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE)
#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2)
kSMC_StopVlls2 = 4U, /*!< Very-Low-Leakage Stop mode, VLPS2/3. */
#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 */
#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0)
kSMC_StopVlls0 = 6U, /*!< Very-Low-Leakage Stop mode, VLPS0/1. */
#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
#else
kSMC_StopVlls = 4U, /*!< Very-Low-Leakage Stop mode. */
#endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
} smc_stop_mode_t;
/*!
* @brief Partial STOP option
*/
typedef enum _smc_partial_stop_mode
{
kSMC_PartialStop = 0U, /*!< STOP - Normal Stop mode*/
kSMC_PartialStop1 = 1U, /*!< Partial Stop with both system and bus clocks disabled*/
kSMC_PartialStop2 = 2U, /*!< Partial Stop with system clock disabled and bus clock enabled*/
kSMC_PartialStop3 = 3U, /*!< Partial Stop with system clock enabled and bus clock disabled*/
} smc_partial_stop_option_t;
/*!
* @brief SMC configuration status
*/
enum _smc_status
{
kStatus_SMC_StopAbort = MAKE_STATUS(kStatusGroup_POWER, 0), /*!< Entering Stop mode is abort*/
};
/*!
* @brief System Reset Source Name definitions
*/
typedef enum _smc_reset_source
{
kSMC_SourceWakeup = SMC_SRS_WAKEUP_MASK, /*!< Very low-leakage wakeup reset */
kSMC_SourcePor = SMC_SRS_POR_MASK, /*!< Power on reset */
kSMC_SourceLvd = SMC_SRS_LVD_MASK, /*!< Low-voltage detect reset */
kSMC_SourceHvd = SMC_SRS_HVD_MASK, /*!< High-voltage detect reset */
kSMC_SourceWarm = SMC_SRS_WARM_MASK, /*!< Warm reset. Warm Reset flag will assert if any of the system reset
sources in this register assert (SRS[31:8]) */
kSMC_SourceFatal = SMC_SRS_FATAL_MASK, /*!< Fatal reset */
kSMC_SourceCore =
SMC_SRS_CORE_MASK, /*!< Software reset that only reset the core, NOT a sticky system reset source. */
kSMC_SourcePin = SMC_SRS_PIN_MASK, /*!< RESET_B pin reset. */
kSMC_SourceMdm = SMC_SRS_MDM_MASK, /*!< MDM reset. */
kSMC_SourceRstAck = SMC_SRS_RSTACK_MASK, /*!< Reset Controller timeout reset. */
kSMC_SourceStopAck = SMC_SRS_STOPACK_MASK, /*!< Stop timeout reset */
kSMC_SourceScg = SMC_SRS_SCG_MASK, /*!< SCG loss of lock or loss of clock */
kSMC_SourceWdog = SMC_SRS_WDOG_MASK, /*!< Watchdog reset */
kSMC_SourceSoftware = SMC_SRS_SW_MASK, /*!< Software reset */
kSMC_SourceLockup = SMC_SRS_LOCKUP_MASK, /*!< Lockup reset. Core lockup or exception. */
kSMC_SourceJtag = SMC_SRS_JTAG_MASK, /*!< JTAG system reset */
#if (defined(FSL_FEATURE_SMC_HAS_SRS_SECVIO) && FSL_FEATURE_SMC_HAS_SRS_SECVIO)
kSMC_SourceSecVio = SMC_SRS_SECVIO_MASK, /*!< Security violation reset */
#endif /* FSL_FEATURE_SMC_HAS_SRS_SECVIO */
#if (defined(FSL_FEATURE_SMC_HAS_SRS_TAMPER) && FSL_FEATURE_SMC_HAS_SRS_TAMPER)
kSMC_SourceTamper = SMC_SRS_TAMPER_MASK, /*!< Tamper reset */
#endif /* FSL_FEATURE_SMC_HAS_SRS_TAMPER */
#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE0) && FSL_FEATURE_SMC_HAS_SRS_CORE0)
kSMC_SourceCore0 = SMC_SRS_CORE0_MASK, /*!< Core0 System Reset. */
#endif /* FSL_FEATURE_SMC_HAS_SRS_CORE0 */
#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE1) && FSL_FEATURE_SMC_HAS_SRS_CORE1)
kSMC_SourceCore1 = SMC_SRS_CORE1_MASK, /*!< Core1 System Reset. */
#endif /* FSL_FEATURE_SMC_HAS_SRS_CORE1 */
/* Source All. */
kSMC_SourceAll = SMC_SRS_WAKEUP_MASK | SMC_SRS_POR_MASK | SMC_SRS_LVD_MASK | SMC_SRS_HVD_MASK | SMC_SRS_WARM_MASK |
SMC_SRS_FATAL_MASK | SMC_SRS_CORE_MASK | SMC_SRS_PIN_MASK | SMC_SRS_MDM_MASK |
SMC_SRS_RSTACK_MASK | SMC_SRS_STOPACK_MASK | SMC_SRS_SCG_MASK | SMC_SRS_WDOG_MASK |
SMC_SRS_SW_MASK | SMC_SRS_LOCKUP_MASK | SMC_SRS_JTAG_MASK
#if (defined(FSL_FEATURE_SMC_HAS_SRS_SECVIO) && FSL_FEATURE_SMC_HAS_SRS_SECVIO)
|
SMC_SRS_SECVIO_MASK
#endif /* FSL_FEATURE_SMC_HAS_SRS_SECVIO */
#if (defined(FSL_FEATURE_SMC_HAS_SRS_TAMPER) && FSL_FEATURE_SMC_HAS_SRS_TAMPER)
|
SMC_SRS_TAMPER_MASK
#endif /* FSL_FEATURE_SMC_HAS_SRS_TAMPER */
#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE0) && FSL_FEATURE_SMC_HAS_SRS_CORE0)
|
SMC_SRS_CORE0_MASK
#endif /* FSL_FEATURE_SMC_HAS_SRS_CORE0 */
#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE1) && FSL_FEATURE_SMC_HAS_SRS_CORE1)
|
SMC_SRS_CORE1_MASK
#endif /* FSL_FEATURE_SMC_HAS_SRS_CORE1 */
,
} smc_reset_source_t;
/*!
* @brief System reset interrupt enable bit definitions.
*/
typedef enum _smc_interrupt_enable
{
kSMC_IntNone = 0U, /*!< No interrupt enabled. */
kSMC_IntPin = SMC_SRIE_PIN_MASK, /*!< Pin reset interrupt. */
kSMC_IntMdm = SMC_SRIE_MDM_MASK, /*!< MDM reset interrupt. */
kSMC_IntStopAck = SMC_SRIE_STOPACK_MASK, /*!< Stop timeout reset interrupt. */
kSMC_IntWdog = SMC_SRIE_WDOG_MASK, /*!< Watchdog interrupt. */
kSMC_IntSoftware = SMC_SRIE_SW_MASK, /*!< Software reset interrupts. */
kSMC_IntLockup = SMC_SRIE_LOCKUP_MASK, /*!< Lock up interrupt. */
#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE0) && FSL_FEATURE_SMC_HAS_CSRE_CORE0)
kSMC_IntCore0 = SMC_SRIE_CORE0_MASK, /*! Core 0 interrupts. */
#endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE0 */
#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE1) && FSL_FEATURE_SMC_HAS_CSRE_CORE1)
kSMC_IntCore1 = SMC_SRIE_CORE1_MASK, /*! Core 1 interrupts. */
#endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE1 */
kSMC_IntAll = SMC_SRIE_PIN_MASK | /*!< All system reset interrupts. */
SMC_SRIE_MDM_MASK |
SMC_SRIE_STOPACK_MASK | SMC_SRIE_WDOG_MASK | SMC_SRIE_SW_MASK | SMC_SRIE_LOCKUP_MASK
#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE0) && FSL_FEATURE_SMC_HAS_CSRE_CORE0)
|
SMC_SRIE_CORE0_MASK
#endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE0 */
#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE1) && FSL_FEATURE_SMC_HAS_CSRE_CORE1)
|
SMC_SRIE_CORE1_MASK
#endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE1 */
} smc_interrupt_enable_t;
/*!
* @brief Reset pin filter configuration
*/
typedef struct _smc_reset_pin_filter_config
{
uint8_t slowClockFilterCount; /*!< Reset pin bus clock filter width from 1 to 32 slow clock cycles. */
bool enableFilter; /*!< Reset pin filter enable/disable. */
#if (defined(FSL_FEATURE_SMC_HAS_RPC_LPOFEN) && FSL_FEATURE_SMC_HAS_RPC_LPOFEN)
bool enableLpoFilter; /*!< LPO clock reset pin filter enabled in all modes. */
#endif /* FSL_FEATURE_SMC_HAS_RPC_LPOFEN */
} smc_reset_pin_filter_config_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*! @name System mode controller APIs*/
/*@{*/
/*!
* @brief Configures all power mode protection settings.
*
* This function configures the power mode protection settings for
* supported power modes in the specified chip family. The available power modes
* are defined in the smc_power_mode_protection_t. This should be done at an early
* system level initialization stage. See the reference manual for details.
* This register can only write once after the power reset.
*
* The allowed modes are passed as bit map, for example, to allow LLS and VLLS,
* use SMC_SetPowerModeProtection(kSMC_AllowPowerModeLls | kSMC_AllowPowerModeVlls).
* To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll).
*
* @param allowedModes Bitmap of the allowed power modes.
*/
static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedModes)
{
base->PMPROT = allowedModes;
}
/*!
* @brief Gets the current power mode status.
*
* This function returns the current power mode stat. Once application
* switches the power mode, it should always check the stat to check whether it
* runs into the specified mode or not. An application should check
* this mode before switching to a different mode. The system requires that
* only certain modes can switch to other specific modes. See the
* reference manual for details and the smc_power_state_t for information about
* the power stat.
*
* @param base SMC peripheral base address.
* @return Current power mode status.
*/
static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base)
{
return (smc_power_state_t)((base->PMSTAT & SMC_PMSTAT_PMSTAT_MASK) >> SMC_PMSTAT_PMSTAT_SHIFT);
}
#if (defined(FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT) && FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT)
/*!
* @brief Gets the result of the previous stop mode entry.
*
* This function returns the result of the previous stop mode entry.
*
* @param base SMC peripheral base address.
* @return Current power stop entry status.
*/
static inline smc_power_stop_entry_status_t SMC_GetStopEntryStatus(SMC_Type *base)
{
return (smc_power_stop_entry_status_t)((base->PMSTAT & SMC_PMSTAT_STOPSTAT_MASK) >> SMC_PMSTAT_STOPSTAT_SHIFT);
}
/*!
* @brief Clears all the result of the previous stop mode entry.
*
* This function clears all the result of the previous stop mode entry.
*
* @param base SMC peripheral base address.
* @return Current power stop entry status.
*/
static inline void SMC_ClearStopEntryStatus(SMC_Type *base)
{
/* Only write 0x01 to clear this field, all other writes are ignored. */
base->PMSTAT = (base->PMSTAT & ~SMC_PMSTAT_STOPSTAT_MASK) | SMC_PMSTAT_STOPSTAT(0x01);
}
#endif /* FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT */
/*!
* @brief Prepare to enter stop modes
*
* This function should be called before entering STOP/VLPS/LLS/VLLS modes.
*/
static inline void SMC_PreEnterStopModes(void)
{
__disable_irq();
__ISB();
}
/*!
* @brief Recovering after wake up from stop modes
*
* This function should be called after wake up from STOP/VLPS/LLS/VLLS modes.
* It is used together with @ref SMC_PreEnterStopModes.
*/
static inline void SMC_PostExitStopModes(void)
{
__enable_irq();
__ISB();
}
/*!
* @brief Prepare to enter wait modes
*
* This function should be called before entering WAIT/VLPW modes..
*/
static inline void SMC_PreEnterWaitModes(void)
{
__disable_irq();
__ISB();
}
/*!
* @brief Recovering after wake up from stop modes
*
* This function should be called after wake up from WAIT/VLPW modes.
* It is used together with @ref SMC_PreEnterWaitModes.
*/
static inline void SMC_PostExitWaitModes(void)
{
__enable_irq();
__ISB();
}
/*!
* @brief Configure the system to RUN power mode.
*
* @param base SMC peripheral base address.
* @return SMC configuration error code.
*/
status_t SMC_SetPowerModeRun(SMC_Type *base);
/*!
* @brief Configure the system to HSRUN power mode.
*
* @param base SMC peripheral base address.
* @return SMC configuration error code.
*/
status_t SMC_SetPowerModeHsrun(SMC_Type *base);
/*!
* @brief Configure the system to WAIT power mode.
*
* @param base SMC peripheral base address.
* @return SMC configuration error code.
*/
status_t SMC_SetPowerModeWait(SMC_Type *base);
/*!
* @brief Configure the system to Stop power mode.
*
* @param base SMC peripheral base address.
* @param option Partial Stop mode option.
* @return SMC configuration error code.
*/
status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option);
/*!
* @brief Configure the system to VLPR power mode.
*
* @param base SMC peripheral base address.
* @return SMC configuration error code.
*/
status_t SMC_SetPowerModeVlpr(SMC_Type *base);
/*!
* @brief Configure the system to VLPW power mode.
*
* @param base SMC peripheral base address.
* @return SMC configuration error code.
*/
status_t SMC_SetPowerModeVlpw(SMC_Type *base);
/*!
* @brief Configure the system to VLPS power mode.
*
* @param base SMC peripheral base address.
* @return SMC configuration error code.
*/
status_t SMC_SetPowerModeVlps(SMC_Type *base);
/*!
* @brief Configure the system to LLS power mode.
*
* @param base SMC peripheral base address.
* @return SMC configuration error code.
*/
status_t SMC_SetPowerModeLls(SMC_Type *base);
#if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE)
#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0)
/*!
* @brief Configure the system to VLLS0 power mode.
*
* @param base SMC peripheral base address.
* @return SMC configuration error code.
*/
status_t SMC_SetPowerModeVlls0(SMC_Type *base);
#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2)
/*!
* @brief Configure the system to VLLS2 power mode.
*
* @param base SMC peripheral base address.
* @return SMC configuration error code.
*/
status_t SMC_SetPowerModeVlls2(SMC_Type *base);
#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 */
#else
/*!
* @brief Configure the system to VLLS power mode.
*
* @param base SMC peripheral base address.
* @return SMC configuration error code.
*/
status_t SMC_SetPowerModeVlls(SMC_Type *base);
#endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
/*!
* @brief Gets the reset source status which caused a previous reset.
*
* This function gets the current reset source status. Use source masks
* defined in the smc_reset_source_t to get the desired source status.
*
* Example:
@code
uint32_t resetStatus;
// To get all reset source statuses.
resetStatus = SMC_GetPreviousResetSources(SMC0) & kSMC_SourceAll;
// To test whether the MCU is reset using Watchdog.
resetStatus = SMC_GetPreviousResetSources(SMC0) & kSMC_SourceWdog;
// To test multiple reset sources.
resetStatus = SMC_GetPreviousResetSources(SMC0) & (kSMC_SourceWdog | kSMC_SourcePin);
@endcode
*
* @param base SMC peripheral base address.
* @return All reset source status bit map.
*/
static inline uint32_t SMC_GetPreviousResetSources(SMC_Type *base)
{
return base->SRS;
}
/*!
* @brief Gets the sticky reset source status.
*
* This function gets the current reset source status that has not been cleared
* by software for some specific source.
*
* Example:
@code
uint32_t resetStatus;
// To get all reset source statuses.
resetStatus = SMC_GetStickyResetSources(SMC0) & kSMC_SourceAll;
// To test whether the MCU is reset using Watchdog.
resetStatus = SMC_GetStickyResetSources(SMC0) & kSMC_SourceWdog;
// To test multiple reset sources.
resetStatus = SMC_GetStickyResetSources(SMC0) & (kSMC_SourceWdog | kSMC_SourcePin);
@endcode
*
* @param base SMC peripheral base address.
* @return All reset source status bit map.
*/
static inline uint32_t SMC_GetStickyResetSources(SMC_Type *base)
{
return base->SSRS;
}
/*!
* @brief Clears the sticky reset source status.
*
* This function clears the sticky system reset flags indicated by source masks.
*
* Example:
@code
// Clears multiple reset sources.
SMC_ClearStickyResetSources(SMC0, (kSMC_SourceWdog | kSMC_SourcePin));
@endcode
*
* @param base SMC peripheral base address.
* @param sourceMasks reset source status bit map
*/
static inline void SMC_ClearStickyResetSources(SMC_Type *base, uint32_t sourceMasks)
{
base->SSRS = sourceMasks;
}
/*!
* @brief Configures the reset pin filter.
*
* This function sets the reset pin filter including the enablement/disablement and filter width.
*
* @param base SMC peripheral base address.
* @param config Pointer to the configuration structure.
*/
void SMC_ConfigureResetPinFilter(SMC_Type *base, const smc_reset_pin_filter_config_t *config);
/*!
* @brief Sets the system reset interrupt configuration.
*
* For a graceful shut down, the MSMC supports delaying the assertion of the system
* reset for a period of time when the reset interrupt is generated. This function
* can be used to enable the interrupt.
* The interrupts are passed in as bit mask. See smc_interrupt_enable_t for details.
* For example, to delay a reset after the WDOG timeout or PIN reset occurs, configure as follows:
* SMC_SetSystemResetInterruptConfig(SMC0, (kSMC_IntWdog | kSMC_IntPin));
*
* @param base SMC peripheral base address.
* @param intMask Bit mask of the system reset interrupts to enable. See
* smc_interrupt_enable_t for details.
*/
static inline void SMC_SetSystemResetInterruptConfig(SMC_Type *base, uint32_t intMask)
{
base->SRIE = intMask;
}
/*!
* @brief Gets the source status of the system reset interrupt.
*
* This function gets the source status of the reset interrupt. Use source masks
* defined in the smc_interrupt_enable_t to get the desired source status.
*
* Example:
@code
uint32_t interruptStatus;
// To get all reset interrupt source statuses.
interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & kSMC_IntAll;
// To test whether the reset interrupt of Watchdog is pending.
interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & kSMC_IntWdog;
// To test multiple reset interrupt sources.
interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & (kSMC_IntWdog | kSMC_IntPin);
@endcode
*
* @param base SMC peripheral base address.
* @return All reset interrupt source status bit map.
*/
static inline uint32_t SMC_GetResetInterruptSourcesStatus(SMC_Type *base)
{
return base->SRIF;
}
/*!
* @brief Clears the source status of the system reset interrupt.
*
* This function clears the source status of the reset interrupt. Use source masks
* defined in the smc_interrupt_enable_t to get the desired source status.
*
* Example:
@code
uint32_t interruptStatus;
// To clear all reset interrupt source statuses.
MMC_ClearResetInterruptSourcesStatus(SMC0, kSMC_IntAll);
// To clear the reset interrupt of Watchdog.
SMC_ClearResetInterruptSourcesStatus(SMC0, kSMC_IntWdog);
// To clear multiple reset interrupt sources status.
SMC_ClearResetInterruptSourcesStatus(SMC0, (kSMC_IntWdog | kSMC_IntPin));
@endcode
*
* @param base SMC peripheral base address.
* @param All reset interrupt source status bit map to clear.
*/
static inline void SMC_ClearResetInterruptSourcesStatus(SMC_Type *base, uint32_t intMask)
{
base->SRIF = intMask;
}
#if (defined(FSL_FEATURE_SMC_HAS_CSRE) && FSL_FEATURE_SMC_HAS_CSRE)
/*!
* @brief Sets the core software reset feature configuration.
*
* The MSMC supports delaying the assertion of the system reset for a period of time while a core
* software reset is generated. This allows software to recover without reseting the entire system.
* This function can be used to enable/disable the core software reset feature.
* The interrupts are passed in as bit mask. See smc_interrupt_enable_t for details.
* For example, to delay a system after the WDOG timeout or PIN core software reset occurs, configure as follows:
* SMC_SetCoreSoftwareResetConfig(SMC0, (kSMC_IntWdog | kSMC_IntPin));
*
* @param base SMC peripheral base address.
* @param intMask Bit mask of the core software reset to enable. See
* smc_interrupt_enable_t for details.
*/
static inline void SMC_SetCoreSoftwareResetConfig(SMC_Type *base, uint32_t intMask)
{
base->CSRE = intMask;
}
#endif /* FSL_FEATURE_SMC_HAS_CSRE */
/*!
* @brief Gets the boot option configuration.
*
* This function gets the boot option configuration of MSMC.
*
* @param base SMC peripheral base address.
* @return The boot option configuration. 1 means boot option enabled. 0 means not.
*/
static inline uint32_t SMC_GetBootOptionConfig(SMC_Type *base)
{
return base->MR;
}
#if (defined(FSL_FEATURE_SMC_HAS_FM) && FSL_FEATURE_SMC_HAS_FM)
/*!
* @brief Sets the force boot option configuration.
*
* This function sets the focus boot option configuration of MSMC. It can force the corresponding
* boot option config to assert on next system reset.
*
* @param base SMC peripheral base address.
* @param val The boot option configuration for next system reset. 1 - boot option enabled. 0 - not.
*/
static inline void SMC_SetForceBootOptionConfig(SMC_Type *base, uint32_t val)
{
base->FM = val;
}
#if (defined(FSL_FEATURE_SMC_HAS_SRAMLPR) && FSL_FEATURE_SMC_HAS_SRAMLPR)
/*!
* @brief Enables the conresponding SRAM array in low power retention mode.
*
* This function enables the conresponding SRAM array in low power retention mode. By default, the SRAM low pwer is
* disabled, and only in RUN mode.
*
* @param base SMC peripheral base address.
* @param arrayIdx Index of responding SRAM array.
* @param enable Enable the SRAM array in low power retention mode.
*/
static inline void SMC_SRAMEnableLowPowerMode(SMC_Type *base, uint32_t arrayIdx, bool enable)
{
if (enable)
{
base->SRAMLPR |= (1U << arrayIdx); /* Set to be placed in RUN modes. */
}
else
{
base->SRAMLPR &= ~(1U << arrayIdx); /* Clear to be placed in low power retention mode. */
}
}
#endif /* FSL_FEATURE_SMC_HAS_SRAMLPR */
#if (defined(FSL_FEATURE_SMC_HAS_SRAMDSR) && FSL_FEATURE_SMC_HAS_SRAMDSR)
/*!
* @brief Enables the conresponding SRAM array in STOP mode.
*
* This function enables the conresponding SRAM array in STOP modes. By default, the SRAM is retained in STOP modes.
* When disabled, the corresponding SRAM array is powered off in STOP modes.
*
* @param base SMC peripheral base address.
* @param arrayIdx Index of responding SRAM array.
* @param enable Enable the SRAM array in STOP modes.
*/
static inline void SMC_SRAMEnableDeepSleepMode(SMC_Type *base, uint32_t arrayIdx, bool enable)
{
if (enable)
{
base->SRAMDSR &= ~(1U << arrayIdx); /* Clear to be retained in STOP modes. */
}
else
{
base->SRAMDSR |= (1U << arrayIdx); /* Set to be powered off in STOP modes. */
}
}
#endif /* FSL_FEATURE_SMC_HAS_SRAMDSR */
#endif /* FSL_FEATURE_SMC_HAS_FM */
/*@}*/
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*! @}*/
#endif /* _FSL_MSMC_H_ */
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/include/fsl_port.h
+476
View File
@@ -0,0 +1,476 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*************************************************
File name: fsl_port
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#ifndef _FSL_PORT_H_
#define _FSL_PORT_H_
#include "fsl_common.h"
/*!
* @addtogroup port
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! Version 2.0.2. */
#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/
#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
/*! @brief Internal resistor pull feature selection */
enum _port_pull
{
kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */
kPORT_PullDown = 2U, /*!< Internal pull-down resistor is enabled. */
kPORT_PullUp = 3U, /*!< Internal pull-up resistor is enabled. */
};
#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
/*! @brief Slew rate selection */
enum _port_slew_rate
{
kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */
kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */
};
#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
/*! @brief Open Drain feature enable/disable */
enum _port_open_drain_enable
{
kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */
kPORT_OpenDrainEnable = 1U, /*!< Open drain output is enabled. */
};
#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
/*! @brief Passive filter feature enable/disable */
enum _port_passive_filter_enable
{
kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */
kPORT_PassiveFilterEnable = 1U, /*!< Passive input filter is enabled. */
};
#endif
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
/*! @brief Configures the drive strength. */
enum _port_drive_strength
{
kPORT_LowDriveStrength = 0U, /*!< Low-drive strength is configured. */
kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */
};
#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
/*! @brief Unlock/lock the pin control register field[15:0] */
enum _port_lock_register
{
kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */
};
#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
/*! @brief Pin mux selection */
typedef enum _port_mux
{
kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */
kPORT_MuxAsGpio = 1U, /*!< Corresponding pin is configured as GPIO. */
kPORT_MuxAlt2 = 2U, /*!< Chip-specific */
kPORT_MuxAlt3 = 3U, /*!< Chip-specific */
kPORT_MuxAlt4 = 4U, /*!< Chip-specific */
kPORT_MuxAlt5 = 5U, /*!< Chip-specific */
kPORT_MuxAlt6 = 6U, /*!< Chip-specific */
kPORT_MuxAlt7 = 7U, /*!< Chip-specific */
kPORT_MuxAlt8 = 8U, /*!< Chip-specific */
kPORT_MuxAlt9 = 9U, /*!< Chip-specific */
kPORT_MuxAlt10 = 10U, /*!< Chip-specific */
kPORT_MuxAlt11 = 11U, /*!< Chip-specific */
kPORT_MuxAlt12 = 12U, /*!< Chip-specific */
kPORT_MuxAlt13 = 13U, /*!< Chip-specific */
kPORT_MuxAlt14 = 14U, /*!< Chip-specific */
kPORT_MuxAlt15 = 15U, /*!< Chip-specific */
} port_mux_t;
#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
/*! @brief Configures the interrupt generation condition. */
typedef enum _port_interrupt
{
kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST
kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */
kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */
#endif
#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG
kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */
kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */
#endif
kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */
kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */
kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */
kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */
#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER
kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */
#endif
} port_interrupt_t;
#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
/*! @brief Digital filter clock source selection */
typedef enum _port_digital_filter_clock_source
{
kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */
kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */
} port_digital_filter_clock_source_t;
/*! @brief PORT digital filter feature configuration definition */
typedef struct _port_digital_filter_config
{
uint32_t digitalFilterWidth; /*!< Set digital filter width */
port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
} port_digital_filter_config_t;
#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
/*! @brief PORT pin configuration structure */
typedef struct _port_pin_config
{
#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */
#else
uint16_t : 2;
#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */
#else
uint16_t : 1;
#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
uint16_t : 1;
#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */
#else
uint16_t : 1;
#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */
#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */
#else
uint16_t : 1;
#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */
#else
uint16_t : 1;
#endif
uint16_t : 1;
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 3)
uint16_t mux : 3; /*!< Pin mux Configure */
uint16_t : 4;
#elif defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 4)
uint16_t mux : 4; /*!< Pin mux Configure */
uint16_t : 3;
#else
uint16_t : 7,
#endif
#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */
#else
uint16_t : 1;
#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
} port_pin_config_t;
#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
/*! @name Configuration */
/*@{*/
/*!
* @brief Sets the port PCR register.
*
* This is an example to define an input pin or output pin PCR configuration.
* @code
* // Define a digital input pin PCR configuration
* port_pin_config_t config = {
* kPORT_PullUp,
* kPORT_FastSlewRate,
* kPORT_PassiveFilterDisable,
* kPORT_OpenDrainDisable,
* kPORT_LowDriveStrength,
* kPORT_MuxAsGpio,
* kPORT_UnLockRegister,
* };
* @endcode
*
* @param base PORT peripheral base pointer.
* @param pin PORT pin number.
* @param config PORT PCR register configuration structure.
*/
static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
{
assert(config);
uint32_t addr = (uint32_t)&base->PCR[pin];
*(volatile uint16_t *)(addr) = *((const uint16_t *)config);
}
/*!
* @brief Sets the port PCR register for multiple pins.
*
* This is an example to define input pins or output pins PCR configuration.
* @code
* // Define a digital input pin PCR configuration
* port_pin_config_t config = {
* kPORT_PullUp ,
* kPORT_PullEnable,
* kPORT_FastSlewRate,
* kPORT_PassiveFilterDisable,
* kPORT_OpenDrainDisable,
* kPORT_LowDriveStrength,
* kPORT_MuxAsGpio,
* kPORT_UnlockRegister,
* };
* @endcode
*
* @param base PORT peripheral base pointer.
* @param mask PORT pin number macro.
* @param config PORT PCR register configuration structure.
*/
static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
{
assert(config);
uint16_t pcrl = *((const uint16_t *)config);
if (mask & 0xffffU)
{
base->GPCLR = ((mask & 0xffffU) << 16) | pcrl;
}
if (mask >> 16)
{
base->GPCHR = (mask & 0xffff0000U) | pcrl;
}
}
#if defined(FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG) && FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG
/*!
* @brief Sets the port interrupt configuration in PCR register for multiple pins.
*
* @param base PORT peripheral base pointer.
* @param mask PORT pin number macro.
* @param config PORT pin interrupt configuration.
* - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
* - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
* - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
* - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
* - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
* - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
* - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
* - #kPORT_InterruptLogicZero : Interrupt when logic zero.
* - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
* - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
* - #kPORT_InterruptEitherEdge : Interrupt on either edge.
* - #kPORT_InterruptLogicOne : Interrupt when logic one.
* - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
* - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit)..
*/
static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t mask, port_interrupt_t config)
{
assert(config);
if (mask & 0xffffU)
{
base->GICLR = (config << 16) | (mask & 0xffffU);
}
if (mask >> 16)
{
base->GICHR = (config << 16) | (mask & 0xffff0000U);
}
}
#endif
/*!
* @brief Configures the pin muxing.
*
* @param base PORT peripheral base pointer.
* @param pin PORT pin number.
* @param mux pin muxing slot selection.
* - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
* - #kPORT_MuxAsGpio : Set as GPIO.
* - #kPORT_MuxAlt2 : chip-specific.
* - #kPORT_MuxAlt3 : chip-specific.
* - #kPORT_MuxAlt4 : chip-specific.
* - #kPORT_MuxAlt5 : chip-specific.
* - #kPORT_MuxAlt6 : chip-specific.
* - #kPORT_MuxAlt7 : chip-specific.
* @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
* the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is
* reset to zero : kPORT_PinDisabledOrAnalog).
* This function is recommended to use to reset the pin mux
*
*/
static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
{
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
}
#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
/*!
* @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
*
* @param base PORT peripheral base pointer.
* @param mask PORT pin number macro.
*/
static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
{
if (enable == true)
{
base->DFER |= mask;
}
else
{
base->DFER &= ~mask;
}
}
/*!
* @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin.
*
* @param base PORT peripheral base pointer.
* @param config PORT digital filter configuration structure.
*/
static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
{
assert(config);
base->DFCR = PORT_DFCR_CS(config->clockSource);
base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
}
#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
/*@}*/
/*! @name Interrupt */
/*@{*/
/*!
* @brief Configures the port pin interrupt/DMA request.
*
* @param base PORT peripheral base pointer.
* @param pin PORT pin number.
* @param config PORT pin interrupt configuration.
* - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
* - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
* - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
* - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
* - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
* - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
* - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
* - #kPORT_InterruptLogicZero : Interrupt when logic zero.
* - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
* - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
* - #kPORT_InterruptEitherEdge : Interrupt on either edge.
* - #kPORT_InterruptLogicOne : Interrupt when logic one.
* - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
* - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).
*/
static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
{
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
}
#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
/*!
* @brief Configures the port pin drive strength.
*
* @param base PORT peripheral base pointer.
* @param pin PORT pin number.
* @param config PORT pin drive strength
* - #kPORT_LowDriveStrength = 0U - Low-drive strength is configured.
* - #kPORT_HighDriveStrength = 1U - High-drive strength is configured.
*/
static inline void PORT_SetPinDriveStrength(PORT_Type* base, uint32_t pin, uint8_t strength)
{
base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(strength);
}
#endif
/*!
* @brief Reads the whole port status flag.
*
* If a pin is configured to generate the DMA request, the corresponding flag
* is cleared automatically at the completion of the requested DMA transfer.
* Otherwise, the flag remains set until a logic one is written to that flag.
* If configured for a level sensitive interrupt that remains asserted, the flag
* is set again immediately.
*
* @param base PORT peripheral base pointer.
* @return Current port interrupt status flags, for example, 0x00010001 means the
* pin 0 and 16 have the interrupt.
*/
static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
{
return base->ISFR;
}
/*!
* @brief Clears the multiple pin interrupt status flag.
*
* @param base PORT peripheral base pointer.
* @param mask PORT pin number macro.
*/
static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
{
base->ISFR = mask;
}
/*@}*/
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_PORT_H_ */
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/include/pin_mux.h
+70
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@@ -0,0 +1,70 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*************************************************
File name: pin_mux
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Direction type */
typedef enum _pin_mux_direction
{
kPIN_MUX_DirectionInput = 0U, /* Input direction */
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
} pin_mux_direction_t;
/*!
* @addtogroup pin_mux
* @{
*/
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/*******************************************************************************
* EOF
******************************************************************************/
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/sys_clock/Kconfig
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Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/sys_clock/Makefile
Executable
+3
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SRC_FILES := clock_config.c
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/sys_clock/clock_config.c
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/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
* Note: The clock could not be set when it is being used as system clock.
* In default out of reset, the CPU is clocked from FIRC(IRC48M),
* so before setting FIRC, change to use another avaliable clock source.
*
* 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
*
* 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
* Wait until the system clock source is changed to target source.
*
* 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
* corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
* Supported run mode and clock restrictions could be found in Reference Manual.
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v3.0
processor: RV32M1
package_id: RV32M1
mcu_data: ksdk2_0
processor_version: 0.0.0
board: RV32M1_VEGA
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*************************************************
File name: clock_config
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#include "fsl_msmc.h"
#include "clock_config.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define SCG_LPFLL_DISABLE 0U /*!< LPFLL clock disabled */
#define SCG_SOSC_DISABLE 0U /*!< System OSC disabled */
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/*******************************************************************************
* Code
******************************************************************************/
#ifndef SDK_SECONDARY_CORE
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_CONFIG_FircSafeConfig
* Description : This function is used to safely configure FIRC clock.
* In default out of reset, the CPU is clocked from FIRC(IRC48M).
* Before setting FIRC, change to use SIRC as system clock,
* then configure FIRC.
* Param fircConfig : FIRC configuration.
*
*END**************************************************************************/
static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
{
scg_sys_clk_config_t curConfig;
const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
.div1 = kSCG_AsyncClkDisable,
.div2 = kSCG_AsyncClkDivBy2,
.range = kSCG_SircRangeHigh};
scg_sys_clk_config_t sysClkSafeConfigSource = {
.divSlow = kSCG_SysClkDivBy4, /* Slow clock divider. */
.divCore = kSCG_SysClkDivBy1, /* Core clock divider. */
.src = kSCG_SysClkSrcSirc /* System clock source. */
};
/* Init Sirc */
CLOCK_InitSirc(&scgSircConfig);
/* Change to use SIRC as system clock source to prepare to change FIRCCFG register */
CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
/* Wait for clock source switch finished */
do
{
CLOCK_GetCurSysClkConfig(&curConfig);
} while (curConfig.src != sysClkSafeConfigSource.src);
/* Init Firc */
CLOCK_InitFirc(fircConfig);
}
#endif
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: Bus_clock.outFreq, value: 48 MHz}
- {id: Core_clock.outFreq, value: 48 MHz}
- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
- {id: LPO_CLK.outFreq, value: 1 kHz}
- {id: Platform_clock.outFreq, value: 48 MHz}
- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
- {id: Slow_clock.outFreq, value: 24 MHz}
- {id: System_clock.outFreq, value: 48 MHz}
settings:
- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
- {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
- {id: SCG.LPFLLDIV1.scale, value: '1', locked: true}
- {id: SCG.LPFLLDIV3.scale, value: '0', locked: true}
- {id: SCG.SIRCDIV1.scale, value: '0', locked: true}
- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
{
.divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
.divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
.divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
.src = kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */
};
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
{
.freq = 0U, /* System Oscillator frequency: 0Hz */
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
};
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
{
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
.div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
};
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
{
.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
.div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
.div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
.trimConfig = NULL,
};
const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN =
{
.enableMode = SCG_LPFLL_DISABLE, /* LPFLL clock disabled */
.div1 = kSCG_AsyncClkDivBy1, /* Low Power FLL Clock Divider 1: divided by 1 */
.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
.range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
.trimConfig = NULL,
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
#ifndef SDK_SECONDARY_CORE
scg_sys_clk_config_t curConfig;
/* Init FIRC */
CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
/* Set SCG to FIRC mode. */
CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
/* Wait for clock source switch finished */
do
{
CLOCK_GetCurSysClkConfig(&curConfig);
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
/* Init SIRC */
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
/* Init LPFLL */
CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
#endif
}
/*******************************************************************************
********************* Configuration BOARD_BootClockHSRUN **********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockHSRUN
outputs:
- {id: Bus_clock.outFreq, value: 72 MHz}
- {id: Core_clock.outFreq, value: 72 MHz}
- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
- {id: LPO_CLK.outFreq, value: 1 kHz}
- {id: Platform_clock.outFreq, value: 72 MHz}
- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
- {id: Slow_clock.outFreq, value: 8 MHz}
- {id: System_clock.outFreq, value: 72 MHz}
settings:
- {id: SCGMode, value: LPFLL}
- {id: powerMode, value: HSRUN}
- {id: SCG.DIVCORE.scale, value: '1', locked: true}
- {id: SCG.DIVSLOW.scale, value: '9'}
- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
- {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
- {id: SCG.LPFLLDIV1.scale, value: '0', locked: true}
- {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
- {id: SCG.SCSSEL.sel, value: SCG.LPFLL}
- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
- {id: SCG.TRIMDIV.scale, value: '24'}
- {id: SCG.TRIMSRCSEL.sel, value: SCG.FIRC}
- {id: 'SCG::RCCR[SCS].bitField', value: '5'}
- {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockHSRUN configuration
******************************************************************************/
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN =
{
.divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
.divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
.divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
.src = kSCG_SysClkSrcLpFll, /* Low power FLL is selected as System Clock Source */
};
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN =
{
.freq = 0U, /* System Oscillator frequency: 0Hz */
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
};
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
{
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
.div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
};
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN =
{
.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
.div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
.div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
.trimConfig = NULL,
};
const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockHSRUN =
{
.enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
.div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
.range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
.trimConfig = NULL,
};
/*******************************************************************************
* Code for BOARD_BootClockHSRUN configuration
******************************************************************************/
void BOARD_BootClockHSRUN(void)
{
#ifndef SDK_SECONDARY_CORE
scg_sys_clk_config_t curConfig;
/* Init FIRC */
CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
/* Init LPFLL */
CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockHSRUN);
#if defined(CPU_RV32M1_cm4) || defined(CPU_RV32M1_ri5cy)
/* Set HSRUN power mode */
SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
SMC_SetPowerModeHsrun(SMC0);
while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateHsrun)
{
}
#elif defined(CPU_RV32M1_cm0plus) || defined(CPU_RV32M1_zero_riscy)
SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
SMC_SetPowerModeHsrun(SMC1);
while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateHsrun)
{
}
#endif
/* Set SCG to LPFLL mode. */
CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
/* Wait for clock source switch finished */
do
{
CLOCK_GetCurSysClkConfig(&curConfig);
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
/* Init SIRC */
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
#endif
}
/*******************************************************************************
********************* Configuration BOARD_BootClockVLPR ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockVLPR
outputs:
- {id: Bus_clock.outFreq, value: 2 MHz}
- {id: Core_clock.outFreq, value: 4 MHz}
- {id: LPO_CLK.outFreq, value: 1 kHz}
- {id: Platform_clock.outFreq, value: 4 MHz}
- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
- {id: SIRCDIV2_CLK.outFreq, value: 8 MHz}
- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
- {id: Slow_clock.outFreq, value: 4000/9 kHz}
- {id: System_clock.outFreq, value: 4 MHz}
settings:
- {id: SCGMode, value: SIRC}
- {id: powerMode, value: VLPR}
- {id: SCG.DIVBUS.scale, value: '2', locked: true}
- {id: SCG.DIVCORE.scale, value: '2', locked: true}
- {id: SCG.DIVSLOW.scale, value: '9'}
- {id: SCG.FIRCDIV1.scale, value: '1'}
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
- {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
- {id: SCG.SIRCDIV2.scale, value: '1', locked: true}
- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockVLPR configuration
******************************************************************************/
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
{
.divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
.divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */
.divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
.divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
.src = kSCG_SysClkSrcSirc, /* Slow IRC is selected as System Clock Source */
};
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
{
.freq = 0U, /* System Oscillator frequency: 0Hz */
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
};
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
{
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
.div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
.div2 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 2: divided by 1 */
.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
};
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
{
.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
.div2 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled */
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
.trimConfig = NULL,
};
const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockVLPR =
{
.enableMode = SCG_LPFLL_DISABLE, /* LPFLL clock disabled */
.div1 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 1: Clock output is disabled */
.div2 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 2: Clock output is disabled */
.div3 = kSCG_AsyncClkDisable, /* Low Power FLL Clock Divider 3: Clock output is disabled */
.range = kSCG_LpFllRange48M, /* LPFLL is trimmed to 48MHz */
.trimConfig = NULL,
};
/*******************************************************************************
* Code for BOARD_BootClockVLPR configuration
******************************************************************************/
void BOARD_BootClockVLPR(void)
{
#ifndef SDK_SECONDARY_CORE
scg_sys_clk_config_t curConfig;
/* Init SIRC */
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
/* Set SCG to SIRC mode. */
CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
/* Init FIRC */
CLOCK_InitFirc(&g_scgFircConfig_BOARD_BootClockVLPR);
/* Init LPFLL */
CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockVLPR);
#if defined(CPU_RV32M1_cm4) || defined(CPU_RV32M1_ri5cy)
/* Set VLPR power mode. */
SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC0);
while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateVlpr)
{
}
#elif defined(CPU_RV32M1_cm0plus) || defined(CPU_RV32M1_zero_riscy)
/* Set VLPR power mode. */
SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
SMC_SetPowerModeVlpr(SMC1);
while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateVlpr)
{
}
#endif
/* Wait for clock source switch finished */
do
{
CLOCK_GetCurSysClkConfig(&curConfig);
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockVLPR.src);
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
#endif
}
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/uart/Kconfig
Executable
+14
View File
@@ -0,0 +1,14 @@
menuconfig BSP_USING_UART0
bool "Enable UART0"
default y
if BSP_USING_UART0
config SERIAL_BUS_NAME_0
string "serial bus name"
default "uart0"
config SERIAL_DRV_NAME_0
string "serial bus driver name"
default "uart0_drv"
config SERIAL_0_DEVICE_NAME_0
string "serial bus device name"
default "uart0_dev0"
endif
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/uart/Makefile
Executable
+4
View File
@@ -0,0 +1,4 @@
SRC_FILES := connect_uart.c fsl_lpuart.c
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/uart/connect_uart.c
Executable
+342
View File
@@ -0,0 +1,342 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_usart.c
* @brief support vega-board uart function and register to bus framework
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-02-16
*/
#include <xizi.h>
#include <device.h>
#include <board.h>
#include "connect_uart.h"
#include "fsl_lpuart.h"
static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
{
struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
}
if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
}
if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
}
if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
}
if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
}
if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
}
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
}
static void UartIsr(struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
{
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.serial_register_base;
/* UART in mode Receiver */
if (LPUART_GetStatusFlags(uart_base) & kLPUART_RxDataRegFullFlag)
{
SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
}
/* If RX overrun. */
if (LPUART_STAT_OR_MASK & uart_base->STAT)
{
/* Clear overrun flag, otherwise the RX does not work. */
uart_base->STAT = ((uart_base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
}
}
static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
{
lpuart_config_t config;
NULL_PARAM_CHECK(serial_drv);
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
LPUART_GetDefaultConfig(&config);
config.baudRate_Bps = serial_cfg->data_cfg.serial_baud_rate;
switch (serial_cfg->data_cfg.serial_data_bits)
{
#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
case DATA_BITS_7:
config.dataBitsCount = kLPUART_SevenDataBits;
break;
#endif
default:
config.dataBitsCount = kLPUART_EightDataBits;
break;
}
switch (serial_cfg->data_cfg.serial_stop_bits)
{
case STOP_BITS_2:
config.stopBitCount = kLPUART_TwoStopBit;
break;
default:
config.stopBitCount = kLPUART_OneStopBit;
break;
}
switch (serial_cfg->data_cfg.serial_parity_mode)
{
case PARITY_ODD:
config.parityMode = kLPUART_ParityOdd;
break;
case PARITY_EVEN:
config.parityMode = kLPUART_ParityEven;
break;
default:
config.parityMode = kLPUART_ParityDisabled;
break;
}
config.enableTx = 1;
config.enableRx = 1;
CLOCK_SetIpSrc(kCLOCK_Lpuart0, kCLOCK_IpSrcFircAsync);
uint32_t uartClkSrcFreq0 = CLOCK_GetIpFreq(kCLOCK_Lpuart0);
LPUART_Init((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base, &config, uartClkSrcFreq0);
LPUART_EnableInterrupts((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base, kLPUART_RxDataRegFullInterruptEnable);
CLOCK_SetIpSrc(kCLOCK_Lpuart1, kCLOCK_IpSrcFircAsync);
uint32_t uartClkSrcFreq1 = CLOCK_GetIpFreq(kCLOCK_Lpuart1);
LPUART_Init((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base, &config, uartClkSrcFreq1);
LPUART_EnableInterrupts((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base, kLPUART_RxDataRegFullInterruptEnable);
return EOK;
}
static uint32 SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
{
NULL_PARAM_CHECK(serial_drv);
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
switch (serial_operation_cmd)
{
case OPER_CLR_INT:
DisableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt);
break;
case OPER_SET_INT:
EnableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt);
break;
}
return EOK;
}
static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
{
NULL_PARAM_CHECK(drv);
NULL_PARAM_CHECK(configure_info);
x_err_t ret = EOK;
int serial_operation_cmd;
struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = SerialInit(serial_drv, configure_info);
break;
case OPE_CFG:
serial_operation_cmd = *(int *)configure_info->private_data;
ret = SerialConfigure(serial_drv, serial_operation_cmd);
break;
default:
break;
}
return ret;
}
static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c)
{
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
LPUART_WriteByte((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base, (uint8_t) c);
while (!(LPUART_GetStatusFlags((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base) & kLPUART_TxDataRegEmptyFlag));
return 0;
}
static int SerialGetChar(struct SerialHardwareDevice *serial_dev)
{
int ch = -1;
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
if (LPUART_GetStatusFlags((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base) & kLPUART_RxDataRegFullFlag)
ch = LPUART_ReadByte((LPUART_Type *)serial_cfg->hw_cfg.serial_register_base);
return ch;
}
static const struct SerialDataCfg data_cfg_init =
{
.serial_baud_rate = BAUD_RATE_115200,
.serial_data_bits = DATA_BITS_8,
.serial_stop_bits = STOP_BITS_1,
.serial_parity_mode = PARITY_NONE,
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
};
/*manage the serial device operations*/
static const struct SerialDrvDone drv_done =
{
.init = SerialInit,
.configure = SerialConfigure,
};
/*manage the serial device hal operations*/
static struct SerialHwDevDone hwdev_done =
{
.put_char = SerialPutChar,
.get_char = SerialGetChar,
};
static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
{
x_err_t ret = EOK;
/*Init the serial bus */
ret = SerialBusInit(serial_bus, bus_name);
if (EOK != ret) {
KPrintf("InitHwUart SerialBusInit error %d\n", ret);
return -ERROR;
}
/*Init the serial driver*/
ret = SerialDriverInit(serial_driver, drv_name);
if (EOK != ret) {
KPrintf("InitHwUart SerialDriverInit error %d\n", ret);
return -ERROR;
}
/*Attach the serial driver to the serial bus*/
ret = SerialDriverAttachToBus(drv_name, bus_name);
if (EOK != ret) {
KPrintf("InitHwUart SerialDriverAttachToBus error %d\n", ret);
return -ERROR;
}
return ret;
}
/*Attach the serial device to the serial bus*/
static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
{
x_err_t ret = EOK;
ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
if (EOK != ret) {
KPrintf("InitHwUart SerialDeviceInit device %s error %d\n", dev_name, ret);
return ERROR;
}
ret = SerialDeviceAttachToBus(dev_name, bus_name);
if (EOK != ret) {
KPrintf("InitHwUart SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
return -ERROR;
}
return ret;
}
#ifdef BSP_USING_UART0
struct SerialDriver serial_driver_0;
struct SerialHardwareDevice serial_device_0;
void LPUART0_IRQHandler(int irq_num, void *arg)
{
UartIsr(&serial_driver_0, &serial_device_0);
}
#endif
int InitHwUart(void)
{
x_err_t ret = EOK;
#ifdef BSP_USING_UART0
static struct SerialBus serial_bus;
memset(&serial_bus, 0, sizeof(struct SerialBus));
memset(&serial_driver_0, 0, sizeof(struct SerialDriver));
memset(&serial_device_0, 0, sizeof(struct SerialHardwareDevice));
static struct SerialCfgParam serial_cfg;
memset(&serial_cfg, 0, sizeof(struct SerialCfgParam));
static struct SerialDevParam serial_dev_param;
memset(&serial_dev_param, 0, sizeof(struct SerialDevParam));
serial_driver_0.drv_done = &drv_done;
serial_driver_0.configure = &SerialDrvConfigure;
serial_device_0.hwdev_done = &hwdev_done;
serial_cfg.data_cfg = data_cfg_init;
serial_cfg.hw_cfg.serial_register_base = (uint32)LPUART0;
serial_cfg.hw_cfg.serial_irq_interrupt = LPUART0_IRQn;
serial_driver_0.private_data = (void *)&serial_cfg;
serial_dev_param.serial_work_mode = SIGN_OPER_INT_RX;
serial_device_0.haldev.private_data = (void *)&serial_dev_param;
ret = BoardSerialBusInit(&serial_bus, &serial_driver_0, SERIAL_BUS_NAME_0, SERIAL_DRV_NAME_0);
if (EOK != ret) {
KPrintf("InitHwUart uarths error ret %u\n", ret);
return -ERROR;
}
ret = BoardSerialDevBend(&serial_device_0, (void *)&serial_cfg, SERIAL_BUS_NAME_0, SERIAL_0_DEVICE_NAME_0);
if (EOK != ret) {
KPrintf("InitHwUart uarths error ret %u\n", ret);
return -ERROR;
}
#endif
return ret;
}
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/uart/fsl_lpuart.c
+1469
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