forked from xuos/xiuos
feat modify XiUOS_Kernel dir from Ubiquitous/XiUOS to Ubiquitous/XiZi
This commit is contained in:
Liu_Weichao
@@ -0,0 +1,11 @@
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config PIN_BUS_NAME
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string "pin bus name"
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default "pin"
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config PIN_DRIVER_NAME
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string "pin driver name"
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default "pin_drv"
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config PIN_DEVICE_NAME
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string "pin device name"
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default "pin_dev"
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@@ -0,0 +1,3 @@
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SRC_FILES := hardware_gpio.c
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include $(KERNEL_ROOT)/compiler.mk
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@@ -0,0 +1,218 @@
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/****************************************************************************
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* arch/risc-v/src/gap8/gap8_gpio.c
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* GAP8 FLL clock generator
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: hhuysqt <1020988872@qq.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* GAP8 has only 1 port. Each pin could be configured to GPIO or alternative
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* functions.
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****************************************************************************/
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/**
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* @file hardware_gpio.c
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* @brief add from Gap8 riscv SDK
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* https://greenwavesdev2.wpengine.com/sdk-manuals/
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* @version 1.1
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* @author AIIT XUOS Lab
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* @date 2021-09-02
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*/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "hardware_gpio.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: gap8_configpin
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*
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* Description:
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* Configure a pin based on bit-encoded description of the pin.
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*
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* GPIO software abstraction: bitmap configuration of pins
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*
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* |31 18| 17 | 16 | 15 |14 10|9 8|7 0|
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* | --- | drive | pull-up/OD | I/O | GPIOn | alt | pinnum |
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* | --- | 1-bit | 1-bit | 1-b | 5-bit | 2-bit | 8-bit |
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*
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* Returned Value:
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* OK on success
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* ERROR on invalid pin.
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*
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****************************************************************************/
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int gap8_configpin(uint32_t cfgset)
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{
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uint32_t pinnum = cfgset & 0xff;
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uint32_t altfunc = (cfgset >> 8) & 0x3;
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uint32_t pin_dr_pu = (cfgset >> 16) & 0x3;
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uint32_t port_cfg_reg;
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uint32_t pin_alt_reg;
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int shiftcnt;
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if (pinnum > MAX_PIN_NUM)
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{
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return -1;
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}
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/* Set pin drive strength (or pin speed in other words) and pulling
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* If it's a GPIO, set input or output.
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*
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* Note that GPIO and non-GPIO uses different register sets...
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* And all the GPIO functions are mapped to ALT-1, and ALT-1 contains
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* only GPIO functions...
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*/
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port_cfg_reg = PORTA->PADCFG[pinnum >> 2];
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shiftcnt = (pinnum & 0x3) << 3;
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port_cfg_reg &= ~(0x3 << shiftcnt);
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port_cfg_reg |= pin_dr_pu << shiftcnt;
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PORTA->PADCFG[pinnum >> 2] = port_cfg_reg;
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if (altfunc == 1)
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{
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uint32_t gpio_n = (cfgset >> 10) & 0x1f;
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uint32_t gpio_dir = (cfgset >> 15) & 0x1;
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uint32_t tmp;
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/* It must be a GPIO */
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GPIOA->EN |= (1L << gpio_n);
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tmp = GPIOA->PADCFG[gpio_n >> 2];
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shiftcnt = (gpio_n & 0x3) << 3;
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tmp &= ~(0x3 << shiftcnt);
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tmp |= pin_dr_pu << shiftcnt;
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GPIOA->PADCFG[gpio_n >> 2] = tmp;
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tmp = GPIOA->DIR;
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tmp &= ~(1L << gpio_n);
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tmp |= gpio_dir << gpio_n;
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GPIOA->DIR = tmp;
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}
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/* Set pin alternative function */
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pin_alt_reg = PORTA->PADFUN[pinnum >> 4];
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shiftcnt = (pinnum & 0xf) << 1;
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pin_alt_reg &= ~(0x3 << shiftcnt);
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pin_alt_reg |= altfunc << shiftcnt;
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PORTA->PADFUN[pinnum >> 4] = pin_alt_reg;
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return 0;
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}
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/****************************************************************************
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* Name: gap8_gpiowrite
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*
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* Description:
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* Write one or zero to the selected GPIO pin
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*
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* Bit encoded pinset:
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*
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* |31 15|14 10|9 0|
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* | --- | GPIOn | --- |
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* | --- | 5-bit | --- |
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*
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****************************************************************************/
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void gap8_gpiowrite(uint32_t pinset, bool value)
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{
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uint32_t gpio_n = (pinset >> 10) & 0x1f;
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if (value)
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{
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GPIOA->OUT |= (1L << gpio_n);
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}
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else
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{
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GPIOA->OUT &= ~(1L << gpio_n);
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}
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}
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/****************************************************************************
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* Name: gap8_gpioread
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*
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* Description:
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* Read one or zero from the selected GPIO pin
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*
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* Bit encoded pinset:
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*
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* |31 15|14 10|9 0|
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* | --- | GPIOn | --- |
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* | --- | 5-bit | --- |
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*
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****************************************************************************/
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bool gap8_gpioread(uint32_t pinset)
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{
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uint32_t gpio_n = (pinset >> 10) & 0x1f;
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return (GPIOA->IN >> gpio_n) & 0x1;
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}
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/****************************************************************************
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* Name: gap8_gpioirqset
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*
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* Description:
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* Enable or disable interrupt on GPIO
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*
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* Bit encoded pinset:
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*
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* |31 20|19 18|17 15|14 10|9 0|
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* | --- | int-typ | --- | GPIOn | --- |
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* | --- | 2-bit | --- | 5-bit | --- |
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*
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****************************************************************************/
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void gap8_gpioirqset(uint32_t pinset, bool enable)
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{
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uint32_t gpio_n = (pinset >> 10) & 0x1f;
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uint32_t int_type = (pinset >> 18) * 0x3;
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uint32_t tmp;
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uint32_t shitfcnt;
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if (enable)
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{
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shitfcnt = (gpio_n & 0xf) << 1;
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tmp = GPIOA->INTCFG[gpio_n >> 4];
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tmp &= ~(0x3 << shitfcnt);
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tmp |= int_type << shitfcnt;
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GPIOA->INTCFG[gpio_n >> 4] = tmp;
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GPIOA->INTEN |= (1L << gpio_n);
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}
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}
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