add DWC3 codes

Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c

@@ -20,3 +20,42 @@ enum usb_phy_interface usb_get_phy_mode(uint32_t id){
 
 
 
+int dwc3_setup_phy(void *dev, struct phy **array, int *num_phys){
+    return 0;
+}
+
+
+
+void dwc3_cache_hwparams(struct dwc3 *dwc){
+
+}
+
+
+
+int dwc3_core_init(struct dwc3 *dwc){
+    return 0;
+}
+
+
+
+int dwc3_event_buffers_setup(struct dwc3 *dwc){
+    return 0;
+}
+
+
+
+int dwc3_core_init_mode(struct dwc3 *dwc){
+    return 0;
+}
+
+
+
+void dwc3_set_mode(struct dwc3 *dwc, uint32_t mode){
+
+}
+
+
+
+int dwc3_init(struct dwc3 *dwc){
+    return 0;
+}

Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.h

@@ -7,6 +7,7 @@
 #include "xhci_reg.h"
 #include "xhci.h"
 #include "gadget.h"
+#include "usb_phy.h"
 
 #define DWC3_MSG_MAX	500
 
@@ -863,11 +864,21 @@ struct dwc3_gadget_ep_cmd_params {
 
 void dwc3_of_parse(struct dwc3 *dwc);
 
-
-int dwc3_host_init(struct dwc3 *dwc);
-
 enum usb_phy_interface usb_get_phy_mode(uint32_t id);
 
+int dwc3_setup_phy(void *dev, struct phy **array, int *num_phys);
 
+int dwc3_init(struct dwc3 *dwc);
 
+void dwc3_cache_hwparams(struct dwc3 *dwc);
+
+int dwc3_core_init(struct dwc3 *dwc);
+
+int dwc3_event_buffers_setup(struct dwc3 *dwc);
+
+int dwc3_core_init_mode(struct dwc3 *dwc);
+
+void dwc3_set_mode(struct dwc3 *dwc, uint32_t mode);
+
+int dwc3_host_init(struct dwc3 *dwc);
 #endif

Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.c

@@ -1 +1,12 @@
 #include "usb_phy.h"
+
+
+int generic_phy_init(struct phy *phy){
+    return 0;
+}
+
+
+
+int generic_phy_power_on(struct phy *phy){
+    return 0;
+}

Ubiquitous/XiZi_AIoT/services/drivers/usb/components/usb_phy/usb_phy.h

@@ -1,8 +1,515 @@
 #ifndef USB_PHY_H_
 #define USB_PHY_H_
 
+#include <stdint.h>
+#include <stdbool.h>
+
+
+enum phy_mode {
+    PHY_MODE_INVALID,
+    PHY_MODE_DP,
+};
+
+
+struct phy_attrs {
+	uint32_t			bus_width;
+	uint32_t			max_link_rate;
+	enum phy_mode		mode;
+};
+
+
+struct phy {
+    void                *dev;
+    uint32_t            id;
+    struct phy_attrs    attrs;
+};
 
 
 
+struct phy_configure_opts_mipi_dphy {
+	/**
+	 * @clk_miss:
+	 *
+	 * Timeout, in picoseconds, for receiver to detect absence of
+	 * Clock transitions and disable the Clock Lane HS-RX.
+	 *
+	 * Maximum value: 60000 ps
+	 */
+    unsigned int		clk_miss;
+
+	/**
+	 * @clk_post:
+	 *
+	 * Time, in picoseconds, that the transmitter continues to
+	 * send HS clock after the last associated Data Lane has
+	 * transitioned to LP Mode. Interval is defined as the period
+	 * from the end of @hs_trail to the beginning of @clk_trail.
+	 *
+	 * Minimum value: 60000 ps + 52 * @hs_clk_rate period in ps
+	 */
+    unsigned int		clk_post;
+
+	/**
+	 * @clk_pre:
+	 *
+	 * Time, in UI, that the HS clock shall be driven by
+	 * the transmitter prior to any associated Data Lane beginning
+	 * the transition from LP to HS mode.
+	 *
+	 * Minimum value: 8 UI
+	 */
+    unsigned int		clk_pre;
+
+	/**
+	 * @clk_prepare:
+	 *
+	 * Time, in picoseconds, that the transmitter drives the Clock
+	 * Lane LP-00 Line state immediately before the HS-0 Line
+	 * state starting the HS transmission.
+	 *
+	 * Minimum value: 38000 ps
+	 * Maximum value: 95000 ps
+	 */
+    unsigned int		clk_prepare;
+
+	/**
+	 * @clk_settle:
+	 *
+	 * Time interval, in picoseconds, during which the HS receiver
+	 * should ignore any Clock Lane HS transitions, starting from
+	 * the beginning of @clk_prepare.
+	 *
+	 * Minimum value: 95000 ps
+	 * Maximum value: 300000 ps
+	 */
+    unsigned int		clk_settle;
+
+	/**
+	 * @clk_term_en:
+	 *
+	 * Time, in picoseconds, for the Clock Lane receiver to enable
+	 * the HS line termination.
+	 *
+	 * Maximum value: 38000 ps
+	 */
+    unsigned int		clk_term_en;
+
+	/**
+	 * @clk_trail:
+	 *
+	 * Time, in picoseconds, that the transmitter drives the HS-0
+	 * state after the last payload clock bit of a HS transmission
+	 * burst.
+	 *
+	 * Minimum value: 60000 ps
+	 */
+    unsigned int		clk_trail;
+
+	/**
+	 * @clk_zero:
+	 *
+	 * Time, in picoseconds, that the transmitter drives the HS-0
+	 * state prior to starting the Clock.
+	 */
+    unsigned int		clk_zero;
+
+	/**
+	 * @d_term_en:
+	 *
+	 * Time, in picoseconds, for the Data Lane receiver to enable
+	 * the HS line termination.
+	 *
+	 * Maximum value: 35000 ps + 4 * @hs_clk_rate period in ps
+	 */
+    unsigned int		d_term_en;
+
+	/**
+	 * @eot:
+	 *
+	 * Transmitted time interval, in picoseconds, from the start
+	 * of @hs_trail or @clk_trail, to the start of the LP- 11
+	 * state following a HS burst.
+	 *
+	 * Maximum value: 105000 ps + 12 * @hs_clk_rate period in ps
+	 */
+    unsigned int		eot;
+
+	/**
+	 * @hs_exit:
+	 *
+	 * Time, in picoseconds, that the transmitter drives LP-11
+	 * following a HS burst.
+	 *
+	 * Minimum value: 100000 ps
+	 */
+    unsigned int		hs_exit;
+
+	/**
+	 * @hs_prepare:
+	 *
+	 * Time, in picoseconds, that the transmitter drives the Data
+	 * Lane LP-00 Line state immediately before the HS-0 Line
+	 * state starting the HS transmission.
+	 *
+	 * Minimum value: 40000 ps + 4 * @hs_clk_rate period in ps
+	 * Maximum value: 85000 ps + 6 * @hs_clk_rate period in ps
+	 */
+    unsigned int		hs_prepare;
+
+	/**
+	 * @hs_settle:
+	 *
+	 * Time interval, in picoseconds, during which the HS receiver
+	 * shall ignore any Data Lane HS transitions, starting from
+	 * the beginning of @hs_prepare.
+	 *
+	 * Minimum value: 85000 ps + 6 * @hs_clk_rate period in ps
+	 * Maximum value: 145000 ps + 10 * @hs_clk_rate period in ps
+	 */
+    unsigned int		hs_settle;
+
+	/**
+	 * @hs_skip:
+	 *
+	 * Time interval, in picoseconds, during which the HS-RX
+	 * should ignore any transitions on the Data Lane, following a
+	 * HS burst. The end point of the interval is defined as the
+	 * beginning of the LP-11 state following the HS burst.
+	 *
+	 * Minimum value: 40000 ps
+	 * Maximum value: 55000 ps + 4 * @hs_clk_rate period in ps
+	 */
+    unsigned int		hs_skip;
+
+	/**
+	 * @hs_trail:
+	 *
+	 * Time, in picoseconds, that the transmitter drives the
+	 * flipped differential state after last payload data bit of a
+	 * HS transmission burst
+	 *
+	 * Minimum value: max(8 * @hs_clk_rate period in ps,
+	 *		      60000 ps + 4 * @hs_clk_rate period in ps)
+	 */
+    unsigned int		hs_trail;
+
+	/**
+	 * @hs_zero:
+	 *
+	 * Time, in picoseconds, that the transmitter drives the HS-0
+	 * state prior to transmitting the Sync sequence.
+	 */
+    unsigned int		hs_zero;
+
+	/**
+	 * @init:
+	 *
+	 * Time, in picoseconds for the initialization period to
+	 * complete.
+	 *
+	 * Minimum value: 100000000 ps
+	 */
+    unsigned int		init;
+
+	/**
+	 * @lpx:
+	 *
+	 * Transmitted length, in picoseconds, of any Low-Power state
+	 * period.
+	 *
+	 * Minimum value: 50000 ps
+	 */
+    unsigned int		lpx;
+
+	/**
+	 * @ta_get:
+	 *
+	 * Time, in picoseconds, that the new transmitter drives the
+	 * Bridge state (LP-00) after accepting control during a Link
+	 * Turnaround.
+	 *
+	 * Value: 5 * @lpx
+	 */
+    unsigned int		ta_get;
+
+	/**
+	 * @ta_go:
+	 *
+	 * Time, in picoseconds, that the transmitter drives the
+	 * Bridge state (LP-00) before releasing control during a Link
+	 * Turnaround.
+	 *
+	 * Value: 4 * @lpx
+	 */
+    unsigned int		ta_go;
+
+	/**
+	 * @ta_sure:
+	 *
+	 * Time, in picoseconds, that the new transmitter waits after
+	 * the LP-10 state before transmitting the Bridge state
+	 * (LP-00) during a Link Turnaround.
+	 *
+	 * Minimum value: @lpx
+	 * Maximum value: 2 * @lpx
+	 */
+    unsigned int		ta_sure;
+
+	/**
+	 * @wakeup:
+	 *
+	 * Time, in picoseconds, that a transmitter drives a Mark-1
+	 * state prior to a Stop state in order to initiate an exit
+	 * from ULPS.
+	 *
+	 * Minimum value: 1000000000 ps
+	 */
+    unsigned int		wakeup;
+
+	/**
+	 * @hs_clk_rate:
+	 *
+	 * Clock rate, in Hertz, of the high-speed clock.
+	 */
+    unsigned long		hs_clk_rate;
+
+	/**
+	 * @lp_clk_rate:
+	 *
+	 * Clock rate, in Hertz, of the low-power clock.
+	 */
+    unsigned long		lp_clk_rate;
+
+	/**
+	 * @lanes:
+	 *
+	 * Number of active data lanes used for the transmissions.
+	 */
+    unsigned char		lanes;
+};
+
+
+struct phy_configure_opts_dp {
+	/**
+	 * @link_rate:
+	 *
+	 * Link Rate, in Mb/s, of the main link.
+	 *
+	 * Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s
+	 */
+    unsigned int link_rate;
+
+	/**
+	 * @lanes:
+	 *
+	 * Number of active, consecutive, data lanes, starting from
+	 * lane 0, used for the transmissions on main link.
+	 *
+	 * Allowed values: 1, 2, 4
+	 */
+    unsigned int lanes;
+
+	/**
+	 * @voltage:
+	 *
+	 * Voltage swing levels, as specified by DisplayPort specification,
+	 * to be used by particular lanes. One value per lane.
+	 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
+	 *
+	 * Maximum value: 3
+	 */
+    unsigned int voltage[4];
+
+	/**
+	 * @pre:
+	 *
+	 * Pre-emphasis levels, as specified by DisplayPort specification, to be
+	 * used by particular lanes. One value per lane.
+	 *
+	 * Maximum value: 3
+	 */
+    unsigned int pre[4];
+
+	/**
+	 * @ssc:
+	 *
+	 * Flag indicating, whether or not to enable spread-spectrum clocking.
+	 *
+	 */
+    uint8_t ssc : 1;
+
+	/**
+	 * @set_rate:
+	 *
+	 * Flag indicating, whether or not reconfigure link rate and SSC to
+	 * requested values.
+	 *
+	 */
+    uint8_t set_rate : 1;
+
+	/**
+	 * @set_lanes:
+	 *
+	 * Flag indicating, whether or not reconfigure lane count to
+	 * requested value.
+	 *
+	 */
+    uint8_t set_lanes : 1;
+
+	/**
+	 * @set_voltages:
+	 *
+	 * Flag indicating, whether or not reconfigure voltage swing
+	 * and pre-emphasis to requested values. Only lanes specified
+	 * by "lanes" parameter will be affected.
+	 *
+	 */
+    uint8_t set_voltages : 1;
+};
+
+
+struct phy_configure_opts_pcie {
+    bool is_bifurcation; /* Bifurcation mode support */
+};
+
+
+/**
+ * union phy_configure_opts - Opaque generic phy configuration
+ *
+ * @mipi_dphy: Configuration set applicable for phys supporting
+ *	       the MIPI_DPHY phy mode.
+ * @dp:	       Configuration set applicable for phys supporting
+ *	       the DisplayPort protocol.
+ */
+union phy_configure_opts {
+    struct phy_configure_opts_mipi_dphy     mipi_dphy;
+    struct phy_configure_opts_dp		dp;
+    struct phy_configure_opts_pcie		pcie;
+};
+
+
+struct phy_ops {
+	/**
+	 * of_xlate - Translate a client's device-tree (OF) phy specifier.
+	 *
+	 * The PHY core calls this function as the first step in implementing
+	 * a client's generic_phy_get_by_*() call.
+	 *
+	 * If this function pointer is set to NULL, the PHY core will use a
+	 * default implementation, which assumes #phy-cells = <0> or
+	 * #phy-cells = <1>, and in the later case that the DT cell
+	 * contains a simple integer PHY port ID.
+	 *
+	 * @phy:	The phy struct to hold the translation result.
+	 * @args:	The phy specifier values from device tree.
+	 * @return 0 if OK, or a negative error code.
+	 */
+//    int	(*of_xlate)(struct phy *phy, struct ofnode_phandle_args *args);
+
+	/**
+	 * init - initialize the hardware.
+	 *
+	 * Hardware intialization should not be done in during probe() but
+	 * should be implemented in this init() function. It could be starting
+	 * PLL, taking a controller out of reset, routing, etc. This function
+	 * is typically called only once per PHY port.
+	 * If power_on() is not implemented, it must power up the phy.
+	 *
+	 * @phy:	the PHY port to initialize
+	 * @return 0 if OK, or a negative error code.
+	 */
+    int	(*init)(struct phy *phy);
+
+	/**
+	* exit - de-initialize the PHY device
+	*
+	* Hardware de-intialization should be done here. Every step done in
+	* init() should be undone here.
+	* This could be used to suspend the phy to reduce power consumption or
+	* to put the phy in a known condition before booting the OS (though it
+	* is NOT called automatically before booting the OS)
+	* If power_off() is not implemented, it must power down the phy.
+	*
+	* @phy:	PHY port to be de-initialized
+	* @return 0 if OK, or a negative error code
+	*/
+    int	(*exit)(struct phy *phy);
+
+	/**
+	* reset - resets a PHY device without shutting down
+	*
+	* @phy:	PHY port to be reset
+	*
+	* During runtime, the PHY may need to be reset in order to
+	* re-establish connection etc without being shut down or exit.
+	*
+	* @return 0 if OK, or a negative error code
+	*/
+    int	(*reset)(struct phy *phy);
+
+	/**
+	 * @configure:
+	 *
+	 * Optional.
+	 *
+	 * Used to change the PHY parameters. phy_init() must have
+	 * been called on the phy.
+	 *
+	 * Returns: 0 if successful, an negative error code otherwise
+	 */
+    int	(*configure)(struct phy *phy, union phy_configure_opts *opts);
+
+	/**
+	 * @validate:
+	 *
+	 * Optional.
+	 *
+	 * Used to check that the current set of parameters can be
+	 * handled by the phy. Implementations are free to tune the
+	 * parameters passed as arguments if needed by some
+	 * implementation detail or constraints. It must not change
+	 * any actual configuration of the PHY, so calling it as many
+	 * times as deemed fit by the consumer must have no side
+	 * effect.
+	 *
+	 * Returns: 0 if the configuration can be applied, an negative
+	 * error code otherwise
+	 */
+    int	(*validate)(struct phy *phy, enum phy_mode mode, int submode,
+			    union phy_configure_opts *opts);
+
+	/**
+	* power_on - power on a PHY device
+	*
+	* @phy:	PHY port to be powered on
+	*
+	* During runtime, the PHY may need to be powered on or off several
+	* times. This function is used to power on the PHY. It relies on the
+	* setup done in init(). If init() is not implemented, it must take care
+	* of setting up the context (PLLs, ...)
+	*
+	* @return 0 if OK, or a negative error code
+	*/
+    int	(*power_on)(struct phy *phy);
+
+	/**
+	* power_off - power off a PHY device
+	*
+	* @phy:	PHY port to be powered off
+	*
+	* During runtime, the PHY may need to be powered on or off several
+	* times. This function is used to power off the PHY. Except if
+	* init()/deinit() are not implemented, it must not de-initialize
+	* everything.
+	*
+	* @return 0 if OK, or a negative error code
+	*/
+    int	(*power_off)(struct phy *phy);
+
+    int     (*set_mode)(struct phy *phy, enum phy_mode mode, int submode);
+};
+
+int generic_phy_init(struct phy *phy);
+int generic_phy_power_on(struct phy *phy);
 
 #endif