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Merge branch 'prepare_for_master' of https://git.trustie.net/xuos/xiuos into wgz

This commit is contained in:
wgzAIIT 2022-03-23 15:16:11 +08:00
parent 40d0320ef8 0340217e24
commit 3d647fc6e6
114 changed files with 6991 additions and 1190 deletions
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93
APP_Framework/Applications/connection_app/socket_demo/lwip_tcp_socket_demo.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* Copyright (c) 2022 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
@ -11,16 +11,14 @@
*/
/**
* @file tcp_echo_socket_demo.c
* @brief One UDP demo based on LwIP
* @file lwip_tcp_socket_demo.c
* @brief TCP socket demo based on LwIP
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-29
* @date 2022-03-21
*/
#include <transform.h>
#include <xizi.h>
#include "board.h"
#include "sys_arch.h"
#include <lwip/sockets.h>
#include "lwip/sys.h"
@ -28,6 +26,7 @@
#define TCP_DEMO_BUF_SIZE 65535
char tcp_socket_ip[] = {192, 168, 250, 252};
u16_t tcp_socket_port = LWIP_TARGET_PORT;
/******************************************************************************/
@ -44,41 +43,46 @@ static void TCPSocketRecvTask(void *arg)
recv_buf = (char *)malloc(TCP_DEMO_BUF_SIZE);
if (recv_buf == NULL)
{
lw_print("No memory\n");
goto __exit;
lw_error("No memory\n");
continue;
}
fd = socket(AF_INET, SOCK_STREAM, 0);
if (fd < 0)
{
lw_print("Socket error\n");
goto __exit;
lw_error("Socket error\n");
free(recv_buf);
continue;
}
tcp_addr.sin_family = AF_INET;
tcp_addr.sin_addr.s_addr = INADDR_ANY;
tcp_addr.sin_port = htons(LWIP_LOCAL_PORT);
tcp_addr.sin_port = htons(tcp_socket_port);
memset(&(tcp_addr.sin_zero), 0, sizeof(tcp_addr.sin_zero));
if (bind(fd, (struct sockaddr *)&tcp_addr, sizeof(struct sockaddr)) == -1)
{
lw_print("Unable to bind\n");
goto __exit;
lw_error("Unable to bind\n");
closesocket(fd);
free(recv_buf);
continue;
}
lw_print("tcp bind success, start to receive.\n");
lw_pr_info("\n\nLocal Port:%d\n\n", LWIP_LOCAL_PORT);
lw_notice("\n\nLocal Port:%d\n\n", tcp_socket_port);
// setup socket fd as listening mode
if (listen(fd, 5) != 0 )
{
lw_print("Unable to listen\n");
goto __exit;
lw_error("Unable to listen\n");
closesocket(fd);
free(recv_buf);
continue;
}
// accept client connection
clientfd = accept(fd, (struct sockaddr *)&tcp_addr, (socklen_t*)&addr_len);
lw_pr_info("client %s connected\n", inet_ntoa(tcp_addr.sin_addr));
lw_notice("client %s connected\n", inet_ntoa(tcp_addr.sin_addr));
while(1)
{
@ -86,34 +90,31 @@ static void TCPSocketRecvTask(void *arg)
recv_len = recvfrom(clientfd, recv_buf, TCP_DEMO_BUF_SIZE, 0, (struct sockaddr *)&tcp_addr, &addr_len);
if(recv_len > 0)
{
lw_pr_info("Receive from : %s\n", inet_ntoa(tcp_addr.sin_addr));
lw_pr_info("Receive data : %d - %s\n\n", recv_len, recv_buf);
lw_notice("Receive from : %s\n", inet_ntoa(tcp_addr.sin_addr));
lw_notice("Receive data : %d - %s\n\n", recv_len, recv_buf);
}
sendto(clientfd, recv_buf, recv_len, 0, (struct sockaddr*)&tcp_addr, addr_len);
}
__exit:
if (fd >= 0)
closesocket(fd);
if (recv_buf)
free(recv_buf);
}
closesocket(fd);
free(recv_buf);
}
void TCPSocketRecvTest(int argc, char *argv[])
{
int result = 0;
pthread_t th_id;
pthread_attr_t attr;
if(argc == 2)
if(argc >= 2)
{
lw_print("lw: [%s] gw %s\n", __func__, argv[1]);
sscanf(argv[1], "%d.%d.%d.%d", &tcp_socket_ip[0], &tcp_socket_ip[1], &tcp_socket_ip[2], &tcp_socket_ip[3]);
lw_print("lw: [%s] target ip %s\n", __func__, argv[1]);
if(sscanf(argv[1], "%d.%d.%d.%d:%d", &tcp_socket_ip[0], &tcp_socket_ip[1], &tcp_socket_ip[2], &tcp_socket_ip[3], &tcp_socket_port) == EOK)
{
sscanf(argv[1], "%d.%d.%d.%d", &tcp_socket_ip[0], &tcp_socket_ip[1], &tcp_socket_ip[2], &tcp_socket_ip[3]);
}
}
lwip_config_tcp(lwip_ipaddr, lwip_netmask, lwip_gwaddr);
lwip_config_tcp(lwip_ipaddr, lwip_netmask, tcp_socket_ip);
sys_thread_new("TCPSocketRecvTask", TCPSocketRecvTask, NULL, LWIP_TASK_STACK_SIZE, LWIP_DEMO_TASK_PRIO);
}
@ -133,51 +134,51 @@ static void TCPSocketSendTask(void *arg)
if (fd < 0)
{
lw_print("Socket error\n");
goto __exit;
return;
}
struct sockaddr_in tcp_sock;
tcp_sock.sin_family = AF_INET;
tcp_sock.sin_port = htons(LWIP_TARGET_PORT);
tcp_sock.sin_port = htons(tcp_socket_port);
tcp_sock.sin_addr.s_addr = PP_HTONL(LWIP_MAKEU32(tcp_socket_ip[0], tcp_socket_ip[1], tcp_socket_ip[2], tcp_socket_ip[3]));
memset(&(tcp_sock.sin_zero), 0, sizeof(tcp_sock.sin_zero));
if (connect(fd, (struct sockaddr *)&tcp_sock, sizeof(struct sockaddr)))
{
lw_print("Unable to connect\n");
goto __exit;
closesocket(fd);
return;
}
lw_print("tcp connect success, start to send.\n");
lw_pr_info("\n\nTarget Port:%d\n\n", LWIP_TARGET_PORT);
lw_notice("\n\nTarget Port:%d\n\n", tcp_socket_port);
while (cnt --)
{
lw_print("Lwip client is running.\n");
snprintf(send_msg, sizeof(send_msg), "TCP test package times %d\r\n", cnt);
sendto(fd, send_msg, strlen(send_msg), 0, (struct sockaddr*)&tcp_sock, sizeof(struct sockaddr));
lw_pr_info("Send tcp msg: %s ", send_msg);
lw_notice("Send tcp msg: %s ", send_msg);
MdelayKTask(1000);
}
__exit:
if (fd >= 0)
closesocket(fd);
closesocket(fd);
return;
}
void TCPSocketSendTest(int argc, char *argv[])
{
if(argc == 2)
if(argc >= 2)
{
lw_print("lw: [%s] gw %s\n", __func__, argv[1]);
sscanf(argv[1], "%d.%d.%d.%d", &tcp_socket_ip[0], &tcp_socket_ip[1], &tcp_socket_ip[2], &tcp_socket_ip[3]);
lw_print("lw: [%s] target ip %s\n", __func__, argv[1]);
if(sscanf(argv[1], "%d.%d.%d.%d:%d", &tcp_socket_ip[0], &tcp_socket_ip[1], &tcp_socket_ip[2], &tcp_socket_ip[3], &tcp_socket_port) == EOK)
{
sscanf(argv[1], "%d.%d.%d.%d", &tcp_socket_ip[0], &tcp_socket_ip[1], &tcp_socket_ip[2], &tcp_socket_ip[3]);
}
}
lwip_config_tcp(lwip_ipaddr, lwip_netmask, tcp_socket_ip);
sys_thread_new("tcp socket", TCPSocketSendTask, NULL, LWIP_TASK_STACK_SIZE, LWIP_DEMO_TASK_PRIO);
sys_thread_new("TCP Socket Send", TCPSocketSendTask, NULL, LWIP_TASK_STACK_SIZE, LWIP_DEMO_TASK_PRIO);
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(0),

142
APP_Framework/Applications/connection_app/socket_demo/lwip_udp_socket_demo.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* Copyright (c) 2022 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
@ -12,33 +12,25 @@
/**
* @file lwip_udp_socket_demo.c
* @brief One UDP demo based on LwIP
* @brief UDP demo based on LwIP
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-29
* @date 2022-03-21
*/
#include <transform.h>
#include <xizi.h>
#include "board.h"
#include "sys_arch.h"
#include "lwip/udp.h"
#include "lwip/opt.h"
#include <lwip/sockets.h>
#include "lwip/sys.h"
#include "lwip/sockets.h"
#define UDP_BUF_SIZE 65536
extern char udp_target[];
static struct udp_pcb *udpecho_raw_pcb;
char udp_socket_ip[] = {192, 168, 250, 252};
u16_t udp_socket_port = LWIP_LOCAL_PORT;
/******************************************************************************/
/*****************************************************************************/
static void UdpSocketRecvTask(void *arg)
{
lw_print("UdpSocketRecvTask start.\n");
int socket_fd = -1;
int fd = -1;
char *recv_buf;
struct sockaddr_in udp_addr, server_addr;
int recv_len;
@ -49,134 +41,124 @@ static void UdpSocketRecvTask(void *arg)
recv_buf = (char *)malloc(UDP_BUF_SIZE);
if(recv_buf == NULL)
{
lw_print("No memory\n");
goto __exit;
lw_error("No memory\n");
continue;
}
socket_fd = socket(AF_INET, SOCK_DGRAM, 0);
if(socket_fd < 0)
fd = socket(AF_INET, SOCK_DGRAM, 0);
if(fd < 0)
{
lw_print("Socket error\n");
goto __exit;
lw_error("Socket error\n");
free(recv_buf);
continue;
}
udp_addr.sin_family = AF_INET;
udp_addr.sin_addr.s_addr = INADDR_ANY;
udp_addr.sin_port = htons(LWIP_LOCAL_PORT);
udp_addr.sin_port = htons(udp_socket_port);
memset(&(udp_addr.sin_zero), 0, sizeof(udp_addr.sin_zero));
if(bind(socket_fd, (struct sockaddr *)&udp_addr, sizeof(struct sockaddr)) == -1)
if(bind(fd, (struct sockaddr *)&udp_addr, sizeof(struct sockaddr)) == -1)
{
lw_print("Unable to bind\n");
goto __exit;
lw_error("Unable to bind\n");
closesocket(fd);
free(recv_buf);
continue;
}
lw_print("UDP bind sucess, start to receive.\n");
lw_print("\n\nLocal Port:%d\n\n", LWIP_LOCAL_PORT);
lw_notice("UDP bind sucess, start to receive.\n");
lw_notice("\n\nLocal Port:%d\n\n", udp_socket_port);
while(1)
{
memset(recv_buf, 0, UDP_BUF_SIZE);
recv_len = recvfrom(socket_fd, recv_buf, UDP_BUF_SIZE, 0, (struct sockaddr *)&server_addr, &addr_len);
lw_pr_info("Receive from : %s\n", inet_ntoa(server_addr.sin_addr));
lw_pr_info("Receive data : %s\n\n", recv_buf);
sendto(socket_fd, recv_buf, recv_len, 0, (struct sockaddr*)&server_addr, addr_len);
recv_len = recvfrom(fd, recv_buf, UDP_BUF_SIZE, 0, (struct sockaddr *)&server_addr, &addr_len);
if(recv_len > 0)
{
lw_notice("Receive from : %s\n", inet_ntoa(server_addr.sin_addr));
lw_notice("Receive data : %s\n\n", recv_buf);
}
sendto(fd, recv_buf, recv_len, 0, (struct sockaddr*)&server_addr, addr_len);
}
__exit:
if(socket_fd >= 0)
{
closesocket(socket_fd);
}
if(recv_buf)
{
free(recv_buf);
}
closesocket(fd);
free(recv_buf);
}
}
void UdpSocketRecvTask(int argc, char *argv[])
void UdpSocketRecvTest(int argc, char *argv[])
{
int result = 0;
pthread_t th_id;
pthread_attr_t attr;
if(argc == 2)
if(argc >= 2)
{
lw_print("lw: [%s] gw %s\n", __func__, argv[1]);
sscanf(argv[1], "%d.%d.%d.%d", &udp_socket_ip[0], &udp_socket_ip[1], &udp_socket_ip[2], &udp_socket_ip[3]);
lw_notice("lw: [%s] target ip %s\n", __func__, argv[1]);
if(sscanf(argv[1], "%d.%d.%d.%d:%d", &udp_socket_ip[0], &udp_socket_ip[1], &udp_socket_ip[2], &udp_socket_ip[3], &udp_socket_port) == EOK)
{
sscanf(argv[1], "%d.%d.%d.%d", &udp_socket_ip[0], &udp_socket_ip[1], &udp_socket_ip[2], &udp_socket_ip[3]);
}
}
lwip_config_tcp(lwip_ipaddr, lwip_netmask, lwip_gwaddr);
lwip_config_tcp(lwip_ipaddr, lwip_netmask, udp_socket_ip);
sys_thread_new("UdpSocketRecvTask", UdpSocketRecvTask, NULL, LWIP_TASK_STACK_SIZE, LWIP_DEMO_TASK_PRIO);
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3),
UDPSocketRecv, UdpSocketRecvTask, UDP recv echo);
UDPSocketRecv, UdpSocketRecvTest, UDP Receive DEMO);
static void UdpSocketSendTask(void *arg)
{
int cnt = LWIP_DEMO_TIMES;
char send_str[128];
int fd = -1;
lw_print("UdpSocketSendTask start.\n");
int socket_fd = -1;
memset(send_str, 0, sizeof(send_str));
socket_fd = socket(AF_INET, SOCK_DGRAM, 0);
if(socket_fd < 0)
fd = socket(AF_INET, SOCK_DGRAM, 0);
if(fd < 0)
{
lw_print("Socket error\n");
goto __exit;
lw_error("Socket error\n");
return;
}
struct sockaddr_in udp_sock;
udp_sock.sin_family = AF_INET;
udp_sock.sin_port = htons(LWIP_TARGET_PORT);
udp_sock.sin_addr.s_addr = PP_HTONL(LWIP_MAKEU32(udp_target[0], udp_target[1], udp_target[2], udp_target[3]));
udp_sock.sin_port = htons(udp_socket_port);
udp_sock.sin_addr.s_addr = PP_HTONL(LWIP_MAKEU32(udp_socket_ip[0], udp_socket_ip[1], udp_socket_ip[2], udp_socket_ip[3]));
memset(&(udp_sock.sin_zero), 0, sizeof(udp_sock.sin_zero));
if(connect(socket_fd, (struct sockaddr *)&udp_sock, sizeof(struct sockaddr)))
if(connect(fd, (struct sockaddr *)&udp_sock, sizeof(struct sockaddr)))
{
lw_print("Unable to connect\n");
goto __exit;
lw_error("Unable to connect\n");
closesocket(fd);
return;
}
lw_print("UDP connect success, start to send.\n");
lw_print("\n\nTarget Port:%d\n\n", udp_sock.sin_port);
lw_notice("\n\nTarget Port:%d\n\n", udp_sock.sin_port);
while (cnt --)
{
snprintf(send_str, sizeof(send_str), "UDP test package times %d\r\n", cnt);
sendto(socket_fd, send_str, strlen(send_str), 0, (struct sockaddr*)&udp_sock, sizeof(struct sockaddr));
lw_pr_info("Send UDP msg: %s ", send_str);
sendto(fd, send_str, strlen(send_str), 0, (struct sockaddr*)&udp_sock, sizeof(struct sockaddr));
lw_notice("Send UDP msg: %s ", send_str);
MdelayKTask(1000);
}
__exit:
if(socket_fd >= 0)
{
closesocket(socket_fd);
}
closesocket(fd);
return;
}
void UdpSocketSendTest(int argc, char *argv[])
{
int result = 0;
pthread_t th_id;
pthread_attr_t attr;
if(argc == 2)
if(argc >= 2)
{
lw_print("lw: [%s] gw %s\n", __func__, argv[1]);
sscanf(argv[1], "%d.%d.%d.%d", &udp_socket_ip[0], &udp_socket_ip[1], &udp_socket_ip[2], &udp_socket_ip[3]);
lw_notice("lw: [%s] target ip %s\n", __func__, argv[1]);
if(sscanf(argv[1], "%d.%d.%d.%d:%d", &udp_socket_ip[0], &udp_socket_ip[1], &udp_socket_ip[2], &udp_socket_ip[3], &udp_socket_port) == EOK)
{
sscanf(argv[1], "%d.%d.%d.%d", &udp_socket_ip[0], &udp_socket_ip[1], &udp_socket_ip[2], &udp_socket_ip[3]);
}
}
lwip_config_tcp(lwip_ipaddr, lwip_netmask, lwip_gwaddr);
lwip_config_tcp(lwip_ipaddr, lwip_netmask, udp_socket_ip);
sys_thread_new("UdpSocketSendTask", UdpSocketSendTask, NULL, LWIP_TASK_STACK_SIZE, LWIP_DEMO_TASK_PRIO);
}

16
APP_Framework/Applications/control_app/opcua_demo/README.md Executable file
View File

@ -0,0 +1,16 @@
# OPCUA DEMO README
## 文件说明
用于OPCUA 相关测试命令演示，需要开启LWIP和OPCUA协议.
### 命令行
UaConnect [IP]
用于测试与OPCUA服务器连接，连接成功应显示OK
UaObject [IP]
用于显示对应的OPCUA设备的节点信息

38
APP_Framework/Applications/control_app/opcua_demo/opcua_demo.c
View File

@ -11,7 +11,7 @@
*/
/**
* @file ua_demo.c
* @file opcua_demo.c
* @brief Demo for OpcUa function
* @version 1.0
* @author AIIT XUOS Lab
@ -29,7 +29,6 @@
* Definitions
******************************************************************************/
#define TCP_LOCAL_PORT 4840
#define UA_URL_SIZE 100
#define UA_STACK_SIZE 4096
#define UA_TASK_PRIO 15
@ -66,18 +65,17 @@ static void UaConnectTestTask(void* arg)
UA_ClientConfig_setDefault(config);
snprintf(ua_uri, sizeof(ua_uri), "opc.tcp://%d.%d.%d.%d:4840",
test_ua_ip[0], test_ua_ip[1], test_ua_ip[2], test_ua_ip[3]);
ua_pr_info("ua uri: %d %s\n", strlen(ua_uri), ua_uri);
ua_notice("ua uri: %d %s\n", strlen(ua_uri), ua_uri);
retval = UA_Client_connect(client,ua_uri);
if(retval != UA_STATUSCODE_GOOD)
{
ua_pr_info("ua: [%s] connected failed %x\n", __func__, retval);
ua_notice("ua: [%s] connected failed %x\n", __func__, retval);
UA_Client_delete(client);
return;
}
ua_pr_info("ua: [%s] connected ok!\n", __func__);
UA_Client_disconnect(client);
ua_notice("ua: [%s] connected ok!\n", __func__);
UA_Client_delete(client);
}
@ -92,12 +90,13 @@ SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) |
void UaBrowserObjectsTestTask(void* param)
{
static int test_cnt = 0;
UA_Client* client = UA_Client_new();
ua_pr_info("ua: [%s] start ...\n", __func__);
ua_notice("ua: [%s] start %d ...\n", __func__, test_cnt++);
if(client == NULL)
{
ua_print("ua: [%s] tcp client null\n", __func__);
ua_error("ua: [%s] tcp client NULL\n", __func__);
return;
}
@ -107,18 +106,17 @@ void UaBrowserObjectsTestTask(void* param)
if(retval != UA_STATUSCODE_GOOD)
{
ua_print("ua: [%s] connect failed %#x\n", __func__, retval);
ua_error("ua: [%s] connect failed %#x\n", __func__, retval);
UA_Client_delete(client);
return;
}
ua_print("ua: [%s] connect ok!\n", __func__);
ua_pr_info("--- start read time ---\n", __func__);
ua_notice("--- start read time ---\n", __func__);
ua_read_time(client);
ua_pr_info("--- get server info ---\n", __func__);
ua_notice("--- get server info ---\n", __func__);
ua_test_browser_objects(client);
/* Clean up */
UA_Client_disconnect(client);
UA_Client_delete(client); /* Disconnects the client internally */
}
@ -130,7 +128,7 @@ void* UaBrowserObjectsTest(int argc, char* argv[])
{
if(sscanf(argv[1], "%d.%d.%d.%d", &test_ua_ip[0], &test_ua_ip[1], &test_ua_ip[2], &test_ua_ip[3]) == EOF)
{
lw_pr_info("input wrong ip\n");
lw_notice("input wrong ip\n");
return NULL;
}
}
@ -147,7 +145,7 @@ SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) |
void UaGetInfoTestTask(void* param)
{
UA_Client* client = UA_Client_new();
ua_pr_info("ua: [%s] start ...\n", __func__);
ua_notice("ua: [%s] start ...\n", __func__);
if(client == NULL)
{
@ -167,7 +165,7 @@ void UaGetInfoTestTask(void* param)
}
ua_print("ua: [%s] connect ok!\n", __func__);
ua_pr_info("--- interactive server ---\n", __func__);
ua_notice("--- interactive server ---\n", __func__);
ua_test_interact_server(client);
/* Clean up */
UA_Client_disconnect(client);
@ -182,7 +180,7 @@ void* UaGetInfoTest(int argc, char* argv[])
{
if(sscanf(argv[1], "%d.%d.%d.%d", &test_ua_ip[0], &test_ua_ip[1], &test_ua_ip[2], &test_ua_ip[3]) == EOF)
{
lw_pr_info("input wrong ip\n");
lw_notice("input wrong ip\n");
return NULL;
}
}
@ -199,7 +197,7 @@ SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) |
void UaAddNodesTask(void* param)
{
UA_Client* client = UA_Client_new();
ua_pr_info("ua: [%s] start ...\n", __func__);
ua_notice("ua: [%s] start ...\n", __func__);
if(client == NULL)
{
@ -219,7 +217,7 @@ void UaAddNodesTask(void* param)
}
ua_print("ua: [%s] connect ok!\n", __func__);
ua_pr_info("--- add nodes ---\n", __func__);
ua_notice("--- add nodes ---\n", __func__);
ua_add_nodes(client);
/* Clean up */
UA_Client_disconnect(client);
@ -234,7 +232,7 @@ void* UaAddNodesTest(int argc, char* argv[])
{
if(sscanf(argv[1], "%d.%d.%d.%d", &test_ua_ip[0], &test_ua_ip[1], &test_ua_ip[2], &test_ua_ip[3]) == EOF)
{
lw_pr_info("input wrong ip\n");
lw_notice("input wrong ip\n");
return NULL;
}
}

48
APP_Framework/Applications/control_app/plc_demo/README.md Executable file
View File

@ -0,0 +1,48 @@
# PLC DEMO README
## 文件说明
用于PLC设备相关测试命令演示，目前支持OPCUA协议对PLC进行远程控制，该命令基于LWIP和OPCUA，需要开启相关开关。
多个PLC设备可以组成一个channel，用于一条相关业务线控制。
### 命令行
ShowChannel
显示注册到channel上的PLC设备，范例如下：
ch_type ch_name drv_name dev_name cnt
-----------------------------------------------------------------
PLC_Channel PLC OPCUA PLC Demo 4 1
PLC Demo 3 2
PLC Demo 2 3
PLC Demo 1 4
PLC Demo 0 5
ShowPLC
用于显示PLC，范例如下：
device vendor model product id
-----------------------------------------------------------------
PLC Demo 4 B&R X20 X20 CP1381 5
PLC Demo 3 B&R X20 X20 CP1586 4
PLC Demo 2 SIEMSNS S7-200 CPU SR60 3
PLC Demo 1 SIEMENS S7-1200 CPU 1215C 2
PLC Demo 0 SIEMENS S7-1500 CPU 1512SP-1PN 1
PlcRead [NodeID]
用于读取PLC节点信息
- [NodeID]: 如n4,1, 其中4代表namespace，1代表节点号
PlcWrite
用于写入PLC节点数值
- [NodeID]: 如n4,1, 其中4代表namespace，1代表节点号
- [value]: 为写入数值，目前支持bool类型，和int类型。bool型应为0b(代表false), 1b(代表true)

4
APP_Framework/Applications/control_app/plc_demo/plc_control_demo.c
View File

@ -101,8 +101,6 @@ void PlcReadUATask(void* arg)
if(EOK != ret)
{
plc_print("plc: [%s] open failed %#x\n", __func__, ret);
// free(plc_demo_dev.priv_data);
// plc_demo_dev.priv_data = NULL;
return;
}
@ -163,8 +161,6 @@ void PlcWriteUATask(void* arg)
if(EOK != ret)
{
plc_print("plc: [%s] open failed %#x\n", __func__, ret);
// free(plc_demo_dev.priv_data);
// plc_demo_dev.priv_data = NULL;
return;
}

4
APP_Framework/Applications/sensor_app/SConscript
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@ -15,6 +15,10 @@ if GetDepend(['APPLICATION_SENSOR_HUMIDITY_HS300X']):
SOURCES = ['humidity_hs300x.c'] + SOURCES
if GetDepend(['APPLICATION_SENSOR_TEMPERATURE_HS300X']):
SOURCES = ['temperature_hs300x.c'] + SOURCES
if GetDepend(['APPLICATION_SENSOR_CH4_AS830']):
SOURCES = ['ch4_as830.c'] + SOURCES
if GetDepend(['APPLICATION_SENSOR_HCHO']):
SOURCES = ['hcho_tb600b_wq_hcho1os.c'] + SOURCES
path = [cwd]
objs = DefineGroup('sensor_app', src = SOURCES, depend = DEPENDS,CPPPATH = path)
Return("objs")

6
APP_Framework/Framework/control/plc/interoperability/Kconfig
View File

@ -2,5 +2,9 @@
menuconfig USING_CONTROL_PLC_OPCUA
bool "PLC support OPCUA"
default y
depends on RESOURCES_LWIP
depends on RESOURCES_LWIP
menuconfig USING_CONTROL_PLC_SOCKET
bool "PLC support SOCKET"
default y
depends on RESOURCES_LWIP

4
APP_Framework/Framework/control/plc/interoperability/Makefile
View File

@ -6,6 +6,10 @@ ifeq ($(CONFIG_USING_CONTROL_PLC_OPCUA), y)
SRC_DIR += opcua
endif
ifeq ($(CONFIG_USING_CONTROL_PLC_SOCKET), y)
SRC_DIR += socket
endif
endif
SRC_FILES += interoperability.c

6
APP_Framework/Framework/control/plc/interoperability/opcua/open62541.c
View File

@ -68231,11 +68231,11 @@ UA_Log_Stdout_log(void *context, UA_LogLevel level, UA_LogCategory category,
// (int)(tOffset / UA_DATETIME_SEC / 36), logLevelNames[level], logCategoryNames[category]);
// vprintf(msg, args);
KPrintf("%s/%s" ANSI_COLOR_RESET "\t",
ua_print("%s/%s" ANSI_COLOR_RESET "\t",
logLevelNames[level], logCategoryNames[category]);
vsnprintf(str, sizeof(str) - 1, msg, args);
KPrintf(msg, str);
KPrintf("\n");
ua_print(msg, str);
ua_print("\n");
// printf("\n");
fflush(stdout);

7
APP_Framework/Framework/control/plc/interoperability/opcua/ua_api.c
View File

@ -28,7 +28,7 @@ int ua_open(void *dev)
param->client = UA_Client_new();
ua_pr_info("ua: [%s] start ...\n", __func__);
ua_notice("ua: [%s] start ...\n", __func__);
if (param->client == NULL)
{
@ -39,11 +39,11 @@ int ua_open(void *dev)
UA_ClientConfig *config = UA_Client_getConfig(param->client);
UA_ClientConfig_setDefault(config);
ua_pr_info("ua: [%s] %d %s\n", __func__, strlen(param->ua_remote_ip), param->ua_remote_ip);
ua_notice("ua: [%s] %d %s\n", __func__, strlen(param->ua_remote_ip), param->ua_remote_ip);
UA_StatusCode retval = UA_Client_connect(param->client, param->ua_remote_ip);
if(retval != UA_STATUSCODE_GOOD) {
ua_pr_info("ua: [%s] deleted ret %x!\n", __func__, retval);
ua_notice("ua: [%s] deleted ret %x!\n", __func__, retval);
return (int)retval;
}
return EOK;
@ -52,7 +52,6 @@ int ua_open(void *dev)
void ua_close(void *dev)
{
UaParamType *param = (UaParamType *)dev;
UA_Client_disconnect(param->client);
UA_Client_delete(param->client); /* Disconnects the client internally */
}

3
APP_Framework/Framework/control/plc/interoperability/opcua/ua_api.h
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@ -43,8 +43,9 @@ typedef struct UaParam
#define ua_print //KPrintf
#define ua_trace() //KPrintf("ua: [%s] line %d checked!\n", __func__, __LINE__)
#define ua_pr_info KPrintf
#define ua_notice KPrintf
#define ua_debug //KPrintf
#define ua_error KPrintf
extern const char *opc_server_url;
extern char test_ua_ip[];

42
APP_Framework/Framework/control/plc/interoperability/opcua/ua_client.c
View File

@ -42,7 +42,7 @@ static UA_StatusCode nodeIter(UA_NodeId childId, UA_Boolean isInverse, UA_NodeId
}
UA_NodeId* parent = (UA_NodeId*)handle;
ua_pr_info("%d, %d --- %d ---> NodeId %d, %d\n",
ua_notice("%d, %d --- %d ---> NodeId %d, %d\n",
parent->namespaceIndex, parent->identifier.numeric,
referenceTypeId.identifier.numeric, childId.namespaceIndex,
childId.identifier.numeric);
@ -81,38 +81,38 @@ void ua_print_value(UA_Variant* val)
if(val->type == &UA_TYPES[UA_TYPES_LOCALIZEDTEXT])
{
UA_LocalizedText* ptr = (UA_LocalizedText*)val->data;
ua_pr_info("%.*s (Text)\n", ptr->text.length, ptr->text.data);
ua_notice("%.*s (Text)\n", ptr->text.length, ptr->text.data);
}
else if(val->type == &UA_TYPES[UA_TYPES_UINT32])
{
UA_UInt32* ptr = (UA_UInt32*)val->data;
ua_pr_info("%d (UInt32)\n", *ptr);
ua_notice("%d (UInt32)\n", *ptr);
}
else if(val->type == &UA_TYPES[UA_TYPES_BOOLEAN])
{
UA_Boolean* ptr = (UA_Boolean*)val->data;
ua_pr_info("%i (BOOL)\n", *ptr);
ua_notice("%i (BOOL)\n", *ptr);
}
else if(val->type == &UA_TYPES[UA_TYPES_INT32])
{
UA_Int32* ptr = (UA_Int32*)val->data;
ua_pr_info("%d (Int32)\n", *ptr);
ua_notice("%d (Int32)\n", *ptr);
}
else if(val->type == &UA_TYPES[UA_TYPES_INT16])
{
UA_Int16* ptr = (UA_Int16*)val->data;
ua_pr_info("%d (Int16)\n", *ptr);
ua_notice("%d (Int16)\n", *ptr);
}
else if(val->type == &UA_TYPES[UA_TYPES_STRING])
{
UA_String* ptr = (UA_String*)val->data;
ua_pr_info("%*.s (String)\n", ptr->length, ptr->data);
ua_notice("%*.s (String)\n", ptr->length, ptr->data);
}
else if(val->type == &UA_TYPES[UA_TYPES_DATETIME])
{
UA_DateTime* ptr = (UA_DateTime*)val->data;
UA_DateTimeStruct dts = UA_DateTime_toStruct(*ptr);
ua_pr_info("%d-%d-%d %d:%d:%d.%03d (Time)\n",
ua_notice("%d-%d-%d %d:%d:%d.%03d (Time)\n",
dts.day, dts.month, dts.year, dts.hour, dts.min, dts.sec, dts.milliSec);
}
}
@ -144,14 +144,14 @@ void ua_print_nodeid(UA_NodeId *node_id)
switch(node_id->identifierType)
{
case UA_NODEIDTYPE_NUMERIC:
ua_pr_info(" NodeID n%d,%d ", node_id->namespaceIndex, node_id->identifier.numeric);
ua_notice(" NodeID n%d,%d ", node_id->namespaceIndex, node_id->identifier.numeric);
break;
case UA_NODEIDTYPE_STRING:
ua_pr_info(" NodeID n%d,%.*s ", node_id->namespaceIndex, node_id->identifier.string.length,
ua_notice(" NodeID n%d,%.*s ", node_id->namespaceIndex, node_id->identifier.string.length,
node_id->identifier.string.data);
break;
case UA_NODEIDTYPE_BYTESTRING:
ua_pr_info(" NodeID n%d,%s ", node_id->namespaceIndex, node_id->identifier.byteString.data);
ua_notice(" NodeID n%d,%s ", node_id->namespaceIndex, node_id->identifier.byteString.data);
break;
default:
break;
@ -160,7 +160,7 @@ void ua_print_nodeid(UA_NodeId *node_id)
void ua_print_object(UA_BrowseResponse* res)
{
ua_pr_info("%-9s %-16s %-16s %-16s\n", "NAMESPACE", "NODEID", "BROWSE NAME", "DISPLAY NAME");
ua_notice("%-9s %-16s %-16s %-16s\n", "NAMESPACE", "NODEID", "BROWSE NAME", "DISPLAY NAME");
for(size_t i = 0; i < res->resultsSize; ++i)
{
@ -170,14 +170,14 @@ void ua_print_object(UA_BrowseResponse* res)
if(ref->nodeId.nodeId.identifierType == UA_NODEIDTYPE_NUMERIC)
{
ua_pr_info("%-9d %-16d %-16.*s %-16.*s\n", ref->nodeId.nodeId.namespaceIndex,
ua_notice("%-9d %-16d %-16.*s %-16.*s\n", ref->nodeId.nodeId.namespaceIndex,
ref->nodeId.nodeId.identifier.numeric, (int)ref->browseName.name.length,
ref->browseName.name.data, (int)ref->displayName.text.length,
ref->displayName.text.data);
}
else if(ref->nodeId.nodeId.identifierType == UA_NODEIDTYPE_STRING)
{
ua_pr_info("%-9d %-16.*s %-16.*s %-16.*s\n", ref->nodeId.nodeId.namespaceIndex,
ua_notice("%-9d %-16.*s %-16.*s %-16.*s\n", ref->nodeId.nodeId.namespaceIndex,
(int)ref->nodeId.nodeId.identifier.string.length,
ref->nodeId.nodeId.identifier.string.data,
(int)ref->browseName.name.length, ref->browseName.name.data,
@ -188,7 +188,7 @@ void ua_print_object(UA_BrowseResponse* res)
}
}
ua_pr_info("\n");
ua_notice("\n");
}
UA_StatusCode ua_read_array_value(UA_Client* client, int array_size, UA_ReadValueId* array)
@ -203,7 +203,7 @@ UA_StatusCode ua_read_array_value(UA_Client* client, int array_size, UA_ReadValu
|| (response.resultsSize != array_size))
{
UA_ReadResponse_clear(&response);
ua_pr_info("ua: [%s] read failed 0x%x\n", __func__,
ua_notice("ua: [%s] read failed 0x%x\n", __func__,
response.responseHeader.serviceResult);
return UA_STATUSCODE_BADUNEXPECTEDERROR;
}
@ -215,11 +215,11 @@ UA_StatusCode ua_read_array_value(UA_Client* client, int array_size, UA_ReadValu
if((response.results[i].status == UA_STATUSCODE_GOOD)
&& (response.results[i].hasValue))
{
ua_pr_info("node %s: ", ua_get_nodeid_str(&array[i].nodeId));
ua_notice("node %s: ", ua_get_nodeid_str(&array[i].nodeId));
ua_print_value(&response.results[i].value);
}
}
ua_pr_info("\n");
ua_notice("\n");
free(arr_ret);
UA_ReadResponse_clear(&response);
@ -229,7 +229,7 @@ UA_StatusCode ua_read_array_value(UA_Client* client, int array_size, UA_ReadValu
void ua_browser_id(UA_Client* client, UA_NodeId id)
{
/* Browse some objects */
ua_pr_info("Browsing nodes in objects folder:\n");
ua_notice("Browsing nodes in objects folder:\n");
UA_BrowseRequest bReq;
UA_BrowseRequest_init(&bReq);
bReq.requestedMaxReferencesPerNode = 0;
@ -327,7 +327,7 @@ void ua_write_nodeid_value(UA_Client* client, UA_NodeId id, char* value)
if(wResp.responseHeader.serviceResult == UA_STATUSCODE_GOOD)
{
ua_pr_info("write new value is: %s\n", value);
ua_notice("write new value is: %s\n", value);
}
UA_WriteRequest_clear(&wReq);
@ -489,7 +489,7 @@ void ua_read_time(UA_Client* client)
{
UA_DateTime raw_date = *(UA_DateTime*) value.data;
UA_DateTimeStruct dts = UA_DateTime_toStruct(raw_date);
ua_pr_info("date is: %d-%d-%d %d:%d:%d.%03d\n",
ua_notice("date is: %d-%d-%d %d:%d:%d.%03d\n",
dts.day, dts.month, dts.year, dts.hour, dts.min, dts.sec, dts.milliSec);
}

6
APP_Framework/Framework/control/plc/interoperability/opcua/ua_test.c
View File

@ -53,7 +53,7 @@ void ua_test_browser_objects(UA_Client *client)
ua_browser_id(client, UA_TEST_BROWSER_NODEID);
ua_browser_id(client, UA_TEST_BROWSER_NODEID1);
test_id = UA_TEST_BROWSER_NODEID1;
ua_pr_info("Show values in %s:\n", ua_get_nodeid_str(&test_id));
ua_notice("Show values in %s:\n", ua_get_nodeid_str(&test_id));
ua_test_read_array(client);
return;
}
@ -64,11 +64,11 @@ void ua_test_write_attr(UA_Client *client)
char val_str[UA_NODE_LEN];
UA_NodeId id = UA_TEST_WRITE_NODEID;
ua_pr_info("--- Test write %s ---\n", ua_get_nodeid_str(&id));
ua_notice("--- Test write %s ---\n", ua_get_nodeid_str(&id));
ua_read_nodeid_value(client, id, &value);
ua_write_nodeid_value(client, id, itoa(value + 1, val_str, 10));
ua_read_nodeid_value(client, id, &value);
ua_pr_info("\n");
ua_notice("\n");
}
int ua_test_interact_server(UA_Client *client)

11
APP_Framework/Framework/control/plc/interoperability/socket/Kconfig Executable file
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@ -0,0 +1,11 @@
menuconfig USING_CONTROL_PLC_OPCUA
bool "PLC support OPCUA"
default y
depends on RESOURCES_LWIP
menuconfig USING_CONTROL_PLC_SOCKET
bool "PLC support SOCKET"
default y
depends on RESOURCES_LWIP

4
APP_Framework/Framework/control/plc/interoperability/socket/Makefile Executable file
View File

@ -0,0 +1,4 @@
SRC_FILES := plc_socket.c
include $(KERNEL_ROOT)/compiler.mk

18
APP_Framework/Framework/control/plc/interoperability/socket/README.md Executable file
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@ -0,0 +1,18 @@
# PLC SOCKET README
## 文件说明
用于测试PLC socket通信. 通过建立与制定IP的PLC设备的socket连接, 发送命令给PLC设备, 实现相关功能. 实现该功能需要开启LWIP, 同时需要扩大shell的栈大小和内存空间。
### 命令行
PLCSocket ip=[PLC IP] port=[PLC port] tcp=[1: TCP; 0: UDP] cmd=[相关命令] file=[制定配置文件]
配置文件支持json格式, 默认文件名为socket_param.json, 放置于plc目录下, 文件内容如下：
{
"ip": "192.168.250.6",
"port": 102,
"tcp": 1,
"cmd": [x, x, x]
}

364
APP_Framework/Framework/control/plc/interoperability/socket/plc_socket.c Executable file
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@ -0,0 +1,364 @@
/*
* Copyright (c) 2022 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file plc_socket.c
* @brief Demo for PLC socket communication function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.03.16
*/
#include "transform.h"
#include "plc_socket.h"
#include "sys_arch.h"
#include "lwip/sockets.h"
#include "control_file.h"
// max support plc socket test commands number
#define PLC_SOCK_CMD_NUM CTL_CMD_NUM
#define PLC_SOCK_TIMEOUT 50000
// for saving PLC command index
int plc_cmd_index = 0;
// only for test
#define SUPPORT_PLC_SIEMENS
//siemens test
PlcBinCmdType TestPlcCmd[PLC_SOCK_CMD_NUM] = {0};
//Test information
//SIEMENS ip: 192.168.250.9 port: 102
//S7-200 ip: 192.168.250.8 port: 102
//S7-1200 ip: 192.168.250.6 port: 102
//OML ip: 192.168.250.3 port: 9600
PlcSocketParamType plc_socket_demo_data = {
#ifdef SUPPORT_PLC_SIEMENS
.ip = {192, 168, 250, 6},
.port = 102,
.device_type = PLC_DEV_TYPE_SIEMENS,
.socket_type = SOCK_STREAM,
.cmd_num = 3,
#else
.ip = {192, 168, 250, 3},
.port = 9600,
.device_type = PLC_DEV_TYPE_OML,
.socket_type = SOCK_DGRAM,
.cmd_num = 1,
#endif
.recv_len = PLC_RECV_BUF_LEN,
.recv_buf = NULL,
};
#define OML_HEADER_LEN 78
#define CHECK_OML_HEADER(_s) ((0xC0 == *(_s)) && (0x00 == *(_s + 1)) && (0x02 == *(_s + 2)) && (0x00 == *(_s + 3)))
/******************************************************************************/
static void plc_print_array(char *title, int size, uint8_t *cmd)
{
lw_notice("%s : %d - ", title, size);
for(int i = 0; i < size; i++)
{
lw_notice(" %#x", cmd[i]);
}
lw_notice("\n");
}
static void *PlcSocketStart(void *arg)
{
int fd = -1;
int timeout, recv_len;
struct sockaddr_in sock_addr;
socklen_t addr_len = sizeof(struct sockaddr_in);
PlcSocketParamType *param = (PlcSocketParamType *)&plc_socket_demo_data;
plc_print("start %d.%d.%d.%d:%d dev %d sock %d\n",
param->ip[0],
param->ip[1],
param->ip[2],
param->ip[3],
param->port,
param->device_type,
param->socket_type);
param->recv_len = PLC_RECV_BUF_LEN;
//malloc memory
param->recv_buf = (char *)malloc(param->recv_len);
if (param->recv_buf == NULL)
{
plc_error("No memory\n");
return NULL;
}
fd = socket(AF_INET, param->socket_type, 0);
if (fd < 0)
{
plc_error("Socket error %d\n", param->socket_type);
free(param->recv_buf);
return NULL;
}
plc_print("start %d.%d.%d.%d:%d\n", param->ip[0], param->ip[1], param->ip[2], param->ip[3], param->port);
sock_addr.sin_family = AF_INET;
sock_addr.sin_port = htons(param->port);
sock_addr.sin_addr.s_addr = PP_HTONL(LWIP_MAKEU32(param->ip[0], param->ip[1], param->ip[2], param->ip[3]));
memset(&(sock_addr.sin_zero), 0, sizeof(sock_addr.sin_zero));
if (connect(fd, (struct sockaddr *)&sock_addr, sizeof(struct sockaddr)) < 0)
{
plc_error("Unable to connect\n");
closesocket(fd);
free(param->recv_buf);
return NULL;
}
lw_notice("client %s connected\n", inet_ntoa(sock_addr.sin_addr));
for(int i = 0; i < param->cmd_num; i ++)
{
PlcBinCmdType *cmd = &TestPlcCmd[i];
sendto(fd, cmd->cmd, cmd->cmd_len, 0, (struct sockaddr*)&sock_addr, addr_len);
plc_print_array("Send cmd", cmd->cmd_len, cmd->cmd);
MdelayKTask(cmd->delay_ms);
timeout = PLC_SOCK_TIMEOUT;
memset(param->recv_buf, 0, param->recv_len);
while(timeout --)
{
recv_len = recvfrom(fd, param->recv_buf, param->recv_len, 0, (struct sockaddr *)&sock_addr, &addr_len);
if(recv_len > 0)
{
if(param->device_type == PLC_DEV_TYPE_OML)
{
if((recv_len == OML_HEADER_LEN) && (CHECK_OML_HEADER(param->recv_buf)))
{
lw_notice("This is Oml package!!!\n");
}
}
lw_notice("Receive from : %s\n", inet_ntoa(sock_addr.sin_addr));
plc_print_array("Receive data", recv_len, param->recv_buf);
break;
}
}
}
closesocket(fd);
free(param->recv_buf);
return NULL;
}
void PlcGetParamCmd(char *cmd)
{
const char s[2] = ",";
char *token;
uint16_t cmd_index = 0;
char bin_cmd[PLC_BIN_CMD_LEN] = {0};
token = strtok(cmd, s);
while(token != NULL)
{
sscanf(token, "%x", &bin_cmd[cmd_index]);
plc_print("%d - %s %d\n", cmd_index, token, bin_cmd[cmd_index]);
token = strtok(NULL, s);
cmd_index ++;
}
TestPlcCmd[plc_cmd_index].cmd_len = cmd_index;
memcpy(TestPlcCmd[plc_cmd_index].cmd, bin_cmd, cmd_index);
plc_print("get %d cmd len %d\n", plc_cmd_index, TestPlcCmd[plc_cmd_index].cmd_len);
plc_cmd_index ++;
plc_socket_demo_data.cmd_num = plc_cmd_index;
}
void PlcShowUsage(void)
{
plc_notice("------------------------------------\n");
plc_notice("PlcSocket [ip].[ip].[ip].[ip]:[port]\n");
plc_notice("PlcSocket support other param:\n");
plc_notice("plc=[] 0: OML 1:SIEMENS\n");
plc_notice("tcp=[] 0: udp 1:tcp\n");
plc_notice("ip=[ip.ip.ip.ip]\n");
plc_notice("port=port\n");
plc_notice("file: use %s\n", PLC_SOCK_FILE_NAME);
plc_notice("------------------------------------\n");
}
#if defined(MOUNT_SDCARD) && defined(LIB_USING_CJSON)
void PlcGetParamFromFile(char *file_name)
{
PlcSocketParamType *param = &plc_socket_demo_data;
char *file_buf = malloc(CTL_FILE_LEN);
if(file_buf == NULL)
{
plc_error("No enough buffer %d\n", CTL_FILE_LEN);
return;
}
memset(file_buf, 0, CTL_FILE_LEN);
if(CtlFileReadWithFilename(file_name, CTL_FILE_LEN, file_buf) != EOK)
{
plc_error("Can't open file %s\n", file_name);
//try again default file
if(strcmp(file_name, PLC_SOCK_FILE_NAME) != 0)
{
if(CtlFileReadWithFilename(PLC_SOCK_FILE_NAME, CTL_FILE_LEN, file_buf) != EOK)
{
plc_error("Can't open file %s\n", file_name);
return;
}
}
else
{
return;
}
}
CtlParseJsonData(file_buf);
memcpy(param->ip, ctl_file_param.ip, 4);
param->port = ctl_file_param.port;
param->cmd_num = ctl_file_param.cmd_num;
param->socket_type = ctl_file_param.tcp ? SOCK_STREAM : SOCK_DGRAM;
for(int i = 0; i < param->cmd_num; i++)
{
TestPlcCmd[i].cmd_len = ctl_file_param.cmd_len[i];
memcpy(TestPlcCmd[i].cmd, ctl_file_param.cmd[i], TestPlcCmd[i].cmd_len);
}
plc_print("ip: %d.%d.%d.%d\n", param->ip[0], param->ip[1], param->ip[2], param->ip[3]);
plc_print("port: %d", param->port);
plc_print("tcp: %d", param->socket_type);
plc_print("cmd number: %d\n", param->cmd_num);
for(int i = 0; i < param->cmd_num; i++)
{
plc_print_array("cmd", TestPlcCmd[i].cmd_len, TestPlcCmd[i].cmd);
}
free(file_buf);
}
#endif
void PlcCheckParam(int argc, char *argv[])
{
int i;
PlcSocketParamType *param = &plc_socket_demo_data;
plc_cmd_index = 0;
for(i = 0; i < argc; i++)
{
char *str = argv[i];
int is_tcp = 0;
char cmd_str[PLC_BIN_CMD_LEN] = {0};
plc_print("check %d %s\n", i, str);
#if defined(MOUNT_SDCARD) && defined(LIB_USING_CJSON)
if(strncmp(str, "file", 4) == 0)
{
char file_name[CTL_FILE_NAME_LEN] = {0};
if(sscanf(str, "file=%s", file_name) == EOF)
{
strcpy(file_name, PLC_SOCK_FILE_NAME);
}
plc_notice("get %s parameter file %s\n", str, file_name);
PlcGetParamFromFile(file_name);
return;
}
#endif
if(sscanf(str, "ip=%d.%d.%d.%d",
&param->ip[0],
&param->ip[1],
&param->ip[2],
&param->ip[3]) == 4)
{
plc_print("find ip %d %d %d %d\n", param->ip[0], param->ip[1], param->ip[2], param->ip[3]);
continue;
}
if(sscanf(str, "port=%d", &param->port) == 1)
{
plc_print("find port %d\n", param->port);
continue;
}
if(sscanf(str, "tcp=%d", &is_tcp) == 1)
{
plc_print("find tcp %d\n", is_tcp);
param->socket_type = is_tcp ? SOCK_STREAM:SOCK_DGRAM;
continue;
}
if(sscanf(str, "plc=%d", &param->device_type) == 1)
{
plc_print("find device %d\n", param->device_type);
continue;
}
if(sscanf(str, "cmd=%s", cmd_str) == 1)
{
plc_print("find cmd %s\n", cmd_str);
PlcGetParamCmd(cmd_str);
continue;
}
}
if(argc >= 2)
{
if(sscanf(argv[1], "%d.%d.%d.%d:%d",
&param->ip[0],
&param->ip[1],
&param->ip[2],
&param->ip[3],
&param->port) != EOF)
{
return;
}
if(sscanf(argv[1], "%d.%d.%d.%d",
&param->ip[0],
&param->ip[1],
&param->ip[2],
&param->ip[3]) != EOF)
{
return;
}
}
else
{
PlcShowUsage();
}
}
void PlcSocketTask(int argc, char *argv[])
{
int result = 0;
pthread_t th_id;
pthread_attr_t attr;
attr.schedparam.sched_priority = LWIP_DEMO_TASK_PRIO;
attr.stacksize = LWIP_TASK_STACK_SIZE;
PlcSocketParamType *param = &plc_socket_demo_data;
PlcCheckParam(argc, argv);
lwip_config_net(lwip_ipaddr, lwip_netmask, param->ip);
PrivTaskCreate(&th_id, &attr, PlcSocketStart, param);
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(3),
PlcSocket, PlcSocketTask, Test PLC Socket);

66
APP_Framework/Framework/control/plc/interoperability/socket/plc_socket.h Executable file
View File

@ -0,0 +1,66 @@
/*
* Copyright (c) 2022 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file plc_socket.h
* @brief Demo for PLC socket communication function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.03.16
*/
#ifndef __PLC_SOCKET_H_
#define __PLC_SOCKET_H_
#define PLC_BIN_CMD_LEN 512
// for plc socket test bin commands
typedef struct
{
uint16_t delay_ms;
uint8_t cmd_len;
uint8_t cmd[PLC_BIN_CMD_LEN];
}PlcBinCmdType;
enum PlcDeviceType {
PLC_DEV_TYPE_OML = 0,
PLC_DEV_TYPE_IPC,
PLC_DEV_TYPE_BRL,
PLC_DEV_TYPE_SIEMENS,
PLC_DEV_TYPE_SIEMENS_1200,
PLC_DEV_TYPE_JF_IPC,
PLC_DEV_TYPE_HG,
/* ...... */
PLC_DEV_TYPE_END,
};
#define PLC_IP_LEN 16
#define PLC_DEV_NAME_LEN 32
#define PLC_RECV_BUF_LEN CTL_FILE_LEN
typedef struct PlcSocketParamStruct{
char ip[PLC_IP_LEN];
uint32_t port;
uint32_t device_type; //PlcDeviceType
uint32_t socket_type; //UDP or TCP
char device[PLC_DEV_NAME_LEN];
uint32_t cmd_num; // command number
uint32_t recv_len; // receive length
uint8_t *recv_buf; // receive buffer
}PlcSocketParamType;
//debug command
#define plc_print //KPrintf
#define plc_error KPrintf
#define plc_notice KPrintf
#endif

2
APP_Framework/Framework/control/plc/shared/plc_device.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021 AIIT XUOS Lab
* Copyright (c) 2022 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:

4
APP_Framework/Framework/control/shared/Makefile
View File

@ -1,4 +1,8 @@
SRC_FILES := control.c
ifeq ($(CONFIG_MOUNT_SDCARD),y)
SRC_FILES += control_file.c
endif
include $(KERNEL_ROOT)/compiler.mk

213
APP_Framework/Framework/control/shared/control_file.c Executable file
View File

@ -0,0 +1,213 @@
/*
* Copyright (c) 2022 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file control_file.c
* @brief control relative file operation
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-03-17
*/
#include <stdio.h>
#include "cJSON.h"
#include "transform.h"
#include "control_file.h"
//json file parameter for PLC socket communication as below:
//{
// "ip": "192.168.250.6",
// "port": 102,
// "cmd": [3, 0, 0, 22, 17, 224, 0, 0, 2, 200, 0, 193, 2, 2, 1, 194, 2, 2, 1, 192, 1, 10],
// "cmd1": [3, 0, 0, 25, 2, 240, 128, 50, 1, 0, 0, 0, 13, 0, 8, 0, 0, 240, 0, 0, 1, 0, 1, 0, 240], \r\n" \
// "cmd2": [3, 0, 0, 31, 2, 240, 128, 50, 1, 0, 0, 51, 1, 0, 14, 0, 0, 4, 1, 18, 10, 16, 2, 0, 210, 0, 52, 132, 0, 0, 0]\r\n" \
//}"
#define TEST_PLC_JSON_TXT \
"{ \r\n"\
" \"ip\": \"192.168.250.6\", \r\n"\
" \"port\": 102, \r\n"\
" \"tcp\": 1, \r\n"\
" \"cmd\": [3, 0, 0, 22, 17, 224, 0, 0, 2, 200, 0, 193, 2, 2, 1, 194, 2, 2, 1, 192, 1, 10], \r\n"\
" \"cmd1\": [3, 0, 0, 25, 2, 240, 128, 50, 1, 0, 0, 0, 13, 0, 8, 0, 0, 240, 0, 0, 1, 0, 1, 0, 240], \r\n" \
" \"cmd2\": [3, 0, 0, 31, 2, 240, 128, 50, 1, 0, 0, 51, 1, 0, 14, 0, 0, 4, 1, 18, 10, 16, 2, 0, 210, 0, 52, 132, 0, 0, 0]\r\n" \
"}"
CtlPlcSockParamType ctl_file_param;
FILE *CtlFileInit(char *file)
{
FILE *fd = NULL;
#ifdef MOUNT_SDCARD
// SD card mount flag 1: OK
if(sd_mount_flag == 0)
{
ctl_error("SD card mount failed\n");
return NULL;
}
fd = fopen(file, "a+");
if(fd == NULL)
{
ctl_error("open file %s failed\n", file);
}
#endif
return fd;
}
void CtlFileClose(FILE *fd)
{
fclose(fd);
}
void CtlFileRead(FILE *fd, int size, char *buf)
{
fseek(fd, 0, SEEK_SET);
fread(buf, size, 1, fd);
ctl_print("read file %d: %.100s\n", size, buf);
}
void CtlFileWrite(FILE *fd, int size, char *buf)
{
size_t write_size = 0;
write_size = fwrite(buf, strlen(buf) + 1, 1, fd);
ctl_print("write size %d: %s\n", size, buf);
}
int CtlFileReadWithFilename(char *file, int size, char *buf)
{
FILE *fd;
fd = fopen(file, "r");
if(fd == NULL)
{
ctl_error("open file %s failed\n", file);
return EEMPTY;
}
fseek(fd, 0, SEEK_SET);
fread(buf, size, 1, fd);
ctl_print("read file %d: %.100s\n", size, buf);
return EOK;
}
void CtlCreateFileTest(void)
{
FILE *fd = CtlFileInit(PLC_SOCK_FILE_NAME);
if(fd == NULL)
return;
char *file_buf = TEST_PLC_JSON_TXT;
CtlFileWrite(fd, strlen(file_buf), file_buf);
CtlFileClose(fd);
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(0),
CtlCreateFile, CtlCreateFileTest, Test control file);
#ifdef LIB_USING_CJSON
void CtlParseJsonArray(cJSON *dat, int *cmd_len, char *cmd)
{
int len, i;
if(cJSON_IsArray(dat))
{
len = cJSON_GetArraySize(dat);
ctl_print("json cmd %d\n", len);
for(i = 0; i < len; i++)
{
cJSON *cmd_val = cJSON_GetArrayItem(dat, i);
if(NULL == cmd_val)
continue;
ctl_print("0x%x ", cmd_val->valueint);
cmd[i] = cmd_val->valueint;
}
*cmd_len = len;
ctl_print("\n");
}
}
void CtlParseJsonData(char *buf)
{
cJSON *file_dat = NULL;
cJSON *ip_dat = NULL;
cJSON *port_dat = NULL;
cJSON *tcp_dat = NULL;
cJSON *cmd_dat = NULL;
char cmd_title[10] = {"cmd"};
CtlPlcSockParamType *file_param = &ctl_file_param;
file_dat = cJSON_Parse(buf);
if(file_dat == NULL)
{
ctl_error("ctrl parse failed\n");
return;
}
ip_dat = cJSON_GetObjectItem(file_dat, "ip");
port_dat = cJSON_GetObjectItem(file_dat, "port");
tcp_dat = cJSON_GetObjectItem(file_dat, "tcp");
ctl_print(" ip : %s\n", ip_dat->valuestring);
sscanf(ip_dat->valuestring, "%d.%d.%d.%d", &file_param->ip[0],
&file_param->ip[1],
&file_param->ip[2],
&file_param->ip[3]);
ctl_print(" port: %s %d\n", ip_dat->string, port_dat->valueint);
file_param->port = port_dat->valueint;
file_param->tcp = tcp_dat->valueint;
file_param->cmd_num = 0;
for(int i = 0; i < CTL_CMD_NUM; i++)
{
cmd_dat = cJSON_GetObjectItem(file_dat, cmd_title);
if(!cmd_dat)
break;
CtlParseJsonArray(cmd_dat, &file_param->cmd_len[i], file_param->cmd[i]);
snprintf(cmd_title, sizeof(cmd_title), "cmd%d", ++file_param->cmd_num);
}
cJSON_Delete(file_dat);
}
void CtlParseFileTest(void)
{
//for PLC socket parameter file
FILE *fd = CtlFileInit(PLC_SOCK_FILE_NAME);
if(fd == NULL)
{
ctl_error("ctl get file %s failed\n", PLC_SOCK_FILE_NAME);
return;
}
char *file_buf = malloc(CTL_FILE_LEN);
if(file_buf == NULL)
{
ctl_error("ctl malloc failed\n");
return;
}
memset(file_buf, 0, CTL_FILE_LEN);
CtlFileRead(fd, CTL_FILE_LEN, file_buf);
CtlFileClose(fd);
CtlParseJsonData(file_buf);
free(file_buf);
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0) | SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN) | SHELL_CMD_PARAM_NUM(0),
CtlParseFile, CtlParseFileTest, Parse control file);
#endif

59
APP_Framework/Framework/control/shared/control_file.h Executable file
View File

@ -0,0 +1,59 @@
/*
* Copyright (c) 2022 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file control_file.h
* @brief control relative API
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-03-17
*/
#ifndef __CONTROL_FILE_H_
#define __CONTROL_FILE_H_
#define CTL_FILE_LEN 1000 // control file size
#define CTL_CMD_NUM 10 // support command number
#define CTL_CMD_LEN 100 // control command length
#define CTL_IP_LEN 32 // IP address length
#define CTL_FILE_NAME_LEN 100 // file name length
#define PLC_SOCK_FILE_NAME "/plc/socket_param.json"
#define ctl_print //KPrintf
#define ctl_error KPrintf
// for running plc socket
typedef struct CtlPlcSockParamStruct
{
char ip[CTL_IP_LEN];
int port;
int tcp; // 1: TCP 0: UDP
int cmd_num; //command number
int cmd_len[CTL_CMD_NUM]; // command length
char cmd[CTL_CMD_NUM][CTL_CMD_LEN];
}CtlPlcSockParamType;
extern CtlPlcSockParamType ctl_file_param;
extern int sd_mount_flag;
FILE *CtlFileInit(char *file);
void CtlFileClose(FILE *fd);
void CtlFileRead(FILE *fd, int size, char *buf);
void CtlFileWrite(FILE *fd, int size, char *buf);
int CtlFileReadWithFilename(char *file_name, int size, char *buf);
#ifdef LIB_USING_CJSON
void CtlParseJsonData(char *buf);
#endif
#endif

17
APP_Framework/Framework/sensor/ch4/Kconfig
View File

@ -43,6 +43,23 @@ config SENSOR_AS830
endif
if ADD_RTTHREAD_FETURES
config SENSOR_AS830_DRIVER_EXTUART
bool "Using extra uart to support as830"
default y
config SENSOR_DEVICE_AS830_DEV
string "as830 device uart path"
default "/dev/uart2"
depends on !SENSOR_AS830_DRIVER_EXTUART
if SENSOR_AS830_DRIVER_EXTUART
config SENSOR_DEVICE_AS830_DEV
string "as830 device extra uart path"
default "/dev/extuart_dev4"
config SENSOR_DEVICE_AS830_DEV_EXT_PORT
int "if AS830 device using extuart, choose port"
default "4"
endif
endif
endif

14
APP_Framework/Framework/sensor/ch4/SConscript Normal file
View File

@ -0,0 +1,14 @@
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(path, 'SConscript'))
Return('objs')

10
APP_Framework/Framework/sensor/ch4/as830/SConscript Normal file
View File

@ -0,0 +1,10 @@
from building import *
import os
cwd = GetCurrentDir()
src = []
if GetDepend(['SENSOR_AS830']):
src += ['as830.c']
group = DefineGroup('sensor ch4 as830', src, depend = [], CPPPATH = [cwd])
Return('group')

17
APP_Framework/Framework/sensor/co2/Kconfig
View File

@ -43,7 +43,24 @@ config SENSOR_ZG09
endif
if ADD_RTTHREAD_FETURES
config SENSOR_ZG09_DRIVER_EXTUART
bool "Using extra uart to support zg09"
default y
config SENSOR_DEVICE_ZG09_DEV
string "zg09 device uart path"
default "/dev/uart2_dev2"
depends on !SENSOR_ZG09_DRIVER_EXTUART
if SENSOR_ZG09_DRIVER_EXTUART
config SENSOR_DEVICE_ZG09_DEV
string "zg09 device extra uart path"
default "/dev/extuart_dev4"
config SENSOR_DEVICE_ZG09_DEV_EXT_PORT
int "if ZG09 device using extuart, choose port"
default "4"
endif
endif
endif

10
APP_Framework/Framework/sensor/co2/zg09/SConscript Normal file
View File

@ -0,0 +1,10 @@
from building import *
import os
cwd = GetCurrentDir()
src = []
if GetDepend(['SENSOR_ZG09']):
src += ['zg09.c']
group = DefineGroup('sensor co2 zg09', src, depend = [], CPPPATH = [cwd])
Return('group')

17
APP_Framework/Framework/sensor/hcho/Kconfig
View File

@ -43,6 +43,23 @@ config SENSOR_TB600B_WQ_HCHO1OS
endif
if ADD_RTTHREAD_FETURES
config SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART
bool "Using extra uart to support tb600b wq_hcho1os"
default y
config SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV
string "tb600b wq_hcho1os device uart path"
default "/dev/uart2"
depends on !SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART
if SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART
config SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV
string "tb600b wq_hcho1os device extra uart path"
default "/dev/extuart_dev1"
config SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV_EXT_PORT
int "if TB600B_WQ_HCHO1OS device using extuart, choose port"
default "1"
endif
endif
endif

14
APP_Framework/Framework/sensor/hcho/SConscript Normal file
View File

@ -0,0 +1,14 @@
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(path, 'SConscript'))
Return('objs')

10
APP_Framework/Framework/sensor/hcho/tb600b_wq_hcho1os/SConscript Normal file
View File

@ -0,0 +1,10 @@
from building import *
import os
cwd = GetCurrentDir()
src = []
if GetDepend(['SENSOR_TB600B_WQ_HCHO1OS']):
src += ['tb600b_wq_hcho1os.c']
group = DefineGroup('sensor hcho', src, depend = [], CPPPATH = [cwd])
Return('group')

17
APP_Framework/Framework/sensor/voice/Kconfig
View File

@ -43,6 +43,23 @@ config SENSOR_D124
endif
if ADD_RTTHREAD_FETURES
config SENSOR_D124_DRIVER_EXTUART
bool "Using extra uart to support D124"
default y
config SENSOR_DEVICE_D124_DEV
string "D124 device name"
default "/dev/uart2_dev2"
depends on !SENSOR_D124_DRIVER_EXTUART
if SENSOR_D124_DRIVER_EXTUART
config SENSOR_DEVICE_D124_DEV
string "D124 device extra uart path"
default "/dev/extuart_dev4"
config SENSOR_DEVICE_D124_DEV_EXT_PORT
int "if D124 device using extuart, choose port"
default "4"
endif
endif
endif

4
APP_Framework/lib/Kconfig
View File

@ -5,12 +5,12 @@ menu "lib"
config APP_SELECT_NEWLIB
bool "app select newlib"
config APP_SELECT_OTHER_LIB
bool "app select other lib"
endchoice
source "$APP_DIR/lib/cJSON/Kconfig"
source "$APP_DIR/lib/queue/Kconfig"
source "$APP_DIR/lib/queue/Kconfig"
source "$APP_DIR/lib/lvgl/Kconfig"
source "$APP_DIR/lib/embedded_database/Kconfig"
endmenu

3
APP_Framework/lib/Makefile
View File

@ -10,5 +10,8 @@ ifeq ($(CONFIG_LIB_LV),y)
SRC_DIR += lvgl
endif
ifeq ($(CONFIG_LIB_USING_CJSON),y)
SRC_DIR += cJSON
endif
include $(KERNEL_ROOT)/compiler.mk

3
APP_Framework/lib/cJSON/Makefile Executable file
View File

@ -0,0 +1,3 @@
SRC_FILES := cJSON.c
include $(KERNEL_ROOT)/compiler.mk

45
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/.config
View File

@ -11,7 +11,7 @@ CONFIG_BOARD_K210_EVB=y
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
CONFIG_RT_NAME_MAX=24
# CONFIG_RT_USING_BIG_ENDIAN is not set
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
CONFIG_RT_USING_SMP=y
@ -292,11 +292,6 @@ CONFIG_BSP_UART1_CTS_PIN=-1
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_SPI1 is not set
# CONFIG_BSP_USING_LCD is not set
# CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_LOW is not set
# CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_HIGH is not set
# CONFIG_BSP_BOARD_KD233 is not set
# CONFIG_BSP_BOARD_K210_OPENMV_TEST is not set
# CONFIG_BSP_BOARD_USER is not set
# CONFIG_BSP_USING_SDCARD is not set
# CONFIG_BSP_USING_DVP is not set
CONFIG_BSP_USING_CH438=y
@ -332,10 +327,34 @@ CONFIG_PKG_KENDRYTE_SDK_VERNUM=0x0055
# Framework
#
CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y
CONFIG_ADD_XIZI_FETURES=y
# CONFIG_ADD_XIZI_FETURES is not set
# CONFIG_ADD_NUTTX_FETURES is not set
# CONFIG_ADD_RTTHREAD_FETURES is not set
# CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set
CONFIG_ADD_RTTHREAD_FETURES=y
CONFIG_SUPPORT_SENSOR_FRAMEWORK=y
CONFIG_SENSOR_HCHO=y
CONFIG_SENSOR_TB600B_WQ_HCHO1OS=y
CONFIG_SENSOR_DEVICE_TB600B_WQ_HCHO1OS="tb600b_wq_hcho1os_1"
CONFIG_SENSOR_QUANTITY_TB600B_HCHO="hcho_1"
CONFIG_SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART=y
CONFIG_SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV="/dev/extuart_dev1"
CONFIG_SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV_EXT_PORT=1
# CONFIG_SENSOR_TVOC is not set
# CONFIG_SENSOR_IAQ is not set
CONFIG_SENSOR_CH4=y
CONFIG_SENSOR_AS830=y
CONFIG_SENSOR_DEVICE_AS830="as830_1"
CONFIG_SENSOR_QUANTITY_AS830_CH4="ch4_1"
CONFIG_SENSOR_AS830_DRIVER_EXTUART=y
CONFIG_SENSOR_DEVICE_AS830_DEV="/dev/extuart_dev4"
CONFIG_SENSOR_DEVICE_AS830_DEV_EXT_PORT=4
# CONFIG_SENSOR_CO2 is not set
# CONFIG_SENSOR_PM is not set
# CONFIG_SENSOR_VOICE is not set
# CONFIG_SENSOR_TEMPERATURE is not set
# CONFIG_SENSOR_HUMIDITY is not set
# CONFIG_SENSOR_WINDSPEED is not set
# CONFIG_SENSOR_WINDDIRECTION is not set
# CONFIG_SENSOR_ALTITUDE is not set
# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set
# CONFIG_SUPPORT_KNOWING_FRAMEWORK is not set
# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set
@ -382,10 +401,12 @@ CONFIG_MAIN_KTASK_STACK_SIZE=1024
# sensor app
#
CONFIG_APPLICATION_SENSOR=y
# CONFIG_APPLICATION_SENSOR_HCHO is not set
CONFIG_APPLICATION_SENSOR_HCHO=y
CONFIG_APPLICATION_SENSOR_HCHO_TB600B_WQ_HCHO1OS=y
# CONFIG_APPLICATION_SENSOR_TVOC is not set
# CONFIG_APPLICATION_SENSOR_IAQ is not set
# CONFIG_APPLICATION_SENSOR_CH4 is not set
CONFIG_APPLICATION_SENSOR_CH4=y
CONFIG_APPLICATION_SENSOR_CH4_AS830=y
# CONFIG_APPLICATION_SENSOR_CO2 is not set
# CONFIG_APPLICATION_SENSOR_PM1_0 is not set
# CONFIG_APPLICATION_SENSOR_PM2_5 is not set
@ -403,7 +424,7 @@ CONFIG_APPLICATION_SENSOR=y
#
CONFIG_APP_SELECT_NEWLIB=y
# CONFIG_APP_SELECT_OTHER_LIB is not set
CONFIG_LIB_USING_CJSON=y
# CONFIG_LIB_USING_CJSON is not set
# CONFIG_LIB_USING_QUEUE is not set
# CONFIG_LIB_LV is not set
# CONFIG_USING_EMBEDDED_DATABASE is not set

3
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/applications/main.c
View File

@ -20,9 +20,10 @@
#include <rtthread.h>
#include <stdio.h>
extern int FrameworkInit();
int main(void)
{
printf("Hello World\n");
FrameworkInit();
return 0;
}

350
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/base-drivers/ch438.c
View File

@ -5,11 +5,10 @@
#include "board.h"
#include "ch438.h"
#include "sleep.h"
static struct rt_semaphore ch438_sem;
#include <math.h>
static rt_uint8_t offsetadd[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* Offset address of serial port number */
rt_uint8_t RevLen ,Ch438Buff[8][BUFFSIZE],Ch438BuffPtr[8];
struct rt_serial_device *extuart_serial_parm[8];
void CH438_INIT(void)
{
@ -25,7 +24,7 @@ void CH438_INIT(void)
gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH);
}
void CH438_PORT_INIT( rt_uint8_t ext_uart_no,rt_uint32_t BaudRate )
void CH438_PORT_INIT( rt_uint8_t ext_uart_no,rt_uint32_t BaudRate )
{
rt_uint32_t div;
rt_uint8_t DLL,DLM,dlab;
@ -117,7 +116,7 @@ void set_485_output(rt_uint8_t ch_no)
rt_uint8_t ReadCH438Data( rt_uint8_t addr )
{
rt_uint8_t dat;
rt_uint8_t dat = 0;
gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_HIGH);
gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_HIGH);
@ -164,7 +163,6 @@ rt_uint8_t ReadCH438Data( rt_uint8_t addr )
usleep(1);
return dat;
}
@ -216,141 +214,98 @@ static void WriteCH438Data( rt_uint8_t addr, rt_uint8_t dat)
return;
}
static void WriteCH438Block( rt_uint8_t mAddr, rt_uint8_t mLen, rt_uint8_t *mBuf )
{
while ( mLen -- )
WriteCH438Data( mAddr, *mBuf++ );
}
static int Ch438Irq(void *parameter)
{
rt_uint8_t gInterruptStatus;
rt_uint8_t port = 0;
struct rt_serial_device *serial = (struct rt_serial_device *)parameter;
/* multi irq may happen*/
gInterruptStatus = ReadCH438Data(REG_SSR_ADDR);
port = log(gInterruptStatus & 0xFF)/log(2);
// void CH438UARTSend( rt_uint8_t ext_uart_no,rt_uint8_t *Data, rt_uint8_t Num )
// {
// rt_uint8_t REG_LSR_ADDR,REG_THR_ADDR;
// REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
// REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
// while( 1 )
// {
// while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_TEMT ) == 0 );
// if( Num <= 128 )
// {
// WriteCH438Block( REG_THR_ADDR, Num, Data );
// break;
// }
// else
// {
// WriteCH438Block( REG_THR_ADDR, 128, Data );
// Num -= 128;
// Data += 128;
// }
// }
// }
// rt_uint8_t CH438UARTRcv( rt_uint8_t ext_uart_no, rt_uint8_t* buf )
// {
// rt_uint8_t RcvNum = 0;
// rt_uint8_t dat = 0;
// rt_uint8_t REG_LSR_ADDR,REG_RBR_ADDR;
// rt_uint8_t *p_rev;
// p_rev = buf;
// REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
// REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
// {
// while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_DATARDY ) == 0 );
// while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
// {
// dat = ReadCH438Data( REG_RBR_ADDR );
// Ch438Buff[ext_uart_no][Ch438BuffPtr[ext_uart_no]] = dat;
// Ch438BuffPtr[ext_uart_no] = Ch438BuffPtr[ext_uart_no] + 1;
// if (Ch438BuffPtr[ext_uart_no] == BUFFSIZE)
// Ch438BuffPtr[ext_uart_no] = 0;
// RcvNum = RcvNum + 1;
// }
// }
// return( RcvNum );
// }
rt_hw_serial_isr(extuart_serial_parm[port], RT_SERIAL_EVENT_RX_IND);
}
static rt_err_t rt_extuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
rt_uint32_t baud_rate = cfg->baud_rate;
rt_uint16_t port = cfg->reserved;
rt_uint32_t baud_rate = cfg->baud_rate;
uint16_t port = cfg->reserved;
CH438_PORT_INIT(port, baud_rate);
return RT_EOK;
}
static rt_err_t extuart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
rt_uint16_t ext_uart_no = serial->config.reserved;
static rt_uint16_t register_flag = 0;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
if(1 == register_flag)
{
gpiohs_irq_unregister(FPIOA_CH438_INT);
register_flag = 0;
}
break;
case RT_DEVICE_CTRL_SET_INT:
break;
if(0 == register_flag)
{
gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_pin_edge(FPIOA_CH438_INT,GPIO_PE_FALLING);
gpiohs_irq_register(FPIOA_CH438_INT, 1, Ch438Irq, (void*)serial);
register_flag = 1;
}
break;
}
return (RT_EOK);
}
static int drv_extuart_putc(struct rt_serial_device *serial, char c)
{
uint16_t ext_uart_no = serial->config.reserved;
rt_uint8_t REG_LSR_ADDR,REG_THR_ADDR;
REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_TEMT ) == 0 );
WriteCH438Block( REG_THR_ADDR, 1, &c );
if((ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_TEMT) != 0)
{
WriteCH438Block( REG_THR_ADDR, 1, &c );
return 1;
} else {
return 0;
}
}
static int drv_extuart_getc(struct rt_serial_device *serial)
{
rt_uint8_t dat = 0;
rt_uint8_t REG_LSR_ADDR,REG_RBR_ADDR;
uint16_t ext_uart_no = serial->config.reserved;///< get extern uart port
REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_DATARDY ) == 0 );
// while( ( ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
// {
dat = ReadCH438Data( REG_RBR_ADDR );
// }
return( dat );
if((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0x01)
{
dat = ReadCH438Data( REG_RBR_ADDR );
if(dat >= 0)
return dat;
} else {
return -1;
}
}
const struct rt_uart_ops extuart_ops =
@ -362,111 +317,168 @@ const struct rt_uart_ops extuart_ops =
RT_NULL
};
static int Ch438Irq(void *parameter)
{
rt_sem_release(&ch438_sem);
}
int Ch438InitDefault(void)
{
rt_err_t flag;
flag = rt_sem_init(&ch438_sem, "sem_438",0,RT_IPC_FLAG_FIFO);
if (flag != RT_EOK)
{
rt_kprintf("ch438.drv create sem failed .\n");
return -1;
}
gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_pin_edge(FPIOA_CH438_INT,GPIO_PE_FALLING);
gpiohs_irq_register(FPIOA_CH438_INT, 1, Ch438Irq, 0);
CH438_INIT();
return 0;
}
INIT_APP_EXPORT(Ch438InitDefault);
int rt_hw_ch438_init(void)
{
struct rt_serial_device *extserial;
struct device_uart *extuart;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
rt_err_t ret;
// #ifdef BSP_USING_UART1
{
static struct rt_serial_device extserial0;
// static struct device_uart extuart0;
extserial = &extserial0;
// extuart = &extuart0;
extserial->ops = &extuart_ops;
extserial->config = config;
extserial->config.baud_rate = 115200;
extserial->config.reserved = 0; ///< extern uart port
extserial->config.reserved = 0; ///< extern uart port
// extuart->hw_base = UART1_BASE_ADDR;
// extuart->irqno = IRQN_UART1_INTERRUPT;
extuart_serial_parm[0] = &extserial0;
// _uart_init(UART_DEVICE_1);
rt_hw_serial_register(extserial,
ret = rt_hw_serial_register(extserial,
"extuart_dev0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
extuart);
if(ret < 0){
rt_kprintf("extuart_dev0 register failed.\n");
}
}
// #endif
{
static struct rt_serial_device extserial1;
// #ifdef BSP_USING_UART2
// {
// static struct rt_serial_device serial2;
// static struct device_uart uart2;
extserial = &extserial1;
extserial->ops = &extuart_ops;
extserial->config = config;
extserial->config.baud_rate = 9600;
extserial->config.reserved = 1; ///< extern uart port
// serial = &serial2;
// uart = &uart2;
extuart_serial_parm[1] = &extserial1;
// serial->ops = &_uart_ops;
// serial->config = config;
// serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
ret = rt_hw_serial_register(extserial,
"extuart_dev1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
extuart);
if(ret < 0){
rt_kprintf("extuart_dev1 register failed.\n");
}
}
{
static struct rt_serial_device extserial2;
// uart->hw_base = UART2_BASE_ADDR;
// uart->irqno = IRQN_UART2_INTERRUPT;
extserial = &extserial2;
extserial->ops = &extuart_ops;
extserial->config = config;
extserial->config.baud_rate = 9600;
extserial->config.reserved = 2; ///< extern uart port
// _uart_init(UART_DEVICE_2);
extuart_serial_parm[2] = &extserial2;
// rt_hw_serial_register(serial,
// "uart2",
// RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
// uart);
// }
// #endif
ret = rt_hw_serial_register(extserial,
"extuart_dev2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
extuart);
if(ret < 0){
rt_kprintf("extuart_dev2 register failed.\n");
}
// #ifdef BSP_USING_UART3
// {
// static struct rt_serial_device serial3;
// static struct device_uart uart3;
}
{
static struct rt_serial_device extserial3;
// serial = &serial3;
// uart = &uart3;
extserial = &extserial3;
extserial->ops = &extuart_ops;
extserial->config = config;
extserial->config.baud_rate = 9600;
extserial->config.reserved = 3; ///< extern uart port
// serial->ops = &_uart_ops;
// serial->config = config;
// serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
ret = rt_hw_serial_register(extserial,
"extuart_dev3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
extuart);
if(ret < 0){
rt_kprintf("extuart_dev3 register failed.\n");
}
// uart->hw_base = UART3_BASE_ADDR;
// uart->irqno = IRQN_UART3_INTERRUPT;
extuart_serial_parm[3] = &extserial3;
}
{
static struct rt_serial_device extserial4;
// _uart_init(UART_DEVICE_3);
extserial = &extserial4;
extserial->ops = &extuart_ops;
extserial->config = config;
extserial->config.baud_rate = 9600;
extserial->config.reserved = 4; ///< extern uart port
// rt_hw_serial_register(serial,
// "uart3",
// RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
// uart);
// }
// #endif
// Ch438InitDefault();
ret = rt_hw_serial_register(extserial,
"extuart_dev4",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
extuart);
if(ret < 0){
rt_kprintf("extuart_dev4 register failed.\n");
}
extuart_serial_parm[4] = &extserial4;
}
{
static struct rt_serial_device extserial5;
extserial = &extserial5;
extserial->ops = &extuart_ops;
extserial->config = config;
extserial->config.baud_rate = 115200;
extserial->config.reserved = 5; ///< extern uart port
ret = rt_hw_serial_register(extserial,
"extuart_dev5",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
extuart);
if(ret < 0){
rt_kprintf("extuart_dev5 register failed.\n");
}
extuart_serial_parm[5] = &extserial5;
}
{
static struct rt_serial_device extserial6;
extserial = &extserial6;
extserial->ops = &extuart_ops;
extserial->config = config;
extserial->config.baud_rate = 57600;
extserial->config.reserved = 6; ///< extern uart port
ret = rt_hw_serial_register(extserial,
"extuart_dev6",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
extuart);
if(ret < 0){
rt_kprintf("extuart_dev6 register failed.\n");
}
extuart_serial_parm[6] = &extserial6;
}
{
static struct rt_serial_device extserial7;
extserial = &extserial7;
extserial->ops = &extuart_ops;
extserial->config = config;
extserial->config.baud_rate = 9600;
extserial->config.reserved = 7; ///< extern uart port
ret = rt_hw_serial_register(extserial,
"extuart_dev7",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
extuart);
if(ret < 0){
rt_kprintf("extuart_dev7 register failed.\n");
}
extuart_serial_parm[7] = &extserial7;
}
CH438_INIT();
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_ch438_init);

24
Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/rtconfig.h
View File

@ -12,7 +12,7 @@
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_NAME_MAX 24
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 8
@ -206,7 +206,22 @@
/* Framework */
#define TRANSFORM_LAYER_ATTRIUBUTE
#define ADD_XIZI_FETURES
#define ADD_RTTHREAD_FETURES
#define SUPPORT_SENSOR_FRAMEWORK
#define SENSOR_HCHO
#define SENSOR_TB600B_WQ_HCHO1OS
#define SENSOR_DEVICE_TB600B_WQ_HCHO1OS "tb600b_wq_hcho1os_1"
#define SENSOR_QUANTITY_TB600B_HCHO "hcho_1"
#define SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART
#define SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV "/dev/extuart_dev1"
#define SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV_EXT_PORT 1
#define SENSOR_CH4
#define SENSOR_AS830
#define SENSOR_DEVICE_AS830 "as830_1"
#define SENSOR_QUANTITY_AS830_CH4 "ch4_1"
#define SENSOR_AS830_DRIVER_EXTUART
#define SENSOR_DEVICE_AS830_DEV "/dev/extuart_dev4"
#define SENSOR_DEVICE_AS830_DEV_EXT_PORT 4
/* Security */
@ -234,11 +249,14 @@
/* sensor app */
#define APPLICATION_SENSOR
#define APPLICATION_SENSOR_HCHO
#define APPLICATION_SENSOR_HCHO_TB600B_WQ_HCHO1OS
#define APPLICATION_SENSOR_CH4
#define APPLICATION_SENSOR_CH4_AS830
/* lib */
#define APP_SELECT_NEWLIB
#define LIB_USING_CJSON
#define __STACKSIZE__ 4096
#endif

2
Ubiquitous/XiZi/board/ok1052-c/Makefile
View File

@ -1,4 +1,4 @@
SRC_DIR := third_party_driver
SRC_DIR := third_party_driver xip
SRC_FILES := board.c

5
Ubiquitous/XiZi/board/ok1052-c/README.md
View File

@ -161,7 +161,10 @@ make BOARD=ok1052-c
2、ok1052-c开发板支持micro usb口烧写程序，打开NXP MCU Boot Utility后，选择好芯片类型为i.MXRT105x，开发板上电，使用usb线将开发板和PC连接，拨码开关设置为1 on 2 on 3 off 4 off，按下复位键K1后，若连接成功，可见Vendor ID和Product ID均有数字显示，点击reconnect，等待NXP MCU Boot Utility中红色显示变成蓝色显示，则表示已正确识别并连接到了开发板。如下图所示：
![NXPBootUtility_1](./img/NXPBootUtility_1.png)
3、选择编译生成的XiZi_ok1052-c.elf文件路径，并选择.out(elf) from GCC ARM烧写选项，最后点击ALL-In-One Action即可烧写程序，若烧写无误，则下列绿色进度条会执行到底。如下图所示：
3、同时需要匹配ok1052-c开发板所使用的Flash型号，点击Boot Device Configuration，在Use Typical Device中选择Winbond_W25QxxxJV，然后点击ok。如下图所示：
![flashconfig](./img/flashconfig.png)
4、选择编译生成的XiZi_ok1052-c.elf或bin文件路径，按照图示步骤，将文件烧写至Flash中（link.lds中已构造Flash Bootable image，如有修改Flash相关配置需求，可修改/xip目录内相关文件，无需NXPBootUtility再次构造），若烧写无误，则下列绿色进度条会执行到底。如下图所示：
![NXPBootUtility_2](./img/NXPBootUtility_2.png)
### 3.2 运行结果

36
Ubiquitous/XiZi/board/ok1052-c/board.c
View File

@ -7,7 +7,7 @@
/**
* @file board.c
* @brief relative configure for ok1052-c
* @brief relative configure for ok1052-c board
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021.11.11
@ -15,15 +15,15 @@
/*************************************************
File name: board.c
Description: support imxrt1052-board init function
Description: support ok1052-c board init function
Others: take SDK_2.6.1_MIMXRT1052xxxxB for references
History:
1. Date: 2022-01-25
History:
1. Date: 2021-11-11
Author: AIIT XUOS Lab
Modification:
1. support imxrt1052-board MPU、clock、memory init
2. support imxrt1052-board uart、semc、sdio driver init
3. support imxrt1052-board I2C, SPI, ADC, RTC driver init
Modification:
1. support ok1052-c board MPU, Clock, Memory init
2. support ok1052-c board uart, semc, sdio driver init
3. support ok1052-c board I2C, SPI, ADC, RTC driver init
*************************************************/
#include "fsl_common.h"
@ -44,6 +44,9 @@ extern int ExtSramInit(void);
#if defined(FS_VFS) && defined(MOUNT_SDCARD)
#include <iot-vfs.h>
// SD card mount flag 1: OK
int sd_mount_flag = 0;
/**
* @description: Mount SD card
* @return 0
@ -51,10 +54,13 @@ extern int ExtSramInit(void);
int MountSDCard(void)
{
if (MountFilesystem(SDIO_BUS_NAME, SDIO_DEVICE_NAME, SDIO_DRIVER_NAME, FSTYPE_FATFS, "/") == 0)
{
sd_mount_flag = 1;
KPrintf("sd card mount to '/'");
}
else
KPrintf("sd card mount to '/' failed!");
return 0;
}
#endif
@ -72,15 +78,23 @@ int MountSDCard(void)
#ifdef BSP_USING_LWIP
#include <connect_ethernet.h>
#endif
#ifdef BSP_USING_LPUART
#include <connect_uart.h>
#endif
#ifdef BSP_USING_ADC
#include <connect_adc.h>
#endif
#ifdef BSP_USING_I2C
#include <connect_i2c.h>
#endif
#ifdef BSP_USING_SPI
#include <connect_spi.h>
#endif
#ifdef BSP_USING_RTC
#include <connect_rtc.h>
#endif
@ -685,6 +699,10 @@ void InitBoardHardware()
Imxrt1052HwAdcInit();
#endif
#ifdef BSP_USING_I2C
Imxrt1052HwI2cInit();
#endif
#ifdef BSP_USING_SPI
Imxrt1052HwSpiInit();
#endif

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4
Ubiquitous/XiZi/board/ok1052-c/include/board.h
View File

@ -7,7 +7,7 @@
/**
* @file board.h
* @brief define imxrt1052-board init configure and start-up function
* @brief define ok1052-c init configure and start-up function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
@ -15,7 +15,7 @@
/*************************************************
File name: board.h
Description: define imxrt1052-board board init function and struct
Description: define ok1052-c board init function and struct
Others:
History:
1. Date: 2021-05-28

4
Ubiquitous/XiZi/board/ok1052-c/include/clock_config.h
View File

@ -7,8 +7,8 @@
/**
* @file clock_config.h
* @brief define imxrt1052-board clock configure
* @version 1.0
* @brief define ok1052-c board clock configure
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-29
*/

2
Ubiquitous/XiZi/board/ok1052-c/include/pin_mux.h
View File

@ -7,7 +7,7 @@
/**
* @file pin_mux.h
* @brief define imxrt1052-board pin configure
* @brief define ok1052-c board pin configure
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-29

18
Ubiquitous/XiZi/board/ok1052-c/link-usb.lds
View File

@ -28,7 +28,7 @@
/**
* @file link.lds
* @brief ok1052-c Linker script
* @brief ok1052-c board Linker script
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
@ -36,7 +36,7 @@
/*************************************************
File name: link.lds
Description: ok1052-c Linker script
Description: ok1052-c board Linker script
Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references
History:
1. Date: 2021-05-28
@ -54,6 +54,9 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
/* Specify the memory areas */
MEMORY
{
m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000
m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000
m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400
m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
@ -63,6 +66,17 @@ MEMORY
/* Define output sections */
SECTIONS
{
.boot_data :
{
KEEP(*(.boot_hdr.conf))
} > m_boot_data
.image_vertor_table :
{
KEEP(*(.boot_hdr.ivt))
KEEP(*(.boot_hdr.boot_data))
KEEP(*(.boot_hdr.dcd_data))
} > m_image_vertor_table
/* The startup code goes first into internal RAM */
.interrupts :

18
Ubiquitous/XiZi/board/ok1052-c/link.lds
View File

@ -28,7 +28,7 @@
/**
* @file link.lds
* @brief ok1052-c Linker script
* @brief ok1052-c board Linker script
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
@ -36,7 +36,7 @@
/*************************************************
File name: link.lds
Description: ok1052-c Linker script
Description: ok1052-c board Linker script
Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references
History:
1. Date: 2021-05-28
@ -54,6 +54,9 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
/* Specify the memory areas */
MEMORY
{
m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000
m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000
m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400
m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
@ -63,6 +66,17 @@ MEMORY
/* Define output sections */
SECTIONS
{
.boot_data :
{
KEEP(*(.boot_hdr.conf))
} > m_boot_data
.image_vertor_table :
{
KEEP(*(.boot_hdr.ivt))
KEEP(*(.boot_hdr.boot_data))
KEEP(*(.boot_hdr.dcd_data))
} > m_image_vertor_table
/* The startup code goes first into internal RAM */
.interrupts :

4
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/common/clock_config.c
View File

@ -7,8 +7,8 @@
/**
* @file clock_config.c
* @brief support imxrt1052-board clock configure
* @version 1.0
* @brief support ok1052-c board clock configure
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-29
*/

4
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/common/pin_mux.c
View File

@ -7,7 +7,7 @@
/**
* @file pin_mux.c
* @brief support imxrt1052-board pin configure
* @brief support ok1052-c board pin configure
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-29
@ -271,7 +271,7 @@ void SemcPinmuxConfig(void)
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_41_SEMC_CSX00, /* GPIO_EMC_41 is configured as SEMC_CSX00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_00_SEMC_DATA00, /* GPIO_EMC_00 PAD functional properties : */
0x0110F9u); /* Slew Rate Field: Fast Slew Rate

67
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/gpio/connect_gpio.c
View File

@ -13,7 +13,7 @@
* @brief support gpio function using bus driver framework
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-03-16
* @date 2022-03-22
*/
/*************************************************
@ -22,7 +22,7 @@ Description: support gpio configure and register to bus framework
Others: take RT-Thread v4.0.2/bsp/imxrt/libraries/drivers/drv_gpio.c for references
https://github.com/RT-Thread/rt-thread/tree/v4.0.2
History:
1. Date: 2022-03-16
1. Date: 2022-03-22
Author: AIIT XUOS Lab
Modification: add bus driver framework support for gpio
*************************************************/
@ -215,6 +215,20 @@ struct PinIrqHdr pin_irq_hdr_tab[] =
{-1, 0, NONE, NONE},
};
#define MUX_BASE 0x401f8014
#define CONFIG_BASE 0x401f8204
#define GPIO5_MUX_BASE 0x400A8000
#define GPIO5_CONFIG_BASE 0x400A8018
const uint8_t reg_offset[] =
{
42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73,
74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,103,104,105,
112,113,114,115,116,117,118,119,120,121,122,123,106,107,108,109,110,111, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, -1, -1, -1, -1,
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
};
static int GetPin(struct PinIndex *pin_index, uint8_t pin)
{
pin_index->index = pin >> 5;//0:GPIO1 1:GPIO2 2:GPIO3 3:GPIO4 4:GPIO5
@ -229,39 +243,52 @@ static int GetPin(struct PinIndex *pin_index, uint8_t pin)
return 0;
}
static int32 GpioConfigMode(int mode, struct PinIndex *index)
static int32 GpioConfigMode(int mode, struct PinIndex *pin_index, int32 pin)
{
gpio_pin_config_t gpio_config;
NULL_PARAM_CHECK(index);
uint32_t config_value = 0;
NULL_PARAM_CHECK(pin_index);
gpio_config.outputLogic = 0;
gpio_config.interruptMode = kGPIO_NoIntmode;
switch (mode)
{
case GPIO_CFG_OUTPUT:
gpio_config.direction = kGPIO_DigitalOutput;
gpio_config.interruptMode = kGPIO_NoIntmode;
config_value = 0x0030U; /* Drive Strength R0/6 */
break;
case GPIO_CFG_INPUT:
gpio_config.direction = kGPIO_DigitalInput;
gpio_config.interruptMode = kGPIO_NoIntmode;
config_value = 0x0830U; /* Open Drain Enable */
break;
case GPIO_CFG_INPUT_PULLUP:
gpio_config.direction = kGPIO_DigitalInput;
gpio_config.interruptMode = kGPIO_NoIntmode;
config_value = 0xB030U; /* 100K Ohm Pull Up */
break;
case GPIO_CFG_INPUT_PULLDOWN:
gpio_config.direction = kGPIO_DigitalInput;
gpio_config.interruptMode = kGPIO_NoIntmode;
config_value = 0x3030U; /* 100K Ohm Pull Down */
break;
case GPIO_CFG_OUTPUT_OD:
gpio_config.direction = kGPIO_DigitalOutput;
gpio_config.interruptMode = kGPIO_NoIntmode;
config_value = 0x0830U; /* Open Drain Enable */
break;
default:
break;
}
GPIO_PinInit(index->gpio, index->pin, &gpio_config);
if (pin_mask[pin_index->index].gpio != GPIO5) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, 1);
IOMUXC_SetPinConfig(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, config_value);
} else {
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
IOMUXC_SetPinMux(GPIO5_MUX_BASE + pin_index->pin * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_index->pin * 4, 1);
IOMUXC_SetPinConfig(GPIO5_MUX_BASE + pin_index->pin * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_index->pin * 4, config_value);
}
GPIO_PinInit(pin_index->gpio, pin_index->pin, &gpio_config);
return EOK;
}
@ -385,6 +412,7 @@ static uint32 Imxrt1052PinConfigure(struct PinParam *param)
struct PinIndex pin_index;
KPrintf("Imxrt1052PinConfigure\n");
if (GetPin(&pin_index, param->pin) < 0) {
return ERROR;
}
@ -392,7 +420,8 @@ static uint32 Imxrt1052PinConfigure(struct PinParam *param)
switch(param->cmd)
{
case GPIO_CONFIG_MODE:
GpioConfigMode(param->mode, &pin_index);
KPrintf("GpioConfigMode %u\n", param->pin);
GpioConfigMode(param->mode, &pin_index, param->pin);
break;
case GPIO_IRQ_REGISTER:
ret = GpioIrqRegister(param->pin, param->irq_set.irq_mode, param->irq_set.hdr, param->irq_set.args);
@ -705,21 +734,6 @@ void GpioLedTest(void)
KPrintf("initialize %s failed!\n", PIN_BUS_NAME);
return;
}
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
0U); /* Software Input On Field: Input Path is determined by functionality */
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
struct PinParam led_gpio_param;
struct PinStat led_gpio_stat;
@ -762,4 +776,3 @@ void GpioLedTest(void)
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
GpioLedTest, GpioLedTest, GpioLedTest GPIO1 IO09 LED);
#endif

41
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/i2c/connect_i2c.c
View File

@ -1,43 +1,28 @@
/*
* Copyright (c) 2020 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2012-04-25 weety first version
*/
* Copyright (c) 2022 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_i2c.c
* @brief support ok1052-c i2c function and register to bus framework
* @brief support ok1052-c board i2c function and register to bus framework
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-03-01
*/
/*************************************************
File name: connect_i2c.c
Description: support ok1052-c i2c configure and i2c bus register function
Others: take RT-Thread v4.0.2/components/drivers/i2c/i2c-bit-ops.c for references
https://github.com/RT-Thread/rt-thread/tree/v4.0.2
History:
1. Date: 2022-03-01
Author: AIIT XUOS Lab
Modification:
1. support ok1052-c i2c bit configure, write and read
2. support ok1052-c i2c bus device and driver register
*************************************************/
#include <board.h>
#include "bus_serial.h"
#include "connect_i2c.h"
#include "fsl_lpi2c.h"
#ifndef BSP_USING_I2C1
#define BSP_USING_I2C1
#endif
static uint32 I2cWriteData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStandard *msg)
{
status_t ret;
@ -158,7 +143,7 @@ static int BoardI2cDevBend(void)
}
/*BOARD I2C INIT*/
int Stm32HwI2cInit(void)
int Imxrt1052HwI2cInit(void)
{
static int init_flag = 0;
x_err_t ret = EOK;
@ -174,7 +159,7 @@ int Stm32HwI2cInit(void)
static struct I2cDriver i2c_driver;
memset(&i2c_driver, 0, sizeof(struct I2cDriver));
#ifdef BSP_USING_I2C1
#ifdef BSP_USING_I2C
i2c_driver.configure = I2cDrvConfigure;
ret = BoardI2cBusInit(&i2c_bus, &i2c_driver);

45
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/i2c/connect_i2c_eeprom.c
View File

@ -1,40 +1,18 @@
/*
* The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
* Copyright (c) 2022 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_i2c_eeprom.h
* @brief ok1052-c eeprom relative codes
* @brief ok1052-c board eeprom relative codes
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-03-01
@ -87,7 +65,6 @@ void I2cEEpromTestWrite(void)
int I2cEEpromTest(void)
{
Stm32HwI2cInit();
BOARD_InitI2C1Pins();
I2cHardwareInit();
I2cEEpromTestWrite();

2
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/i2c/hardware_i2c.c
View File

@ -34,7 +34,7 @@
/**
* @file hardware_i2c.c
* @brief ok1052-c i2c relative codes
* @brief ok1052-c i2c board relative codes
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-03-01

6
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/include/connect_adc.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* Copyright (c) 2021 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
@ -12,8 +12,8 @@
/**
* @file connect_adc.h
* @brief define imxrt1052-baord adc function and struct
* @version 1.1
* @brief define ok1052-c board adc function and struct
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-12-28
*/

6
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/include/connect_gpio.h
View File

@ -12,10 +12,10 @@
/**
* @file connect_gpio.h
* @brief define imxrt1052-board gpio function and struct
* @version 2.0
* @brief define ok1052-c board gpio function and struct
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-03-15
* @date 2022-03-01
*/
#ifndef __CONNECT_GPIO_H_

6
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/include/connect_i2c.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* Copyright (c) 2021 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
@ -12,7 +12,7 @@
/**
* @file connect_i2c.h
* @brief define imxrt1052-baord i2c function and struct
* @brief define ok1052-c board i2c function and struct
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
@ -37,7 +37,7 @@ typedef struct Stm32I2c
#define i2c_print KPrintf
int Stm32HwI2cInit(void);
int Imxrt1052HwI2cInit(void);
#ifdef __cplusplus
}

2
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/include/connect_rtc.h
View File

@ -12,7 +12,7 @@
/**
* @file connect_rtc.h
* @brief define imxrt1052-baord rtc function and structure
* @brief define ok1052-c board rtc function and struct
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-03-01

8
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/include/connect_sdio.h
View File

@ -9,15 +9,15 @@
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_sdio.h
* @brief define imxrt1052-baord sdio function and struct
* @version 2.0
* @brief define ok1052-c board sdio function and struct
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-01-24
*/
#ifndef CONNECT_SDIO_H
#define CONNECT_SDIO_H

4
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/include/connect_spi.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* Copyright (c) 2021 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
@ -12,7 +12,7 @@
/**
* @file connect_spi.h
* @brief define imxrt1052-baord spi function and struct
* @brief define ok1052-c board spi function and struct
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25

14
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/include/connect_uart.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* Copyright (c) 2021 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
@ -9,11 +9,11 @@
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_uart.h
* @brief define imxrt1052-board usart function and struct
* @version 1.0
* @brief define ok1052-c board usart function and struct
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
*/
@ -27,10 +27,8 @@
extern "C" {
#endif
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1
#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1
#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1
#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
int Imxrt1052HwUartInit(void);

8
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/include/connect_usb.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* Copyright (c) 2022 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
@ -9,11 +9,11 @@
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_usb.h
* @brief define imxrt1052-baord usb function and struct
* @version 2.0
* @brief define ok1052-c board usb function and struct
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-02-09
*/

4
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/include/fsl_lpi2c.h
View File

@ -8,7 +8,7 @@
/**
* @file fsl_lpi2c.h
* @brief support ok1052-c i2c driver
* @brief support ok1052-c board i2c driver
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-03-01
@ -16,7 +16,7 @@
/*************************************************
File name: fsl_lpi2c.h
Description: support ok1052-c i2c driver
Description: support ok1052-c board i2c driver
History:
1. Date: 2022-03-01

5
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/rtc/connect_rtc.c
View File

@ -34,7 +34,7 @@
/**
* @file connect_rtc.c
* @brief ok1052-c rtc function and structure
* @brief ok1052-c board rtc function and structure
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-03-01
@ -42,13 +42,14 @@
/*************************************************
File name: connect_rtc.c
Description: support ok1052-c rtc configure and spi bus register function
Description: support ok1052-c board rtc configure and spi bus register function
History:
1. Date: 2022-03-01
Author: AIIT XUOS Lab
Modification:
1. change command for XUOS
2. add module codes for XUOS
*************************************************/
#include "board.h"

4
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/rtc/hardware_rtc.c
View File

@ -42,13 +42,13 @@
/*************************************************
File name: hardware_rtc.c
Description: support ok1052-c rtc driver I2C function
Description: support ok1052-c board rtc hardware driver I2C function
History:
1. Date: 2022-01-18
Author: AIIT XUOS Lab
Modification:
1. support ok1052-c rtc
1. support ok1052-c board rtc
*************************************************/
#include "connect_rtc.h"

18
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/sdio/connect_sdio.c
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@ -9,21 +9,21 @@
/**
* @file connect_sdio.c
* @brief support sdio function using bus driver framework on OK1052 board
* @version 2.0
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-01-24
*/
/*************************************************
File name: connect_sdio.c
Description: support imxrt1052-board sd card configure and sdio bus register function
Description: support ok1052-c board sd card configure and sdio bus register function
Others: take SDK_2.6.1_MIMXRT1052xxxxB/boards/evkbimxrt1050/driver_examples/sdcard/polling/sdcard_polling.c for references
History:
History:
1. Date: 2022-01-24
Author: AIIT XUOS Lab
Modification:
1. support imxrt1052-board sdio configure, write and read
2. support imxrt1052-board sdio bus device and driver register
Modification:
1. support ok1052-c board sdio configure, write and read
2. support ok1052-c board sdio bus device and driver register
*************************************************/
#include <connect_sdio.h>
@ -261,7 +261,7 @@ static uint32 SdioWrite(void *dev, struct BusBlockWriteParam *write_param)
return write_param->size;
}
static struct SdioDevDone dev_done =
static struct SdioDevDone dev_done =
{
SdioOpen,
SdioClose,
@ -273,7 +273,7 @@ int Imxrt1052HwSdioInit(void)
{
x_err_t ret = EOK;
bool is_read_only;
static struct SdioBus sdio_bus;
static struct SdioDriver sdio_drv;
static struct SdioHardwareDevice sdio_dev;
@ -333,7 +333,7 @@ int Imxrt1052HwSdioInit(void)
/* Check if card is readonly. */
is_read_only = SD_CheckReadOnly(card);
ret = SdioBusInit(&sdio_bus, SDIO_BUS_NAME);
if (ret != EOK) {
KPrintf("Sdio bus init error %d\n", ret);

20
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/semc/fsl_semc.c
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@ -5,26 +5,6 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/**
* @file board.c
* @brief relative configure for ok1052-c
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021.11.11
*/
/*************************************************
File name: board.c
Description: support imxrt1052-board init function
Others: take SDK_2.6.1_MIMXRT1052xxxxB for references
History:
1. Date: 2022-01-25
Author: AIIT XUOS Lab
Modification:
1. support imxrt1052-board MPU、clock、memory init
2. support imxrt1052-board uart、semc、sdio driver init
*************************************************/
#include "fsl_semc.h"
/*******************************************************************************

6
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/spi/connect_flash_spi.c
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@ -10,7 +10,7 @@
/**
* @file connect_flash_spi.c
* @brief support ok1052-c-board spi flash function and register to bus framework
* @brief support ok1052-c board spi flash function and register to bus framework
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-03-01
@ -18,14 +18,14 @@
/*************************************************
File name: connect_flash_spi.c
Description: support ok1052-c-board spi flash bus register function
Description: support ok1052-c board spi flash bus register function
Others: take RT-Thread v4.0.2/bsp/stm32/stm32f407-atk-explorer/board/ports/spi-flash-init.c
https://github.com/RT-Thread/rt-thread/tree/v4.0.2
History:
1. Date: 2022-03-01
Author: AIIT XUOS Lab
Modification:
1. for ok1052-c compilation
1. for ok1052-c board compilation
*************************************************/
#include "flash_spi.h"

11
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/spi/connect_spi.c
View File

@ -15,7 +15,7 @@
/**
* @file connect_spi.c
* @brief support ok1052-c spi function and register to bus framework
* @brief support ok1052-c board spi function and register to bus framework
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-03-01
@ -23,16 +23,16 @@
/*************************************************
File name: connect_spi.c
Description: support ok1052-c spi configure and spi bus register function
Description: support ok1052-c board spi configure and spi bus register function
Others: take RT-Thread v4.0.2/bsp/stm32/libraries/HAL_Drivers/drv_spi.c for references
https://github.com/RT-Thread/rt-thread/tree/v4.0.2
History:
1. Date: 2022-03-01
Author: AIIT XUOS Lab
Modification:
1. support ok1052-c spi configure, write and read
2. support ok1052-c spi bus device and driver register
3. add ok1052-c spi test letter command
1. support ok1052-c board spi configure, write and read
2. support ok1052-c board spi bus device and driver register
3. add ok1052-c board spi test letter command
*************************************************/
#include "board.h"
@ -58,7 +58,6 @@ Modification:
#define TRANSFER_BAUDRATE (500000U) /*! Transfer baudrate - 500k */
#define spi_print KPrintf
#define spi_trace() KPrintf("lw: [%s][%d] passed!\n", __func__, __LINE__)
typedef struct __spi_transfer_t
{

32
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/uart/connect_uart.c
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@ -8,22 +8,22 @@
/**
* @file connect_uart.c
* @brief support imxrt1052-board uart function and register to bus framework
* @version 1.0
* @brief support ok1052-c board uart function and register to bus framework
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
*/
/*************************************************
File name: connect_uart.c
Description: support imxrt1052-board uart configure and uart bus register function
Description: support ok1052-c board uart configure and uart bus register function
Others: take SDK_2.6.1_MIMXRT1052xxxxB/components/uart/lpuart_adapter.c for references
History:
History:
1. Date: 2021-05-28
Author: AIIT XUOS Lab
Modification:
1. support imxrt1052-board uart configure, write and read
2. support imxrt1052-board uart bus device and driver register
Modification:
1. support ok1052-c board uart configure, write and read
2. support ok1052-c board uart bus device and driver register
*************************************************/
#include <board.h>
@ -105,7 +105,7 @@ static void UartIsr(struct SerialBus *serial, struct SerialDriver *serial_drv, s
{
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data;
/* kLPUART_RxDataRegFullFlag can only cleared or set by hardware */
if (LPUART_GetStatusFlags(uart_base) & kLPUART_RxDataRegFullFlag) {
SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
@ -262,7 +262,7 @@ static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_i
return ret;
}
static const struct SerialDataCfg data_cfg_init =
static const struct SerialDataCfg data_cfg_init =
{
.serial_baud_rate = BAUD_RATE_115200,
.serial_data_bits = DATA_BITS_8,
@ -310,7 +310,7 @@ static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver
if (EOK != ret) {
KPrintf("Imxrt1052HwUartInit SerialDriverAttachToBus error %d\n", ret);
return ERROR;
}
}
return ret;
}
@ -324,13 +324,13 @@ static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *
if (EOK != ret) {
KPrintf("Imxrt1052HwUartInit SerialDeviceInit device %s error %d\n", dev_name, ret);
return ERROR;
}
}
ret = SerialDeviceAttachToBus(dev_name, bus_name);
if (EOK != ret) {
KPrintf("Imxrt1052HwUartInit SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
return ERROR;
}
}
return ret;
}
@ -345,7 +345,7 @@ int Imxrt1052HwUartInit(void)
static struct SerialDevParam serial_dev_param_1;
memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
serial_driver_1.drv_done = &drv_done;
serial_driver_1.configure = &SerialDrvConfigure;
serial_device_1.hwdev_done = &hwdev_done;
@ -369,7 +369,7 @@ int Imxrt1052HwUartInit(void)
if (EOK != ret) {
KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
return ERROR;
}
}
#endif
#ifdef BSP_USING_LPUART2
@ -378,7 +378,7 @@ int Imxrt1052HwUartInit(void)
static struct SerialDevParam serial_dev_param_2;
memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
serial_driver_2.drv_done = &drv_done;
serial_driver_2.configure = &SerialDrvConfigure;
serial_device_2.hwdev_done = &hwdev_done;
@ -402,7 +402,7 @@ int Imxrt1052HwUartInit(void)
if (EOK != ret) {
KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret);
return ERROR;
}
}
#endif
return ret;

24
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/usb/connect_usb.c
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@ -9,21 +9,21 @@
/**
* @file connect_usb.c
* @brief support usb host function using bus driver framework on OK1052 board
* @version 2.0
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-02-09
*/
/*************************************************
File name: connect_usb.c
Description: support imxrt1052-board usb host configure and sdio bus register function
Description: support ok1052-c board usb host configure and sdio bus register function
Others: take SDK_2.6.1_MIMXRT1052xxxxB/boards/evkbimxrt1050/usb_examples/usb_host_msd_command for references
History:
History:
1. Date: 2022-02-09
Author: AIIT XUOS Lab
Modification:
1. support imxrt1052-board usb host configure, write and read
2. support imxrt1052-board usb host bus device and driver register
Modification:
1. support ok1052-c board usb host configure, write and read
2. support ok1052-c board usb host bus device and driver register
*************************************************/
#include <board.h>
#include <connect_usb.h>
@ -202,7 +202,7 @@ static void UsbHostTask(void* parameter)
}
}
/*Init usb host bus、driver*/
/*Init usb host bus driver*/
static int BoardUsbBusInit(struct UsbBus *usb_bus, struct UsbDriver *usb_driver)
{
x_err_t ret = EOK;
@ -255,7 +255,7 @@ static int BoardUsbDevBend(void)
return ret;
}
/*RT1052 BOARD USB INIT*/
/*OK1052-C BOARD USB INIT*/
int Imxrt1052HwUsbHostInit(void)
{
x_err_t ret = EOK;
@ -283,10 +283,10 @@ int Imxrt1052HwUsbHostInit(void)
usb_host_task = KTaskCreate("usbh", UsbHostTask, NONE,
USB_HOST_STACK_SIZE, 8);
if(usb_host_task < 0) {
KPrintf("usb_host_task create failed ...%s %d.\n", __FUNCTION__,__LINE__);
return ERROR;
}
if(usb_host_task < 0) {
KPrintf("usb_host_task create failed ...%s %d.\n", __FUNCTION__,__LINE__);
return ERROR;
}
StartupKTask(usb_host_task);

3
Ubiquitous/XiZi/board/ok1052-c/xip/Makefile Executable file
View File

@ -0,0 +1,3 @@
SRC_FILES := fsl_flexspi_nor_boot.c fsl_flexspi_nor_flash.c
include $(KERNEL_ROOT)/compiler.mk

1149
Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_boot.c Normal file
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123
Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_boot.h Normal file
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@ -0,0 +1,123 @@
/*
* Copyright 2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file fsl_flexspi_nor_boot.h
* @brief support to register flexspi image vector table
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-03-22
*/
#ifndef _QUADSPI_BOOT_H_
#define _QUADSPI_BOOT_H_
#include <stdint.h>
/*************************************
* IVT Data
*************************************/
typedef struct _ivt_ {
/** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields
* (see @ref data)
*/
uint32_t hdr;
/** Absolute address of the first instruction to execute from the
* image
*/
uint32_t entry;
/** Reserved in this version of HAB: should be NULL. */
uint32_t reserved1;
/** Absolute address of the image DCD: may be NULL. */
uint32_t dcd;
/** Absolute address of the Boot Data: may be NULL, but not interpreted
* any further by HAB
*/
uint32_t boot_data;
/** Absolute address of the IVT.*/
uint32_t self;
/** Absolute address of the image CSF.*/
uint32_t csf;
/** Reserved in this version of HAB: should be zero. */
uint32_t reserved2;
} ivt;
#define IVT_MAJOR_VERSION 0x4
#define IVT_MAJOR_VERSION_SHIFT 0x4
#define IVT_MAJOR_VERSION_MASK 0xF
#define IVT_MINOR_VERSION 0x1
#define IVT_MINOR_VERSION_SHIFT 0x0
#define IVT_MINOR_VERSION_MASK 0xF
#define IVT_VERSION(major, minor) \
((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \
(((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT))
#define IVT_TAG_HEADER (0xD1) /**< Image Vector Table */
#define IVT_SIZE 0x2000
#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION)
#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24))
#define IVT_RSVD (uint32_t)(0x00000000)
/*************************************
* Boot Data
*************************************/
typedef struct _boot_data_ {
uint32_t start; /* boot start location */
uint32_t size; /* size */
uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */
uint32_t placeholder; /* placehoder to make even 0x10 size */
}BOOT_DATA_T;
/*************************************
* DCD Data
*************************************/
#define DCD_TAG_HEADER (0xD2)
#define DCD_TAG_HEADER_SHIFT (24)
#define DCD_VERSION (0x40)
#define DCD_ARRAY_SIZE 1
#define FLASH_BASE 0x60000000
#define FLASH_END 0x7F7FFFFF
#define SCLK 1
#define DCD_ADDRESS dcd_sdram
#define BOOT_DATA_ADDRESS &boot_data
#define CSF_ADDRESS 0
#define PLUGIN_FLAG (uint32_t)0
/* External Variables */
//extern const uint8_t dcd_sdram[1044];
extern const uint8_t dcd_sdram[1072];
extern const BOOT_DATA_T boot_data;
#endif

88
Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_flash.c Normal file
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@ -0,0 +1,88 @@
/*
* Copyright 2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file fsl_flexspi_nor_flash.c
* @brief support to define flexspi flash config
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-03-22
*/
#include "fsl_flexspi_nor_flash.h"
/*******************************************************************************
* Code
******************************************************************************/
#if defined(__CC_ARM) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf")))
#elif defined(__ICCARM__)
#pragma location=".boot_hdr.conf"
#endif
const flexspi_nor_config_t Qspiflash_config =
{
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally,
.csHoldTime = 3u,
.csSetupTime = 3u,
.deviceModeCfgEnable = true,
.deviceModeType = 1,//Quad Enable command
.deviceModeSeq.seqNum = 1,
.deviceModeSeq.seqId = 4,
.deviceModeArg = 0x000200,//Set QE
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_60MHz,//80MHz for Winbond, 100MHz for GD, 133MHz for ISSI
.sflashA1Size = 16u * 1024u * 1024u,//4MBytes
.dataValidTime = {16u, 16u},
.lookupTable =
{
// //Fast Read Sequence
// [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B, RADDR_SDR, FLEXSPI_1PAD, 0x18),
// [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 0x08, READ_SDR, FLEXSPI_1PAD, 0x08),
// [2] = FLEXSPI_LUT_SEQ(JMP_ON_CS, 0, 0, 0, 0, 0),
//Quad Input/output read sequence
[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
[2] = FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0),
//Read Status
[1*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
//Write Enable
[3*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, 0, 0),
//Write status
[4*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x2),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
};

303
Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_flash.h Normal file
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@ -0,0 +1,303 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without
* modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this
* list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice,
* this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file fsl_flexspi_nor_flash.h
* @brief support to define flexspi flash config
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-03-22
*/
#ifndef __FLEXSPI_NOR_FLASH_H__
#define __FLEXSPI_NOR_FLASH_H__
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/* FLEXSPI memory config block related defintions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)
/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
/* Lookup table related defintions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq
{
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_133MHz = 7,
kFlexSpiSerialClk_166MHz = 8,
kFlexSpiSerialClk_200MHz = 9,
} flexspi_serial_clk_freq_t;
//!@brief FlexSPI clock configuration type
enum
{
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};
//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource
{
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;
//!@brief Misc feature bit definitions
enum
{
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};
//!@brief Flash Type Definition
enum
{
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};
//!@brief Flash Pad Definitions
enum
{
kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
};
//!@brief FlexSPI LUT Sequence structure
typedef struct _lut_sequence
{
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
uint8_t seqId; //!< Sequence Index, valid number: 0-15
uint16_t reserved;
} flexspi_lut_seq_t;
//!@brief Flash Configuration Command Type
enum
{
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
kDeviceConfigCmdType_Reset, //!< Reset device command
};
//!@brief FlexSPI Memory Configuration Block
typedef struct _FlexSPIConfig
{
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
//! Serial NAND, need to refer to datasheet
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
//! Generic configuration, etc.
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
//! DPI/QPI/OPI switch or reset command
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
//! sequence number, [31:16] Reserved
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
flexspi_lut_seq_t
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
//! details
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
//! Chapter for more details
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
//! busy flag is 0 when flash device is busy
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
} flexspi_mem_config_t;
/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
/*
* Serial NOR configuration block
*/
typedef struct _flexspi_nor_config
{
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
uint32_t pageSize; //!< Page size of Serial NOR
uint32_t sectorSize; //!< Sector size of Serial NOR
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
uint8_t reserved0[2]; //!< Reserved for future use
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
uint32_t blockSize; //!< Block size
uint32_t reserve2[11]; //!< Reserved for future use
} flexspi_nor_config_t;
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif // __FLEXSPI_NOR_FLASH_H__

2
Ubiquitous/XiZi/board/xidatong/Makefile
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@ -1,4 +1,4 @@
SRC_DIR := third_party_driver
SRC_DIR := third_party_driver xip
SRC_FILES := board.c

11
Ubiquitous/XiZi/board/xidatong/README.md
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@ -156,8 +156,17 @@ make BOARD=xidatong
## 3. 烧写及运行
### 3.1 烧写
1、烧写工具：NXP MCU Boot Utility，可参考[https://github.com/JayHeng/NXP-MCUBootUtility](https://github.com/JayHeng/NXP-MCUBootUtility)
2、xidatong开发板支持UART串口烧写程序，打开NXP MCU Boot Utility后，选择好芯片类型为i.MXRT105x，开发板上电，使用串口转USB线将开发板和PC连接，拨码开关设置为1 on 2 on 3 off 4 off，重新上电，选择对应的COM口和波特率（需关闭串口终端连接，确保该COM口空闲，否则会导致Utility工具连接失败），连接成功后，点击reconnect，等待NXP MCU Boot Utility中红色显示变成蓝色显示，则表示已正确识别并连接到了开发板。如下图所示：
![NXPBootUtility_1](./img/NXPBootUtility_1.png)
3、同时需要匹配xidatong开发板所使用的Flash型号，点击Boot Device Configuration，在Use Typical Device中选择Winbond_W25QxxxJV，然后点击ok。如下图所示：
![flashconfig](./img/flashconfig.png)
4、选择编译生成的XiZi_xidatong.elf或bin文件路径，按照图示步骤，将文件烧写至Flash中（link.lds中已构造Flash Bootable image，如有修改Flash相关配置需求，可修改/xip目录内相关文件，无需NXPBootUtility再次构造），若烧写无误，则下列绿色进度条会执行到底。如下图所示：
![NXPBootUtility_2](./img/NXPBootUtility_2.png)
### 3.2 运行结果
按照3.1烧写步骤执行后，将拨码开关设置为1 off 2 off 3 off 4 off，重新上电后，重新打开该COM口串口终端，若程序正常，则串口终端上会显示启动信息打印输出。如下图所示：
![terminal](./img/terminal.png)

8
Ubiquitous/XiZi/board/xidatong/board.c
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@ -300,22 +300,18 @@ void InitBoardHardware()
BOARD_InitUartPins();
#endif
#ifdef BSP_USING_CH438
BOARD_InitCh438Pins();
#endif
InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END);
#ifdef BSP_USING_LPUART
Imxrt1052HwUartInit();
#endif
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
#ifdef BSP_USING_CH438
Imxrt1052HwCh438Init();
#endif
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
#ifdef BSP_USING_SDIO
Imxrt1052HwSdioInit();
#endif

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14
Ubiquitous/XiZi/board/xidatong/link-usb.lds
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@ -54,6 +54,9 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
/* Specify the memory areas */
MEMORY
{
m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000
m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000
m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400
m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
@ -63,6 +66,17 @@ MEMORY
/* Define output sections */
SECTIONS
{
.boot_data :
{
KEEP(*(.boot_hdr.conf))
} > m_boot_data
.image_vertor_table :
{
KEEP(*(.boot_hdr.ivt))
KEEP(*(.boot_hdr.boot_data))
KEEP(*(.boot_hdr.dcd_data))
} > m_image_vertor_table
/* The startup code goes first into internal RAM */
.interrupts :

14
Ubiquitous/XiZi/board/xidatong/link.lds
View File

@ -54,6 +54,9 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
/* Specify the memory areas */
MEMORY
{
m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000
m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000
m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400
m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
@ -63,7 +66,18 @@ MEMORY
/* Define output sections */
SECTIONS
{
.boot_data :
{
KEEP(*(.boot_hdr.conf))
} > m_boot_data
.image_vertor_table :
{
KEEP(*(.boot_hdr.ivt))
KEEP(*(.boot_hdr.boot_data))
KEEP(*(.boot_hdr.dcd_data))
} > m_image_vertor_table
/* The startup code goes first into internal RAM */
.interrupts :
{

39
Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Kconfig Normal file
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@ -0,0 +1,39 @@
config CH438_BUS_NAME
string
default "extuart"
config CH438_DRIVER_NAME
string
default "extuart_drv"
config CH438_DEVICE_NAME_0
string
default "extuart_dev0"
config CH438_DEVICE_NAME_1
string
default "extuart_dev1"
config CH438_DEVICE_NAME_2
string
default "extuart_dev2"
config CH438_DEVICE_NAME_3
string
default "extuart_dev3"
config CH438_DEVICE_NAME_4
string
default "extuart_dev4"
config CH438_DEVICE_NAME_5
string
default "extuart_dev5"
config CH438_DEVICE_NAME_6
string
default "extuart_dev6"
config CH438_DEVICE_NAME_7
string
default "extuart_dev7"

4
Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Makefile Normal file
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@ -0,0 +1,4 @@
SRC_FILES := connect_ch438.c
include $(KERNEL_ROOT)/compiler.mk

1296
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247
Ubiquitous/XiZi/board/xidatong/third_party_driver/common/pin_mux.c
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@ -8,9 +8,9 @@
/**
* @file pin_mux.c
* @brief support imxrt1052-board pin configure
* @version 1.0
* @version 2.0
* @author AIIT XUOS Lab
* @date 2021-05-29
* @date 2022-03-22
*/
/***********************************************************************************************************************
@ -749,121 +749,9 @@ BOARD_InitPins:
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitSPIPins ( void )
{
IOMUXC_SetPinMux (
IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK, /* GPIO_AD_B0_00 is configured as LPSPI3_SCK */
0U ); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux (
IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO, /* GPIO_AD_B0_01 is configured as LPSPI3_SDO */
0U ); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux (
IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI, /* GPIO_AD_B0_02 is configured as LPSPI3_SDI */
0U ); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux (
IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0, /* GPIO_AD_B0_03 is configured as LPSPI3_PCS0 */
0U ); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux (
IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK, /* GPIO_SD_B0_00 is configured as LPSPI1_SCK */
0U ); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux (
IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0, /* GPIO_SD_B0_01 is configured as LPSPI1_PCS0 */
0U ); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux (
IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO, /* GPIO_SD_B0_02 is configured as LPSPI1_SDO */
0U ); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux (
IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI, /* GPIO_SD_B0_03 is configured as LPSPI1_SDI */
0U ); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig (
IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK, /* GPIO_AD_B0_00 PAD functional properties : */
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig (
IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO, /* GPIO_AD_B0_01 PAD functional properties : */
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig (
IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI, /* GPIO_AD_B0_02 PAD functional properties : */
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig (
IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0, /* GPIO_AD_B0_03 PAD functional properties : */
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig (
IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK, /* GPIO_SD_B0_00 PAD functional properties : */
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig (
IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0, /* GPIO_SD_B0_01 PAD functional properties : */
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig (
IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO, /* GPIO_SD_B0_02 PAD functional properties : */
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig (
IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI, /* GPIO_SD_B0_03 PAD functional properties : */
0x10B0u ); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
}
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
// IOMUXC_SetPinMux(
// IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
// 0U); /* Software Input On Field: Input Path is determined by functionality */
/* Software Input On Field: Input Path is determined by functionality */
SemcPinmuxConfig();
IOMUXC_SetPinMux(
@ -914,16 +802,6 @@ void BOARD_InitPins(void) {
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */
0U); /* Software Input On Field: Input Path is determined by functionality */
// IOMUXC_SetPinConfig(
// IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */
// 0xB0A9u); /* Slew Rate Field: Fast Slew Rate
// Drive Strength Field: R0/5
// Speed Field: medium(100MHz)
// Open Drain Enable Field: Open Drain Disabled
// Pull / Keep Enable Field: Pull/Keeper Enabled
// Pull / Keep Select Field: Pull
// Pull Up / Down Config. Field: 100K Ohm Pull Up
// Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_03_GPIO1_IO03, /* GPIO_AD_B0_09 PAD functional properties : */
@ -1073,37 +951,6 @@ void BOARD_InitPins(void) {
Hyst. Enable Field: Hysteresis Disabled */
}
void BOARD_InitI2C1Pins ( void )
{
CLOCK_EnableClock ( kCLOCK_Iomuxc ); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
IOMUXC_SetPinMux (
IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 is configured as LPI2C1_SCL */
1U ); /* Software Input On Field: Force input path of pad GPIO_AD_B1_00 */
IOMUXC_SetPinMux (
IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 is configured as LPI2C1_SDA */
1U ); /* Software Input On Field: Force input path of pad GPIO_AD_B1_01 */
IOMUXC_SetPinConfig (
IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 PAD functional properties : */
0xD8B0u ); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Enabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 22K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig (
IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 PAD functional properties : */
0xD8B0u ); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Enabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 22K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
}
void BOARD_InitUartPins(void)
{
#ifdef BSP_USING_LPUART1
@ -1150,94 +997,6 @@ void BOARD_InitUartPins(void)
#endif
}
void BOARD_InitCh438Pins(void)
{
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_09_GPIO1_IO25, /* GPIO1_IO25 is configured as CH438_DATA0 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_08_GPIO1_IO24, /* GPIO1_IO24 is configured as CH438_DATA1 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_04_GPIO1_IO20, /* GPIO1_IO20 is configured as CH438_DATA2 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_05_GPIO1_IO21, /* GPIO1_IO21 is configured as CH438_DATA3 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_15_GPIO1_IO31, /* GPIO1_IO31 is configured as CH438_DATA4 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_12_GPIO1_IO28, /* GPIO1_IO28 is configured as CH438_DATA5 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_14_GPIO1_IO30, /* GPIO1_IO30 is configured as CH438_DATA6 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_13_GPIO1_IO29, /* GPIO1_IO29 is configured as CH438_DATA7 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_04_GPIO3_IO04, /* GPIO3_IO04 is configured as CH438_nWR */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_05_GPIO3_IO05, /* GPIO3_IO05 is configured as CH438_nRD */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_02_GPIO3_IO02, /* GPIO3_IO02 is configured as CH438_ALE */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_03_GPIO3_IO03, /* GPIO3_IO03 is configured as CH438_INT */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, /* GPIO3_IO02 is configured as CH438_485_A_DIR */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_00_GPIO1_IO00, /* GPIO1_IO00 is configured as CH438_485_B_DIR */
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_09_GPIO1_IO25, /* GPIO1_IO25 is configured as CH438_DATA0 */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_08_GPIO1_IO24, /* GPIO1_IO24 is configured as CH438_DATA1 */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_04_GPIO1_IO20, /* GPIO1_IO20 is configured as CH438_DATA2 */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_05_GPIO1_IO21, /* GPIO1_IO21 is configured as CH438_DATA3 */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_15_GPIO1_IO31, /* GPIO1_IO31 is configured as CH438_DATA4 */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_12_GPIO1_IO28, /* GPIO1_IO28 is configured as CH438_DATA5 */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_14_GPIO1_IO30, /* GPIO1_IO30 is configured as CH438_DATA6 */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_13_GPIO1_IO29, /* GPIO1_IO29 is configured as CH438_DATA7 */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_SD_B1_04_GPIO3_IO04, /* GPIO3_IO04 is configured as CH438_nWR */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_SD_B1_05_GPIO3_IO05, /* GPIO3_IO05 is configured as CH438_nRD */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_SD_B1_02_GPIO3_IO02, /* GPIO3_IO02 is configured as CH438_ALE */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_SD_B1_03_GPIO3_IO03, /* GPIO3_IO03 is configured as CH438_INT */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, /* GPIO3_IO02 is configured as CH438_485_A_DIR */
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_00_GPIO1_IO00, /* GPIO1_IO00 is configured as CH438_485_B_DIR */
0x10B0u);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

63
Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/connect_gpio.c
View File

@ -215,6 +215,20 @@ struct PinIrqHdr pin_irq_hdr_tab[] =
{-1, 0, NONE, NONE},
};
#define MUX_BASE 0x401f8014
#define CONFIG_BASE 0x401f8204
#define GPIO5_MUX_BASE 0x400A8000
#define GPIO5_CONFIG_BASE 0x400A8018
const uint8_t reg_offset[] =
{
42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73,
74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,103,104,105,
112,113,114,115,116,117,118,119,120,121,122,123,106,107,108,109,110,111, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, -1, -1, -1, -1,
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
};
static int GetPin(struct PinIndex *pin_index, uint8_t pin)
{
pin_index->index = pin >> 5;//0:GPIO1 1:GPIO2 2:GPIO3 3:GPIO4 4:GPIO5
@ -229,39 +243,52 @@ static int GetPin(struct PinIndex *pin_index, uint8_t pin)
return 0;
}
static int32 GpioConfigMode(int mode, struct PinIndex *index)
static int32 GpioConfigMode(int mode, struct PinIndex *pin_index, int32 pin)
{
gpio_pin_config_t gpio_config;
NULL_PARAM_CHECK(index);
uint32_t config_value = 0;
NULL_PARAM_CHECK(pin_index);
gpio_config.outputLogic = 0;
gpio_config.interruptMode = kGPIO_NoIntmode;
switch (mode)
{
case GPIO_CFG_OUTPUT:
gpio_config.direction = kGPIO_DigitalOutput;
gpio_config.interruptMode = kGPIO_NoIntmode;
config_value = 0x0030U; /* Drive Strength R0/6 */
break;
case GPIO_CFG_INPUT:
gpio_config.direction = kGPIO_DigitalInput;
gpio_config.interruptMode = kGPIO_NoIntmode;
config_value = 0x0830U; /* Open Drain Enable */
break;
case GPIO_CFG_INPUT_PULLUP:
gpio_config.direction = kGPIO_DigitalInput;
gpio_config.interruptMode = kGPIO_NoIntmode;
config_value = 0xB030U; /* 100K Ohm Pull Up */
break;
case GPIO_CFG_INPUT_PULLDOWN:
gpio_config.direction = kGPIO_DigitalInput;
gpio_config.interruptMode = kGPIO_NoIntmode;
config_value = 0x3030U; /* 100K Ohm Pull Down */
break;
case GPIO_CFG_OUTPUT_OD:
gpio_config.direction = kGPIO_DigitalOutput;
gpio_config.interruptMode = kGPIO_NoIntmode;
config_value = 0x0830U; /* Open Drain Enable */
break;
default:
break;
}
GPIO_PinInit(index->gpio, index->pin, &gpio_config);
if (pin_mask[pin_index->index].gpio != GPIO5) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, 1);
IOMUXC_SetPinConfig(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, config_value);
} else {
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
IOMUXC_SetPinMux(GPIO5_MUX_BASE + pin_index->pin * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_index->pin * 4, 1);
IOMUXC_SetPinConfig(GPIO5_MUX_BASE + pin_index->pin * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_index->pin * 4, config_value);
}
GPIO_PinInit(pin_index->gpio, pin_index->pin, &gpio_config);
return EOK;
}
@ -385,6 +412,7 @@ static uint32 Imxrt1052PinConfigure(struct PinParam *param)
struct PinIndex pin_index;
KPrintf("Imxrt1052PinConfigure\n");
if (GetPin(&pin_index, param->pin) < 0) {
return ERROR;
}
@ -392,7 +420,8 @@ static uint32 Imxrt1052PinConfigure(struct PinParam *param)
switch(param->cmd)
{
case GPIO_CONFIG_MODE:
GpioConfigMode(param->mode, &pin_index);
KPrintf("GpioConfigMode %u\n", param->pin);
GpioConfigMode(param->mode, &pin_index, param->pin);
break;
case GPIO_IRQ_REGISTER:
ret = GpioIrqRegister(param->pin, param->irq_set.irq_mode, param->irq_set.hdr, param->irq_set.args);
@ -705,21 +734,6 @@ void GpioLedTest(void)
KPrintf("initialize %s failed!\n", PIN_BUS_NAME);
return;
}
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
0U); /* Software Input On Field: Input Path is determined by functionality */
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
struct PinParam led_gpio_param;
struct PinStat led_gpio_stat;
@ -762,4 +776,3 @@ void GpioLedTest(void)
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
GpioLedTest, GpioLedTest, GpioLedTest GPIO1 IO09 LED);
#endif

277
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_ch438.h Executable file
View File

@ -0,0 +1,277 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_ch438.h
* @brief define imxrt1052-board ch438 function and struct
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-03-15
*/
#ifndef CONNECT_CH438_H
#define CONNECT_CH438_H
#include <board.h>
#include <device.h>
#include <connect_gpio.h>
#define CH438_BUFFSIZE 255
/******************************************************************************************/
/* chip definition */
/* CH438serial port0 register address */
#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */
#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */
#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */
#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */
#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */
#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */
#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */
#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */
#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */
#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */
#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port1 register address */
#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */
#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */
#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */
#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */
#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */
#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */
#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */
#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */
#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */
#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */
#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port2 register address */
#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */
#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */
#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */
#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */
#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */
#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */
#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */
#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */
#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */
#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */
#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port3 register address */
#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */
#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */
#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */
#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */
#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */
#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */
#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */
#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */
#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */
#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */
#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port4 register address */
#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */
#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */
#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */
#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */
#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */
#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */
#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */
#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */
#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */
#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */
#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port5 register address */
#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */
#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */
#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */
#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */
#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */
#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */
#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */
#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */
#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */
#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */
#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port6 register address */
#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */
#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */
#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */
#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */
#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */
#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */
#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */
#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */
#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */
#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */
#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port7 register address */
#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */
#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */
#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */
#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */
#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */
#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */
#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */
#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */
#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */
#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */
#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */
#define REG_SSR_ADDR 0x4F /* pecial status register address */
/* IER register bit */
#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */
#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */
#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */
#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */
#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */
#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */
#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */
#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */
/* IIR register bit */
#define BIT_IIR_FIFOENS1 0x80
#define BIT_IIR_FIFOENS0 0x40 /* The two is 1 said use FIFO */
/* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted,
1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */
#define BIT_IIR_IID3 0x08
#define BIT_IIR_IID2 0x04
#define BIT_IIR_IID1 0x02
#define BIT_IIR_NOINT 0x01
/* FCR register bit */
/* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */
#define BIT_FCR_RECVTG1 0x80 /* Set the trigger point for FIFO interruption and automatic hardware flow control */
#define BIT_FCR_RECVTG0 0x40 /* Set the trigger point for FIFO interruption and automatic hardware flow control */
#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */
#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */
#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */
/* LCR register bit */
#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */
#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/
/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */
#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */
#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */
#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */
#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */
/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */
#define BIT_LCR_WORDSZ1 0x02 /* Set the word length length */
#define BIT_LCR_WORDSZ0 0x01
/* MCR register bit */
#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */
#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */
#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */
#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */
#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */
#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */
/* LSR register bit */
#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */
#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */
#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/
#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/
#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */
#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */
#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */
#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */
/* MSR register bit */
#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */
#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */
#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */
#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */
#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */
#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */
#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */
#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */
/* Interrupt status code */
#define INT_NOINT 0x01 /* There is no interruption */
#define INT_THR_EMPTY 0x02 /* THR empty interruption */
#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */
#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */
#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */
#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */
#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */
#define Fpclk 1843200 /* Define the internal clock frequency */
#define CH438_D0_PIN IMXRT_GET_PIN(1, 25)
#define CH438_D1_PIN IMXRT_GET_PIN(1, 24)
#define CH438_D2_PIN IMXRT_GET_PIN(1, 20)
#define CH438_D3_PIN IMXRT_GET_PIN(1, 21)
#define CH438_D4_PIN IMXRT_GET_PIN(1, 31)
#define CH438_D5_PIN IMXRT_GET_PIN(1, 28)
#define CH438_D6_PIN IMXRT_GET_PIN(1, 30)
#define CH438_D7_PIN IMXRT_GET_PIN(1, 29)
#define CH438_NWR_PIN IMXRT_GET_PIN(3, 4)
#define CH438_NRD_PIN IMXRT_GET_PIN(3, 5)
#define CH438_ALE_PIN IMXRT_GET_PIN(3, 2)
#define CH438_INT_PIN IMXRT_GET_PIN(3, 3)
// #define DIR_485CH1_PIN
// #define DIR_485CH2_PIN
void CH438RegTest(unsigned char num);
int Imxrt1052HwCh438Init(void);
#endif

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SRC_FILES := fsl_flexspi_nor_boot.c fsl_flexspi_nor_flash.c
include $(KERNEL_ROOT)/compiler.mk

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/*
* Copyright 2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file fsl_flexspi_nor_boot.h
* @brief support to register flexspi image vector table
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-03-22
*/
#ifndef _QUADSPI_BOOT_H_
#define _QUADSPI_BOOT_H_
#include <stdint.h>
/*************************************
* IVT Data
*************************************/
typedef struct _ivt_ {
/** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields
* (see @ref data)
*/
uint32_t hdr;
/** Absolute address of the first instruction to execute from the
* image
*/
uint32_t entry;
/** Reserved in this version of HAB: should be NULL. */
uint32_t reserved1;
/** Absolute address of the image DCD: may be NULL. */
uint32_t dcd;
/** Absolute address of the Boot Data: may be NULL, but not interpreted
* any further by HAB
*/
uint32_t boot_data;
/** Absolute address of the IVT.*/
uint32_t self;
/** Absolute address of the image CSF.*/
uint32_t csf;
/** Reserved in this version of HAB: should be zero. */
uint32_t reserved2;
} ivt;
#define IVT_MAJOR_VERSION 0x4
#define IVT_MAJOR_VERSION_SHIFT 0x4
#define IVT_MAJOR_VERSION_MASK 0xF
#define IVT_MINOR_VERSION 0x1
#define IVT_MINOR_VERSION_SHIFT 0x0
#define IVT_MINOR_VERSION_MASK 0xF
#define IVT_VERSION(major, minor) \
((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \
(((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT))
#define IVT_TAG_HEADER (0xD1) /**< Image Vector Table */
#define IVT_SIZE 0x2000
#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION)
#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24))
#define IVT_RSVD (uint32_t)(0x00000000)
/*************************************
* Boot Data
*************************************/
typedef struct _boot_data_ {
uint32_t start; /* boot start location */
uint32_t size; /* size */
uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */
uint32_t placeholder; /* placehoder to make even 0x10 size */
}BOOT_DATA_T;
/*************************************
* DCD Data
*************************************/
#define DCD_TAG_HEADER (0xD2)
#define DCD_TAG_HEADER_SHIFT (24)
#define DCD_VERSION (0x40)
#define DCD_ARRAY_SIZE 1
#define FLASH_BASE 0x60000000
#define FLASH_END 0x7F7FFFFF
#define SCLK 1
#define DCD_ADDRESS dcd_sdram
#define BOOT_DATA_ADDRESS &boot_data
#define CSF_ADDRESS 0
#define PLUGIN_FLAG (uint32_t)0
/* External Variables */
//extern const uint8_t dcd_sdram[1044];
extern const uint8_t dcd_sdram[1072];
extern const BOOT_DATA_T boot_data;
#endif

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/*
* Copyright 2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file fsl_flexspi_nor_flash.c
* @brief support to define flexspi flash config
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-03-22
*/
#include "fsl_flexspi_nor_flash.h"
/*******************************************************************************
* Code
******************************************************************************/
#if defined(__CC_ARM) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf")))
#elif defined(__ICCARM__)
#pragma location=".boot_hdr.conf"
#endif
const flexspi_nor_config_t Qspiflash_config =
{
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally,
.csHoldTime = 3u,
.csSetupTime = 3u,
.deviceModeCfgEnable = true,
.deviceModeType = 1,//Quad Enable command
.deviceModeSeq.seqNum = 1,
.deviceModeSeq.seqId = 4,
.deviceModeArg = 0x000200,//Set QE
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_60MHz,//80MHz for Winbond, 100MHz for GD, 133MHz for ISSI
.sflashA1Size = 16u * 1024u * 1024u,//4MBytes
.dataValidTime = {16u, 16u},
.lookupTable =
{
// //Fast Read Sequence
// [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B, RADDR_SDR, FLEXSPI_1PAD, 0x18),
// [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 0x08, READ_SDR, FLEXSPI_1PAD, 0x08),
// [2] = FLEXSPI_LUT_SEQ(JMP_ON_CS, 0, 0, 0, 0, 0),
//Quad Input/output read sequence
[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
[2] = FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0),
//Read Status
[1*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
//Write Enable
[3*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, 0, 0),
//Write status
[4*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x2),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
};

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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
*
* Redistribution and use in source and binary forms, with or without
* modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this
* list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice,
* this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file fsl_flexspi_nor_flash.h
* @brief support to define flexspi flash config
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-03-22
*/
#ifndef __FLEXSPI_NOR_FLASH_H__
#define __FLEXSPI_NOR_FLASH_H__
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/* FLEXSPI memory config block related defintions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)
/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
/* Lookup table related defintions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq
{
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_133MHz = 7,
kFlexSpiSerialClk_166MHz = 8,
kFlexSpiSerialClk_200MHz = 9,
} flexspi_serial_clk_freq_t;
//!@brief FlexSPI clock configuration type
enum
{
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};
//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource
{
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;
//!@brief Misc feature bit definitions
enum
{
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};
//!@brief Flash Type Definition
enum
{
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};
//!@brief Flash Pad Definitions
enum
{
kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
};
//!@brief FlexSPI LUT Sequence structure
typedef struct _lut_sequence
{
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
uint8_t seqId; //!< Sequence Index, valid number: 0-15
uint16_t reserved;
} flexspi_lut_seq_t;
//!@brief Flash Configuration Command Type
enum
{
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
kDeviceConfigCmdType_Reset, //!< Reset device command
};
//!@brief FlexSPI Memory Configuration Block
typedef struct _FlexSPIConfig
{
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
//! Serial NAND, need to refer to datasheet
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
//! Generic configuration, etc.
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
//! DPI/QPI/OPI switch or reset command
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
//! sequence number, [31:16] Reserved
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
flexspi_lut_seq_t
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
//! details
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
//! Chapter for more details
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
//! busy flag is 0 when flash device is busy
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
} flexspi_mem_config_t;
/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
/*
* Serial NOR configuration block
*/
typedef struct _flexspi_nor_config
{
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
uint32_t pageSize; //!< Page size of Serial NOR
uint32_t sectorSize; //!< Sector size of Serial NOR
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
uint8_t reserved0[2]; //!< Reserved for future use
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
uint32_t blockSize; //!< Block size
uint32_t reserve2[11]; //!< Reserved for future use
} flexspi_nor_config_t;
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif // __FLEXSPI_NOR_FLASH_H__

24
Ubiquitous/XiZi/kernel/thread/msgqueue.c
View File

@ -38,13 +38,13 @@ static struct MsgQueue *GetMsgQueueById(int32 id)
if (id < 0 )
return NONE;
lock = CriticalAreaLock();
idnode = IdGetObj(&k_mq_id_manager, id);
if (idnode == NONE){
CriticalAreaUnLock(lock);
return NONE;
}
}
mq = CONTAINER_OF(idnode, struct MsgQueue, id);
CriticalAreaUnLock(lock);
return mq;
@ -61,7 +61,7 @@ static x_err_t _InitMsgQueue( struct MsgQueue *mq ,x_size_t msg_size,
mq->num_msgs = 0;
mq->each_len = ALIGN_MEN_UP(msg_size, MEM_ALIGN_SIZE);
mq->index = 0;
InitDoubleLinkList(&mq->send_pend_list);
InitDoubleLinkList(&(mq->recv_pend_list));
@ -102,9 +102,9 @@ static x_err_t _MsgQueueSend(struct MsgQueue *mq,
CriticalAreaUnLock(lock);
return -EFULL;
}
while(mq->num_msgs >= mq->max_msgs ) {
task->exstatus = EOK;
if (timeout == 0) {
CriticalAreaUnLock(lock);
@ -171,7 +171,7 @@ static x_err_t _MsgQueueUrgentSend(struct MsgQueue *mq, const void *buffer, x_si
mq->index --;
if (mq->index < 0)
mq->index += mq->max_msgs;
msg = mq->msg_buf + ( ( mq->index + mq->num_msgs ) % mq->max_msgs ) * mq->each_len ;
memcpy(msg , buffer, size);
mq->num_msgs ++;
@ -382,7 +382,7 @@ x_err_t KMsgQueueReinit(int32 id)
* @param buffer message info
* @param size the size of buffer
* @param timeout time needed waiting
*
*
* @return EOK on success;EINVALED on failure
*
*/
@ -407,7 +407,7 @@ x_err_t KMsgQueueRecv(int32 id,
* a dynamic messagequeue will be deleted from the manage list
*
* @param id the message id
*
*
* @return EOK on success;EINVALED on failure
*
*/
@ -430,7 +430,7 @@ x_err_t KDeleteMsgQueue(int32 id)
* @param id the message id
* @param buffer message info
* @param size the size of buffer
*
*
* @return EOK on success;EINVALED on failure
*
*/
@ -454,7 +454,7 @@ x_err_t KMsgQueueUrgentSend(int32 id, const void *buffer, x_size_t size)
* @param id the message id
* @param buffer message info
* @param size the size of buffer
*
*
* @return EOK on success;EINVALED on failure
*
*/
@ -478,7 +478,7 @@ x_err_t KMsgQueueSend(int32 id, const void *buffer, x_size_t size)
* @param buffer message info
* @param size the size of buffer
* @param timeout waiting time
*
*
* @return EOK on success;EINVALED on failure
*
*/
@ -494,4 +494,4 @@ x_err_t KMsgQueueSendwait(int32 id, const void *buffer, x_size_t size,int32 tim
return mq->Done->send(mq,buffer,size,timeout);
else
return -EINVALED;
}
}

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