forked from xuos/xiuos
feat add ch438 register clear when receiving interrrupts
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909f3cc635
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3c9347b856
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@ -1027,15 +1027,15 @@ static uint32 ImxrtCh438ReadData(void *dev, struct BusBlockReadParam *read_param
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if (EOK == result) {
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gInterruptStatus = ReadCH438Data(REG_SSR_ADDR);
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if (!gInterruptStatus) {
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// dat = ReadCH438Data(REG_LCR0_ADDR);
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// dat = ReadCH438Data(REG_IER0_ADDR);
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// dat = ReadCH438Data(REG_MCR0_ADDR);
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// dat = ReadCH438Data(REG_LSR0_ADDR);
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// dat = ReadCH438Data(REG_MSR0_ADDR);
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// dat = ReadCH438Data(REG_RBR0_ADDR);
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// dat = ReadCH438Data(REG_THR0_ADDR);
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// dat = ReadCH438Data(REG_IIR0_ADDR);
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// dat = dat;
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dat = ReadCH438Data(REG_LCR0_ADDR);
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dat = ReadCH438Data(REG_IER0_ADDR);
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dat = ReadCH438Data(REG_MCR0_ADDR);
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dat = ReadCH438Data(REG_LSR0_ADDR);
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dat = ReadCH438Data(REG_MSR0_ADDR);
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dat = ReadCH438Data(REG_RBR0_ADDR);
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dat = ReadCH438Data(REG_THR0_ADDR);
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dat = ReadCH438Data(REG_IIR0_ADDR);
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dat = dat;
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interrupt_done = 0;
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} else {
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if (gInterruptStatus & interrupt_num[dev_param->ext_uart_no]) { /* check which uart port triggers interrupt*/
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@ -1053,17 +1053,26 @@ static uint32 ImxrtCh438ReadData(void *dev, struct BusBlockReadParam *read_param
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InterruptStatus = ReadCH438Data( REG_IIR_ADDR ) & 0x0f; /* read the status of the uart port*/
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if ((INT_RCV_OVERTIME == InterruptStatus) || (INT_RCV_SUCCESS == InterruptStatus)) {
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switch( InterruptStatus )
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{
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case INT_NOINT: /* NO INTERRUPT */
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break;
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case INT_THR_EMPTY: /* THR EMPTY INTERRUPT */
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break;
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case INT_RCV_OVERTIME: /* RECV OVERTIME INTERRUPT */
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case INT_RCV_SUCCESS: /* RECV INTERRUPT SUCCESSFULLY */
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rcv_num = Ch438UartRcv(dev_param->ext_uart_no, (uint8 *)read_param->buffer, read_param->size);
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read_param->read_length = rcv_num;
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interrupt_done = 1;
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// int i;
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// uint8 *buffer = (uint8 *)read_param->buffer;
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// for (i = 0; i < rcv_num; i ++) {
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// KPrintf("Ch438UartRcv i %u data 0x%x\n", i, buffer[i]);
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// }
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break;
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case INT_RCV_LINES: /* RECV LINES INTERRUPT */
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ReadCH438Data( REG_LSR_ADDR );
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break;
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case INT_MODEM_CHANGE: /* MODEM CHANGE INTERRUPT */
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ReadCH438Data( REG_MSR_ADDR );
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break;
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default:
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break;
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}
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}
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}
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