+
+#include "xparameters.h"
+#include "xscutimer.h"
+
+#include "clock_common_op.h"
+#include "log.h"
+
+XScuTimer global_timer;
+#define TIMER_LOAD_VALUE 0x514C7
+
+static void _sys_clock_init()
+{
+ XScuTimer_Config* timer_cfg = XScuTimer_LookupConfig(XPAR_PS7_SCUTIMER_0_DEVICE_ID);
+ if (XScuTimer_CfgInitialize(&global_timer, timer_cfg, timer_cfg->BaseAddr) != XST_SUCCESS || XScuTimer_SelfTest(&global_timer) != XST_SUCCESS) {
+ ERROR("Error initializing timer\n");
+ return;
+ }
+ XScuTimer_EnableInterrupt(&global_timer);
+ XScuTimer_EnableAutoReload(&global_timer);
+ XScuTimer_LoadTimer(&global_timer, TIMER_LOAD_VALUE);
+ XScuTimer_Start(&global_timer);
+}
+
+static uint32_t _get_clock_int()
+{
+ return XPAR_PS7_SCUTIMER_0_INTR;
+}
+
+static uint64_t _get_tick()
+{
+ return 0;
+}
+
+static uint64_t _get_second()
+{
+ return 0;
+}
+
+static bool _is_timer_expired()
+{
+ return XScuTimer_IsExpired(&global_timer);
+}
+
+static void _clear_clock_intr()
+{
+ XScuTimer_ClearInterruptStatus(&global_timer);
+}
+
+static struct XiziClockDriver hardkernel_clock_driver = {
+ .sys_clock_init = _sys_clock_init,
+ .get_clock_int = _get_clock_int,
+ .get_tick = _get_tick,
+ .get_second = _get_second,
+ .is_timer_expired = _is_timer_expired,
+ .clear_clock_intr = _clear_clock_intr,
+};
+
+struct XiziClockDriver* hardkernel_clock_init(struct TraceTag* hardkernel_tag)
+{
+ hardkernel_clock_driver.sys_clock_init();
+ return &hardkernel_clock_driver;
+}
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/include/xscutimer.h b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/include/xscutimer.h
new file mode 100755
index 000000000..5a35f6210
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/include/xscutimer.h
@@ -0,0 +1,366 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.h
+* @addtogroup scutimer_v2_1
+* @{
+* @details
+*
+* The timer driver supports the Cortex A9 private timer.
+*
+* The timer driver supports the following features:
+* - Normal mode and Auto reload mode
+* - Interrupts (Interrupt handler is not provided in this driver. Application
+* has to register it's own handler)
+*
+* Initialization and Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Timer.
+*
+* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
+* user needs to first call the XScuTimer_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuTimer_CfgInitialize() API.
+*
+* Interrupts
+*
+* The Timer hardware supports interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+* Virtual Memory
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XScuTimer driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*
+* NOTE:
+* The timer is not a part of the snoop control unit as indicated by the
+* prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+#ifndef XSCUTIMER_H /* prevent circular inclusions */
+#define XSCUTIMER_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscutimer_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+ u16 DeviceId; /**< Unique ID of device */
+ u32 BaseAddr; /**< Base address of the device */
+} XScuTimer_Config;
+
+/**
+ * The XScuTimer driver instance data. The user is required to allocate a
+ * variable of this type for every timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+ XScuTimer_Config Config; /**< Hardware Configuration */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 IsStarted; /**< Device timer is running */
+} XScuTimer;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Check if the timer has expired.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+* - TRUE if the timer has expired.
+* - FALSE if the timer has not expired.
+*
+* @note C-style signature:
+* int XScuTimer_IsExpired(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_IsExpired(InstancePtr) \
+ ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET) & \
+ XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
+ XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the timer. This macro will read the timer load register
+* and writes the same value to load register to update the counter register.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_RestartTimer(InstancePtr) \
+ XScuTimer_LoadTimer((InstancePtr), \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_LOAD_OFFSET))
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_LoadTimer(InstancePtr, Value) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value. It can be called at any
+* time.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterValue(InstancePtr) \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableAutoReload(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) | \
+ XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable auto-reload mode.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableAutoReload(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) & \
+ ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Enable the Timer interrupt.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableInterrupt(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) | \
+ XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable the Timer interrupt.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableInterrupt(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET, \
+ (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_CONTROL_OFFSET) & \
+ ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetInterruptStatus(InstancePtr) \
+ XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_ClearInterruptStatus(InstancePtr) \
+ XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
+ XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscutimer_sinit.c
+ */
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscutimer_selftest.c
+ */
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
+
+/*
+ * Interface functions in xscutimer.c
+ */
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+ XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
+void XScuTimer_Start(XScuTimer *InstancePtr);
+void XScuTimer_Stop(XScuTimer *InstancePtr);
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/include/xscutimer_hw.h b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/include/xscutimer_hw.h
new file mode 100755
index 000000000..ac7b42934
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/include/xscutimer_hw.h
@@ -0,0 +1,287 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_hw.h
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains the hardware interface to the Timer.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
+* and interrupt registers
+* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+* when the xstatus.h in the common driver overwrites
+* the xstatus.h of the standalone BSP during the
+* libgen.
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
+#define XSCUTIMER_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
+#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
+#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
+#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
+ Status Register */
+/* @} */
+
+/** @name Timer Control register
+ * This register bits control the prescaler, Intr enable,
+ * auto-reload and timer enable.
+ * @{
+ */
+
+#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
+#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
+#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
+#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
+#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Timer counter register has reached zero.
+ * @{
+ */
+
+#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetLoadReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer load register.
+*
+* @note C-style signature:
+* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetLoadReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the counter register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetCounterReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetCounterReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the load register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetControlReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer load register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetControlReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetControlReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param BaseAddr is the base address of the scu timer.
+* @param Value is the count to be loaded in to the counter register.
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetIntrReg(BaseAddr, Value) \
+ XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param BaseAddr is the base address of the scu timer.
+*
+* @return Contents of the timer counter register.
+*
+* @note C-style signature:
+ u32 XScuTimer_GetIntrReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetIntrReg(BaseAddr) \
+ XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Read from the given Timer register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be read
+*
+* @return The 32-bit value of the register
+*
+* @note C-style signature:
+* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
+ Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given Timer register.
+*
+* @param BaseAddr is the base address of the device
+* @param RegOffset is the register offset to be written
+* @param Data is the 32-bit value to write to the register
+*
+* @return None.
+*
+* @note C-style signature:
+* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
+ Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/include/xtime_l.h b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/include/xtime_l.h
new file mode 100644
index 000000000..e5f43b846
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/include/xtime_l.h
@@ -0,0 +1,89 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.h
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd 05/15/12 Upadted get/set time functions to make use Global Timer
+* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer
+*
+*
+* @note None.
+*
+******************************************************************************/
+
+#ifndef XTIME_H /* prevent circular inclusions */
+#define XTIME_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xparameters.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+typedef u64 XTime;
+
+/************************** Constant Definitions *****************************/
+#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR
+#define GTIMER_COUNTER_LOWER_OFFSET 0x00U
+#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
+#define GTIMER_CONTROL_OFFSET 0x08U
+
+
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XTime_SetTime(XTime Xtime_Global);
+void XTime_GetTime(XTime *Xtime_Global);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XTIME_H */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/xscutimer.c b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/xscutimer.c
new file mode 100755
index 000000000..9d477d971
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/xscutimer.c
@@ -0,0 +1,286 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* Contains the implementation of interface functions of the SCU Timer driver.
+* See xscutimer.h for a description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize a specific timer instance/driver. This function must be called
+* before other functions of the driver are called.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+* @param ConfigPtr points to the XScuTimer configuration structure.
+* @param EffectiveAddress is the base address for the device. It could be
+* a virtual address if address translation is supported in the
+* system, otherwise it is the physical address.
+*
+* @return
+* - XST_SUCCESS if initialization was successful.
+* - XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+ XScuTimer_Config *ConfigPtr, u32 EffectiveAddress)
+{
+ s32 Status;
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ /*
+ * If the device is started, disallow the initialize and return a
+ * status indicating it is started. This allows the user to stop the
+ * device and reinitialize, but prevents a user from inadvertently
+ * initializing.
+ */
+ if (InstancePtr->IsStarted != XIL_COMPONENT_IS_STARTED) {
+ /*
+ * Copy configuration into the instance structure.
+ */
+ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+ /*
+ * Save the base address pointer such that the registers of the block
+ * can be accessed and indicate it has not been started yet.
+ */
+ InstancePtr->Config.BaseAddr = EffectiveAddress;
+
+ InstancePtr->IsStarted = (u32)0;
+
+ /*
+ * Indicate the instance is ready to use, successfully initialized.
+ */
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ Status =(s32)XST_SUCCESS;
+ }
+ else {
+ Status = (s32)XST_DEVICE_IS_STARTED;
+ }
+ return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Start the timer.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XScuTimer_Start(XScuTimer *InstancePtr)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the contents of the Control register.
+ */
+ Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+
+ /*
+ * Set the 'timer enable' bit in the register.
+ */
+ Register |= XSCUTIMER_CONTROL_ENABLE_MASK;
+
+ /*
+ * Update the Control register with the new value.
+ */
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, Register);
+
+ /*
+ * Indicate that the device is started.
+ */
+ InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+}
+
+/****************************************************************************/
+/**
+*
+* Stop the timer.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+void XScuTimer_Stop(XScuTimer *InstancePtr)
+{
+ u32 Register;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the contents of the Control register.
+ */
+ Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+
+ /*
+ * Clear the 'timer enable' bit in the register.
+ */
+ Register &= (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
+
+ /*
+ * Update the Control register with the new value.
+ */
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, Register);
+
+ /*
+ * Indicate that the device is stopped.
+ */
+ InstancePtr->IsStarted = (u32)0;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the prescaler bits in the timer control register.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+* @param PrescalerValue is a 8 bit value that sets the prescaler to use.
+*
+* @return None
+*
+* @note None
+*
+****************************************************************************/
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue)
+{
+ u32 ControlReg;
+
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ /*
+ * Read the Timer control register.
+ */
+ ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+
+ /*
+ * Clear all of the prescaler control bits in the register.
+ */
+ ControlReg &= (u32)(~XSCUTIMER_CONTROL_PRESCALER_MASK);
+
+ /*
+ * Set the prescaler value.
+ */
+ ControlReg |= (((u32)PrescalerValue) << XSCUTIMER_CONTROL_PRESCALER_SHIFT);
+
+ /*
+ * Write the register with the new values.
+ */
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, ControlReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current prescaler value.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return The prescaler value.
+*
+* @note None.
+*
+****************************************************************************/
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr)
+{
+ u32 ControlReg;
+
+ /*
+ * Assert to validate input arguments.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Read the Timer control register.
+ */
+ ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+ ControlReg &= XSCUTIMER_CONTROL_PRESCALER_MASK;
+
+ return (u8)(ControlReg >> XSCUTIMER_CONTROL_PRESCALER_SHIFT);
+}
+/** @} */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/xscutimer_g.c b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/xscutimer_g.c
new file mode 100755
index 000000000..e3b07b591
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/xscutimer_g.c
@@ -0,0 +1,52 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2024 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscutimer.h"
+
+#include "mmio_access.h"
+
+/*
+ * The configuration table for devices
+ */
+
+XScuTimer_Config XScuTimer_ConfigTable[] = {
+ { XPAR_PS7_SCUTIMER_0_DEVICE_ID,
+ MMIO_P2V_WO(XPAR_PS7_SCUTIMER_0_BASEADDR) }
+};
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/xscutimer_selftest.c b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/xscutimer_selftest.c
new file mode 100755
index 000000000..6e37fef3b
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/xscutimer_selftest.c
@@ -0,0 +1,139 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_selftest.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* Contains diagnostic self-test functions for the XScuTimer driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XSCUTIMER_SELFTEST_VALUE 0xA55AF00FU
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the timer. This test clears the timer enable bit in
+* the control register, writes to the timer load register and verifies the
+* value read back matches the value written and restores the control register
+* and the timer load register.
+*
+* @param InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+* - XST_SUCCESS if self-test was successful.
+* - XST_FAILURE if self test was not successful.
+*
+* @note None.
+*
+******************************************************************************/
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr)
+{
+ u32 Register;
+ u32 CtrlOrig;
+ u32 LoadOrig;
+ s32 Status;
+
+ /*
+ * Assert to ensure the inputs are valid and the instance has been
+ * initialized.
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * Save the contents of the Control Register and stop the timer.
+ */
+ CtrlOrig = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET);
+ Register = CtrlOrig & (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, Register);
+
+ /*
+ * Save the contents of the Load Register.
+ * Load a new test value in the Load Register, read it back and
+ * compare it with the written value.
+ */
+ LoadOrig = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
+ XSCUTIMER_LOAD_OFFSET);
+ XScuTimer_LoadTimer(InstancePtr, XSCUTIMER_SELFTEST_VALUE);
+ Register = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
+ XSCUTIMER_LOAD_OFFSET);
+
+ /*
+ * Restore the contents of the Load Register and Control Register.
+ */
+ XScuTimer_LoadTimer(InstancePtr, LoadOrig);
+ XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+ XSCUTIMER_CONTROL_OFFSET, CtrlOrig);
+
+ /*
+ * Return a Failure if the contents of the Load Register do not
+ * match with the value written to it.
+ */
+ if (Register != XSCUTIMER_SELFTEST_VALUE) {
+ Status = (s32)XST_FAILURE;
+ }
+ else {
+ Status = (s32)XST_SUCCESS;
+ }
+
+ return Status;
+}
+/** @} */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/xscutimer_sinit.c b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/xscutimer_sinit.c
new file mode 100755
index 000000000..3bcc57ebd
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/xscutimer_sinit.c
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscutimer_sinit.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm 03/10/10 First release
+* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions ****************************/
+extern XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return A pointer to the configuration table entry corresponding to the
+* given device ID, or NULL if no match is found.
+*
+* @note None.
+*
+******************************************************************************/
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId)
+{
+ XScuTimer_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < XPAR_XSCUTIMER_NUM_INSTANCES; Index++) {
+ if (XScuTimer_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XScuTimer_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XScuTimer_Config *)CfgPtr;
+}
+/** @} */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/xtime_l.c b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/xtime_l.c
new file mode 100644
index 000000000..28f5dcd14
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/zynq7000-zc702/xtime_l.c
@@ -0,0 +1,117 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ * @file xtime_l.c
+ *
+ * This file contains low level functions to get/set time from the Global Timer
+ * register in the ARM Cortex A9 MP core.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ------ -------- ---------------------------------------------------
+ * 1.00a rp/sdm 11/03/09 Initial release.
+ * 3.07a sgd 07/05/12 Upadted get/set time functions to make use Global Timer
+ *
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xtime_l.h"
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/****************************************************************************
+ *
+ * Set the time in the Global Timer Counter Register.
+ *
+ * @param Value to be written to the Global Timer Counter Register.
+ *
+ * @return None.
+ *
+ * @note In multiprocessor environment reference time will reset/lost for
+ * all processors, when this function called by any one processor.
+ *
+ ****************************************************************************/
+void XTime_SetTime(XTime Xtime_Global)
+{
+ /* Disable Global Timer */
+ Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0);
+
+ /* Updating Global Timer Counter Register */
+ Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global);
+ Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET,
+ (u32)((u32)(Xtime_Global >> 32U)));
+
+ /* Enable Global Timer */
+ Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1);
+}
+
+/****************************************************************************
+ *
+ * Get the time from the Global Timer Counter Register.
+ *
+ * @param Pointer to the location to be updated with the time.
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ ****************************************************************************/
+void XTime_GetTime(XTime* Xtime_Global)
+{
+ u32 low;
+ u32 high;
+
+ /* Reading Global Timer Counter Register */
+ do {
+ high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET);
+ low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET);
+ } while (Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high);
+
+ *Xtime_Global = (((XTime)high) << 32U) | (XTime)low;
+}
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/clock_common_op.h b/Ubiquitous/XiZi_AIoT/hardkernel/clock/clock_common_op.h
index 5f7c79a14..cab615eb1 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/clock/clock_common_op.h
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/clock_common_op.h
@@ -35,6 +35,7 @@ Modification:
struct XiziClockDriver {
void (*sys_clock_init)();
uint32_t (*get_clock_int)();
+ bool (*is_timer_expired)();
void (*clear_clock_intr)();
uint64_t (*get_tick)();
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/Makefile
index 7975056fd..8ea2c7e2f 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/Makefile
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/Makefile
@@ -1,4 +1,16 @@
+
+SRC_FILES := vector.S trampoline.S $(BOARD)/trap_common.c error_debug.c spinlock.c hard_spinlock.S
+
+ifeq ($(BOARD), imx6q-sabrelite)
SRC_DIR := gicv2
-SRC_FILES := vector.S trampoline.S trap_common.c error_debug.c spinlock.c hard_spinlock.S
+endif
+
+ifeq ($(BOARD), zynq7000-zc702)
+# SRC_DIR := gicv2
+SRC_DIR := gicv3
+SRC_FILES += $(BOARD)/xil_assert.c
+# SRC_FILES := vector.S trampoline.S imx6q-sabrelite/trap_common.c error_debug.c spinlock.c hard_spinlock.S
+endif
+
include $(KERNEL_ROOT)/compiler.mk
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/error_debug.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/error_debug.c
index a9fccbe4f..9d7224da8 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/error_debug.c
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/error_debug.c
@@ -91,6 +91,7 @@ void handle_undefined_instruction(struct trapframe* tf)
panic("");
}
+extern void context_switch(struct context**, struct context*);
void dabort_handler(struct trapframe* r)
{
uint32_t dfs, dfa;
@@ -100,15 +101,16 @@ void dabort_handler(struct trapframe* r)
if (r->pc < KERN_MEM_BASE) { // Exception occured in User space: exit
ERROR("dabort in user space: %s\n", cur_cpu()->task->name);
- LOG("program counter: 0x%x(%s) caused\n", r->pc, cur_cpu()->task);
+ LOG("program counter: 0x%x caused\n", r->pc);
LOG("data abort at 0x%x, status 0x%x\n", dfa, dfs);
_abort_reason(dfs);
dump_tf(r);
}
if (cur_cpu()->task != NULL) {
sys_exit();
+ context_switch(&cur_cpu()->task->main_thread.context, cur_cpu()->scheduler);
} else { // Exception occured in Kernel space: panic
- LOG("program counter: 0x%x(%s) caused\n", r->pc, cur_cpu()->task);
+ LOG("program counter: 0x%x caused\n", r->pc);
LOG("data abort at 0x%x, status 0x%x\n", dfa, dfs);
_abort_reason(dfs);
dump_tf(r);
@@ -132,6 +134,7 @@ void iabort_handler(struct trapframe* r)
}
if (cur_cpu()->task != NULL) {
sys_exit();
+ context_switch(&cur_cpu()->task->main_thread.context, cur_cpu()->scheduler);
} else { // Exception occured in Kernel space: panic
LOG("program counter: 0x%x(%s) caused\n", r->pc, cur_cpu()->task);
LOG("prefetch abort at 0x%x, status 0x%x\n", ifa, ifs);
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/Makefile
new file mode 100644
index 000000000..20fd6a277
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/Makefile
@@ -0,0 +1,7 @@
+SRC_FILES := xscugic_g.c \
+ xscugic_hw.c \
+ xscugic_intr.c \
+ xscugic_sinit.c \
+ xscugic.c
+
+include $(KERNEL_ROOT)/compiler.mk
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xil_exception.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xil_exception.h
new file mode 100755
index 000000000..1606c1f8d
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xil_exception.h
@@ -0,0 +1,234 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex A9 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm 11/04/09 First release
+*
+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST 0U
+#define XIL_EXCEPTION_ID_RESET 0U
+#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
+#define XIL_EXCEPTION_ID_SWI_INT 2U
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
+#define XIL_EXCEPTION_ID_IRQ_INT 5U
+#define XIL_EXCEPTION_ID_FIQ_INT 6U
+#define XIL_EXCEPTION_ID_LAST 6U
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Enable Exceptions.
+*
+* @param Mask for exceptions to be enabled.
+*
+* @return None.
+*
+* @note If bit is 0, exception is enabled.
+* C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*
+******************************************************************************/
+#ifdef __GNUC__
+#define Xil_ExceptionEnableMask(Mask) \
+ mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+#elif defined (__ICCARM__)
+#define Xil_ExceptionEnableMask(Mask) \
+ mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionEnableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
+ }
+#endif
+
+/****************************************************************************/
+/**
+* Enable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_ExceptionEnable() \
+ Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* Disable Exceptions.
+*
+* @param Mask for exceptions to be enabled.
+*
+* @return None.
+*
+* @note If bit is 1, exception is disabled.
+* C-Style signature: Xil_ExceptionDisableMask(Mask)
+*
+******************************************************************************/
+#ifdef __GNUC__
+#define Xil_ExceptionDisableMask(Mask) \
+ mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
+#elif defined (__ICCARM__)
+#define Xil_ExceptionDisableMask(Mask) \
+ mtcpsr(mfcpsr() | (Mask & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionDisableMask(Mask) \
+ { \
+ register u32 Reg __asm("cpsr"); \
+ mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
+ }
+#endif
+
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return None.
+*
+* @note None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+ Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* Enable nested interrupts by clearing the I and F bits it CPSR
+*
+* @return None.
+*
+* @note This macro is supposed to be used from interrupt handlers. In the
+* interrupt handler the interrupts are disabled by default (I and F
+* are 1). To allow nesting of interrupts, this macro should be
+* used. It clears the I and F bits by changing the ARM mode to
+* system mode. Once these bits are cleared and provided the
+* preemption of interrupt conditions are met in the GIC, nesting of
+* interrupts will start happening.
+* Caution: This macro must be used with caution. Before calling this
+* macro, the user must ensure that the source of the current IRQ
+* is appropriately cleared. Otherwise, as soon as we clear the I and
+* F bits, there can be an infinite loop of interrupts with an
+* eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+ __asm__ __volatile__ ("mrs lr, spsr"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
+ __asm__ __volatile__ ("stmfd sp!, {lr}");
+
+/****************************************************************************/
+/**
+* Disable the nested interrupts by setting the I and F bits.
+*
+* @return None.
+*
+* @note This macro is meant to be called in the interrupt service routines.
+* This macro cannot be used independently. It can only be used when
+* nesting of interrupts have been enabled by using the macro
+* Xil_EnableNestedInterrupts(). In a typical flow, the user first
+* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+* point. The user then must call this macro before exiting the interrupt
+* service routine. This macro puts the ARM back in IRQ/FIQ mode and
+* hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
+ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
+ __asm__ __volatile__ ("msr spsr_cxsf, lr");
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+ Xil_ExceptionHandler Handler,
+ void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+
+extern void Xil_ExceptionInit(void);
+extern void Xil_DataAbortHandler(void *CallBackRef);
+extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic.c
new file mode 100755
index 000000000..b87c31830
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic.c
@@ -0,0 +1,731 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xscugic.c
+ * @addtogroup scugic_v3_1
+ * @{
+ *
+ * Contains required functions for the XScuGic driver for the Interrupt
+ * Controller. See xscugic.h for a detailed description of the driver.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a drg 01/19/10 First release
+ * 1.01a sdm 11/09/11 Changes are made in function XScuGic_CfgInitialize. Since
+ * "Config" entry is now made as pointer in the XScuGic
+ * structure, necessary changes are made.
+ * The HandlerTable can now be populated through the low
+ * level routine XScuGic_RegisterHandler added in this
+ * release. Hence necessary checks are added not to
+ * overwrite the HandlerTable entriesin function
+ * XScuGic_CfgInitialize.
+ * 1.03a srt 02/27/13 Added APIs
+ * - XScuGic_SetPriTrigTypeByDistAddr()
+ * - XScuGic_GetPriTrigTypeByDistAddr()
+ * Removed Offset calculation macros, defined in _hw.h
+ * (CR 702687)
+ * Added support to direct interrupts to the appropriate CPU. Earlier
+ * interrupts were directed to CPU1 (hard coded). Now depending
+ * upon the CPU selected by the user (xparameters.h), interrupts
+ * will be directed to the relevant CPU. This fixes CR 699688.
+ *
+ * 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+ * XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+ * Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+ * XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+ * This is fix for CR#705621.
+ * 1.06a asa 16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
+ * in function XScuGic_CfgInitialize is removed as it was
+ * a bug.
+ * 3.00 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
+ * 3.01 pkp 06/19/15 Added XScuGic_InterruptMaptoCpu API for an interrupt
+ * target CPU mapping
+ *
+ *
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xil_assert.h"
+#include "xil_types.h"
+#include "xparameters.h"
+
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void* CallBackRef);
+
+/*****************************************************************************/
+/**
+ *
+ * DistributorInit initializes the distributor of the GIC. The
+ * initialization entails:
+ *
+ * - Write the trigger mode, priority and target CPU
+ * - All interrupt sources are disabled
+ * - Enable the distributor
+ *
+ * @param InstancePtr is a pointer to the XScuGic instance.
+ * @param CpuID is the Cpu ID to be initialized.
+ *
+ * @return None
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+static void DistributorInit(XScuGic* InstancePtr, u32 CpuID)
+{
+ u32 Int_Id;
+ u32 LocalCpuID = CpuID;
+
+#if USE_AMP == 1
+#warning "Building GIC for AMP"
+
+ /*
+ * The distrubutor should not be initialized by FreeRTOS in the case of
+ * AMP -- it is assumed that Linux is the master of this device in that
+ * case.
+ */
+ return;
+#endif
+ Xil_AssertVoid(InstancePtr != NULL);
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
+
+ /*
+ * Set the security domains in the int_security registers for
+ * non-secure interrupts
+ * All are secure, so leave at the default. Set to 1 for non-secure
+ * interrupts.
+ */
+
+ /*
+ * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+ */
+
+ /*
+ * 1. The trigger mode in the int_config register
+ * Only write to the SPI interrupts, so start at 32
+ */
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id = Int_Id + 16U) {
+ /*
+ * Each INT_ID uses two bits, or 16 INT_ID per register
+ * Set them all to be level sensitive, active HIGH.
+ */
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+ 0U);
+ }
+
+#define DEFAULT_PRIORITY 0xa0a0a0a0U
+ for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id = Int_Id + 4U) {
+ /*
+ * 2. The priority using int the priority_level register
+ * The priority_level and spi_target registers use one byte per
+ * INT_ID.
+ * Write a default value that can be changed elsewhere.
+ */
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+ DEFAULT_PRIORITY);
+ }
+
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id = Int_Id + 4U) {
+ /*
+ * 3. The CPU interface in the spi_target register
+ * Only write to the SPI interrupts, so start at 32
+ */
+ LocalCpuID |= LocalCpuID << 8U;
+ LocalCpuID |= LocalCpuID << 16U;
+
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+ LocalCpuID);
+ }
+
+ for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id = Int_Id + 32U) {
+ /*
+ * 4. Enable the SPI using the enable_set register. Leave all
+ * disabled for now.
+ */
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, Int_Id),
+ 0xFFFFFFFFU);
+ }
+
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET,
+ XSCUGIC_EN_INT_MASK);
+}
+
+/*****************************************************************************/
+/**
+ *
+ * CPUInitialize initializes the CPU Interface of the GIC. The initialization entails:
+ *
+ * - Set the priority of the CPU
+ * - Enable the CPU interface
+ *
+ * @param InstancePtr is a pointer to the XScuGic instance.
+ *
+ * @return None
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+static void CPUInitialize(XScuGic* InstancePtr)
+{
+ /*
+ * Program the priority mask of the CPU using the Priority mask register
+ */
+ XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CPU_PRIOR_OFFSET, 0xF0U);
+
+ /*
+ * If the CPU operates in both security domains, set parameters in the
+ * control_s register.
+ * 1. Set FIQen=1 to use FIQ for secure interrupts,
+ * 2. Program the AckCtl bit
+ * 3. Program the SBPR bit to select the binary pointer behavior
+ * 4. Set EnableS = 1 to enable secure interrupts
+ * 5. Set EnbleNS = 1 to enable non secure interrupts
+ */
+
+ /*
+ * If the CPU operates only in the secure domain, setup the
+ * control_s register.
+ * 1. Set FIQen=1,
+ * 2. Set EnableS=1, to enable the CPU interface to signal secure interrupts.
+ * Only enable the IRQ output unless secure interrupts are needed.
+ */
+ XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_CONTROL_OFFSET, 0x07U);
+}
+
+/*****************************************************************************/
+/**
+ *
+ * CfgInitialize a specific interrupt controller instance/driver. The
+ * initialization entails:
+ *
+ * - Initialize fields of the XScuGic structure
+ * - Initial vector table with stub function calls
+ * - All interrupt sources are disabled
+ *
+ * @param InstancePtr is a pointer to the XScuGic instance.
+ * @param ConfigPtr is a pointer to a config table for the particular
+ * device this driver is associated with.
+ * @param EffectiveAddr is the device base address in the virtual memory
+ * address space. The caller is responsible for keeping the address
+ * mapping from EffectiveAddr to the device physical base address
+ * unchanged once this function is invoked. Unexpected errors may
+ * occur if the address mapping changes after this function is
+ * called. If address translation is not used, use
+ * Config->BaseAddress for this parameters, passing the physical
+ * address instead.
+ *
+ * @return
+ * - XST_SUCCESS if initialization was successful
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+s32 XScuGic_CfgInitialize(XScuGic* InstancePtr,
+ XScuGic_Config* ConfigPtr,
+ u32 EffectiveAddr)
+{
+ u32 Int_Id;
+ u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1;
+ (void)EffectiveAddr;
+
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(ConfigPtr != NULL);
+
+ if (InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
+
+ InstancePtr->IsReady = 0;
+ InstancePtr->Config = ConfigPtr;
+
+ for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id++) {
+ /*
+ * Initalize the handler to point to a stub to handle an
+ * interrupt which has not been connected to a handler. Only
+ * initialize it if the handler is 0 which means it was not
+ * initialized statically by the tools/user. Set the callback
+ * reference to this instance so that unhandled interrupts
+ * can be tracked.
+ */
+ if ((InstancePtr->Config->HandlerTable[Int_Id].Handler == NULL)) {
+ InstancePtr->Config->HandlerTable[Int_Id].Handler = StubHandler;
+ }
+ InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
+ }
+
+ DistributorInit(InstancePtr, Cpu_Id);
+ CPUInitialize(InstancePtr);
+
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+ }
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Makes the connection between the Int_Id of the interrupt source and the
+ * associated handler that is to run when the interrupt is recognized. The
+ * argument provided in this call as the Callbackref is used as the argument
+ * for the handler when it is called.
+ *
+ * @param InstancePtr is a pointer to the XScuGic instance.
+ * @param Int_Id contains the ID of the interrupt source and should be
+ * in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+ * @param Handler to the handler for that interrupt.
+ * @param CallBackRef is the callback reference, usually the instance
+ * pointer of the connecting driver.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if the handler was connected correctly.
+ *
+ * @note
+ *
+ * WARNING: The handler provided as an argument will overwrite any handler
+ * that was previously connected.
+ *
+ ****************************************************************************/
+s32 XScuGic_Connect(XScuGic* InstancePtr, u32 Int_Id,
+ Xil_InterruptHandler Handler, void* CallBackRef)
+{
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertNonvoid(Handler != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The Int_Id is used as an index into the table to select the proper
+ * handler
+ */
+ InstancePtr->Config->HandlerTable[Int_Id].Handler = Handler;
+ InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef;
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Updates the interrupt table with the Null Handler and NULL arguments at the
+ * location pointed at by the Int_Id. This effectively disconnects that interrupt
+ * source from any handler. The interrupt is disabled also.
+ *
+ * @param InstancePtr is a pointer to the XScuGic instance to be worked on.
+ * @param Int_Id contains the ID of the interrupt source and should
+ * be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ ****************************************************************************/
+void XScuGic_Disconnect(XScuGic* InstancePtr, u32 Int_Id)
+{
+ u32 Mask;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The Int_Id is used to create the appropriate mask for the
+ * desired bit position. Int_Id currently limited to 0 - 31
+ */
+ Mask = 0x00000001U << (Int_Id % 32U);
+
+ /*
+ * Disable the interrupt such that it won't occur while disconnecting
+ * the handler, only disable the specified interrupt id without modifying
+ * the other interrupt ids
+ */
+ XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET + ((Int_Id / 32U) * 4U), Mask);
+
+ /*
+ * Disconnect the handler and connect a stub, the callback reference
+ * must be set to this instance to allow unhandled interrupts to be
+ * tracked
+ */
+ InstancePtr->Config->HandlerTable[Int_Id].Handler = StubHandler;
+ InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Enables the interrupt source provided as the argument Int_Id. Any pending
+ * interrupt condition for the specified Int_Id will occur after this function is
+ * called.
+ *
+ * @param InstancePtr is a pointer to the XScuGic instance.
+ * @param Int_Id contains the ID of the interrupt source and should be
+ * in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ ****************************************************************************/
+void XScuGic_Enable(XScuGic* InstancePtr, u32 Int_Id)
+{
+ u32 Mask;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The Int_Id is used to create the appropriate mask for the
+ * desired bit position. Int_Id currently limited to 0 - 31
+ */
+ Mask = 0x00000001U << (Int_Id % 32U);
+
+ /*
+ * Enable the selected interrupt source by setting the
+ * corresponding bit in the Enable Set register.
+ */
+ XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET + ((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Disables the interrupt source provided as the argument Int_Id such that the
+ * interrupt controller will not cause interrupts for the specified Int_Id. The
+ * interrupt controller will continue to hold an interrupt condition for the
+ * Int_Id, but will not cause an interrupt.
+ *
+ * @param InstancePtr is a pointer to the XScuGic instance.
+ * @param Int_Id contains the ID of the interrupt source and should be
+ * in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ ****************************************************************************/
+void XScuGic_Disable(XScuGic* InstancePtr, u32 Int_Id)
+{
+ u32 Mask;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ /*
+ * The Int_Id is used to create the appropriate mask for the
+ * desired bit position. Int_Id currently limited to 0 - 31
+ */
+ Mask = 0x00000001U << (Int_Id % 32U);
+
+ /*
+ * Disable the selected interrupt source by setting the
+ * corresponding bit in the IDR.
+ */
+ XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET + ((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Allows software to simulate an interrupt in the interrupt controller. This
+ * function will only be successful when the interrupt controller has been
+ * started in simulation mode. A simulated interrupt allows the interrupt
+ * controller to be tested without any device to drive an interrupt input
+ * signal into it.
+ *
+ * @param InstancePtr is a pointer to the XScuGic instance.
+ * @param Int_Id is the software interrupt ID to simulate an interrupt.
+ * @param Cpu_Id is the list of CPUs to send the interrupt.
+ *
+ * @return
+ *
+ * XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be
+ * simulated
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+s32 XScuGic_SoftwareIntr(XScuGic* InstancePtr, u32 Int_Id, u32 Cpu_Id)
+{
+ u32 Mask;
+
+ /*
+ * Assert the arguments
+ */
+ Xil_AssertNonvoid(InstancePtr != NULL);
+ Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertNonvoid(Int_Id <= 15U);
+ Xil_AssertNonvoid(Cpu_Id <= 255U);
+
+ /*
+ * The Int_Id is used to create the appropriate mask for the
+ * desired interrupt. Int_Id currently limited to 0 - 15
+ * Use the target list for the Cpu ID.
+ */
+ Mask = ((Cpu_Id << 16U) | Int_Id) & (XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK);
+
+ /*
+ * Write to the Software interrupt trigger register. Use the appropriate
+ * CPU Int_Id.
+ */
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask);
+
+ /* Indicate the interrupt was successfully simulated */
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ *
+ * A stub for the asynchronous callback. The stub is here in case the upper
+ * layers forget to set the handler.
+ *
+ * @param CallBackRef is a pointer to the upper layer callback reference
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+static void StubHandler(void* CallBackRef)
+{
+ /*
+ * verify that the inputs are valid
+ */
+ Xil_AssertVoid(CallBackRef != NULL);
+
+ /*
+ * Indicate another unhandled interrupt for stats
+ */
+ ((XScuGic*)((void*)CallBackRef))->UnhandledInterrupts++;
+}
+
+/****************************************************************************/
+/**
+ * Sets the interrupt priority and trigger type for the specificd IRQ source.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Int_Id is the IRQ source number to modify
+ * @param Priority is the new priority for the IRQ source. 0 is highest
+ * priority, 0xF8 (248) is lowest. There are 32 priority levels
+ * supported with a step of 8. Hence the supported priorities are
+ * 0, 8, 16, 32, 40 ..., 248.
+ * @param Trigger is the new trigger type for the IRQ source.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI Read Only b10 always
+ * PPI Read Only depending on how the PPIs are configured.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive
+ * SPI LSB is read only.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive/
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ *****************************************************************************/
+void XScuGic_SetPriorityTriggerType(XScuGic* InstancePtr, u32 Int_Id,
+ u8 Priority, u8 Trigger)
+{
+ u32 RegValue;
+ u8 LocalPriority;
+ LocalPriority = Priority;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK);
+ Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL);
+
+ /*
+ * Determine the register to write to using the Int_Id.
+ */
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+ /*
+ * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+ * means the number of priority levels supported are 32 and they are
+ * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+ * The lower order 3 bits are masked before putting it in the register.
+ */
+ LocalPriority = LocalPriority & (u8)XSCUGIC_INTR_PRIO_MASK;
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id % 4U) * 8U));
+ RegValue |= (u32)LocalPriority << ((Int_Id % 4U) * 8U);
+
+ /*
+ * Write the value back to the register.
+ */
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+ RegValue);
+
+ /*
+ * Determine the register to write to using the Int_Id.
+ */
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id % 16U) * 2U));
+ RegValue |= (u32)Trigger << ((Int_Id % 16U) * 2U);
+
+ /*
+ * Write the value back to the register.
+ */
+ XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+ RegValue);
+}
+
+/****************************************************************************/
+/**
+ * Gets the interrupt priority and trigger type for the specificd IRQ source.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Int_Id is the IRQ source number to modify
+ * @param Priority is a pointer to the value of the priority of the IRQ
+ * source. This is a return value.
+ * @param Trigger is pointer to the value of the trigger of the IRQ
+ * source. This is a return value.
+ *
+ * @return None.
+ *
+ * @note None
+ *
+ *****************************************************************************/
+void XScuGic_GetPriorityTriggerType(XScuGic* InstancePtr, u32 Int_Id,
+ u8* Priority, u8* Trigger)
+{
+ u32 RegValue;
+
+ Xil_AssertVoid(InstancePtr != NULL);
+ Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(Priority != NULL);
+ Xil_AssertVoid(Trigger != NULL);
+
+ /*
+ * Determine the register to read to using the Int_Id.
+ */
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue = RegValue >> ((Int_Id % 4U) * 8U);
+ *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+ /*
+ * Determine the register to read to using the Int_Id.
+ */
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue = RegValue >> ((Int_Id % 16U) * 2U);
+
+ *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+/****************************************************************************/
+/**
+ * Sets the target CPU for the interrupt of a peripheral
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Cpu_Id is a CPU number for which the interrupt has to be targeted
+ * @param Int_Id is the IRQ source number to modify
+ *
+ * @return None.
+ *
+ * @note None
+ *
+ *****************************************************************************/
+void XScuGic_InterruptMaptoCpu(XScuGic* InstancePtr, u8 Cpu_Id, u32 Int_Id)
+{
+ u32 RegValue, Offset;
+ RegValue = XScuGic_DistReadReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+ Offset = (Int_Id & 0x3);
+
+ RegValue = (RegValue | (~(0xFF << (Offset * 8))));
+ RegValue |= ((Cpu_Id) << (Offset * 8));
+
+ XScuGic_DistWriteReg(InstancePtr,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+ RegValue);
+}
+/** @} */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic.h
new file mode 100755
index 000000000..373e2c0eb
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic.h
@@ -0,0 +1,312 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xscugic.h
+ * @addtogroup scugic_v3_1
+ * @{
+ * @details
+ *
+ * The generic interrupt controller driver component.
+ *
+ * The interrupt controller driver uses the idea of priority for the various
+ * handlers. Priority is an integer within the range of 1 and 31 inclusive with
+ * default of 1 being the highest priority interrupt source. The priorities
+ * of the various sources can be dynamically altered as needed through
+ * hardware configuration.
+ *
+ * The generic interrupt controller supports the following
+ * features:
+ *
+ * - specific individual interrupt enabling/disabling
+ * - specific individual interrupt acknowledging
+ * - attaching specific callback function to handle interrupt source
+ * - assigning desired priority to interrupt source if default is not
+ * acceptable.
+ *
+ * Details about connecting the interrupt handler of the driver are contained
+ * in the source file specific to interrupt processing, xscugic_intr.c.
+ *
+ * This driver is intended to be RTOS and processor independent. It works with
+ * physical addresses only. Any needs for dynamic memory management, threads
+ * or thread mutual exclusion, virtual memory, or cache control must be
+ * satisfied by the layer above this driver.
+ *
+ * Interrupt Vector Tables
+ *
+ * The device ID of the interrupt controller device is used by the driver as a
+ * direct index into the configuration data table. The user should populate the
+ * vector table with handlers and callbacks at run-time using the
+ * XScuGic_Connect() and XScuGic_Disconnect() functions.
+ *
+ * Each vector table entry corresponds to a device that can generate an
+ * interrupt. Each entry contains an interrupt handler function and an
+ * argument to be passed to the handler when an interrupt occurs. The
+ * user must use XScuGic_Connect() when the interrupt handler takes an
+ * argument other than the base address.
+ *
+ * Nested Interrupts Processing
+ *
+ * Nested interrupts are not supported by this driver.
+ *
+ * NOTE:
+ * The generic interrupt controller is not a part of the snoop control unit
+ * as indicated by the prefix "scu" in the name of the driver.
+ * It is an independent module in APU.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- ---------------------------------------------------------
+ * 1.00a drg 01/19/00 First release
+ * 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed.
+ * The HandlerTable (of type XScuGic_VectorTableEntry) is
+ * moved to XScuGic_Config structure from XScuGic structure.
+ *
+ * The "Config" entry in XScuGic structure is made as
+ * pointer for better efficiency.
+ *
+ * A new file named as xscugic_hw.c is now added. It is
+ * to implement low level driver routines without using
+ * any xscugic instance pointer. They are useful when the
+ * user wants to use xscugic through device id or
+ * base address. The driver routines provided are explained
+ * below.
+ * XScuGic_DeviceInitialize that takes device id as
+ * argument and initializes the device (without calling
+ * XScuGic_CfgInitialize).
+ * XScuGic_DeviceInterruptHandler that takes device id
+ * as argument and calls appropriate handlers from the
+ * HandlerTable.
+ * XScuGic_RegisterHandler that registers a new handler
+ * by taking xscugic hardware base address as argument.
+ * LookupConfigByBaseAddress is used to return the
+ * corresponding config structure from XScuGic_ConfigTable
+ * based on the scugic base address passed.
+ * 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config
+ * structure.
+ * 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+ * *_hw.h
+ * Added APIs
+ * - XScuGic_SetPriTrigTypeByDistAddr()
+ * - XScuGic_GetPriTrigTypeByDistAddr()
+ * (CR 702687)
+ * Added support to direct interrupts to the appropriate CPU. Earlier
+ * interrupts were directed to CPU1 (hard coded). Now depending
+ * upon the CPU selected by the user (xparameters.h), interrupts
+ * will be directed to the relevant CPU. This fixes CR 699688.
+ * 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+ * XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+ * Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+ * XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+ * This is fix for CR#705621.
+ * 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to
+ * xparameters.h. Fix for CR's 690505, 708928 & 719359.
+ * 2.0 adk 12/10/13 Updated as per the New Tcl API's
+ * 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+ * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ *
+ *
+ *
+ ******************************************************************************/
+
+#ifndef XSCUGIC_H /* prevent circular inclusions */
+#define XSCUGIC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_exception.h"
+#include "xil_io.h"
+#include "xscugic_hw.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the low level driver and an instance pointer for the high level driver.
+ */
+typedef struct
+{
+ Xil_InterruptHandler Handler;
+ void* CallBackRef;
+} XScuGic_VectorTableEntry;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct
+{
+ u16 DeviceId; /**< Unique ID of device */
+ u32 CpuBaseAddress; /**< CPU Interface Register base address */
+ u32 DistBaseAddress; /**< Distributor Register base address */
+ XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS]; /**<
+ Vector table of interrupt handlers */
+} XScuGic_Config;
+
+/**
+ * The XScuGic driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct
+{
+ XScuGic_Config* Config; /**< Configuration table entry */
+ u32 IsReady; /**< Device is initialized and ready */
+ u32 UnhandledInterrupts; /**< Intc Statistics */
+} XScuGic;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+ *
+ * Write the given CPU Interface register
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param RegOffset is the register offset to be written
+ * @param Data is the 32-bit value to write to the register
+ *
+ * @return None.
+ *
+ * @note
+ * C-style signature:
+ * void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+ *
+ *****************************************************************************/
+#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
+ (XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
+ ((u32)(Data))))
+
+/****************************************************************************/
+/**
+ *
+ * Read the given CPU Interface register
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param RegOffset is the register offset to be read
+ *
+ * @return The 32-bit value of the register
+ *
+ * @note
+ * C-style signature:
+ * u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
+ *
+ *****************************************************************************/
+#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
+ (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+ *
+ * Write the given Distributor Interface register
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param RegOffset is the register offset to be written
+ * @param Data is the 32-bit value to write to the register
+ *
+ * @return None.
+ *
+ * @note
+ * C-style signature:
+ * void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+ *
+ *****************************************************************************/
+#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
+ (XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
+ ((u32)(Data))))
+
+/****************************************************************************/
+/**
+ *
+ * Read the given Distributor Interface register
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param RegOffset is the register offset to be read
+ *
+ * @return The 32-bit value of the register
+ *
+ * @note
+ * C-style signature:
+ * u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+ *
+ *****************************************************************************/
+#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
+ (XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xscugic.c
+ */
+
+s32 XScuGic_Connect(XScuGic* InstancePtr, u32 Int_Id,
+ Xil_InterruptHandler Handler, void* CallBackRef);
+void XScuGic_Disconnect(XScuGic* InstancePtr, u32 Int_Id);
+
+void XScuGic_Enable(XScuGic* InstancePtr, u32 Int_Id);
+void XScuGic_Disable(XScuGic* InstancePtr, u32 Int_Id);
+
+s32 XScuGic_CfgInitialize(XScuGic* InstancePtr, XScuGic_Config* ConfigPtr,
+ u32 EffectiveAddr);
+
+s32 XScuGic_SoftwareIntr(XScuGic* InstancePtr, u32 Int_Id, u32 Cpu_Id);
+
+void XScuGic_GetPriorityTriggerType(XScuGic* InstancePtr, u32 Int_Id,
+ u8* Priority, u8* Trigger);
+void XScuGic_SetPriorityTriggerType(XScuGic* InstancePtr, u32 Int_Id,
+ u8 Priority, u8 Trigger);
+void XScuGic_InterruptMaptoCpu(XScuGic* InstancePtr, u8 Cpu_Id, u32 Int_Id);
+/*
+ * Initialization functions in xscugic_sinit.c
+ */
+XScuGic_Config* XScuGic_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt functions in xscugic_intr.c
+ */
+void XScuGic_InterruptHandler(XScuGic* InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic_g.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic_g.c
new file mode 100755
index 000000000..1bd8410b9
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic_g.c
@@ -0,0 +1,52 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version:
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2024 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+#include "xparameters.h"
+#include "xscugic.h"
+
+#include "mmio_access.h"
+
+/*
+ * The configuration table for devices
+ */
+
+XScuGic_Config XScuGic_ConfigTable[] = {
+ { XPAR_PS7_SCUGIC_0_DEVICE_ID,
+ MMIO_P2V_WO(XPAR_PS7_SCUGIC_0_BASEADDR),
+ MMIO_P2V_WO(XPAR_PS7_SCUGIC_0_DIST_BASEADDR) }
+};
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic_hw.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic_hw.c
new file mode 100755
index 000000000..bbd221131
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic_hw.c
@@ -0,0 +1,563 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xscugic_hw.c
+ * @addtogroup scugic_v3_1
+ * @{
+ *
+ * This file contains low-level driver functions that can be used to access the
+ * device. The user should refer to the hardware device specification for more
+ * details of the device operation.
+ * These routines are used when the user does not want to create an instance of
+ * XScuGic structure but still wants to use the ScuGic device. Hence the
+ * routines provided here take device id or scugic base address as arguments.
+ * Separate static versions of DistInit and CPUInit are provided to implement
+ * the low level driver routines.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.01a sdm 07/18/11 First release
+ * 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
+ * 702687).
+ * Added support to direct interrupts to the appropriate CPU.
+ * Earlier interrupts were directed to CPU1 (hard coded). Now
+ * depending upon the CPU selected by the user (xparameters.h),
+ * interrupts will be directed to the relevant CPU.
+ * This fixes CR 699688.
+ * 1.04a hk 05/04/13 Fix for CR#705621. Moved functions
+ * XScuGic_SetPriTrigTypeByDistAddr and
+ * XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c
+ * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ *
+ *
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_assert.h"
+#include "xil_types.h"
+#include "xparameters.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void DistInit(XScuGic_Config* Config, u32 CpuID);
+static void CPUInit(XScuGic_Config* Config);
+static XScuGic_Config* LookupConfigByBaseAddress(u32 CpuBaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+ *
+ * DistInit initializes the distributor of the GIC. The
+ * initialization entails:
+ *
+ * - Write the trigger mode, priority and target CPU
+ * - All interrupt sources are disabled
+ * - Enable the distributor
+ *
+ * @param InstancePtr is a pointer to the XScuGic instance.
+ * @param CpuID is the Cpu ID to be initialized.
+ *
+ * @return None
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+static void DistInit(XScuGic_Config* Config, u32 CpuID)
+{
+ u32 Int_Id;
+ u32 LocalCpuID = CpuID;
+
+#if USE_AMP == 1
+#warning "Building GIC for AMP"
+
+ /*
+ * The distrubutor should not be initialized by FreeRTOS in the case of
+ * AMP -- it is assumed that Linux is the master of this device in that
+ * case.
+ */
+ return;
+#endif
+
+ XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0U);
+
+ /*
+ * Set the security domains in the int_security registers for non-secure
+ * interrupts. All are secure, so leave at the default. Set to 1 for
+ * non-secure interrupts.
+ */
+
+ /*
+ * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+ */
+
+ /*
+ * 1. The trigger mode in the int_config register
+ * Only write to the SPI interrupts, so start at 32
+ */
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id = Int_Id + 16U) {
+ /*
+ * Each INT_ID uses two bits, or 16 INT_ID per register
+ * Set them all to be level sensitive, active HIGH.
+ */
+ XScuGic_WriteReg(Config->DistBaseAddress,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U);
+ }
+
+#define DEFAULT_PRIORITY 0xa0a0a0a0U
+ for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id = Int_Id + 4U) {
+ /*
+ * 2. The priority using int the priority_level register
+ * The priority_level and spi_target registers use one byte per
+ * INT_ID.
+ * Write a default value that can be changed elsewhere.
+ */
+ XScuGic_WriteReg(Config->DistBaseAddress,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+ DEFAULT_PRIORITY);
+ }
+
+ for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id = Int_Id + 4U) {
+ /*
+ * 3. The CPU interface in the spi_target register
+ * Only write to the SPI interrupts, so start at 32
+ */
+ LocalCpuID |= LocalCpuID << 8U;
+ LocalCpuID |= LocalCpuID << 16U;
+
+ XScuGic_WriteReg(Config->DistBaseAddress,
+ XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), LocalCpuID);
+ }
+
+ for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id = Int_Id + 32U) {
+ /*
+ * 4. Enable the SPI using the enable_set register. Leave all disabled
+ * for now.
+ */
+ XScuGic_WriteReg(Config->DistBaseAddress,
+ XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
+ Int_Id),
+ 0xFFFFFFFFU);
+ }
+
+ XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET,
+ XSCUGIC_EN_INT_MASK);
+}
+
+/*****************************************************************************/
+/**
+ *
+ * CPUInit initializes the CPU Interface of the GIC. The initialization entails:
+ *
+ * - Set the priority of the CPU.
+ * - Enable the CPU interface
+ *
+ * @param ConfigPtr is a pointer to a config table for the particular
+ * device this driver is associated with.
+ *
+ * @return None
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+static void CPUInit(XScuGic_Config* Config)
+{
+ /*
+ * Program the priority mask of the CPU using the Priority mask
+ * register
+ */
+ XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET,
+ 0xF0U);
+
+ /*
+ * If the CPU operates in both security domains, set parameters in the
+ * control_s register.
+ * 1. Set FIQen=1 to use FIQ for secure interrupts,
+ * 2. Program the AckCtl bit
+ * 3. Program the SBPR bit to select the binary pointer behavior
+ * 4. Set EnableS = 1 to enable secure interrupts
+ * 5. Set EnbleNS = 1 to enable non secure interrupts
+ */
+
+ /*
+ * If the CPU operates only in the secure domain, setup the
+ * control_s register.
+ * 1. Set FIQen=1,
+ * 2. Set EnableS=1, to enable the CPU interface to signal secure .
+ * interrupts Only enable the IRQ output unless secure interrupts
+ * are needed.
+ */
+ XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07U);
+}
+
+/*****************************************************************************/
+/**
+ *
+ * CfgInitialize a specific interrupt controller instance/driver. The
+ * initialization entails:
+ *
+ * - Initialize fields of the XScuGic structure
+ * - Initial vector table with stub function calls
+ * - All interrupt sources are disabled
+ *
+ * @param InstancePtr is a pointer to the XScuGic instance to be worked on.
+ * @param ConfigPtr is a pointer to a config table for the particular device
+ * this driver is associated with.
+ * @param EffectiveAddr is the device base address in the virtual memory address
+ * space. The caller is responsible for keeping the address mapping
+ * from EffectiveAddr to the device physical base address unchanged
+ * once this function is invoked. Unexpected errors may occur if the
+ * address mapping changes after this function is called. If address
+ * translation is not used, use Config->BaseAddress for this parameters,
+ * passing the physical address instead.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if initialization was successful
+ *
+ * @note
+ *
+ * None.
+ *
+ ******************************************************************************/
+s32 XScuGic_DeviceInitialize(u32 DeviceId)
+{
+ XScuGic_Config* Config;
+ u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1;
+
+ Config = &XScuGic_ConfigTable[(u32)DeviceId];
+
+ DistInit(Config, Cpu_Id);
+
+ CPUInit(Config);
+
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * This function is the primary interrupt handler for the driver. It must be
+ * connected to the interrupt source such that it is called when an interrupt of
+ * the interrupt controller is active. It will resolve which interrupts are
+ * active and enabled and call the appropriate interrupt handler. It uses
+ * the Interrupt Type information to determine when to acknowledge the
+ * interrupt.Highest priority interrupts are serviced first.
+ *
+ * This function assumes that an interrupt vector table has been previously
+ * initialized. It does not verify that entries in the table are valid before
+ * calling an interrupt handler.
+ *
+ * @param DeviceId is the unique identifier for the ScuGic device.
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+void XScuGic_DeviceInterruptHandler(void* DeviceId)
+{
+
+ u32 InterruptID;
+ u32 IntIDFull;
+ XScuGic_VectorTableEntry* TablePtr;
+ XScuGic_Config* CfgPtr;
+
+ CfgPtr = &XScuGic_ConfigTable[(INTPTR)DeviceId];
+
+ /*
+ * Read the int_ack register to identify the highest priority
+ * interrupt ID and make sure it is valid. Reading Int_Ack will
+ * clear the interrupt in the GIC.
+ */
+ IntIDFull = XScuGic_ReadReg(CfgPtr->CpuBaseAddress, XSCUGIC_INT_ACK_OFFSET);
+ InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+ if (XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID) {
+ goto IntrExit;
+ }
+
+ /*
+ * If the interrupt is shared, do some locking here if there are
+ * multiple processors.
+ */
+ /*
+ * If pre-eption is required:
+ * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+ * interrupts or the F bit for secure interrupts
+ */
+
+ /*
+ * If we need to change security domains, issue a SMC instruction here.
+ */
+
+ /*
+ * Execute the ISR. Jump into the Interrupt service routine based on
+ * the IRQSource. A software trigger is cleared by the ACK.
+ */
+ TablePtr = &(CfgPtr->HandlerTable[InterruptID]);
+ if (TablePtr != NULL) {
+ TablePtr->Handler(TablePtr->CallBackRef);
+ }
+
+IntrExit:
+ /*
+ * Write to the EOI register, we are all done here.
+ * Let this function return, the boot code will restore the stack.
+ */
+ XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+ /*
+ * Return from the interrupt. Change security domains could happen
+ * here.
+ */
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Register a handler function for a specific interrupt ID. The vector table
+ * of the interrupt controller is updated, overwriting any previous handler.
+ * The handler function will be called when an interrupt occurs for the given
+ * interrupt ID.
+ *
+ * @param BaseAddress is the CPU Interface Register base address of the
+ * interrupt controller whose vector table will be modified.
+ * @param InterruptId is the interrupt ID to be associated with the input
+ * handler.
+ * @param Handler is the function pointer that will be added to
+ * the vector table for the given interrupt ID.
+ * @param CallBackRef is the argument that will be passed to the new
+ * handler function when it is called. This is user-specific.
+ *
+ * @return None.
+ *
+ * @note
+ *
+ * Note that this function has no effect if the input base address is invalid.
+ *
+ ******************************************************************************/
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+ Xil_InterruptHandler IntrHandler, void* CallBackRef)
+{
+ XScuGic_Config* CfgPtr;
+ CfgPtr = LookupConfigByBaseAddress(BaseAddress);
+
+ if (CfgPtr != NULL) {
+ if (IntrHandler != NULL) {
+ CfgPtr->HandlerTable[InterruptID].Handler = IntrHandler;
+ }
+ if (CallBackRef != NULL) {
+ CfgPtr->HandlerTable[InterruptID].CallBackRef = CallBackRef;
+ }
+ }
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Looks up the device configuration based on the CPU interface base address of
+ * the device. A table contains the configuration info for each device in the
+ * system.
+ *
+ * @param CpuBaseAddress is the CPU Interface Register base address.
+ *
+ * @return A pointer to the configuration structure for the specified
+ * device, or NULL if the device was not found.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+static XScuGic_Config* LookupConfigByBaseAddress(u32 CpuBaseAddress)
+{
+ XScuGic_Config* CfgPtr = NULL;
+ u32 Index;
+
+ for (Index = 0U; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+ if (XScuGic_ConfigTable[Index].CpuBaseAddress == CpuBaseAddress) {
+ CfgPtr = &XScuGic_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XScuGic_Config*)CfgPtr;
+}
+
+/****************************************************************************/
+/**
+ * Sets the interrupt priority and trigger type for the specificd IRQ source.
+ *
+ * @param BaseAddr is the device base address
+ * @param Int_Id is the IRQ source number to modify
+ * @param Priority is the new priority for the IRQ source. 0 is highest
+ * priority, 0xF8 (248) is lowest. There are 32 priority levels
+ * supported with a step of 8. Hence the supported priorities are
+ * 0, 8, 16, 32, 40 ..., 248.
+ * @param Trigger is the new trigger type for the IRQ source.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI Read Only b10 always
+ * PPI Read Only depending on how the PPIs are configured.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive
+ * SPI LSB is read only.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive/
+ *
+ * @return None.
+ *
+ * @note This API has the similar functionality of XScuGic_SetPriority
+ * TriggerType() and should be used when there is no InstancePtr.
+ *
+ *****************************************************************************/
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 Priority, u8 Trigger)
+{
+ u32 RegValue;
+ u8 LocalPriority = Priority;
+
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK);
+ Xil_AssertVoid(LocalPriority <= XSCUGIC_MAX_INTR_PRIO_VAL);
+
+ /*
+ * Determine the register to write to using the Int_Id.
+ */
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+ /*
+ * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+ * means the number of priority levels supported are 32 and they are
+ * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+ * The lower order 3 bits are masked before putting it in the register.
+ */
+ LocalPriority = LocalPriority & XSCUGIC_INTR_PRIO_MASK;
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id % 4U) * 8U));
+ RegValue |= (u32)LocalPriority << ((Int_Id % 4U) * 8U);
+
+ /*
+ * Write the value back to the register.
+ */
+ XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+ RegValue);
+ /*
+ * Determine the register to write to using the Int_Id.
+ */
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id % 16U) * 2U));
+ RegValue |= (u32)Trigger << ((Int_Id % 16U) * 2U);
+
+ /*
+ * Write the value back to the register.
+ */
+ XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+ RegValue);
+}
+
+/****************************************************************************/
+/**
+ * Gets the interrupt priority and trigger type for the specificd IRQ source.
+ *
+ * @param BaseAddr is the device base address
+ * @param Int_Id is the IRQ source number to modify
+ * @param Priority is a pointer to the value of the priority of the IRQ
+ * source. This is a return value.
+ * @param Trigger is pointer to the value of the trigger of the IRQ
+ * source. This is a return value.
+ *
+ * @return None.
+ *
+ * @note This API has the similar functionality of XScuGic_GetPriority
+ * TriggerType() and should be used when there is no InstancePtr.
+ *
+ *****************************************************************************/
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8* Priority, u8* Trigger)
+{
+ u32 RegValue;
+
+ Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+ Xil_AssertVoid(Priority != NULL);
+ Xil_AssertVoid(Trigger != NULL);
+
+ /*
+ * Determine the register to read to using the Int_Id.
+ */
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue = RegValue >> ((Int_Id % 4U) * 8U);
+ *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+ /*
+ * Determine the register to read to using the Int_Id.
+ */
+ RegValue = XScuGic_ReadReg(DistBaseAddress,
+ XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
+
+ /*
+ * Shift and Mask the correct bits for the priority and trigger in the
+ * register
+ */
+ RegValue = RegValue >> ((Int_Id % 16U) * 2U);
+
+ *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+/** @} */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic_hw.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic_hw.h
new file mode 100755
index 000000000..49505f107
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic_hw.h
@@ -0,0 +1,635 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xscugic_hw.h
+ * @addtogroup scugic_v3_1
+ * @{
+ *
+ * This header file contains identifiers and HW access functions (or
+ * macros) that can be used to access the device. The user should refer to the
+ * hardware device specification for more details of the device operation.
+ * The driver functions/APIs are defined in xscugic.h.
+ *
+ * This GIC device has two parts, a distributor and CPU interface(s). Each part
+ * has separate register definition sections.
+ *
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -----------------------------------------------------
+ * 1.00a drg 01/19/10 First release
+ * 1.01a sdm 11/09/11 "xil_exception.h" added as include.
+ * Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+ * added to enable or disable interrupts based on
+ * Distributor Register base address. Normally users use
+ * XScuGic instance and call XScuGic_Enable or
+ * XScuGic_Disable to enable/disable interrupts. These
+ * new macros are provided when user does not want to
+ * use an instance pointer but still wants to enable or
+ * disable interrupts.
+ * Function prototypes for functions (present in newly
+ * added file xscugic_hw.c) are added.
+ * 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
+ * 702687).
+ * 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
+ * XScuGic_SetPriTrigTypeByDistAddr and
+ * XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+ * 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+ * Zynq Ultrascale Mp
+ * 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
+ *
+ *
+ ******************************************************************************/
+
+#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
+#define XSCUGIC_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_exception.h"
+#include "xil_io.h"
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The maximum number of interrupts supported by the hardware.
+ */
+#ifdef __ARM_NEON__
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
+#else
+#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
+#endif
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
+#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
+
+/** @name Distributor Interface Register Map
+ *
+ * Define the offsets from the base address for all Distributor registers of
+ * the interrupt controller, some registers may be reserved in the hardware
+ * device.
+ * @{
+ */
+#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable \
+ Register */
+#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller \
+ Type Register */
+#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID \
+ Register */
+#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security \
+ Register */
+#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set \
+ Register */
+#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
+#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set \
+ Register */
+#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear \
+ Register */
+#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
+#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
+#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target \
+ Register 0x800-0x8FB */
+#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration \
+ Register 0xC00-0xCFC */
+#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
+#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register \
+ 0xd04-0xd7C */
+#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration \
+ Register */
+#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered \
+ Interrupt Register */
+#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
+#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
+/* @} */
+
+/** @name Distributor Enable Register
+ * Controls if the distributor response to external interrupt inputs.
+ * @{
+ */
+#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
+/* @} */
+
+/** @name Interrupt Controller Type Register
+ * @{
+ */
+#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable \
+ Shared Peripheral \
+ Interrupts*/
+#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
+#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
+#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
+/* @} */
+
+/** @name Implementor ID Register
+ * Implementor and revision information.
+ * @{
+ */
+#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
+#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
+/* @} */
+
+/** @name Interrupt Security Registers
+ * Each bit controls the security level of an interrupt, either secure or non
+ * secure. These registers can only be accessed using secure read and write.
+ * There are registers for each of the CPU interfaces at offset 0x080. A
+ * register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x084.
+ * @{
+ */
+#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an \
+ INT_ID */
+/* @} */
+
+/** @name Enable Set Register
+ * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
+ * bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x100. With up
+ * to 8 registers aliased to the same address. A register set for the SPI
+ * interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x104.
+ * @{
+ */
+#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an \
+ INT_ID */
+/* @} */
+
+/** @name Enable Clear Register
+ * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
+ * sets the corresponding bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x180. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x184.
+ * @{
+ */
+#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an \
+ INT_ID */
+/* @} */
+
+/** @name Pending Set Register
+ * Each bit controls the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
+ * an interrupt to the pending state.
+ * There are registers for each of the CPU interfaces at offset 0x200. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x204.
+ * @{
+ */
+#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an \
+ INT_ID */
+/* @} */
+
+/** @name Pending Clear Register
+ * Each bit can clear the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
+ * clears the pending state of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x280. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x284.
+ * @{
+ */
+#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an \
+ INT_ID */
+/* @} */
+
+/** @name Active Status Register
+ * Each bit provides the Active status of an interrupt, a
+ * 0 is not Active, a 1 is Active. This is a read only register.
+ * There are registers for each of the CPU interfaces at offset 0x300. With up
+ * to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x380.
+ * @{
+ */
+#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an \
+ INT_ID */
+/* @} */
+
+/** @name Priority Level Register
+ * Each byte in a Priority Level Register sets the priority level of an
+ * interrupt. Reading the register provides the priority level of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x400 through
+ * 0x41C. With up to 8 registers aliased to each address.
+ * 0 is highest priority, 0xFF is lowest.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x420.
+ * @{
+ */
+#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an \
+ INT_ID */
+#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority \
+ actually the lowest priority*/
+/* @} */
+
+/** @name SPI Target Register 0x800-0x8FB
+ * Each byte references a separate SPI and programs which of the up to 8 CPU
+ * interfaces are sent a Pending interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x800 through
+ * 0x81C. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x820.
+ *
+ * This driver does not support multiple CPU interfaces. These are included
+ * for complete documentation.
+ * @{
+ */
+#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
+#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
+#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
+#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
+#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
+#define XSCUGIC_SPI_CPU2_MASK 0x00000003U /**< CPU 2 Mask*/
+#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
+#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
+/* @} */
+
+/** @name Interrupt Configuration Register 0xC00-0xCFC
+ * The interrupt configuration registers program an SFI to be active HIGH level
+ * sensitive or rising edge sensitive.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI Read Only b10 always
+ * PPI Read Only depending on how the PPIs are configured.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive
+ * SPI LSB is read only.
+ * b01 Active HIGH level sensitive
+ * b11 Rising edge sensitive/
+ * There are registers for each of the CPU interfaces at offset 0xC00 through
+ * 0xC04. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0xC08.
+ * @{
+ */
+#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
+/* @} */
+
+/** @name PPI Status Register
+ * Enables an external AMBA master to access the status of the PPI inputs.
+ * A CPU can only read the status of its local PPI signals and cannot read the
+ * status for other CPUs.
+ * This register is aliased for each CPU interface.
+ * @{
+ */
+#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
+#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
+#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
+#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
+#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
+#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
+#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
+#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
+#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
+#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
+#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
+#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
+#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
+#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
+#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
+#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
+/* @} */
+
+/** @name SPI Status Register 0xd04-0xd7C
+ * Enables an external AMBA master to access the status of the SPI inputs.
+ * There are up to 63 registers if the maximum number of SPI inputs are
+ * configured.
+ * @{
+ */
+#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI \
+ input */
+/* @} */
+
+/** @name AHB Configuration Register
+ * Provides the status of the CFGBIGEND input signal and allows the endianess
+ * of the GIC to be set.
+ * @{
+ */
+#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian, \
+ 1-GIC uses Big Endian */
+#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control, \
+ 1-use the AHB_END bit */
+#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
+
+/* @} */
+
+/** @name Software Triggered Interrupt Register
+ * Controls issueing of software interrupts.
+ * @{
+ */
+#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
+#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter \
+ b00-Use the target List \
+ b01-All CPUs except requester \
+ b10-To Requester \
+ b11-reserved */
+#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
+#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
+#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID \
+ signaled to the CPU*/
+/* @} */
+
+/** @name CPU Interface Register Map
+ *
+ * Define the offsets from the base address for all CPU registers of the
+ * interrupt controller, some registers may be reserved in the hardware device.
+ * @{
+ */
+#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control \
+ Register */
+#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
+#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
+#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
+#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
+#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
+#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt \
+ Register */
+#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure \
+ Binary Point Register */
+
+/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
+ * to. */
+/* @} */
+
+/** @name Control Register
+ * CPU Interface Control register definitions
+ * All bits are defined here although some are not available in the non-secure
+ * mode.
+ * @{
+ */
+#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer, \
+ 0=separate registers, \
+ 1=both use bin_pt_s */
+#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure \
+ interrupts, \
+ 0= use IRQ for both, \
+ 1=Use FIQ for secure, IRQ for non*/
+#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
+#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
+#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
+/* @} */
+
+/** @name Priority Mask Register
+ * Priority Mask register definitions
+ * The CPU interface does not send interrupt if the level of the interrupt is
+ * lower than the level of the register.
+ * @{
+ */
+/*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */
+/* @} */
+
+/** @name Binary Point Register
+ * Binary Point register definitions
+ * @{
+ */
+
+#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value \
+ Value Secure Non-secure \
+ b000 0xFE 0xFF \
+ b001 0xFC 0xFE \
+ b010 0xF8 0xFC \
+ b011 0xF0 0xF8 \
+ b100 0xE0 0xF0 \
+ b101 0xC0 0xE0 \
+ b110 0x80 0xC0 \
+ b111 0x00 0x80 \
+ */
+/*@}*/
+
+/** @name Interrupt Acknowledge Register
+ * Interrupt Acknowledge register definitions
+ * Identifies the current Pending interrupt, and the CPU ID for software
+ * interrupts.
+ */
+#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
+#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
+/* @} */
+
+/** @name End of Interrupt Register
+ * End of Interrupt register definitions
+ * Allows the CPU to signal the GIC when it completes an interrupt service
+ * routine.
+ */
+#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
+
+/* @} */
+
+/** @name Running Priority Register
+ * Running Priority register definitions
+ * Identifies the interrupt priority level of the highest priority active
+ * interrupt.
+ */
+#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
+/* @} */
+
+/*
+ * Highest Pending Interrupt register definitions
+ * Identifies the interrupt priority of the highest priority pending interupt
+ */
+#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
+/*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+ *
+ * Read the Interrupt Configuration Register offset for an interrupt id.
+ *
+ * @param InterruptID is the interrupt number.
+ *
+ * @return The 32-bit value of the offset
+ *
+ * @note
+ *
+ *****************************************************************************/
+#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID) / 16U) * 4U))
+
+/****************************************************************************/
+/**
+ *
+ * Read the Interrupt Priority Register offset for an interrupt id.
+ *
+ * @param InterruptID is the interrupt number.
+ *
+ * @return The 32-bit value of the offset
+ *
+ * @note
+ *
+ *****************************************************************************/
+#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID) / 4U) * 4U))
+
+/****************************************************************************/
+/**
+ *
+ * Read the SPI Target Register offset for an interrupt id.
+ *
+ * @param InterruptID is the interrupt number.
+ *
+ * @return The 32-bit value of the offset
+ *
+ * @note
+ *
+ *****************************************************************************/
+#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
+ ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID) / 4U) * 4U))
+
+/****************************************************************************/
+/**
+ *
+ * Read the Interrupt Clear-Enable Register offset for an interrupt ID
+ *
+ * @param Register is the register offset for the clear/enable bank.
+ * @param InterruptID is the interrupt number.
+ *
+ * @return The 32-bit value of the offset
+ *
+ * @note
+ *
+ *****************************************************************************/
+#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
+ ((Register) + (((InterruptID) / 32U) * 4U))
+
+/****************************************************************************/
+/**
+ *
+ * Read the given Intc register.
+ *
+ * @param BaseAddress is the base address of the device.
+ * @param RegOffset is the register offset to be read
+ *
+ * @return The 32-bit value of the register
+ *
+ * @note
+ * C-style signature:
+ * u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
+ *
+ *****************************************************************************/
+#define XScuGic_ReadReg(BaseAddress, RegOffset) \
+ (Xil_In32((BaseAddress) + (RegOffset)))
+
+/****************************************************************************/
+/**
+ *
+ * Write the given Intc register.
+ *
+ * @param BaseAddress is the base address of the device.
+ * @param RegOffset is the register offset to be written
+ * @param Data is the 32-bit value to write to the register
+ *
+ * @return None.
+ *
+ * @note
+ * C-style signature:
+ * void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+ *
+ *****************************************************************************/
+#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
+ (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
+
+/****************************************************************************/
+/**
+ *
+ * Enable specific interrupt(s) in the interrupt controller.
+ *
+ * @param DistBaseAddress is the Distributor Register base address of the
+ * device
+ * @param Int_Id is the ID of the interrupt source and should be in the
+ * range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+ *
+ * @return None.
+ *
+ * @note C-style signature:
+ * void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
+ *
+ *****************************************************************************/
+#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
+ XScuGic_WriteReg((DistBaseAddress), \
+ XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
+ (0x00000001U << ((Int_Id) % 32U)))
+
+/****************************************************************************/
+/**
+ *
+ * Disable specific interrupt(s) in the interrupt controller.
+ *
+ * @param DistBaseAddress is the Distributor Register base address of the
+ * device
+ * @param Int_Id is the ID of the interrupt source and should be in the
+ * range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+ *
+ *
+ * @return None.
+ *
+ * @note C-style signature:
+ * void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
+ *
+ *****************************************************************************/
+#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
+ XScuGic_WriteReg((DistBaseAddress), \
+ XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
+ (0x00000001U << ((Int_Id) % 32U)))
+
+/************************** Function Prototypes ******************************/
+
+void XScuGic_DeviceInterruptHandler(void* DeviceId);
+s32 XScuGic_DeviceInitialize(u32 DeviceId);
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+ Xil_InterruptHandler Handler, void* CallBackRef);
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8 Priority, u8 Trigger);
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+ u8* Priority, u8* Trigger);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic_intr.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic_intr.c
new file mode 100755
index 000000000..9b2a3cde6
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic_intr.c
@@ -0,0 +1,173 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xscugic_intr.c
+ * @addtogroup scugic_v3_1
+ * @{
+ *
+ * This file contains the interrupt processing for the driver for the Xilinx
+ * Interrupt Controller. The interrupt processing is partitioned separately such
+ * that users are not required to use the provided interrupt processing. This
+ * file requires other files of the driver to be linked in also.
+ *
+ * The interrupt handler, XScuGic_InterruptHandler, uses an input argument which
+ * is an instance pointer to an interrupt controller driver such that multiple
+ * interrupt controllers can be supported. This handler requires the calling
+ * function to pass it the appropriate argument, so another level of indirection
+ * may be required.
+ *
+ * The interrupt processing may be used by connecting the interrupt handler to
+ * the interrupt system. The handler does not save and restore the processor
+ * context but only handles the processing of the Interrupt Controller. The user
+ * is encouraged to supply their own interrupt handler when performance tuning is
+ * deemed necessary.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- ---------------------------------------------------------
+ * 1.00a drg 01/19/10 First release
+ * 1.01a sdm 11/09/11 XScuGic_InterruptHandler has changed correspondingly
+ * since the HandlerTable has now moved to XScuGic_Config.
+ * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ *
+ *
+ *
+ * @internal
+ *
+ * This driver assumes that the context of the processor has been saved prior to
+ * the calling of the Interrupt Controller interrupt handler and then restored
+ * after the handler returns. This requires either the running RTOS to save the
+ * state of the machine or that a wrapper be used as the destination of the
+ * interrupt vector to save the state of the processor and restore the state
+ * after the interrupt handler returns.
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_assert.h"
+#include "xil_types.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+ * This function is the primary interrupt handler for the driver. It must be
+ * connected to the interrupt source such that it is called when an interrupt of
+ * the interrupt controller is active. It will resolve which interrupts are
+ * active and enabled and call the appropriate interrupt handler. It uses
+ * the Interrupt Type information to determine when to acknowledge the interrupt.
+ * Highest priority interrupts are serviced first.
+ *
+ * This function assumes that an interrupt vector table has been previously
+ * initialized. It does not verify that entries in the table are valid before
+ * calling an interrupt handler.
+ *
+ *
+ * @param InstancePtr is a pointer to the XScuGic instance.
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+void XScuGic_InterruptHandler(XScuGic* InstancePtr)
+{
+
+ u32 InterruptID;
+ u32 IntIDFull;
+ XScuGic_VectorTableEntry* TablePtr;
+
+ /* Assert that the pointer to the instance is valid
+ */
+ Xil_AssertVoid(InstancePtr != NULL);
+
+ /*
+ * Read the int_ack register to identify the highest priority interrupt ID
+ * and make sure it is valid. Reading Int_Ack will clear the interrupt
+ * in the GIC.
+ */
+ IntIDFull = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET);
+ InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+
+ if (XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID) {
+ goto IntrExit;
+ }
+
+ /*
+ * If the interrupt is shared, do some locking here if there are multiple
+ * processors.
+ */
+ /*
+ * If pre-eption is required:
+ * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+ * interrupts or the F bit for secure interrupts
+ */
+
+ /*
+ * If we need to change security domains, issue a SMC instruction here.
+ */
+
+ /*
+ * Execute the ISR. Jump into the Interrupt service routine based on the
+ * IRQSource. A software trigger is cleared by the ACK.
+ */
+ TablePtr = &(InstancePtr->Config->HandlerTable[InterruptID]);
+ if (TablePtr != NULL) {
+ TablePtr->Handler(TablePtr->CallBackRef);
+ }
+
+IntrExit:
+ /*
+ * Write to the EOI register, we are all done here.
+ * Let this function return, the boot code will restore the stack.
+ */
+ XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+ /*
+ * Return from the interrupt. Change security domains could happen here.
+ */
+}
+/** @} */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic_sinit.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic_sinit.c
new file mode 100755
index 000000000..d30390ab8
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xscugic_sinit.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_sinit.c
+* @addtogroup scugic_v3_1
+* @{
+*
+* Contains static init functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg 01/19/10 First release
+* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_SCUGIC_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique identifier for a device.
+*
+* @return A pointer to the XScuGic configuration structure for the
+* specified device, or NULL if the device was not found.
+*
+* @note None.
+*
+******************************************************************************/
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId)
+{
+ XScuGic_Config *CfgPtr = NULL;
+ u32 Index;
+
+ for (Index=0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+ if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) {
+ CfgPtr = &XScuGic_ConfigTable[Index];
+ break;
+ }
+ }
+
+ return (XScuGic_Config *)CfgPtr;
+}
+/** @} */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xstatus.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xstatus.h
new file mode 100755
index 000000000..c4ed69426
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3/xstatus.h
@@ -0,0 +1,430 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xstatus.h
+ *
+ * This file contains Xilinx software status codes. Status codes have their
+ * own data type called int. These codes are used throughout the Xilinx
+ * device drivers.
+ *
+ ******************************************************************************/
+
+#ifndef XSTATUS_H /* prevent circular inclusions */
+#define XSTATUS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+// clang-format off
+#define XST_SUCCESS 0L
+#define XST_FAILURE 1L
+#define XST_DEVICE_NOT_FOUND 2L
+#define XST_DEVICE_BLOCK_NOT_FOUND 3L
+#define XST_INVALID_VERSION 4L
+#define XST_DEVICE_IS_STARTED 5L
+#define XST_DEVICE_IS_STOPPED 6L
+#define XST_FIFO_ERROR 7L /* an error occurred during an
+ operation with a FIFO such as
+ an underrun or overrun, this
+ error requires the device to
+ be reset */
+#define XST_RESET_ERROR 8L /* an error occurred which requires
+ the device to be reset */
+#define XST_DMA_ERROR 9L /* a DMA error occurred, this error
+ typically requires the device
+ using the DMA to be reset */
+#define XST_NOT_POLLED 10L /* the device is not configured for
+ polled mode operation */
+#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put
+ the specified data into */
+#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough
+ to hold the expected data */
+#define XST_NO_DATA 13L /* there was no data available */
+#define XST_REGISTER_ERROR 14L /* a register did not contain the
+ expected value */
+#define XST_INVALID_PARAM 15L /* an invalid parameter was passed
+ into the function */
+#define XST_NOT_SGDMA 16L /* the device is not configured for
+ scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */
+#define XST_NO_CALLBACK 18L /* a callback has not yet been
+ registered */
+#define XST_NO_FEATURE 19L /* device is not configured with
+ the requested feature */
+#define XST_NOT_INTERRUPT 20L /* device is not configured for
+ interrupt mode operation */
+#define XST_DEVICE_BUSY 21L /* device is busy */
+#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device
+ have maxed out */
+#define XST_IS_STARTED 23L /* used when part of device is
+ already started i.e.
+ sub channel */
+#define XST_IS_STOPPED 24L /* used when part of device is
+ already stopped i.e.
+ sub channel */
+#define XST_DATA_LOST 26L /* driver defined error */
+#define XST_RECV_ERROR 27L /* generic receive error */
+#define XST_SEND_ERROR 28L /* generic transmit error */
+#define XST_NOT_ENABLED 29L /* a requested service is not
+ available because it has not
+ been enabled */
+
+/***************** Utility Component statuses 401 - 500 *********************/
+
+#define XST_MEMTEST_FAILED 401L /* memory test failed */
+
+
+/***************** Common Components statuses 501 - 1000 *********************/
+
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */
+#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */
+#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value
+ was invalid after reset */
+#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting
+ * empty and full simultaneously
+ */
+
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer
+ failed */
+#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value
+ was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains
+ no buffer descriptors ready
+ to be processed */
+#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */
+#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of
+ the scatter gather list are
+ being used */
+#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer
+ descriptor which is to be
+ copied over in the scatter
+ list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been
+ put into the scatter gather
+ list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold
+ specified was larger than the
+ total # of buffer descriptors
+ in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has
+ already been created */
+#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has
+ been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was
+ being started was not committed
+ to the list */
+#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start
+ has already been used by the
+ hardware so it can't be reused
+ */
+#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access
+ error */
+#define XST_DMA_BD_ERROR 527L /* general buffer descriptor
+ error */
+
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width
+ was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at
+ reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status
+ register did not reset when
+ acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable
+ register was not updated when
+ other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt
+ status register did not read
+ back correctly */
+#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register
+ did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was
+ not updated correctly when other
+ registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending
+ register did not indicate the
+ expected value */
+#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register
+ did not indicate the expected
+ value */
+#define XST_IPIF_ERROR 541L /* generic ipif error */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough
+ * to hold the minimum number of
+ * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */
+#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late
+ * collision on polled send */
+
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR 1051L
+#define XST_UART_START_ERROR 1052L
+#define XST_UART_CONFIG_ERROR 1053L
+#define XST_UART_TEST_FAIL 1054L
+#define XST_UART_BAUD_ERROR 1055L
+#define XST_UART_BAUD_RANGE 1056L
+
+
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */
+#define XST_IIC_BUS_BUSY 1077 /* bus found busy */
+#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */
+ /* general call address */
+#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */
+ /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */
+ /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */
+ /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */
+ /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */
+ /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */
+ /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */
+ /* didn't return written value */
+#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */
+
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM
+ controller hit the max value
+ which requires the statistics
+ to be cleared */
+
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming
+ */
+#define XST_FLASH_READY 1127L /* Flash is ready for commands */
+#define XST_FLASH_ERROR 1128L /* Flash had detected an internal
+ error. Use XFlash_DeviceControl
+ to retrieve device specific codes
+ */
+#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state
+ */
+#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state
+ */
+#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by
+ driver */
+#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation
+ aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its
+ addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from
+ write/erase function with
+ XFL_NON_BLOCKING_WRITE/ERASE
+ option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */
+
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */
+#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */
+#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being
+ * selected */
+#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only
+ */
+#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */
+
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either
+ * one master assigned to two or more
+ * priorities, or one master not
+ * assigned to any priority
+ */
+#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the
+ * priority levels without first
+ * suspending the use of priority
+ * levels
+ */
+#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but
+ * bus parking was not enabled
+ */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed
+ * priority mode to allow the
+ * priorities to be changed
+ */
+
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */
+#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */
+
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */
+
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED 1251L
+
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST 1276L
+
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST 1301L
+
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST 1326L
+
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */
+
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS 1361L
+
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR 1400
+#define XST_FR_TX_BUSY 1401
+#define XST_FR_BUF_LOCKED 1402
+#define XST_FR_NO_BUF 1403
+
+/****************** USB constants 1410 - 1420 *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED 1410
+#define XST_USB_BUF_ALIGN_ERROR 1411
+#define XST_USB_NO_DESC_AVAILABLE 1412
+#define XST_USB_BUF_TOO_BIG 1413
+#define XST_USB_NO_BUF 1414
+
+/****************** HWICAP constants 1421 - 1429 *****************************/
+
+#define XST_HWICAP_WRITE_DONE 1421
+
+
+/****************** AXI VDMA constants 1430 - 1440 *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR 1430
+
+/*********************** NAND Flash statuses 1441 - 1459 *********************/
+
+#define XST_NAND_BUSY 1441L /* Flash is erasing or
+ * programming
+ */
+#define XST_NAND_READY 1442L /* Flash is ready for commands
+ */
+#define XST_NAND_ERROR 1443L /* Flash had detected an
+ * internal error.
+ */
+#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by
+ * driver
+ */
+#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported
+ */
+#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase
+ * operation aborted due to a
+ * timeout
+ */
+#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its
+ * addressible range
+ */
+#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error
+ */
+#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter
+ * page of the device
+ */
+#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error
+ */
+
+#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected
+ */
+
+// clang-format on
+
+/**************************** Type Definitions *******************************/
+
+typedef s32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/irq_numbers.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/imx6q-sabrelite/irq_numbers.h
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/irq_numbers.h
rename to Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/imx6q-sabrelite/irq_numbers.h
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/trap_common.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/imx6q-sabrelite/trap_common.c
similarity index 98%
rename from Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/trap_common.c
rename to Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/imx6q-sabrelite/trap_common.c
index ed78f4ce5..3e1acbc0d 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/trap_common.c
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/imx6q-sabrelite/trap_common.c
@@ -213,7 +213,7 @@ static int _is_interruptable(void)
return !(val & DIS_INT);
}
-static struct XiziTrapDriver xizi_trap_driver = (struct XiziTrapDriver) {
+static struct XiziTrapDriver xizi_trap_driver = {
.sys_irq_init = _sys_irq_init,
.cpu_irq_enable = _cpu_irq_enable,
@@ -235,6 +235,6 @@ static struct XiziTrapDriver xizi_trap_driver = (struct XiziTrapDriver) {
struct XiziTrapDriver* hardkernel_intr_init(struct TraceTag* hardkernel_tag)
{
xizi_trap_driver.sys_irq_init();
- xizi_trap_driver.cpu_irq_enable();
+ xizi_trap_driver.cpu_irq_disable();
return &xizi_trap_driver;
}
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/trampoline.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/trampoline.S
index e5dd6df1e..6ee8ba751 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/trampoline.S
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/trampoline.S
@@ -246,9 +246,9 @@ init_stack:
bic r2, r2, #ARM_CPSR_MODE_MASK
orr r2, r2, r0
msr cpsr_cxsf, r2
-
- # switch back to the SVC mode
mov sp, r1
+
+ @ # switch back to the SVC mode
bic r2, r2, #ARM_CPSR_MODE_MASK
orr r2, r2, #ARM_MODE_SVC
msr cpsr_cxsf, r2
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/zynq7000-zc702/irq_numbers.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/zynq7000-zc702/irq_numbers.h
new file mode 100644
index 000000000..3366ae6c7
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/zynq7000-zc702/irq_numbers.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ * http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+/**
+ * @file irq_numbers.c
+ * @brief irq numbers
+ * @version 3.0
+ * @author AIIT XUOS Lab
+ * @date 2024.03.04
+ */
+
+/*************************************************
+File name: irq_numbers.c
+Description: irq numbers
+Others:
+History:
+1. Date: 2024-03-04
+Author: AIIT XUOS Lab
+Modification:
+1. Add HW_NR_IRQS
+*************************************************/
+#pragma once
+
+#include "xparameters_ps.h"
+#include "xscugic_hw.h"
+
+#define HW_NR_IRQS XSCUGIC_MAX_NUM_INTR_INPUTS
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/zynq7000-zc702/trap_common.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/zynq7000-zc702/trap_common.c
new file mode 100644
index 000000000..4d06f20f4
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/zynq7000-zc702/trap_common.c
@@ -0,0 +1,242 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ * http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+/**
+ * @file trap_common.c
+ * @brief trap interface of hardkernel
+ * @version 3.0
+ * @author AIIT XUOS Lab
+ * @date 2023.08.25
+ */
+
+/*************************************************
+File name: trap_common.c
+Description: trap interface of hardkernel
+Others:
+History:
+1. Date: 2023-08-28
+Author: AIIT XUOS Lab
+Modification:
+1. first version
+*************************************************/
+#include
+
+#include "core.h"
+#include "trap_common.h"
+#include "xparameters.h"
+#include "xscugic.h"
+
+#include "log.h"
+
+extern void init_stack(uint32_t, uint32_t);
+extern void user_trap_swi_enter(void);
+extern void trap_iabort(void);
+extern void trap_dabort(void);
+extern void trap_irq_enter(void);
+extern void trap_undefined_instruction(void);
+
+static struct XiziTrapDriver xizi_trap_driver;
+
+void panic(char* s)
+{
+ xizi_trap_driver.cpu_irq_disable();
+ KPrintf("panic: %s\n", s);
+ for (;;)
+ ;
+}
+
+/* stack for different mode*/
+static char mode_stack_pages[NR_CPU][NR_MODE_STACKS][MODE_STACK_SIZE];
+
+extern uint32_t _vector_jumper;
+extern uint32_t _vector_start;
+extern uint32_t _vector_end;
+
+static XScuGic IntcInstance; /* Instance of the Interrupt Controller */
+
+void init_cpu_mode_stacks(int cpu_id)
+{
+ uint32_t modes[] = { ARM_MODE_FIQ, ARM_MODE_IRQ, ARM_MODE_ABT, ARM_MODE_UND };
+ // initialize the stacks for different mode
+ for (int i = 0; i < sizeof(modes) / sizeof(uint32_t); i++) {
+ memset(mode_stack_pages[cpu_id][i], 0, MODE_STACK_SIZE);
+ init_stack(modes[i], (uint32_t)mode_stack_pages[cpu_id][i]);
+ }
+}
+
+void handle_reserved(void)
+{
+ // unimplemented trap handler
+ LOG("Unimplemented Reserved\n");
+ panic("");
+}
+
+void handle_fiq(void)
+{
+ LOG("Unimplemented FIQ\n");
+ panic("");
+}
+
+static void _sys_irq_init()
+{
+ /* load exception vectors */
+ volatile uint32_t* vector_base = &_vector_start;
+
+ // Set Interrupt handler start address
+ vector_base[1] = (uint32_t)trap_undefined_instruction; // Undefined Instruction
+ vector_base[2] = (uint32_t)user_trap_swi_enter; // Software Interrupt
+ vector_base[3] = (uint32_t)trap_iabort; // Prefetch Abort
+ vector_base[4] = (uint32_t)trap_dabort; // Data Abort
+ vector_base[5] = (uint32_t)handle_reserved; // Reserved
+ vector_base[6] = (uint32_t)trap_irq_enter; // IRQ
+ vector_base[7] = (uint32_t)handle_fiq; // FIQ
+
+ init_cpu_mode_stacks(0);
+
+ /* active hardware irq responser */
+ XScuGic_Config* gic_config = XScuGic_LookupConfig(XPAR_PS7_SCUGIC_0_DEVICE_ID);
+ if (NULL == gic_config) {
+ ERROR("Error while looking up gic config\n");
+ return;
+ }
+ int gic_init_status = XScuGic_CfgInitialize(&IntcInstance, gic_config, gic_config->CpuBaseAddress);
+ if (gic_init_status != XST_SUCCESS) {
+ ERROR("Error initializing gic\n");
+ return;
+ }
+
+ xizi_trap_driver.switch_hw_irqtbl((uint32_t*)&_vector_jumper);
+}
+
+static void _cpu_irq_enable(void)
+{
+ // Xil_ExceptionEnable();
+ arm_set_interrupt_state(true);
+}
+
+static void _cpu_irq_disable(void)
+{
+ // Xil_ExceptionDisable();
+ arm_set_interrupt_state(false);
+}
+
+static void _single_irq_enable(int irq, int cpu, int prio)
+{
+ XScuGic_Enable(&IntcInstance, irq);
+}
+
+static void _single_irq_disable(int irq, int cpu)
+{
+ XScuGic_Disable(&IntcInstance, irq);
+}
+
+#define VBAR
+static inline uint32_t* _switch_hw_irqtbl(uint32_t* new_tbl_base)
+{
+ // get old irq table base addr
+ uint32_t old_tbl_base = 0;
+ _ARM_MRC(15, 0, old_tbl_base, 12, 0, 0);
+
+ // set new irq table base addr
+ _ARM_MCR(15, 0, new_tbl_base, 12, 0, 0);
+
+ // set sctlr to use VBAR
+ uint32_t sctlr = 0;
+ _ARM_MRC(15, 0, sctlr, 1, 0, 0);
+ sctlr &= ~(1 << 13);
+ _ARM_MCR(15, 0, sctlr, 1, 0, 0);
+
+ return (uint32_t*)old_tbl_base;
+}
+
+static void _bind_irq_handler(int irq, irq_handler_t handler)
+{
+ xizi_trap_driver.sw_irqtbl[irq].handler = handler;
+}
+
+static bool _send_sgi(uint32_t irq, uint32_t bitmask, enum SgiFilterType type)
+{
+ if (bitmask > (1 << NR_CPU) - 1) {
+ return false;
+ }
+
+ int cpu_id = 0;
+ while (bitmask != 0) {
+ if ((bitmask & 0x1) != 0) {
+ XScuGic_SoftwareIntr(&IntcInstance, irq, cpu_id);
+ }
+ cpu_id++;
+ bitmask >>= 1;
+ }
+
+ return true;
+}
+
+static uint32_t _hw_before_irq()
+{
+
+ uint32_t IntIDFull = XScuGic_CPUReadReg(&IntcInstance, XSCUGIC_INT_ACK_OFFSET);
+ return IntIDFull;
+}
+
+static uint32_t _hw_cur_int_num(uint32_t int_info)
+{
+ return int_info & XSCUGIC_ACK_INTID_MASK;
+}
+
+static uint32_t _hw_cur_int_cpu(uint32_t int_info)
+{
+ return (int_info >> 5) & 0x3;
+}
+
+static void _hw_after_irq(uint32_t int_info)
+{
+ XScuGic_CPUWriteReg(&IntcInstance, XSCUGIC_EOI_OFFSET, int_info);
+}
+
+static int _is_interruptable(void)
+{
+ uint32_t val;
+
+ __asm__ __volatile__(
+ "mrs %0, cpsr"
+ : "=r"(val)
+ :
+ :);
+
+ return !(val & DIS_INT);
+}
+
+static struct XiziTrapDriver xizi_trap_driver = {
+ .sys_irq_init = _sys_irq_init,
+
+ .cpu_irq_enable = _cpu_irq_enable,
+ .cpu_irq_disable = _cpu_irq_disable,
+ .single_irq_enable = _single_irq_enable,
+ .single_irq_disable = _single_irq_disable,
+ .switch_hw_irqtbl = _switch_hw_irqtbl,
+
+ .bind_irq_handler = _bind_irq_handler,
+ .send_sgi = _send_sgi,
+
+ .is_interruptable = _is_interruptable,
+ .hw_before_irq = _hw_before_irq,
+ .hw_cur_int_num = _hw_cur_int_num,
+ .hw_cur_int_cpu = _hw_cur_int_cpu,
+ .hw_after_irq = _hw_after_irq,
+};
+
+struct XiziTrapDriver* hardkernel_intr_init(struct TraceTag* hardkernel_tag)
+{
+ xizi_trap_driver.sys_irq_init();
+ xizi_trap_driver.cpu_irq_enable();
+ return &xizi_trap_driver;
+}
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/zynq7000-zc702/xil_assert.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/zynq7000-zc702/xil_assert.c
new file mode 100755
index 000000000..6b940e103
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/cortex-a9/zynq7000-zc702/xil_assert.c
@@ -0,0 +1,145 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xil_assert.c
+ *
+ * This file contains basic assert related functions for Xilinx software IP.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a hbm 07/14/09 Initial release
+ *
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_assert.h"
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/**
+ * This variable allows testing to be done easier with asserts. An assert
+ * sets this variable such that a driver can evaluate this variable
+ * to determine if an assert occurred.
+ */
+u32 Xil_AssertStatus;
+
+/**
+ * This variable allows the assert functionality to be changed for testing
+ * such that it does not wait infinitely. Use the debugger to disable the
+ * waiting during testing of asserts.
+ */
+/*s32 Xil_AssertWait = 1*/
+
+/* The callback function to be invoked when an assert is taken */
+static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * Implement assert. Currently, it calls a user-defined callback function
+ * if one has been set. Then, it potentially enters an infinite loop depending
+ * on the value of the Xil_AssertWait variable.
+ *
+ * @param file is the name of the filename of the source
+ * @param line is the linenumber within File
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+void Xil_Assert(const char8* File, s32 Line)
+{
+ s32 Xil_AssertWait = 1;
+ /* if the callback has been set then invoke it */
+ if (Xil_AssertCallbackRoutine != 0) {
+ (*Xil_AssertCallbackRoutine)(File, Line);
+ }
+
+ /* if specified, wait indefinitely such that the assert will show up
+ * in testing
+ */
+ while (Xil_AssertWait != 0) {
+ }
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Set up a callback function to be invoked when an assert occurs. If there
+ * was already a callback installed, then it is replaced.
+ *
+ * @param routine is the callback to be invoked when an assert is taken
+ *
+ * @return None.
+ *
+ * @note This function has no effect if NDEBUG is set
+ *
+ ******************************************************************************/
+void Xil_AssertSetCallback(Xil_AssertCallback Routine)
+{
+ Xil_AssertCallbackRoutine = Routine;
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Null handler function. This follows the XInterruptHandler signature for
+ * interrupt handlers. It can be used to assign a null handler (a stub) to an
+ * interrupt controller vector table.
+ *
+ * @param NullParameter is an arbitrary void pointer and not used.
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+void XNullHandler(void* NullParameter)
+{
+}
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/Makefile
index cbe95fadd..07901e1e9 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/Makefile
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/Makefile
@@ -1,4 +1,4 @@
-SRC_DIR := src
+SRC_FILES := bootmmu.c mmu.c pagetable_attr.c
include $(KERNEL_ROOT)/compiler.mk
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/src/bootmmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/bootmmu.c
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/src/bootmmu.c
rename to Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/bootmmu.c
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/memlayout.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/imx6q-sabrelite/memlayout.h
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/include/memlayout.h
rename to Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/imx6q-sabrelite/memlayout.h
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/src/mmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/mmu.c
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/src/mmu.c
rename to Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/mmu.c
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/src/pagetable_attr.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/pagetable_attr.c
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/src/pagetable_attr.c
rename to Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/pagetable_attr.c
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/src/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/src/Makefile
deleted file mode 100644
index 07901e1e9..000000000
--- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/src/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-SRC_FILES := bootmmu.c mmu.c pagetable_attr.c
-
-include $(KERNEL_ROOT)/compiler.mk
-
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/zynq7000-zc702/memlayout.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/zynq7000-zc702/memlayout.h
new file mode 100644
index 000000000..f68861da0
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv7-a/cortex-a9/zynq7000-zc702/memlayout.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ * http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+
+/**
+ * @file memlayout.h
+ * @brief virtual memory and physical memory layout
+ * @version 1.0
+ * @author AIIT XUOS Lab
+ * @date 2024-01-25
+ */
+/*************************************************
+File name: memlayout.h
+Description: virtual memory and physical memory layout
+Others:
+History:
+1. Date: 2023-08-28
+Author: AIIT XUOS Lab
+Modification:
+1. first version
+*************************************************/
+#pragma once
+
+// Memory layout
+// clang-format off
+
+#define ARCH_BIT 32
+
+/* A9 physical memory layout */
+#define PHY_MEM_BASE (0x00100000)
+#define PHY_USER_FREEMEM_BASE (0x20000000)
+#define PHY_USER_FREEMEM_TOP (0x3FF00000)
+#define PHY_MEM_STOP (0x3FF00000)
+
+/* PTE-PAGE_SIZE */
+#define LEVEL4_PTE_SHIFT 12
+#define LEVEL4_PTE_SIZE (1 << LEVEL4_PTE_SHIFT)
+
+/* PDE-SECTION_SIZE */
+#define LEVEL3_PDE_SHIFT 20
+#define LEVEL3_PDE_SIZE (1 << LEVEL3_PDE_SHIFT)
+
+#define NUM_LEVEL3_PDE (1 << (ARCH_BIT - LEVEL3_PDE_SHIFT)) // how many PTE in a PT
+#define NUM_LEVEL4_PTE (1 << (LEVEL3_PDE_SHIFT - LEVEL4_PTE_SHIFT)) // how many PTE in a PT
+#define NUM_TOPLEVEL_PDE NUM_LEVEL3_PDE
+
+#define PAGE_SIZE LEVEL4_PTE_SIZE
+#define MAX_NR_FREE_PAGES ((PHY_MEM_STOP - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT)
+
+/* User memory layout */
+#define USER_STACK_SIZE PAGE_SIZE
+#define USER_MEM_BASE (0x00000000)
+#define USER_MEM_TOP DEV_VRTMEM_BASE
+#define USER_IPC_SPACE_BASE (0x70000000)
+#define USER_IPC_SPACE_TOP (USER_MEM_TOP - USER_STACK_SIZE)
+
+/* Deivce memory layout */
+#define DEV_PHYMEM_BASE (0xE0000000)
+#define DEV_VRTMEM_BASE (0x80000000)
+#define DEV_MEM_SZ (0x1FFFFFFF)
+
+/* Kernel memory layout */
+#define KERN_MEM_BASE (0xA0000000) // First kernel virtual address
+#define KERN_OFFSET (KERN_MEM_BASE - PHY_MEM_BASE)
+
+// clang-format on
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/Makefile
index 064e25a56..0b899a28b 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/Makefile
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/Makefile
@@ -1,3 +1,3 @@
-SRC_DIR := uart_io_for_imx6q_sabrelite
+SRC_DIR := uart_io_for_$(BOARD)
include $(KERNEL_ROOT)/compiler.mk
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/Makefile
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/Makefile
rename to Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/Makefile
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/imx_uart.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/imx_uart.c
similarity index 92%
rename from Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/imx_uart.c
rename to Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/imx_uart.c
index d86045f0b..56012fc25 100755
--- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/imx_uart.c
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/imx_uart.c
@@ -59,17 +59,17 @@ Modification:
static void UartInitGpio(void)
{
- /* UART1 TXD */
- mxc_iomux_v3_setup_pad(MX6Q_PAD_SD3_DAT6__UART1_TXD);
+ /* UART1 TXD */
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_SD3_DAT6__UART1_TXD);
- /* UART1 RXD */
- mxc_iomux_v3_setup_pad(MX6Q_PAD_SD3_DAT7__UART1_RXD);
+ /* UART1 RXD */
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_SD3_DAT7__UART1_RXD);
- /* UART2 TXD */
- mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D26__UART2_TXD);
+ /* UART2 TXD */
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D26__UART2_TXD);
- /* UART2 RXD */
- mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D27__UART2_RXD);
+ /* UART2 RXD */
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D27__UART2_RXD);
}
static uint32_t GetUartClk(void)
@@ -131,13 +131,13 @@ __attribute__((__always_inline__)) static inline uint8_t UartGetCharInstance(uin
if (!(HW_UART_USR2(instance).B.RDR))
return 0xFF;
- read_data = HW_UART_URXD_RD(instance);
+ read_data = HW_UART_URXD_RD(instance);
/* If error are detected */
if (read_data & 0x7C00)
return 0xFF;
- return (uint8_t) read_data;
+ return (uint8_t)read_data;
}
__attribute__((__always_inline__)) static inline uint32_t UartGetIrqnumInstance(uint32_t instance)
@@ -177,7 +177,7 @@ static uint32_t UartGetIrqnum()
}
/// @todo make this static
-static struct XiziSerialDriver hardkernel_serial_driver = (struct XiziSerialDriver) {
+static struct XiziSerialDriver hardkernel_serial_driver = {
.sys_serial_init = UartInit,
.get_serial_irqnum = UartGetIrqnum,
.putc = UartPutChar,
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/include/crm_regs.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/include/crm_regs.h
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/include/crm_regs.h
rename to Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/include/crm_regs.h
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/include/imx_uart.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/include/imx_uart.h
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/include/imx_uart.h
rename to Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/include/imx_uart.h
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/include/iomux_v3.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/include/iomux_v3.h
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/include/iomux_v3.h
rename to Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/include/iomux_v3.h
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/include/regs_pins.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/include/regs_pins.h
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/include/regs_pins.h
rename to Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/include/regs_pins.h
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/include/regsuart.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/include/regsuart.h
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/include/regsuart.h
rename to Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/include/regsuart.h
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/iomux_v3.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/iomux_v3.c
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/iomux_v3.c
rename to Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q-sabrelite/iomux_v3.c
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/Makefile
new file mode 100644
index 000000000..2bb51eb7b
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/Makefile
@@ -0,0 +1,3 @@
+SRC_FILES := xil_uart.c xil_io.c
+
+include $(KERNEL_ROOT)/compiler.mk
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/include/xil_io.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/include/xil_io.h
new file mode 100755
index 000000000..83a0af224
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/include/xil_io.h
@@ -0,0 +1,244 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xil_io.h
+ *
+ * This file contains the interface for the general IO component, which
+ * encapsulates the Input/Output functions for processors that do not
+ * require any special I/O handling.
+ *
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- -------- -------- -----------------------------------------------
+ * 1.00a ecm/sdm 10/24/09 First release
+ * 1.00a sdm 07/21/10 Added Xil_Htonl/s, Xil_Ntohl/s
+ * 3.07a asa 08/31/12 Added xil_printf.h include
+ * 3.08a sgd 11/05/12 Reverted SYNC macros definitions
+ *
+ ******************************************************************************/
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#if defined __GNUC__
+#define SYNCHRONIZE_IO dmb()
+#define INST_SYNC isb()
+#define DATA_SYNC dsb()
+#else
+#define SYNCHRONIZE_IO
+#define INST_SYNC
+#define DATA_SYNC
+#endif /* __GNUC__ */
+
+/*****************************************************************************/
+/**
+ *
+ * Perform an big-endian input operation for a 16-bit memory location
+ * by reading from the specified address and returning the Value read from
+ * that address.
+ *
+ * @param Addr contains the address to perform the input operation at.
+ *
+ * @return The Value read from the specified input address with the
+ * proper endianness. The return Value has the same endianness
+ * as that of the processor, i.e. if the processor is
+ * little-engian, the return Value is the byte-swapped Value read
+ * from the address.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+#define Xil_In16LE(Addr) Xil_In16((Addr))
+
+/*****************************************************************************/
+/**
+ *
+ * Perform a big-endian input operation for a 32-bit memory location
+ * by reading from the specified address and returning the Value read from
+ * that address.
+ *
+ * @param Addr contains the address to perform the input operation at.
+ *
+ * @return The Value read from the specified input address with the
+ * proper endianness. The return Value has the same endianness
+ * as that of the processor, i.e. if the processor is
+ * little-engian, the return Value is the byte-swapped Value read
+ * from the address.
+ *
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+#define Xil_In32LE(Addr) Xil_In32((Addr))
+
+/*****************************************************************************/
+/**
+ *
+ * Perform a big-endian output operation for a 16-bit memory location
+ * by writing the specified Value to the specified address.
+ *
+ * @param Addr contains the address to perform the output operation at.
+ * @param Value contains the Value to be output at the specified address.
+ * The Value has the same endianness as that of the processor.
+ * If the processor is little-endian, the byte-swapped Value is
+ * written to the address.
+ *
+ *
+ * @return None
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value))
+
+/*****************************************************************************/
+/**
+ *
+ * Perform a big-endian output operation for a 32-bit memory location
+ * by writing the specified Value to the specified address.
+ *
+ * @param Addr contains the address to perform the output operation at.
+ * @param Value contains the Value to be output at the specified address.
+ * The Value has the same endianness as that of the processor.
+ * If the processor is little-endian, the byte-swapped Value is
+ * written to the address.
+ *
+ * @return None
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value))
+
+/*****************************************************************************/
+/**
+ *
+ * Convert a 32-bit number from host byte order to network byte order.
+ *
+ * @param Data the 32-bit number to be converted.
+ *
+ * @return The converted 32-bit number in network byte order.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+#define Xil_Htonl(Data) Xil_EndianSwap32((Data))
+
+/*****************************************************************************/
+/**
+ *
+ * Convert a 16-bit number from host byte order to network byte order.
+ *
+ * @param Data the 16-bit number to be converted.
+ *
+ * @return The converted 16-bit number in network byte order.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+#define Xil_Htons(Data) Xil_EndianSwap16((Data))
+
+/*****************************************************************************/
+/**
+ *
+ * Convert a 32-bit number from network byte order to host byte order.
+ *
+ * @param Data the 32-bit number to be converted.
+ *
+ * @return The converted 32-bit number in host byte order.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+#define Xil_Ntohl(Data) Xil_EndianSwap32((Data))
+
+/*****************************************************************************/
+/**
+ *
+ * Convert a 16-bit number from network byte order to host byte order.
+ *
+ * @param Data the 16-bit number to be converted.
+ *
+ * @return The converted 16-bit number in host byte order.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+#define Xil_Ntohs(Data) Xil_EndianSwap16((Data))
+
+/************************** Function Prototypes ******************************/
+
+/* The following functions allow the software to be transportable across
+ * processors which may use memory mapped I/O or I/O which is mapped into a
+ * seperate address space.
+ */
+u8 Xil_In8(INTPTR Addr);
+u16 Xil_In16(INTPTR Addr);
+u32 Xil_In32(INTPTR Addr);
+
+void Xil_Out8(INTPTR Addr, u8 Value);
+void Xil_Out16(INTPTR Addr, u16 Value);
+void Xil_Out32(INTPTR Addr, u32 Value);
+
+u16 Xil_In16BE(INTPTR Addr);
+u32 Xil_In32BE(INTPTR Addr);
+void Xil_Out16BE(INTPTR Addr, u16 Value);
+void Xil_Out32BE(INTPTR Addr, u32 Value);
+
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/include/xpseudo_asm.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/include/xpseudo_asm.h
new file mode 100755
index 000000000..29298617c
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/include/xpseudo_asm.h
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* This header file contains macros for using inline assembler code.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm 10/18/09 First release
+* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
+*
+*
+******************************************************************************/
+#ifndef XPSEUDO_ASM_H
+#define XPSEUDO_ASM_H
+
+#include "xreg_cortexa9.h"
+#ifdef __GNUC__
+ #include "xpseudo_asm_gcc.h"
+#elif defined (__ICCARM__)
+ #include "xpseudo_asm_iccarm.h"
+#else
+ #include "xpseudo_asm_rvct.h"
+#endif
+
+#endif /* XPSEUDO_ASM_H */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/include/xpseudo_asm_gcc.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/include/xpseudo_asm_gcc.h
new file mode 100755
index 000000000..9b34a008e
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/include/xpseudo_asm_gcc.h
@@ -0,0 +1,175 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm 10/28/09 First release
+*
+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s) tostring(s)
+#define tostring(s) #s
+
+/* pseudo assembler instructions */
+#define mfcpsr() ({u32 rval; \
+ __asm__ __volatile__(\
+ "mrs %0, cpsr\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+#define mtcpsr(v) __asm__ __volatile__(\
+ "msr cpsr,%0\n"\
+ : : "r" (v)\
+ )
+
+#define cpsiei() __asm__ __volatile__("cpsie i\n")
+#define cpsidi() __asm__ __volatile__("cpsid i\n")
+
+#define cpsief() __asm__ __volatile__("cpsie f\n")
+#define cpsidf() __asm__ __volatile__("cpsid f\n")
+
+
+
+#define mtgpr(rn, v) __asm__ __volatile__(\
+ "mov r" stringify(rn) ", %0 \n"\
+ : : "r" (v)\
+ )
+
+#define mfgpr(rn) ({u32 rval; \
+ __asm__ __volatile__(\
+ "mov %0,r" stringify(rn) "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr) ({u32 rval; \
+ __asm__ __volatile__(\
+ "ldr %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define ldrb(adr) ({u8 rval; \
+ __asm__ __volatile__(\
+ "ldrb %0,[%1]"\
+ : "=r" (rval) : "r" (adr)\
+ );\
+ rval;\
+ })
+
+#define str(adr, val) __asm__ __volatile__(\
+ "str %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+#define strb(adr, val) __asm__ __volatile__(\
+ "strb %0,[%1]\n"\
+ : : "r" (val), "r" (adr)\
+ )
+
+/* Count leading zeroes (clz) */
+#define clz(arg) ({u8 rval; \
+ __asm__ __volatile__(\
+ "clz %0,%1"\
+ : "=r" (rval) : "r" (arg)\
+ );\
+ rval;\
+ })
+
+/* CP15 operations */
+#define mtcp(rn, v) __asm__ __volatile__(\
+ "mcr " rn "\n"\
+ : : "r" (v)\
+ );
+
+#define mfcp(rn) ({u32 rval; \
+ __asm__ __volatile__(\
+ "mrc " rn "\n"\
+ : "=r" (rval)\
+ );\
+ rval;\
+ })
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/include/xreg_cortexa9.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/include/xreg_cortexa9.h
new file mode 100755
index 000000000..dc9a4ebd2
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/include/xreg_cortexa9.h
@@ -0,0 +1,591 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexa9.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU, ARMCC compiler.
+*
+* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+*
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm 10/20/09 First release
+*
+*
+******************************************************************************/
+#ifndef XREG_CORTEXA9_H
+#define XREG_CORTEXA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPRs */
+#define XREG_GPR0 r0
+#define XREG_GPR1 r1
+#define XREG_GPR2 r2
+#define XREG_GPR3 r3
+#define XREG_GPR4 r4
+#define XREG_GPR5 r5
+#define XREG_GPR6 r6
+#define XREG_GPR7 r7
+#define XREG_GPR8 r8
+#define XREG_GPR9 r9
+#define XREG_GPR10 r10
+#define XREG_GPR11 r11
+#define XREG_GPR12 r12
+#define XREG_GPR13 r13
+#define XREG_GPR14 r14
+#define XREG_GPR15 r15
+#define XREG_CPSR cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0 0
+#define XREG_CP1 1
+#define XREG_CP2 2
+#define XREG_CP3 3
+#define XREG_CP4 4
+#define XREG_CP5 5
+#define XREG_CP6 6
+#define XREG_CP7 7
+#define XREG_CP8 8
+#define XREG_CP9 9
+#define XREG_CP10 10
+#define XREG_CP11 11
+#define XREG_CP12 12
+#define XREG_CP13 13
+#define XREG_CP14 14
+#define XREG_CP15 15
+
+/* Coprocessor control register defines */
+#define XREG_CR0 cr0
+#define XREG_CR1 cr1
+#define XREG_CR2 cr2
+#define XREG_CR3 cr3
+#define XREG_CR4 cr4
+#define XREG_CR5 cr5
+#define XREG_CR6 cr6
+#define XREG_CR7 cr7
+#define XREG_CR8 cr8
+#define XREG_CR9 cr9
+#define XREG_CR10 cr10
+#define XREG_CR11 cr11
+#define XREG_CR12 cr12
+#define XREG_CR13 cr13
+#define XREG_CR14 cr14
+#define XREG_CR15 cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE 0x20
+#define XREG_CPSR_MODE_BITS 0x1F
+#define XREG_CPSR_SYSTEM_MODE 0x1F
+#define XREG_CPSR_UNDEFINED_MODE 0x1B
+#define XREG_CPSR_DATA_ABORT_MODE 0x17
+#define XREG_CPSR_SVC_MODE 0x13
+#define XREG_CPSR_IRQ_MODE 0x12
+#define XREG_CPSR_FIQ_MODE 0x11
+#define XREG_CPSR_USER_MODE 0x10
+
+#define XREG_CPSR_IRQ_ENABLE 0x80
+#define XREG_CPSR_FIQ_ENABLE 0x40
+
+#define XREG_CPSR_N_BIT 0x80000000
+#define XREG_CPSR_Z_BIT 0x40000000
+#define XREG_CPSR_C_BIT 0x20000000
+#define XREG_CPSR_V_BIT 0x10000000
+
+
+/* CP15 defines */
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
+#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
+#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
+
+#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
+#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
+
+#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
+#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
+#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
+#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
+#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
+
+#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
+#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
+#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
+
+#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
+#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
+#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
+
+#else /* RVCT */
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
+#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
+#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
+#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
+#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
+
+#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
+#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
+#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
+#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
+#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
+#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
+#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
+
+#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
+#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
+#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
+#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
+#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
+
+#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
+#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
+#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
+
+#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
+#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
+#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
+
+#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
+#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
+#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
+#endif
+
+/* XREG_CP15_CONTROL bit defines */
+#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
+#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
+#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
+#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
+#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
+#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
+#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
+#define XREG_CP15_CONTROL_V_BIT 0x00002000U
+#define XREG_CP15_CONTROL_I_BIT 0x00001000U
+#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
+#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
+#define XREG_CP15_CONTROL_B_BIT 0x00000080U
+#define XREG_CP15_CONTROL_C_BIT 0x00000004U
+#define XREG_CP15_CONTROL_A_BIT 0x00000002U
+#define XREG_CP15_CONTROL_M_BIT 0x00000001U
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
+#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
+#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
+
+#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
+
+#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
+
+#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
+#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
+#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
+#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
+#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
+#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
+#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
+#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
+
+#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
+
+#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
+#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
+
+#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
+#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
+#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
+#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
+#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
+#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
+
+#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
+#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
+
+#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
+
+#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
+
+#else
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
+#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
+#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
+#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
+#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP "cp15:0:c7:c0:4"
+
+#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
+
+#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
+
+#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
+#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
+#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
+#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
+#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
+#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
+#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
+
+#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
+#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
+#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
+#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
+#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
+#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
+#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
+#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
+#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
+#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
+#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
+#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
+#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
+#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
+#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
+#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
+
+#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
+#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
+#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
+
+#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
+#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
+
+#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
+#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
+#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
+#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
+#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
+#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
+
+#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
+#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
+
+#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
+
+#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
+
+#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
+#endif
+
+
+/* MPE register definitions */
+#define XREG_FPSID c0
+#define XREG_FPSCR c1
+#define XREG_MVFR1 c6
+#define XREG_MVFR0 c7
+#define XREG_FPEXC c8
+#define XREG_FPINST c9
+#define XREG_FPINST2 c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT (24)
+#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE (1<<23)
+#define XREG_FPSID_ARCH_BIT (16)
+#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT (8)
+#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT (4)
+#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT (0)
+#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT (1 << 31)
+#define XREG_FPSCR_Z_BIT (1 << 30)
+#define XREG_FPSCR_C_BIT (1 << 29)
+#define XREG_FPSCR_V_BIT (1 << 28)
+#define XREG_FPSCR_QC (1 << 27)
+#define XREG_FPSCR_AHP (1 << 26)
+#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
+#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
+#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
+#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
+#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
+#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
+#define XREG_FPSCR_RMODE_BIT (22)
+#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT (20)
+#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT (16)
+#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC (1 << 7)
+#define XREG_FPSCR_IXC (1 << 4)
+#define XREG_FPSCR_UFC (1 << 3)
+#define XREG_FPSCR_OFC (1 << 2)
+#define XREG_FPSCR_DZC (1 << 1)
+#define XREG_FPSCR_IOC (1 << 0)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT (28)
+#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT (24)
+#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT (20)
+#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT (16)
+#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT (12)
+#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT (8)
+#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT (4)
+#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT (0)
+#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX (1 << 31)
+#define XREG_FPEXC_EN (1 << 30)
+#define XREG_FPEXC_DEX (1 << 29)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXA9_H */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/include/xuartps_hw.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/include/xuartps_hw.h
new file mode 100644
index 000000000..bed889aa4
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/include/xuartps_hw.h
@@ -0,0 +1,439 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xuartps_hw.h
+ * @addtogroup uartps_v3_1
+ * @{
+ *
+ * This header file contains the hardware interface of an XUartPs device.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ------ -------- ----------------------------------------------
+ * 1.00 drg/jz 01/12/10 First Release
+ * 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
+ * and XUARTPS_IXR_TTRIG.
+ * Modified the names of these defines
+ * XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+ * XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+ * XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+ * XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+ * 1.05a hk 08/22/13 Added prototype for uart reset and related
+ * constant definitions.
+ * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.1 kvn 04/10/15 Modified code for latest RTL changes.
+ *
+ *
+ *
+ ******************************************************************************/
+#ifndef XUARTPS_HW_H /* prevent circular inclusions */
+#define XUARTPS_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the UART.
+ * @{
+ */
+#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
+#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
+#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
+#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
+#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
+#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
+#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
+/* @}*/
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
+#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
+#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
+/* @} */
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
+#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
+#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK 0x00001FFFU /**< Valid bit mask */
+/* @} */
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
+#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
+#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
+/* @} */
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
+#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
+#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Transmit FIFO Trigger Level Register
+ *
+ * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
+ * which the TX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
+#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMCR_FCM 0x00000010U /**< Flow control mode */
+#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
+#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
+#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
+#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
+#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
+#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
+#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
+#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
+#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
+#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
+#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
+#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
+#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
+/* @} */
+
+/** @name Receiver FIFO Byte Status Register
+ *
+ * The Receiver FIFO Status register is used to have a continuous
+ * monitoring of the raw unmasked byte status information. The register
+ * contains frame, parity and break status information for the top
+ * four bytes in the RX FIFO.
+ *
+ * Receiver FIFO Byte Status Register Bit Definition
+ * @{
+ */
+#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
+#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
+#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
+#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
+#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
+#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
+#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
+#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
+#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
+#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
+#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
+#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
+#define XUARTPS_RXBS_MASK 0x00000FFFU /**< 24 bit RX byte status mask */
+/* @} */
+
+/*
+ * Defines for backwards compatabilty, will be removed
+ * in the next version of the driver
+ */
+#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
+#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
+#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
+#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+ * Read a UART register.
+ *
+ * @param BaseAddress contains the base address of the device.
+ * @param RegOffset contains the offset from the base address of the
+ * device.
+ *
+ * @return The value read from the register.
+ *
+ * @note C-Style signature:
+ * u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
+ *
+ ******************************************************************************/
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+ * Write a UART register.
+ *
+ * @param BaseAddress contains the base address of the device.
+ * @param RegOffset contains the offset from the base address of the
+ * device.
+ * @param RegisterValue is the value to be written to the register.
+ *
+ * @return None.
+ *
+ * @note C-Style signature:
+ * void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
+ * u16 RegisterValue)
+ *
+ ******************************************************************************/
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+ * Determine if there is receive data in the receiver and/or FIFO.
+ *
+ * @param BaseAddress contains the base address of the device.
+ *
+ * @return TRUE if there is receive data, FALSE otherwise.
+ *
+ * @note C-Style signature:
+ * u32 XUartPs_IsReceiveData(u32 BaseAddress)
+ *
+ ******************************************************************************/
+#define XUartPs_IsReceiveData(BaseAddress) \
+ !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+ * Determine if a byte of data can be sent with the transmitter.
+ *
+ * @param BaseAddress contains the base address of the device.
+ *
+ * @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+ * FIFO.
+ *
+ * @note C-Style signature:
+ * u32 XUartPs_IsTransmitFull(u32 BaseAddress)
+ *
+ ******************************************************************************/
+#define XUartPs_IsTransmitFull(BaseAddress) \
+ ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
+
+/************************** Function Prototypes ******************************/
+
+void XUartPs_SendByte(u32 BaseAddress, u8 Data);
+
+u8 XUartPs_RecvByte(u32 BaseAddress);
+
+void XUartPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/xil_io.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/xil_io.c
new file mode 100755
index 000000000..b8e4c0485
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/xil_io.c
@@ -0,0 +1,342 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xil_io.c
+ *
+ * Contains I/O functions for memory-mapped or non-memory-mapped I/O
+ * architectures. These functions encapsulate Cortex A9 architecture-specific
+ * I/O requirements.
+ *
+ * @note
+ *
+ * This file contains architecture-dependent code.
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- -------- -------- -----------------------------------------------
+ * 1.00a ecm/sdm 10/24/09 First release
+ * 3.06a sgd 05/15/12 Pointer volatile used for the all read functions
+ * 3.07a sgd 08/17/12 Removed barriers (SYNCHRONIZE_IO) calls.
+ * 3.09a sgd 02/05/13 Comments cleanup
+ *
+ ******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#include "xreg_cortexa9.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * Performs an input operation for an 8-bit memory location by reading from the
+ * specified address and returning the Value read from that address.
+ *
+ * @param Addr contains the address to perform the input operation
+ * at.
+ *
+ * @return The Value read from the specified input address.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+u8 Xil_In8(INTPTR Addr)
+{
+ return *(volatile u8*)Addr;
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Performs an input operation for a 16-bit memory location by reading from the
+ * specified address and returning the Value read from that address.
+ *
+ * @param Addr contains the address to perform the input operation
+ * at.
+ *
+ * @return The Value read from the specified input address.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+u16 Xil_In16(INTPTR Addr)
+{
+ return *(volatile u16*)Addr;
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Performs an input operation for a 32-bit memory location by reading from the
+ * specified address and returning the Value read from that address.
+ *
+ * @param Addr contains the address to perform the input operation
+ * at.
+ *
+ * @return The Value read from the specified input address.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+u32 Xil_In32(INTPTR Addr)
+{
+ return *(volatile u32*)Addr;
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Performs an output operation for an 8-bit memory location by writing the
+ * specified Value to the the specified address.
+ *
+ * @param Addr contains the address to perform the output operation
+ * at.
+ * @param Value contains the Value to be output at the specified address.
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+void Xil_Out8(INTPTR Addr, u8 Value)
+{
+ u8* LocalAddr = (u8*)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Performs an output operation for a 16-bit memory location by writing the
+ * specified Value to the the specified address.
+ *
+ * @param Addr contains the address to perform the output operation
+ * at.
+ * @param Value contains the Value to be output at the specified address.
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+void Xil_Out16(INTPTR Addr, u16 Value)
+{
+ u16* LocalAddr = (u16*)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Performs an output operation for a 32-bit memory location by writing the
+ * specified Value to the the specified address.
+ *
+ * @param Addr contains the address to perform the output operation
+ * at.
+ * @param Value contains the Value to be output at the specified address.
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+void Xil_Out32(INTPTR Addr, u32 Value)
+{
+ u32* LocalAddr = (u32*)Addr;
+ *LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Performs an input operation for a 16-bit memory location by reading from the
+ * specified address and returning the byte-swapped Value read from that
+ * address.
+ *
+ * @param Addr contains the address to perform the input operation
+ * at.
+ *
+ * @return The byte-swapped Value read from the specified input address.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+u16 Xil_In16BE(INTPTR Addr)
+{
+ u16 temp;
+ u16 result;
+
+ temp = Xil_In16(Addr);
+
+ result = Xil_EndianSwap16(temp);
+
+ return result;
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Performs an input operation for a 32-bit memory location by reading from the
+ * specified address and returning the byte-swapped Value read from that
+ * address.
+ *
+ * @param Addr contains the address to perform the input operation
+ * at.
+ *
+ * @return The byte-swapped Value read from the specified input address.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+u32 Xil_In32BE(INTPTR Addr)
+{
+ u32 temp;
+ u32 result;
+
+ temp = Xil_In32(Addr);
+
+ result = Xil_EndianSwap32(temp);
+
+ return result;
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Performs an output operation for a 16-bit memory location by writing the
+ * specified Value to the the specified address. The Value is byte-swapped
+ * before being written.
+ *
+ * @param Addr contains the address to perform the output operation
+ * at.
+ * @param Value contains the Value to be output at the specified address.
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+void Xil_Out16BE(INTPTR Addr, u16 Value)
+{
+ u16 temp;
+
+ temp = Xil_EndianSwap16(Value);
+
+ Xil_Out16(Addr, temp);
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Performs an output operation for a 32-bit memory location by writing the
+ * specified Value to the the specified address. The Value is byte-swapped
+ * before being written.
+ *
+ * @param Addr contains the address to perform the output operation
+ * at.
+ * @param Value contains the Value to be output at the specified address.
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+void Xil_Out32BE(INTPTR Addr, u32 Value)
+{
+ u32 temp;
+
+ temp = Xil_EndianSwap32(Value);
+
+ Xil_Out32(Addr, temp);
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Perform a 16-bit endian converion.
+ *
+ * @param Data contains the value to be converted.
+ *
+ * @return converted value.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
+{
+ return (u16)(((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Perform a 32-bit endian converion.
+ *
+ * @param Data contains the value to be converted.
+ *
+ * @return converted value.
+ *
+ * @note None.
+ *
+ ******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+ u16 LoWord;
+ u16 HiWord;
+
+ /* get each of the half words from the 32 bit word */
+
+ LoWord = (u16)(Data & 0x0000FFFFU);
+ HiWord = (u16)((Data & 0xFFFF0000U) >> 16U);
+
+ /* byte swap each of the 16 bit half words */
+
+ LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+ HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
+
+ /* swap the half words before returning the value */
+
+ return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
+}
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/xil_uart.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/xil_uart.c
new file mode 100644
index 000000000..3f462a337
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_zynq7000-zc702/xil_uart.c
@@ -0,0 +1,214 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+ ******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xuartps_hw.c
+ * @addtogroup uartps_v3_1
+ * @{
+ *
+ *
+ *
+ * MODIFICATION HISTORY:
+ *
+ * Ver Who Date Changes
+ * ----- ------ -------- ----------------------------------------------
+ * 1.00 drg/jz 01/12/10 First Release
+ * 1.05a hk 08/22/13 Added reset function
+ * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
+ *
+ *
+ *****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#include "mmio_access.h"
+#include "uart_common_ope.h"
+
+/************************** Constant Definitions ****************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+ *
+ * This function sends one byte using the device. This function operates in
+ * polled mode and blocks until the data has been put into the TX FIFO register.
+ *
+ * @param BaseAddress contains the base address of the device.
+ * @param Data contains the byte to be sent.
+ *
+ * @return None.
+ *
+ * @note None.
+ *
+ *****************************************************************************/
+void XUartPs_SendByte(u32 BaseAddress, u8 Data)
+{
+ /* Wait until there is space in TX FIFO */
+ while (XUartPs_IsTransmitFull(BaseAddress)) {
+ ;
+ }
+
+ /* Write the byte into the TX FIFO */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data);
+}
+
+/****************************************************************************/
+/**
+ *
+ * This function receives a byte from the device. It operates in polled mode
+ * and blocks until a byte has received.
+ *
+ * @param BaseAddress contains the base address of the device.
+ *
+ * @return The data byte received.
+ *
+ * @note None.
+ *
+ *****************************************************************************/
+u8 XUartPs_RecvByte(u32 BaseAddress)
+{
+ u32 RecievedByte;
+ /* Wait until there is data */
+ while (!XUartPs_IsReceiveData(BaseAddress)) {
+ ;
+ }
+ RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET);
+ /* Return the byte received */
+ return (u8)RecievedByte;
+}
+
+/****************************************************************************/
+/**
+ *
+ * This function resets UART
+ *
+ * @param BaseAddress contains the base address of the device.
+ *
+ * @return None
+ *
+ * @note None.
+ *
+ *****************************************************************************/
+void XUartPs_ResetHw(u32 BaseAddress)
+{
+
+ /* Disable interrupts */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK);
+
+ /* Disable receive and transmit */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+ ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS));
+
+ /*
+ * Software reset of receive and transmit
+ * This clears the FIFO.
+ */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+ ((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST));
+
+ /* Clear status flags - SW reset wont clear sticky flags. */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK);
+
+ /*
+ * Mode register reset value : All zeroes
+ * Normal mode, even parity, 1 stop bit
+ */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET,
+ XUARTPS_MR_CHMODE_NORM);
+
+ /* Rx and TX trigger register reset values */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET,
+ XUARTPS_RXWM_RESET_VAL);
+ XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET,
+ XUARTPS_TXWM_RESET_VAL);
+
+ /* Rx timeout disabled by default */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET,
+ XUARTPS_RXTOUT_DISABLE);
+
+ /* Baud rate generator and dividor reset values */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET,
+ XUARTPS_BAUDGEN_RESET_VAL);
+ XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET,
+ XUARTPS_BAUDDIV_RESET_VAL);
+
+ /*
+ * Control register reset value -
+ * RX and TX are disable by default
+ */
+ XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+ ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS | (u32)XUARTPS_CR_STOPBRK));
+}
+
+void UartPutChar(uint8_t ch)
+{
+ if (ch == '\n') {
+ XUartPs_SendByte(MMIO_P2V(STDOUT_BASEADDRESS), '\r');
+ }
+ XUartPs_SendByte(MMIO_P2V(STDOUT_BASEADDRESS), ch);
+}
+
+static uint8_t UartGetChar()
+{
+ return XUartPs_RecvByte(MMIO_P2V(STDIN_BASEADDRESS));
+}
+
+static void UartInit()
+{
+}
+
+static uint32_t UartGetIrqnum()
+{
+ return 0;
+}
+
+static struct XiziSerialDriver hardkernel_serial_driver = {
+ .sys_serial_init = UartInit,
+ .get_serial_irqnum = UartGetIrqnum,
+ .putc = UartPutChar,
+ .getc = UartGetChar,
+};
+
+struct XiziSerialDriver* hardkernel_uart_init(struct TraceTag* hardkernel_tag)
+{
+ hardkernel_serial_driver.sys_serial_init();
+ return &hardkernel_serial_driver;
+}
+/** @} */
diff --git a/Ubiquitous/XiZi_AIoT/kernel_actracer/Readme.txt b/Ubiquitous/XiZi_AIoT/kernel_actracer/Readme.txt
new file mode 100644
index 000000000..d8d0f55fb
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/kernel_actracer/Readme.txt
@@ -0,0 +1,13 @@
+Actracer接口：
+
+bool AchieveResourceTag(struct TraceTag* target, struct TraceTag* owner, char* name):
+ 将owner资源（以tag标识）下属名为name的资源标识（tag）的值赋给传入的target。（调用者自行创建target并负责其生命周期）
+
+void* AchieveResource(struct TraceTag* target):
+ 若资源给定存储的形式为指针，则根据给入的target标识，返回资源的指针。
+
+bool CreateResourceTag(struct TraceTag* new_tag, struct TraceTag* owner, char* name, tracemeta_ac_type type, void* p_resource):
+ 在owner资源下，创建一个名为name的资源，并将该资源的标识赋值给new_tag。（调用者自行创建target并负责其生命周期）
+
+bool DeleteResource(struct TraceTag* target, struct TraceTag* owner):
+ 删除owner资源下属以target标识的资源。
diff --git a/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.c b/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.c
index eedfe2b61..32dcbf651 100644
--- a/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.c
+++ b/Ubiquitous/XiZi_AIoT/kernel_actracer/actracer.c
@@ -495,7 +495,7 @@ void tracer_find_tag(struct TraceTag* target, struct TraceTag* const source, cha
bool AchieveResourceTag(struct TraceTag* target, struct TraceTag* owner, char* name)
{
tracer_find_tag(target, owner, name);
- if (target == NULL) {
+ if (target->meta == NULL) {
return false;
}
return true;
diff --git a/Ubiquitous/XiZi_AIoT/path_kernel.mk b/Ubiquitous/XiZi_AIoT/path_kernel.mk
index dc5108cf3..33d069622 100755
--- a/Ubiquitous/XiZi_AIoT/path_kernel.mk
+++ b/Ubiquitous/XiZi_AIoT/path_kernel.mk
@@ -5,32 +5,51 @@ ifeq ($(CONFIG_LIB_NEWLIB),y)
KERNELPATHS += -I$(KERNEL_ROOT)/services/lib/newlib/include #
endif
-ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/services/boards/imx6q-sabrelite)
+ifeq ($(BOARD), imx6q-sabrelite)
KERNELPATHS += \
- -I$(KERNEL_ROOT)/hardkernel \
- -I$(KERNEL_ROOT)/hardkernel/boot/include \
- -I$(KERNEL_ROOT)/hardkernel/boot/sdk/imx6/include \
- -I$(KERNEL_ROOT)/hardkernel/cpu/include \
- -I$(KERNEL_ROOT)/hardkernel/cpu/sdk/imx6/include \
- -I$(KERNEL_ROOT)/hardkernel/clock/ \
-I$(KERNEL_ROOT)/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include \
- -I$(KERNEL_ROOT)/hardkernel/mmu/ \
-I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv7-a/cortex-a9/include \
- -I$(KERNEL_ROOT)/hardkernel/intr/ \
+ -I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv7-a/cortex-a9/$(BOARD) \
-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv7-a/cortex-a9/ \
-I$(KERNEL_ROOT)/hardkernel/intr/arm/armv7-a/cortex-a9/gicv2 \
- -I$(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_nxp_imx6q_sabrelite/include \
+ -I$(KERNEL_ROOT)/hardkernel/intr/arm/armv7-a/cortex-a9/$(BOARD) \
+ -I$(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_$(BOARD)/include \
-I$(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/ \
- -I$(KERNEL_ROOT)/hardkernel/uart/ \
- -I$(KERNEL_ROOT)/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_imx6q_sabrelite/include \
+ -I$(KERNEL_ROOT)/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_$(BOARD)/include \
-I$(KERNEL_ROOT)/hardkernel/uart/arm/armv7-a/cortex-a9/ \
- -I$(KERNEL_ROOT)/hardkernel/cache/ \
-I$(KERNEL_ROOT)/hardkernel/cache/L1/arm/cortex-a9/ \
- -I$(KERNEL_ROOT)/hardkernel/cache/L2/pl310/ \
+ -I$(KERNEL_ROOT)/hardkernel/cache/L2/pl310/
+endif
+
+ifeq ($(BOARD), zynq7000-zc702)
+KERNELPATHS += \
+ -I$(KERNEL_ROOT)/hardkernel/clock/arm/armv7-a/cortex-a9/$(BOARD)/include \
+ -I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv7-a/cortex-a9/include \
+ -I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv7-a/cortex-a9/$(BOARD) \
+ -I$(KERNEL_ROOT)/hardkernel/intr/arm/armv7-a/cortex-a9/ \
+ -I$(KERNEL_ROOT)/hardkernel/intr/arm/armv7-a/cortex-a9/gicv2 \
+ -I$(KERNEL_ROOT)/hardkernel/intr/arm/armv7-a/cortex-a9/gicv3 \
+ -I$(KERNEL_ROOT)/hardkernel/intr/arm/armv7-a/cortex-a9/$(BOARD) \
+ -I$(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_$(BOARD)/include \
+ -I$(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/ \
+ -I$(KERNEL_ROOT)/hardkernel/uart/arm/armv7-a/cortex-a9/uart_io_for_$(BOARD)/include \
+ -I$(KERNEL_ROOT)/hardkernel/uart/arm/armv7-a/cortex-a9/ \
+ -I$(KERNEL_ROOT)/hardkernel/cache/L1/arm/cortex-a9/ \
+ -I$(KERNEL_ROOT)/hardkernel/cache/L2/pl310/
+endif
+
+KERNELPATHS += \
+ -I$(KERNEL_ROOT)/hardkernel \
+ -I$(KERNEL_ROOT)/hardkernel/clock/ \
+ -I$(KERNEL_ROOT)/hardkernel/mmu/ \
+ -I$(KERNEL_ROOT)/hardkernel/intr/ \
+ -I$(KERNEL_ROOT)/hardkernel/uart/ \
+ -I$(KERNEL_ROOT)/hardkernel/cache/
+
+KERNELPATHS += \
-I$(KERNEL_ROOT)/softkernel/include \
-I$(KERNEL_ROOT)/kernel_actracer/ \
-I$(KERNEL_ROOT)/include
-endif
KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Applications/general_functions/list #
diff --git a/Ubiquitous/XiZi_AIoT/services/Makefile b/Ubiquitous/XiZi_AIoT/services/Makefile
index cadecb450..b888b74fc 100644
--- a/Ubiquitous/XiZi_AIoT/services/Makefile
+++ b/Ubiquitous/XiZi_AIoT/services/Makefile
@@ -1,6 +1,5 @@
-SRC_DIR := fs shell lib tools boards
-
+SRC_DIR := fs shell lib boards tools app
include $(KERNEL_ROOT)/compiler.mk
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/.config b/Ubiquitous/XiZi_AIoT/services/app/.config
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/.config
rename to Ubiquitous/XiZi_AIoT/services/app/.config
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Kconfig b/Ubiquitous/XiZi_AIoT/services/app/Kconfig
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Kconfig
rename to Ubiquitous/XiZi_AIoT/services/app/Kconfig
diff --git a/Ubiquitous/XiZi_AIoT/services/app/Makefile b/Ubiquitous/XiZi_AIoT/services/app/Makefile
new file mode 100644
index 000000000..fd0fb506b
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/services/app/Makefile
@@ -0,0 +1,67 @@
+ifeq ($(BOARD), imx6q-sabrelite)
+toolchain ?= arm-none-eabi-
+user_ldflags = --specs=nosys.specs -Wl,-Map=user.map,-cref -N
+cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie -no-pie
+endif
+ifeq ($(BOARD), zynq7000-zc702)
+toolchain ?= arm-xilinx-eabi-
+user_ldflags = -Wl,--start-group,-lgcc,-lc,--end-group -N
+cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
+board_specs = stub.o
+#cflags = -Wall -g -std=c11
+endif
+
+cc = ${toolchain}gcc
+ld = ${toolchain}g++
+objdump = ${toolchain}objdump
+c_useropts = -O0
+
+INC_DIR = -I$(KERNEL_ROOT)/services/shell/letter-shell \
+ -I$(KERNEL_ROOT)/services/lib/ipc \
+ -I$(KERNEL_ROOT)/services/lib/memory \
+ -I$(KERNEL_ROOT)/services/fs/libfs \
+ -I$(KERNEL_ROOT)/services/boards/$(BOARD) \
+ -I$(KERNEL_ROOT)/services/app
+
+all: init test_fs simple_client simple_server shell fs_server test_priority readme.txt | bin
+ ../tools/mkfs/mkfs ./fs.img $^
+ @mv $(filter-out readme.txt, $^) bin
+ @mv *.o bin
+ @mv *.asm bin
+
+bin:
+ @mkdir -p bin
+
+shell: shell_port.o libserial.o shell_cmd_list.o shell.o shell_ext.o libfs_to_client.o libipc.o session.o usyscall.o
+ @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
+ @${objdump} -S $@ > $@.asm
+
+init: init.o libfs_to_client.o libipc.o session.o libserial.o usyscall.o
+ @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
+ @${objdump} -S $@ > $@.asm
+
+test_fs: test_fs.o libfs_to_client.o libipc.o session.o libserial.o usyscall.o
+ @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
+ @${objdump} -S $@ > $@.asm
+
+simple_client: simple_client.o libserial.o libipc.o session.o simple_service.o libfs_to_client.o usyscall.o
+ @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
+ @${objdump} -S $@ > $@.asm
+
+simple_server: simple_server.o libserial.o libipc.o session.o simple_service.o usyscall.o
+ @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
+ @${objdump} -S $@ > $@.asm
+
+fs_server: fs_server.o libfs_to_client.o fs.o libserial.o libipc.o session.o block_io.o usyscall.o
+ @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
+ @${objdump} -S $@ > $@.asm
+
+test_priority: test_priority.o libserial.o usyscall.o
+ @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
+ @${objdump} -S $@ > $@.asm
+
+%.o: %.c
+ @${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $<
+
+%.o: %.S
+ @${cc} ${cflags} ${c_useropts} -o $@ -c $<
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/init.c b/Ubiquitous/XiZi_AIoT/services/app/init.c
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/init.c
rename to Ubiquitous/XiZi_AIoT/services/app/init.c
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/readme.txt b/Ubiquitous/XiZi_AIoT/services/app/readme.txt
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/readme.txt
rename to Ubiquitous/XiZi_AIoT/services/app/readme.txt
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/shell_port.c b/Ubiquitous/XiZi_AIoT/services/app/shell_port.c
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/shell_port.c
rename to Ubiquitous/XiZi_AIoT/services/app/shell_port.c
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/simple_client.c b/Ubiquitous/XiZi_AIoT/services/app/simple_client.c
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/simple_client.c
rename to Ubiquitous/XiZi_AIoT/services/app/simple_client.c
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/simple_server.c b/Ubiquitous/XiZi_AIoT/services/app/simple_server.c
similarity index 89%
rename from Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/simple_server.c
rename to Ubiquitous/XiZi_AIoT/services/app/simple_server.c
index 612ce293a..90cb8e442 100755
--- a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/simple_server.c
+++ b/Ubiquitous/XiZi_AIoT/services/app/simple_server.c
@@ -15,6 +15,8 @@
#include "simple_service.h"
#include "usyscall.h"
+/// @warning all the parameters should in the form of pointers
+/// for the true storing memory of parameters is session(shared memory between tasks)
int IPC_DO_SERVE_FUNC(Ipc_add)(int* a, int* b)
{
return *a + *b;
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/simple_service.c b/Ubiquitous/XiZi_AIoT/services/app/simple_service.c
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/simple_service.c
rename to Ubiquitous/XiZi_AIoT/services/app/simple_service.c
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/simple_service.h b/Ubiquitous/XiZi_AIoT/services/app/simple_service.h
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/simple_service.h
rename to Ubiquitous/XiZi_AIoT/services/app/simple_service.h
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/test_fs.c b/Ubiquitous/XiZi_AIoT/services/app/test_fs.c
similarity index 90%
rename from Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/test_fs.c
rename to Ubiquitous/XiZi_AIoT/services/app/test_fs.c
index 4c612e6d7..3e592530f 100644
--- a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/test_fs.c
+++ b/Ubiquitous/XiZi_AIoT/services/app/test_fs.c
@@ -19,6 +19,7 @@
#include "libfs_to_client.h"
#include "usyscall.h"
+#define BLOCK_SIZE 256
int main(int argc, char* argv[])
{
printf("file system test\n");
@@ -26,8 +27,6 @@ int main(int argc, char* argv[])
struct Session session;
connect_session(&session, "MemFS", 4096);
- register_server("TEST_FS");
-
int fd;
char* fd_path = "/readme.txt";
fd = open(&session, fd_path);
@@ -43,9 +42,12 @@ int main(int argc, char* argv[])
printf("file content: %s\n", buffer);
close(&session, fd);
-
free_session(&session);
+ printf("file test done.\n");
+ printf("Test memry error %s.\n", 0x50000000);
+ printf("After error computing.\n");
+
exit();
return 0;
}
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/test_priority.c b/Ubiquitous/XiZi_AIoT/services/app/test_priority.c
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/test_priority.c
rename to Ubiquitous/XiZi_AIoT/services/app/test_priority.c
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/xsconfig.h b/Ubiquitous/XiZi_AIoT/services/app/xsconfig.h
similarity index 100%
rename from Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/xsconfig.h
rename to Ubiquitous/XiZi_AIoT/services/app/xsconfig.h
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Makefile b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Makefile
index 5e8d2e69d..71ddf042c 100644
--- a/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Makefile
+++ b/Ubiquitous/XiZi_AIoT/services/boards/imx6q-sabrelite/Makefile
@@ -1,53 +1,28 @@
-
+ifeq ($(BOARD), imx6q-sabrelite)
toolchain ?= arm-none-eabi-
+endif
+ifeq ($(BOARD), zynq7000-zc702)
+toolchain ?= arm-xilinx-eabi-
+endif
cc = ${toolchain}gcc
ld = ${toolchain}g++
objdump = ${toolchain}objdump
-user_ldflags = --specs=nosys.specs -Wl,-Map=user.map,-cref -N
-cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie -no-pie
+user_ldflags = -N -Ttext 0
+
+cflags = -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie -no-pie
c_useropts = -O0
-INC_DIR = -I$(KERNEL_ROOT)/services/shell/letter-shell \
+INC_DIR = -I$(KERNEL_ROOT)/services/fs/libfs \
+ -I$(KERNEL_ROOT)/services/fs/fs_server/include \
-I$(KERNEL_ROOT)/services/lib/ipc \
- -I$(KERNEL_ROOT)/services/lib/memory \
- -I$(KERNEL_ROOT)/services/boards/imx6q-sabrelite \
- -I$(KERNEL_ROOT)/services/fs/libfs
+ -I$(KERNEL_ROOT)/services/boards/$(BOARD) \
+ -I$(KERNEL_ROOT)/services/app
-all: init simple_client simple_server shell fs_server test_priority readme.txt | bin
- ../../tools/mkfs/mkfs ./fs.img $^
- @mv $(filter-out readme.txt, $^) bin
- @mv *.o bin
- @mv *.asm bin
-
-bin:
- @mkdir -p bin
-
-shell: shell_port.o libserial.o shell_cmd_list.o shell.o shell_ext.o libfs_to_client.o libipc.o session.o usyscall.o
- @${ld} ${user_ldflags} -e main -o $@ $^
- @${objdump} -S $@ > $@.asm
-
-init: init.o libfs_to_client.o libipc.o session.o libserial.o usyscall.o
- @${ld} ${user_ldflags} -e main -o $@ $^
- @${objdump} -S $@ > $@.asm
-
-simple_client: simple_client.o libserial.o libipc.o session.o simple_service.o libfs_to_client.o usyscall.o
- @${ld} ${user_ldflags} -e main -o $@ $^
- @${objdump} -S $@ > $@.asm
-
-simple_server: simple_server.o libserial.o libipc.o session.o simple_service.o usyscall.o
- @${ld} ${user_ldflags} -e main -o $@ $^
- @${objdump} -S $@ > $@.asm
-
-fs_server: fs_server.o libfs_to_client.o fs.o libserial.o libipc.o session.o block_io.o usyscall.o
- @${ld} ${user_ldflags} -e main -o $@ $^
- @${objdump} -S $@ > $@.asm
-
-test_priority: test_priority.o libserial.o usyscall.o
- @${ld} ${user_ldflags} -e main -o $@ $^
- @${objdump} -S $@ > $@.asm
+board: libserial.o usyscall.o
+ @mv $^ ../../app
%.o: %.c
- @${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $<
+ @echo "cc $^"
+ @${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $^
-%.o: %.S
- @${cc} ${cflags} ${c_useropts} -o $@ -c $<
\ No newline at end of file
+include $(KERNEL_ROOT)/compiler.mk
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/Makefile b/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/Makefile
new file mode 100644
index 000000000..f312ba643
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/Makefile
@@ -0,0 +1,31 @@
+ifeq ($(BOARD), imx6q-sabrelite)
+toolchain ?= arm-none-eabi-
+user_ldflags = -N -Ttext 0
+cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
+endif
+ifeq ($(BOARD), zynq7000-zc702)
+toolchain ?= arm-xilinx-eabi-
+user_ldflags = --start-group,-lgcc,-lc,--end-group
+cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
+#cflags = -Wall -g -std=c11
+endif
+cc = ${toolchain}gcc
+ld = ${toolchain}g++
+objdump = ${toolchain}objdump
+
+c_useropts = -O0
+
+INC_DIR = -I$(KERNEL_ROOT)/services/fs/libfs \
+ -I$(KERNEL_ROOT)/services/fs/fs_server/include \
+ -I$(KERNEL_ROOT)/services/lib/ipc \
+ -I$(KERNEL_ROOT)/services/boards/$(BOARD) \
+ -I$(KERNEL_ROOT)/services/app
+
+board: libserial.o stub.o usyscall.o
+ @mv $^ ../../app
+
+%.o: %.c
+ @echo "cc $^"
+ @${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $^
+
+include $(KERNEL_ROOT)/compiler.mk
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/libserial.c b/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/libserial.c
new file mode 100644
index 000000000..2a788aa82
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/libserial.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ * http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+
+/// this file is only used for debug
+#include "libserial.h"
+#include "usyscall.h"
+
+uint32_t Xil_In32(intptr_t Addr)
+{
+ return *(volatile uint32_t*)Addr;
+}
+void Xil_Out32(intptr_t Addr, uint32_t Value)
+{
+ uint32_t* LocalAddr = (uint32_t*)Addr;
+ *LocalAddr = Value;
+}
+#define XUartPs_IsTransmitFull(BaseAddress) \
+ ((*(volatile uint32_t*)((BaseAddress) + 0x002CU) & (uint32_t)0x00000010U) == (uint32_t)0x00000010U)
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+ Xil_Out32((BaseAddress) + (uint32_t)(RegOffset), (uint32_t)(RegisterValue))
+
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (uint32_t)(RegOffset))
+#define XUartPs_IsReceiveData(BaseAddress) \
+ !((Xil_In32((BaseAddress) + 0x002CU) & (uint32_t)0x00000002U) == (uint32_t)0x00000002U)
+
+uint8_t XUartPs_RecvByte(uint32_t BaseAddress)
+{
+ uint32_t RecievedByte;
+ /* Wait until there is data */
+ while (!XUartPs_IsReceiveData(BaseAddress)) {
+ ;
+ }
+ RecievedByte = XUartPs_ReadReg(BaseAddress, 0x0030U);
+ /* Return the byte received */
+ return (uint8_t)RecievedByte;
+}
+
+#define USER_UART_BASE 0x6FFFF000
+
+static bool init_uart_mmio()
+{
+ static int mapped = 0;
+ if (mapped == 0) {
+ if (-1 == mmap(USER_UART_BASE, 0xE0001000, 4096, true)) {
+ return false;
+ }
+ mapped = 1;
+ }
+ return true;
+}
+
+static void putc(char c)
+{
+ if (c == '\n') {
+ while (XUartPs_IsTransmitFull(USER_UART_BASE)) {
+ ;
+ }
+
+ XUartPs_WriteReg(USER_UART_BASE, 0x0030U, (uint32_t)'\r');
+ }
+
+ while (XUartPs_IsTransmitFull(USER_UART_BASE)) {
+ ;
+ }
+
+ XUartPs_WriteReg(USER_UART_BASE, 0x0030U, (uint32_t)c);
+}
+
+char getc(void)
+{
+ if (!init_uart_mmio()) {
+ return 0xFF;
+ }
+ return XUartPs_RecvByte(USER_UART_BASE);
+}
+
+static void printint(int xx, int base, int sgn)
+{
+ static char digits[] = "0123456789ABCDEF";
+ char buf[16];
+ int i, neg;
+ uint32_t x;
+
+ neg = 0;
+ if (sgn && xx < 0) {
+ neg = 1;
+ x = -xx;
+ } else {
+ x = xx;
+ }
+
+ i = 0;
+ do {
+ buf[i++] = digits[x % base];
+ } while ((x /= base) != 0);
+ if (neg)
+ buf[i++] = '-';
+
+ while (--i >= 0)
+ putc(buf[i]);
+}
+
+// Print to usart. Only understands %d, %x, %p, %s.
+void printf(char* fmt, ...)
+{
+ if (!init_uart_mmio()) {
+ return;
+ }
+ char* s;
+ int c, i, state;
+ uint32_t* ap;
+
+ state = 0;
+ ap = (uint32_t*)(void*)&fmt + 1;
+ for (i = 0; fmt[i]; i++) {
+ c = fmt[i] & 0xff;
+ if (state == 0) {
+ if (c == '%') {
+ state = '%';
+ } else {
+ putc(c);
+ }
+ } else if (state == '%') {
+ if (c == 'd') {
+ printint(*ap, 10, 1);
+ ap++;
+ } else if (c == 'x' || c == 'p') {
+ printint(*ap, 16, 0);
+ ap++;
+ } else if (c == 's') {
+ s = (char*)*ap;
+ ap++;
+ if (s == 0)
+ s = "(null)";
+ while (*s != 0) {
+ putc(*s);
+ s++;
+ }
+ } else if (c == 'c') {
+ putc(*ap);
+ ap++;
+ } else if (c == '%') {
+ putc(c);
+ } else {
+ // Unknown % sequence. Print it to draw attention.
+ putc('%');
+ putc(c);
+ }
+ state = 0;
+ }
+ }
+}
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/libserial.h b/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/libserial.h
new file mode 100644
index 000000000..02d3e18af
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/libserial.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ * http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+
+/// this file is only used for debug
+#pragma once
+
+void printf(char* fmt, ...);
+
+char getc();
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/stub.c b/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/stub.c
new file mode 100644
index 000000000..c2c3af9d4
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/stub.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ * http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+
+#include
+#include
+#include
+
+// _exit: 用于退出程序
+void _exit(int status)
+{
+ while (1) { }
+}
+
+// _sbrk: 用于增加程序的数据空间
+void* _sbrk(ptrdiff_t incr)
+{
+ extern char end; /* Defined by the linker */
+ static char* heap_end;
+ char* prev_heap_end;
+
+ if (heap_end == 0) {
+ heap_end = &end;
+ }
+ prev_heap_end = heap_end;
+
+ // 在这里，你应该添加一些检查来确保堆不会与栈或其他内存区域冲突
+ // 例如，检查 incr 是否会导致堆超出预定的内存区域
+
+ heap_end += incr;
+ return (void*)prev_heap_end;
+}
+
+// _write: 用于将数据写入文件描述符
+ssize_t _write(int file, const void* ptr, size_t len)
+{
+ // 在这里，你需要实现将数据写入文件描述符的逻辑
+ // 如果你的系统不支持文件系统，你可以将数据发送到串口或其他输出
+
+ return len; // 假设所有数据都被写入
+}
+
+// _close: 用于关闭文件描述符
+int _close(int file)
+{
+ return -1; // 表示失败，因为没有实际关闭文件的功能
+}
+
+// _fstat: 用于获取文件状态
+int _fstat(int file, struct stat* st)
+{
+ return 0; // 表示成功
+}
+
+// _isatty: 检查文件描述符是否指向TTY设备
+int _isatty(int file)
+{
+ return 1; // 表示是TTY设备
+}
+
+// _lseek: 用于重新定位文件读/写的位置
+off_t _lseek(int file, off_t offset, int whence)
+{
+ return -1; // 表示失败，因为不支持文件定位
+}
+
+// _read: 用于从文件描述符读取数据
+ssize_t _read(int file, void* ptr, size_t len)
+{
+ return 0; // 表示没有数据被读取
+}
+
+// _kill: 发送信号给进程
+int _kill(int pid, int sig)
+{
+ return -1; // 表示失败，因为不支持信号
+}
+
+// _getpid: 获取进程ID
+int _getpid()
+{
+ return 1; // 返回假设的进程ID
+}
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/usyscall.c b/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/usyscall.c
new file mode 100644
index 000000000..c03893a43
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/usyscall.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ * http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+#include "usyscall.h"
+
+static int
+syscall(int sys_num, intptr_t a1, intptr_t a2, intptr_t a3, intptr_t a4)
+{
+ int ret = -1;
+
+ __asm__ volatile(
+ "mov r0, %1;\
+ mov r1, %2;\
+ mov r2, %3;\
+ mov r3, %4;\
+ mov r4, %5;\
+ swi 0;\
+ dsb;\
+ isb;\
+ mov %0, r0"
+ : "=r"(ret)
+ : "r"(sys_num), "r"(a1), "r"(a2), "r"(a3), "r"(a4)
+ : "memory", "r0", "r1", "r2", "r3", "r4");
+
+ return ret;
+}
+
+int spawn(struct Session* session, int fd, ipc_read_fn ipc_read, char* name, char** argv)
+{
+ struct KernReadTool read_tool = {
+ .session = session,
+ .fd = fd,
+ .ipc_read = ipc_read,
+ };
+ return syscall(SYSCALL_SPAWN, (intptr_t)&read_tool, (intptr_t)name, (intptr_t)argv, 0);
+}
+
+int exit()
+{
+ return syscall(SYSCALL_EXIT, 0, 0, 0, 0);
+}
+
+int yield()
+{
+ return syscall(SYSCALL_YIELD, 0, 0, 0, 0);
+}
+
+int register_server(char* name)
+{
+ return syscall(SYSCALL_SERVER, (intptr_t)name, 0, 0, 0);
+}
+
+int session(char* path, int capacity, struct Session* user_session)
+{
+ return syscall(SYSCALL_SESSION, (intptr_t)path, (intptr_t)capacity, (intptr_t)user_session, 0);
+}
+
+int poll_session(struct Session* userland_session_arr, int arr_capacity)
+{
+ return syscall(SYSCALL_POLL_SESSION, (intptr_t)userland_session_arr, (intptr_t)arr_capacity, 0, 0);
+}
+
+int close_session(struct Session* session)
+{
+ return syscall(SYSCALL_CLOSE_SESSION, (intptr_t)session, 0, 0, 0);
+}
+
+int get_memblock_info(sys_state_info* info)
+{
+ return syscall(SYSCALL_SYS_STATE, SYS_STATE_MEMBLOCK_INFO, (intptr_t)info, 0, 0);
+}
+
+int set_priority(sys_state_info* info)
+{
+ return syscall(SYSCALL_SYS_STATE, SYS_STATE_SET_TASK_PRIORITY, (intptr_t)info, 0, 0);
+}
+
+int task_heap_base()
+{
+ return syscall(SYSCALL_SYS_STATE, SYS_STATE_GET_HEAP_BASE, 0, 0, 0);
+}
+
+int show_task()
+{
+ return syscall(SYSCALL_SYS_STATE, SYS_STATE_SHOW_TASKS, 0, 0, 0);
+}
+
+int show_mem()
+{
+ return syscall(SYSCALL_SYS_STATE, SYS_STATE_SHOW_MEM_INFO, 0, 0, 0);
+}
+
+int show_cpu()
+{
+ return syscall(SYSCALL_SYS_STATE, SYS_STATE_SHOW_CPU_INFO, 0, 0, 0);
+}
+
+int mmap(uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev)
+{
+ return syscall(SYSCALL_MMAP, vaddr, paddr, (intptr_t)len, (intptr_t)is_dev);
+}
+
+int register_irq(int irq, int opcode)
+{
+ return syscall(SYSCALL_REGISTER_IRQ, (intptr_t)irq, (intptr_t)opcode, 0, 0);
+}
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/usyscall.h b/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/usyscall.h
new file mode 100644
index 000000000..65ab3cd6f
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/services/boards/zynq7000-zc702/usyscall.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ * http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+#pragma once
+#include
+
+#include "libserial.h"
+#include "session.h"
+
+// clang-format off
+#define SYSCALL_TEST 0
+#define SYSCALL_SPAWN 1 // generate a brand new task to run elf
+#define SYSCALL_EXIT 2 // exit task, delete the task cb
+#define SYSCALL_YIELD 3 // yield task, go to scheduler
+
+#define SYSCALL_MMAP 4 // map a virt page to phy page
+#define SYSCALL_SERVER 5 // register current task as a server
+#define SYSCALL_SESSION 6 // create a session to a server
+#define SYSCALL_POLL_SESSION 7 // server poll for it's server sessions
+#define SYSCALL_CLOSE_SESSION 8 // client close it's client sessions
+
+#define SYSCALL_EXEC 9 // run elf using current task
+#define SYSCALL_SYS_STATE 10 // run system state
+#define SYSCALL_REGISTER_IRQ 11 //
+// clang-format on
+
+typedef enum {
+ SYS_STATE_TEST = 0,
+ SYS_STATE_SET_TASK_PRIORITY,
+ SYS_STATE_GET_HEAP_BASE,
+ SYS_STATE_MEMBLOCK_INFO,
+ SYS_STATE_SHOW_TASKS,
+ SYS_STATE_SHOW_MEM_INFO,
+ SYS_STATE_SHOW_CPU_INFO,
+} sys_state_option;
+
+typedef union {
+ struct {
+ uintptr_t memblock_start;
+ uintptr_t memblock_end;
+ } memblock_info;
+ int priority;
+} sys_state_info;
+
+typedef int (*ipc_read_fn)(struct Session* session, int fd, char* dst, int offset, int len);
+typedef int (*ipc_write_fn)(struct Session* session, int fd, char* src, int offset, int len);
+
+struct KernReadTool {
+ struct Session* session;
+ int fd;
+ ipc_read_fn ipc_read;
+};
+
+int spawn(struct Session* session, int fd, ipc_read_fn ipc_read, char* name, char** argv);
+int exit();
+int yield();
+int register_server(char* name);
+int session(char* path, int capacity, struct Session* user_session);
+int poll_session(struct Session* userland_session_arr, int arr_capacity);
+int close_session(struct Session* session);
+int task_heap_base();
+int get_memblock_info(sys_state_info* info);
+int set_priority(sys_state_info* info);
+int show_task();
+int show_mem();
+int show_cpu();
+int mmap(uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev);
+int register_irq(int irq, int opcode);
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile b/Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile
index 673d8eb3e..6e254bcee 100644
--- a/Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile
+++ b/Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile
@@ -1,19 +1,28 @@
+ifeq ($(BOARD), imx6q-sabrelite)
toolchain ?= arm-none-eabi-
+user_ldflags = -N -Ttext 0
+cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie -no-pie
+endif
+ifeq ($(BOARD), zynq7000-zc702)
+toolchain ?= arm-xilinx-eabi-
+user_ldflags = --start-group,-lgcc,-lc,--end-group
+cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
+#cflags = -Wall -g -std=c11
+endif
cc = ${toolchain}gcc
ld = ${toolchain}g++
objdump = ${toolchain}objdump
-user_ldflags = -N -Ttext 0
-cflags = -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie -no-pie
c_useropts = -O0
INC_DIR = -I$(KERNEL_ROOT)/services/fs/libfs \
-I$(KERNEL_ROOT)/services/fs/fs_server/include \
-I$(KERNEL_ROOT)/services/lib/ipc \
- -I$(KERNEL_ROOT)/services/boards/imx6q-sabrelite
+ -I$(KERNEL_ROOT)/services/boards/$(BOARD) \
+ -I$(KERNEL_ROOT)/services/app
fs_server: fs_server.o fs.o block_io.o
- @mv $^ ../../boards/imx6q-sabrelite
+ @mv $^ ../../app
%.o: %.c
@echo "cc $^"
diff --git a/Ubiquitous/XiZi_AIoT/services/fs/fs_server/fs_server.c b/Ubiquitous/XiZi_AIoT/services/fs/fs_server/fs_server.c
index 673a1c2c6..1e0d2dbad 100644
--- a/Ubiquitous/XiZi_AIoT/services/fs/fs_server/fs_server.c
+++ b/Ubiquitous/XiZi_AIoT/services/fs/fs_server/fs_server.c
@@ -63,11 +63,11 @@ int IPC_DO_SERVE_FUNC(Ipc_ls)(char* path)
}
if (!(ip = InodeSeek(dp, path))) {
- printf("ls:find target Inode failed\n");
+ printf("ls: find target Inode failed, ip: %x(%d), dp: %x(%d)\n", ip, ip->inum, dp, dp->inum);
return -1;
}
- if (ip->type != FS_DIRECTORY) {
- printf("ls:not a dir\n");
+ if (ip->type != T_DIR) {
+ printf("ls: not a dir\n");
return -1;
}
diff --git a/Ubiquitous/XiZi_AIoT/services/fs/fs_server/include/list.h b/Ubiquitous/XiZi_AIoT/services/fs/fs_server/include/list.h
index 2961c9c46..bbf6e0caa 100644
--- a/Ubiquitous/XiZi_AIoT/services/fs/fs_server/include/list.h
+++ b/Ubiquitous/XiZi_AIoT/services/fs/fs_server/include/list.h
@@ -31,15 +31,15 @@ struct double_list_node {
#define DOUBLE_LIST_ENTRY(item, type, member) \
CONTAINER_OF(item, type, member)
-#define DOUBLE_LIST_FOR_EACH_ENTRY(item, head, member) \
- for (item = DOUBLE_LIST_ENTRY((head)->next, typeof(*item), member); \
- &item->member != (head); \
- item = DOUBLE_LIST_ENTRY(item->member.next, typeof(*item), member))
+#define DOUBLE_LIST_FOR_EACH_ENTRY(item, head, member) \
+ for (item = DOUBLE_LIST_ENTRY((head)->next, __typeof__(*item), member); \
+ &item->member != (head); \
+ item = DOUBLE_LIST_ENTRY(item->member.next, __typeof__(*item), member))
-#define DOUBLE_LIST_FOR_EACH_ENTRY_REVERSE(item, head, member) \
- for (item = DOUBLE_LIST_ENTRY((head)->prev, typeof(*item), member); \
- &item->member != (head); \
- item = DOUBLE_LIST_ENTRY(item->member.prev, typeof(*item), member))
+#define DOUBLE_LIST_FOR_EACH_ENTRY_REVERSE(item, head, member) \
+ for (item = DOUBLE_LIST_ENTRY((head)->prev, __typeof__(*item), member); \
+ &item->member != (head); \
+ item = DOUBLE_LIST_ENTRY(item->member.prev, __typeof__(*item), member))
__attribute__((always_inline)) static void inline doubleListNodeInit(struct double_list_node* list)
{
diff --git a/Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile b/Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile
index 35645c9cc..ce34b4855 100644
--- a/Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile
+++ b/Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile
@@ -1,18 +1,27 @@
+ifeq ($(BOARD), imx6q-sabrelite)
toolchain ?= arm-none-eabi-
+user_ldflags = -N -Ttext 0
+cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie -no-pie
+endif
+ifeq ($(BOARD), zynq7000-zc702)
+toolchain ?= arm-xilinx-eabi-
+user_ldflags = --start-group,-lgcc,-lc,--end-group
+cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
+#cflags = -Wall -g -std=c11
+endif
cc = ${toolchain}gcc
ld = ${toolchain}g++
objdump = ${toolchain}objdump
-user_ldflags = -N -Ttext 0
-cflags = -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie -no-pie
c_useropts = -O0
INC_DIR = -I$(KERNEL_ROOT)/services/fs/libfs \
-I$(KERNEL_ROOT)/services/lib/ipc \
- -I$(KERNEL_ROOT)/services/boards/imx6q-sabrelite
+ -I$(KERNEL_ROOT)/services/boards/$(BOARD) \
+ -I$(KERNEL_ROOT)/services/app
fs_server: libfs_to_client.o
- @mv $^ ../../boards/imx6q-sabrelite
+ @mv $^ ../../app
%.o: %.c
@echo "cc $^"
diff --git a/Ubiquitous/XiZi_AIoT/services/lib/Makefile b/Ubiquitous/XiZi_AIoT/services/lib/Makefile
index c242de34a..1d6142afd 100644
--- a/Ubiquitous/XiZi_AIoT/services/lib/Makefile
+++ b/Ubiquitous/XiZi_AIoT/services/lib/Makefile
@@ -1,4 +1,4 @@
-SRC_DIR := ipc memory
+SRC_DIR := ipc
include $(KERNEL_ROOT)/compiler.mk
diff --git a/Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile b/Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile
index 0ab8ae2f1..c9c573cf2 100644
--- a/Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile
+++ b/Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile
@@ -1,16 +1,27 @@
+ifeq ($(BOARD), imx6q-sabrelite)
toolchain ?= arm-none-eabi-
+user_ldflags = -N -Ttext 0
+cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie -no-pie
+endif
+ifeq ($(BOARD), zynq7000-zc702)
+toolchain ?= arm-xilinx-eabi-
+user_ldflags = --start-group,-lgcc,-lc,--end-group
+cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
+#cflags = -Wall -g -std=c11
+endif
cc = ${toolchain}gcc
ld = ${toolchain}g++
objdump = ${toolchain}objdump
-user_ldflags = -N -Ttext 0
-cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie -no-pie
c_useropts = -O0
-INC_DIR = -I$(KERNEL_ROOT)/services/shell/letter-shell -I$(KERNEL_ROOT)/services/lib/ipc -I$(KERNEL_ROOT)/services/boards/imx6q-sabrelite
+INC_DIR = -I$(KERNEL_ROOT)/services/shell/letter-shell \
+ -I$(KERNEL_ROOT)/services/lib/ipc \
+ -I$(KERNEL_ROOT)/services/boards/$(BOARD) \
+ -I$(KERNEL_ROOT)/services/app
all: libipc.o session.o
- @mv $^ ../../boards/imx6q-sabrelite
+ @mv $^ ../../app
%.o: %.c
@echo "cc $^"
diff --git a/Ubiquitous/XiZi_AIoT/services/lib/ipc/Readme.txt b/Ubiquitous/XiZi_AIoT/services/lib/ipc/Readme.txt
new file mode 100644
index 000000000..9dca77ff0
--- /dev/null
+++ b/Ubiquitous/XiZi_AIoT/services/lib/ipc/Readme.txt
@@ -0,0 +1,31 @@
+libipc接口说明：
+
+libipc使用共享内存在两个进程之间实现进程间函数调用。
+
+server的实现参考simple_server。
+1. 在server程序和client库函数共用的头文件(参考simple_service.h)中定义IPC_SERVICES，
+ I. 包含(1)服务名称，(2)服务提供的接口名。
+ II. simple_service.h中还包含了client库函数提供的接口(add(), hello_string(),...)，这些接口可以单独为一个头文件提供给用户。
+
+2. 在client库中使用提供给用户的接口，
+ I. 使用默认形式的接口需要依照：
+ IPC_INTERFACE(1.I中定义的接口名，参数的个数，[函数中使用的参数名...]，[各个参数占用的内存大小])；
+ II. 默认接口要求传入的“参数的实际内容”在共享内存中存在一份拷贝，因此在IPC_INTERFACE中需要给出“参数占用的内存大小”。
+ III. 使用IPC_CALL(接口名)()调用IPC_INTERFACE中生成的消息发送函数，IPC_CALL(接口名)()中只接受指针参数（需传入IPC_INTERFACE中定义的参数名），指针指向“存储实际参数”的地址。
+ 如hello_string()函数，IPC_CALL(Ipc_hello_string)传入(buf, &len)，指针buf指向缓存数组的真正位置，指针&len指向存储(int)len的真正位置。
+ IV. hello_string_nowait()给出了消息传输的真正逻辑：
+ (1) 在Session中创建Message;
+ (2) 使用ipc_msg_get_nth_arg_buf()和ipc_msg_set_nth_arg()为参数赋值。
+ (3) 设置Message的操作码（此处为Ipc_hello_string）;
+ (4) 调用ipc_msg_send_nowait()或ipc_msg_send()发送消息。
+
+3. 定义server程序：
+ I. 在server的c文件（此处为simple_server.c）中定义IPC_DO_SERVE_FUNC(接口名)()中实现函数逻辑。（传入参数均为指针）；
+ II. 为server定义在message中解析接口的函数，使用宏IPC_SERVER_INTERFACE(接口名，参数个数)；
+ III. 向server处理表注册接口，使用IPC_SERVER_REGISTER_INTERFACES(服务名，接口个数，[接口名, ...]) ；
+ IV. 定义main函数：
+ (1) 初始化server所需的数据结构；
+ (2) 向操作系统注册服务：register_server(“用来访问服务的名称”)；
+ (3) 调用ipc_server_loop()：该函数单线程得处理传入到server的调用请求。
+
+注：创建session时传入的大小必须大于后续在 使用session发起的调用中 参数实际所占的大小。
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/services/lib/ipc/libipc.h b/Ubiquitous/XiZi_AIoT/services/lib/ipc/libipc.h
index 12d44cddb..86148a9a6 100644
--- a/Ubiquitous/XiZi_AIoT/services/lib/ipc/libipc.h
+++ b/Ubiquitous/XiZi_AIoT/services/lib/ipc/libipc.h
@@ -88,8 +88,7 @@ struct IpcNode {
#define _IPC_INSERT_SERVE(interface) [interface] = IPC_SERVE(interface)
#define IPC_SERVER_REGISTER_INTERFACES(ipc_node_name, num_interfaces, ...) \
- static struct IpcNode ipc_node_name = (struct IpcNode) \
- { \
+ static struct IpcNode ipc_node_name = { \
.interfaces = { \
_VA_FRONT_WRAP_ARG##num_interfaces(_IPC_INSERT_SERVE, __VA_ARGS__), \
}, \
@@ -183,6 +182,14 @@ void ipc_server_loop(struct IpcNode* ipc_node);
#define IPC_SERVE(ipc_name) ipc_serve_##ipc_name
#define IPC_DO_SERVE_FUNC(ipc_name) ipc_do_serve_##ipc_name
+/// when defining a ipc server:
+/// 1. requires a IPC_SERVICES(server_name, interface_name, ...) to announce the name and interfaces that the server will support
+/// 2. implement IPC_DO_SERVE_FUNC(interface_name) for each interface
+/// 3. use IPC_SERVER_INTERFACE(interface_name, argc) to generate necessary helper functions
+/// 4. use IPC_SERVER_REGISTER_INTERFACES(server_name, nr_interfaces, interface_names, ...) to bind interfaces to server after implementations
+/// 5. use ipc_server_loop in main()
+/// Refer to simple_service.h, simple_service.c and simple_server.c for example
+
#define IPC_INTERFACE(ipc_name, argc, ...) \
__always_inline static inline struct IpcMsg* IPC_CREATE_MSG_FUNC(ipc_name)(struct Session * session, _VA_FRONT_PTR_ARG##argc(__VA_ARGS__)) \
{ \
diff --git a/Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile b/Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile
index 61a39a8a1..80cb8d3da 100644
--- a/Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile
+++ b/Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile
@@ -1,13 +1,19 @@
+ifeq ($(BOARD), imx6q-sabrelite)
toolchain ?= arm-none-eabi-
+endif
+ifeq ($(BOARD), zynq7000-zc702)
+toolchain ?= arm-xilinx-eabi-
+endif
cc = ${toolchain}gcc
ld = ${toolchain}g++
objdump = ${toolchain}objdump
user_ldflags = -N -Ttext 0
-cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie -no-pie
+cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
c_useropts = -O0
-INC_DIR = -I$(KERNEL_ROOT)/services/boards/imx6q-sabrelite \
+INC_DIR = -I$(KERNEL_ROOT)/services/app \
+ -I$(KERNEL_ROOT)/services/boards/$(BOARD) \
-I$(KERNEL_ROOT)/services/lib/ipc
all:
diff --git a/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile b/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile
index 0b55ac74e..ac0b851b3 100644
--- a/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile
+++ b/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile
@@ -1,18 +1,27 @@
+ifeq ($(BOARD), imx6q-sabrelite)
toolchain ?= arm-none-eabi-
+user_ldflags = -N -Ttext 0
+cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
+endif
+ifeq ($(BOARD), zynq7000-zc702)
+toolchain ?= arm-xilinx-eabi-
+user_ldflags = --start-group,-lgcc,-lc,--end-group
+cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie
+#cflags = -Wall -g -std=c11 -Wno-unused
+endif
cc = ${toolchain}gcc
ld = ${toolchain}g++
objdump = ${toolchain}objdump
-# user_ldflags = -N -Ttext 0
-cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie -no-pie
c_useropts = -O0
-INC_DIR = -I$(KERNEL_ROOT)/services/boards/imx6q-sabrelite -I$(KERNEL_ROOT)/services/lib/ipc -I$(KERNEL_ROOT)/services/fs/libfs
+INC_DIR = -I$(KERNEL_ROOT)/services/app \
+ -I$(KERNEL_ROOT)/services/lib/ipc \
+ -I$(KERNEL_ROOT)/services/boards/$(BOARD) \
+ -I$(KERNEL_ROOT)/services/fs/libfs
all: shell_cmd_list.o shell_ext.o shell.o
- @mv shell_cmd_list.o ../../boards/imx6q-sabrelite
- @mv shell_ext.o ../../boards/imx6q-sabrelite
- @mv shell.o ../../boards/imx6q-sabrelite
+ @mv $^ ../../app
shell_cmd_list.o: shell_cmd_list.c
@echo "cc shell_cmd_list"
diff --git a/Ubiquitous/XiZi_AIoT/softkernel/Makefile b/Ubiquitous/XiZi_AIoT/softkernel/Makefile
index 7e15af1a7..1464fe7b9 100644
--- a/Ubiquitous/XiZi_AIoT/softkernel/Makefile
+++ b/Ubiquitous/XiZi_AIoT/softkernel/Makefile
@@ -1,4 +1,4 @@
-SRC_DIR := init memory trap task syscall ipc
+SRC_DIR := init memory trap task syscall
SRC_FILES := main.c load_apps.S
diff --git a/Ubiquitous/XiZi_AIoT/softkernel/include/list.h b/Ubiquitous/XiZi_AIoT/softkernel/include/list.h
index de16ac88b..add341b62 100644
--- a/Ubiquitous/XiZi_AIoT/softkernel/include/list.h
+++ b/Ubiquitous/XiZi_AIoT/softkernel/include/list.h
@@ -52,15 +52,15 @@ struct double_list_node {
#define DOUBLE_LIST_ENTRY(item, type, member) \
CONTAINER_OF(item, type, member)
-#define DOUBLE_LIST_FOR_EACH_ENTRY(item, head, member) \
- for (item = DOUBLE_LIST_ENTRY((head)->next, typeof(*item), member); \
- &item->member != (head); \
- item = DOUBLE_LIST_ENTRY(item->member.next, typeof(*item), member))
+#define DOUBLE_LIST_FOR_EACH_ENTRY(item, head, member) \
+ for (item = DOUBLE_LIST_ENTRY((head)->next, __typeof__(*item), member); \
+ &item->member != (head); \
+ item = DOUBLE_LIST_ENTRY(item->member.next, __typeof__(*item), member))
-#define DOUBLE_LIST_FOR_EACH_ENTRY_REVERSE(item, head, member) \
- for (item = DOUBLE_LIST_ENTRY((head)->prev, typeof(*item), member); \
- &item->member != (head); \
- item = DOUBLE_LIST_ENTRY(item->member.prev, typeof(*item), member))
+#define DOUBLE_LIST_FOR_EACH_ENTRY_REVERSE(item, head, member) \
+ for (item = DOUBLE_LIST_ENTRY((head)->prev, __typeof__(*item), member); \
+ &item->member != (head); \
+ item = DOUBLE_LIST_ENTRY(item->member.prev, __typeof__(*item), member))
__attribute__((always_inline))
static void inline doubleListNodeInit(struct double_list_node *list)
diff --git a/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h b/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h
index 7d2925419..bd3f70af4 100644
--- a/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h
+++ b/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h
@@ -71,7 +71,7 @@ extern struct MmuCommonDone* _p_pgtbl_mmu_access;
uintptr_t* _page_walk(uintptr_t* pgdir, uintptr_t vaddr, bool alloc);
extern struct TopLevelPageDirectory kern_pgdir;
-void load_kern_pgdir(struct TraceTag* mmu_driver_tag);
+void load_kern_pgdir(struct TraceTag* mmu_driver_tag, struct TraceTag* intr_driver_tag);
extern struct XiziPageManager xizi_pager;
bool module_pager_init(struct PagerRightGroup*);
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/softkernel/init/softkernel_init.c b/Ubiquitous/XiZi_AIoT/softkernel/init/softkernel_init.c
index cc64c57ba..d2fea7f52 100644
--- a/Ubiquitous/XiZi_AIoT/softkernel/init/softkernel_init.c
+++ b/Ubiquitous/XiZi_AIoT/softkernel/init/softkernel_init.c
@@ -42,17 +42,18 @@ bool softkernel_init(struct TraceTag* _hardkernel_tag, struct TraceTag* _softker
/* init soft kernel */
module_phymem_init(); // init buddy management system
- struct PagerRightGroup pager_rights = { 0 };
+ struct PagerRightGroup pager_rights;
AchieveResourceTag(&pager_rights.mmu_driver_tag, _hardkernel_tag, "mmu-ac-resource");
module_pager_init(&pager_rights);
- struct TraceTag mmu_driver_tag;
+ struct TraceTag mmu_driver_tag, intr_driver_tag;
AchieveResourceTag(&mmu_driver_tag, _hardkernel_tag, "mmu-ac-resource");
- load_kern_pgdir(&mmu_driver_tag); // enter kernel virtmem space
+ AchieveResourceTag(&intr_driver_tag, _hardkernel_tag, "intr-ac-resource");
+ load_kern_pgdir(&mmu_driver_tag, &intr_driver_tag); // enter kernel virtmem space
module_task_manager_init(); // init task
- struct SharePageRightGroup sp_rights = { 0 };
+ struct SharePageRightGroup sp_rights;
AchieveResourceTag(&sp_rights.dcache_driver_tag, _hardkernel_tag, "dcache-ac-resource");
AchieveResourceTag(&sp_rights.mmu_driver_tag, _hardkernel_tag, "mmu-ac-resource");
module_share_page_init(&sp_rights);
diff --git a/Ubiquitous/XiZi_AIoT/softkernel/ipc/Makefile b/Ubiquitous/XiZi_AIoT/softkernel/ipc/Makefile
deleted file mode 100644
index a8abfc5fb..000000000
--- a/Ubiquitous/XiZi_AIoT/softkernel/ipc/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-SRC_FILES := share_page.c
-
-include $(KERNEL_ROOT)/compiler.mk
diff --git a/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S b/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S
index c6f31f377..71d5278bd 100644
--- a/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S
+++ b/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S
@@ -30,16 +30,16 @@ Modification:
.section .rawdata_fs_img
.globl user_apps
user_apps:
- .incbin "../services/boards/imx6q-sabrelite/fs.img"
+ .incbin "../services/app/fs.img"
.section .rawdata_init
.globl initapp
initapp:
- .incbin "../services/boards/imx6q-sabrelite/bin/init"
+ .incbin "../services/app/bin/init"
.section .rawdata_memfs
.globl memfs
memfs:
- .incbin "../services/boards/imx6q-sabrelite/bin/fs_server"
+ .incbin "../services/app/bin/fs_server"
.end
diff --git a/Ubiquitous/XiZi_AIoT/softkernel/main.c b/Ubiquitous/XiZi_AIoT/softkernel/main.c
index ade61e0ae..d283b4b27 100644
--- a/Ubiquitous/XiZi_AIoT/softkernel/main.c
+++ b/Ubiquitous/XiZi_AIoT/softkernel/main.c
@@ -32,6 +32,8 @@ Modification:
#include "assert.h"
#include "task.h"
+#include "trap_common.h"
+
extern uint32_t _binary_init_start[], _binary_default_fs_start[];
extern int sys_spawn(char* path, char** argv);
int main(void)
@@ -64,11 +66,19 @@ int main(void)
spawn_embedded_task((char*)_binary_default_fs_start, "memfs", fs_server_task_param);
/* start scheduler */
- struct SchedulerRightGroup scheduler_rights = { 0 };
+ struct SchedulerRightGroup scheduler_rights;
assert(AchieveResourceTag(&scheduler_rights.mmu_driver_tag, &hardkernel_tag, "mmu-ac-resource"));
assert(AchieveResourceTag(&scheduler_rights.intr_driver_tag, &hardkernel_tag, "intr-ac-resource"));
xizi_task_manager.task_scheduler(scheduler_rights);
// never reached
return 0;
+}
+
+__attribute__((weak)) void _exit(int32_t status)
+{
+ (void)status;
+ while (1) {
+ ;
+ }
}
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile b/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile
index efc31e387..9014b9e7c 100644
--- a/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile
+++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile
@@ -1,3 +1,3 @@
-SRC_FILES:= kalloc.c pagetable.c pagetable_level2.c buddy.c object_allocator.c
+SRC_FILES:= kalloc.c pagetable.c pagetable_level2.c buddy.c object_allocator.c share_page.c
include $(KERNEL_ROOT)/compiler.mk
diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable.c
index 420ead35e..0ad42a9e3 100644
--- a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable.c
+++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable.c
@@ -252,7 +252,7 @@ static uintptr_t _cross_vspace_data_copy(struct TopLevelPageDirectory* pgdir, ui
return len;
}
-struct XiziPageManager xizi_pager = (struct XiziPageManager) {
+struct XiziPageManager xizi_pager = {
.new_pgdir = _new_pgdir,
.free_user_pgdir = _free_user_pgdir,
.map_pages = _map_user_pages,
@@ -273,7 +273,7 @@ bool module_pager_init(struct PagerRightGroup* _right_group)
/// @brief kernel pagedir
struct TopLevelPageDirectory kern_pgdir;
-void load_kern_pgdir(struct TraceTag* mmu_driver_tag)
+void load_kern_pgdir(struct TraceTag* mmu_driver_tag, struct TraceTag* intr_driver_tag)
{
if (mmu_driver_tag->meta == NULL) {
ERROR("Invalid mmu driver tag.\n");
@@ -293,5 +293,6 @@ void load_kern_pgdir(struct TraceTag* mmu_driver_tag)
// dev mem
_map_pages((uintptr_t*)kern_pgdir.pd_addr, DEV_VRTMEM_BASE, DEV_PHYMEM_BASE, DEV_MEM_SZ, dev_attr);
- _p_pgtbl_mmu_access->LoadPgdir((uintptr_t)V2P(kern_pgdir.pd_addr));
+ // _p_pgtbl_mmu_access->LoadPgdir((uintptr_t)V2P(kern_pgdir.pd_addr));
+ _p_pgtbl_mmu_access->LoadPgdirCrit((uintptr_t)V2P(kern_pgdir.pd_addr), intr_driver_tag);
}
\ No newline at end of file
diff --git a/Ubiquitous/XiZi_AIoT/softkernel/ipc/share_page.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/share_page.c
similarity index 99%
rename from Ubiquitous/XiZi_AIoT/softkernel/ipc/share_page.c
rename to Ubiquitous/XiZi_AIoT/softkernel/memory/share_page.c
index f76cb0773..3f6001114 100644
--- a/Ubiquitous/XiZi_AIoT/softkernel/ipc/share_page.c
+++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/share_page.c
@@ -250,7 +250,7 @@ int delete_share_pages(struct session_backend* session_backend)
return 0;
}
-struct XiziSharePageManager xizi_share_page_manager = (struct XiziSharePageManager) {
+struct XiziSharePageManager xizi_share_page_manager = {
.create_share_pages = create_share_pages,
.unmap_task_share_pages = unmap_task_share_pages,
.delete_share_pages = delete_share_pages,
diff --git a/Ubiquitous/XiZi_AIoT/softkernel/task/task.c b/Ubiquitous/XiZi_AIoT/softkernel/task/task.c
index b34cdc707..b90cc944e 100644
--- a/Ubiquitous/XiZi_AIoT/softkernel/task/task.c
+++ b/Ubiquitous/XiZi_AIoT/softkernel/task/task.c
@@ -256,7 +256,7 @@ static void _set_cur_task_priority(int priority)
return;
}
-struct XiziTaskManager xizi_task_manager = (struct XiziTaskManager) {
+struct XiziTaskManager xizi_task_manager = {
.init = _task_manager_init,
.new_task_cb = _new_task_cb,
.free_pcb = _dealloc_task_cb,
diff --git a/Ubiquitous/XiZi_AIoT/softkernel/trap/clock_irq_handler.c b/Ubiquitous/XiZi_AIoT/softkernel/trap/clock_irq_handler.c
index 987a7bb82..b3453dd2c 100644
--- a/Ubiquitous/XiZi_AIoT/softkernel/trap/clock_irq_handler.c
+++ b/Ubiquitous/XiZi_AIoT/softkernel/trap/clock_irq_handler.c
@@ -34,6 +34,8 @@ Modification:
#include "multicores.h"
#include "task.h"
+#include "log.h"
+
static struct TraceTag clock_driver_tag;
static struct XiziClockDriver* p_clock_driver = NULL;
@@ -48,14 +50,16 @@ uint64_t global_tick = 0;
int xizi_clock_handler(int irq, void* tf, void* arg)
{
/* handle clock interrupt using driver */
- p_clock_driver->clear_clock_intr();
- global_tick++;
- struct TaskMicroDescriptor* current_task = cur_cpu()->task;
- if (current_task) {
- current_task->remain_tick--;
- current_task->maxium_tick--;
- if (current_task->remain_tick == 0) {
- xizi_task_manager.cur_task_yield_noschedule();
+ if (p_clock_driver->is_timer_expired()) {
+ p_clock_driver->clear_clock_intr();
+ global_tick++;
+ struct TaskMicroDescriptor* current_task = cur_cpu()->task;
+ if (current_task) {
+ current_task->remain_tick--;
+ current_task->maxium_tick--;
+ if (current_task->remain_tick == 0) {
+ xizi_task_manager.cur_task_yield_noschedule();
+ }
}
}
return 0;
diff --git a/Ubiquitous/XiZi_AIoT/softkernel/trap/default_irq_handler.c b/Ubiquitous/XiZi_AIoT/softkernel/trap/default_irq_handler.c
index d737452ea..445c64add 100644
--- a/Ubiquitous/XiZi_AIoT/softkernel/trap/default_irq_handler.c
+++ b/Ubiquitous/XiZi_AIoT/softkernel/trap/default_irq_handler.c
@@ -60,7 +60,7 @@ void intr_irq_dispatch(struct trapframe* tf)
p_intr_driver->cpu_irq_disable();
// enter irq
- uint32_t int_info = 0;
+ uintptr_t int_info = 0;
if ((int_info = p_intr_driver->hw_before_irq()) == 0) {
return;
}