forked from xuos/xiuos
feat add abstruction_mmu for XiZi_AIoT(support MmuInit\MmuSectionMap\MmuSectionUnmap\MmuTtbSwitch\MmuTransform)
This commit is contained in:
Liu_Weichao
parent
a110ab511c
commit
3463c8515f
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@ -1,3 +1,3 @@
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SRC_FILES := cache.c isr.c mmu.c
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SRC_FILES := cache.c isr.c abstraction_mmu.c
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include $(KERNEL_ROOT)/compiler.mk
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@ -0,0 +1,206 @@
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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/**
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* @file: abstraction_mmu.c
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* @brief: the general management of system mmu
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* @version: 3.0
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* @author: AIIT XUOS Lab
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* @date: 2023/4/27
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*
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*/
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#include <abstraction_mmu.h>
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AbstractionMmu abstraction_mmu;
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volatile uint32_t global_L1_pte_table[4096];
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/**
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* @description: write cmd to CP15 register
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* @param reg_type - CP15 register type
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* @param val - ops val pointer
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* @return
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*/
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static void MmuCp15Write(uint8_t reg_type, uint32_t *val)
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{
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uint32_t write_val = *val;
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switch (reg_type) {
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case AM_MMU_CP15_TTBCR:
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TTBCR_W(write_val);
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AM_ISB;
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case AM_MMU_CP15_TTBR0:
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TTBR0_W(write_val);
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AM_ISB;
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default:
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break;
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}
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}
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/**
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* @description: read CP15 register from mmu
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* @param reg_type - CP15 register type
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* @param val - ops val pointer
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* @return
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*/
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static void MmuCp15Read(uint8_t reg_type, uint32_t *val)
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{
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uint32_t read_val = 0;
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switch (reg_type) {
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case AM_MMU_CP15_TTBCR:
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TTBCR_R(read_val);
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case AM_MMU_CP15_TTBR0:
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TTBR0_R(read_val);
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default:
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break;
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}
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*val = read_val;
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}
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/**
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* @description: write or read CP15 register to set mmu
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* @param ops_type - CP15 write or read
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* @param reg_type - CP15 register type
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* @param val - ops val pointer
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* @return
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*/
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static void MmuRegOps(uint8_t ops_type, uint8_t reg_type, uint32_t *val)
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{
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switch (ops_type) {
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case AM_MMU_CP15_WRITE:
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MmuCp15Write(reg_type, val);
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case AM_MMU_CP15_READ:
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MmuCp15Read(reg_type, val);
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default:
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break;
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}
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}
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/**
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* @description: Init abstraction_mmu function
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* @param mmu - abstraction mmu pointer
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* @param ttb_base - ttb base pointer
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* @return success : 0 error : -1
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*/
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static int _AbstractionMmuInit(AbstractionMmu *mmu, uint32_t *ttb_base)
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{
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mmu_init();
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return 0;
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}
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/**
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* @description: map L1 or L2 page table section
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* @param mmu - abstraction mmu pointer
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* @param section_size - section size
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* @return success : 0 error : -1
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*/
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static int _AbstractionMmuSectionMap(AbstractionMmu *mmu, uint32_t section_size)
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{
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uint32_t vaddr_length = mmu->vaddr_end - mmu->vaddr_start + 1;
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mmu_map_l1_range(mmu->paddr_start, mmu->vaddr_start, vaddr_length,
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mmu->mmu_memory_type, mmu->mmu_shareability, mmu->mmu_access);
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mmu->mmu_status = 1;
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return 0;
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}
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/**
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* @description: unmap L1 or L2 page table section
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* @param mmu - abstraction mmu pointer
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* @param vaddr_start - virtual address start
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* @param vaddr_size - virtual address size
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* @return success : 0 error : -1
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*/
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static int _AbstractionMmuSectionUnmap(AbstractionMmu *mmu, uint32_t vaddr_start, uint32_t vaddr_size)
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{
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uint32_t *l1_umap_ventry = mmu->ttb_vbase + (vaddr_start >> AM_MMU_L1_SECTION_SHIFT);
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uint32_t vaddr_end = vaddr_start + vaddr_size - 1;
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uint32_t umap_count = (vaddr_end >> AM_MMU_L1_SECTION_SHIFT) - (vaddr_start >> AM_MMU_L1_SECTION_SHIFT) + 1;
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while (umap_count) {
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AM_DMB;
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*l1_umap_ventry = 0;
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AM_DSB;
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umap_count--;
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l1_umap_ventry += (1 << AM_MMU_L1_SECTION_SHIFT);//1MB section
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}
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AM_DSB;
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CLEARTLB(0);//clear TLB data and configure
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AM_DSB;
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AM_ISB;
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mmu->mmu_status = 0;
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return 0;
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}
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/**
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* @description: switch ttb base by re-write ttbr register
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* @param mmu - abstraction mmu pointer
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* @return success : 0 error : -1
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*/
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static int _AbstractionMmuTtbSwitch(AbstractionMmu *mmu)
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{
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uint32_t ttbr, ttbcr;
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MmuRegOps(AM_MMU_CP15_READ, AM_MMU_CP15_TTBCR, &ttbcr);
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/* Set TTBR0 with inner/outer write back write allocate and not shareable, [4:3]=01, [1]=0, [6,0]=01 */
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ttbr = ((mmu->ttb_pbase & 0xFFFFC000UL) | 0x9UL);
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/* enable TTBR0 */
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ttbcr = 0;
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AM_DSB;
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MmuRegOps(AM_MMU_CP15_WRITE, AM_MMU_CP15_TTBR0, &ttbr);
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MmuRegOps(AM_MMU_CP15_WRITE, AM_MMU_CP15_TTBCR, &ttbcr);
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return 0;
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}
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/**
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* @description: get physical address transformed from virtual address
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* @param mmu - abstraction mmu pointer
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* @param vaddr - virtual address pointer
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* @param paddr - physical address pointer
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* @return success : 0 error : -1
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*/
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static int _AbstracktonMmuTransform(AbstractionMmu *mmu, uint32_t *vaddr, uint32_t *paddr)
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{
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uint32_t virtualAddress = *vaddr;
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if (mmu->mmu_status) {
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mmu_virtual_to_physical(virtualAddress, paddr);
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}
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return 0;
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}
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static struct AbstractionMmuDone mmu_done = {
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.AbstractionMmuInit = _AbstractionMmuInit,
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.AbstractionMmuSectionMap = _AbstractionMmuSectionMap,
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.AbstractionMmuSectionUnmap = _AbstractionMmuSectionUnmap,
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.AbstractionMmuTtbSwitch = _AbstractionMmuTtbSwitch,
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.AbstracktonMmuTransform = _AbstracktonMmuTransform,
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};
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/**
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* @description: init abstraciton mmu info when system start
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* @return success : 0 error : -1
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*/
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int SysInitAbstractionMmu(void)
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{
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abstraction_mmu.mmu_done = &mmu_done;
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}
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@ -0,0 +1,114 @@
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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/**
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* @file: mmu.h
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* @brief: the general management of system mmu
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* @version: 3.0
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* @author: AIIT XUOS Lab
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* @date: 2023/5/24
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*
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*/
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#include <stdint.h>
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#include <mmu.h>
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#define ARCH_ARM
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#ifdef ARCH_ARM
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/* ARM System Registers */
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#define AM_DSB __asm__ volatile("dsb" ::: "memory")
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#define AM_DMB __asm__ volatile("dmb" ::: "memory")
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#define AM_ISB __asm__ volatile("isb" ::: "memory")
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#define AM_WFI __asm__ volatile("wfi" ::: "memory")
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#define AM_BARRIER __asm__ volatile("":::"memory")
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#define AM_WFE __asm__ volatile("wfe" ::: "memory")
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#define AM_SEV __asm__ volatile("sev" ::: "memory")
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#define TTBR0_R(val) __asm__ volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(val))
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#define TTBR0_W(val) __asm__ volatile("mcr p15, 0, %0, c2, c0, 0" ::"r"(val))
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#define TTBCR_R(val) __asm__ volatile("mrc p15, 0, %0, c2, c0, 2" : "=r"(val))
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#define TTBCR_W(val) __asm__ volatile("mcr p15, 0, %0, c2, c0, 2" ::"r"(val))
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#define CLEARTLB(val) __asm__ volatile("mcr p15, 0, %0, c8, c7, 0" ::"r"(val))
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#endif
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#define AM_MMU_L1_PAGE_TABLE_SIZE (4 * 4096)
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#define AM_MMU_L1_SECTION_SHIFT 20
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typedef enum
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{
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AM_MMU_CP15_WRITE = 0,
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AM_MMU_CP15_READ,
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}MmuCP15OpsType;
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typedef enum
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{
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AM_MMU_CP15_TTBCR = 0,
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AM_MMU_CP15_TTBR0,
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AM_MMU_CP15_CLEARTLB,
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}MmuCP15RegType;
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typedef enum
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{
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AM_StronglyOrdered = 0,
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AM_Device,
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AM_OuterInner_WB_WA,
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AM_OuterInner_WT,
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AM_Noncacheable,
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}MmuMemoryType;
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typedef enum
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{
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AM_Noaccess = 0,
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AM_Read_Write,
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AM_Read,
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}MmuAccess;
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typedef enum
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{
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AM_Shareable = 1,
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AM_Nonshareable = 0
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}MmuShareability;
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struct AbstractionMmuDone
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{
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int (*AbstractionMmuInit)(AbstractionMmu *mmu, uint32_t *ttb_base);
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int (*AbstractionMmuSectionMap)(AbstractionMmu *mmu, uint32_t section_size);
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int (*AbstractionMmuSectionUnmap)(AbstractionMmu *mmu, uint32_t vaddr_start, uint32_t vaddr_size);
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int (*AbstractionMmuTtbSwitch)(AbstractionMmu *mmu);
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int (*AbstracktonMmuTransform)(AbstractionMmu *mmu, uint32_t *vaddr, uint32_t *paddr);
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};
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typedef struct
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{
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uint32_t ttb_vbase;
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uint32_t ttb_pbase;
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uint32_t vaddr_start;
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uint32_t vaddr_end;
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uint32_t paddr_start;
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uint32_t paddr_end;
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uint32_t vpaddr_offset;
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uint32_t pte_attr;
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uint32_t mmu_status;
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MmuMemoryType mmu_memory_type;
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MmuAccess mmu_access;
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MmuShareability mmu_shareability;
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struct AbstractionMmuDone *mmu_done;
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int lock;
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int link_list;
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}AbstractionMmu;
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@ -1,4 +1,23 @@
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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/**
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* @file: cache.c
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* @brief: the general management of system cache
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* @version: 3.0
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* @author: AIIT XUOS Lab
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* @date: 2023/4/27
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*
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*/
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void InvalidInsCache()
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{
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@ -0,0 +1,20 @@
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/*
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* Copyright (c) 2020 AIIT XUOS Lab
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* XiUOS is licensed under Mulan PSL v2.
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* You can use this software according to the terms and conditions of the Mulan PSL v2.
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* You may obtain a copy of Mulan PSL v2 at:
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* http://license.coscl.org.cn/MulanPSL2
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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* See the Mulan PSL v2 for more details.
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*/
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/**
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* @file: memory.c
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* @brief: the general management of system memory
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* @version: 3.0
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* @author: AIIT XUOS Lab
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* @date: 2023/4/27
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*
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*/
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