From 455fd31c7fe3525e7dfa915125945b42c7841275 Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Thu, 13 Jul 2023 10:56:20 +0800 Subject: [PATCH 01/21] mqtt update --- APP_Framework/Applications/app_test/Makefile | 3 ++- APP_Framework/Applications/connection_app/Makefile | 2 +- .../Applications/connection_app/mqtt_demo/Makefile | 12 ++++++++++++ APP_Framework/lib/cJSON/Makefile | 1 + .../XiZi_IIoT/resources/ethernet/LwIP/Makefile | 4 ++++ .../XiZi_IIoT/resources/ethernet/LwIP/apps/Makefile | 2 ++ .../resources/ethernet/LwIP/include/Makefile | 6 ++++++ .../resources/ethernet/LwIP/include/lwip/Makefile | 6 ++++++ .../ethernet/LwIP/include/lwip/apps/MQTT/Makefile | 13 +++++++++++++ .../ethernet/LwIP/include/lwip/apps/Makefile | 6 ++++++ 10 files changed, 53 insertions(+), 2 deletions(-) create mode 100644 APP_Framework/Applications/connection_app/mqtt_demo/Makefile create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/apps/Makefile create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/Makefile create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/Makefile create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/Makefile create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/Makefile diff --git a/APP_Framework/Applications/app_test/Makefile b/APP_Framework/Applications/app_test/Makefile index 1cf919846..5215f5091 100644 --- a/APP_Framework/Applications/app_test/Makefile +++ b/APP_Framework/Applications/app_test/Makefile @@ -1,4 +1,5 @@ include $(KERNEL_ROOT)/.config + ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) include $(APPDIR)/Make.defs @@ -24,7 +25,7 @@ endif ifeq ($(CONFIG_ADD_XIZI_FETURES),y) SRC_FILES := test_shell.c - + SRC_FILES += test_hash.c ifeq ($(CONFIG_USER_TEST_ADC),y) SRC_FILES += test_adc.c endif diff --git a/APP_Framework/Applications/connection_app/Makefile b/APP_Framework/Applications/connection_app/Makefile index df4ae9b97..65d5842e0 100755 --- a/APP_Framework/Applications/connection_app/Makefile +++ b/APP_Framework/Applications/connection_app/Makefile @@ -14,7 +14,7 @@ ifeq ($(CONFIG_ADD_XIZI_FETURES),y) ifeq ($(CONFIG_RESOURCES_LWIP),y) SRC_DIR += socket_demo endif - + SRC_DIR +=mqtt_demo include $(KERNEL_ROOT)/compiler.mk endif diff --git a/APP_Framework/Applications/connection_app/mqtt_demo/Makefile b/APP_Framework/Applications/connection_app/mqtt_demo/Makefile new file mode 100644 index 000000000..e5d888bb3 --- /dev/null +++ b/APP_Framework/Applications/connection_app/mqtt_demo/Makefile @@ -0,0 +1,12 @@ +ifeq ($(CONFIG_ADD_XIZI_FETURES),y) +SRC_FILES := lwip_mqtt_demo.c +include $(KERNEL_ROOT)/compiler.mk +endif + +include $(KERNEL_ROOT)/.config +ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) + include $(APPDIR)/Make.defs + CSRCS += lwip_mqtt_demo.c + include $(APPDIR)/Application.mk +endif + diff --git a/APP_Framework/lib/cJSON/Makefile b/APP_Framework/lib/cJSON/Makefile index 79f1fc37d..8d2e20e45 100755 --- a/APP_Framework/lib/cJSON/Makefile +++ b/APP_Framework/lib/cJSON/Makefile @@ -1,3 +1,4 @@ SRC_FILES := cJSON.c +SRC_FILES += cJSON_Process.c include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/Makefile b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/Makefile index 1c0cdf531..184021487 100644 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/Makefile +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/Makefile @@ -2,10 +2,14 @@ SRC_DIR += api SRC_DIR += arch SRC_DIR += core SRC_DIR += netif +SRC_DIR += include + LWIP_DIR += api LWIP_DIR += arch LWIP_DIR += core LWIP_DIR += netif +LWIP_DIR += include + include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/apps/Makefile b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/apps/Makefile new file mode 100644 index 000000000..98aa92bfb --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/apps/Makefile @@ -0,0 +1,2 @@ + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/Makefile b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/Makefile new file mode 100644 index 000000000..c53e661a4 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/Makefile @@ -0,0 +1,6 @@ +SRC_DIR += lwip + +LWIP_DIR += lwip + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/Makefile b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/Makefile new file mode 100644 index 000000000..1d8dcd833 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/Makefile @@ -0,0 +1,6 @@ +SRC_DIR += apps + +LWIP_DIR += apps + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/Makefile b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/Makefile new file mode 100644 index 000000000..2cc7a23d1 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/Makefile @@ -0,0 +1,13 @@ +SRC_FILES += MQTTPacket.c\ + MQTTConnectClient.c \ + MQTTConnectServer.c \ + MQTTDeserializePublish.c \ + MQTTFormat.c \ + MQTTSerializePublish.c \ + MQTTSubscribeClient.c \ + MQTTSubscribeServer.c \ + MQTTUnsubscribeClient.c \ + MQTTUnsubscribeServer.c \ + transport.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/Makefile b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/Makefile new file mode 100644 index 000000000..a7d676dbc --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/Makefile @@ -0,0 +1,6 @@ +SRC_DIR += MQTT + +LWIP_DIR += MQTT + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file From c06138364fbe3231199f205eb53038bf2211c809 Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Thu, 13 Jul 2023 10:56:50 +0800 Subject: [PATCH 02/21] mqtt update --- .../Applications/app_test/test_hash.c | 44 ++ .../connection_app/mqtt_demo/lwip_mqtt_demo.c | 726 ++++++++++++++++++ .../connection_app/mqtt_demo/lwip_mqtt_demo.h | 71 ++ APP_Framework/lib/cJSON/cJSON_Process.c | 85 ++ APP_Framework/lib/cJSON/cJSON_Process.h | 23 + Ubiquitous/XiZi_IIoT/kernel/include/xs_hash.h | 144 ++++ .../LwIP/include/lwip/apps/MQTT/MQTTConnect.h | 137 ++++ .../lwip/apps/MQTT/MQTTConnectClient.c | 214 ++++++ .../lwip/apps/MQTT/MQTTConnectServer.c | 148 ++++ .../lwip/apps/MQTT/MQTTDeserializePublish.c | 107 +++ .../LwIP/include/lwip/apps/MQTT/MQTTFormat.c | 262 +++++++ .../LwIP/include/lwip/apps/MQTT/MQTTFormat.h | 37 + .../LwIP/include/lwip/apps/MQTT/MQTTPacket.c | 412 ++++++++++ .../LwIP/include/lwip/apps/MQTT/MQTTPacket.h | 134 ++++ .../LwIP/include/lwip/apps/MQTT/MQTTPublish.h | 38 + .../lwip/apps/MQTT/MQTTSerializePublish.c | 169 ++++ .../include/lwip/apps/MQTT/MQTTSubscribe.h | 39 + .../lwip/apps/MQTT/MQTTSubscribeClient.c | 137 ++++ .../lwip/apps/MQTT/MQTTSubscribeServer.c | 112 +++ .../include/lwip/apps/MQTT/MQTTUnsubscribe.h | 38 + .../lwip/apps/MQTT/MQTTUnsubscribeClient.c | 106 +++ .../lwip/apps/MQTT/MQTTUnsubscribeServer.c | 102 +++ .../LwIP/include/lwip/apps/MQTT/StackTrace.h | 78 ++ .../LwIP/include/lwip/apps/MQTT/transport.c | 102 +++ .../LwIP/include/lwip/apps/MQTT/transport.h | 45 ++ 25 files changed, 3510 insertions(+) create mode 100644 APP_Framework/Applications/app_test/test_hash.c create mode 100644 APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c create mode 100644 APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.h create mode 100644 APP_Framework/lib/cJSON/cJSON_Process.c create mode 100644 APP_Framework/lib/cJSON/cJSON_Process.h create mode 100644 Ubiquitous/XiZi_IIoT/kernel/include/xs_hash.h create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnect.h create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnectClient.c create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnectServer.c create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTDeserializePublish.c create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTFormat.c create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTFormat.h create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPacket.c create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPacket.h create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPublish.h create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSerializePublish.c create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribe.h create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribeClient.c create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribeServer.c create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribe.h create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribeClient.c create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribeServer.c create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/StackTrace.h create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/transport.c create mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/transport.h diff --git a/APP_Framework/Applications/app_test/test_hash.c b/APP_Framework/Applications/app_test/test_hash.c new file mode 100644 index 000000000..14539fc3e --- /dev/null +++ b/APP_Framework/Applications/app_test/test_hash.c @@ -0,0 +1,44 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: test_ethernet.c +* @brief: a application of ethernet function +* @version: 1.1 +* @author: AIIT XUOS Lab +* @date: 2022/12/17 +*/ +#include +#include +#include +#include + +int Testhash(void) +{ + Element a[]={{12,1},{2,2},{31,3},{45,4},{8,5},{45,5}}; + + int n = sizeof(a)/sizeof(Element); + Hash_table *h = Creat_Table(n); + int i = 0; + for(i = 0 ; idata->value); //查找key值为12的Element + printf("%d\n",h->length); //打印哈希表的元素个数 + Destroy_Table(h); // 摧毁哈希表 + + return 0; +} + +PRIV_SHELL_CMD_FUNCTION(Testhash, a hash test sample, PRIV_SHELL_CMD_MAIN_ATTR); \ No newline at end of file diff --git a/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c b/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c new file mode 100644 index 000000000..3592016e0 --- /dev/null +++ b/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c @@ -0,0 +1,726 @@ +#include +#include "lwip_mqtt_demo.h" + +#ifdef ADD_XIZI_FETURES +#include +#include +#include "lwip/sys.h" +#include "lwip/api.h" + +#include +#include +#include +#include + +#endif + +#ifdef ADD_NUTTX_FETURES +#include +#include +#include +#include "stdio.h" +#endif + + +#define MQTT_DEMO_BUF_SIZE 65535 +#define MQTT_DEMO_SEND_TIMES 20 +#define LWIP_MQTT_DEMO_TASK_STACK_SIZE 4096 +#define LWIP_MQTT_DEMO_TASK_PRIO 20 + +static char mqtt_demo_ipaddr[] = {192, 168, 131, 77}; +static char mqtt_demo_netmask[] = {255, 255, 254, 0}; +static char mqtt_demo_gwaddr[] = {192, 168, 131, 1}; + +static pthread_t mqtt_client_task; +static pthread_t mqtt_server_task; + +static uint16_t mqtt_socket_port = 1883; +static char mqtt_ip_str[128] = {192,168,100,1}; + +void MqttSocketConfigParam(char *ip_str) +{ + int ip1, ip2, ip3, ip4, port = 0; + + if(ip_str == NULL) + return; + + if(sscanf(ip_str, "%d.%d.%d.%d:%d", &ip1, &ip2, &ip3, &ip4, &port)) { + printf("config ip %s port %d\n", ip_str, port); + strcpy(mqtt_ip_str, ip_str); + if(port) + mqtt_socket_port = port; + return; + } + + if(sscanf(ip_str, "%d.%d.%d.%d", &ip1, &ip2, &ip3, &ip4)) { + printf("config ip %s\n", ip_str); + strcpy(mqtt_ip_str, ip_str); + } +} + +MQTT_USER_MSG mqtt_user_msg; + +uint8_t MQTT_Connect(void) +{ + MQTTPacket_connectData data = MQTTPacket_connectData_initializer; + uint8_t buf[200]; + int buflen = sizeof(buf); + int len = 0; + data.clientID.cstring = CLIENT_ID; //随机 + data.keepAliveInterval = KEEPLIVE_TIME; //保持活跃 + data.username.cstring = USER_NAME; //用户名 + data.password.cstring = PASSWORD; //密钥 + data.MQTTVersion = MQTT_VERSION; //3表示3.1版本，4表示3.11版本 + data.cleansession = 1; + //组装消息 + len = MQTTSerialize_connect((unsigned char *)buf, buflen, &data); + //发送消息 + transport_sendPacketBuffer(buf, len); + + /* 等待连接响应 */ + if (MQTTPacket_read(buf, buflen, transport_getdata) == CONNACK) + { + unsigned char sessionPresent, connack_rc; + if (MQTTDeserialize_connack(&sessionPresent, &connack_rc, buf, buflen) != 1 || connack_rc != 0) + { + lw_print("无法连接，错误代码是: %d！\n", connack_rc); + return Connect_NOK; + } + else + { + lw_print("用户名与密钥验证成功，MQTT连接成功！\n"); + return Connect_OK; + } + } + else + lw_print("MQTT连接无响应！\n"); + return Connect_NOTACK; +} + + +int32_t MQTT_PingReq(int32_t sock) +{ + int32_t len; + uint8_t buf[200]; + int32_t buflen = sizeof(buf); + fd_set readfd; + struct timeval tv; + tv.tv_sec = 5; + tv.tv_usec = 0; + + FD_ZERO(&readfd); + FD_SET(sock,&readfd); + + len = MQTTSerialize_pingreq(buf, buflen); + transport_sendPacketBuffer(buf, len); + + //等待可读事件 + if(select(sock+1,&readfd,NULL,NULL,&tv) == 0) + return -1; + + //有可读事件 + if(FD_ISSET(sock,&readfd) == 0) + return -2; + + if(MQTTPacket_read(buf, buflen, transport_getdata) != PINGRESP) + return -3; + + return 0; + +} + + +/************************************************************************ +** 函数名称: MQTTSubscribe +** 函数功能: 订阅消息 +** 入口参数: int32_t sock：套接字 +** int8_t *topic：主题 +** enum QoS pos：消息质量 +** 出口参数: >=0:发送成功 <0:发送失败 +** 备 注: +************************************************************************/ +int32_t MQTTSubscribe(int32_t sock,char *topic,enum QoS pos) +{ + static uint32_t PacketID = 0; + uint16_t packetidbk = 0; + int32_t conutbk = 0; + uint8_t buf[100]; + int32_t buflen = sizeof(buf); + MQTTString topicString = MQTTString_initializer; + int32_t len; + int32_t req_qos,qosbk; + + fd_set readfd; + struct timeval tv; + tv.tv_sec = 2; + tv.tv_usec = 0; + + FD_ZERO(&readfd); + FD_SET(sock,&readfd); + + //复制主题 + topicString.cstring = (char *)topic; + //订阅质量 + req_qos = pos; + + //串行化订阅消息 + len = MQTTSerialize_subscribe(buf, buflen, 0, PacketID++, 1, &topicString, &req_qos); + //发送TCP数据 + if(transport_sendPacketBuffer(buf, len) < 0) + return -1; + + //等待可读事件--等待超时 + if(select(sock+1,&readfd,NULL,NULL,&tv) == 0) + return -2; + //有可读事件--没有可读事件 + if(FD_ISSET(sock,&readfd) == 0) + return -3; + + //等待订阅返回--未收到订阅返回 + if(MQTTPacket_read(buf, buflen, transport_getdata) != SUBACK) + return -4; + + //拆订阅回应包 + if(MQTTDeserialize_suback(&packetidbk,1, &conutbk, &qosbk, buf, buflen) != 1) + return -5; + + //检测返回数据的正确性 + if((qosbk == 0x80)||(packetidbk != (PacketID-1))) + return -6; + + //订阅成功 + return 0; +} + +int32_t ReadPacketTimeout(int32_t sock,uint8_t *buf,int32_t buflen,uint32_t timeout) +{ + fd_set readfd; + struct timeval tv; + if(timeout != 0) + { + tv.tv_sec = timeout; + tv.tv_usec = 0; + FD_ZERO(&readfd); + FD_SET(sock,&readfd); + + + if(select(sock+1,&readfd,NULL,NULL,&tv) == 0) + return -1; + + if(FD_ISSET(sock,&readfd) == 0) + return -1; + } + + return MQTTPacket_read(buf, buflen, transport_getdata); +} + +void deliverMessage(MQTTString *TopicName,MQTTMessage *msg,MQTT_USER_MSG *mqtt_user_msg) +{ + //消息质量 + mqtt_user_msg->msgqos = msg->qos; + //保存消息 + memcpy(mqtt_user_msg->msg,msg->payload,msg->payloadlen); + mqtt_user_msg->msg[msg->payloadlen] = 0; + //保存消息长度 + mqtt_user_msg->msglenth = msg->payloadlen; + //消息主题 + memcpy((char *)mqtt_user_msg->topic,TopicName->lenstring.data,TopicName->lenstring.len); + mqtt_user_msg->topic[TopicName->lenstring.len] = 0; + //消息ID + mqtt_user_msg->packetid = msg->id; + //标明消息合法 + mqtt_user_msg->valid = 1; +} + +void UserMsgCtl(MQTT_USER_MSG *msg) +{ + //这里处理数据只是打印，用户可以在这里添加自己的处理方式 + lw_print("****收到订阅的消息******\n"); + //���غ�����Ϣ + switch(msg->msgqos) + { + case 0: + lw_print("MQTT>>消息质量QoS0\n"); + break; + case 1: + lw_print("MQTT>>消息质量QoS1\n"); + break; + case 2: + lw_print("MQTT>>消息质量QoS2\n"); + break; + default: + lw_print("MQTT>>错误的消息质量\n"); + break; + } + lw_print("MQTT>>消息主题：%s\n",msg->topic); + lw_print("MQTT>>消息内容：%s\n",msg->msg); + lw_print("MQTT>>消息长度：%d\n",msg->msglenth); + Proscess(msg->msg); + //处理完后销毁数据 + msg->valid = 0; +} + + +void mqtt_pktype_ctl(uint8_t packtype,uint8_t *buf,uint32_t buflen) +{ + MQTTMessage msg; + int32_t rc; + MQTTString receivedTopic; + uint32_t len; + lw_print("packtype:%d\n",packtype); + switch(packtype) + { + case PUBLISH: + + if(MQTTDeserialize_publish(&msg.dup,(int*)&msg.qos, &msg.retained, &msg.id, &receivedTopic, + (unsigned char **)&msg.payload, &msg.payloadlen, buf, buflen) != 1) + return; + + deliverMessage(&receivedTopic,&msg,&mqtt_user_msg); + + + if(msg.qos == QOS0) + { + //QOS0-不需要ACK + //直接处理数据 + UserMsgCtl(&mqtt_user_msg); + return; + } + //发送PUBACK消息 + if(msg.qos == QOS1) + { + len =MQTTSerialize_puback(buf,buflen,mqtt_user_msg.packetid); + if(len == 0) + return; + //发送返回 + if(transport_sendPacketBuffer(buf,len)<0) + return; + //返回后处理消息 + UserMsgCtl(&mqtt_user_msg); + return; + } + + //对于质量2,只需要发送PUBREC就可以了 + if(msg.qos == QOS2) + { + len = MQTTSerialize_ack(buf, buflen, PUBREC, 0, mqtt_user_msg.packetid); + if(len == 0) + return; + //发送返回 + transport_sendPacketBuffer(buf,len); + } + break; + case PUBREL: + //解析包数据，必须包ID相同才可以 + rc = MQTTDeserialize_ack(&msg.type,&msg.dup, &msg.id, buf,buflen); + if((rc != 1)||(msg.type != PUBREL)||(msg.id != mqtt_user_msg.packetid)) + return ; + //收到PUBREL，需要处理并抛弃数据 + if(mqtt_user_msg.valid == 1) + { + //返回后处理消息 + UserMsgCtl(&mqtt_user_msg); + } + //串行化PUBCMP消息 + len = MQTTSerialize_pubcomp(buf,buflen,msg.id); + if(len == 0) + return; + //发送返回--PUBCOMP + transport_sendPacketBuffer(buf,len); + break; + case PUBACK://等级1客户端推送数据后，服务器返回 + break; + case PUBREC://等级2客户端推送数据后，服务器返回 + break; + case PUBCOMP://等级2客户端推送PUBREL后，服务器返回 + break; + default: + break; + } +} + + +static void *MqttSocketRecvTask(void *arg) +{ + lw_print("Recv begin**********\n"); + int fd = -1, clientfd; + int recv_len; + int ret; + char *recv_buf; + struct sockaddr_in mqtt_addr; + socklen_t addr_len; + + fd = socket(AF_INET, SOCK_STREAM, 0); + if (fd < 0) { + lw_print("Socket error\n"); + return NULL; + } + + struct sockaddr_in mqtt_sock; + mqtt_sock.sin_family = AF_INET; + mqtt_sock.sin_port = htons(mqtt_socket_port); + mqtt_sock.sin_addr.s_addr = inet_addr(mqtt_ip_str); + + memset(&(mqtt_sock.sin_zero), 0, sizeof(mqtt_sock.sin_zero)); + + ret = connect(fd, (struct sockaddr *)&mqtt_sock, sizeof(struct sockaddr)); + + if (ret < 0) { + lw_print("Unable to connect %s:%d = %d\n", mqtt_ip_str, mqtt_socket_port, ret); + close(fd); + return NULL; + } + + lw_print("MQTT connect %s:%d success, begin to verify hostname and password.\n", mqtt_ip_str, mqtt_socket_port); + + if(MQTT_Connect() != Connect_OK) + { + lw_print("MQTT verify failed.\n"); + shutdown(fd, SHUT_WR); + recv(fd, NULL, (size_t)0, 0); + close(fd); + return NULL; + } + + lw_print("MQTT subscribe begin.\n"); + if(MQTTSubscribe(fd,(char *)TOPIC,QOS1) < 0) + { + lw_print("MQTT subscribe failed.\n"); + shutdown(fd, SHUT_WR); + recv(fd, NULL, (size_t)0, 0); + close(fd); + return NULL; + } + + lw_print("subscribe success.\n"); + + fd_set readfd; + uint8_t no_mqtt_msg_exchange = 1; + uint8_t buf[MSG_MAX_LEN]; + int32_t buflen = sizeof(buf); + int32_t type; + struct timeval tv; + tv.tv_sec = 0; + tv.tv_usec = 10; + + int32_t curtick=0; + + while(1) + { + // lw_print("waiting********\n"); + curtick +=1; + no_mqtt_msg_exchange = 1; + + FD_ZERO(&readfd); + FD_SET(fd,&readfd); + select(fd+1,&readfd,NULL,NULL,&tv); + + if(FD_ISSET(fd,&readfd) != 0) + { + + type = ReadPacketTimeout(fd,buf,buflen,0); + if(type != -1) + { + lw_print("ctl***********\n"); + mqtt_pktype_ctl(type,buf,buflen); + + no_mqtt_msg_exchange = 0; + + } + } + + if( curtick >(2*10000)) + { + curtick =0; + //判断是否有数据交换 + if(no_mqtt_msg_exchange == 0) + { + //如果有数据交换，这次就不需要发送PING消息 + continue; + } + + if(MQTT_PingReq(fd) < 0) + { + //重连服务器 + lw_print("发送保持活性ping失败....\n"); + goto CLOSE; + } + + + lw_print("发送保持活性ping作为心跳成功....\n"); + + no_mqtt_msg_exchange = 0; + } + } + +CLOSE: + lw_print("MQTT subscribe failed.\n"); + shutdown(fd, SHUT_WR); + recv(fd, NULL, (size_t)0, 0); + close(fd); + return NULL; + + +} + + + +void MqttSocketRecvTest(int argc, char *argv[]) +{ + if(argc >= 2) { + lw_print("lw: [%s] target ip %s\n", __func__, argv[1]); + MqttSocketConfigParam(argv[1]); + } + + + // ip4_addr_t dns_ip; + // netconn_gethostbyname(HOST_NAME, &dns_ip); + // char* host_ip = ip_ntoa(&dns_ip); + // lw_print("host name : %s , host_ip : %s\n",HOST_NAME,host_ip); + // MqttSocketConfigParam(host_ip); + + +#ifdef ADD_XIZI_FETURES + lwip_config_tcp(0, mqtt_demo_ipaddr, mqtt_demo_netmask, mqtt_demo_gwaddr); + + pthread_attr_t attr; + attr.schedparam.sched_priority = LWIP_MQTT_DEMO_TASK_PRIO; + attr.stacksize = LWIP_MQTT_DEMO_TASK_STACK_SIZE; +#endif + +#ifdef ADD_NUTTX_FETURES + pthread_attr_t attr = PTHREAD_ATTR_INITIALIZER; + attr.priority = LWIP_mqtt_DEMO_TASK_PRIO; + attr.stacksize = LWIP_mqtt_DEMO_TASK_STACK_SIZE; +#endif + + PrivTaskCreate(&mqtt_server_task, &attr, &MqttSocketRecvTask, NULL); + PrivTaskStartup(&mqtt_server_task); +} + +PRIV_SHELL_CMD_FUNCTION(MqttSocketRecvTest, a tcp send sample, PRIV_SHELL_CMD_MAIN_ATTR); + + +typedef struct +{ + uint8_t humi_high8bit; //ԭʼ���ݣ�ʪ�ȸ�8λ + uint8_t humi_low8bit; //ԭʼ���ݣ�ʪ�ȵ�8λ + uint8_t temp_high8bit; //ԭʼ���ݣ��¶ȸ�8λ + uint8_t temp_low8bit; //ԭʼ���ݣ��¶ȸ�8λ + uint8_t check_sum; //У��� + double humidity; //ʵ��ʪ�� + double temperature; //ʵ���¶� +} DHT11_Data_TypeDef; + + +uint16_t GetNextPackID(void) +{ + static uint16_t pubpacketid = 0; + return pubpacketid++; +} + +int32_t WaitForPacket(int32_t sock,uint8_t packettype,uint8_t times) +{ + int32_t type; + uint8_t buf[MSG_MAX_LEN]; + uint8_t n = 0; + int32_t buflen = sizeof(buf); + do + { + //读取数据包 + type = ReadPacketTimeout(sock,buf,buflen,2); + if(type != -1) + mqtt_pktype_ctl(type,buf,buflen); + n++; + }while((type != packettype)&&(n < times)); + //收到期望的包 + if(type == packettype) + return 0; + else + return -1; +} + +int32_t MQTTMsgPublish(int32_t sock, char *topic, int8_t qos, uint8_t* msg) +{ + int8_t retained = 0; //保留标志位 + uint32_t msg_len; //数据长度 + uint8_t buf[MSG_MAX_LEN]; + int32_t buflen = sizeof(buf),len; + MQTTString topicString = MQTTString_initializer; + uint16_t packid = 0,packetidbk; + + //填充主题 + topicString.cstring = (char *)topic; + + //填充数据包ID + if((qos == QOS1)||(qos == QOS2)) + { + packid = GetNextPackID(); + } + else + { + qos = QOS0; + retained = 0; + packid = 0; + } + + msg_len = strlen((char *)msg); + + //推送消息 + len = MQTTSerialize_publish(buf, buflen, 0, qos, retained, packid, topicString, (unsigned char*)msg, msg_len); + if(len <= 0) + return -1; + if(transport_sendPacketBuffer(buf, len) < 0) + return -2; + + //质量等级0，不需要返回 + if(qos == QOS0) + { + return 0; + } + + //等级1 + if(qos == QOS1) + { + //等待PUBACK + if(WaitForPacket(sock,PUBACK,5) < 0) + return -3; + return 1; + + } + //等级2 + if(qos == QOS2) + { + //等待PUBREC + if(WaitForPacket(sock,PUBREC,5) < 0) + return -3; + //发送PUBREL + len = MQTTSerialize_pubrel(buf, buflen,0, packetidbk); + if(len == 0) + return -4; + if(transport_sendPacketBuffer(buf, len) < 0) + return -6; + //等待PUBCOMP + if(WaitForPacket(sock,PUBREC,5) < 0) + return -7; + return 2; + } + //等级错误 + return -8; +} + + +static void *MqttSocketSendTask(void *arg) +{ + + int fd = -1, clientfd; + int recv_len; + int ret; + char *recv_buf; + struct sockaddr_in mqtt_addr; + socklen_t addr_len; + + fd = socket(AF_INET, SOCK_STREAM, 0); + if (fd < 0) { + lw_print("Socket error\n"); + return NULL; + } + + struct sockaddr_in mqtt_sock; + mqtt_sock.sin_family = AF_INET; + mqtt_sock.sin_port = htons(mqtt_socket_port); + mqtt_sock.sin_addr.s_addr = inet_addr(mqtt_ip_str); + + memset(&(mqtt_sock.sin_zero), 0, sizeof(mqtt_sock.sin_zero)); + + ret = connect(fd, (struct sockaddr *)&mqtt_sock, sizeof(struct sockaddr)); + + if (ret < 0) { + lw_print("Unable to connect %s:%d = %d\n", mqtt_ip_str, mqtt_socket_port, ret); + close(fd); + return NULL; + } + + lw_print("MQTT connect %s:%d success, begin to verify hostname and password.\n", mqtt_ip_str, mqtt_socket_port); + + if(MQTT_Connect() != Connect_OK) + { + lw_print("MQTT verify failed.\n"); + shutdown(fd, SHUT_WR); + recv(fd, NULL, (size_t)0, 0); + close(fd); + return NULL; + } + + lw_print("MQTT subscribe begin.\n"); + if(MQTTSubscribe(fd,(char *)TOPIC,QOS1) < 0) + { + lw_print("MQTT subscribe failed.\n"); + shutdown(fd, SHUT_WR); + recv(fd, NULL, (size_t)0, 0); + close(fd); + return NULL; + } + + lw_print("subscribe success.\n"); + + + + uint8_t no_mqtt_msg_exchange = 1; + uint32_t curtick=0; + uint8_t res; + + cJSON* cJSON_Data = NULL; + cJSON_Data = cJSON_Data_Init(); + DHT11_Data_TypeDef* recv_data; + + double a,b; + while(1) + { + curtick+=1; + char* p ="Hello,here is hc"; + ret = MQTTMsgPublish(fd,(char*)TOPIC,QOS0,(uint8_t*)p); + if(ret >= 0) + { + no_mqtt_msg_exchange = 0; + PrivTaskDelay(1000); + } + } +} + + +void MqttSocketSendTest(int argc, char *argv[]) +{ + if(argc >= 2) { + lw_print("lw: [%s] target ip %s\n", __func__, argv[1]); + MqttSocketConfigParam(argv[1]); + } + + + // ip4_addr_t dns_ip; + // netconn_gethostbyname(HOST_NAME, &dns_ip); + // char* host_ip = ip_ntoa(&dns_ip); + // lw_print("host name : %s , host_ip : %s\n",HOST_NAME,host_ip); + // MqttSocketConfigParam(host_ip); + + +#ifdef ADD_XIZI_FETURES + lwip_config_tcp(0, mqtt_demo_ipaddr, mqtt_demo_netmask, mqtt_demo_gwaddr); + + pthread_attr_t attr; + attr.schedparam.sched_priority = LWIP_MQTT_DEMO_TASK_PRIO; + attr.stacksize = LWIP_MQTT_DEMO_TASK_STACK_SIZE; +#endif + +#ifdef ADD_NUTTX_FETURES + pthread_attr_t attr = PTHREAD_ATTR_INITIALIZER; + attr.priority = LWIP_mqtt_DEMO_TASK_PRIO; + attr.stacksize = LWIP_mqtt_DEMO_TASK_STACK_SIZE; +#endif + + PrivTaskCreate(&mqtt_client_task, &attr, &MqttSocketSendTask, NULL); + PrivTaskStartup(&mqtt_client_task); +} + +PRIV_SHELL_CMD_FUNCTION(MqttSocketSendTest, a tcp send sample, PRIV_SHELL_CMD_MAIN_ATTR); + diff --git a/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.h b/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.h new file mode 100644 index 000000000..f1a68e95a --- /dev/null +++ b/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.h @@ -0,0 +1,71 @@ +#include + +#define MSG_MAX_LEN 500 +#define MSG_TOPIC_LEN 50 +#define KEEPLIVE_TIME 50 +#define MQTT_VERSION 4 + +#ifdef LWIP_DNS +#define HOST_NAME "iot-06z00im0uwa0ki2.mqtt.iothub.aliyuncs.com" //服务器域名 +#else +#define HOST_NAME "iot-06z00im0uwa0ki2.mqtt.iothub.aliyuncs.com" //服务器IP地址 +#endif + + +//#define HOST_IP "129.204.201.235" +#define HOST_PORT 1883 //由于是TCP连接，端口必须是1883 + +#define CLIENT_ID "mqttx_24d1dccf" //随机的id +#define USER_NAME "test" //用户名 +#define PASSWORD "hc123456" //秘钥 + +#define TOPIC "temp" //订阅的主题 + +#define TEST_MESSAGE "test_message" //发送测试消息 + +enum QoS +{ QOS0 = 0, + QOS1, + QOS2 +}; + +enum MQTT_Connect +{ + Connect_OK = 0, + Connect_NOK, + Connect_NOTACK +}; + +//数据交互结构体 +typedef struct __MQTTMessage +{ + uint32_t qos; + uint8_t retained; + uint8_t dup; + uint16_t id; + uint8_t type; + void *payload; + int32_t payloadlen; +}MQTTMessage; + +//用户接收消息结构体 +typedef struct __MQTT_MSG +{ + uint8_t msgqos; //消息质量 + uint8_t msg[MSG_MAX_LEN]; //消息 + uint32_t msglenth; //消息长度 + uint8_t topic[MSG_TOPIC_LEN]; //主题 + uint16_t packetid; //消息ID + uint8_t valid; //标明消息是否有效 +}MQTT_USER_MSG; + +//发送消息结构体 +typedef struct +{ + int8_t topic[MSG_TOPIC_LEN]; + int8_t qos; + int8_t retained; + + uint8_t msg[MSG_MAX_LEN]; + uint8_t msglen; +} mqtt_recv_msg_t, *p_mqtt_recv_msg_t, mqtt_send_msg_t, *p_mqtt_send_msg_t; \ No newline at end of file diff --git a/APP_Framework/lib/cJSON/cJSON_Process.c b/APP_Framework/lib/cJSON/cJSON_Process.c new file mode 100644 index 000000000..6e2aa9c1e --- /dev/null +++ b/APP_Framework/lib/cJSON/cJSON_Process.c @@ -0,0 +1,85 @@ +#include "cJSON_Process.h" +#include + + + + + +cJSON* cJSON_Data_Init(void) +{ + cJSON* cJSON_Root = NULL; //json根节点 + + + cJSON_Root = cJSON_CreateObject(); /*创建项目*/ + if(NULL == cJSON_Root) + { + return NULL; + } + cJSON_AddStringToObject(cJSON_Root, NAME, DEFAULT_NAME); /*添加元素 键值对*/ + cJSON_AddNumberToObject(cJSON_Root, TEMP_NUM, DEFAULT_TEMP_NUM); + cJSON_AddNumberToObject(cJSON_Root, HUM_NUM, DEFAULT_HUM_NUM); + + char* p = cJSON_Print(cJSON_Root); /*p 指向的字符串是json格式的*/ + + p = NULL; + + return cJSON_Root; + +} +uint8_t cJSON_Update(const cJSON * const object,const char * const string,void *d) +{ + cJSON* node = NULL; //json根节点 + node = cJSON_GetObjectItem(object,string); + if(node == NULL) + return 0; + if(cJSON_IsBool(node)) + { + int *b = (int*)d; + + cJSON_GetObjectItem(object,string)->type = *b ? cJSON_True : cJSON_False; + + return 1; + } + else if(cJSON_IsString(node)) + { + cJSON_GetObjectItem(object,string)->valuestring = (char*)d; + + return 1; + } + else if(cJSON_IsNumber(node)) + { + double *num = (double*)d; + + cJSON_GetObjectItem(object,string)->valuedouble = (double)*num; + + return 1; + } + else + return 1; +} + +void Proscess(void* data) +{ + lw_print("��ʼ����JSON����"); + cJSON *root,*json_name,*json_temp_num,*json_hum_num; + root = cJSON_Parse((char*)data); //解析成json形式 + + json_name = cJSON_GetObjectItem( root , NAME); //获取键值内容 + json_temp_num = cJSON_GetObjectItem( root , TEMP_NUM ); + json_hum_num = cJSON_GetObjectItem( root , HUM_NUM ); + + lw_print("name:%s\n temp_num:%f\n hum_num:%f\n", + json_name->valuestring, + json_temp_num->valuedouble, + json_hum_num->valuedouble); + + cJSON_Delete(root); //释放内存 +} + + + + + + + + diff --git a/APP_Framework/lib/cJSON/cJSON_Process.h b/APP_Framework/lib/cJSON/cJSON_Process.h new file mode 100644 index 000000000..5dcdd3bf5 --- /dev/null +++ b/APP_Framework/lib/cJSON/cJSON_Process.h @@ -0,0 +1,23 @@ +#ifndef _CJSON_PROCESS_H_ +#define _CJSON_PROCESS_H_ +#include "cJSON.h" +#include "stdint.h" + + +#define NAME "name" +#define TEMP_NUM "temp" +#define HUM_NUM "hum" + +#define DEFAULT_NAME "fire" +#define DEFAULT_TEMP_NUM 25.0 +#define DEFAULT_HUM_NUM 50.0 + + +#define UPDATE_SUCCESS 1 +#define UPDATE_FAIL 0 + +cJSON* cJSON_Data_Init(void); +uint8_t cJSON_Update(const cJSON * const object,const char * const string,void * d); +void Proscess(void* data); +#endif + diff --git a/Ubiquitous/XiZi_IIoT/kernel/include/xs_hash.h b/Ubiquitous/XiZi_IIoT/kernel/include/xs_hash.h new file mode 100644 index 000000000..4423d9573 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/kernel/include/xs_hash.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** +* @file: xs_hash.h +* @brief: hash table +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2023/7/10 +* +*/ + +#include +#include +#include +#include "xs_base.h" + +#define REMAINDER 11 + +typedef struct element +{ + uint8_t key; + uint8_t value; + uint8_t hash; +}Element; + + +typedef struct Pnode +{ + Element *data; + struct Pnode *next; +}Node; + + +typedef struct hash_table +{ + uint8_t size; + uint8_t length; + struct Pnode *head; +}Hash_table; + + +Hash_table* Creat_Table(int table_size) +{ + Hash_table *h = (Hash_table *)malloc(sizeof(Hash_table)); + h->size = REMAINDER; + h->head = (Node *)malloc((h->size)*sizeof(Node)); + h->length = 0; + int i = 0; + for(i=0 ; isize ; i++) + { + h->head[i].next = NULL; + } + return h; +} + +int hash(int value) +{ + return value%REMAINDER; +} + +Node *lookup(Hash_table *h , int key) +{ + int i; + i = hash(key); + Node * p = h->head[i].next; + while(p && key != p->data->key) + { + p = p->next; + } + + return p; +} + + + +void Insert(Hash_table *h , Element k) +{ + Node * p = lookup(h,k.key); + if(!p) + { + Node *q = (Node *)malloc(sizeof(Node)); + q->data = (Element *)malloc(sizeof(Element)); + (q->data)->key = k.key; + (q->data)->value = k.value; + int position; + position = (q->data)->hash = hash(k.key); + q->next = h->head[position].next; + h->head[position].next = q; + + h->length += 1; + return ; + } + else + { + printf("The keys is exist !\n"); + return ; + } +} + +void Destroy_Table(Hash_table *h) +{ + int i; + Node *p , *q; + for(i=0 ; isize ; i++) + { + p = h->head[i].next; + while(p) + { + q=p->next; + free(p); + p=q; + } + } + free(h->head); + free(h); +} + + +void print_Table(Hash_table *h) +{ + int i = 0; + for (i = 0; i < h->size ; i++) + { + Node * p = h->head[i].next; + while (p) + { + printf("[%d-%d] ",p->data->key, p->data->value); + p = p->next; + } + printf("NULL\n"); + } +} + + diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnect.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnect.h new file mode 100644 index 000000000..4d247a3c2 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnect.h @@ -0,0 +1,137 @@ +/******************************************************************************* + * Copyright (c) 2014, 2017 IBM Corp. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * and Eclipse Distribution License v1.0 which accompany this distribution. + * + * The Eclipse Public License is available at + * http://www.eclipse.org/legal/epl-v10.html + * and the Eclipse Distribution License is available at + * http://www.eclipse.org/org/documents/edl-v10.php. + * + * Contributors: + * Ian Craggs - initial API and implementation and/or initial documentation + * Xiang Rong - 442039 Add makefile to Embedded C client + * Ian Craggs - fix for issue #64, bit order in connack response + *******************************************************************************/ + +#ifndef MQTTCONNECT_H_ +#define MQTTCONNECT_H_ + +#if !defined(DLLImport) + #define DLLImport +#endif +#if !defined(DLLExport) + #define DLLExport +#endif + + +typedef union +{ + unsigned char all; /**< all connect flags */ +#if defined(REVERSED) + struct + { + unsigned int username : 1; /**< 3.1 user name */ + unsigned int password : 1; /**< 3.1 password */ + unsigned int willRetain : 1; /**< will retain setting */ + unsigned int willQoS : 2; /**< will QoS value */ + unsigned int will : 1; /**< will flag */ + unsigned int cleansession : 1; /**< clean session flag */ + unsigned int : 1; /**< unused */ + } bits; +#else + struct + { + unsigned int : 1; /**< unused */ + unsigned int cleansession : 1; /**< cleansession flag */ + unsigned int will : 1; /**< will flag */ + unsigned int willQoS : 2; /**< will QoS value */ + unsigned int willRetain : 1; /**< will retain setting */ + unsigned int password : 1; /**< 3.1 password */ + unsigned int username : 1; /**< 3.1 user name */ + } bits; +#endif +} MQTTConnectFlags; /**< connect flags byte */ + + + +/** + * Defines the MQTT "Last Will and Testament" (LWT) settings for + * the connect packet. + */ +typedef struct +{ + /** The eyecatcher for this structure. must be MQTW. */ + char struct_id[4]; + /** The version number of this structure. Must be 0 */ + int struct_version; + /** The LWT topic to which the LWT message will be published. */ + MQTTString topicName; + /** The LWT payload. */ + MQTTString message; + /** + * The retained flag for the LWT message (see MQTTAsync_message.retained). + */ + unsigned char retained; + /** + * The quality of service setting for the LWT message (see + * MQTTAsync_message.qos and @ref qos). + */ + char qos; +} MQTTPacket_willOptions; + + +#define MQTTPacket_willOptions_initializer { {'M', 'Q', 'T', 'W'}, 0, {NULL, {0, NULL}}, {NULL, {0, NULL}}, 0, 0 } + + +typedef struct +{ + /** The eyecatcher for this structure. must be MQTC. */ + char struct_id[4]; + /** The version number of this structure. Must be 0 */ + int struct_version; + /** Version of MQTT to be used. 3 = 3.1 4 = 3.1.1 + */ + unsigned char MQTTVersion; + MQTTString clientID; + unsigned short keepAliveInterval; + unsigned char cleansession; + unsigned char willFlag; + MQTTPacket_willOptions will; + MQTTString username; + MQTTString password; +} MQTTPacket_connectData; + +typedef union +{ + unsigned char all; /**< all connack flags */ +#if defined(REVERSED) + struct + { + unsigned int reserved : 7; /**< unused */ + unsigned int sessionpresent : 1; /**< session present flag */ + } bits; +#else + struct + { + unsigned int sessionpresent : 1; /**< session present flag */ + unsigned int reserved: 7; /**< unused */ + } bits; +#endif +} MQTTConnackFlags; /**< connack flags byte */ + +#define MQTTPacket_connectData_initializer { {'M', 'Q', 'T', 'C'}, 0, 4, {NULL, {0, NULL}}, 60, 1, 0, \ + MQTTPacket_willOptions_initializer, {NULL, {0, NULL}}, {NULL, {0, NULL}} } + +DLLExport int MQTTSerialize_connect(unsigned char* buf, int buflen, MQTTPacket_connectData* options); +DLLExport int MQTTDeserialize_connect(MQTTPacket_connectData* data, unsigned char* buf, int len); + +DLLExport int MQTTSerialize_connack(unsigned char* buf, int buflen, unsigned char connack_rc, unsigned char sessionPresent); +DLLExport int MQTTDeserialize_connack(unsigned char* sessionPresent, unsigned char* connack_rc, unsigned char* buf, int buflen); + +DLLExport int MQTTSerialize_disconnect(unsigned char* buf, int buflen); +DLLExport int MQTTSerialize_pingreq(unsigned char* buf, int buflen); + +#endif /* MQTTCONNECT_H_ */ diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnectClient.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnectClient.c new file mode 100644 index 000000000..5f3cc2963 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnectClient.c @@ -0,0 +1,214 @@ +/******************************************************************************* + * Copyright (c) 2014 IBM Corp. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * and Eclipse Distribution License v1.0 which accompany this distribution. + * + * The Eclipse Public License is available at + * http://www.eclipse.org/legal/epl-v10.html + * and the Eclipse Distribution License is available at + * http://www.eclipse.org/org/documents/edl-v10.php. + * + * Contributors: + * Ian Craggs - initial API and implementation and/or initial documentation + *******************************************************************************/ + +#include "MQTTPacket.h" +#include "StackTrace.h" + +#include + +/** + * Determines the length of the MQTT connect packet that would be produced using the supplied connect options. + * @param options the options to be used to build the connect packet + * @return the length of buffer needed to contain the serialized version of the packet + */ +int MQTTSerialize_connectLength(MQTTPacket_connectData* options) +{ + int len = 0; + + FUNC_ENTRY; + + if (options->MQTTVersion == 3) + len = 12; /* variable depending on MQTT or MQIsdp */ + else if (options->MQTTVersion == 4) + len = 10; + + len += MQTTstrlen(options->clientID)+2; + if (options->willFlag) + len += MQTTstrlen(options->will.topicName)+2 + MQTTstrlen(options->will.message)+2; + if (options->username.cstring || options->username.lenstring.data) + len += MQTTstrlen(options->username)+2; + if (options->password.cstring || options->password.lenstring.data) + len += MQTTstrlen(options->password)+2; + + FUNC_EXIT_RC(len); + return len; +} + + +/** + * Serializes the connect options into the buffer. + * @param buf the buffer into which the packet will be serialized + * @param len the length in bytes of the supplied buffer + * @param options the options to be used to build the connect packet + * @return serialized length, or error if 0 + */ +int MQTTSerialize_connect(unsigned char* buf, int buflen, MQTTPacket_connectData* options) +{ + unsigned char *ptr = buf; + MQTTHeader header = {0}; + MQTTConnectFlags flags = {0}; + int len = 0; + int rc = -1; + + FUNC_ENTRY; + if (MQTTPacket_len(len = MQTTSerialize_connectLength(options)) > buflen) + { + rc = MQTTPACKET_BUFFER_TOO_SHORT; + goto exit; + } + + header.byte = 0; + header.bits.type = CONNECT; + writeChar(&ptr, header.byte); /* write header */ + + ptr += MQTTPacket_encode(ptr, len); /* write remaining length */ + + if (options->MQTTVersion == 4) + { + writeCString(&ptr, "MQTT"); + writeChar(&ptr, (char) 4); + } + else + { + writeCString(&ptr, "MQIsdp"); + writeChar(&ptr, (char) 3); + } + + flags.all = 0; + flags.bits.cleansession = options->cleansession; + flags.bits.will = (options->willFlag) ? 1 : 0; + if (flags.bits.will) + { + flags.bits.willQoS = options->will.qos; + flags.bits.willRetain = options->will.retained; + } + + if (options->username.cstring || options->username.lenstring.data) + flags.bits.username = 1; + if (options->password.cstring || options->password.lenstring.data) + flags.bits.password = 1; + + writeChar(&ptr, flags.all); + writeInt(&ptr, options->keepAliveInterval); + writeMQTTString(&ptr, options->clientID); + if (options->willFlag) + { + writeMQTTString(&ptr, options->will.topicName); + writeMQTTString(&ptr, options->will.message); + } + if (flags.bits.username) + writeMQTTString(&ptr, options->username); + if (flags.bits.password) + writeMQTTString(&ptr, options->password); + + rc = ptr - buf; + + exit: FUNC_EXIT_RC(rc); + return rc; +} + + +/** + * Deserializes the supplied (wire) buffer into connack data - return code + * @param sessionPresent the session present flag returned (only for MQTT 3.1.1) + * @param connack_rc returned integer value of the connack return code + * @param buf the raw buffer data, of the correct length determined by the remaining length field + * @param len the length in bytes of the data in the supplied buffer + * @return error code. 1 is success, 0 is failure + */ +int MQTTDeserialize_connack(unsigned char* sessionPresent, unsigned char* connack_rc, unsigned char* buf, int buflen) +{ + MQTTHeader header = {0}; + unsigned char* curdata = buf; + unsigned char* enddata = NULL; + int rc = 0; + int mylen; + MQTTConnackFlags flags = {0}; + + FUNC_ENTRY; + header.byte = readChar(&curdata); + if (header.bits.type != CONNACK) + goto exit; + + curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ + enddata = curdata + mylen; + if (enddata - curdata < 2) + goto exit; + + flags.all = readChar(&curdata); + *sessionPresent = flags.bits.sessionpresent; + *connack_rc = readChar(&curdata); + + rc = 1; +exit: + FUNC_EXIT_RC(rc); + return rc; +} + + +/** + * Serializes a 0-length packet into the supplied buffer, ready for writing to a socket + * @param buf the buffer into which the packet will be serialized + * @param buflen the length in bytes of the supplied buffer, to avoid overruns + * @param packettype the message type + * @return serialized length, or error if 0 + */ +int MQTTSerialize_zero(unsigned char* buf, int buflen, unsigned char packettype) +{ + MQTTHeader header = {0}; + int rc = -1; + unsigned char *ptr = buf; + + FUNC_ENTRY; + if (buflen < 2) + { + rc = MQTTPACKET_BUFFER_TOO_SHORT; + goto exit; + } + header.byte = 0; + header.bits.type = packettype; + writeChar(&ptr, header.byte); /* write header */ + + ptr += MQTTPacket_encode(ptr, 0); /* write remaining length */ + rc = ptr - buf; +exit: + FUNC_EXIT_RC(rc); + return rc; +} + + +/** + * Serializes a disconnect packet into the supplied buffer, ready for writing to a socket + * @param buf the buffer into which the packet will be serialized + * @param buflen the length in bytes of the supplied buffer, to avoid overruns + * @return serialized length, or error if 0 + */ +int MQTTSerialize_disconnect(unsigned char* buf, int buflen) +{ + return MQTTSerialize_zero(buf, buflen, DISCONNECT); +} + + +/** + * Serializes a disconnect packet into the supplied buffer, ready for writing to a socket + * @param buf the buffer into which the packet will be serialized + * @param buflen the length in bytes of the supplied buffer, to avoid overruns + * @return serialized length, or error if 0 + */ +int MQTTSerialize_pingreq(unsigned char* buf, int buflen) +{ + return MQTTSerialize_zero(buf, buflen, PINGREQ); +} diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnectServer.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnectServer.c new file mode 100644 index 000000000..07c7cb537 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnectServer.c @@ -0,0 +1,148 @@ +/******************************************************************************* + * Copyright (c) 2014 IBM Corp. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * and Eclipse Distribution License v1.0 which accompany this distribution. + * + * The Eclipse Public License is available at + * http://www.eclipse.org/legal/epl-v10.html + * and the Eclipse Distribution License is available at + * http://www.eclipse.org/org/documents/edl-v10.php. + * + * Contributors: + * Ian Craggs - initial API and implementation and/or initial documentation + *******************************************************************************/ + +#include "StackTrace.h" +#include "MQTTPacket.h" +#include + +#define min(a, b) ((a < b) ? a : b) + + +/** + * Validates MQTT protocol name and version combinations + * @param protocol the MQTT protocol name as an MQTTString + * @param version the MQTT protocol version number, as in the connect packet + * @return correct MQTT combination? 1 is true, 0 is false + */ +int MQTTPacket_checkVersion(MQTTString* protocol, int version) +{ + int rc = 0; + + if (version == 3 && memcmp(protocol->lenstring.data, "MQIsdp", + min(6, protocol->lenstring.len)) == 0) + rc = 1; + else if (version == 4 && memcmp(protocol->lenstring.data, "MQTT", + min(4, protocol->lenstring.len)) == 0) + rc = 1; + return rc; +} + + +/** + * Deserializes the supplied (wire) buffer into connect data structure + * @param data the connect data structure to be filled out + * @param buf the raw buffer data, of the correct length determined by the remaining length field + * @param len the length in bytes of the data in the supplied buffer + * @return error code. 1 is success, 0 is failure + */ +int MQTTDeserialize_connect(MQTTPacket_connectData* data, unsigned char* buf, int len) +{ + MQTTHeader header = {0}; + MQTTConnectFlags flags = {0}; + unsigned char* curdata = buf; + unsigned char* enddata = &buf[len]; + int rc = 0; + MQTTString Protocol; + int version; + int mylen = 0; + + FUNC_ENTRY; + header.byte = readChar(&curdata); + if (header.bits.type != CONNECT) + goto exit; + + curdata += MQTTPacket_decodeBuf(curdata, &mylen); /* read remaining length */ + + if (!readMQTTLenString(&Protocol, &curdata, enddata) || + enddata - curdata < 0) /* do we have enough data to read the protocol version byte? */ + goto exit; + + version = (int)readChar(&curdata); /* Protocol version */ + /* If we don't recognize the protocol version, we don't parse the connect packet on the + * basis that we don't know what the format will be. + */ + if (MQTTPacket_checkVersion(&Protocol, version)) + { + flags.all = readChar(&curdata); + data->cleansession = flags.bits.cleansession; + data->keepAliveInterval = readInt(&curdata); + if (!readMQTTLenString(&data->clientID, &curdata, enddata)) + goto exit; + data->willFlag = flags.bits.will; + if (flags.bits.will) + { + data->will.qos = flags.bits.willQoS; + data->will.retained = flags.bits.willRetain; + if (!readMQTTLenString(&data->will.topicName, &curdata, enddata) || + !readMQTTLenString(&data->will.message, &curdata, enddata)) + goto exit; + } + if (flags.bits.username) + { + if (enddata - curdata < 3 || !readMQTTLenString(&data->username, &curdata, enddata)) + goto exit; /* username flag set, but no username supplied - invalid */ + if (flags.bits.password && + (enddata - curdata < 3 || !readMQTTLenString(&data->password, &curdata, enddata))) + goto exit; /* password flag set, but no password supplied - invalid */ + } + else if (flags.bits.password) + goto exit; /* password flag set without username - invalid */ + rc = 1; + } +exit: + FUNC_EXIT_RC(rc); + return rc; +} + + +/** + * Serializes the connack packet into the supplied buffer. + * @param buf the buffer into which the packet will be serialized + * @param buflen the length in bytes of the supplied buffer + * @param connack_rc the integer connack return code to be used + * @param sessionPresent the MQTT 3.1.1 sessionPresent flag + * @return serialized length, or error if 0 + */ +int MQTTSerialize_connack(unsigned char* buf, int buflen, unsigned char connack_rc, unsigned char sessionPresent) +{ + MQTTHeader header = {0}; + int rc = 0; + unsigned char *ptr = buf; + MQTTConnackFlags flags = {0}; + + FUNC_ENTRY; + if (buflen < 2) + { + rc = MQTTPACKET_BUFFER_TOO_SHORT; + goto exit; + } + header.byte = 0; + header.bits.type = CONNACK; + writeChar(&ptr, header.byte); /* write header */ + + ptr += MQTTPacket_encode(ptr, 2); /* write remaining length */ + + flags.all = 0; + flags.bits.sessionpresent = sessionPresent; + writeChar(&ptr, flags.all); + writeChar(&ptr, connack_rc); + + rc = ptr - buf; +exit: + FUNC_EXIT_RC(rc); + return rc; +} + diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTDeserializePublish.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTDeserializePublish.c new file mode 100644 index 000000000..5014c46d3 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTDeserializePublish.c @@ -0,0 +1,107 @@ +/******************************************************************************* + * Copyright (c) 2014 IBM Corp. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * and Eclipse Distribution License v1.0 which accompany this distribution. + * + * The Eclipse Public License is available at + * http://www.eclipse.org/legal/epl-v10.html + * and the Eclipse Distribution License is available at + * http://www.eclipse.org/org/documents/edl-v10.php. + * + * Contributors: + * Ian Craggs - initial API and implementation and/or initial documentation + *******************************************************************************/ + +#include "StackTrace.h" +#include "MQTTPacket.h" +#include + +#define min(a, b) ((a < b) ? 1 : 0) + +/** + * Deserializes the supplied (wire) buffer into publish data + * @param dup returned integer - the MQTT dup flag + * @param qos returned integer - the MQTT QoS value + * @param retained returned integer - the MQTT retained flag + * @param packetid returned integer - the MQTT packet identifier + * @param topicName returned MQTTString - the MQTT topic in the publish + * @param payload returned byte buffer - the MQTT publish payload + * @param payloadlen returned integer - the length of the MQTT payload + * @param buf the raw buffer data, of the correct length determined by the remaining length field + * @param buflen the length in bytes of the data in the supplied buffer + * @return error code. 1 is success + */ +int MQTTDeserialize_publish(unsigned char* dup, int* qos, unsigned char* retained, unsigned short* packetid, MQTTString* topicName, + unsigned char** payload, int32_t* payloadlen, unsigned char* buf, int buflen) +{ + MQTTHeader header = {0}; + unsigned char* curdata = buf; + unsigned char* enddata = NULL; + int rc = 0; + int mylen = 0; + + FUNC_ENTRY; + header.byte = readChar(&curdata); + if (header.bits.type != PUBLISH) + goto exit; + *dup = header.bits.dup; + *qos = header.bits.qos; + *retained = header.bits.retain; + + curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ + enddata = curdata + mylen; + + if (!readMQTTLenString(topicName, &curdata, enddata) || + enddata - curdata < 0) /* do we have enough data to read the protocol version byte? */ + goto exit; + + if (*qos > 0) + *packetid = readInt(&curdata); + + *payloadlen = enddata - curdata; + *payload = curdata; + rc = 1; +exit: + FUNC_EXIT_RC(rc); + return rc; +} + + + +/** + * Deserializes the supplied (wire) buffer into an ack + * @param packettype returned integer - the MQTT packet type + * @param dup returned integer - the MQTT dup flag + * @param packetid returned integer - the MQTT packet identifier + * @param buf the raw buffer data, of the correct length determined by the remaining length field + * @param buflen the length in bytes of the data in the supplied buffer + * @return error code. 1 is success, 0 is failure + */ +int MQTTDeserialize_ack(unsigned char* packettype, unsigned char* dup, unsigned short* packetid, unsigned char* buf, int buflen) +{ + MQTTHeader header = {0}; + unsigned char* curdata = buf; + unsigned char* enddata = NULL; + int rc = 0; + int mylen; + + FUNC_ENTRY; + header.byte = readChar(&curdata); + *dup = header.bits.dup; + *packettype = header.bits.type; + + curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ + enddata = curdata + mylen; + + if (enddata - curdata < 2) + goto exit; + *packetid = readInt(&curdata); + + rc = 1; +exit: + FUNC_EXIT_RC(rc); + return rc; +} + diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTFormat.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTFormat.c new file mode 100644 index 000000000..2eff31f89 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTFormat.c @@ -0,0 +1,262 @@ +/******************************************************************************* + * Copyright (c) 2014 IBM Corp. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * and Eclipse Distribution License v1.0 which accompany this distribution. + * + * The Eclipse Public License is available at + * http://www.eclipse.org/legal/epl-v10.html + * and the Eclipse Distribution License is available at + * http://www.eclipse.org/org/documents/edl-v10.php. + * + * Contributors: + * Ian Craggs - initial API and implementation and/or initial documentation + *******************************************************************************/ + +#include "StackTrace.h" +#include "MQTTPacket.h" + +#include + + +const char* MQTTPacket_names[] = +{ + "RESERVED", "CONNECT", "CONNACK", "PUBLISH", "PUBACK", "PUBREC", "PUBREL", + "PUBCOMP", "SUBSCRIBE", "SUBACK", "UNSUBSCRIBE", "UNSUBACK", + "PINGREQ", "PINGRESP", "DISCONNECT" +}; + + +const char* MQTTPacket_getName(unsigned short packetid) +{ + return MQTTPacket_names[packetid]; +} + + +int MQTTStringFormat_connect(char* strbuf, int strbuflen, MQTTPacket_connectData* data) +{ + int strindex = 0; + + strindex = snprintf(strbuf, strbuflen, + "CONNECT MQTT version %d, client id %.*s, clean session %d, keep alive %d", + (int)data->MQTTVersion, data->clientID.lenstring.len, data->clientID.lenstring.data, + (int)data->cleansession, data->keepAliveInterval); + if (data->willFlag) + strindex += snprintf(&strbuf[strindex], strbuflen - strindex, + ", will QoS %d, will retain %d, will topic %.*s, will message %.*s", + data->will.qos, data->will.retained, + data->will.topicName.lenstring.len, data->will.topicName.lenstring.data, + data->will.message.lenstring.len, data->will.message.lenstring.data); + if (data->username.lenstring.data && data->username.lenstring.len > 0) + strindex += snprintf(&strbuf[strindex], strbuflen - strindex, + ", user name %.*s", data->username.lenstring.len, data->username.lenstring.data); + if (data->password.lenstring.data && data->password.lenstring.len > 0) + strindex += snprintf(&strbuf[strindex], strbuflen - strindex, + ", password %.*s", data->password.lenstring.len, data->password.lenstring.data); + return strindex; +} + + +int MQTTStringFormat_connack(char* strbuf, int strbuflen, unsigned char connack_rc, unsigned char sessionPresent) +{ + int strindex = snprintf(strbuf, strbuflen, "CONNACK session present %d, rc %d", sessionPresent, connack_rc); + return strindex; +} + + +int MQTTStringFormat_publish(char* strbuf, int strbuflen, unsigned char dup, int qos, unsigned char retained, + unsigned short packetid, MQTTString topicName, unsigned char* payload, int payloadlen) +{ + int strindex = snprintf(strbuf, strbuflen, + "PUBLISH dup %d, QoS %d, retained %d, packet id %d, topic %.*s, payload length %d, payload %.*s", + dup, qos, retained, packetid, + (topicName.lenstring.len < 20) ? topicName.lenstring.len : 20, topicName.lenstring.data, + payloadlen, (payloadlen < 20) ? payloadlen : 20, payload); + return strindex; +} + + +int MQTTStringFormat_ack(char* strbuf, int strbuflen, unsigned char packettype, unsigned char dup, unsigned short packetid) +{ + int strindex = snprintf(strbuf, strbuflen, "%s, packet id %d", MQTTPacket_names[packettype], packetid); + if (dup) + strindex += snprintf(strbuf + strindex, strbuflen - strindex, ", dup %d", dup); + return strindex; +} + + +int MQTTStringFormat_subscribe(char* strbuf, int strbuflen, unsigned char dup, unsigned short packetid, int count, + MQTTString topicFilters[], int requestedQoSs[]) +{ + return snprintf(strbuf, strbuflen, + "SUBSCRIBE dup %d, packet id %d count %d topic %.*s qos %d", + dup, packetid, count, + topicFilters[0].lenstring.len, topicFilters[0].lenstring.data, + requestedQoSs[0]); +} + + +int MQTTStringFormat_suback(char* strbuf, int strbuflen, unsigned short packetid, int count, int* grantedQoSs) +{ + return snprintf(strbuf, strbuflen, + "SUBACK packet id %d count %d granted qos %d", packetid, count, grantedQoSs[0]); +} + + +int MQTTStringFormat_unsubscribe(char* strbuf, int strbuflen, unsigned char dup, unsigned short packetid, + int count, MQTTString topicFilters[]) +{ + return snprintf(strbuf, strbuflen, + "UNSUBSCRIBE dup %d, packet id %d count %d topic %.*s", + dup, packetid, count, + topicFilters[0].lenstring.len, topicFilters[0].lenstring.data); +} + + +#if defined(MQTT_CLIENT) +char* MQTTFormat_toClientString(char* strbuf, int strbuflen, unsigned char* buf, int buflen) +{ + int index = 0; + int rem_length = 0; + MQTTHeader header = {0}; + int strindex = 0; + + header.byte = buf[index++]; + index += MQTTPacket_decodeBuf(&buf[index], &rem_length); + + switch (header.bits.type) + { + + case CONNACK: + { + unsigned char sessionPresent, connack_rc; + if (MQTTDeserialize_connack(&sessionPresent, &connack_rc, buf, buflen) == 1) + strindex = MQTTStringFormat_connack(strbuf, strbuflen, connack_rc, sessionPresent); + } + break; + case PUBLISH: + { + unsigned char dup, retained, *payload; + unsigned short packetid; + int qos, payloadlen; + MQTTString topicName = MQTTString_initializer; + if (MQTTDeserialize_publish(&dup, &qos, &retained, &packetid, &topicName, + &payload, &payloadlen, buf, buflen) == 1) + strindex = MQTTStringFormat_publish(strbuf, strbuflen, dup, qos, retained, packetid, + topicName, payload, payloadlen); + } + break; + case PUBACK: + case PUBREC: + case PUBREL: + case PUBCOMP: + { + unsigned char packettype, dup; + unsigned short packetid; + if (MQTTDeserialize_ack(&packettype, &dup, &packetid, buf, buflen) == 1) + strindex = MQTTStringFormat_ack(strbuf, strbuflen, packettype, dup, packetid); + } + break; + case SUBACK: + { + unsigned short packetid; + int maxcount = 1, count = 0; + int grantedQoSs[1]; + if (MQTTDeserialize_suback(&packetid, maxcount, &count, grantedQoSs, buf, buflen) == 1) + strindex = MQTTStringFormat_suback(strbuf, strbuflen, packetid, count, grantedQoSs); + } + break; + case UNSUBACK: + { + unsigned short packetid; + if (MQTTDeserialize_unsuback(&packetid, buf, buflen) == 1) + strindex = MQTTStringFormat_ack(strbuf, strbuflen, UNSUBACK, 0, packetid); + } + break; + case PINGREQ: + case PINGRESP: + case DISCONNECT: + strindex = snprintf(strbuf, strbuflen, "%s", MQTTPacket_names[header.bits.type]); + break; + } + return strbuf; +} +#endif + +#if defined(MQTT_SERVER) +char* MQTTFormat_toServerString(char* strbuf, int strbuflen, unsigned char* buf, int buflen) +{ + int index = 0; + int rem_length = 0; + MQTTHeader header = {0}; + int strindex = 0; + + header.byte = buf[index++]; + index += MQTTPacket_decodeBuf(&buf[index], &rem_length); + + switch (header.bits.type) + { + case CONNECT: + { + MQTTPacket_connectData data; + int rc; + if ((rc = MQTTDeserialize_connect(&data, buf, buflen)) == 1) + strindex = MQTTStringFormat_connect(strbuf, strbuflen, &data); + } + break; + case PUBLISH: + { + unsigned char dup, retained, *payload; + unsigned short packetid; + int qos, payloadlen; + MQTTString topicName = MQTTString_initializer; + if (MQTTDeserialize_publish(&dup, &qos, &retained, &packetid, &topicName, + &payload, &payloadlen, buf, buflen) == 1) + strindex = MQTTStringFormat_publish(strbuf, strbuflen, dup, qos, retained, packetid, + topicName, payload, payloadlen); + } + break; + case PUBACK: + case PUBREC: + case PUBREL: + case PUBCOMP: + { + unsigned char packettype, dup; + unsigned short packetid; + if (MQTTDeserialize_ack(&packettype, &dup, &packetid, buf, buflen) == 1) + strindex = MQTTStringFormat_ack(strbuf, strbuflen, packettype, dup, packetid); + } + break; + case SUBSCRIBE: + { + unsigned char dup; + unsigned short packetid; + int maxcount = 1, count = 0; + MQTTString topicFilters[1]; + int requestedQoSs[1]; + if (MQTTDeserialize_subscribe(&dup, &packetid, maxcount, &count, + topicFilters, requestedQoSs, buf, buflen) == 1) + strindex = MQTTStringFormat_subscribe(strbuf, strbuflen, dup, packetid, count, topicFilters, requestedQoSs);; + } + break; + case UNSUBSCRIBE: + { + unsigned char dup; + unsigned short packetid; + int maxcount = 1, count = 0; + MQTTString topicFilters[1]; + if (MQTTDeserialize_unsubscribe(&dup, &packetid, maxcount, &count, topicFilters, buf, buflen) == 1) + strindex = MQTTStringFormat_unsubscribe(strbuf, strbuflen, dup, packetid, count, topicFilters); + } + break; + case PINGREQ: + case PINGRESP: + case DISCONNECT: + strindex = snprintf(strbuf, strbuflen, "%s", MQTTPacket_names[header.bits.type]); + break; + } + strbuf[strbuflen] = '\0'; + return strbuf; +} +#endif diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTFormat.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTFormat.h new file mode 100644 index 000000000..47b0c4143 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTFormat.h @@ -0,0 +1,37 @@ +/******************************************************************************* + * Copyright (c) 2014 IBM Corp. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * and Eclipse Distribution License v1.0 which accompany this distribution. + * + * The Eclipse Public License is available at + * http://www.eclipse.org/legal/epl-v10.html + * and the Eclipse Distribution License is available at + * http://www.eclipse.org/org/documents/edl-v10.php. + * + * Contributors: + * Ian Craggs - initial API and implementation and/or initial documentation + *******************************************************************************/ + +#if !defined(MQTTFORMAT_H) +#define MQTTFORMAT_H + +#include "StackTrace.h" +#include "MQTTPacket.h" + +const char* MQTTPacket_getName(unsigned short packetid); +int MQTTStringFormat_connect(char* strbuf, int strbuflen, MQTTPacket_connectData* data); +int MQTTStringFormat_connack(char* strbuf, int strbuflen, unsigned char connack_rc, unsigned char sessionPresent); +int MQTTStringFormat_publish(char* strbuf, int strbuflen, unsigned char dup, int qos, unsigned char retained, + unsigned short packetid, MQTTString topicName, unsigned char* payload, int payloadlen); +int MQTTStringFormat_ack(char* strbuf, int strbuflen, unsigned char packettype, unsigned char dup, unsigned short packetid); +int MQTTStringFormat_subscribe(char* strbuf, int strbuflen, unsigned char dup, unsigned short packetid, int count, + MQTTString topicFilters[], int requestedQoSs[]); +int MQTTStringFormat_suback(char* strbuf, int strbuflen, unsigned short packetid, int count, int* grantedQoSs); +int MQTTStringFormat_unsubscribe(char* strbuf, int strbuflen, unsigned char dup, unsigned short packetid, + int count, MQTTString topicFilters[]); +char* MQTTFormat_toClientString(char* strbuf, int strbuflen, unsigned char* buf, int buflen); +char* MQTTFormat_toServerString(char* strbuf, int strbuflen, unsigned char* buf, int buflen); + +#endif diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPacket.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPacket.c new file mode 100644 index 000000000..4f1f95a78 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPacket.c @@ -0,0 +1,412 @@ +/******************************************************************************* + * Copyright (c) 2014 IBM Corp. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * and Eclipse Distribution License v1.0 which accompany this distribution. + * + * The Eclipse Public License is available at + * http://www.eclipse.org/legal/epl-v10.html + * and the Eclipse Distribution License is available at + * http://www.eclipse.org/org/documents/edl-v10.php. + * + * Contributors: + * Ian Craggs - initial API and implementation and/or initial documentation + * Sergio R. Caprile - non-blocking packet read functions for stream transport + *******************************************************************************/ + +#include "StackTrace.h" +#include "MQTTPacket.h" + +#include + +/** + * Encodes the message length according to the MQTT algorithm + * @param buf the buffer into which the encoded data is written + * @param length the length to be encoded + * @return the number of bytes written to buffer + */ +int MQTTPacket_encode(unsigned char* buf, int length) +{ + int rc = 0; + + FUNC_ENTRY; + do + { + char d = length % 128; + length /= 128; + /* if there are more digits to encode, set the top bit of this digit */ + if (length > 0) + d |= 0x80; + buf[rc++] = d; + } while (length > 0); + FUNC_EXIT_RC(rc); + return rc; +} + + +/** + * Decodes the message length according to the MQTT algorithm + * @param getcharfn pointer to function to read the next character from the data source + * @param value the decoded length returned + * @return the number of bytes read from the socket + */ +int MQTTPacket_decode(int (*getcharfn)(unsigned char*, int), int* value) +{ + unsigned char c; + int multiplier = 1; + int len = 0; +#define MAX_NO_OF_REMAINING_LENGTH_BYTES 4 + + FUNC_ENTRY; + *value = 0; + do + { + int rc = MQTTPACKET_READ_ERROR; + + if (++len > MAX_NO_OF_REMAINING_LENGTH_BYTES) + { + rc = MQTTPACKET_READ_ERROR; /* bad data */ + goto exit; + } + rc = (*getcharfn)(&c, 1); + if (rc != 1) + goto exit; + *value += (c & 127) * multiplier; + multiplier *= 128; + } while ((c & 128) != 0); +exit: + FUNC_EXIT_RC(len); + return len; +} + + +int MQTTPacket_len(int rem_len) +{ + rem_len += 1; /* header byte */ + + /* now remaining_length field */ + if (rem_len < 128) + rem_len += 1; + else if (rem_len < 16384) + rem_len += 2; + else if (rem_len < 2097151) + rem_len += 3; + else + rem_len += 4; + return rem_len; +} + + +static unsigned char* bufptr; + +int bufchar(unsigned char* c, int count) +{ + int i; + + for (i = 0; i < count; ++i) + *c = *bufptr++; + return count; +} + + +int MQTTPacket_decodeBuf(unsigned char* buf, int* value) +{ + bufptr = buf; + return MQTTPacket_decode(bufchar, value); +} + + +/** + * Calculates an integer from two bytes read from the input buffer + * @param pptr pointer to the input buffer - incremented by the number of bytes used & returned + * @return the integer value calculated + */ +int readInt(unsigned char** pptr) +{ + unsigned char* ptr = *pptr; + int len = 256*(*ptr) + (*(ptr+1)); + *pptr += 2; + return len; +} + + +/** + * Reads one character from the input buffer. + * @param pptr pointer to the input buffer - incremented by the number of bytes used & returned + * @return the character read + */ +char readChar(unsigned char** pptr) +{ + char c = **pptr; + (*pptr)++; + return c; +} + + +/** + * Writes one character to an output buffer. + * @param pptr pointer to the output buffer - incremented by the number of bytes used & returned + * @param c the character to write + */ +void writeChar(unsigned char** pptr, char c) +{ + **pptr = c; + (*pptr)++; +} + + +/** + * Writes an integer as 2 bytes to an output buffer. + * @param pptr pointer to the output buffer - incremented by the number of bytes used & returned + * @param anInt the integer to write + */ +void writeInt(unsigned char** pptr, int anInt) +{ + **pptr = (unsigned char)(anInt / 256); + (*pptr)++; + **pptr = (unsigned char)(anInt % 256); + (*pptr)++; +} + + +/** + * Writes a "UTF" string to an output buffer. Converts C string to length-delimited. + * @param pptr pointer to the output buffer - incremented by the number of bytes used & returned + * @param string the C string to write + */ +void writeCString(unsigned char** pptr, const char* string) +{ + int len = strlen(string); + writeInt(pptr, len); + memcpy(*pptr, string, len); + *pptr += len; +} + + +int getLenStringLen(char* ptr) +{ + int len = 256*((unsigned char)(*ptr)) + (unsigned char)(*(ptr+1)); + return len; +} + + +void writeMQTTString(unsigned char** pptr, MQTTString mqttstring) +{ + if (mqttstring.lenstring.len > 0) + { + writeInt(pptr, mqttstring.lenstring.len); + memcpy(*pptr, mqttstring.lenstring.data, mqttstring.lenstring.len); + *pptr += mqttstring.lenstring.len; + } + else if (mqttstring.cstring) + writeCString(pptr, mqttstring.cstring); + else + writeInt(pptr, 0); +} + + +/** + * @param mqttstring the MQTTString structure into which the data is to be read + * @param pptr pointer to the output buffer - incremented by the number of bytes used & returned + * @param enddata pointer to the end of the data: do not read beyond + * @return 1 if successful, 0 if not + */ +int readMQTTLenString(MQTTString* mqttstring, unsigned char** pptr, unsigned char* enddata) +{ + int rc = 0; + + FUNC_ENTRY; + /* the first two bytes are the length of the string */ + if (enddata - (*pptr) > 1) /* enough length to read the integer? */ + { + mqttstring->lenstring.len = readInt(pptr); /* increments pptr to point past length */ + if (&(*pptr)[mqttstring->lenstring.len] <= enddata) + { + mqttstring->lenstring.data = (char*)*pptr; + *pptr += mqttstring->lenstring.len; + rc = 1; + } + } + mqttstring->cstring = NULL; + FUNC_EXIT_RC(rc); + return rc; +} + + +/** + * Return the length of the MQTTstring - C string if there is one, otherwise the length delimited string + * @param mqttstring the string to return the length of + * @return the length of the string + */ +int MQTTstrlen(MQTTString mqttstring) +{ + int rc = 0; + + if (mqttstring.cstring) + rc = strlen(mqttstring.cstring); + else + rc = mqttstring.lenstring.len; + return rc; +} + + +/** + * Compares an MQTTString to a C string + * @param a the MQTTString to compare + * @param bptr the C string to compare + * @return boolean - equal or not + */ +int MQTTPacket_equals(MQTTString* a, char* bptr) +{ + int alen = 0, + blen = 0; + char *aptr; + + if (a->cstring) + { + aptr = a->cstring; + alen = strlen(a->cstring); + } + else + { + aptr = a->lenstring.data; + alen = a->lenstring.len; + } + blen = strlen(bptr); + + return (alen == blen) && (strncmp(aptr, bptr, alen) == 0); +} + + +/** + * Helper function to read packet data from some source into a buffer + * @param buf the buffer into which the packet will be serialized + * @param buflen the length in bytes of the supplied buffer + * @param getfn pointer to a function which will read any number of bytes from the needed source + * @return integer MQTT packet type, or -1 on error + * @note the whole message must fit into the caller's buffer + */ +int MQTTPacket_read(unsigned char* buf, int buflen, int (*getfn)(unsigned char*, int)) +{ + int rc = -1; + MQTTHeader header = {0}; + int len = 0; + int rem_len = 0; + + /* 1. read the header byte. This has the packet type in it */ + if ((*getfn)(buf, 1) != 1) + goto exit; + + len = 1; + /* 2. read the remaining length. This is variable in itself */ + MQTTPacket_decode(getfn, &rem_len); + len += MQTTPacket_encode(buf + 1, rem_len); /* put the original remaining length back into the buffer */ + + /* 3. read the rest of the buffer using a callback to supply the rest of the data */ + if((rem_len + len) > buflen) + goto exit; + if (rem_len && ((*getfn)(buf + len, rem_len) != rem_len)) + goto exit; + + header.byte = buf[0]; + rc = header.bits.type; +exit: + return rc; +} + +/** + * Decodes the message length according to the MQTT algorithm, non-blocking + * @param trp pointer to a transport structure holding what is needed to solve getting data from it + * @param value the decoded length returned + * @return integer the number of bytes read from the socket, 0 for call again, or -1 on error + */ +static int MQTTPacket_decodenb(MQTTTransport *trp) +{ + unsigned char c; + int rc = MQTTPACKET_READ_ERROR; + + FUNC_ENTRY; + if(trp->len == 0){ /* initialize on first call */ + trp->multiplier = 1; + trp->rem_len = 0; + } + do { + int frc; + if (trp->len >= MAX_NO_OF_REMAINING_LENGTH_BYTES) + goto exit; + if ((frc=(*trp->getfn)(trp->sck, &c, 1)) == -1) + goto exit; + if (frc == 0){ + rc = 0; + goto exit; + } + ++(trp->len); + trp->rem_len += (c & 127) * trp->multiplier; + trp->multiplier *= 128; + } while ((c & 128) != 0); + rc = trp->len; +exit: + FUNC_EXIT_RC(rc); + return rc; +} + +/** + * Helper function to read packet data from some source into a buffer, non-blocking + * @param buf the buffer into which the packet will be serialized + * @param buflen the length in bytes of the supplied buffer + * @param trp pointer to a transport structure holding what is needed to solve getting data from it + * @return integer MQTT packet type, 0 for call again, or -1 on error + * @note the whole message must fit into the caller's buffer + */ +int MQTTPacket_readnb(unsigned char* buf, int buflen, MQTTTransport *trp) +{ + int rc = -1, frc; + MQTTHeader header = {0}; + + switch(trp->state){ + default: + trp->state = 0; + /*FALLTHROUGH*/ + case 0: + /* read the header byte. This has the packet type in it */ + if ((frc=(*trp->getfn)(trp->sck, buf, 1)) == -1) + goto exit; + if (frc == 0) + return 0; + trp->len = 0; + ++trp->state; + /*FALLTHROUGH*/ + /* read the remaining length. This is variable in itself */ + case 1: + if((frc=MQTTPacket_decodenb(trp)) == MQTTPACKET_READ_ERROR) + goto exit; + if(frc == 0) + return 0; + trp->len = 1 + MQTTPacket_encode(buf + 1, trp->rem_len); /* put the original remaining length back into the buffer */ + if((trp->rem_len + trp->len) > buflen) + goto exit; + ++trp->state; + /*FALLTHROUGH*/ + case 2: + if(trp->rem_len){ + /* read the rest of the buffer using a callback to supply the rest of the data */ + if ((frc=(*trp->getfn)(trp->sck, buf + trp->len, trp->rem_len)) == -1) + goto exit; + if (frc == 0) + return 0; + trp->rem_len -= frc; + trp->len += frc; + if(trp->rem_len) + return 0; + } + header.byte = buf[0]; + rc = header.bits.type; + break; + } + +exit: + trp->state = 0; + return rc; +} + diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPacket.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPacket.h new file mode 100644 index 000000000..a1c5038d8 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPacket.h @@ -0,0 +1,134 @@ +/******************************************************************************* + * Copyright (c) 2014 IBM Corp. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * and Eclipse Distribution License v1.0 which accompany this distribution. + * + * The Eclipse Public License is available at + * http://www.eclipse.org/legal/epl-v10.html + * and the Eclipse Distribution License is available at + * http://www.eclipse.org/org/documents/edl-v10.php. + * + * Contributors: + * Ian Craggs - initial API and implementation and/or initial documentation + * Xiang Rong - 442039 Add makefile to Embedded C client + *******************************************************************************/ +#include + +#ifndef MQTTPACKET_H_ +#define MQTTPACKET_H_ + +#if defined(__cplusplus) /* If this is a C++ compiler, use C linkage */ +extern "C" { +#endif + +#if defined(WIN32_DLL) || defined(WIN64_DLL) + #define DLLImport __declspec(dllimport) + #define DLLExport __declspec(dllexport) +#elif defined(LINUX_SO) + #define DLLImport extern + #define DLLExport __attribute__ ((visibility ("default"))) +#else + #define DLLImport + #define DLLExport +#endif + +enum errors +{ + MQTTPACKET_BUFFER_TOO_SHORT = -2, + MQTTPACKET_READ_ERROR = -1, + MQTTPACKET_READ_COMPLETE +}; + +enum msgTypes +{ + CONNECT = 1, CONNACK, PUBLISH, PUBACK, PUBREC, PUBREL, + PUBCOMP, SUBSCRIBE, SUBACK, UNSUBSCRIBE, UNSUBACK, + PINGREQ, PINGRESP, DISCONNECT +}; + +/** + * Bitfields for the MQTT header byte. + */ +typedef union +{ + unsigned char byte; /**< the whole byte */ +#if defined(REVERSED) + struct + { + unsigned int type : 4; /**< message type nibble */ + unsigned int dup : 1; /**< DUP flag bit */ + unsigned int qos : 2; /**< QoS value, 0, 1 or 2 */ + unsigned int retain : 1; /**< retained flag bit */ + } bits; +#else + struct + { + unsigned int retain : 1; /**< retained flag bit */ + unsigned int qos : 2; /**< QoS value, 0, 1 or 2 */ + unsigned int dup : 1; /**< DUP flag bit */ + unsigned int type : 4; /**< message type nibble */ + } bits; +#endif +} MQTTHeader; + +typedef struct +{ + int len; + char* data; +} MQTTLenString; + +typedef struct +{ + char* cstring; + MQTTLenString lenstring; +} MQTTString; + +#define MQTTString_initializer {NULL, {0, NULL}} + +int MQTTstrlen(MQTTString mqttstring); + +#include "MQTTConnect.h" +#include "MQTTPublish.h" +#include "MQTTSubscribe.h" +#include "MQTTUnsubscribe.h" +#include "MQTTFormat.h" + +DLLExport int MQTTSerialize_ack(unsigned char* buf, int buflen, unsigned char type, unsigned char dup, unsigned short packetid); +DLLExport int MQTTDeserialize_ack(unsigned char* packettype, unsigned char* dup, unsigned short* packetid, unsigned char* buf, int buflen); + +int MQTTPacket_len(int rem_len); +DLLExport int MQTTPacket_equals(MQTTString* a, char* b); + +DLLExport int MQTTPacket_encode(unsigned char* buf, int length); +int MQTTPacket_decode(int (*getcharfn)(unsigned char*, int), int* value); +int MQTTPacket_decodeBuf(unsigned char* buf, int* value); + +int readInt(unsigned char** pptr); +char readChar(unsigned char** pptr); +void writeChar(unsigned char** pptr, char c); +void writeInt(unsigned char** pptr, int anInt); +int readMQTTLenString(MQTTString* mqttstring, unsigned char** pptr, unsigned char* enddata); +void writeCString(unsigned char** pptr, const char* string); +void writeMQTTString(unsigned char** pptr, MQTTString mqttstring); + +DLLExport int MQTTPacket_read(unsigned char* buf, int buflen, int (*getfn)(unsigned char*, int)); + +typedef struct { + int (*getfn)(void *, unsigned char*, int); /* must return -1 for error, 0 for call again, or the number of bytes read */ + void *sck; /* pointer to whatever the system may use to identify the transport */ + int multiplier; + int rem_len; + int len; + char state; +}MQTTTransport; + +int MQTTPacket_readnb(unsigned char* buf, int buflen, MQTTTransport *trp); + +#ifdef __cplusplus /* If this is a C++ compiler, use C linkage */ +} +#endif + + +#endif /* MQTTPACKET_H_ */ diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPublish.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPublish.h new file mode 100644 index 000000000..88aca927e --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPublish.h @@ -0,0 +1,38 @@ +/******************************************************************************* + * Copyright (c) 2014 IBM Corp. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * and Eclipse Distribution License v1.0 which accompany this distribution. + * + * The Eclipse Public License is available at + * http://www.eclipse.org/legal/epl-v10.html + * and the Eclipse Distribution License is available at + * http://www.eclipse.org/org/documents/edl-v10.php. + * + * Contributors: + * Ian Craggs - initial API and implementation and/or initial documentation + * Xiang Rong - 442039 Add makefile to Embedded C client + *******************************************************************************/ + +#ifndef MQTTPUBLISH_H_ +#define MQTTPUBLISH_H_ + +#if !defined(DLLImport) + #define DLLImport +#endif +#if !defined(DLLExport) + #define DLLExport +#endif + +DLLExport int MQTTSerialize_publish(unsigned char* buf, int buflen, unsigned char dup, int qos, unsigned char retained, unsigned short packetid, + MQTTString topicName, unsigned char* payload, int payloadlen); + +DLLExport int MQTTDeserialize_publish(unsigned char* dup, int* qos, unsigned char* retained, unsigned short* packetid, MQTTString* topicName, + unsigned char** payload, int32_t* payloadlen, unsigned char* buf, int len); + +DLLExport int MQTTSerialize_puback(unsigned char* buf, int buflen, unsigned short packetid); +DLLExport int MQTTSerialize_pubrel(unsigned char* buf, int buflen, unsigned char dup, unsigned short packetid); +DLLExport int MQTTSerialize_pubcomp(unsigned char* buf, int buflen, unsigned short packetid); + +#endif /* MQTTPUBLISH_H_ */ diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSerializePublish.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSerializePublish.c new file mode 100644 index 000000000..77a58b54a --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSerializePublish.c @@ -0,0 +1,169 @@ +/******************************************************************************* + * Copyright (c) 2014 IBM Corp. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * and Eclipse Distribution License v1.0 which accompany this distribution. + * + * The Eclipse Public License is available at + * http://www.eclipse.org/legal/epl-v10.html + * and the Eclipse Distribution License is available at + * http://www.eclipse.org/org/documents/edl-v10.php. + * + * Contributors: + * Ian Craggs - initial API and implementation and/or initial documentation + * Ian Craggs - fix for https://bugs.eclipse.org/bugs/show_bug.cgi?id=453144 + *******************************************************************************/ + +#include "MQTTPacket.h" +#include "StackTrace.h" + +#include + + +/** + * Determines the length of the MQTT publish packet that would be produced using the supplied parameters + * @param qos the MQTT QoS of the publish (packetid is omitted for QoS 0) + * @param topicName the topic name to be used in the publish + * @param payloadlen the length of the payload to be sent + * @return the length of buffer needed to contain the serialized version of the packet + */ +int MQTTSerialize_publishLength(int qos, MQTTString topicName, int payloadlen) +{ + int len = 0; + + len += 2 + MQTTstrlen(topicName) + payloadlen; + if (qos > 0) + len += 2; /* packetid */ + return len; +} + + +/** + * Serializes the supplied publish data into the supplied buffer, ready for sending + * @param buf the buffer into which the packet will be serialized + * @param buflen the length in bytes of the supplied buffer + * @param dup integer - the MQTT dup flag + * @param qos integer - the MQTT QoS value + * @param retained integer - the MQTT retained flag + * @param packetid integer - the MQTT packet identifier + * @param topicName MQTTString - the MQTT topic in the publish + * @param payload byte buffer - the MQTT publish payload + * @param payloadlen integer - the length of the MQTT payload + * @return the length of the serialized data. <= 0 indicates error + */ +int MQTTSerialize_publish(unsigned char* buf, int buflen, unsigned char dup, int qos, unsigned char retained, unsigned short packetid, + MQTTString topicName, unsigned char* payload, int payloadlen) +{ + unsigned char *ptr = buf; + MQTTHeader header = {0}; + int rem_len = 0; + int rc = 0; + + FUNC_ENTRY; + if (MQTTPacket_len(rem_len = MQTTSerialize_publishLength(qos, topicName, payloadlen)) > buflen) + { + rc = MQTTPACKET_BUFFER_TOO_SHORT; + goto exit; + } + + header.bits.type = PUBLISH; + header.bits.dup = dup; + header.bits.qos = qos; + header.bits.retain = retained; + writeChar(&ptr, header.byte); /* write header */ + + ptr += MQTTPacket_encode(ptr, rem_len); /* write remaining length */; + + writeMQTTString(&ptr, topicName); + + if (qos > 0) + writeInt(&ptr, packetid); + + memcpy(ptr, payload, payloadlen); + ptr += payloadlen; + + rc = ptr - buf; + +exit: + FUNC_EXIT_RC(rc); + return rc; +} + + + +/** + * Serializes the ack packet into the supplied buffer. + * @param buf the buffer into which the packet will be serialized + * @param buflen the length in bytes of the supplied buffer + * @param type the MQTT packet type + * @param dup the MQTT dup flag + * @param packetid the MQTT packet identifier + * @return serialized length, or error if 0 + */ +int MQTTSerialize_ack(unsigned char* buf, int buflen, unsigned char packettype, unsigned char dup, unsigned short packetid) +{ + MQTTHeader header = {0}; + int rc = 0; + unsigned char *ptr = buf; + + FUNC_ENTRY; + if (buflen < 4) + { + rc = MQTTPACKET_BUFFER_TOO_SHORT; + goto exit; + } + header.bits.type = packettype; + header.bits.dup = dup; + header.bits.qos = (packettype == PUBREL) ? 1 : 0; + writeChar(&ptr, header.byte); /* write header */ + + ptr += MQTTPacket_encode(ptr, 2); /* write remaining length */ + writeInt(&ptr, packetid); + rc = ptr - buf; +exit: + FUNC_EXIT_RC(rc); + return rc; +} + + +/** + * Serializes a puback packet into the supplied buffer. + * @param buf the buffer into which the packet will be serialized + * @param buflen the length in bytes of the supplied buffer + * @param packetid integer - the MQTT packet identifier + * @return serialized length, or error if 0 + */ +int MQTTSerialize_puback(unsigned char* buf, int buflen, unsigned short packetid) +{ + return MQTTSerialize_ack(buf, buflen, PUBACK, 0, packetid); +} + + +/** + * Serializes a pubrel packet into the supplied buffer. + * @param buf the buffer into which the packet will be serialized + * @param buflen the length in bytes of the supplied buffer + * @param dup integer - the MQTT dup flag + * @param packetid integer - the MQTT packet identifier + * @return serialized length, or error if 0 + */ +int MQTTSerialize_pubrel(unsigned char* buf, int buflen, unsigned char dup, unsigned short packetid) +{ + return MQTTSerialize_ack(buf, buflen, PUBREL, dup, packetid); +} + + +/** + * Serializes a pubrel packet into the supplied buffer. + * @param buf the buffer into which the packet will be serialized + * @param buflen the length in bytes of the supplied buffer + * @param packetid integer - the MQTT packet identifier + * @return serialized length, or error if 0 + */ +int MQTTSerialize_pubcomp(unsigned char* buf, int buflen, unsigned short packetid) +{ + return MQTTSerialize_ack(buf, buflen, PUBCOMP, 0, packetid); +} + + diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribe.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribe.h new file mode 100644 index 000000000..4b702bd59 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribe.h @@ -0,0 +1,39 @@ +/******************************************************************************* + * Copyright (c) 2014 IBM Corp. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * and Eclipse Distribution License v1.0 which accompany this distribution. + * + * The Eclipse Public License is available at + * http://www.eclipse.org/legal/epl-v10.html + * and the Eclipse Distribution License is available at + * http://www.eclipse.org/org/documents/edl-v10.php. + * + * Contributors: + * Ian Craggs - initial API and implementation and/or initial documentation + * Xiang Rong - 442039 Add makefile to Embedded C client + *******************************************************************************/ + +#ifndef MQTTSUBSCRIBE_H_ +#define MQTTSUBSCRIBE_H_ + +#if !defined(DLLImport) + #define DLLImport +#endif +#if !defined(DLLExport) + #define DLLExport +#endif + +DLLExport int MQTTSerialize_subscribe(unsigned char* buf, int buflen, unsigned char dup, unsigned short packetid, + int count, MQTTString topicFilters[], int32_t requestedQoSs[]); + +DLLExport int MQTTDeserialize_subscribe(unsigned char* dup, unsigned short* packetid, + int maxcount, int* count, MQTTString topicFilters[], int requestedQoSs[], unsigned char* buf, int len); + +DLLExport int MQTTSerialize_suback(unsigned char* buf, int buflen, unsigned short packetid, int count, int* grantedQoSs); + +DLLExport int MQTTDeserialize_suback(unsigned short* packetid, int maxcount, int32_t* count, int32_t grantedQoSs[], unsigned char* buf, int len); + + +#endif /* MQTTSUBSCRIBE_H_ */ diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribeClient.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribeClient.c new file mode 100644 index 000000000..dc131882d --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribeClient.c @@ -0,0 +1,137 @@ +/******************************************************************************* + * Copyright (c) 2014 IBM Corp. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * and Eclipse Distribution License v1.0 which accompany this distribution. + * + * The Eclipse Public License is available at + * http://www.eclipse.org/legal/epl-v10.html + * and the Eclipse Distribution License is available at + * http://www.eclipse.org/org/documents/edl-v10.php. + * + * Contributors: + * Ian Craggs - initial API and implementation and/or initial documentation + *******************************************************************************/ + +#include "MQTTPacket.h" +#include "StackTrace.h" + +#include + +/** + * Determines the length of the MQTT subscribe packet that would be produced using the supplied parameters + * @param count the number of topic filter strings in topicFilters + * @param topicFilters the array of topic filter strings to be used in the publish + * @return the length of buffer needed to contain the serialized version of the packet + */ +int MQTTSerialize_subscribeLength(int count, MQTTString topicFilters[]) +{ + int i; + int len = 2; /* packetid */ + + for (i = 0; i < count; ++i) + len += 2 + MQTTstrlen(topicFilters[i]) + 1; /* length + topic + req_qos */ + return len; +} + + +/** + * Serializes the supplied subscribe data into the supplied buffer, ready for sending + * @param buf the buffer into which the packet will be serialized + * @param buflen the length in bytes of the supplied bufferr + * @param dup integer - the MQTT dup flag + * @param packetid integer - the MQTT packet identifier + * @param count - number of members in the topicFilters and reqQos arrays + * @param topicFilters - array of topic filter names + * @param requestedQoSs - array of requested QoS + * @return the length of the serialized data. <= 0 indicates error + */ +int MQTTSerialize_subscribe(unsigned char* buf, int buflen, unsigned char dup, unsigned short packetid, int count, + MQTTString topicFilters[], int32_t requestedQoSs[]) +{ + unsigned char *ptr = buf; + MQTTHeader header = {0}; + int rem_len = 0; + int rc = 0; + int i = 0; + + FUNC_ENTRY; + if (MQTTPacket_len(rem_len = MQTTSerialize_subscribeLength(count, topicFilters)) > buflen) + { + rc = MQTTPACKET_BUFFER_TOO_SHORT; + goto exit; + } + + header.byte = 0; + header.bits.type = SUBSCRIBE; + header.bits.dup = dup; + header.bits.qos = 1; + writeChar(&ptr, header.byte); /* write header */ + + ptr += MQTTPacket_encode(ptr, rem_len); /* write remaining length */; + + writeInt(&ptr, packetid); + + for (i = 0; i < count; ++i) + { + writeMQTTString(&ptr, topicFilters[i]); + writeChar(&ptr, requestedQoSs[i]); + } + + rc = ptr - buf; +exit: + FUNC_EXIT_RC(rc); + return rc; +} + + + +/** + * Deserializes the supplied (wire) buffer into suback data + * @param packetid returned integer - the MQTT packet identifier + * @param maxcount - the maximum number of members allowed in the grantedQoSs array + * @param count returned integer - number of members in the grantedQoSs array + * @param grantedQoSs returned array of integers - the granted qualities of service + * @param buf the raw buffer data, of the correct length determined by the remaining length field + * @param buflen the length in bytes of the data in the supplied buffer + * @return error code. 1 is success, 0 is failure + */ +int MQTTDeserialize_suback(unsigned short* packetid, int maxcount, int32_t* count, int32_t grantedQoSs[], unsigned char* buf, int buflen) +{ + MQTTHeader header = {0}; + unsigned char* curdata = buf; + unsigned char* enddata = NULL; + int rc = 0; + int mylen; + + FUNC_ENTRY; + header.byte = readChar(&curdata); + if (header.bits.type != SUBACK) + goto exit; + + curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ + enddata = curdata + mylen; + if (enddata - curdata < 2) + goto exit; + + *packetid = readInt(&curdata); + + *count = 0; + while (curdata < enddata) + { + if (*count > maxcount) + { + rc = -1; + goto exit; + } + grantedQoSs[(*count)++] = readChar(&curdata); + } + + rc = 1; +exit: + FUNC_EXIT_RC(rc); + return rc; +} + + diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribeServer.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribeServer.c new file mode 100644 index 000000000..5579645fe --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribeServer.c @@ -0,0 +1,112 @@ +/******************************************************************************* + * Copyright (c) 2014 IBM Corp. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * and Eclipse Distribution License v1.0 which accompany this distribution. + * + * The Eclipse Public License is available at + * http://www.eclipse.org/legal/epl-v10.html + * and the Eclipse Distribution License is available at + * http://www.eclipse.org/org/documents/edl-v10.php. + * + * Contributors: + * Ian Craggs - initial API and implementation and/or initial documentation + *******************************************************************************/ + +#include "MQTTPacket.h" +#include "StackTrace.h" + +#include + + +/** + * Deserializes the supplied (wire) buffer into subscribe data + * @param dup integer returned - the MQTT dup flag + * @param packetid integer returned - the MQTT packet identifier + * @param maxcount - the maximum number of members allowed in the topicFilters and requestedQoSs arrays + * @param count - number of members in the topicFilters and requestedQoSs arrays + * @param topicFilters - array of topic filter names + * @param requestedQoSs - array of requested QoS + * @param buf the raw buffer data, of the correct length determined by the remaining length field + * @param buflen the length in bytes of the data in the supplied buffer + * @return the length of the serialized data. <= 0 indicates error + */ +int MQTTDeserialize_subscribe(unsigned char* dup, unsigned short* packetid, int maxcount, int* count, MQTTString topicFilters[], + int requestedQoSs[], unsigned char* buf, int buflen) +{ + MQTTHeader header = {0}; + unsigned char* curdata = buf; + unsigned char* enddata = NULL; + int rc = -1; + int mylen = 0; + + FUNC_ENTRY; + header.byte = readChar(&curdata); + if (header.bits.type != SUBSCRIBE) + goto exit; + *dup = header.bits.dup; + + curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ + enddata = curdata + mylen; + + *packetid = readInt(&curdata); + + *count = 0; + while (curdata < enddata) + { + if (!readMQTTLenString(&topicFilters[*count], &curdata, enddata)) + goto exit; + if (curdata >= enddata) /* do we have enough data to read the req_qos version byte? */ + goto exit; + requestedQoSs[*count] = readChar(&curdata); + (*count)++; + } + + rc = 1; +exit: + FUNC_EXIT_RC(rc); + return rc; +} + + +/** + * Serializes the supplied suback data into the supplied buffer, ready for sending + * @param buf the buffer into which the packet will be serialized + * @param buflen the length in bytes of the supplied buffer + * @param packetid integer - the MQTT packet identifier + * @param count - number of members in the grantedQoSs array + * @param grantedQoSs - array of granted QoS + * @return the length of the serialized data. <= 0 indicates error + */ +int MQTTSerialize_suback(unsigned char* buf, int buflen, unsigned short packetid, int count, int* grantedQoSs) +{ + MQTTHeader header = {0}; + int rc = -1; + unsigned char *ptr = buf; + int i; + + FUNC_ENTRY; + if (buflen < 2 + count) + { + rc = MQTTPACKET_BUFFER_TOO_SHORT; + goto exit; + } + header.byte = 0; + header.bits.type = SUBACK; + writeChar(&ptr, header.byte); /* write header */ + + ptr += MQTTPacket_encode(ptr, 2 + count); /* write remaining length */ + + writeInt(&ptr, packetid); + + for (i = 0; i < count; ++i) + writeChar(&ptr, grantedQoSs[i]); + + rc = ptr - buf; +exit: + FUNC_EXIT_RC(rc); + return rc; +} + + diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribe.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribe.h new file mode 100644 index 000000000..355ca9a42 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribe.h @@ -0,0 +1,38 @@ +/******************************************************************************* + * Copyright (c) 2014 IBM Corp. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * and Eclipse Distribution License v1.0 which accompany this distribution. + * + * The Eclipse Public License is available at + * http://www.eclipse.org/legal/epl-v10.html + * and the Eclipse Distribution License is available at + * http://www.eclipse.org/org/documents/edl-v10.php. + * + * Contributors: + * Ian Craggs - initial API and implementation and/or initial documentation + * Xiang Rong - 442039 Add makefile to Embedded C client + *******************************************************************************/ + +#ifndef MQTTUNSUBSCRIBE_H_ +#define MQTTUNSUBSCRIBE_H_ + +#if !defined(DLLImport) + #define DLLImport +#endif +#if !defined(DLLExport) + #define DLLExport +#endif + +DLLExport int MQTTSerialize_unsubscribe(unsigned char* buf, int buflen, unsigned char dup, unsigned short packetid, + int count, MQTTString topicFilters[]); + +DLLExport int MQTTDeserialize_unsubscribe(unsigned char* dup, unsigned short* packetid, int max_count, int* count, MQTTString topicFilters[], + unsigned char* buf, int len); + +DLLExport int MQTTSerialize_unsuback(unsigned char* buf, int buflen, unsigned short packetid); + +DLLExport int MQTTDeserialize_unsuback(unsigned short* packetid, unsigned char* buf, int len); + +#endif /* MQTTUNSUBSCRIBE_H_ */ diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribeClient.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribeClient.c new file mode 100644 index 000000000..e7ec53021 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribeClient.c @@ -0,0 +1,106 @@ +/******************************************************************************* + * Copyright (c) 2014 IBM Corp. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * and Eclipse Distribution License v1.0 which accompany this distribution. + * + * The Eclipse Public License is available at + * http://www.eclipse.org/legal/epl-v10.html + * and the Eclipse Distribution License is available at + * http://www.eclipse.org/org/documents/edl-v10.php. + * + * Contributors: + * Ian Craggs - initial API and implementation and/or initial documentation + *******************************************************************************/ + +#include "MQTTPacket.h" +#include "StackTrace.h" + +#include + +/** + * Determines the length of the MQTT unsubscribe packet that would be produced using the supplied parameters + * @param count the number of topic filter strings in topicFilters + * @param topicFilters the array of topic filter strings to be used in the publish + * @return the length of buffer needed to contain the serialized version of the packet + */ +int MQTTSerialize_unsubscribeLength(int count, MQTTString topicFilters[]) +{ + int i; + int len = 2; /* packetid */ + + for (i = 0; i < count; ++i) + len += 2 + MQTTstrlen(topicFilters[i]); /* length + topic*/ + return len; +} + + +/** + * Serializes the supplied unsubscribe data into the supplied buffer, ready for sending + * @param buf the raw buffer data, of the correct length determined by the remaining length field + * @param buflen the length in bytes of the data in the supplied buffer + * @param dup integer - the MQTT dup flag + * @param packetid integer - the MQTT packet identifier + * @param count - number of members in the topicFilters array + * @param topicFilters - array of topic filter names + * @return the length of the serialized data. <= 0 indicates error + */ +int MQTTSerialize_unsubscribe(unsigned char* buf, int buflen, unsigned char dup, unsigned short packetid, + int count, MQTTString topicFilters[]) +{ + unsigned char *ptr = buf; + MQTTHeader header = {0}; + int rem_len = 0; + int rc = -1; + int i = 0; + + FUNC_ENTRY; + if (MQTTPacket_len(rem_len = MQTTSerialize_unsubscribeLength(count, topicFilters)) > buflen) + { + rc = MQTTPACKET_BUFFER_TOO_SHORT; + goto exit; + } + + header.byte = 0; + header.bits.type = UNSUBSCRIBE; + header.bits.dup = dup; + header.bits.qos = 1; + writeChar(&ptr, header.byte); /* write header */ + + ptr += MQTTPacket_encode(ptr, rem_len); /* write remaining length */; + + writeInt(&ptr, packetid); + + for (i = 0; i < count; ++i) + writeMQTTString(&ptr, topicFilters[i]); + + rc = ptr - buf; +exit: + FUNC_EXIT_RC(rc); + return rc; +} + + +/** + * Deserializes the supplied (wire) buffer into unsuback data + * @param packetid returned integer - the MQTT packet identifier + * @param buf the raw buffer data, of the correct length determined by the remaining length field + * @param buflen the length in bytes of the data in the supplied buffer + * @return error code. 1 is success, 0 is failure + */ +int MQTTDeserialize_unsuback(unsigned short* packetid, unsigned char* buf, int buflen) +{ + unsigned char type = 0; + unsigned char dup = 0; + int rc = 0; + + FUNC_ENTRY; + rc = MQTTDeserialize_ack(&type, &dup, packetid, buf, buflen); + if (type == UNSUBACK) + rc = 1; + FUNC_EXIT_RC(rc); + return rc; +} + + diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribeServer.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribeServer.c new file mode 100644 index 000000000..42b6102a7 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribeServer.c @@ -0,0 +1,102 @@ +/******************************************************************************* + * Copyright (c) 2014 IBM Corp. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * and Eclipse Distribution License v1.0 which accompany this distribution. + * + * The Eclipse Public License is available at + * http://www.eclipse.org/legal/epl-v10.html + * and the Eclipse Distribution License is available at + * http://www.eclipse.org/org/documents/edl-v10.php. + * + * Contributors: + * Ian Craggs - initial API and implementation and/or initial documentation + *******************************************************************************/ + +#include "MQTTPacket.h" +#include "StackTrace.h" + +#include + + +/** + * Deserializes the supplied (wire) buffer into unsubscribe data + * @param dup integer returned - the MQTT dup flag + * @param packetid integer returned - the MQTT packet identifier + * @param maxcount - the maximum number of members allowed in the topicFilters and requestedQoSs arrays + * @param count - number of members in the topicFilters and requestedQoSs arrays + * @param topicFilters - array of topic filter names + * @param buf the raw buffer data, of the correct length determined by the remaining length field + * @param buflen the length in bytes of the data in the supplied buffer + * @return the length of the serialized data. <= 0 indicates error + */ +int MQTTDeserialize_unsubscribe(unsigned char* dup, unsigned short* packetid, int maxcount, int* count, MQTTString topicFilters[], + unsigned char* buf, int len) +{ + MQTTHeader header = {0}; + unsigned char* curdata = buf; + unsigned char* enddata = NULL; + int rc = 0; + int mylen = 0; + + FUNC_ENTRY; + header.byte = readChar(&curdata); + if (header.bits.type != UNSUBSCRIBE) + goto exit; + *dup = header.bits.dup; + + curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ + enddata = curdata + mylen; + + *packetid = readInt(&curdata); + + *count = 0; + while (curdata < enddata) + { + if (!readMQTTLenString(&topicFilters[*count], &curdata, enddata)) + goto exit; + (*count)++; + } + + rc = 1; +exit: + FUNC_EXIT_RC(rc); + return rc; +} + + +/** + * Serializes the supplied unsuback data into the supplied buffer, ready for sending + * @param buf the buffer into which the packet will be serialized + * @param buflen the length in bytes of the supplied buffer + * @param packetid integer - the MQTT packet identifier + * @return the length of the serialized data. <= 0 indicates error + */ +int MQTTSerialize_unsuback(unsigned char* buf, int buflen, unsigned short packetid) +{ + MQTTHeader header = {0}; + int rc = 0; + unsigned char *ptr = buf; + + FUNC_ENTRY; + if (buflen < 2) + { + rc = MQTTPACKET_BUFFER_TOO_SHORT; + goto exit; + } + header.byte = 0; + header.bits.type = UNSUBACK; + writeChar(&ptr, header.byte); /* write header */ + + ptr += MQTTPacket_encode(ptr, 2); /* write remaining length */ + + writeInt(&ptr, packetid); + + rc = ptr - buf; +exit: + FUNC_EXIT_RC(rc); + return rc; +} + + diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/StackTrace.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/StackTrace.h new file mode 100644 index 000000000..2808a0d18 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/StackTrace.h @@ -0,0 +1,78 @@ +/******************************************************************************* + * Copyright (c) 2014 IBM Corp. + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * and Eclipse Distribution License v1.0 which accompany this distribution. + * + * The Eclipse Public License is available at + * http://www.eclipse.org/legal/epl-v10.html + * and the Eclipse Distribution License is available at + * http://www.eclipse.org/org/documents/edl-v10.php. + * + * Contributors: + * Ian Craggs - initial API and implementation and/or initial documentation + * Ian Craggs - fix for bug #434081 + *******************************************************************************/ + +#ifndef STACKTRACE_H_ +#define STACKTRACE_H_ + +#include +#define NOSTACKTRACE 1 + +#if defined(NOSTACKTRACE) +#define FUNC_ENTRY +#define FUNC_ENTRY_NOLOG +#define FUNC_ENTRY_MED +#define FUNC_ENTRY_MAX +#define FUNC_EXIT +#define FUNC_EXIT_NOLOG +#define FUNC_EXIT_MED +#define FUNC_EXIT_MAX +#define FUNC_EXIT_RC(x) +#define FUNC_EXIT_MED_RC(x) +#define FUNC_EXIT_MAX_RC(x) + +#else + +#if defined(WIN32) +#define inline __inline +#define FUNC_ENTRY StackTrace_entry(__FUNCTION__, __LINE__, TRACE_MINIMUM) +#define FUNC_ENTRY_NOLOG StackTrace_entry(__FUNCTION__, __LINE__, -1) +#define FUNC_ENTRY_MED StackTrace_entry(__FUNCTION__, __LINE__, TRACE_MEDIUM) +#define FUNC_ENTRY_MAX StackTrace_entry(__FUNCTION__, __LINE__, TRACE_MAXIMUM) +#define FUNC_EXIT StackTrace_exit(__FUNCTION__, __LINE__, NULL, TRACE_MINIMUM) +#define FUNC_EXIT_NOLOG StackTrace_exit(__FUNCTION__, __LINE__, -1) +#define FUNC_EXIT_MED StackTrace_exit(__FUNCTION__, __LINE__, NULL, TRACE_MEDIUM) +#define FUNC_EXIT_MAX StackTrace_exit(__FUNCTION__, __LINE__, NULL, TRACE_MAXIMUM) +#define FUNC_EXIT_RC(x) StackTrace_exit(__FUNCTION__, __LINE__, &x, TRACE_MINIMUM) +#define FUNC_EXIT_MED_RC(x) StackTrace_exit(__FUNCTION__, __LINE__, &x, TRACE_MEDIUM) +#define FUNC_EXIT_MAX_RC(x) StackTrace_exit(__FUNCTION__, __LINE__, &x, TRACE_MAXIMUM) +#else +#define FUNC_ENTRY StackTrace_entry(__func__, __LINE__, TRACE_MINIMUM) +#define FUNC_ENTRY_NOLOG StackTrace_entry(__func__, __LINE__, -1) +#define FUNC_ENTRY_MED StackTrace_entry(__func__, __LINE__, TRACE_MEDIUM) +#define FUNC_ENTRY_MAX StackTrace_entry(__func__, __LINE__, TRACE_MAXIMUM) +#define FUNC_EXIT StackTrace_exit(__func__, __LINE__, NULL, TRACE_MINIMUM) +#define FUNC_EXIT_NOLOG StackTrace_exit(__func__, __LINE__, NULL, -1) +#define FUNC_EXIT_MED StackTrace_exit(__func__, __LINE__, NULL, TRACE_MEDIUM) +#define FUNC_EXIT_MAX StackTrace_exit(__func__, __LINE__, NULL, TRACE_MAXIMUM) +#define FUNC_EXIT_RC(x) StackTrace_exit(__func__, __LINE__, &x, TRACE_MINIMUM) +#define FUNC_EXIT_MED_RC(x) StackTrace_exit(__func__, __LINE__, &x, TRACE_MEDIUM) +#define FUNC_EXIT_MAX_RC(x) StackTrace_exit(__func__, __LINE__, &x, TRACE_MAXIMUM) + +void StackTrace_entry(const char* name, int line, int trace); +void StackTrace_exit(const char* name, int line, void* return_value, int trace); + +void StackTrace_printStack(FILE* dest); +char* StackTrace_get(unsigned long); + +#endif + +#endif + + + + +#endif /* STACKTRACE_H_ */ diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/transport.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/transport.c new file mode 100644 index 000000000..5df2b8692 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/transport.c @@ -0,0 +1,102 @@ +#include "transport.h" +#include "lwip/opt.h" +#include "lwip/arch.h" +#include "lwip/api.h" +#include "lwip/inet.h" +#include "lwip/sockets.h" +#include "string.h" + +static int mysock; + +/************************************************************************ +** ��������: transport_sendPacketBuffer +** ��������: ��TCP��ʽ�������� +** ��ڲ���: unsigned char* buf�����ݻ����� +** int buflen�����ݳ��� +** ���ڲ���: <0��������ʧ�� +************************************************************************/ +int32_t transport_sendPacketBuffer( uint8_t* buf, int32_t buflen) +{ + int32_t rc; + rc = write(mysock, buf, buflen); + return rc; +} + +/************************************************************************ +** ��������: transport_getdata +** ��������: �������ķ�ʽ����TCP���� +** ��ڲ���: unsigned char* buf�����ݻ����� +** int count�����ݳ��� +** ���ڲ���: <=0��������ʧ�� +************************************************************************/ +int transport_getdata(unsigned char* buf, int count) +{ + int32_t rc; + //������������ﲻ���� + rc = recv(mysock, buf, count, 0); + lw_print("get data : %d\n",rc); + return rc; +} + + + +/************************************************************************ +** ��������: transport_open +** ��������: ��һ���ӿڣ����Һͷ����� �������� +** ��ڲ���: char* servip:���������� +** int port:�˿ں� +** ���ڲ���: <0������ʧ�� +************************************************************************/ +// int32_t transport_open(int8_t* servip, int32_t port) +// { +// int32_t *sock = &mysock; +// int32_t ret; +// // int32_t opt; +// struct sockaddr_in addr; + +// //��ʼ����������Ϣ +// memset(&addr,0,sizeof(addr)); +// addr.sin_len = sizeof(addr); +// addr.sin_family = AF_INET; +// //��д�������˿ں� +// addr.sin_port = PP_HTONS(port); +// //��д������IP��ַ +// addr.sin_addr.s_addr = inet_addr((const char*)servip); + +// //����SOCK +// *sock = socket(AF_INET,SOCK_STREAM,0); +// //���ӷ����� +// ret = connect(*sock,(struct sockaddr*)&addr,sizeof(addr)); +// if(ret != 0) +// { +// //�ر����� +// close(*sock); +// //����ʧ�� +// return -1; +// } +// //���ӳɹ�,���ó�ʱʱ��1000ms +// // opt = 1000; +// // setsockopt(*sock,SOL_SOCKET,SO_RCVTIMEO,&opt,sizeof(int)); + +// //�����׽��� +// return *sock; +// } + + +/************************************************************************ +** ��������: transport_close +** ��������: �ر��׽��� +** ��ڲ���: unsigned char* buf�����ݻ����� +** int buflen�����ݳ��� +** ���ڲ���: <0��������ʧ�� +************************************************************************/ +int32_t transport_close(void) +{ + + int rc; +// rc = close(mysock); + rc = shutdown(mysock, SHUT_WR); + rc = recv(mysock, NULL, (size_t)0, 0); + rc = close(mysock); + return rc; +} diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/transport.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/transport.h new file mode 100644 index 000000000..a11ef1923 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/transport.h @@ -0,0 +1,45 @@ +#ifndef __TRANSPORT_H +#define __TRANSPORT_H + +#include + + +/************************************************************************ +** ��������: transport_sendPacketBuffer +** ��������: ��TCP��ʽ�������� +** ��ڲ���: unsigned char* buf�����ݻ����� +** int buflen�����ݳ��� +** ���ڲ���: <0��������ʧ�� +************************************************************************/ +int32_t transport_sendPacketBuffer( uint8_t* buf, int32_t buflen); + +/************************************************************************ +** ��������: transport_getdata +** ��������: �������ķ�ʽ����TCP���� +** ��ڲ���: unsigned char* buf�����ݻ����� +** int count�����ݳ��� +** ���ڲ���: <=0��������ʧ�� +************************************************************************/ +int transport_getdata(unsigned char* buf, int count); + +/************************************************************************ +** ��������: transport_open +** ��������: ��һ���ӿڣ����Һͷ����� �������� +** ��ڲ���: char* servip:���������� +** int port:�˿ں� +** ���ڲ���: <0������ʧ�� +************************************************************************/ +int32_t transport_open(int8_t* servip, int32_t port); + +/************************************************************************ +** ��������: transport_close +** ��������: �ر��׽��� +** ��ڲ���: unsigned char* buf�����ݻ����� +** int buflen�����ݳ��� +** ���ڲ���: <0��������ʧ�� +************************************************************************/ +int32_t transport_close(void); + + + +#endif From 5869154cca26edaecf181293cf849093210b6c0a Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Mon, 17 Jul 2023 14:23:08 +0800 Subject: [PATCH 03/21] delete online --- .../connection_app/mqtt_demo/Makefile | 1 - .../connection_app/mqtt_demo/online_mqtt.c | 328 ------------------ .../connection_app/mqtt_demo/online_mqtt.h | 29 -- .../resources/ethernet/LwIP/apps/Makefile | 2 +- 4 files changed, 1 insertion(+), 359 deletions(-) delete mode 100644 APP_Framework/Applications/connection_app/mqtt_demo/online_mqtt.c delete mode 100644 APP_Framework/Applications/connection_app/mqtt_demo/online_mqtt.h diff --git a/APP_Framework/Applications/connection_app/mqtt_demo/Makefile b/APP_Framework/Applications/connection_app/mqtt_demo/Makefile index 6f459e9f4..d8f57d094 100644 --- a/APP_Framework/Applications/connection_app/mqtt_demo/Makefile +++ b/APP_Framework/Applications/connection_app/mqtt_demo/Makefile @@ -1,6 +1,5 @@ ifeq ($(CONFIG_ADD_XIZI_FETURES),y) SRC_FILES += lwip_mqtt_demo.c -SRC_FILES += online_mqtt.c include $(KERNEL_ROOT)/compiler.mk endif diff --git a/APP_Framework/Applications/connection_app/mqtt_demo/online_mqtt.c b/APP_Framework/Applications/connection_app/mqtt_demo/online_mqtt.c deleted file mode 100644 index 64c7f7d1e..000000000 --- a/APP_Framework/Applications/connection_app/mqtt_demo/online_mqtt.c +++ /dev/null @@ -1,328 +0,0 @@ -#include -#include -#include - -/* lwip includes. */ -#include "lwip/apps/mqtt.h" -#include "lwip/ip4_addr.h" - - - - -static mqtt_client_t *s__mqtt_client_instance = NULL; //mqtt连接句柄，这里一定要设置全局变量，防止 lwip 底层重复申请空间 - -//MQTT 数据结构体 -struct mqtt_recv_buffer -{ - char recv_buffer[1024]; //储存接收的buffer - uint16_t recv_len; //记录已接收多少个字节的数据，MQTT的数据分包来的 - uint16_t recv_total; //MQTT接收数据的回调函数会有个总的大小 -}; - -//结构体初始化 -struct mqtt_recv_buffer s__mqtt_recv_buffer_g = { - .recv_len = 0, - .recv_total = 0, -}; - - - - - -/*! -* @brief MQTT 处理失败调用的函数 -* -* @param [in1] : MQTT 连接句柄 -* @param [in2] : MQTT 连接参数指针 -* -* @retval: None -*/ -void mqtt_error_process_callback(mqtt_client_t * client, void *arg) -{ - -} - - -/*! -* @brief mqtt 接收数据处理函数接口，需要在应用层进行处理 -* 执行条件：mqtt连接成功 -* -* @param [in1] : 用户提供的回调参数指针 -* @param [in2] : 接收的数据指针 -* @param [in3] : 接收数据长度 -* @retval: 处理的结果 -*/ -int mqtt_rec_data_process(void* arg, char *rec_buf, uint64_t buf_len) -{ - lw_print("recv_buffer = %s\n", rec_buf); - return 0; -} - -/*! -* @brief MQTT 订阅的回调函数 -* 执行条件：MQTT 连接成功 -* -* @param [in] : 用户提供的回调参数指针 -* @param [in] : MQTT 订阅结果 -* @retval: None -*/ -static void bsp_mqtt_request_cb(void *arg, err_t err) -{ - if ( arg == NULL ) - { - lw_print("bsp_mqtt_request_cb: input error@@\n"); - return; - } - - mqtt_client_t *client = (mqtt_client_t *)arg; - - if ( err != ERR_OK ) - { - lw_print("bsp_mqtt_request_cb: FAIL sub, sub again, err = %s\n", lwip_strerr(err)); - - //错误处理 - mqtt_error_process_callback(client, arg); - } - else - { - lw_print("bsp_mqtt_request_cb: sub SUCCESS!\n"); - } -} - - -/*! -* @brief mqtt 订阅 -* 执行条件：连接成功 -* -* @param [in1] : mqtt 连接句柄 -* @param [in2] : mqtt 发送 topic 指针 -* @param [in5] : qos -* @retval: 订阅状态 -*/ -static err_t bsp_mqtt_subscribe(mqtt_client_t* mqtt_client, char * sub_topic, uint8_t qos) -{ - lw_print("bsp_mqtt_subscribe: Enter\n"); - - if( ( mqtt_client == NULL) || ( sub_topic == NULL) || ( qos > 2 ) ) - { - lw_print("bsp_mqtt_subscribe: input error@@\n"); - return ERR_VAL; - } - - if ( mqtt_client_is_connected(mqtt_client) != true ) - { - lw_print("bsp_mqtt_subscribe: mqtt is not connected, return ERR_CLSD.\n"); - return ERR_CLSD; - } - - err_t err; - err = mqtt_subscribe(mqtt_client, sub_topic, qos, bsp_mqtt_request_cb, (void *)mqtt_client); // subscribe and call back. - - if (err != ERR_OK) - { - lw_print("bsp_mqtt_subscribe: mqtt_subscribe Fail, return:%s \n", lwip_strerr(err)); - } - else - { - lw_print("bsp_mqtt_subscribe: mqtt_subscribe SUCCESS, reason: %s\n", lwip_strerr(err)); - } - - return err; -} - -/*! -* @brief MQTT 连接成功的处理函数，需要的话在应用层定义 -* -* @param [in1] : MQTT 连接句柄 -* @param [in2] : MQTT 连接参数指针 -* -* @retval: None -*/ - -void mqtt_conn_suc_proc(mqtt_client_t *client, void *arg) -{ - char test_sub_topic[] = "/public/TEST/AidenHinGwenWong_sub"; - bsp_mqtt_subscribe(client,test_sub_topic,0); -} - - -/*! -* @brief MQTT 接收到数据的回调函数 -* 执行条件：MQTT 连接成功 -* -* @param [in1] : 用户提供的回调参数指针 -* @param [in2] : MQTT 收到的分包数据指针 -* @param [in3] : MQTT 分包数据长度 -* @param [in4] : MQTT 数据包的标志位 -* @retval: None -*/ -static void bsp_mqtt_incoming_data_cb(void *arg, const u8_t *data, u16_t len, u8_t flags) -{ - if( (data == NULL) || (len == 0) ) - { - lw_print("mqtt_client_incoming_data_cb: condition error @entry\n"); - return; - } - - if(s__mqtt_recv_buffer_g.recv_len + len < sizeof(s__mqtt_recv_buffer_g.recv_buffer)) - { - // - snprintf(&s__mqtt_recv_buffer_g.recv_buffer[s__mqtt_recv_buffer_g.recv_len], len, "%s", data); - s__mqtt_recv_buffer_g.recv_len += len; - } - - if ( (flags & MQTT_DATA_FLAG_LAST) == MQTT_DATA_FLAG_LAST ) - { - //处理数据 - mqtt_rec_data_process(arg , s__mqtt_recv_buffer_g.recv_buffer, s__mqtt_recv_buffer_g.recv_len); - - //已接收字节计数归0 - s__mqtt_recv_buffer_g.recv_len = 0; - - //清空接收buffer - memset(s__mqtt_recv_buffer_g.recv_buffer, 0, sizeof(s__mqtt_recv_buffer_g.recv_buffer)); - } - - - lw_print("mqtt_client_incoming_data_cb:reveiving incomming data.\n"); -} - -/*! -* @brief MQTT 接收到数据的回调函数 -* 执行条件：MQTT 连接成功 -* -* @param [in] : 用户提供的回调参数指针 -* @param [in] : MQTT 收到数据的topic -* @param [in] : MQTT 收到数据的总长度 -* @retval: None -*/ -static void bsp_mqtt_incoming_publish_cb(void *arg, const char *topic, u32_t tot_len) -{ - if( (topic == NULL) || (tot_len == 0) ) - { - lw_print("bsp_mqtt_incoming_publish_cb: condition error @entry\n"); - return; - } - - lw_print("bsp_mqtt_incoming_publish_cb: topic = %s.\n",topic); - lw_print("bsp_mqtt_incoming_publish_cb: tot_len = %d.\n",tot_len); - s__mqtt_recv_buffer_g.recv_total = tot_len; //需要接收的总字节 - s__mqtt_recv_buffer_g.recv_len = 0; //已接收字节计数归0 - - //清空接收buffer - memset(s__mqtt_recv_buffer_g.recv_buffer, 0, sizeof(s__mqtt_recv_buffer_g.recv_buffer)); -} - - -/*! -* @brief MQTT 连接状态的回调函数 -* -* @param [in] : MQTT 连接句柄 -* @param [in] : 用户提供的回调参数指针 -* @param [in] : MQTT 连接状态 -* @retval: None -*/ -static void bsp_mqtt_connection_cb(mqtt_client_t *client, void *arg, mqtt_connection_status_t status) -{ - if( client == NULL ) - { - lw_print("bsp_mqtt_connection_cb: condition error @entry\n"); - return; - } - lw_print("status:%d",status); - if ( status == MQTT_CONNECT_ACCEPTED ) //Successfully connected - { - lw_print("bsp_mqtt_connection_cb: Successfully connected\n"); - - // 注册接收数据的回调函数 - mqtt_set_inpub_callback(client, bsp_mqtt_incoming_publish_cb, bsp_mqtt_incoming_data_cb, arg); - - - - //成功处理函数 - mqtt_conn_suc_proc(client, arg); - } - else - { - lw_print("bsp_mqtt_connection_cb: Fail connected, status = %s\n", lwip_strerr(status) ); - //错误处理 - mqtt_error_process_callback(client, arg); - } -} - -static err_t bsp_mqtt_connect(void) -{ - lw_print("bsp_mqtt_connect: Enter!\n"); - err_t ret; - - struct mqtt_connect_client_info_t mqtt_connect_info = { - "Hc_MQTT_Test", /* 这里需要修改，以免在同一个服务器两个相同ID会发生冲突 */ - NULL, /* MQTT 服务器用户名 */ - NULL, /* MQTT 服务器密码 */ - 60, /* 与 MQTT 服务器保持连接时间，时间超过未发送数据会断开 */ - "/public/TEST/AidenHinGwenWong_pub",/* MQTT遗嘱的消息发送topic */ - "Offline_pls_check", /* MQTT遗嘱的消息，断开服务器的时候会发送 */ - 0, /* MQTT遗嘱的消息 Qos */ - 0 /* MQTT遗嘱的消息 Retain */ - }; - - ip_addr_t server_ip; - ip4_addr_set_u32(&server_ip, ipaddr_addr("120.76.100.197")); //MQTT服务器IP - - uint16_t server_port = 18830; //注意这里是 MQTT 的 TCP 连接方式的端口号！！！！ - - if (s__mqtt_client_instance == NULL) - { - // 句柄==NULL 才申请空间，否则无需重复申请 - s__mqtt_client_instance = mqtt_client_new(); - } - - if (s__mqtt_client_instance == NULL) - { - //防止申请失败 - lw_print("bsp_mqtt_connect: s__mqtt_client_instance malloc fail @@!!!\n"); - return ERR_MEM; - } - - //进行连接,注意：如果需要带入 arg ，arg必须是全局变量，局部变量指针会被回收，大坑！！！！！ - ret = mqtt_client_connect(s__mqtt_client_instance, &server_ip, server_port, bsp_mqtt_connection_cb, NULL, &mqtt_connect_info); - - /****************** - 小提示：连接错误不需要做任何操作，mqtt_client_connect 中注册的回调函数里面做判断并进行对应的操作 - *****************/ - - lw_print("bsp_mqtt_connect: connect to mqtt %s\n", lwip_strerr(ret)); - - return ret; -} - - -/* =========================================== - 初始化接口函数 -============================================== */ - -/*! -* @brief 封装 MQTT 初始化接口 -* 执行条件：无 -* -* @retval: 无 -*/ -void MQTTOnline(void) -{ - lw_print("Mqtt init..."); - - // 连接服务器 - bsp_mqtt_connect(); - - // 发送消息到服务器 - // char message_test[] = "Hello mqtt server"; - // for(int i = 0; i < 10; i++) - // { - // bsp_mqtt_publish(s__mqtt_client_instance,"/public/TEST/AidenHinGwenWong_pub",message_test,sizeof(message_test),1,0); - // PrivTaskDelay(1000); - // } - -} - - -PRIV_SHELL_CMD_FUNCTION(MQTTOnline, a tcp send sample, PRIV_SHELL_CMD_MAIN_ATTR); diff --git a/APP_Framework/Applications/connection_app/mqtt_demo/online_mqtt.h b/APP_Framework/Applications/connection_app/mqtt_demo/online_mqtt.h deleted file mode 100644 index abac5506f..000000000 --- a/APP_Framework/Applications/connection_app/mqtt_demo/online_mqtt.h +++ /dev/null @@ -1,29 +0,0 @@ - -#ifndef __BSP_MQTT_H -#define __BSP_MQTT_H - -/*----------------------------------------------------------- - * Includes files - *----------------------------------------------------------*/ - -/*----------------------------------------------------------- - * Exported constants - *----------------------------------------------------------*/ - - -/*----------------------------------------------------------- - * Exported macro - *----------------------------------------------------------*/ - -/*----------------------------------------------------------- - * Exported function - *----------------------------------------------------------*/ -/*! -* @brief 封装 MQTT 初始化接口 -* 执行条件：无 -* -* @retval: 无 -*/ -void bsp_mqtt_init(void); - -#endif /* __BSP_WOLFSSL_H */ diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/apps/Makefile b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/apps/Makefile index 03bc603dd..6f5f2913e 100644 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/apps/Makefile +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/apps/Makefile @@ -1,3 +1,3 @@ SRC_FILES += lwiperf/lwiperf.c http/http_client.c -SRC_FILES += mqtt/mqtt.c + include $(KERNEL_ROOT)/compiler.mk From b0eabde4f6acc46841134c2a5ffe25e0126519d6 Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Wed, 26 Jul 2023 11:31:29 +0800 Subject: [PATCH 04/21] modify features --- .../Applications/connection_app/mqtt_demo/Makefile | 4 ++-- .../connection_app/mqtt_demo/lwip_mqtt_demo.c | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/APP_Framework/Applications/connection_app/mqtt_demo/Makefile b/APP_Framework/Applications/connection_app/mqtt_demo/Makefile index d8f57d094..b0e21dc77 100644 --- a/APP_Framework/Applications/connection_app/mqtt_demo/Makefile +++ b/APP_Framework/Applications/connection_app/mqtt_demo/Makefile @@ -1,10 +1,10 @@ -ifeq ($(CONFIG_ADD_XIZI_FETURES),y) +ifeq ($(CONFIG_ADD_XIZI_FEATURES),y) SRC_FILES += lwip_mqtt_demo.c include $(KERNEL_ROOT)/compiler.mk endif include $(KERNEL_ROOT)/.config -ifeq ($(CONFIG_ADD_NUTTX_FETURES),y) +ifeq ($(CONFIG_ADD_NUTTX_FEATURES),y) include $(APPDIR)/Make.defs CSRCS += lwip_mqtt_demo.c include $(APPDIR)/Application.mk diff --git a/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c b/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c index 7209054bb..2d7d6fa29 100644 --- a/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c +++ b/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c @@ -1,7 +1,7 @@ #include #include "lwip_mqtt_demo.h" #include -#ifdef ADD_XIZI_FETURES +#ifdef ADD_XIZI_FEATURES #include #include #include "lwip/sys.h" @@ -14,7 +14,7 @@ #endif -#ifdef ADD_NUTTX_FETURES +#ifdef ADD_NUTTX_FEATURES #include #include #include @@ -482,7 +482,7 @@ void MqttSocketRecvTest(int argc, char *argv[]) // MqttSocketConfigParam(host_ip); -#ifdef ADD_XIZI_FETURES +#ifdef ADD_XIZI_FEATURES lwip_config_tcp(0, mqtt_demo_ipaddr, mqtt_demo_netmask, mqtt_demo_gwaddr); pthread_attr_t attr; @@ -490,7 +490,7 @@ void MqttSocketRecvTest(int argc, char *argv[]) attr.stacksize = LWIP_MQTT_DEMO_TASK_STACK_SIZE; #endif -#ifdef ADD_NUTTX_FETURES +#ifdef ADD_NUTTX_FEATURES pthread_attr_t attr = PTHREAD_ATTR_INITIALIZER; attr.priority = LWIP_mqtt_DEMO_TASK_PRIO; attr.stacksize = LWIP_mqtt_DEMO_TASK_STACK_SIZE; @@ -706,7 +706,7 @@ void MqttSocketSendTest(int argc, char *argv[]) // MqttSocketConfigParam(host_ip); -#ifdef ADD_XIZI_FETURES +#ifdef ADD_XIZI_FEATURES lwip_config_tcp(0, mqtt_demo_ipaddr, mqtt_demo_netmask, mqtt_demo_gwaddr); pthread_attr_t attr; @@ -714,7 +714,7 @@ void MqttSocketSendTest(int argc, char *argv[]) attr.stacksize = LWIP_MQTT_DEMO_TASK_STACK_SIZE; #endif -#ifdef ADD_NUTTX_FETURES +#ifdef ADD_NUTTX_FEATURES pthread_attr_t attr = PTHREAD_ATTR_INITIALIZER; attr.priority = LWIP_mqtt_DEMO_TASK_PRIO; attr.stacksize = LWIP_mqtt_DEMO_TASK_STACK_SIZE; From b481abd4eb8331034727831a006fb83cb52411c5 Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Mon, 7 Aug 2023 09:41:15 +0800 Subject: [PATCH 05/21] cortex m7 emulator --- Ubiquitous/XiZi_IIoT/Makefile | 2 +- Ubiquitous/XiZi_IIoT/arch/arm/Makefile | 5 + .../XiZi_IIoT/arch/arm/cortex-m7/Makefile | 5 + .../XiZi_IIoT/arch/arm/cortex-m7/V2M/Makefile | 3 + .../arch/arm/cortex-m7/V2M/arch_interrupt.h | 39 + .../XiZi_IIoT/arch/arm/cortex-m7/V2M/boot.S | 204 ++ .../arch/arm/cortex-m7/V2M/interrupt.c | 89 + .../arch/arm/cortex-m7/V2M/interrupt_vector.S | 319 ++ .../board/cortex-m7-emulator/.defconfig | 294 ++ .../board/cortex-m7-emulator/Kconfig | 61 + .../board/cortex-m7-emulator/Makefile | 8 + .../board/cortex-m7-emulator/board.c | 205 ++ .../board/cortex-m7-emulator/board.h | 64 + .../board/cortex-m7-emulator/config.mk | 15 + .../board/cortex-m7-emulator/link.lds | 252 ++ .../board/cortex-m7-emulator/link_m7.lds | 252 ++ .../CMSIS/Include/cmsis_compiler.h | 266 ++ .../CMSIS/Include/cmsis_gcc.h | 2088 +++++++++++++ .../CMSIS/Include/cmsis_version.h | 39 + .../CMSIS/Include/core_cm7.h | 2660 +++++++++++++++++ .../CMSIS/Include/mpu_armv7.h | 197 ++ .../third_party_driver/CMSIS/LICENSE.txt | 201 ++ .../third_party_driver/Kconfig | 10 + .../third_party_driver/Makefile | 3 + .../third_party_driver/common/Makefile | 5 + .../third_party_driver/common/clock_config.c | 70 + .../third_party_driver/common/fsl_common.c | 155 + .../common/startup_CMSDK_CM7.c | 418 +++ .../common/system_CMSDK_CM7.c | 79 + .../include/V2M/CMSDK_CM7_SP.h | 616 ++++ .../third_party_driver/include/V2M/Device.h | 40 + .../include/V2M/Driver_Common.h | 69 + .../include/V2M/Driver_USART.h | 341 +++ .../include/V2M/RTE_Components.h | 26 + .../include/V2M/RTE_Device.h | 50 + .../include/V2M/USART_V2M-MPS2.h | 99 + .../include/V2M/system_CMSDK_CM7.h | 68 + .../third_party_driver/include/clock_config.h | 76 + .../third_party_driver/include/connect_gpio.h | 38 + .../third_party_driver/include/connect_uart.h | 42 + .../third_party_driver/include/fsl_clock.h | 0 .../third_party_driver/include/fsl_common.h | 605 ++++ .../include/fsl_device_registers.h | 46 + .../third_party_driver/uart/Kconfig | 74 + .../third_party_driver/uart/Makefile | 3 + .../third_party_driver/uart/USART_V2M-MPS2.c | 50 + .../third_party_driver/uart/connect_uart.c | 1221 ++++++++ .../third_party_driver/uart/stdout_uart.c | 133 + Ubiquitous/XiZi_IIoT/path_kernel.mk | 16 + 49 files changed, 11620 insertions(+), 1 deletion(-) create mode 100644 Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/Makefile create mode 100644 Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/arch_interrupt.h create mode 100644 Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/boot.S create mode 100644 Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/interrupt.c create mode 100644 Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/interrupt_vector.S create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/.defconfig create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/Kconfig create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/Makefile create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.c create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.h create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/config.mk create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link.lds create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link_m7.lds create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/cmsis_compiler.h create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/cmsis_gcc.h create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/cmsis_version.h create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/core_cm7.h create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/mpu_armv7.h create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/LICENSE.txt create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/Kconfig create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/Makefile create mode 100755 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/Makefile create mode 100755 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/clock_config.c create mode 100755 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/fsl_common.c create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/startup_CMSDK_CM7.c create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/system_CMSDK_CM7.c create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/CMSDK_CM7_SP.h create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/Device.h create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/Driver_Common.h create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/Driver_USART.h create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/RTE_Components.h create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/RTE_Device.h create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/USART_V2M-MPS2.h create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/system_CMSDK_CM7.h create mode 100755 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/clock_config.h create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/connect_gpio.h create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/connect_uart.h create mode 100755 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/fsl_clock.h create mode 100755 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/fsl_common.h create mode 100755 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/fsl_device_registers.h create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/Kconfig create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/Makefile create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/USART_V2M-MPS2.c create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/connect_uart.c create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/stdout_uart.c diff --git a/Ubiquitous/XiZi_IIoT/Makefile b/Ubiquitous/XiZi_IIoT/Makefile index 251cd08de..b16f46a94 100755 --- a/Ubiquitous/XiZi_IIoT/Makefile +++ b/Ubiquitous/XiZi_IIoT/Makefile @@ -7,7 +7,7 @@ MAKEFLAGS += --no-print-directory riscv_support := kd233 maix-go hifive1-rev-B gapuino gd32vf103-rvstar rv32m1-vega aiit-riscv64-board xidatong-riscv64 edu-riscv64 arm_support += stm32f407-st-discovery stm32f407zgt6 stm32f103-nano nuvoton-m2354 ok1052-c imxrt1176-sbc aiit-arm32-board xidatong-arm32 xiwangtong-arm32 hc32f4a0 -emulator_support += hifive1-emulator k210-emulator cortex-m0-emulator cortex-m3-emulator cortex-m4-emulator +emulator_support += hifive1-emulator k210-emulator cortex-m0-emulator cortex-m3-emulator cortex-m4-emulator cortex-m7-emulator support := $(riscv_support) $(arm_support) $(emulator_support) SRC_DIR := diff --git a/Ubiquitous/XiZi_IIoT/arch/arm/Makefile b/Ubiquitous/XiZi_IIoT/arch/arm/Makefile index c612d35b7..21150d06e 100644 --- a/Ubiquitous/XiZi_IIoT/arch/arm/Makefile +++ b/Ubiquitous/XiZi_IIoT/arch/arm/Makefile @@ -35,6 +35,11 @@ SRC_DIR := shared SRC_DIR += cortex-m7 endif +ifeq ($(CONFIG_BOARD_CORTEX_V2M_EVB),y) +SRC_DIR := shared +SRC_DIR += cortex-m7 +endif + ifeq ($(CONFIG_BOARD_IMXRT1176_SBC_EVB),y) SRC_DIR := shared SRC_DIR += cortex-m7 diff --git a/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/Makefile b/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/Makefile index cc89c7fa3..509b1107c 100644 --- a/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/Makefile +++ b/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/Makefile @@ -1,3 +1,8 @@ +ifeq ($(CONFIG_BOARD_CORTEX_M7_EVB),y) SRC_FILES := boot.S interrupt.c interrupt_vector.S +endif +ifeq ($(CONFIG_BOARD_CORTEX_V2M_EVB),y) +SRC_DIR += V2M +endif include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/Makefile b/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/Makefile new file mode 100644 index 000000000..cc89c7fa3 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := boot.S interrupt.c interrupt_vector.S + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/arch_interrupt.h b/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/arch_interrupt.h new file mode 100644 index 000000000..d90311c39 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/arch_interrupt.h @@ -0,0 +1,39 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#ifndef ARCH_INTERRUPT_H__ +#define ARCH_INTERRUPT_H__ + +#include + +#define ARCH_MAX_IRQ_NUM (256) + +//#define ARCH_IRQ_NUM_OFFSET 0 + +//#define SYSTICK_IRQN 15 +//#define UART1_IRQn 36 +//#define UART2_IRQn 37 + +#define ARCH_IRQ_NUM_OFFSET 16 + +#define SYSTICK_IRQN -1 +#define UART0RX_IRQn 0 +#define UART0TX_IRQn 1 +#define UART1RX_IRQn 2 + +// #define USB1_IRQn 113 +// #define USB2_IRQn 112 + +int32 ArchEnableHwIrq(uint32 irq_num); +int32 ArchDisableHwIrq(uint32 irq_num); + +#endif diff --git a/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/boot.S b/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/boot.S new file mode 100644 index 000000000..2eb699f9c --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/boot.S @@ -0,0 +1,204 @@ +/* ------------------------------------------------------------------------- */ +/* @file: startup_MIMXRT1052.s */ +/* @purpose: CMSIS Cortex-M7 Core Device Startup File */ +/* MIMXRT1052 */ +/* @version: 1.0 */ +/* @date: 2018-9-21 */ +/* @build: b180921 */ +/* ------------------------------------------------------------------------- */ +/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2018 NXP */ +/* All rights reserved. */ +/* */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + + +/** +* @file boot.S +* @brief Cortex-M7 start function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-28 +*/ + +/************************************************* +File name: boot.S +Description: Contex-M7 start function function +Others: take startup_MIMXRT1052.s for references +History: +1. Date: 2021-05-28 +Author: AIIT XUOS Lab +Modification: +1. add OS entry function +*************************************************/ + + .syntax unified + .arch armv7-m + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +#ifdef __BOOTLOADER /* BOOT */ + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] + ldr r2, [r1] + msr msp, r2 + + ldr r0,=SystemInit + blx r0 + +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __bootloader_end: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * __noncachedata_start__/__noncachedata_end__ : none cachable region + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + /* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LoopCopy0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LoopCopy0 + + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LoopCopy1: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LoopCopy1 + + ldr r0,=ota_entry + blx r0 +#else /* APP */ + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] + ldr r2, [r1] + msr msp, r2 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * __noncachedata_start__/__noncachedata_end__ : none cachable region + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif +#ifdef __STARTUP_INITIALIZE_NONCACHEDATA + ldr r2, =__noncachedata_start__ + ldr r3, =__noncachedata_init_end__ +#if 1 +.LC2: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC2 +#else + subs r3, r2 + ble .LC3 +.LC2: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC2 +.LC3: +#endif +/* zero inited ncache section initialization */ + ldr r3, =__noncachedata_end__ + movs r0,0 +.LC4: + cmp r2,r3 + itt lt + strlt r0,[r2],#4 + blt .LC4 +#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */ + +#if 1 +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC5: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC5 +#endif /* __STARTUP_CLEAR_BSS */ + + ldr r0,=entry + blx r0 +#endif /* MCUBOOT_BOOTLOADER */ + +.size Reset_Handler, . - Reset_Handler \ No newline at end of file diff --git a/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/interrupt.c b/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/interrupt.c new file mode 100644 index 000000000..5d5748252 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/interrupt.c @@ -0,0 +1,89 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file interrupt.c +* @brief support arm cortex-m7 interrupt function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-28 +*/ + +#include +#include +#include "fsl_common.h" + +x_base __attribute__((naked)) DisableLocalInterrupt() +{ + asm volatile ("MRS r0, PRIMASK"); + asm volatile ("CPSID I"); + asm volatile ("BX LR "); +} + +void __attribute__((naked)) EnableLocalInterrupt(x_base level) +{ + asm volatile ("MSR PRIMASK, r0"); + asm volatile ("BX LR"); +} + +int32 ArchEnableHwIrq(uint32 irq_num) +{ + EnableIRQ(irq_num); + return EOK; +} + +int32 ArchDisableHwIrq(uint32 irq_num) +{ + DisableIRQ(irq_num); + return EOK; +} + +extern void KTaskOsAssignAfterIrq(void *context); + +void IsrEntry() +{ + uint32 ipsr; + + __asm__ volatile("MRS %0, IPSR" : "=r"(ipsr)); + if (ipsr!=17){ + KPrintf("%d\n",ipsr); + } + + isrManager.done->incCounter(); + isrManager.done->handleIrq(ipsr); + KTaskOsAssignAfterIrq(NONE); + isrManager.done->decCounter(); + +} + +void UsageFault_Handler(int irqn, void *arg) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +void BusFault_Handler(int irqn, void *arg) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +void NMI_Handler(int irqn, void *arg) +{ + while (1) + { + } +} diff --git a/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/interrupt_vector.S b/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/interrupt_vector.S new file mode 100644 index 000000000..949c8b809 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/arch/arm/cortex-m7/V2M/interrupt_vector.S @@ -0,0 +1,319 @@ +/* ------------------------------------------------------------------------- */ +/* @file: startup_MIMXRT1052.s */ +/* @purpose: CMSIS Cortex-M7 Core Device Startup File */ +/* MIMXRT1052 */ +/* @version: 1.0 */ +/* @date: 2018-9-21 */ +/* @build: b180921 */ +/* ------------------------------------------------------------------------- */ +/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2018 NXP */ +/* All rights reserved. */ +/* */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + + +/** +* @file interrupt_vector.S +* @brief vector table for Cortex M7 +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-28 +*/ + +/************************************************* +File name: interrupt_vector.S +Description: vector table for a Cortex M7 +Others: +History: +1. Date: 2021-05-28 +Author: AIIT XUOS Lab +Modification: +1. add IsrEntry as default isr function +*************************************************/ + + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Initial Stack Pointer */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFaultHandler /* Hard Fault Handler*/ + .long MemFaultHandler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* -5 SVC Handler */ + .long DebugMon_Handler /* -4 Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* -2 PendSV Handler */ + .long SysTick_Handler /* -1 SysTick Handler */ + + /* Interrupts */ + .long UART0RX_Handler /* 0 UART 0 receive interrupt */ + .long UART0TX_Handler /* 1 UART 0 transmit interrupt */ + .long UART1RX_Handler /* 2 UART 1 receive interrupt */ + .long UART1TX_Handler /* 3 UART 1 transmit interrupt */ + .long UART2RX_Handler /* 4 UART 2 receive interrupt */ + .long UART2TX_Handler /* 5 UART 2 transmit interrupt */ + .long GPIO0ALL_Handler /* 6 GPIO 0 combined interrupt */ + .long GPIO1ALL_Handler /* 7 GPIO 1 combined interrupt */ + .long TIMER0_Handler /* 8 Timer 0 interrupt */ + .long TIMER1_Handler /* 9 Timer 1 interrupt */ + .long DUALTIMER_Handler /* 10 Dual Timer interrupt */ + .long SPI_0_1_Handler /* 11 SPI 0, 1 interrupt */ + .long UART_0_1_2_OVF_Handler /* 12 UART overflow (0, 1 & 2) interrupt */ + .long ETHERNET_Handler /* 13 Ethernet interrupt */ + .long I2S_Handler /* 14 Audio I2S interrupt */ + .long TOUCHSCREEN_Handler /* 15 Touch Screen interrupt */ + .long GPIO2_Handler /* 16 GPIO 2 combined interrupt */ + .long GPIO3_Handler /* 17 GPIO 3 combined interrupt */ + .long UART3RX_Handler /* 18 UART 3 receive interrupt */ + .long UART3TX_Handler /* 19 UART 3 transmit interrupt */ + .long UART4RX_Handler /* 20 UART 4 receive interrupt */ + .long UART4TX_Handler /* 21 UART 4 transmit interrupt */ + .long SPI_2_Handler /* 22 SPI 2 interrupt */ + .long SPI_3_4_Handler /* 23 SPI 3, 4 interrupt */ + .long GPIO0_0_Handler /* 24 GPIO 0 individual interrupt ( 0) */ + .long GPIO0_1_Handler /* 25 GPIO 0 individual interrupt ( 1) */ + .long GPIO0_2_Handler /* 26 GPIO 0 individual interrupt ( 2) */ + .long GPIO0_3_Handler /* 27 GPIO 0 individual interrupt ( 3) */ + .long GPIO0_4_Handler /* 28 GPIO 0 individual interrupt ( 4) */ + .long GPIO0_5_Handler /* 29 GPIO 0 individual interrupt ( 5) */ + .long GPIO0_6_Handler /* 30 GPIO 0 individual interrupt ( 6) */ + .long GPIO0_7_Handler /* 31 GPIO 0 individual interrupt ( 7) */ + .long 0 /* 32 Reserved */ + .long 0 /* 33 Reserved */ + .long 0 /* 34 Reserved */ + .long 0 /* 35 Reserved */ + .long 0 /* 36 Reserved */ + .long 0 /* 37 Reserved */ + .long 0 /* 38 Reserved */ + .long 0 /* 39 Reserved */ + .long 0 /* 40 Reserved */ + .long 0 /* 41 Reserved */ + .long 0 /* 42 Reserved */ + .long 0 /* 43 Reserved */ + .long 0 /* 44 Reserved */ + .long 0 /* 45 Reserved */ + .long 0 /* 46 Reserved */ + .long 0 /* 47 Reserved */ + .long 0 /* 48 Reserved */ + .long 0 /* 49 Reserved */ + .long 0 /* 50 Reserved */ + .long 0 /* 51 Reserved */ + .long 0 /* 52 Reserved */ + .long 0 /* 53 Reserved */ + .long 0 /* 54 Reserved */ + .long 0 /* 55 Reserved */ + .long 0 /* 56 Reserved */ + .long 0 /* 57 Reserved */ + .long 0 /* 58 Reserved */ + .long 0 /* 59 Reserved */ + .long 0 /* 60 Reserved */ + .long 0 /* 61 Reserved */ + .long 0 /* 62 Reserved */ + .long 0 /* 63 Reserved */ + .long 0 /* 64 Reserved */ + .long 0 /* 65 Reserved */ + .long 0 /* 66 Reserved */ + .long 0 /* 67 Reserved */ + .long 0 /* 68 Reserved */ + .long 0 /* 69 Reserved */ + .long 0 /* 70 Reserved */ + .long 0 /* 71 Reserved */ + .long 0 /* 72 Reserved */ + .long 0 /* 73 Reserved */ + .long 0 /* 74 Reserved */ + .long 0 /* 75 Reserved */ + .long 0 /* 76 Reserved */ + .long 0 /* 77 Reserved */ + .long 0 /* 78 Reserved */ + .long 0 /* 79 Reserved */ + .long 0 /* 80 Reserved */ + .long 0 /* 81 Reserved */ + .long 0 /* 82 Reserved */ + .long 0 /* 83 Reserved */ + .long 0 /* 84 Reserved */ + .long 0 /* 85 Reserved */ + .long 0 /* 86 Reserved */ + .long 0 /* 87 Reserved */ + .long 0 /* 88 Reserved */ + .long 0 /* 89 Reserved */ + .long 0 /* 90 Reserved */ + .long 0 /* 91 Reserved */ + .long 0 /* 92 Reserved */ + .long 0 /* 93 Reserved */ + .long 0 /* 94 Reserved */ + .long 0 /* 95 Reserved */ + .long 0 /* 96 Reserved */ + .long 0 /* 97 Reserved */ + .long 0 /* 98 Reserved */ + .long 0 /* 99 Reserved */ + .long 0 /* 100 Reserved */ + .long 0 /* 101 Reserved */ + .long 0 /* 102 Reserved */ + .long 0 /* 103 Reserved */ + .long 0 /* 104 Reserved */ + .long 0 /* 105 Reserved */ + .long 0 /* 106 Reserved */ + .long 0 /* 107 Reserved */ + .long 0 /* 108 Reserved */ + .long 0 /* 109 Reserved */ + .long 0 /* 110 Reserved */ + .long 0 /* 111 Reserved */ + .long 0 /* 112 Reserved */ + .long 0 /* 113 Reserved */ + .long 0 /* 114 Reserved */ + .long 0 /* 115 Reserved */ + .long 0 /* 116 Reserved */ + .long 0 /* 117 Reserved */ + .long 0 /* 118 Reserved */ + .long 0 /* 119 Reserved */ + .long 0 /* 120 Reserved */ + .long 0 /* 121 Reserved */ + .long 0 /* 122 Reserved */ + .long 0 /* 123 Reserved */ + .long 0 /* 124 Reserved */ + .long 0 /* 125 Reserved */ + .long 0 /* 126 Reserved */ + .long 0 /* 127 Reserved */ + .long 0 /* 128 Reserved */ + .long 0 /* 129 Reserved */ + .long 0 /* 130 Reserved */ + .long 0 /* 131 Reserved */ + .long 0 /* 132 Reserved */ + .long 0 /* 133 Reserved */ + .long 0 /* 134 Reserved */ + .long 0 /* 135 Reserved */ + .long 0 /* 136 Reserved */ + .long 0 /* 137 Reserved */ + .long 0 /* 138 Reserved */ + .long 0 /* 139 Reserved */ + .long 0 /* 140 Reserved */ + .long 0 /* 141 Reserved */ + .long 0 /* 142 Reserved */ + .long 0 /* 143 Reserved */ + .long 0 /* 144 Reserved */ + .long 0 /* 145 Reserved */ + .long 0 /* 146 Reserved */ + .long 0 /* 147 Reserved */ + .long 0 /* 148 Reserved */ + .long 0 /* 149 Reserved */ + .long 0 /* 150 Reserved */ + .long 0 /* 151 Reserved */ + .long 0 /* 152 Reserved */ + .long 0 /* 153 Reserved */ + .long 0 /* 154 Reserved */ + .long 0 /* 155 Reserved */ + .long 0 /* 156 Reserved */ + .long 0 /* 157 Reserved */ + .long 0 /* 158 Reserved */ + .long 0 /* 159 Reserved */ + .long 0 /* 160 Reserved */ + .long 0 /* 161 Reserved */ + .long 0 /* 162 Reserved */ + .long 0 /* 163 Reserved */ + .long 0 /* 164 Reserved */ + .long 0 /* 165 Reserved */ + .long 0 /* 166 Reserved */ + .long 0 /* 167 Reserved */ + .long 0 /* 168 Reserved */ + .long 0 /* 169 Reserved */ + .long 0 /* 170 Reserved */ + .long 0 /* 171 Reserved */ + .long 0 /* 172 Reserved */ + .long 0 /* 173 Reserved */ + .long 0 /* 174 Reserved */ + .long 0 /* 175 Reserved */ + .long 0 /* 176 Reserved */ + .long 0 /* 177 Reserved */ + .long 0 /* 178 Reserved */ + .long 0 /* 179 Reserved */ + .long 0 /* 180 Reserved */ + .long 0 /* 181 Reserved */ + .long 0 /* 182 Reserved */ + .long 0 /* 183 Reserved */ + .long 0 /* 184 Reserved */ + .long 0 /* 185 Reserved */ + .long 0 /* 186 Reserved */ + .long 0 /* 187 Reserved */ + .long 0 /* 188 Reserved */ + .long 0 /* 189 Reserved */ + .long 0 /* 190 Reserved */ + .long 0 /* 191 Reserved */ + .long 0 /* 192 Reserved */ + .long 0 /* 193 Reserved */ + .long 0 /* 194 Reserved */ + .long 0 /* 195 Reserved */ + .long 0 /* 196 Reserved */ + .long 0 /* 197 Reserved */ + .long 0 /* 198 Reserved */ + .long 0 /* 199 Reserved */ + .long 0 /* 200 Reserved */ + .long 0 /* 201 Reserved */ + .long 0 /* 202 Reserved */ + .long 0 /* 203 Reserved */ + .long 0 /* 204 Reserved */ + .long 0 /* 205 Reserved */ + .long 0 /* 206 Reserved */ + .long 0 /* 207 Reserved */ + .long 0 /* 208 Reserved */ + .long 0 /* 209 Reserved */ + .long 0 /* 210 Reserved */ + .long 0 /* 211 Reserved */ + .long 0 /* 212 Reserved */ + .long 0 /* 213 Reserved */ + .long 0 /* 214 Reserved */ + .long 0 /* 215 Reserved */ + .long 0 /* 216 Reserved */ + .long 0 /* 217 Reserved */ + .long 0 /* 218 Reserved */ + .long 0 /* 219 Reserved */ + .long 0 /* 220 Reserved */ + .long 0 /* 221 Reserved */ + .long 0 /* 222 Reserved */ + .long 0 /* 223 Reserved */ + #if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT + .long ARM_VSI0_Handler /* 224 VSI 0 interrupt */ + .long ARM_VSI1_Handler /* 225 VSI 1 interrupt */ + .long ARM_VSI2_Handler /* 226 VSI 2 interrupt */ + .long ARM_VSI3_Handler /* 227 VSI 3 interrupt */ + .long ARM_VSI4_Handler /* 228 VSI 4 interrupt */ + .long ARM_VSI5_Handler /* 229 VSI 5 interrupt */ + .long ARM_VSI6_Handler /* 230 VSI 6 interrupt */ + .long ARM_VSI7_Handler /* 231 VSI 7 interrupt */ + #else + .long 0 /* 224 reserved */ + .long 0 /* 225 reserved */ + .long 0 /* 226 reserved */ + .long 0 /* 227 reserved */ + .long 0 /* 228 reserved */ + .long 0 /* 229 reserved */ + .long 0 /* 230 reserved */ + .long 0 /* 231 reserved */ + #endif + .long 0 /* 232 reserved */ + .long 0 /* 233 reserved */ + .long 0 /* 234 reserved */ + .long 0 /* 235 reserved */ + .long 0 /* 236 reserved */ + .long 0 /* 237 reserved */ + .long 0 /* 238 reserved */ + .long 0 /* 239 reserved */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/.defconfig b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/.defconfig new file mode 100644 index 000000000..e9a899147 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/.defconfig @@ -0,0 +1,294 @@ +# +# Automatically generated file; DO NOT EDIT. +# XiZi_IIoT Project Configuration +# +CONFIG_BOARD_CORTEX_M7_EVB=y +CONFIG_ARCH_ARM=y + +# +# xidatong-arm32 feature +# +CONFIG_BSP_USING_LPUART=y +CONFIG_BSP_USING_LPUART1=y +CONFIG_SERIAL_BUS_NAME_1="uart1" +CONFIG_SERIAL_DRV_NAME_1="uart1_drv" +CONFIG_SERIAL_1_DEVICE_NAME_0="uart1_dev1" +CONFIG_BSP_USING_LPUART2=y +CONFIG_SERIAL_BUS_NAME_2="uart2" +CONFIG_SERIAL_DRV_NAME_2="uart2_drv" +CONFIG_SERIAL_2_DEVICE_NAME_0="uart2_dev2" +CONFIG_BSP_USING_LPUART3=y +CONFIG_SERIAL_BUS_NAME_3="uart3" +CONFIG_SERIAL_DRV_NAME_3="uart3_drv" +CONFIG_SERIAL_3_DEVICE_NAME_0="uart3_dev3" +# CONFIG_BSP_USING_LPUART4 is not set +# CONFIG_BSP_USING_LPUART8 is not set +# CONFIG_BSP_USING_CH438 is not set +CONFIG_BSP_USING_GPIO=y +CONFIG_PIN_BUS_NAME="pin" +CONFIG_PIN_DRIVER_NAME="pin_drv" +CONFIG_PIN_DEVICE_NAME="pin_dev" +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_LWIP is not set +# CONFIG_BSP_USING_SEMC is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_TOUCH is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_WDT is not set + +# +# config default board resources +# + +# +# config board app name +# +CONFIG_BOARD_APP_NAME="/XiUOS_xidatong_app.bin" + +# +# config board service table +# +CONFIG_SERVICE_TABLE_ADDRESS=0x2007F0000 +CONFIG___STACKSIZE__=4096 + +# +# config board peripheral +# +# CONFIG_MOUNT_SDCARD is not set +# CONFIG_MOUNT_USB is not set + +# +# Hardware feature +# +CONFIG_RESOURCES_SERIAL=y +CONFIG_SERIAL_USING_DMA=y +CONFIG_SERIAL_RB_BUFSZ=128 +CONFIG_RESOURCES_PIN=y + +# +# Kernel feature +# + +# +# separate compile(choose none for compile once) +# +# CONFIG_SEPARATE_COMPILE is not set +# CONFIG_COMPILER_APP is not set +# CONFIG_APP_STARTUP_FROM_SDCARD is not set +CONFIG_APP_STARTUP_FROM_FLASH=y +# CONFIG_COMPILER_KERNEL is not set + +# +# Memory Management +# +# CONFIG_KERNEL_MEMBLOCK is not set +CONFIG_MEM_ALIGN_SIZE=8 +# CONFIG_MEM_EXTERN_SRAM is not set +CONFIG_MM_PAGE_SIZE=4096 + +# +# Using small memory allocator +# +CONFIG_KERNEL_SMALL_MEM_ALLOC=y +CONFIG_SMALL_NUMBER_32B=64 +CONFIG_SMALL_NUMBER_64B=32 + +# +# Task feature +# +CONFIG_USER_APPLICATION=y +# CONFIG_TASK_ISOLATION is not set + +# +# Inter-Task communication +# +CONFIG_KERNEL_SEMAPHORE=y +CONFIG_KERNEL_MUTEX=y +CONFIG_KERNEL_EVENT=y +CONFIG_KERNEL_MESSAGEQUEUE=y +# CONFIG_KERNEL_SOFTTIMER is not set +CONFIG_SCHED_POLICY_RR_REMAINSLICE=y +# CONFIG_SCHED_POLICY_RR is not set +# CONFIG_SCHED_POLICY_FIFO is not set +# CONFIG_KTASK_PRIORITY_8 is not set +CONFIG_KTASK_PRIORITY_32=y +# CONFIG_KTASK_PRIORITY_256 is not set +CONFIG_KTASK_PRIORITY_MAX=32 +CONFIG_TICK_PER_SECOND=1000 +CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y +CONFIG_IDLE_KTASK_STACKSIZE=1024 +CONFIG_ZOMBIE_KTASK_STACKSIZE=2048 + +# +# Kernel Console +# +CONFIG_KERNEL_CONSOLE=y +CONFIG_KERNEL_BANNER=y +CONFIG_KERNEL_CONSOLEBUF_SIZE=128 + +# +# Kernel Hook +# +# CONFIG_KERNEL_HOOK is not set + +# +# Command shell +# +CONFIG_TOOL_SHELL=y +CONFIG_SHELL_ENTER_CR=y +CONFIG_SHELL_ENTER_LF=y +CONFIG_SHELL_ENTER_CR_AND_LF=y +# CONFIG_SHELL_ENTER_CRLF is not set + +# +# Set shell user control +# +CONFIG_SHELL_DEFAULT_USER="letter" +CONFIG_SHELL_DEFAULT_USER_PASSWORD="" +CONFIG_SHELL_LOCK_TIMEOUT=10000 + +# +# Set shell config param +# +CONFIG_SHELL_TASK_STACK_SIZE=4096 +CONFIG_SHELL_TASK_PRIORITY=20 +CONFIG_SHELL_MAX_NUMBER=5 +CONFIG_SHELL_PARAMETER_MAX_NUMBER=8 +CONFIG_SHELL_HISTORY_MAX_NUMBER=5 +CONFIG_SHELL_PRINT_BUFFER=128 +CONFIG_SHELL_HELP_SHOW_PERMISSION=y +# CONFIG_SHELL_HELP_LIST_USER is not set +CONFIG_SHELL_HELP_LIST_VAR=y +# CONFIG_SHELL_HELP_LIST_KEY is not set + +# +# Kernel data structure Manage +# +CONFIG_KERNEL_QUEUEMANAGE=y +CONFIG_KERNEL_WORKQUEUE=y +CONFIG_WORKQUEUE_KTASK_STACKSIZE=2048 +CONFIG_WORKQUEUE_KTASK_PRIORITY=23 +CONFIG_QUEUE_MAX=16 +CONFIG_KERNEL_WAITQUEUE=y +CONFIG_KERNEL_DATAQUEUE=y +# CONFIG_KERNEL_CIRCULAR_AREA is not set +# CONFIG_KERNEL_AVL_TREE is not set + +# +# Kernel components init +# +CONFIG_KERNEL_COMPONENTS_INIT=y +CONFIG_ENV_INIT_KTASK_STACK_SIZE=8192 +CONFIG_KERNEL_USER_MAIN=y +CONFIG_NAME_NUM_MAX=32 +# CONFIG_KERNEL_DEBUG is not set +# CONFIG_ARCH_SMP is not set + +# +# hash table config +# +CONFIG_ID_HTABLE_SIZE=16 +CONFIG_ID_NUM_MAX=128 +# CONFIG_KERNEL_TEST is not set + +# +# Lib +# +CONFIG_LIB=y +CONFIG_LIB_POSIX=y +CONFIG_LIB_NEWLIB=y +# CONFIG_LIB_MUSLLIB is not set + +# +# C++ features +# +# CONFIG_LIB_CPLUSPLUS is not set + +# +# File system +# +# CONFIG_FS_VFS=y +# CONFIG_VFS_USING_WORKDIR=y +# CONFIG_FS_VFS_DEVFS=y +# CONFIG_FS_VFS_FATFS=y +# CONFIG_FS_CH376 is not set +# CONFIG_FS_LWEXT4 is not set + +# +# APP_Framework +# + +# +# Framework +# +CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y +CONFIG_ADD_XIZI_FEATURES=y +# CONFIG_ADD_NUTTX_FEATURES is not set +# CONFIG_ADD_RTTHREAD_FEATURES is not set +# CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set +# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set +# CONFIG_SUPPORT_KNOWING_FRAMEWORK is not set +# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set + +# +# Security +# +# CONFIG_CRYPTO is not set +# CONFIG_MBEDTLS is not set + +# +# Applications +# + +# +# config stack size and priority of main task +# +CONFIG_MAIN_KTASK_STACK_SIZE=4096 +CONFIG_MAIN_KTASK_PRIORITY=16 + +# +# ota app +# +# CONFIG_APPLICATION_OTA is not set + +# +# test app +# +# CONFIG_USER_TEST is not set + +# +# connection app +# +# CONFIG_APPLICATION_CONNECTION is not set + +# +# control app +# + +# +# knowing app +# +# CONFIG_APPLICATION_KNOWING is not set + +# +# sensor app +# +# CONFIG_APPLICATION_SENSOR is not set +# CONFIG_USING_EMBEDDED_DATABASE_APP is not set +# CONFIG_APP_USING_WEBNET is not set + +# +# lib +# +CONFIG_APP_SELECT_NEWLIB=y +# CONFIG_APP_SELECT_OTHER_LIB is not set +# CONFIG_LIB_USING_CJSON is not set +# CONFIG_LIB_USING_QUEUE is not set +# CONFIG_LIB_LV is not set + +# +# LVGL configuration +# +# CONFIG_LV_CONF_MINIMAL is not set +# CONFIG_USING_EMBEDDED_DATABASE is not set diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/Kconfig b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/Kconfig new file mode 100644 index 000000000..dc7cae3d4 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/Kconfig @@ -0,0 +1,61 @@ +mainmenu "XiZi_IIoT Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_CORTEX_V2M_EVB + bool + select ARCH_ARM + default y + + +source "$KERNEL_DIR/arch/Kconfig" + +menu "cortex-m7-emulator feature" + source "$BSP_DIR/third_party_driver/Kconfig" + + menu "config default board resources" + menu "config board app name" + config BOARD_APP_NAME + string "config board app name" + default "/XiUOS_cortex-m7-emulator_app.bin" + endmenu + + menu "config board service table" + config SERVICE_TABLE_ADDRESS + hex "board service table address" + default 0x20000000 + endmenu + + + endmenu + + config __STACKSIZE__ + int "stack size for interrupt" + default 4096 + + menu "config board peripheral" + config MOUNT_SDCARD + bool + default n + config MOUNT_USB + bool + default n + endmenu + + +endmenu + + +menu "Hardware feature" +source "$KERNEL_DIR/resources/Kconfig" +endmenu + +source "$KERNEL_DIR/Kconfig" diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/Makefile b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/Makefile new file mode 100644 index 000000000..683e42a90 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/Makefile @@ -0,0 +1,8 @@ +SRC_FILES := board.c + +SRC_DIR := third_party_driver + + + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.c b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.c new file mode 100644 index 000000000..72aac8356 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.c @@ -0,0 +1,205 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.c +* @brief support cortex-m7-emulator-board init configure and start-up +* @version 1.0 +* @author fudan +* @date 2021-08-26 +*/ + +/************************************************* +File name: board.c +Description: support cortex-m7-emulator-board init configure and driver/task/... init +Others: +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +Modification: +1. support cortex-m7-emulator-board InitBoardHardware +*************************************************/ + + +#include "board.h" +#include "clock_config.h" +#include + + +#ifdef BSP_USING_LPUART +#include +#endif + +#ifdef BSP_USING_GPIO +#include +#endif + + + + + +extern uint32_t SystemCoreClock; +/* MPU configuration. */ +void BOARD_ConfigMPU(void) +{ + + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* MPU configure: + * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, + * SubRegionDisable, Size) + * API in mpu_armv7.h. + * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches + * disabled. + * param AccessPermission Data access permissions, allows you to configure read/write access for User and + * Privileged mode. + * Use MACROS defined in mpu_armv7.h: + * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO + * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. + * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache + * 0 x 0 0 Strongly Ordered shareable + * 0 x 0 1 Device shareable + * 0 0 1 0 Normal not shareable Outer and inner write + * through no write allocate + * 0 0 1 1 Normal not shareable Outer and inner write + * back no write allocate + * 0 1 1 0 Normal shareable Outer and inner write + * through no write allocate + * 0 1 1 1 Normal shareable Outer and inner write + * back no write allocate + * 1 0 0 0 Normal not shareable outer and inner + * noncache + * 1 1 0 0 Normal shareable outer and inner + * noncache + * 1 0 1 1 Normal not shareable outer and inner write + * back write/read acllocate + * 1 1 1 1 Normal shareable outer and inner write + * back write/read acllocate + * 2 x 0 0 Device not shareable + * Above are normal use settings, if your want to see more details or want to config different inner/outter cache + * policy. + * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide + * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. + * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in + * mpu_armv7.h. + */ + + // /* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */ + // MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U); + // MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(0, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_256MB); + +/* Region 2 setting */ +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) + /* Setting Memory with Normal type, not shareable, outer/inner write back. */ + MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB); +#else + /* Setting Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_64MB); +#endif + + /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(2, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(4, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(5, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + +/* The define sets the cacheable memory to shareable, + * this suggestion is referred from chapter 2.2.1 Memory regions, + * types and attributes in Cortex-M7 Devices, Generic User Guide */ +#if defined(SDRAM_IS_SHAREABLE) + /* Region 7 setting: Memory with Normal type, shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); +#else + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x21000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_2MB); +#endif + + /* Region 8 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be + * accessed by cache can be put here */ + /* Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x21200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable I cache and D cache */ + SCB_EnableDCache(); + SCB_EnableICache(); +} + +/* This is the timer interrupt service routine. */ +void SysTick_Handler(int irqn, void *arg) +{ + TickAndTaskTimesliceUpdate(); +} + + + +void InitBoardHardware() +{ + int i = 0; + int ret = 0; + + BOARD_ConfigMPU(); + // BOARD_InitPins(); + BOARD_BootClockRUN(); + + NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + SysTick_Config(SystemCoreClock / TICK_PER_SECOND); + + InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END); + + +#ifdef BSP_USING_LPUART + Imxrt1052HwUartInit(); + + +#endif + + InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME); + KPrintf("0"); + KPrintf("\nconsole init completed.\n"); + KPrintf("board initialization......\n"); + + // for(i = 0; _board_init[i].fn != NONE; i++) { + // ret = _board_init[i].fn(); + // KPrintf("initialize %s %s\n",_board_init[i].fn_name, ret == 0 ? "success" : "failed"); + // } + KPrintf("board init done.\n"); + KPrintf("start kernel...\n"); + +#ifdef TOOL_USING_OTA + //跳转成功设置lastjumpflag为JUMP_SUCCESS_FLAG + app_clear_jumpflag(); +#endif +} diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.h new file mode 100644 index 000000000..2b4d50398 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.h @@ -0,0 +1,64 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file board.h +* @brief define imxrt1052-board init configure and start-up function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-28 +*/ + +/************************************************* +File name: board.h +Description: define imxrt1052-board board init function and struct +Others: +History: +1. Date: 2021-05-28 +Author: AIIT XUOS Lab +Modification: +1. define imxrt-board InitBoardHardware +2. define imxrt-board heap struct +*************************************************/ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#define M7_EMULATOR + +#include + +#include +#include +#include "fsl_common.h" +#include "xsconfig.h" + +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority*/ + + + + +extern int heap_start; +extern int heap_end; +#define HEAP_BEGIN (&heap_start) +#define HEAP_END (&heap_end) + +#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN) + +void InitBoardHardware(void); + + + +#endif /* _BOARD_H_ */ diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/config.mk b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/config.mk new file mode 100644 index 000000000..bad2cfaad --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/config.mk @@ -0,0 +1,15 @@ +export CROSS_COMPILE ?=/usr/bin/arm-none-eabi- + +export CFLAGS := -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb -Werror +export AFLAGS := -c -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2 +export LFLAGS := -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi-cortex-m7-emulator.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds +export CXXFLAGS := -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -Werror + + +export APPLFLAGS := -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiZi-app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds + + +export DEFINES := -DHAVE_CCONFIG_H -DCPU_MIMXRT1052CVL5B + +export ARCH = arm +export MCU = cortex-m7 \ No newline at end of file diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link.lds b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link.lds new file mode 100644 index 000000000..b71abc9fd --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link.lds @@ -0,0 +1,252 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 1.0, 2018-09-21 +** Build: b180921 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/** +* @file link.lds +* @brief xidatong-arm32 Linker script +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-28 +*/ + +/************************************************* +File name: link.lds +Description: xidatong-arm32 Linker script +Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references +History: +1. Date: 2021-05-28 +Author: AIIT XUOS Lab +Modification: +1. add shell cmd table and g_service_table +*************************************************/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +STACK_SIZE = 0x400; + +/* Specify the memory areas */ +MEMORY +{ + + + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x000FDC00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00060000 + + m_sdram (RW) : ORIGIN = 0x21000000, LENGTH = 0x00200000 + m_nocache (RW) : ORIGIN = 0x21200000, LENGTH = 0x00200000 +} + +/* Define output sections */ +SECTIONS +{ + + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + + /* section information for shell */ + . = ALIGN(4); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(4); + + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(4); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_nocache + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_nocache + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .stack : + { + . = ALIGN(8); + stack_start = .; + . += STACK_SIZE; + stack_end = .; + __StackTop = .; + heap_start = .; + } > m_data2 + + PROVIDE(heap_end = ORIGIN(m_data2) + LENGTH(m_data2)); + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link_m7.lds b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link_m7.lds new file mode 100644 index 000000000..b71abc9fd --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link_m7.lds @@ -0,0 +1,252 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 1.0, 2018-09-21 +** Build: b180921 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/** +* @file link.lds +* @brief xidatong-arm32 Linker script +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-28 +*/ + +/************************************************* +File name: link.lds +Description: xidatong-arm32 Linker script +Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references +History: +1. Date: 2021-05-28 +Author: AIIT XUOS Lab +Modification: +1. add shell cmd table and g_service_table +*************************************************/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +STACK_SIZE = 0x400; + +/* Specify the memory areas */ +MEMORY +{ + + + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x000FDC00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00060000 + + m_sdram (RW) : ORIGIN = 0x21000000, LENGTH = 0x00200000 + m_nocache (RW) : ORIGIN = 0x21200000, LENGTH = 0x00200000 +} + +/* Define output sections */ +SECTIONS +{ + + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + + /* section information for shell */ + . = ALIGN(4); + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(4); + + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(4); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_nocache + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_nocache + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .stack : + { + . = ALIGN(8); + stack_start = .; + . += STACK_SIZE; + stack_end = .; + __StackTop = .; + heap_start = .; + } > m_data2 + + PROVIDE(heap_end = ORIGIN(m_data2) + LENGTH(m_data2)); + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/cmsis_compiler.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 000000000..94212eb87 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/cmsis_gcc.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 000000000..5d0f07e8a --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2088 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.3 + * @date 16. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/cmsis_version.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/cmsis_version.h new file mode 100644 index 000000000..660f612aa --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/core_cm7.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/core_cm7.h new file mode 100644 index 000000000..1fe53bf01 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/core_cm7.h @@ -0,0 +1,2660 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + register uint32_t ccsidr; + register uint32_t sets; + register uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/mpu_armv7.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/mpu_armv7.h new file mode 100644 index 000000000..aa180c9e5 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,197 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) + +#define ARM_MPU_AP_NONE 0U +#define ARM_MPU_AP_PRIV 1U +#define ARM_MPU_AP_URO 2U +#define ARM_MPU_AP_FULL 3U +#define ARM_MPU_AP_PRO 5U +#define ARM_MPU_AP_RO 6U + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (MPU_RASR_ENABLE_Msk)) + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/LICENSE.txt b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/LICENSE.txt new file mode 100644 index 000000000..8dada3eda --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/Kconfig b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/Kconfig new file mode 100644 index 000000000..f6f0e8caa --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/Kconfig @@ -0,0 +1,10 @@ +menuconfig BSP_USING_LPUART + bool "Using UART device" + default y + select RESOURCES_SERIAL + if BSP_USING_LPUART + source "$BSP_DIR/third_party_driver/uart/Kconfig" + endif + + + \ No newline at end of file diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/Makefile b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/Makefile new file mode 100644 index 000000000..bc1a58672 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/Makefile @@ -0,0 +1,3 @@ +SRC_DIR := common uart + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/Makefile b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/Makefile new file mode 100755 index 000000000..9426cf2cb --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/Makefile @@ -0,0 +1,5 @@ +SRC_FILES := fsl_common.c system_CMSDK_CM7.c startup_CMSDK_CM7.c clock_config.c + + + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/clock_config.c b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/clock_config.c new file mode 100755 index 000000000..592dca830 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/clock_config.c @@ -0,0 +1,70 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file clock_config.c +* @brief support imxrt1052-board clock configure +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-29 +*/ + +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v5.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 5.0.2 +board: IMXRT1050-EVKB + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + + +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/fsl_common.c b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/fsl_common.c new file mode 100755 index 000000000..77c3a9039 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/fsl_common.c @@ -0,0 +1,155 @@ +/* +* Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP +* All rights reserved. +* +* +* SPDX-License-Identifier: BSD-3-Clause +*/ + +/** + * @file fsl_common.c + * @brief common drivers + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2021.11.11 + */ + +#include "fsl_common.h" +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned address to real address */ +} mem_align_cb_t; + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + +#ifndef __GIC_PRIO_BITS +#if defined(ENABLE_RAM_VECTOR_TABLE) +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif + + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1u << intNumber; + EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1u << intNumber; +} +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t); + void *p_align_addr, *p_addr = malloc(alignedsize); + + if (!p_addr) + { + return NULL; + } + + p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4U); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr; + + return (void *)p_align_addr; +} + +void SDK_Free(void *ptr) +{ + mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4U); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + free((void *)((uint32_t)ptr - p_cb->offset)); +} diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/startup_CMSDK_CM7.c b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/startup_CMSDK_CM7.c new file mode 100644 index 000000000..640436693 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/startup_CMSDK_CM7.c @@ -0,0 +1,418 @@ +/****************************************************************************** + * @file startup_CMSDK_CM7.c + * @brief CMSIS Startup File for CMSDK_M7 Device + ******************************************************************************/ +/* Copyright (c) 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#include "CMSDK_CM7_SP.h" +#include "system_CMSDK_CM7.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __StackTop ; + +// extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +extern __NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* Interrupts */ +void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT +void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +// extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; +// const VECTOR_TABLE_Type __VECTOR_TABLE[256] = { +// (VECTOR_TABLE_Type)(&__StackTop), /* Initial Stack Pointer */ +// Reset_Handler, /* Reset Handler */ +// NMI_Handler, /* -14 NMI Handler */ +// HardFault_Handler, /* -13 Hard Fault Handler */ +// MemManage_Handler, /* -12 MPU Fault Handler */ +// BusFault_Handler, /* -11 Bus Fault Handler */ +// UsageFault_Handler, /* -10 Usage Fault Handler */ +// 0, /* Reserved */ +// 0, /* Reserved */ +// 0, /* Reserved */ +// 0, /* Reserved */ +// SVC_Handler, /* -5 SVC Handler */ +// DebugMon_Handler, /* -4 Debug Monitor Handler */ +// 0, /* Reserved */ +// PendSV_Handler, /* -2 PendSV Handler */ +// SysTick_Handler, /* -1 SysTick Handler */ + +// /* Interrupts */ +// UART0RX_Handler, /* 0 UART 0 receive interrupt */ +// UART0TX_Handler, /* 1 UART 0 transmit interrupt */ +// UART1RX_Handler, /* 2 UART 1 receive interrupt */ +// UART1TX_Handler, /* 3 UART 1 transmit interrupt */ +// UART2RX_Handler, /* 4 UART 2 receive interrupt */ +// UART2TX_Handler, /* 5 UART 2 transmit interrupt */ +// GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ +// GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ +// TIMER0_Handler, /* 8 Timer 0 interrupt */ +// TIMER1_Handler, /* 9 Timer 1 interrupt */ +// DUALTIMER_Handler, /* 10 Dual Timer interrupt */ +// SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ +// UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ +// ETHERNET_Handler, /* 13 Ethernet interrupt */ +// I2S_Handler, /* 14 Audio I2S interrupt */ +// TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ +// GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ +// GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ +// UART3RX_Handler, /* 18 UART 3 receive interrupt */ +// UART3TX_Handler, /* 19 UART 3 transmit interrupt */ +// UART4RX_Handler, /* 20 UART 4 receive interrupt */ +// UART4TX_Handler, /* 21 UART 4 transmit interrupt */ +// SPI_2_Handler, /* 22 SPI 2 interrupt */ +// SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ +// GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ +// GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ +// GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ +// GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ +// GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ +// GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ +// GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ +// GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ +// 0, /* 32 Reserved */ +// 0, /* 33 Reserved */ +// 0, /* 34 Reserved */ +// 0, /* 35 Reserved */ +// 0, /* 36 Reserved */ +// 0, /* 37 Reserved */ +// 0, /* 38 Reserved */ +// 0, /* 39 Reserved */ +// 0, /* 40 Reserved */ +// 0, /* 41 Reserved */ +// 0, /* 42 Reserved */ +// 0, /* 43 Reserved */ +// 0, /* 44 Reserved */ +// 0, /* 45 Reserved */ +// 0, /* 46 Reserved */ +// 0, /* 47 Reserved */ +// 0, /* 48 Reserved */ +// 0, /* 49 Reserved */ +// 0, /* 50 Reserved */ +// 0, /* 51 Reserved */ +// 0, /* 52 Reserved */ +// 0, /* 53 Reserved */ +// 0, /* 54 Reserved */ +// 0, /* 55 Reserved */ +// 0, /* 56 Reserved */ +// 0, /* 57 Reserved */ +// 0, /* 58 Reserved */ +// 0, /* 59 Reserved */ +// 0, /* 60 Reserved */ +// 0, /* 61 Reserved */ +// 0, /* 62 Reserved */ +// 0, /* 63 Reserved */ +// 0, /* 64 Reserved */ +// 0, /* 65 Reserved */ +// 0, /* 66 Reserved */ +// 0, /* 67 Reserved */ +// 0, /* 68 Reserved */ +// 0, /* 69 Reserved */ +// 0, /* 70 Reserved */ +// 0, /* 71 Reserved */ +// 0, /* 72 Reserved */ +// 0, /* 73 Reserved */ +// 0, /* 74 Reserved */ +// 0, /* 75 Reserved */ +// 0, /* 76 Reserved */ +// 0, /* 77 Reserved */ +// 0, /* 78 Reserved */ +// 0, /* 79 Reserved */ +// 0, /* 80 Reserved */ +// 0, /* 81 Reserved */ +// 0, /* 82 Reserved */ +// 0, /* 83 Reserved */ +// 0, /* 84 Reserved */ +// 0, /* 85 Reserved */ +// 0, /* 86 Reserved */ +// 0, /* 87 Reserved */ +// 0, /* 88 Reserved */ +// 0, /* 89 Reserved */ +// 0, /* 90 Reserved */ +// 0, /* 91 Reserved */ +// 0, /* 92 Reserved */ +// 0, /* 93 Reserved */ +// 0, /* 94 Reserved */ +// 0, /* 95 Reserved */ +// 0, /* 96 Reserved */ +// 0, /* 97 Reserved */ +// 0, /* 98 Reserved */ +// 0, /* 99 Reserved */ +// 0, /* 100 Reserved */ +// 0, /* 101 Reserved */ +// 0, /* 102 Reserved */ +// 0, /* 103 Reserved */ +// 0, /* 104 Reserved */ +// 0, /* 105 Reserved */ +// 0, /* 106 Reserved */ +// 0, /* 107 Reserved */ +// 0, /* 108 Reserved */ +// 0, /* 109 Reserved */ +// 0, /* 110 Reserved */ +// 0, /* 111 Reserved */ +// 0, /* 112 Reserved */ +// 0, /* 113 Reserved */ +// 0, /* 114 Reserved */ +// 0, /* 115 Reserved */ +// 0, /* 116 Reserved */ +// 0, /* 117 Reserved */ +// 0, /* 118 Reserved */ +// 0, /* 119 Reserved */ +// 0, /* 120 Reserved */ +// 0, /* 121 Reserved */ +// 0, /* 122 Reserved */ +// 0, /* 123 Reserved */ +// 0, /* 124 Reserved */ +// 0, /* 125 Reserved */ +// 0, /* 126 Reserved */ +// 0, /* 127 Reserved */ +// 0, /* 128 Reserved */ +// 0, /* 129 Reserved */ +// 0, /* 130 Reserved */ +// 0, /* 131 Reserved */ +// 0, /* 132 Reserved */ +// 0, /* 133 Reserved */ +// 0, /* 134 Reserved */ +// 0, /* 135 Reserved */ +// 0, /* 136 Reserved */ +// 0, /* 137 Reserved */ +// 0, /* 138 Reserved */ +// 0, /* 139 Reserved */ +// 0, /* 140 Reserved */ +// 0, /* 141 Reserved */ +// 0, /* 142 Reserved */ +// 0, /* 143 Reserved */ +// 0, /* 144 Reserved */ +// 0, /* 145 Reserved */ +// 0, /* 146 Reserved */ +// 0, /* 147 Reserved */ +// 0, /* 148 Reserved */ +// 0, /* 149 Reserved */ +// 0, /* 150 Reserved */ +// 0, /* 151 Reserved */ +// 0, /* 152 Reserved */ +// 0, /* 153 Reserved */ +// 0, /* 154 Reserved */ +// 0, /* 155 Reserved */ +// 0, /* 156 Reserved */ +// 0, /* 157 Reserved */ +// 0, /* 158 Reserved */ +// 0, /* 159 Reserved */ +// 0, /* 160 Reserved */ +// 0, /* 161 Reserved */ +// 0, /* 162 Reserved */ +// 0, /* 163 Reserved */ +// 0, /* 164 Reserved */ +// 0, /* 165 Reserved */ +// 0, /* 166 Reserved */ +// 0, /* 167 Reserved */ +// 0, /* 168 Reserved */ +// 0, /* 169 Reserved */ +// 0, /* 170 Reserved */ +// 0, /* 171 Reserved */ +// 0, /* 172 Reserved */ +// 0, /* 173 Reserved */ +// 0, /* 174 Reserved */ +// 0, /* 175 Reserved */ +// 0, /* 176 Reserved */ +// 0, /* 177 Reserved */ +// 0, /* 178 Reserved */ +// 0, /* 179 Reserved */ +// 0, /* 180 Reserved */ +// 0, /* 181 Reserved */ +// 0, /* 182 Reserved */ +// 0, /* 183 Reserved */ +// 0, /* 184 Reserved */ +// 0, /* 185 Reserved */ +// 0, /* 186 Reserved */ +// 0, /* 187 Reserved */ +// 0, /* 188 Reserved */ +// 0, /* 189 Reserved */ +// 0, /* 190 Reserved */ +// 0, /* 191 Reserved */ +// 0, /* 192 Reserved */ +// 0, /* 193 Reserved */ +// 0, /* 194 Reserved */ +// 0, /* 195 Reserved */ +// 0, /* 196 Reserved */ +// 0, /* 197 Reserved */ +// 0, /* 198 Reserved */ +// 0, /* 199 Reserved */ +// 0, /* 200 Reserved */ +// 0, /* 201 Reserved */ +// 0, /* 202 Reserved */ +// 0, /* 203 Reserved */ +// 0, /* 204 Reserved */ +// 0, /* 205 Reserved */ +// 0, /* 206 Reserved */ +// 0, /* 207 Reserved */ +// 0, /* 208 Reserved */ +// 0, /* 209 Reserved */ +// 0, /* 210 Reserved */ +// 0, /* 211 Reserved */ +// 0, /* 212 Reserved */ +// 0, /* 213 Reserved */ +// 0, /* 214 Reserved */ +// 0, /* 215 Reserved */ +// 0, /* 216 Reserved */ +// 0, /* 217 Reserved */ +// 0, /* 218 Reserved */ +// 0, /* 219 Reserved */ +// 0, /* 220 Reserved */ +// 0, /* 221 Reserved */ +// 0, /* 222 Reserved */ +// 0, /* 223 Reserved */ +// #if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT +// ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ +// ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ +// ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ +// ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ +// ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ +// ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ +// ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ +// ARM_VSI7_Handler /* 231 VSI 7 interrupt */ +// #else +// 0, /* 224 Reserved */ +// 0, /* 225 Reserved */ +// 0, /* 226 Reserved */ +// 0, /* 227 Reserved */ +// 0, /* 228 Reserved */ +// 0, /* 229 Reserved */ +// 0, /* 230 Reserved */ +// 0 /* 231 Reserved */ +// #endif +// }; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +// __NO_RETURN void Reset_Handler(void) +// { +// SystemInit(); +// } + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/system_CMSDK_CM7.c b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/system_CMSDK_CM7.c new file mode 100644 index 000000000..8314d29a5 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/common/system_CMSDK_CM7.c @@ -0,0 +1,79 @@ +/****************************************************************************** + * @file system_CMSDK_CM7.c + * @brief CMSIS System Source File for CMSDK_CM7 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#include "CMSDK_CM7_SP.h" +#include "system_CMSDK_CM7.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/CMSDK_CM7_SP.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/CMSDK_CM7_SP.h new file mode 100644 index 000000000..023a107e4 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/CMSDK_CM7_SP.h @@ -0,0 +1,616 @@ +/****************************************************************************** + * @file CMSDK_CM7_SP.h + * @brief CMSIS Device Header File for CMSDK_CM7 Device (single precision FPU) + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef CMSDK_CM7_SP_H +#define CMSDK_CM7_SP_H + + + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ + + +/* ------------------- Processor Exceptions Numbers ----------------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + +/* ------------------- Processor Interrupt Numbers ------------------------------ */ + UART0RX_IRQn = 0, /* UART 0 receive interrupt */ + UART0TX_IRQn = 1, /* UART 0 transmit interrupt */ + UART1RX_IRQn = 2, /* UART 1 receive interrupt */ + UART1TX_IRQn = 3, /* UART 1 transmit interrupt */ + UART2RX_IRQn = 4, /* UART 2 receive interrupt */ + UART2TX_IRQn = 5, /* UART 2 transmit interrupt */ + GPIO0ALL_IRQn = 6, /* GPIO 0 combined interrupt */ + GPIO1ALL_IRQn = 7, /* GPIO 1 combined interrupt */ + TIMER0_IRQn = 8, /* Timer 0 interrupt */ + TIMER1_IRQn = 9, /* Timer 1 interrupt */ + DUALTIMER_IRQn = 10, /* Dual Timer interrupt */ + SPI_0_1_IRQn = 11, /* SPI 0, SPI 1 interrupt */ + UART_0_1_2_OVF_IRQn = 12, /* UART overflow (0, 1 & 2) interrupt */ + ETHERNET_IRQn = 13, /* Ethernet interrupt */ + I2S_IRQn = 14, /* Audio I2S interrupt */ + TOUCHSCREEN_IRQn = 15, /* Touch Screen interrupt */ + GPIO2_IRQn = 16, /* GPIO 2 combined interrupt */ + GPIO3_IRQn = 17, /* GPIO 3 combined interrupt */ + UART3RX_IRQn = 18, /* UART 3 receive interrupt */ + UART3TX_IRQn = 19, /* UART 3 transmit interrupt */ + UART4RX_IRQn = 20, /* UART 4 receive interrupt */ + UART4TX_IRQn = 21, /* UART 4 transmit interrupt */ + SPI_2_IRQn = 22, /* SPI 2 interrupt */ + SPI_3_4_IRQn = 23, /* SPI 3, SPI 4 interrupt */ + GPIO0_0_IRQn = 24, /* GPIO 0 individual interrupt ( 0) */ + GPIO0_1_IRQn = 25, /* GPIO 0 individual interrupt ( 1) */ + GPIO0_2_IRQn = 26, /* GPIO 0 individual interrupt ( 2) */ + GPIO0_3_IRQn = 27, /* GPIO 0 individual interrupt ( 3) */ + GPIO0_4_IRQn = 28, /* GPIO 0 individual interrupt ( 4) */ + GPIO0_5_IRQn = 29, /* GPIO 0 individual interrupt ( 5) */ + GPIO0_6_IRQn = 30, /* GPIO 0 individual interrupt ( 6) */ + GPIO0_7_IRQn = 31, /* GPIO 0 individual interrupt ( 7) */ +#if defined CMSDK_CM7_SP_VHT + ARM_VSI0_IRQn = 224, /* VSI 0 interrupt */ + ARM_VSI1_IRQn = 225, /* VSI 1 interrupt */ + ARM_VSI2_IRQn = 226, /* VSI 2 interrupt */ + ARM_VSI3_IRQn = 227, /* VSI 3 interrupt */ + ARM_VSI4_IRQn = 228, /* VSI 4 interrupt */ + ARM_VSI5_IRQn = 229, /* VSI 5 interrupt */ + ARM_VSI6_IRQn = 230, /* VSI 6 interrupt */ + ARM_VSI7_IRQn = 231, /* VSI 7 interrupt */ +#endif +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of Core Peripherals ----------------------------------- */ +#define __CM4_REV 0x0000U /* Core revision r0p0 */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __FPU_DP 0U /* unused */ +#define __ICACHE_PRESENT 1U +#define __DCACHE_PRESENT 1U + +#include "core_cm7.h" /* Processor and core peripherals */ +#if defined CMSDK_CM7_SP_VHT +#include "arm_vio.h" +#include "arm_vsi.h" +#include "arm_vsocket.h" +#endif +// #include "system_CMSDK_CM7.h" /* System Header */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + __IOM uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */ + __IOM uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */ + __IOM uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */ + union { + __IM uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __OM uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + __IOM uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */ + +} CMSDK_UART_TypeDef; + +/* CMSDK_UART DATA Register Definitions */ +#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */ +#define CMSDK_UART_DATA_Msk (0xFFUL /*<< CMSDK_UART_DATA_Pos*/) /* CMSDK_UART DATA: DATA Mask */ + +/* CMSDK_UART STATE Register Definitions */ +#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */ +#define CMSDK_UART_STATE_RXOR_Msk (0x1UL << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */ + +#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */ +#define CMSDK_UART_STATE_TXOR_Msk (0x1UL << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */ + +#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */ +#define CMSDK_UART_STATE_RXBF_Msk (0x1UL << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */ + +#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */ +#define CMSDK_UART_STATE_TXBF_Msk (0x1UL /*<< CMSDK_UART_STATE_TXBF_Pos*/) /* CMSDK_UART STATE: TXBF Mask */ + +/* CMSDK_UART CTRL Register Definitions */ +#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */ +#define CMSDK_UART_CTRL_HSTM_Msk (0x01UL << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */ + +#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */ +#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */ +#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */ +#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */ + +#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */ +#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01UL << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */ + +#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */ +#define CMSDK_UART_CTRL_RXEN_Msk (0x01UL << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */ + +#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */ +#define CMSDK_UART_CTRL_TXEN_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXEN_Pos*/) /* CMSDK_UART CTRL: TXEN Mask */ + +#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */ +#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01UL << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */ + +#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */ +#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01UL << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */ + +#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */ +#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01UL << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */ + +#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */ +#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01UL /*<< CMSDK_UART_CTRL_TXIRQ_Pos*/) /* CMSDK_UART CTRL: TXIRQ Mask */ + +/* CMSDK_UART BAUDDIV Register Definitions */ +#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */ +#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFUL /*<< CMSDK_UART_BAUDDIV_Pos*/) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */ + + +/*----------------------------- Timer (TIMER) -------------------------------*/ +typedef struct +{ + __IOM uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */ + __IOM uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */ + union { + __IM uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */ + __OM uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */ + }; + +} CMSDK_TIMER_TypeDef; + +/* CMSDK_TIMER CTRL Register Definitions */ +#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */ +#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01UL << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */ +#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01UL << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */ +#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01UL << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */ + +#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */ +#define CMSDK_TIMER_CTRL_EN_Msk (0x01UL /*<< CMSDK_TIMER_CTRL_EN_Pos*/) /* CMSDK_TIMER CTRL: EN Mask */ + +/* CMSDK_TIMER VAL Register Definitions */ +#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */ +#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFUL /*<< CMSDK_TIMER_VAL_CURRENT_Pos*/) /* CMSDK_TIMER VALUE: CURRENT Mask */ + +/* CMSDK_TIMER RELOAD Register Definitions */ +#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */ +#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFUL /*<< CMSDK_TIMER_RELOAD_VAL_Pos*/) /* CMSDK_TIMER RELOAD: RELOAD Mask */ + +/* CMSDK_TIMER INTSTATUS Register Definitions */ +#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ +#define CMSDK_TIMER_INTSTATUS_Msk (0x01UL /*<< CMSDK_TIMER_INTSTATUS_Pos*/) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */ + +/* CMSDK_TIMER INTCLEAR Register Definitions */ +#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */ +#define CMSDK_TIMER_INTCLEAR_Msk (0x01UL /*<< CMSDK_TIMER_INTCLEAR_Pos*/) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ + + +/*------------- Timer (TIM) --------------------------------------------------*/ +typedef struct +{ + __IOM uint32_t T1LOAD; /* Offset: 0x000 (R/W) Timer 1 Load */ + __IM uint32_t T1VALUE; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ + __IOM uint32_t T1CTRL; /* Offset: 0x008 (R/W) Timer 1 Control */ + __OM uint32_t T1INTCLR; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ + __IM uint32_t T1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ + __IM uint32_t T1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ + __IOM uint32_t T1BGLOAD; /* Offset: 0x018 (R/W) Background Load Register */ + uint32_t RESERVED0; + __IOM uint32_t T2LOAD; /* Offset: 0x020 (R/W) Timer 2 Load */ + __IM uint32_t T2VALUE; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ + __IOM uint32_t T2CTRL; /* Offset: 0x028 (R/W) Timer 2 Control */ + __OM uint32_t T2INTCLR; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ + __IM uint32_t T2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ + __IM uint32_t T2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ + __IOM uint32_t T2BGLOAD; /* Offset: 0x038 (R/W) Background Load Register */ + uint32_t RESERVED1[945]; + __IOM uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */ + __OM uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */ +} CMSDK_DUALTIMER_BOTH_TypeDef; + + +typedef struct +{ + __IOM uint32_t LOAD; /* Offset: 0x000 (R/W) Timer Load */ + __IM uint32_t VALUE; /* Offset: 0x000 (R/W) Timer Counter Current Value */ + __IOM uint32_t CTRL; /* Offset: 0x000 (R/W) Timer Control */ + __OM uint32_t INTCLR; /* Offset: 0x000 (R/W) Timer Interrupt Clear */ + __IM uint32_t RIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */ + __IM uint32_t MIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */ + __IOM uint32_t BGLOAD; /* Offset: 0x000 (R/W) Background Load Register */ +} CMSDK_DUALTIMER_SINGLE_TypeDef; + +/* CMSDK_DUALTIMER_SINGLE LOAD Register Definitions */ +#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */ +#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_LOAD_Pos*/) /* CMSDK_DUALTIMER LOAD: LOAD Mask */ + +/* CMSDK_DUALTIMER_SINGLE VALUE Register Definitions */ +#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */ +#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_VALUE_Pos*/) /* CMSDK_DUALTIMER VALUE: VALUE Mask */ + +/* CMSDK_DUALTIMER_SINGLE CTRL Register Definitions */ +#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3UL << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1UL << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */ +#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1UL /*<< CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos*/) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */ + +/* CMSDK_DUALTIMER_SINGLE INTCLR Register Definitions */ +#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER_INTCLR_Msk (0x1UL /*<< CMSDK_DUALTIMER_INTCLR_Pos*/) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */ + +/* CMSDK_DUALTIMER_SINGLE RIS Register Definitions */ +#define CMSDK_DUALTIMER_RIS_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER_RIS_Msk (0x1UL /*<< CMSDK_DUALTIMER_RAWINTSTAT_Pos*/) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ + +/* CMSDK_DUALTIMER_SINGLE MIS Register Definitions */ +#define CMSDK_DUALTIMER_MIS_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER_MIS_Msk (0x1UL /*<< CMSDK_DUALTIMER_MASKINTSTAT_Pos*/) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ + +/* CMSDK_DUALTIMER_SINGLE BGLOAD Register Definitions */ +#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFUL /*<< CMSDK_DUALTIMER_BGLOAD_Pos*/) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */ + + +/*-------------------- General Purpose Input Output (GPIO) -------------------*/ +typedef struct +{ + __IOM uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */ + __IOM uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */ + uint32_t RESERVED0[2]; + __IOM uint32_t OUTENSET; /* Offset: 0x010 (R/W) Output Enable Set Register */ + __IOM uint32_t OUTENCLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */ + __IOM uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */ + __IOM uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */ + __IOM uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */ + __IOM uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */ + __IOM uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */ + __IOM uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */ + __IOM uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */ + __IOM uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */ + union { + __IM uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */ + __OM uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */ + }; + uint32_t RESERVED1[241]; + __IOM uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */ + __IOM uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */ +} CMSDK_GPIO_TypeDef; + +/* CMSDK_GPIO DATA Register Definitions */ +#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */ +#define CMSDK_GPIO_DATA_Msk (0xFFFFUL /*<< CMSDK_GPIO_DATA_Pos*/) /* CMSDK_GPIO DATA: DATA Mask */ + +/* CMSDK_GPIO DATAOUT Register Definitions */ +#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */ +#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFUL /*<< CMSDK_GPIO_DATAOUT_Pos*/) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */ + +/* CMSDK_GPIO OUTENSET Register Definitions */ +#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_OUTEN_Pos*/) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +/* CMSDK_GPIO OUTENCLR Register Definitions */ +#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */ +#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_OUTEN_Pos*/) /* CMSDK_GPIO OUTEN: OUTEN Mask */ + +/* CMSDK_GPIO ALTFUNCSET Register Definitions */ +#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_ALTFUNC_Pos*/) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +/* CMSDK_GPIO ALTFUNCCLR Register Definitions */ +#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */ +#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_ALTFUNC_Pos*/) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */ + +/* CMSDK_GPIO INTENSET Register Definitions */ +#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTEN_Pos*/) /* CMSDK_GPIO INTEN: INTEN Mask */ + +/* CMSDK_GPIO INTENCLR Register Definitions */ +#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */ +#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTEN_Pos*/) /* CMSDK_GPIO INTEN: INTEN Mask */ + +/* CMSDK_GPIO INTTYPESET Register Definitions */ +#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTTYPE_Pos*/) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +/* CMSDK_GPIO INTTYPECLR Register Definitions */ +#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */ +#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTTYPE_Pos*/) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */ + +/* CMSDK_GPIO INTPOLSET Register Definitions */ +#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTPOL_Pos*/) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +/* CMSDK_GPIO INTPOLCLR Register Definitions */ +#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */ +#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFUL /*<< CMSDK_GPIO_INTPOL_Pos*/) /* CMSDK_GPIO INTPOL: INTPOL Mask */ + +/* CMSDK_GPIO INTCLEAR Register Definitions */ +#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */ +#define CMSDK_GPIO_INTCLEAR_Msk (0xFFUL /*<< CMSDK_GPIO_INTSTATUS_Pos*/) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */ + +/* CMSDK_GPIO INTCLEAR Register Definitions */ +#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */ +#define CMSDK_GPIO_INTCLEAR_Msk (0xFFUL /*<< CMSDK_GPIO_INTCLEAR_Pos*/) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */ + +/* CMSDK_GPIO MASKLOWBYTE Register Definitions */ +#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */ +#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFUL /*<< CMSDK_GPIO_MASKLOWBYTE_Pos*/) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */ + +/* CMSDK_GPIO MASKHIGHBYTE Register Definitions */ +#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */ +#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00UL /*<< CMSDK_GPIO_MASKHIGHBYTE_Pos*/) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */ + + +/*------------- System Control (SYSCON) --------------------------------------*/ +typedef struct +{ + __IOM uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */ + __IOM uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */ + __IOM uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */ + __IOM uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */ + __IOM uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */ +} CMSDK_SYSCON_TypeDef; + +/* CMSDK_SYSCON REMAP Register Definitions */ +#define CMSDK_SYSCON_REMAP_Pos 0 +#define CMSDK_SYSCON_REMAP_Msk (0x1UL /*<< CMSDK_SYSCON_REMAP_Pos*/) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */ + +/* CMSDK_SYSCON PMUCTRL Register Definitions */ +#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0 +#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x1UL /*<< CMSDK_SYSCON_PMUCTRL_EN_Pos*/) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */ + +/* CMSDK_SYSCON LOCKUPRST Register Definitions */ +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0 +#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x1UL /*<< CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos*/) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */ + +/* CMSDK_SYSCON EMICTRL Register Definitions */ +#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24 +#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x1UL << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */ + +#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16 +#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x7UL << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8 +#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x3UL << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */ + +#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0 +#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x7UL /*<< CMSDK_SYSCON_EMICTRL_RCYC_Pos*/) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */ + +/* CMSDK_SYSCON RSTINFO Register Definitions */ +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2 +#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x1UL << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */ + +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1 +#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x1UL << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */ + +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0 +#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x1UL /*<< CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos*/) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */ + + +/*------------------- Watchdog ----------------------------------------------*/ +typedef struct +{ + + __IOM uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ + __IM uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ + __IOM uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ + __OM uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ + __IM uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ + __IM uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ + uint32_t RESERVED0[762]; + __IOM uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ + uint32_t RESERVED1[191]; + __IOM uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ + __OM uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ +}CMSDK_WATCHDOG_TypeDef; + +/* CMSDK_WATCHDOG LOAD Register Definitions */ +#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */ +#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFUL /*<< CMSDK_Watchdog_LOAD_Pos*/) /* CMSDK_Watchdog LOAD: LOAD Mask */ + +/* CMSDK_WATCHDOG VALUE Register Definitions */ +#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */ +#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFUL /*<< CMSDK_Watchdog_VALUE_Pos*/) /* CMSDK_Watchdog VALUE: VALUE Mask */ + +/* CMSDK_WATCHDOG CTRL Register Definitions */ +#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */ +#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1UL << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */ + +#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */ +#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1UL /*<< CMSDK_Watchdog_CTRL_INTEN_Pos*/) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */ + +/* CMSDK_WATCHDOG INTCLR Register Definitions */ +#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */ +#define CMSDK_Watchdog_INTCLR_Msk (0x1UL /*<< CMSDK_Watchdog_INTCLR_Pos*/) /* CMSDK_Watchdog INTCLR: Int Clear Mask */ + +/* CMSDK_WATCHDOG RAWINTSTAT Register Definitions */ +#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1UL /*<< CMSDK_Watchdog_RAWINTSTAT_Pos*/) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */ + +/* CMSDK_WATCHDOG MASKINTSTAT Register Definitions */ +#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1UL /*<< CMSDK_Watchdog_MASKINTSTAT_Pos*/) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */ + +/* CMSDK_WATCHDOG LOCK Register Definitions */ +#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */ +#define CMSDK_Watchdog_LOCK_Msk (0x1UL /*<< CMSDK_Watchdog_LOCK_Pos*/) /* CMSDK_Watchdog LOCK: LOCK Mask */ + +/* CMSDK_WATCHDOG INTEGTESTEN Register Definitions */ +#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */ +#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1UL /*<< CMSDK_Watchdog_INTEGTESTEN_Pos*/) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */ + +/* CMSDK_WATCHDOG INTEGTESTOUTSET Register Definitions */ +#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */ +#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1UL /*<< CMSDK_Watchdog_INTEGTESTOUTSET_Pos*/) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */ + + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +/* Peripheral and SRAM base address */ +#define CMSDK_FLASH_BASE (0x00000000UL) +#define CMSDK_SRAM_BASE (0x20000000UL) +#define CMSDK_PERIPH_BASE (0x40000000UL) + +#define CMSDK_RAM_BASE (0x20000000UL) +#define CMSDK_APB_BASE (0x40000000UL) +#define CMSDK_AHB_BASE (0x40010000UL) + +/* APB peripherals */ +#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL) +#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL) +#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL) +#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) +#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) +#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) +#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) +#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL) +#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) + +/* AHB peripherals */ +#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL) +#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL) +#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL) + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) +#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) +#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE ) +#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) +#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) +#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE ) +#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE ) +#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE ) +#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE ) +#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE ) +#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE ) +#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE ) + + +#ifdef __cplusplus +} +#endif + +#endif /* CMSDK_CM7_SP_H */ diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/Device.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/Device.h new file mode 100644 index 000000000..9fcad0718 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/Device.h @@ -0,0 +1,40 @@ +/*----------------------------------------------------------------------------- + * Name: Device.h + * Purpose: Include the correct device header file + *----------------------------------------------------------------------------*/ + +/* Copyright (c) 2011 - 2021 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef __DEVICE_H +#define __DEVICE_H + + +#include "CMSDK_CM7_SP.h" /* device specific header file */ + + +#endif /* __DEVICE_H */ diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/Driver_Common.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/Driver_Common.h new file mode 100644 index 000000000..59d5b759c --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/Driver_Common.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 2. Feb 2017 + * $Revision: V2.0 + * + * Project: Common Driver definitions + */ + +/* History: + * Version 2.0 + * Changed prefix ARM_DRV -> ARM_DRIVER + * Added General return codes definitions + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef DRIVER_COMMON_H_ +#define DRIVER_COMMON_H_ + +#include +#include +#include + +#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor)) + +/** +\brief Driver Version +*/ +typedef struct _ARM_DRIVER_VERSION { + uint16_t api; ///< API version + uint16_t drv; ///< Driver version +} ARM_DRIVER_VERSION; + +/* General return codes */ +#define ARM_DRIVER_OK 0 ///< Operation succeeded +#define ARM_DRIVER_ERROR -1 ///< Unspecified error +#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy +#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred +#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported +#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error +#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors + +/** +\brief General power states +*/ +typedef enum _ARM_POWER_STATE { + ARM_POWER_OFF, ///< Power off: no operation possible + ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events + ARM_POWER_FULL ///< Power on: full operation at maximum performance +} ARM_POWER_STATE; + +#endif /* DRIVER_COMMON_H_ */ diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/Driver_USART.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/Driver_USART.h new file mode 100644 index 000000000..e60bf51a3 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/Driver_USART.h @@ -0,0 +1,341 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 2. Feb 2017 + * $Revision: V2.3 + * + * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter) + * Driver definitions + */ + +/* History: + * Version 2.3 + * ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile + * Version 2.2 + * Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions + * Version 2.1 + * Removed optional argument parameter from Signal Event + * Version 2.0 + * New simplified driver: + * complexity moved to upper layer (especially data handling) + * more unified API for different communication interfaces + * renamed driver UART -> USART (Asynchronous & Synchronous) + * Added modes: + * Synchronous + * Single-wire + * IrDA + * Smart Card + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.01 + * Added events: + * ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT + * ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD + * Added functions: SetTxThreshold, SetRxThreshold + * Added "rx_timeout_event" to capabilities + * Version 1.00 + * Initial release + */ + +#ifndef DRIVER_USART_H_ +#define DRIVER_USART_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "Driver_Common.h" + +#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */ + + +/****** USART Control Codes *****/ + +#define ARM_USART_CONTROL_Pos 0 +#define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos) + +/*----- USART Control Codes: Mode -----*/ +#define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate +#define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate +#define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal) +#define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate +#define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate +#define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate + +/*----- USART Control Codes: Mode Parameters: Data Bits -----*/ +#define ARM_USART_DATA_BITS_Pos 8 +#define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos) +#define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits +#define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit +#define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits +#define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default) +#define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits + +/*----- USART Control Codes: Mode Parameters: Parity -----*/ +#define ARM_USART_PARITY_Pos 12 +#define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos) +#define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default) +#define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity +#define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity + +/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/ +#define ARM_USART_STOP_BITS_Pos 14 +#define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos) +#define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default) +#define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits +#define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits +#define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits + +/*----- USART Control Codes: Mode Parameters: Flow Control -----*/ +#define ARM_USART_FLOW_CONTROL_Pos 16 +#define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos) +#define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default) +#define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control +#define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control +#define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control + +/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/ +#define ARM_USART_CPOL_Pos 18 +#define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos) +#define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default) +#define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1 + +/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/ +#define ARM_USART_CPHA_Pos 19 +#define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos) +#define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default) +#define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1 + + +/*----- USART Control Codes: Miscellaneous Controls -----*/ +#define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value +#define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period +#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods +#define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated +#define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled +#define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send +#define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive +#define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer + + + +/****** USART specific error codes *****/ +#define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported +#define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported +#define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported +#define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported +#define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported +#define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported +#define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported +#define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported + + +/** +\brief USART Status +*/ +typedef volatile struct _ARM_USART_STATUS { + uint32_t tx_busy : 1; ///< Transmitter busy flag + uint32_t rx_busy : 1; ///< Receiver busy flag + uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation) + uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) + uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation) + uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation) + uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation) + uint32_t reserved : 25; +} ARM_USART_STATUS; + +/** +\brief USART Modem Control +*/ +typedef enum _ARM_USART_MODEM_CONTROL { + ARM_USART_RTS_CLEAR, ///< Deactivate RTS + ARM_USART_RTS_SET, ///< Activate RTS + ARM_USART_DTR_CLEAR, ///< Deactivate DTR + ARM_USART_DTR_SET ///< Activate DTR +} ARM_USART_MODEM_CONTROL; + +/** +\brief USART Modem Status +*/ +typedef volatile struct _ARM_USART_MODEM_STATUS { + uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive + uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive + uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive + uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive + uint32_t reserved : 28; +} ARM_USART_MODEM_STATUS; + + +/****** USART Event *****/ +#define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data +#define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed +#define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed +#define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional) +#define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave) +#define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow +#define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional) +#define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive +#define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive +#define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive +#define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional) +#define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional) +#define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional) +#define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional) + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void) + \brief Get driver capabilities + \return \ref ARM_USART_CAPABILITIES + + \fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event) + \brief Initialize USART Interface. + \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent + \return \ref execution_status + + \fn int32_t ARM_USART_Uninitialize (void) + \brief De-initialize USART Interface. + \return \ref execution_status + + \fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state) + \brief Control USART Interface Power. + \param[in] state Power state + \return \ref execution_status + + \fn int32_t ARM_USART_Send (const void *data, uint32_t num) + \brief Start sending data to USART transmitter. + \param[in] data Pointer to buffer with data to send to USART transmitter + \param[in] num Number of data items to send + \return \ref execution_status + + \fn int32_t ARM_USART_Receive (void *data, uint32_t num) + \brief Start receiving data from USART receiver. + \param[out] data Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to receive + \return \ref execution_status + + \fn int32_t ARM_USART_Transfer (const void *data_out, + void *data_in, + uint32_t num) + \brief Start sending/receiving data to/from USART transmitter/receiver. + \param[in] data_out Pointer to buffer with data to send to USART transmitter + \param[out] data_in Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to transfer + \return \ref execution_status + + \fn uint32_t ARM_USART_GetTxCount (void) + \brief Get transmitted data count. + \return number of data items transmitted + + \fn uint32_t ARM_USART_GetRxCount (void) + \brief Get received data count. + \return number of data items received + + \fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg) + \brief Control USART Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return common \ref execution_status and driver specific \ref usart_execution_status + + \fn ARM_USART_STATUS ARM_USART_GetStatus (void) + \brief Get USART status. + \return USART status \ref ARM_USART_STATUS + + \fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control) + \brief Set USART Modem Control line state. + \param[in] control \ref ARM_USART_MODEM_CONTROL + \return \ref execution_status + + \fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void) + \brief Get USART Modem Status lines state. + \return modem status \ref ARM_USART_MODEM_STATUS + + \fn void ARM_USART_SignalEvent (uint32_t event) + \brief Signal USART Events. + \param[in] event \ref USART_events notification mask + \return none +*/ + +typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event. + + +/** +\brief USART Device Driver Capabilities. +*/ +typedef struct _ARM_USART_CAPABILITIES { + uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode + uint32_t synchronous_master : 1; ///< supports Synchronous Master mode + uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode + uint32_t single_wire : 1; ///< supports UART Single-wire mode + uint32_t irda : 1; ///< supports UART IrDA mode + uint32_t smart_card : 1; ///< supports UART Smart Card mode + uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available + uint32_t flow_control_rts : 1; ///< RTS Flow Control available + uint32_t flow_control_cts : 1; ///< CTS Flow Control available + uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE + uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT + uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available + uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available + uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available + uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available + uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available + uint32_t ri : 1; ///< RI Line: 0=not available, 1=available + uint32_t event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS + uint32_t event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR + uint32_t event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD + uint32_t event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI + uint32_t reserved : 11; ///< Reserved (must be zero) +} ARM_USART_CAPABILITIES; + + +/** +\brief Access structure of the USART Driver. +*/ +typedef struct _ARM_DRIVER_USART { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version. + ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power. + int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter. + int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver. + int32_t (*Transfer) (const void *data_out, + void *data_in, + uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART. + uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count. + uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count. + int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface. + ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status. + int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state. + ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state. +} const ARM_DRIVER_USART; + +#ifdef __cplusplus +} +#endif + +#endif /* DRIVER_USART_H_ */ diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/RTE_Components.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/RTE_Components.h new file mode 100644 index 000000000..8919484c7 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/RTE_Components.h @@ -0,0 +1,26 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'Blinky' + * Target: 'FastModels' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "CMSDK_CM7_SP.h" + +/* Keil.ARM Compiler::Compiler:I/O:STDOUT:User:1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ +/* Keil::CMSIS Driver:USART:1.0.3 */ +#define RTE_Drivers_USART + + +#endif /* RTE_COMPONENTS_H */ diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/RTE_Device.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/RTE_Device.h new file mode 100644 index 000000000..7584efda3 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/RTE_Device.h @@ -0,0 +1,50 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 25. April 2016 + * $Revision: V1.0.0 + * + * Project: RTE Device Configuration for ARM CMSDK_CM device + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_USART0 1 + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_UART2 0 + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_UART3 0 + +#endif /* __RTE_DEVICE_H */ diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/USART_V2M-MPS2.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/USART_V2M-MPS2.h new file mode 100644 index 000000000..022414ac9 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/USART_V2M-MPS2.h @@ -0,0 +1,99 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2016 -2017 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 16. February 2017 + * $Revision: V1.0.2 + * + * Project: UART Driver Definitions for ARM CMSDK_CM device + * -------------------------------------------------------------------------- */ + +#ifndef USART_V2M_MPS2_H_ +#define USART_V2M_MPS2_H_ + + +#include +#include +#include "Driver_USART.h" +#include "Device.h" +#include "RTE_Device.h" +#include "RTE_Components.h" + +#if (defined(RTE_Drivers_USART) \ + && (RTE_USART0 == 0) \ + && (RTE_USART1 == 0) \ + && (RTE_USART2 == 0) \ + && (RTE_USART3 == 0)) + #error "USART not configured in RTE_Device.h!" +#endif + +// USART Flags +#define USART_FLAG_INITIALIZED ((uint8_t)(1U)) +#define USART_FLAG_POWERED ((uint8_t)(1U << 1)) +#define USART_FLAG_CONFIGURED ((uint8_t)(1U << 2)) +#define USART_FLAG_TX_ENABLED ((uint8_t)(1U << 3)) +#define USART_FLAG_RX_ENABLED ((uint8_t)(1U << 4)) + +typedef struct _PIN +{ + CMSDK_GPIO_TypeDef *PinGpio; // Pin GPIO + uint8_t PinNum; // Pin Number +} PIN; + +// USART Pin Configuration +typedef const struct _USART_PINS { + PIN *pin_rx; // RX Pin identifier + PIN *pin_tx; // TX Pin identifier +} USART_PINS; + +// USART Transfer Information (Run-Time) +typedef struct _USART_TRANSFER_INFO { + uint32_t rx_num; // Total number of receive data + uint32_t tx_num; // Total number of transmit data + uint8_t *rx_buf; // Pointer to in data buffer + const uint8_t *tx_buf; // Pointer to out data buffer + uint32_t rx_cnt; // Number of data received + uint32_t tx_cnt; // Number of data sent +} USART_TRANSFER_INFO; + +typedef struct _USART_STATUS { + uint8_t tx_busy; // Transmitter busy flag + uint8_t rx_busy; // Receiver busy flag + uint8_t rx_overflow; // Receive data overflow detected (cleared on start of next receive operation) +} USART_STATUS; + +// USART Information (Run-Time) +typedef struct _USART_INFO { + ARM_USART_SignalEvent_t cb_event; // Event callback + USART_STATUS status; // Status flags + uint8_t flags; // Current USART flags +} USART_INFO; + +// USART Resources Definitions +typedef const struct { + ARM_USART_CAPABILITIES capabilities; // Capabilities + USART_PINS pins; // USART pins configuration + CMSDK_UART_TypeDef *reg; // USART peripheral pointer + IRQn_Type irq_num_rx; // USART RX IRQ Number + IRQn_Type irq_num_tx; // USART TX IRQ Number + USART_INFO *info; // Run-Time Information + USART_TRANSFER_INFO *xfer; // USART transfer information +} USART_RESOURCES; + +#endif /* USART_V2M_MPS2_H_ */ diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/system_CMSDK_CM7.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/system_CMSDK_CM7.h new file mode 100644 index 000000000..ca3394162 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/system_CMSDK_CM7.h @@ -0,0 +1,68 @@ +/****************************************************************************** + * @file system_CMSDK_CM7.h + * @brief CMSIS System Header File for CMSDK_CM7 Device + ******************************************************************************/ +/* Copyright (c) 2011 - 2022 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef SYSTEM_CMSDK_CM7_H +#define SYSTEM_CMSDK_CM7_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); + + +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_CMSDK_CM7_H */ diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/clock_config.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/clock_config.h new file mode 100755 index 000000000..b71b63220 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/clock_config.h @@ -0,0 +1,76 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file clock_config.h +* @brief define imxrt1052-board clock configure +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-29 +*/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 25000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 25000000U /*!< Core clock frequency: 600000000Hz */ + + + + + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/connect_gpio.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/connect_gpio.h new file mode 100644 index 000000000..f9da70b31 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/connect_gpio.h @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2022 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_gpio.h +* @brief define imxrt1052-board gpio function and struct +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-15 +*/ + +#ifndef __CONNECT_GPIO_H_ +#define __CONNECT_GPIO_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define IMXRT_GET_PIN(PORTx, PIN) (32 * (PORTx - 1) + (PIN & 31)) /* PORTx:1,2,3,4,5 */ + +int Imxrt1052HwGpioInit(void); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/connect_uart.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/connect_uart.h new file mode 100644 index 000000000..4b4c947a8 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/connect_uart.h @@ -0,0 +1,42 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_uart.h +* @brief define imxrt1052-board usart function and struct +* @version 2.0 +* @author AIIT XUOS Lab +* @date 2022-03-15 +*/ + +#ifndef CONNECT_UART_H +#define CONNECT_UART_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + + +#define KERNEL_CONSOLE_BUS_NAME SERIAL_BUS_NAME_1 +#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1 +#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0 + +int Imxrt1052HwUartInit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/fsl_clock.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/fsl_clock.h new file mode 100755 index 000000000..e69de29bb diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/fsl_common.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/fsl_common.h new file mode 100755 index 000000000..e5e2e9d72 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/fsl_common.h @@ -0,0 +1,605 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file fsl_common.h + * @brief common drivers header + * @version 2.0 + * @author AIIT XUOS Lab + * @date 2022-03-15 + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @name Driver version */ +/*@{*/ +/*! @brief common driver version 2.0.1. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ + kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ + kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ + kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ +}; + +/*! @brief Generic status return codes. */ +enum _generic_status +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/* + * Macro guard for whether to use default weak IRQ implementation in drivers + */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/** + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http://supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var +#endif +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) +#endif +#else +#error Toolchain not supported +#define SDK_ALIGN(var, alignbytes) var +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var +#endif +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var +#endif +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, + * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables + * will be initialized to zero in system startup. + */ +/* @{ */ +#if (defined(__ICCARM__)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#endif +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var +#endif +#elif(defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) +#endif +#else +#error Toolchain not supported. +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var +#endif +/* @} */ + +/*! @name Time sensitive region */ +/* @{ */ +#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +#else +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#else +#error Toolchain not supported. +#endif +#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ +/* @} */ + +/*! @name Ram Function */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif(defined(__GNUC__)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/* @} */ + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +// #include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) + extern "C" +{ +#endif + + /*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ + static inline status_t EnableIRQ(IRQn_Type interrupt) + { + // if (NotAvail_IRQn == interrupt) + // { + // return kStatus_Fail; + // } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ + static inline status_t DisableIRQ(IRQn_Type interrupt) + { + // if (NotAvail_IRQn == interrupt) + // { + // return kStatus_Fail; + // } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ + static inline uint32_t DisableGlobalIRQ(void) + { +#if defined (__XCC__) + return 0; +#else +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif +#endif + } + + /*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ + static inline void EnableGlobalIRQ(uint32_t primask) + { +#if defined (__XCC__) +#else +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif +#endif + } + +#if defined(ENABLE_RAM_VECTOR_TABLE) + /*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ + uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + /*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ + void EnableDeepSleepIRQ(IRQn_Type interrupt); + + /*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ + void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + + /*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ + void *SDK_Malloc(size_t size, size_t alignbytes); + + /*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ + void SDK_Free(void *ptr); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_COMMON_H_ */ diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/fsl_device_registers.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/fsl_device_registers.h new file mode 100755 index 000000000..db905cf31 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/fsl_device_registers.h @@ -0,0 +1,46 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/** + * @file fsl_device_registers.h + * @brief device register function + * @version 2.0 + * @author AIIT XUOS Lab + * @date 2022-03-15 + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MIMXRT1052CVJ5B) || defined(CPU_MIMXRT1052CVL5B) || defined(CPU_MIMXRT1052DVJ6B) || \ + defined(CPU_MIMXRT1052DVL6B)) + +#define MIMXRT1052_SERIES + +// /* CMSIS-style register definitions */ +// #include "MIMXRT1052.h" +// /* CPU specific feature definitions */ +// #include "MIMXRT1052_features.h" + +#include "CMSDK_CM7_SP.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/Kconfig b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/Kconfig new file mode 100644 index 000000000..50dcb94cf --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/Kconfig @@ -0,0 +1,74 @@ +config BSP_USING_LPUART1 + bool "Enable LPUART1" + default y + if BSP_USING_LPUART1 + config SERIAL_BUS_NAME_1 + string "serial bus 1 name" + default "uart1" + config SERIAL_DRV_NAME_1 + string "serial bus 1 driver name" + default "uart1_drv" + config SERIAL_1_DEVICE_NAME_0 + string "serial bus 1 device name" + default "uart1_dev1" + endif + +config BSP_USING_LPUART2 + bool "Enable LPUART2" + default y + if BSP_USING_LPUART2 + config SERIAL_BUS_NAME_2 + string "serial bus 2 name" + default "uart2" + config SERIAL_DRV_NAME_2 + string "serial bus 2 driver name" + default "uart2_drv" + config SERIAL_2_DEVICE_NAME_0 + string "serial bus 2 device name" + default "uart2_dev2" + endif + +config BSP_USING_LPUART3 + bool "Enable LPUART3" + default y + if BSP_USING_LPUART3 + config SERIAL_BUS_NAME_3 + string "serial bus 3 name" + default "uart3" + config SERIAL_DRV_NAME_3 + string "serial bus 3 driver name" + default "uart3_drv" + config SERIAL_3_DEVICE_NAME_0 + string "serial bus 3 device name" + default "uart3_dev3" + endif + +config BSP_USING_LPUART4 + bool "Enable LPUART4" + default n + if BSP_USING_LPUART4 + config SERIAL_BUS_NAME_4 + string "serial bus 4 name" + default "uart4" + config SERIAL_DRV_NAME_4 + string "serial bus 4 driver name" + default "uart4_drv" + config SERIAL_4_DEVICE_NAME_0 + string "serial bus 4 device name" + default "uart4_dev4" + endif + +config BSP_USING_LPUART8 + bool "Enable LPUART8" + default n + if BSP_USING_LPUART8 + config SERIAL_BUS_NAME_8 + string "serial bus 8 name" + default "uart8" + config SERIAL_DRV_NAME_8 + string "serial bus 8 driver name" + default "uart8_drv" + config SERIAL_8_DEVICE_NAME_0 + string "serial bus 8 device name" + default "uart8_dev8" + endif diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/Makefile b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/Makefile new file mode 100644 index 000000000..aec03ad7d --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := stdout_uart.c USART_V2M-MPS2.c connect_uart.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/USART_V2M-MPS2.c b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/USART_V2M-MPS2.c new file mode 100644 index 000000000..7256b82a0 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/USART_V2M-MPS2.c @@ -0,0 +1,50 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2016 - 2017 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 26. October 2017 + * $Revision: V1.0.3 + * + * Driver: Driver_USART0, Driver_USART1, Driver_USART2, Driver_USART3 + * + * Configured: via RTE_Device.h configuration file + * Project: UART Driver for ARM CMSDK_CM device + * -------------------------------------------------------------------------- + * Use the following configuration settings in the middleware component + * to connect to this driver. + * + * Configuration Setting Value UART Interface + * --------------------- ----- -------------- + * Connect to hardware via Driver_USART# = 0 use UART0 + * Connect to hardware via Driver_USART# = 1 use UART1 + * Connect to hardware via Driver_USART# = 2 use UART2 + * Connect to hardware via Driver_USART# = 3 use UART3 + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.0.0 + * Initial release + * Version 1.0.1 + * Removed ARMCLANG warnings + * Version 1.0.2 + * Removed ARMCLANG warnings + * Version 1.0.3 + * Removed race condition in USARTTX_IRQHandler + */ + diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/connect_uart.c b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/connect_uart.c new file mode 100644 index 000000000..c1e379636 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/connect_uart.c @@ -0,0 +1,1221 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** +* @file connect_uart.c +* @brief support imxrt1052-board uart function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-28 +*/ + +/************************************************* +File name: connect_uart.c +Description: support imxrt1052-board uart configure and uart bus register function +Others: take SDK_2.6.1_MIMXRT1052xxxxB/components/uart/lpuart_adapter.c for references +History: +1. Date: 2021-05-28 +Author: AIIT XUOS Lab +Modification: +1. support imxrt1052-board uart configure, write and read +2. support imxrt1052-board uart bus device and driver register +*************************************************/ + +#include +#include +#include + +#include "USART_V2M-MPS2.h" +// #include "board.h" + +extern uint32_t SystemCoreClock; + + +#define UNUSED(x) (void)(x) /* macro to get rid of 'unused parameter' warning */ + +#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) + +// Driver Version +static const ARM_DRIVER_VERSION usart_driver_version = { ARM_USART_API_VERSION, ARM_USART_DRV_VERSION }; + + +// USART0 +#if (defined (RTE_USART0) && (RTE_USART0 != 0)) + +// USART0 Run-Time Information +static USART_INFO USART0_Info = { 0U, { 0U, 0U, 0U }, 0U }; +static USART_TRANSFER_INFO USART0_TransferInfo = { 0U, 0U, 0U, 0U, 0U, 0U }; +static PIN USART0_pin_rx = { CMSDK_GPIO1, 0U }; +static PIN USART0_pin_tx = { CMSDK_GPIO1, 1U }; + + +// USART0 Resources +static const USART_RESOURCES USART0_Resources = { + { // Capabilities + 1, // supports UART (Asynchronous) mode + 0, // supports Synchronous Master mode + 0, // supports Synchronous Slave mode + 0, // supports UART Single-wire mode + 0, // supports UART IrDA mode + 0, // supports UART Smart Card mode + 0, // Smart Card Clock generator + 0, // RTS Flow Control available + 0, // CTS Flow Control available + 1, // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE + 1, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT + 0, // RTS Line: 0=not available, 1=available + 0, // CTS Line: 0=not available, 1=available + 0, // DTR Line: 0=not available, 1=available + 0, // DSR Line: 0=not available, 1=available + 0, // DCD Line: 0=not available, 1=available + 0, // RI Line: 0=not available, 1=available + 0, // Signal CTS change event: \ref ARM_USART_EVENT_CTS + 0, // Signal DSR change event: \ref ARM_USART_EVENT_DSR + 0, // Signal DCD change event: \ref ARM_USART_EVENT_DCD + 0, // Signal RI change event: \ref ARM_USART_EVENT_RI + 0 // Reserved (must be zero) + }, + { + &USART0_pin_rx, + &USART0_pin_tx + }, + CMSDK_UART0, + UART0RX_IRQn, + UART0TX_IRQn, + &USART0_Info, + &USART0_TransferInfo +}; + +#endif + +// USART1 +#if (defined (RTE_USART1) && (RTE_USART1 != 0)) + +// USART1 Run-Time Information +static USART_INFO USART1_Info = { 0U, { 0U, 0U, 0U }, 0U }; +static USART_TRANSFER_INFO USART1_TransferInfo = { 0U, 0U, 0U, 0U, 0U, 0U }; +static PIN USART1_pin_rx = { CMSDK_GPIO1, 7U }; +static PIN USART1_pin_tx = { CMSDK_GPIO1, 8U }; + +// USART1 Resources +static const USART_RESOURCES USART1_Resources = { + { // Capabilities + 1, // supports UART (Asynchronous) mode + 0, // supports Synchronous Master mode + 0, // supports Synchronous Slave mode + 0, // supports UART Single-wire mode + 0, // supports UART IrDA mode + 0, // supports UART Smart Card mode + 0, // Smart Card Clock generator + 0, // RTS Flow Control available + 0, // CTS Flow Control available + 1, // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE + 1, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT + 0, // RTS Line: 0=not available, 1=available + 0, // CTS Line: 0=not available, 1=available + 0, // DTR Line: 0=not available, 1=available + 0, // DSR Line: 0=not available, 1=available + 0, // DCD Line: 0=not available, 1=available + 0, // RI Line: 0=not available, 1=available + 0, // Signal CTS change event: \ref ARM_USART_EVENT_CTS + 0, // Signal DSR change event: \ref ARM_USART_EVENT_DSR + 0, // Signal DCD change event: \ref ARM_USART_EVENT_DCD + 0, // Signal RI change event: \ref ARM_USART_EVENT_RI + 0 // Reserved (must be zero) + }, + { + &USART1_pin_rx, + &USART1_pin_tx + }, + CMSDK_UART1, + UART1RX_IRQn, + UART1TX_IRQn, + &USART1_Info, + &USART1_TransferInfo +}; +#endif + +// USART2 +#if (defined (RTE_USART2) && (RTE_USART2 != 0)) + +// USART2 Run-Time Information +static USART_INFO USART2_Info = { 0U, { 0U, 0U, 0U }, 0U }; +static USART_TRANSFER_INFO USART2_TransferInfo = { 0U, 0U, 0U, 0U, 0U, 0U }; +static PIN USART2_pin_rx = { CMSDK_GPIO1, 0U }; +static PIN USART2_pin_tx = { CMSDK_GPIO1, 1U }; + +// USART2 Resources +static const USART_RESOURCES USART2_Resources = { + { // Capabilities + 1, // supports UART (Asynchronous) mode + 0, // supports Synchronous Master mode + 0, // supports Synchronous Slave mode + 0, // supports UART Single-wire mode + 0, // supports UART IrDA mode + 0, // supports UART Smart Card mode + 0, // Smart Card Clock generator + 0, // RTS Flow Control available + 0, // CTS Flow Control available + 1, // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE + 1, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT + 0, // RTS Line: 0=not available, 1=available + 0, // CTS Line: 0=not available, 1=available + 0, // DTR Line: 0=not available, 1=available + 0, // DSR Line: 0=not available, 1=available + 0, // DCD Line: 0=not available, 1=available + 0, // RI Line: 0=not available, 1=available + 0, // Signal CTS change event: \ref ARM_USART_EVENT_CTS + 0, // Signal DSR change event: \ref ARM_USART_EVENT_DSR + 0, // Signal DCD change event: \ref ARM_USART_EVENT_DCD + 0, // Signal RI change event: \ref ARM_USART_EVENT_RI + 0 // Reserved (must be zero) + }, + { + &USART2_pin_rx, + &USART2_pin_tx + }, + CMSDK_UART2, + UART2RX_IRQn, + UART2TX_IRQn, + &USART2_Info, + &USART2_TransferInfo +}; +#endif + +// USART3 +#if (defined (RTE_USART3) && (RTE_USART3 != 0)) + +// USART3 Run-Time Information +static USART_INFO USART3_Info = { 0U, { 0U, 0U, 0U }, 0U }; +static USART_TRANSFER_INFO USART3_TransferInfo = { 0U, 0U, 0U, 0U, 0U, 0U }; +static PIN USART3_pin_rx = { CMSDK_GPIO0, 0U }; +static PIN USART3_pin_tx = { CMSDK_GPIO0, 4U }; + +// USART3 Resources +static const USART_RESOURCES USART3_Resources = { + { // Capabilities + 1, // supports UART (Asynchronous) mode + 0, // supports Synchronous Master mode + 0, // supports Synchronous Slave mode + 0, // supports UART Single-wire mode + 0, // supports UART IrDA mode + 0, // supports UART Smart Card mode + 0, // Smart Card Clock generator + 0, // RTS Flow Control available + 0, // CTS Flow Control available + 1, // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE + 1, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT + 0, // RTS Line: 0=not available, 1=available + 0, // CTS Line: 0=not available, 1=available + 0, // DTR Line: 0=not available, 1=available + 0, // DSR Line: 0=not available, 1=available + 0, // DCD Line: 0=not available, 1=available + 0, // RI Line: 0=not available, 1=available + 0, // Signal CTS change event: \ref ARM_USART_EVENT_CTS + 0, // Signal DSR change event: \ref ARM_USART_EVENT_DSR + 0, // Signal DCD change event: \ref ARM_USART_EVENT_DCD + 0, // Signal RI change event: \ref ARM_USART_EVENT_RI + 0 // Reserved (must be zero) + }, + { + &USART3_pin_rx, + &USART3_pin_tx + }, + CMSDK_UART3, + UART3RX_IRQn, + UART3TX_IRQn, + &USART3_Info, + &USART3_TransferInfo +}; +#endif + + +// USART Driver functions + +/** + \fn ARM_DRIVER_VERSION USARTx_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION +*/ +static ARM_DRIVER_VERSION USARTx_GetVersion (void) { + return usart_driver_version; +} + +/** + \fn ARM_USART_CAPABILITIES USART_GetCapabilities (const USART_RESOURCES *usart) + \brief Get driver capabilities + \param[in] usart Pointer to USART resources + \return \ref ARM_USART_CAPABILITIES +*/ +static ARM_USART_CAPABILITIES USART_GetCapabilities (const USART_RESOURCES *usart) { + return usart->capabilities; +} + +/** + \fn int32_t USART_Initialize ( ARM_USART_SignalEvent_t cb_event + const USART_RESOURCES *usart) + \brief Initialize USART Interface. + \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent + \param[in] usart Pointer to USART resources + \return \ref execution_status +*/ +static int32_t USART_Initialize ( ARM_USART_SignalEvent_t cb_event, + const USART_RESOURCES *usart) { + + if (usart->info->flags & USART_FLAG_INITIALIZED) { + // Driver is already initialized + return ARM_DRIVER_OK; + } + + // Initialize callback + usart->info->cb_event = cb_event; + + // Clear transfer information + memset(usart->xfer, 0U, sizeof(USART_TRANSFER_INFO)); + + // configure USART pins + usart->pins.pin_rx->PinGpio->ALTFUNCSET |= (1u << usart->pins.pin_rx->PinNum); + usart->pins.pin_tx->PinGpio->ALTFUNCSET |= (1u << usart->pins.pin_tx->PinNum); + + usart->info->flags = USART_FLAG_INITIALIZED; // Set status flags + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t USART_Uninitialize (const USART_RESOURCES *usart) + \brief De-initialize USART Interface. + \param[in] usart Pointer to USART resources + \return \ref execution_status +*/ +static int32_t USART_Uninitialize (const USART_RESOURCES *usart) { + + // unconfigure USART pins + usart->pins.pin_rx->PinGpio->ALTFUNCSET &= ~(1u << usart->pins.pin_rx->PinNum); + usart->pins.pin_tx->PinGpio->ALTFUNCSET &= ~(1u << usart->pins.pin_tx->PinNum); + + usart->info->flags = 0U; // Reset status flags + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t USART_PowerControl (ARM_POWER_STATE state) + \brief Control USART Interface Power. + \param[in] state Power state + \param[in] usart Pointer to USART resources + \return \ref execution_status +*/ +static int32_t USART_PowerControl ( ARM_POWER_STATE state, + const USART_RESOURCES *usart) { + + switch (state) { + case ARM_POWER_OFF: + // Clear powered flag + usart->info->flags &= ~USART_FLAG_POWERED; + + // Clear and disable USART IRQ + NVIC_DisableIRQ(usart->irq_num_rx); + NVIC_ClearPendingIRQ(usart->irq_num_rx); + NVIC_DisableIRQ(usart->irq_num_tx); + NVIC_ClearPendingIRQ(usart->irq_num_tx); + break; + + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + case ARM_POWER_FULL: + if ((usart->info->flags & USART_FLAG_INITIALIZED) == 0U) { + return ARM_DRIVER_ERROR; + } + if ((usart->info->flags & USART_FLAG_POWERED) != 0U) { + return ARM_DRIVER_OK; + } + + // Initialize status flags + usart->info->status.tx_busy = 0U; + usart->info->status.rx_busy = 0U; + usart->info->status.rx_overflow = 0U; + + // Set flag initialized + usart->info->flags = USART_FLAG_POWERED | USART_FLAG_INITIALIZED; + + // Clear and enable USART IRQ + NVIC_ClearPendingIRQ(usart->irq_num_rx); + NVIC_EnableIRQ(usart->irq_num_rx); + NVIC_ClearPendingIRQ(usart->irq_num_tx); + NVIC_EnableIRQ(usart->irq_num_tx); + break; + +// default: return ARM_DRIVER_ERROR_UNSUPPORTED; + } + return ARM_DRIVER_OK; +} + +/** + \fn int32_t USART_Send (const void *data, + uint32_t num, + const USART_RESOURCES *usart) + \brief Start sending data to USART transmitter. + \param[in] data Pointer to buffer with data to send to USART transmitter + \param[in] num Number of data items to send + \param[in] usart Pointer to USART resources + \return \ref execution_status +*/ +static int32_t USART_Send (const void *data, + uint32_t num, + const USART_RESOURCES *usart) { + + if ((data == NULL) || (num == 0U)) { + // Invalid parameters + return ARM_DRIVER_ERROR_PARAMETER; + } + + if ((usart->info->flags & USART_FLAG_CONFIGURED) == 0U) { + // USART is not configured (mode not selected) + return ARM_DRIVER_ERROR; + } + + if ((usart->info->status.tx_busy != 0U) || + ((usart->reg->STATE & CMSDK_UART_STATE_TXBF_Msk) != 0U)) { + // Send is not completed yet + return ARM_DRIVER_ERROR_BUSY; + } + + // Set tx_busy flag + usart->info->status.tx_busy = 0U; + + // Save transmit buffer info + usart->xfer->tx_buf = (const uint8_t *)data; + usart->xfer->tx_num = num; + usart->xfer->tx_cnt = 0U; + + // TX interrupt enable + usart->reg->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk; + + // Start sending + usart->reg->DATA = usart->xfer->tx_buf[usart->xfer->tx_cnt]; + + return ARM_DRIVER_OK; +} + +/** + \fn int32_t USART_Receive ( void *data, + uint32_t num, + const USART_RESOURCES *usart) + \brief Start receiving data from USART receiver. + \param[out] data Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to receive + \param[in] usart Pointer to USART resources + \return \ref execution_status +*/ +static int32_t USART_Receive ( void *data, + uint32_t num, + const USART_RESOURCES *usart) { + + if ((data == NULL) || (num == 0U)) { + // Invalid parameters + return ARM_DRIVER_ERROR_PARAMETER; + } + uint32_t state = 0; + state = usart->reg->STATE; + int ch=-1; + if (state){ + ch=usart->reg->DATA& 0xff; + usart->reg->STATE=0; + } + +// if ((usart->info->flags & USART_FLAG_CONFIGURED) == 0U) { +// // USART is not configured (mode not selected) +// return ARM_DRIVER_ERROR; +// } + +// // Check if receiver is busy +// if ((usart->info->status.rx_busy != 0U) || +// ((usart->reg->STATE & CMSDK_UART_STATE_RXBF_Msk) != 0U)) { +// return ARM_DRIVER_ERROR_BUSY; +// } + +// // Save number of data to be received +// usart->xfer->rx_num = num; + +// // Clear RX status +// usart->info->status.rx_overflow = 0U; + +// // Save receive buffer info +// usart->xfer->rx_buf = (uint8_t *)data; +// usart->xfer->rx_cnt = 0U; + +// // Set RX busy flag +// usart->info->status.rx_busy = 1U; + +// // RX interrupt enable +// usart->reg->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk; + + return ch; +} + +/** + \fn int32_t USART_Transfer (const void *data_out, + void *data_in, + uint32_t num, + const USART_RESOURCES *usart) + \brief Start sending/receiving data to/from USART transmitter/receiver. + \param[in] data_out Pointer to buffer with data to send to USART transmitter + \param[out] data_in Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to transfer + \param[in] usart Pointer to USART resources + \return \ref execution_status +*/ +static int32_t USART_Transfer (const void *data_out, + void *data_in, + uint32_t num, + const USART_RESOURCES *usart) { + UNUSED(data_out); + UNUSED(data_in); + UNUSED(num); + UNUSED(usart); + + // Synchronous mode not supported + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +/** + \fn uint32_t USART_GetTxCount (const USART_RESOURCES *usart) + \brief Get transmitted data count. + \param[in] usart Pointer to USART resources + \return number of data items transmitted +*/ +static uint32_t USART_GetTxCount (const USART_RESOURCES *usart) { + + return usart->xfer->tx_cnt; + +} + +/** + \fn uint32_t USART_GetRxCount (const USART_RESOURCES *usart) + \brief Get received data count. + \param[in] usart Pointer to USART resources + \return number of data items received +*/ +static uint32_t USART_GetRxCount (const USART_RESOURCES *usart) { + + return usart->xfer->rx_cnt; + +} + +/** + \fn int32_t USART_Control ( uint32_t control, + uint32_t arg, + const USART_RESOURCES *usart) + \brief Control USART Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \param[in] usart Pointer to USART resources + \return common \ref execution_status and driver specific \ref usart_execution_status +*/ +static int32_t USART_Control ( uint32_t control, + uint32_t arg, + const USART_RESOURCES *usart) { + + if ((usart->info->flags & USART_FLAG_POWERED) == 0U) { + // USART not powered + return ARM_DRIVER_ERROR; + } + + switch (control & ARM_USART_CONTROL_Msk) { + // Control break + case ARM_USART_CONTROL_BREAK: + return ARM_DRIVER_ERROR_UNSUPPORTED; + + // Abort Send + case ARM_USART_ABORT_SEND: + // TX interrupt disable + usart->reg->CTRL &= ~CMSDK_UART_CTRL_TXIRQEN_Msk; + // Clear tx_busy status + usart->info->status.tx_busy = 0U; + return ARM_DRIVER_OK; + + // Abort receive + case ARM_USART_ABORT_RECEIVE: + // RX interrupt disable + usart->reg->CTRL &= ~CMSDK_UART_CTRL_RXIRQEN_Msk; + // Clear rx_busy status + usart->info->status.rx_busy = 0U; + return ARM_DRIVER_OK; + + // Abort transfer + case ARM_USART_ABORT_TRANSFER: + // Synchronous mode not supported + return ARM_DRIVER_ERROR_UNSUPPORTED; + + // Control TX + case ARM_USART_CONTROL_TX: + usart->info->flags |= USART_FLAG_TX_ENABLED; + // Transmitter enable + usart->reg->CTRL |= ((arg & 1U) << CMSDK_UART_CTRL_TXEN_Pos); + return ARM_DRIVER_OK; + + // Control RX + case ARM_USART_CONTROL_RX: + usart->info->flags |= USART_FLAG_RX_ENABLED; + // Receiver enable + usart->reg->CTRL |= ((arg & 1U) << CMSDK_UART_CTRL_RXEN_Pos); + return ARM_DRIVER_OK; + default: break; + } + + // Check if busy + if ((usart->info->status.tx_busy != 0U) || + (usart->info->status.rx_busy != 0U) || + ((usart->reg->STATE & (CMSDK_UART_STATE_TXBF_Msk | CMSDK_UART_STATE_RXBF_Msk)) != 0U)) { + return ARM_DRIVER_ERROR_BUSY; + } + + switch (control & ARM_USART_CONTROL_Msk) { + case ARM_USART_MODE_ASYNCHRONOUS: break; + // Unsupported command + default: return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + // USART Data bits + switch (control & ARM_USART_DATA_BITS_Msk) { + case ARM_USART_DATA_BITS_8: break; + default: return ARM_USART_ERROR_DATA_BITS; + } + + // USART Parity + switch (control & ARM_USART_PARITY_Msk) { + case ARM_USART_PARITY_NONE: break; + default: return ARM_USART_ERROR_PARITY; + } + + // USART Stop bits + switch (control & ARM_USART_STOP_BITS_Msk) { + case ARM_USART_STOP_BITS_1: break; + default: return ARM_USART_ERROR_STOP_BITS; + } + + // USART Flow control + switch (control & ARM_USART_FLOW_CONTROL_Msk) { + case ARM_USART_FLOW_CONTROL_NONE: break; + default: return ARM_USART_ERROR_FLOW_CONTROL; + } + + // USART Baudrate + if ((SystemCoreClock/arg) < 16U) + return ARM_USART_ERROR_BAUDRATE; + else + usart->reg->BAUDDIV = SystemCoreClock/arg; + + // Set configured flag + usart->info->flags |= USART_FLAG_CONFIGURED; + + return ARM_DRIVER_OK; +} + +/** + \fn ARM_USART_STATUS USART_GetStatus (const USART_RESOURCES *usart) + \brief Get USART status. + \param[in] usart Pointer to USART resources + \return USART status \ref ARM_USART_STATUS +*/ +static ARM_USART_STATUS USART_GetStatus (const USART_RESOURCES *usart) { + ARM_USART_STATUS status; + + status.tx_busy = usart->info->status.tx_busy; + status.rx_busy = usart->info->status.rx_busy; + status.rx_overflow = usart->info->status.rx_overflow; + + return status; +} + +/** + \fn int32_t USART_SetModemControl ( ARM_USART_MODEM_CONTROL control, + const USART_RESOURCES *usart) + \brief Set USART Modem Control line state. + \param[in] control \ref ARM_USART_MODEM_CONTROL + \param[in] usart Pointer to USART resources + \return \ref execution_status +*/ +static int32_t USART_SetModemControl ( ARM_USART_MODEM_CONTROL control, + const USART_RESOURCES *usart) { + UNUSED(control); + UNUSED(usart); + + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +/** + \fn ARM_USART_MODEM_STATUS USART_GetModemStatus (const USART_RESOURCES *usart) + \brief Get USART Modem Status lines state. + \param[in] usart Pointer to USART resources + \return modem status \ref ARM_USART_MODEM_STATUS +*/ +static ARM_USART_MODEM_STATUS USART_GetModemStatus (const USART_RESOURCES *usart) { + ARM_USART_MODEM_STATUS modem_status = { 0U, 0U, 0U, 0U }; + + UNUSED(usart); + + return modem_status; +} + + +static void UartIsr(struct SerialBus *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev); +#ifdef BSP_USING_LPUART1 +struct SerialBus serial_bus_1; +struct SerialDriver serial_driver_1; +struct SerialHardwareDevice serial_device_1; + +// void LPUART1_IRQHandler(int irqn, void *arg) +// { + +// DisableIRQ(UART1_IRQn); + +// UartIsr(&serial_bus_1, &serial_driver_1, &serial_device_1); +// // UART0TX_Handler(); +// EnableIRQ(UART1_IRQn); + +// } +// DECLARE_HW_IRQ(UART0TX_IRQn, UART0TX_Handler, NONE); +// DECLARE_HW_IRQ(UART0RX_IRQn, UART0RX_Handler, NONE); +#endif + + + +/** + \fn void USARTRX_IRQHandler (UART_RESOURCES *usart) + \brief USART RX Interrupt handler. + \param[in] usart Pointer to USART resources +*/ +static void USARTRX_IRQHandler (USART_RESOURCES *usart) { + uint32_t status; +// // KPrintf("RX Handler\n"); + status = usart->reg->INTSTATUS; +// if (usart->xfer->rx_buf != NULL) +// usart->xfer->rx_buf[usart->xfer->rx_cnt++] = (uint8_t)usart->reg->DATA; + usart->xfer->rx_num = 0U; + usart->info->status.rx_busy = 0U; + usart->reg->CTRL &= ~CMSDK_UART_CTRL_RXIRQEN_Msk; + usart->reg->INTCLEAR = status; + +#ifdef BSP_USING_LPUART1 + DisableIRQ(UART0RX_IRQn); + UartIsr(&serial_bus_1, &serial_driver_1, &serial_device_1); + EnableIRQ(UART0RX_IRQn); +#endif + + usart->reg->BAUDDIV = 16; + usart->reg->CTRL = CMSDK_UART_CTRL_RXIRQEN_Msk | CMSDK_UART_CTRL_RXEN_Msk | CMSDK_UART_CTRL_TXEN_Msk; + usart->reg->STATE = 0U; + +} + +/** + \fn void USARTTX_IRQHandler (UART_RESOURCES *usart) + \brief USART TX Interrupt handler. + \param[in] usart Pointer to USART resources +*/ +static void USARTTX_IRQHandler (USART_RESOURCES *usart) { + uint32_t status; + + // read interrupt status + status = usart->reg->INTSTATUS; + + // clear interrupt + usart->reg->INTCLEAR = status; + + if (usart->xfer->tx_num > 0) { + + usart->xfer->tx_cnt++; + + if (usart->xfer->tx_cnt < usart->xfer->tx_num) { + // Send next byte + usart->reg->DATA = usart->xfer->tx_buf[usart->xfer->tx_cnt]; + } else { + // TX is completed + usart->xfer->tx_num = 0U; + usart->info->status.tx_busy = 0U; + + // TX interrupt disable + usart->reg->CTRL &= ~CMSDK_UART_CTRL_TXIRQEN_Msk; + + // Send event + if (usart->info->cb_event!=NULL) + usart->info->cb_event(ARM_USART_EVENT_SEND_COMPLETE); + } + } + +} + +#if (defined (RTE_USART0) && (RTE_USART0 == 1)) +// USART0 Driver Wrapper functions + void UART0RX_Handler (void); + void UART0TX_Handler (void); +static ARM_USART_CAPABILITIES USART0_GetCapabilities (void) { return USART_GetCapabilities (&USART0_Resources); } +static int32_t USART0_Initialize (ARM_USART_SignalEvent_t cb_event) { return USART_Initialize (cb_event, &USART0_Resources); } +static int32_t USART0_Uninitialize (void) { return USART_Uninitialize (&USART0_Resources); } +static int32_t USART0_PowerControl (ARM_POWER_STATE state) { return USART_PowerControl (state, &USART0_Resources); } +static int32_t USART0_Send (const void *data, uint32_t num) { return USART_Send (data, num, &USART0_Resources); } +static int32_t USART0_Receive (void *data, uint32_t num) { return USART_Receive (data, num, &USART0_Resources); } +static int32_t USART0_Transfer (const void *data_out, void *data_in, uint32_t num) { return USART_Transfer (data_out, data_in, num, &USART0_Resources); } +static uint32_t USART0_GetTxCount (void) { return USART_GetTxCount (&USART0_Resources); } +static uint32_t USART0_GetRxCount (void) { return USART_GetRxCount (&USART0_Resources); } +static int32_t USART0_Control (uint32_t control, uint32_t arg) { return USART_Control (control, arg, &USART0_Resources); } +static ARM_USART_STATUS USART0_GetStatus (void) { return USART_GetStatus (&USART0_Resources); } +static int32_t USART0_SetModemControl (ARM_USART_MODEM_CONTROL control) { return USART_SetModemControl (control, &USART0_Resources); } +static ARM_USART_MODEM_STATUS USART0_GetModemStatus (void) { return USART_GetModemStatus (&USART0_Resources); } + void UART0RX_Handler (void) { USARTRX_IRQHandler (&USART0_Resources); } + void UART0TX_Handler (void) { USARTTX_IRQHandler (&USART0_Resources); } + +// USART0 Driver Control Block +extern ARM_DRIVER_USART Driver_USART0; + ARM_DRIVER_USART Driver_USART0 = { + USARTx_GetVersion, + USART0_GetCapabilities, + USART0_Initialize, + USART0_Uninitialize, + USART0_PowerControl, + USART0_Send, + USART0_Receive, + USART0_Transfer, + USART0_GetTxCount, + USART0_GetRxCount, + USART0_Control, + USART0_GetStatus, + USART0_SetModemControl, + USART0_GetModemStatus +}; +#endif + +#if (defined (RTE_USART1) && (RTE_USART1 == 1)) +// USART1 Driver Wrapper functions + void UART1RX_Handler (void); + void UART1TX_Handler (void); +static ARM_USART_CAPABILITIES USART1_GetCapabilities (void) { return USART_GetCapabilities (&USART1_Resources); } +static int32_t USART1_Initialize (ARM_USART_SignalEvent_t cb_event) { return USART_Initialize (cb_event, &USART1_Resources); } +static int32_t USART1_Uninitialize (void) { return USART_Uninitialize (&USART1_Resources); } +static int32_t USART1_PowerControl (ARM_POWER_STATE state) { return USART_PowerControl (state, &USART1_Resources); } +static int32_t USART1_Send (const void *data, uint32_t num) { return USART_Send (data, num, &USART1_Resources); } +static int32_t USART1_Receive (void *data, uint32_t num) { return USART_Receive (data, num, &USART1_Resources); } +static int32_t USART1_Transfer (const void *data_out, void *data_in, uint32_t num) { return USART_Transfer (data_out, data_in, num, &USART1_Resources); } +static uint32_t USART1_GetTxCount (void) { return USART_GetTxCount (&USART1_Resources); } +static uint32_t USART1_GetRxCount (void) { return USART_GetRxCount (&USART1_Resources); } +static int32_t USART1_Control (uint32_t control, uint32_t arg) { return USART_Control (control, arg, &USART1_Resources); } +static ARM_USART_STATUS USART1_GetStatus (void) { return USART_GetStatus (&USART1_Resources); } +static int32_t USART1_SetModemControl (ARM_USART_MODEM_CONTROL control) { return USART_SetModemControl (control, &USART1_Resources); } +static ARM_USART_MODEM_STATUS USART1_GetModemStatus (void) { return USART_GetModemStatus (&USART1_Resources); } + void UART1RX_Handler (void) { USARTRX_IRQHandler (&USART1_Resources); } + void UART1TX_Handler (void) { USARTTX_IRQHandler (&USART1_Resources); } + +// USART1 Driver Control Block +extern ARM_DRIVER_USART Driver_USART1; + ARM_DRIVER_USART Driver_USART1 = { + USARTx_GetVersion, + USART1_GetCapabilities, + USART1_Initialize, + USART1_Uninitialize, + USART1_PowerControl, + USART1_Send, + USART1_Receive, + USART1_Transfer, + USART1_GetTxCount, + USART1_GetRxCount, + USART1_Control, + USART1_GetStatus, + USART1_SetModemControl, + USART1_GetModemStatus +}; +#endif + +#if (defined (RTE_USART2) && (RTE_USART2 == 1)) +// USART2 Driver Wrapper functions + void UART2RX_Handler (void); + void UART2TX_Handler (void); +static ARM_USART_CAPABILITIES USART2_GetCapabilities (void) { return USART_GetCapabilities (&USART2_Resources); } +static int32_t USART2_Initialize (ARM_USART_SignalEvent_t cb_event) { return USART_Initialize (cb_event, &USART2_Resources); } +static int32_t USART2_Uninitialize (void) { return USART_Uninitialize (&USART2_Resources); } +static int32_t USART2_PowerControl (ARM_POWER_STATE state) { return USART_PowerControl (state, &USART2_Resources); } +static int32_t USART2_Send (const void *data, uint32_t num) { return USART_Send (data, num, &USART2_Resources); } +static int32_t USART2_Receive (void *data, uint32_t num) { return USART_Receive (data, num, &USART2_Resources); } +static int32_t USART2_Transfer (const void *data_out, void *data_in, uint32_t num) { return USART_Transfer (data_out, data_in, num, &USART2_Resources); } +static uint32_t USART2_GetTxCount (void) { return USART_GetTxCount (&USART2_Resources); } +static uint32_t USART2_GetRxCount (void) { return USART_GetRxCount (&USART2_Resources); } +static int32_t USART2_Control (uint32_t control, uint32_t arg) { return USART_Control (control, arg, &USART2_Resources); } +static ARM_USART_STATUS USART2_GetStatus (void) { return USART_GetStatus (&USART2_Resources); } +static int32_t USART2_SetModemControl (ARM_USART_MODEM_CONTROL control) { return USART_SetModemControl (control, &USART2_Resources); } +static ARM_USART_MODEM_STATUS USART2_GetModemStatus (void) { return USART_GetModemStatus (&USART2_Resources); } + void UART2RX_Handler (void) { USARTRX_IRQHandler (&USART2_Resources); } + void UART2TX_Handler (void) { USARTTX_IRQHandler (&USART2_Resources); } + +// USART2 Driver Control Block +extern ARM_DRIVER_USART Driver_USART2; + ARM_DRIVER_USART Driver_USART2 = { + USARTx_GetVersion, + USART2_GetCapabilities, + USART2_Initialize, + USART2_Uninitialize, + USART2_PowerControl, + USART2_Send, + USART2_Receive, + USART2_Transfer, + USART2_GetTxCount, + USART2_GetRxCount, + USART2_Control, + USART2_GetStatus, + USART2_SetModemControl, + USART2_GetModemStatus +}; +#endif + +#if (defined (RTE_USART3) && (RTE_USART3 == 1)) +// USART3 Driver Wrapper functions + void UART3RX_Handler (void); + void UART3TX_Handler (void); +static ARM_USART_CAPABILITIES USART3_GetCapabilities (void) { return USART_GetCapabilities (&USART3_Resources); } +static int32_t USART3_Initialize (ARM_USART_SignalEvent_t cb_event) { return USART_Initialize (cb_event, &USART3_Resources); } +static int32_t USART3_Uninitialize (void) { return USART_Uninitialize (&USART3_Resources); } +static int32_t USART3_PowerControl (ARM_POWER_STATE state) { return USART_PowerControl (state, &USART3_Resources); } +static int32_t USART3_Send (const void *data, uint32_t num) { return USART_Send (data, num, &USART3_Resources); } +static int32_t USART3_Receive (void *data, uint32_t num) { return USART_Receive (data, num, &USART3_Resources); } +static int32_t USART3_Transfer (const void *data_out, void *data_in, uint32_t num) { return USART_Transfer (data_out, data_in, num, &USART3_Resources); } +static uint32_t USART3_GetTxCount (void) { return USART_GetTxCount (&USART3_Resources); } +static uint32_t USART3_GetRxCount (void) { return USART_GetRxCount (&USART3_Resources); } +static int32_t USART3_Control (uint32_t control, uint32_t arg) { return USART_Control (control, arg, &USART3_Resources); } +static ARM_USART_STATUS USART3_GetStatus (void) { return USART_GetStatus (&USART3_Resources); } +static int32_t USART3_SetModemControl (ARM_USART_MODEM_CONTROL control) { return USART_SetModemControl (control, &USART3_Resources); } +static ARM_USART_MODEM_STATUS USART3_GetModemStatus (void) { return USART_GetModemStatus (&USART3_Resources); } + void UART3RX_Handler (void) { USARTRX_IRQHandler (&USART3_Resources); } + void UART3TX_Handler (void) { USARTTX_IRQHandler (&USART3_Resources); } + +// USART3 Driver Control Block +extern ARM_DRIVER_USART Driver_USART3; + ARM_DRIVER_USART Driver_USART3 = { + USARTx_GetVersion, + USART3_GetCapabilities, + USART3_Initialize, + USART3_Uninitialize, + USART3_PowerControl, + USART3_Send, + USART3_Receive, + USART3_Transfer, + USART3_GetTxCount, + USART3_GetRxCount, + USART3_Control, + USART3_GetStatus, + USART3_SetModemControl, + USART3_GetModemStatus +}; +#endif + + +extern int stdout_init (void); +extern int stdout_putchar (int ch); +extern int stdout_receivechar(); +// extern void UART0TX_Handler(); +// extern void UART0RX_Handler(); + + + + + + + +static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new) +{ + struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg; + struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg; + + if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) { + data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate; + } + + if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) { + data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order; + } + + if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) { + data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size; + } + + if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) { + data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits; + } + + if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) { + data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode; + } + + if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) { + data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode; + } + + if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) { + data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits; + } + + if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) { + data_cfg_default->serial_timeout = data_cfg_new->serial_timeout; + } +} + +static void UartIsr(struct SerialBus *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + + SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND); + +} + +// static uint32 GetUartSrcFreq(void) +// { +// uint32 freq; + +// /* To make it simple, we assume default PLL and divider settings, and the only variable +// from application is use PLL3 source or OSC source */ +// if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ { +// freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); +// } else { +// freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); +// } + +// return freq; +// } + +static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(serial_drv); + + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + // LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data; + + if (configure_info->private_data) { + struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data; + SerialCfgParamCheck(serial_cfg, serial_cfg_new); + } + + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev; + struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data; + + // config serial receive sem timeout + dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout; + + stdout_init(); + // stdout_putchar(36); + + if (configure_info->private_data) { + DisableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt); + // LPUART_EnableInterrupts(uart_base, kLPUART_RxDataRegFullInterruptEnable); + NVIC_SetPriority(serial_cfg->hw_cfg.serial_irq_interrupt, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0)); + EnableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt); + } + + + + return EOK; +} + +static uint32 SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd) +{ + NULL_PARAM_CHECK(serial_drv); + + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + // LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data; + struct BusConfigureInfo configure_info; + configure_info.private_data = NONE; + + SerialInit(serial_drv, &configure_info); + + switch (serial_operation_cmd) + { + case OPER_CLR_INT: + DisableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt); + break; + + case OPER_SET_INT: + // LPUART_EnableInterrupts(uart_base, kLPUART_RxDataRegFullInterruptEnable); + NVIC_SetPriority(serial_cfg->hw_cfg.serial_irq_interrupt, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0)); + EnableIRQ(serial_cfg->hw_cfg.serial_irq_interrupt); + break; + } + + return EOK; +} + +static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + // LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data; + + stdout_putchar(c); + // LPUART_WriteByte(uart_base, c); + // while (!(LPUART_GetStatusFlags(uart_base) & kLPUART_TxDataRegEmptyFlag)); + + return 1; +} + +static int SerialGetChar(struct SerialHardwareDevice *serial_dev) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + // LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data; + + int c = -1; + c=stdout_receivechar(); + // if (LPUART_GetStatusFlags(uart_base) & kLPUART_RxDataRegFullFlag) { + // c = LPUART_ReadByte(uart_base); + // } + + return c; +} + +static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + int serial_operation_cmd; + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = SerialInit(serial_drv, configure_info); + break; + case OPE_CFG: + serial_operation_cmd = *(int *)configure_info->private_data; + ret = SerialConfigure(serial_drv, serial_operation_cmd); + break; + default: + break; + } + + return ret; +} + +static const struct SerialDataCfg data_cfg_init = +{ + .serial_baud_rate = BAUD_RATE_115200, + .serial_data_bits = DATA_BITS_8, + .serial_stop_bits = STOP_BITS_1, + .serial_parity_mode = PARITY_NONE, + .serial_bit_order = BIT_ORDER_LSB, + .serial_invert_mode = NRZ_NORMAL, + .serial_buffer_size = SERIAL_RB_BUFSZ, + .serial_timeout = WAITING_FOREVER, +}; + +/*manage the serial device operations*/ +static const struct SerialDrvDone drv_done = +{ + .init = SerialInit, + .configure = SerialConfigure, +}; + +/*manage the serial device hal operations*/ +static struct SerialHwDevDone hwdev_done = +{ + .put_char = SerialPutChar, + .get_char = SerialGetChar, +}; + +static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name) +{ + x_err_t ret = EOK; + + /*Init the serial bus */ + ret = SerialBusInit(serial_bus, bus_name); + if (EOK != ret) { + KPrintf("Imxrt1052HwUartInit SerialBusInit error %d\n", ret); + return ERROR; + } + + /*Init the serial driver*/ + ret = SerialDriverInit(serial_driver, drv_name); + if (EOK != ret) { + KPrintf("Imxrt1052HwUartInit SerialDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the serial driver to the serial bus*/ + ret = SerialDriverAttachToBus(drv_name, bus_name); + if (EOK != ret) { + KPrintf("Imxrt1052HwUartInit SerialDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the serial device to the serial bus*/ +static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name) +{ + x_err_t ret = EOK; + + ret = SerialDeviceRegister(serial_device, serial_param, dev_name); + if (EOK != ret) { + KPrintf("Imxrt1052HwUartInit SerialDeviceInit device %s error %d\n", dev_name, ret); + return ERROR; + } + + ret = SerialDeviceAttachToBus(dev_name, bus_name); + if (EOK != ret) { + KPrintf("Imxrt1052HwUartInit SerialDeviceAttachToBus device %s error %d\n", dev_name, ret); + return ERROR; + } + + return ret; +} + +int Imxrt1052HwUartInit(void) +{ + x_err_t ret = EOK; + +#ifdef BSP_USING_LPUART1 + static struct SerialCfgParam serial_cfg_1; + memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam)); + + static struct SerialDevParam serial_dev_param_1; + memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam)); + + serial_driver_1.drv_done = &drv_done; + serial_driver_1.configure = &SerialDrvConfigure; + serial_device_1.hwdev_done = &hwdev_done; + + serial_cfg_1.data_cfg = data_cfg_init; + + CMSDK_UART0->BAUDDIV = 16; + CMSDK_UART0->CTRL = CMSDK_UART_CTRL_RXIRQEN_Msk | CMSDK_UART_CTRL_RXEN_Msk | CMSDK_UART_CTRL_TXEN_Msk; + CMSDK_UART0->STATE = 0U; + + serial_cfg_1.hw_cfg.private_data = (void *)CMSDK_UART0; + serial_cfg_1.hw_cfg.serial_irq_interrupt = UART0RX_IRQn ; + serial_driver_1.private_data = (void *)&serial_cfg_1; + + + + serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX; + serial_device_1.haldev.private_data = (void *)&serial_dev_param_1; + + ret = BoardSerialBusInit(&serial_bus_1, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1); + if (EOK != ret) { + KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_1_DEVICE_NAME_0); + if (EOK != ret) { + KPrintf("Imxrt1052HwUartInit uart error ret %u\n", ret); + return ERROR; + } +#endif + + + + return ret; +} diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/stdout_uart.c b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/stdout_uart.c new file mode 100644 index 000000000..48e877022 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/stdout_uart.c @@ -0,0 +1,133 @@ +/*----------------------------------------------------------------------------- + * Name: stdout_USART.c + * Purpose: STDOUT USART Template + * Rev.: 1.0.0 + *-----------------------------------------------------------------------------*/ + +/* Copyright (c) 2013 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#include "Driver_USART.h" + #include "RTE_Components.h" +#include "CMSDK_CM7_SP.h" +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// STDOUT USART Interface + +// Connect to hardware via Driver_USART# <0-255> +// Select driver control block for USART interface +#define USART_DRV_NUM 0 + +// Baudrate +#define USART_BAUDRATE 115200 + +// + + +#define _USART_Driver_(n) Driver_USART##n +#define USART_Driver_(n) _USART_Driver_(n) + +extern ARM_DRIVER_USART USART_Driver_(USART_DRV_NUM); +#define ptrUSART (&USART_Driver_(USART_DRV_NUM)) + + +/** + Initialize stdout + + \return 0 on success, or -1 on error. +*/ +int stdout_init (void) { + int32_t status; + + status = ptrUSART->Initialize(NULL); + if (status != ARM_DRIVER_OK) return (-1); + + status = ptrUSART->PowerControl(ARM_POWER_FULL); + if (status != ARM_DRIVER_OK) return (-1); + + status = ptrUSART->Control(ARM_USART_MODE_ASYNCHRONOUS | + ARM_USART_DATA_BITS_8 | + ARM_USART_PARITY_NONE | + ARM_USART_STOP_BITS_1 | + ARM_USART_FLOW_CONTROL_NONE, + USART_BAUDRATE); + if (status != ARM_DRIVER_OK) return (-1); + + status = ptrUSART->Control(ARM_USART_CONTROL_TX, 1); + if (status != ARM_DRIVER_OK) return (-1); + + status = ptrUSART->Control(ARM_USART_CONTROL_RX, 1); + if (status != ARM_DRIVER_OK) return (-1); + + return (0); +} + + +/** + Put a character to the stdout + + \param[in] ch Character to output + \return The character written, or -1 on write error. +*/ +extern void UART0TX_Handler(); + +int stdout_putchar (int ch) { + uint8_t buf[1]; + + buf[0] = ch; + if (ptrUSART->Send(buf, 1) != ARM_DRIVER_OK) { + return (-1); + } +// while (ptrUSART->GetTxCount() != 1); + UART0TX_Handler(); + return (ch); +} + + +int stdout_receivechar() { + int ch=-1; + int buf[1]; + buf[0]=0; + do{ + buf[0]=ptrUSART->Receive(buf, 1); + }while (buf[0]==0); + + ch=buf[0]; + + return (ch); +} + +// volatile int32_t ITM_RxBuffer = ITM_RXBUFFER_EMPTY; + +// int stdin_getchar (void) { +// int32_t ch; + +// do { +// ch = ITM_ReceiveChar(); +// } while (ch == -1); +// return (ch); +// } \ No newline at end of file diff --git a/Ubiquitous/XiZi_IIoT/path_kernel.mk b/Ubiquitous/XiZi_IIoT/path_kernel.mk index d97b59204..ee20097dc 100755 --- a/Ubiquitous/XiZi_IIoT/path_kernel.mk +++ b/Ubiquitous/XiZi_IIoT/path_kernel.mk @@ -41,6 +41,8 @@ KERNELPATHS += \ -I$(KERNEL_ROOT)/include \ -I$(KERNEL_ROOT)/resources/include + + ifeq ($(CONFIG_RESOURCES_LWIP),y) KERNELPATHS += \ -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include \ @@ -55,6 +57,20 @@ KERNELPATHS += \ endif endif +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/cortex-m7-emulator) +KERNELPATHS += \ + -I$(KERNEL_ROOT)/arch/arm/cortex-m7 \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/third_party_driver/CMSIS \ + -I$(BSP_ROOT)/third_party_driver/CMSIS/Include\ + -I$(BSP_ROOT)/third_party_driver/include \ + -I$(BSP_ROOT)/third_party_driver/include/V2M \ + -I$(KERNEL_ROOT)/include \ + -I$(KERNEL_ROOT)/resources/include + + +endif + ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/xiwangtong-arm32) KERNELPATHS += \ -I$(KERNEL_ROOT)/arch/arm/cortex-m7 \ From 53619b9b9979ce01aea8c4aa8e9aff28bd36a38f Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Mon, 7 Aug 2023 17:43:40 +0800 Subject: [PATCH 06/21] simplify codes --- .../third_party_driver/uart/Makefile | 2 +- .../third_party_driver/uart/USART_V2M-MPS2.c | 50 ------- .../third_party_driver/uart/connect_uart.c | 86 ++++++----- .../third_party_driver/uart/stdout_uart.c | 133 ------------------ 4 files changed, 55 insertions(+), 216 deletions(-) delete mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/USART_V2M-MPS2.c delete mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/stdout_uart.c diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/Makefile b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/Makefile index aec03ad7d..f8c4610b9 100644 --- a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/Makefile +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/Makefile @@ -1,3 +1,3 @@ -SRC_FILES := stdout_uart.c USART_V2M-MPS2.c connect_uart.c +SRC_FILES := connect_uart.c include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/USART_V2M-MPS2.c b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/USART_V2M-MPS2.c deleted file mode 100644 index 7256b82a0..000000000 --- a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/USART_V2M-MPS2.c +++ /dev/null @@ -1,50 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2016 - 2017 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * - * $Date: 26. October 2017 - * $Revision: V1.0.3 - * - * Driver: Driver_USART0, Driver_USART1, Driver_USART2, Driver_USART3 - * - * Configured: via RTE_Device.h configuration file - * Project: UART Driver for ARM CMSDK_CM device - * -------------------------------------------------------------------------- - * Use the following configuration settings in the middleware component - * to connect to this driver. - * - * Configuration Setting Value UART Interface - * --------------------- ----- -------------- - * Connect to hardware via Driver_USART# = 0 use UART0 - * Connect to hardware via Driver_USART# = 1 use UART1 - * Connect to hardware via Driver_USART# = 2 use UART2 - * Connect to hardware via Driver_USART# = 3 use UART3 - * -------------------------------------------------------------------------- */ - -/* History: - * Version 1.0.0 - * Initial release - * Version 1.0.1 - * Removed ARMCLANG warnings - * Version 1.0.2 - * Removed ARMCLANG warnings - * Version 1.0.3 - * Removed race condition in USARTTX_IRQHandler - */ - diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/connect_uart.c b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/connect_uart.c index c1e379636..5f1a289ec 100644 --- a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/connect_uart.c +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/connect_uart.c @@ -753,7 +753,7 @@ static void USARTTX_IRQHandler (USART_RESOURCES *usart) { } -#if (defined (RTE_USART0) && (RTE_USART0 == 1)) +#ifdef BSP_USING_LPUART1 // USART0 Driver Wrapper functions void UART0RX_Handler (void); void UART0TX_Handler (void); @@ -793,7 +793,7 @@ extern ARM_DRIVER_USART Driver_USART0; }; #endif -#if (defined (RTE_USART1) && (RTE_USART1 == 1)) +#ifdef BSP_USING_LPUART2 // USART1 Driver Wrapper functions void UART1RX_Handler (void); void UART1TX_Handler (void); @@ -833,7 +833,7 @@ extern ARM_DRIVER_USART Driver_USART1; }; #endif -#if (defined (RTE_USART2) && (RTE_USART2 == 1)) +#ifdef BSP_USING_LPUART3 // USART2 Driver Wrapper functions void UART2RX_Handler (void); void UART2TX_Handler (void); @@ -873,7 +873,7 @@ extern ARM_DRIVER_USART Driver_USART2; }; #endif -#if (defined (RTE_USART3) && (RTE_USART3 == 1)) +#ifdef BSP_USING_LPUART4 // USART3 Driver Wrapper functions void UART3RX_Handler (void); void UART3TX_Handler (void); @@ -914,15 +914,20 @@ extern ARM_DRIVER_USART Driver_USART3; #endif -extern int stdout_init (void); -extern int stdout_putchar (int ch); -extern int stdout_receivechar(); +// extern int stdout_init (void); +// extern int stdout_putchar (int ch); +// extern int stdout_receivechar(); // extern void UART0TX_Handler(); // extern void UART0RX_Handler(); +#define _USART_Driver_(n) Driver_USART##n +#define USART_Driver_(n) _USART_Driver_(n) + +extern ARM_DRIVER_USART USART_Driver_(0); +#define ptrUSART1 (&USART_Driver_(0)) - +#define USART_BAUDRATE 115200 @@ -972,20 +977,7 @@ static void UartIsr(struct SerialBus *serial, struct SerialDriver *serial_drv, s } -// static uint32 GetUartSrcFreq(void) -// { -// uint32 freq; -// /* To make it simple, we assume default PLL and divider settings, and the only variable -// from application is use PLL3 source or OSC source */ -// if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ { -// freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); -// } else { -// freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); -// } - -// return freq; -// } static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info) { @@ -1005,7 +997,28 @@ static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInf // config serial receive sem timeout dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout; - stdout_init(); + int32_t status; + + status = ptrUSART1->Initialize(NULL); + if (status != ARM_DRIVER_OK) return (-1); + + status = ptrUSART1->PowerControl(ARM_POWER_FULL); + if (status != ARM_DRIVER_OK) return (-1); + + status = ptrUSART1->Control(ARM_USART_MODE_ASYNCHRONOUS | + ARM_USART_DATA_BITS_8 | + ARM_USART_PARITY_NONE | + ARM_USART_STOP_BITS_1 | + ARM_USART_FLOW_CONTROL_NONE, + USART_BAUDRATE); + if (status != ARM_DRIVER_OK) return (-1); + + status = ptrUSART1->Control(ARM_USART_CONTROL_TX, 1); + if (status != ARM_DRIVER_OK) return (-1); + + status = ptrUSART1->Control(ARM_USART_CONTROL_RX, 1); + if (status != ARM_DRIVER_OK) return (-1); + // stdout_init(); // stdout_putchar(36); if (configure_info->private_data) { @@ -1047,14 +1060,20 @@ static uint32 SerialConfigure(struct SerialDriver *serial_drv, int serial_operat return EOK; } + static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c) { struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; - // LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data; + + uint8_t buf[1]; + + buf[0] = c; + if (ptrUSART1->Send(buf, 1) != ARM_DRIVER_OK) { + return (-1); + } + + UART0TX_Handler(); - stdout_putchar(c); - // LPUART_WriteByte(uart_base, c); - // while (!(LPUART_GetStatusFlags(uart_base) & kLPUART_TxDataRegEmptyFlag)); return 1; } @@ -1062,13 +1081,16 @@ static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c) static int SerialGetChar(struct SerialHardwareDevice *serial_dev) { struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; - // LPUART_Type *uart_base = (LPUART_Type *)serial_cfg->hw_cfg.private_data; + + int c=-1; + int buf[1]; + buf[0]=0; + do{ + buf[0]=ptrUSART1->Receive(buf, 1); + }while (buf[0]==0); + + c=buf[0]; - int c = -1; - c=stdout_receivechar(); - // if (LPUART_GetStatusFlags(uart_base) & kLPUART_RxDataRegFullFlag) { - // c = LPUART_ReadByte(uart_base); - // } return c; } diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/stdout_uart.c b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/stdout_uart.c deleted file mode 100644 index 48e877022..000000000 --- a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/stdout_uart.c +++ /dev/null @@ -1,133 +0,0 @@ -/*----------------------------------------------------------------------------- - * Name: stdout_USART.c - * Purpose: STDOUT USART Template - * Rev.: 1.0.0 - *-----------------------------------------------------------------------------*/ - -/* Copyright (c) 2013 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#include "Driver_USART.h" - #include "RTE_Components.h" -#include "CMSDK_CM7_SP.h" -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// STDOUT USART Interface - -// Connect to hardware via Driver_USART# <0-255> -// Select driver control block for USART interface -#define USART_DRV_NUM 0 - -// Baudrate -#define USART_BAUDRATE 115200 - -// - - -#define _USART_Driver_(n) Driver_USART##n -#define USART_Driver_(n) _USART_Driver_(n) - -extern ARM_DRIVER_USART USART_Driver_(USART_DRV_NUM); -#define ptrUSART (&USART_Driver_(USART_DRV_NUM)) - - -/** - Initialize stdout - - \return 0 on success, or -1 on error. -*/ -int stdout_init (void) { - int32_t status; - - status = ptrUSART->Initialize(NULL); - if (status != ARM_DRIVER_OK) return (-1); - - status = ptrUSART->PowerControl(ARM_POWER_FULL); - if (status != ARM_DRIVER_OK) return (-1); - - status = ptrUSART->Control(ARM_USART_MODE_ASYNCHRONOUS | - ARM_USART_DATA_BITS_8 | - ARM_USART_PARITY_NONE | - ARM_USART_STOP_BITS_1 | - ARM_USART_FLOW_CONTROL_NONE, - USART_BAUDRATE); - if (status != ARM_DRIVER_OK) return (-1); - - status = ptrUSART->Control(ARM_USART_CONTROL_TX, 1); - if (status != ARM_DRIVER_OK) return (-1); - - status = ptrUSART->Control(ARM_USART_CONTROL_RX, 1); - if (status != ARM_DRIVER_OK) return (-1); - - return (0); -} - - -/** - Put a character to the stdout - - \param[in] ch Character to output - \return The character written, or -1 on write error. -*/ -extern void UART0TX_Handler(); - -int stdout_putchar (int ch) { - uint8_t buf[1]; - - buf[0] = ch; - if (ptrUSART->Send(buf, 1) != ARM_DRIVER_OK) { - return (-1); - } -// while (ptrUSART->GetTxCount() != 1); - UART0TX_Handler(); - return (ch); -} - - -int stdout_receivechar() { - int ch=-1; - int buf[1]; - buf[0]=0; - do{ - buf[0]=ptrUSART->Receive(buf, 1); - }while (buf[0]==0); - - ch=buf[0]; - - return (ch); -} - -// volatile int32_t ITM_RxBuffer = ITM_RXBUFFER_EMPTY; - -// int stdin_getchar (void) { -// int32_t ch; - -// do { -// ch = ITM_ReceiveChar(); -// } while (ch == -1); -// return (ch); -// } \ No newline at end of file From 085c418faa32c6863f4618575e1810b5e581b926 Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Tue, 26 Sep 2023 10:17:33 +0800 Subject: [PATCH 07/21] contest chusai --- .../connection_app/mqtt_demo/lwip_mqtt_demo.c | 112 ------------------ 1 file changed, 112 deletions(-) diff --git a/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c b/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c index 2d7d6fa29..8d51ebd23 100644 --- a/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c +++ b/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c @@ -612,117 +612,5 @@ int32_t MQTTMsgPublish(int32_t sock, char *topic, int8_t qos, uint8_t* msg) } -static void *MqttSocketSendTask(void *arg) -{ - - int fd = -1, clientfd; - int recv_len; - int ret; - char *recv_buf; - struct sockaddr_in mqtt_addr; - socklen_t addr_len; - - fd = socket(AF_INET, SOCK_STREAM, 0); - if (fd < 0) { - lw_print("Socket error\n"); - return NULL; - } - - struct sockaddr_in mqtt_sock; - mqtt_sock.sin_family = AF_INET; - mqtt_sock.sin_port = htons(mqtt_socket_port); - mqtt_sock.sin_addr.s_addr = inet_addr(mqtt_ip_str); - - memset(&(mqtt_sock.sin_zero), 0, sizeof(mqtt_sock.sin_zero)); - - ret = connect(fd, (struct sockaddr *)&mqtt_sock, sizeof(struct sockaddr)); - - if (ret < 0) { - lw_print("Unable to connect %s:%d = %d\n", mqtt_ip_str, mqtt_socket_port, ret); - close(fd); - return NULL; - } - - lw_print("MQTT connect %s:%d success, begin to verify hostname and password.\n", mqtt_ip_str, mqtt_socket_port); - - if(MQTT_Connect() != Connect_OK) - { - lw_print("MQTT verify failed.\n"); - shutdown(fd, SHUT_WR); - recv(fd, NULL, (size_t)0, 0); - close(fd); - return NULL; - } - - lw_print("MQTT subscribe begin.\n"); - if(MQTTSubscribe(fd,(char *)TOPIC,QOS1) < 0) - { - lw_print("MQTT subscribe failed.\n"); - shutdown(fd, SHUT_WR); - recv(fd, NULL, (size_t)0, 0); - close(fd); - return NULL; - } - - lw_print("subscribe success.\n"); - - uint8_t no_mqtt_msg_exchange = 1; - uint32_t curtick=0; - uint8_t res; - - cJSON* cJSON_Data = NULL; - cJSON_Data = cJSON_Data_Init(); - DHT11_Data_TypeDef* recv_data; - - double a,b; - while(1) - { - curtick+=1; - char* p ="Hello,here is hc"; - ret = MQTTMsgPublish(fd,(char*)TOPIC,QOS0,(uint8_t*)p); - if(ret >= 0) - { - no_mqtt_msg_exchange = 0; - PrivTaskDelay(1000); - } - } -} - - -void MqttSocketSendTest(int argc, char *argv[]) -{ - if(argc >= 2) { - lw_print("lw: [%s] target ip %s\n", __func__, argv[1]); - MqttSocketConfigParam(argv[1]); - } - - - // ip4_addr_t dns_ip; - // netconn_gethostbyname(HOST_NAME, &dns_ip); - // char* host_ip = ip_ntoa(&dns_ip); - // lw_print("host name : %s , host_ip : %s\n",HOST_NAME,host_ip); - // MqttSocketConfigParam(host_ip); - - -#ifdef ADD_XIZI_FEATURES - lwip_config_tcp(0, mqtt_demo_ipaddr, mqtt_demo_netmask, mqtt_demo_gwaddr); - - pthread_attr_t attr; - attr.schedparam.sched_priority = LWIP_MQTT_DEMO_TASK_PRIO; - attr.stacksize = LWIP_MQTT_DEMO_TASK_STACK_SIZE; -#endif - -#ifdef ADD_NUTTX_FEATURES - pthread_attr_t attr = PTHREAD_ATTR_INITIALIZER; - attr.priority = LWIP_mqtt_DEMO_TASK_PRIO; - attr.stacksize = LWIP_mqtt_DEMO_TASK_STACK_SIZE; -#endif - - PrivTaskCreate(&mqtt_client_task, &attr, &MqttSocketSendTask, NULL); - PrivTaskStartup(&mqtt_client_task); -} - -PRIV_SHELL_CMD_FUNCTION(MqttSocketSendTest, a tcp send sample, PRIV_SHELL_CMD_MAIN_ATTR); - From d884774bcac846f7bc30bb03141b2fd3dbc7bbf4 Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Tue, 26 Sep 2023 10:20:29 +0800 Subject: [PATCH 08/21] contest final --- .../connection_app/mqtt_demo/lwip_mqtt_demo.c | 112 ++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c b/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c index 8d51ebd23..2d7d6fa29 100644 --- a/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c +++ b/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c @@ -612,5 +612,117 @@ int32_t MQTTMsgPublish(int32_t sock, char *topic, int8_t qos, uint8_t* msg) } +static void *MqttSocketSendTask(void *arg) +{ + + int fd = -1, clientfd; + int recv_len; + int ret; + char *recv_buf; + struct sockaddr_in mqtt_addr; + socklen_t addr_len; + + fd = socket(AF_INET, SOCK_STREAM, 0); + if (fd < 0) { + lw_print("Socket error\n"); + return NULL; + } + + struct sockaddr_in mqtt_sock; + mqtt_sock.sin_family = AF_INET; + mqtt_sock.sin_port = htons(mqtt_socket_port); + mqtt_sock.sin_addr.s_addr = inet_addr(mqtt_ip_str); + + memset(&(mqtt_sock.sin_zero), 0, sizeof(mqtt_sock.sin_zero)); + + ret = connect(fd, (struct sockaddr *)&mqtt_sock, sizeof(struct sockaddr)); + + if (ret < 0) { + lw_print("Unable to connect %s:%d = %d\n", mqtt_ip_str, mqtt_socket_port, ret); + close(fd); + return NULL; + } + + lw_print("MQTT connect %s:%d success, begin to verify hostname and password.\n", mqtt_ip_str, mqtt_socket_port); + + if(MQTT_Connect() != Connect_OK) + { + lw_print("MQTT verify failed.\n"); + shutdown(fd, SHUT_WR); + recv(fd, NULL, (size_t)0, 0); + close(fd); + return NULL; + } + + lw_print("MQTT subscribe begin.\n"); + if(MQTTSubscribe(fd,(char *)TOPIC,QOS1) < 0) + { + lw_print("MQTT subscribe failed.\n"); + shutdown(fd, SHUT_WR); + recv(fd, NULL, (size_t)0, 0); + close(fd); + return NULL; + } + + lw_print("subscribe success.\n"); + + uint8_t no_mqtt_msg_exchange = 1; + uint32_t curtick=0; + uint8_t res; + + cJSON* cJSON_Data = NULL; + cJSON_Data = cJSON_Data_Init(); + DHT11_Data_TypeDef* recv_data; + + double a,b; + while(1) + { + curtick+=1; + char* p ="Hello,here is hc"; + ret = MQTTMsgPublish(fd,(char*)TOPIC,QOS0,(uint8_t*)p); + if(ret >= 0) + { + no_mqtt_msg_exchange = 0; + PrivTaskDelay(1000); + } + } +} + + +void MqttSocketSendTest(int argc, char *argv[]) +{ + if(argc >= 2) { + lw_print("lw: [%s] target ip %s\n", __func__, argv[1]); + MqttSocketConfigParam(argv[1]); + } + + + // ip4_addr_t dns_ip; + // netconn_gethostbyname(HOST_NAME, &dns_ip); + // char* host_ip = ip_ntoa(&dns_ip); + // lw_print("host name : %s , host_ip : %s\n",HOST_NAME,host_ip); + // MqttSocketConfigParam(host_ip); + + +#ifdef ADD_XIZI_FEATURES + lwip_config_tcp(0, mqtt_demo_ipaddr, mqtt_demo_netmask, mqtt_demo_gwaddr); + + pthread_attr_t attr; + attr.schedparam.sched_priority = LWIP_MQTT_DEMO_TASK_PRIO; + attr.stacksize = LWIP_MQTT_DEMO_TASK_STACK_SIZE; +#endif + +#ifdef ADD_NUTTX_FEATURES + pthread_attr_t attr = PTHREAD_ATTR_INITIALIZER; + attr.priority = LWIP_mqtt_DEMO_TASK_PRIO; + attr.stacksize = LWIP_mqtt_DEMO_TASK_STACK_SIZE; +#endif + + PrivTaskCreate(&mqtt_client_task, &attr, &MqttSocketSendTask, NULL); + PrivTaskStartup(&mqtt_client_task); +} + +PRIV_SHELL_CMD_FUNCTION(MqttSocketSendTest, a tcp send sample, PRIV_SHELL_CMD_MAIN_ATTR); + From e745fc9129c6cf889f035bc8737f5cdbdaa62391 Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Tue, 26 Sep 2023 10:33:24 +0800 Subject: [PATCH 09/21] aiot cache codes --- .../XiZi_AIoT/hardkernel/abstraction/TLB.c | 56 + .../hardkernel/abstraction/barriers.h | 42 + .../XiZi_AIoT/hardkernel/abstraction/cache.c | 382 +++++- .../XiZi_AIoT/hardkernel/abstraction/cache.h | 419 ++++++ .../hardkernel/abstraction/cp15_cacheops.h | 1141 +++++++++++++++++ .../abstraction/cp15_coherent_dcache.S | 138 ++ .../hardkernel/abstraction/l1cache.c | 279 ++++ .../hardkernel/abstraction/l1cache.h | 130 ++ .../XiZi_AIoT/hardkernel/abstraction/l2cc.h | 243 ++++ .../hardkernel/abstraction/l2cc_pl310.c | 866 +++++++++++++ .../hardkernel/abstraction/l2cc_pl310.h | 483 +++++++ .../arch/arm/armv7-a/cortex-a9/device.h | 72 ++ .../arch/arm/armv7-a/cortex-a9/imx6q_desc.c | 56 + 13 files changed, 4281 insertions(+), 26 deletions(-) create mode 100755 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/TLB.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/barriers.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cp15_cacheops.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cp15_coherent_dcache.S create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/device.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q_desc.c diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/TLB.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/TLB.c new file mode 100755 index 000000000..45ce50e3b --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/TLB.c @@ -0,0 +1,56 @@ + + +#define CP15_TLBIALLIS(r) _CP15(0, r, c8, c3, 0) /* Invalidate entire unified TLB Inner Shareable */ +#define CP15_TLBIMVAIS(r) _CP15(0, r, c8, c3, 1) /* Invalidate unified TLB entry by MVA and ASID, Inner Shareable */ +#define CP15_TLBIASIDIS(r) _CP15(0, r, c8, c3, 2) /* Invalidate unified TLB by ASID match Inner Shareable */ +#define CP15_TLBIMVAAIS(r) _CP15(0, r, c8, c3, 3) /* Invalidate unified TLB entry by MVA all ASID Inner Shareable */ +#define CP15_TLBIALL(r,c) _CP15(0, r, c8, c, 0) /* Invalidate entire instruction TLB. CRm = c5, c6, or c7 */ +#define CP15_TLBIMVA(r,c) _CP15(0, r, c8, c, 1) /* Invalidate instruction TLB entry by MVA and ASID. CRm = c5, c6, or c7 */ +#define CP15_TLBIASID(r,c) _CP15(0, r, c8, c, 2) /* Invalidate data TLB by ASID match. CRm = c5, c6, or c7 */ +#define CP15_TLBIMVAA(r,c) _CP15(0, r, c8, c, 3) /* Invalidate unified TLB entry by MVA and ASID. CRm = c5, c6, or c7 */ + +void InvalidateTlbsAll(void) +{ + __asm__ __volatile__ + ( + "\tmcr p15, 0, r0, c8, c7, 0\n" /* TLBIALL */ + : + : + : "r0", "memory" + ); +} + +void InvalidateTlbMVA(uint32_t vaddr) +{ + __asm__ __volatile__ + ( + "\tdsb\n" + + "\tmcr p15, 0, %0, c8, c7, 1\n" /* TLBIMVA */ + + "\tdsb\n" + "\tisb\n" + : + : "r" (vaddr) + : "r1", "memory" + ); +} + + +void InvalidateTlbASID(uint32_t vaddr) +{ + __asm__ __volatile__ + ( + "\tdsb\n" + + "\tmcr p15, 0, %0, c8, c7, 2\n" /* TLBIASID */ + + "\tdsb\n" + "\tisb\n" + : + : "r" (vaddr) + : "r1", "memory" + ); +} + + diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/barriers.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/barriers.h new file mode 100644 index 000000000..70e98e5d4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/barriers.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * arch/arm/src/armv7-a/barriers.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_ARMV7_A_BARRIERS_H +#define __ARCH_ARM_SRC_ARMV7_A_BARRIERS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* ARMv7-A memory barriers */ + +#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory") +#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory") +#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory") + +#define ARM_DSB() arm_dsb(15) +#define ARM_ISB() arm_isb(15) +#define ARM_DMB() arm_dmb(15) + +#endif /* __ARCH_ARM_SRC_ARMV7_A_BARRIERS_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c index 4a71e6c30..6e613f117 100755 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c @@ -1,35 +1,365 @@ -/* -* Copyright (c) 2020 AIIT XUOS Lab -* XiUOS is licensed under Mulan PSL v2. -* You can use this software according to the terms and conditions of the Mulan PSL v2. -* You may obtain a copy of Mulan PSL v2 at: -* http://license.coscl.org.cn/MulanPSL2 -* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -* See the Mulan PSL v2 for more details. -*/ +/**************************************************************************** + * arch/arm/src/armv7-a/arm_cache.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ -/** -* @file: cache.c -* @brief: the general management of system cache -* @version: 3.0 -* @author: AIIT XUOS Lab -* @date: 2023/4/27 -* -*/ +/**************************************************************************** + * Included Files + ****************************************************************************/ -void InvalidInsCache() + +#include "cache.h" +#include "cp15_cacheops.h" +#include "barriers.h" +#include "l1cache.h" +#include "l2cc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ +struct ICacheDone { - PlatInvalidInsCache(); + uint32_t (*enable) (void ); + uint32_t (*disable) (void); + uint32_t (*invalidate) (uintptr_t start, uintptr_t end); + uint32_t (*invalidateall) (void ); +}; + +static const struct ICacheDone icache_done = +{ + .enable = enable_icache, + .disable = disable_icache, + .invalidate = invalidate_icache, + .invalidateall = invalidate_icache_all, +}; + + +struct DCacheDone +{ + uint32_t (*enable) (void ); + uint32_t (*disable) (void); + uint32_t (*clean) (uintptr_t start, uintptr_t end); + uint32_t (*flush) (uintptr_t start, uintptr_t end); + uint32_t (*invalidate) (uintptr_t start, uintptr_t end); + uint32_t (*cleanall) (void); + uint32_t (*flushall) (void); + uint32_t (*invalidateall) (void); +}; + +static const struct DCacheDone dcache_done = +{ + .enable = enable_dcache, + .disable = disable_dcache, + .clean = clean_dcache, + .flush = flush_dcache, + .invalidate = invalidate_dcache, + .cleanall = clean_dcache_all, + .flushall = flush_dcache_all, + .invalidateall = invalidate_dcache_all, +}; + + +/**************************************************************************** + * Name: invalidate_dcache + * + * Description: + * Invalidate the data cache within the specified region; we will be + * performing a DMA operation in this region and we want to purge old data + * in the cache. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + * Assumptions: + * This operation is not atomic. This function assumes that the caller + * has exclusive access to the address range so that no harm is done if + * the operation is pre-empted. + * + ****************************************************************************/ + +void invalidate_dcache(uintptr_t start, uintptr_t end) +{ + InvalidateL1Dcache(start, end); + InvalidateL2Cache(start, end); } -void InvalidDataCache(unsigned long start, unsigned long end) +/**************************************************************************** + * Name: invalidate_dcache_all + * + * Description: + * Invalidate the entire contents of D cache. + * + * NOTE: This function forces L1 and L2 cache operations to be atomic + * by disabling interrupts. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void invalidate_dcache_all(void) { - PlatInvalidDateCache(start, end); + InvalidateL1DcacheAll(); + +#ifdef CONFIG_ARCH_L2CACHE + InvalidateL2CacheAll(); +#endif + } -void CleanDataCache(unsigned long start, unsigned long end) +/**************************************************************************** + * Name: invalidate_icache + * + * Description: + * Invalidate the instruction cache within the specified region. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ +void invalidate_icache(uintptr_t start, uintptr_t end) { - PlatCleanDateCache(start, end); -} \ No newline at end of file + InvalidateL1Icache(start, end); +} + +/**************************************************************************** + * Name: invalidate_icache_all + * + * Description: + * Invalidate all instruction caches to PoU, also flushes branch target + * cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void invalidate_icache_all(void) +{ + InvalidateL1IcacheAll(); +} + +/**************************************************************************** + * Name: clean_dcache + * + * Description: + * Clean the data cache within the specified region by flushing the + * contents of the data cache to memory. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + * Assumptions: + * This operation is not atomic. This function assumes that the caller + * has exclusive access to the address range so that no harm is done if + * the operation is pre-empted. + * + ****************************************************************************/ + +void clean_dcache(uintptr_t start, uintptr_t end) +{ + + CleanL1Dcache(start, end); + CleanL2Cache(start, end); +} + +/**************************************************************************** + * Name: clean_dcache_all + * + * Description: + * Clean the entire data cache within the specified region by flushing the + * contents of the data cache to memory. + * + * NOTE: This operation is un-necessary if the DCACHE is configured in + * write-through mode. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Assumptions: + * This operation is not atomic. This function assumes that the caller + * has exclusive access to the address range so that no harm is done if + * the operation is pre-empted. + * + ****************************************************************************/ + +void clean_dcache_all(void) +{ + CleanL1DcacheAll(); + CleanL2CacheAll(); +} + +/**************************************************************************** + * Name: flush_dcache + * + * Description: + * Flush the data cache within the specified region by cleaning and + * invalidating the D cache. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + * Assumptions: + * This operation is not atomic. This function assumes that the caller + * has exclusive access to the address range so that no harm is done if + * the operation is pre-empted. + * + ****************************************************************************/ + +void flush_dcache(uintptr_t start, uintptr_t end) +{ + + FlushL1Dcache(start, end); + + + FlushL2Cache(start, end); +} + +/**************************************************************************** + * Name: flush_dcache_all + * + * Description: + * Flush the entire data cache by cleaning and invalidating the D cache. + * + * NOTE: If DCACHE write-through is configured, then this operation is the + * same as invalidate_cache_all(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Assumptions: + * This operation is not atomic. This function assumes that the caller + * has exclusive access to the address range so that no harm is done if + * the operation is pre-empted. + * + ****************************************************************************/ + +void flush_dcache_all(void) +{ + FlushL1DcacheAll(); + + FlushL2CacheAll(); +} + +/**************************************************************************** + * Name: enable_icache + * + * Description: + * Enable the I-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void enable_icache(void) +{ + EnableL1Icache(); +} + +/**************************************************************************** + * Name: disable_icache + * + * Description: + * Disable the I-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void disable_icache(void) +{ + DisableL1Icache(); +} + +/**************************************************************************** + * Name: enable_dcache + * + * Description: + * Enable the D-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void enable_dcache(void) +{ + EnableL1Dcache(); + EnableL2Cache(); +} + +/**************************************************************************** + * Name: disable_dcache + * + * Description: + * Disable the D-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void disable_dcache(void) +{ + DisableL1Dcache(); + DisableL2Cache(); +} + + diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.h new file mode 100644 index 000000000..fb42509fa --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.h @@ -0,0 +1,419 @@ +/**************************************************************************** + * include/nuttx/cache.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_CACHE_H +#define __INCLUDE_NUTTX_CACHE_H + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + + + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: enable_icache + * + * Description: + * Enable the I-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Caution: + * The writable global variables aren't initialized yet. + * + ****************************************************************************/ +void enable_icache(void); + + +/**************************************************************************** + * Name: disable_icache + * + * Description: + * Disable the I-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ +void disable_icache(void); + + +/**************************************************************************** + * Name: invalidate_icache + * + * Description: + * Invalidate the instruction cache within the specified region. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ +void invalidate_icache(uintptr_t start, uintptr_t end); + + +/**************************************************************************** + * Name: invalidate_icache_all + * + * Description: + * Invalidate the entire contents of I cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + + +void invalidate_icache_all(void); + +/**************************************************************************** + * Name: lock_icache + * + * Description: + * Prefetch and lock the instruction cache within the specified region. + * If the specified address if not present in the instruction cache, + * some architectures transfer the line from memory, others wait the + * address be read from memory, and then lock. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + +void lock_icache(uintptr_t start, uintptr_t end); + + +/**************************************************************************** + * Name: unlock_icache + * + * Description: + * Unlock the instruction cache within the specified region. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + +void unlock_icache(uintptr_t start, uintptr_t end); + + +/**************************************************************************** + * Name: unlock_icache_all + * + * Description: + * Unlock the entire contents of instruction cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + + +void unlock_icache_all(void); + + +/**************************************************************************** + * Name: enable_dcache + * + * Description: + * Enable the D-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Caution: + * The writable global variables aren't initialized yet. + * + ****************************************************************************/ + + +void enable_dcache(void); + + +/**************************************************************************** + * Name: disable_dcache + * + * Description: + * Disable the D-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + + +void disable_dcache(void); + + +/**************************************************************************** + * Name: invalidate_dcache + * + * Description: + * Invalidate the data cache within the specified region; we will be + * performing a DMA operation in this region and we want to purge old data + * in the cache. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + + +void invalidate_dcache(uintptr_t start, uintptr_t end); + + +/**************************************************************************** + * Name: invalidate_dcache_all + * + * Description: + * Invalidate the entire contents of D cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + + +void invalidate_dcache_all(void); + + +/**************************************************************************** + * Name: clean_dcache + * + * Description: + * Clean the data cache within the specified region by flushing the + * contents of the data cache to memory. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + + +void clean_dcache(uintptr_t start, uintptr_t end); + + +/**************************************************************************** + * Name: clean_dcache_all + * + * Description: + * Clean the entire data cache within the specified region by flushing the + * contents of the data cache to memory. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + + +void clean_dcache_all(void); + + +/**************************************************************************** + * Name: flush_dcache + * + * Description: + * Flush the data cache within the specified region by cleaning and + * invalidating the D cache. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + + +void flush_dcache(uintptr_t start, uintptr_t end); + + +/**************************************************************************** + * Name: flush_dcache_all + * + * Description: + * Flush the entire data cache by cleaning and invalidating the D cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + + +void flush_dcache_all(void); + + +/**************************************************************************** + * Name: lock_dcache + * + * Description: + * Prefetch and lock the data cache within the specified region. + * If the specified address is not present in the data cache, + * some architectures transfer the line from memory, others wait the + * address be read from memory, and then lock. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + + +void lock_dcache(uintptr_t start, uintptr_t end); + + +/**************************************************************************** + * Name: unlock_dcache + * + * Description: + * Unlock the data cache within the specified region. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + +void unlock_dcache(uintptr_t start, uintptr_t end); + + +/**************************************************************************** + * Name: unlock_dcache_all + * + * Description: + * Unlock the entire contents of data cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + + +void unlock_dcache_all(void); + + +/**************************************************************************** + * Name: coherent_dcache + * + * Description: + * Ensure that the I and D caches are coherent within specified region + * by cleaning the D cache (i.e., flushing the D cache contents to memory + * and invalidating the I cache. This is typically used when code has been + * written to a memory region, and will be executed. + * + * Input Parameters: + * addr - virtual start address of region + * len - Size of the address region in bytes + * + * Returned Value: + * None + * + ****************************************************************************/ + + +void coherent_dcache(uintptr_t addr, size_t len); + + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __INCLUDE_NUTTX_CACHE_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cp15_cacheops.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cp15_cacheops.h new file mode 100644 index 000000000..18fad4d8c --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cp15_cacheops.h @@ -0,0 +1,1141 @@ +/**************************************************************************** + * arch/arm/src/armv7-a/cp15_cacheops.h + * + * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Portions of this file derive from Atmel sample code for the SAMA5D3 + * Cortex-A5 which also has a modified BSD-style license: + * + * Copyright (c) 2012, Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor Atmel nor the names of the contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* References: + * + * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1, + * Copyright 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810) + * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition", + * Copyright 1996-1998, 2000, 2004-2012 ARM. + * All rights reserved. ARM DDI 0406C.b (ID072512) + */ + +#ifndef __ARCH_ARM_SRC_ARMV7_A_CP15_CACHEOPS_H +#define __ARCH_ARM_SRC_ARMV7_A_CP15_CACHEOPS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Cache definitions ********************************************************/ + +/* L1 Memory */ + +#define CP15_L1_LINESIZE 32 + +/* CP15 Registers ***********************************************************/ + +/* Reference: Cortex-A5 MPCore + * Paragraph 4.1.5, "Cache Operations Registers." + * + * Terms: + * 1) Point of coherency (PoC) + * The PoC is the point at which all agents that can access memory are + * guaranteed to see the same copy of a memory location + * 2) Point of unification (PoU) + * The PoU is the point by which the instruction and data caches and the + * translation table walks of the processor are guaranteed to see the same + * copy of a memory location. + * + * Cache Operations: + * + * CP15 Register: ICIALLUIS + * Description: Invalidate entire instruction cache Inner Shareable. + * Register Format: Should be zero (SBZ) + * Instruction: MCR p15, 0, , c7, c1, 0 + * CP15 Register: BPIALLIS + * Description: Invalidate entire branch predictor array Inner + * Shareable. + * Register Format: Should be zero (SBZ) + * Instruction: MCR p15, 0, , c7, c1, 6 + * CP15 Register: ICIALLU + * Description: Invalidate all instruction caches to PoU. Also flushes + * branch target cache. + * Register Format: Should be zero (SBZ) + * Instruction: MCR p15, 0, , c7, c5, 0 + * CP15 Register: ICIMVAU + * Description: Invalidate instruction cache by VA to PoU. + * Register Format: VA + * Instruction: MCR p15, 0, , c7, c5, 1 + * CP15 Register: BPIALL + * Description: Invalidate entire branch predictor array. + * Register Format: Should be zero (SBZ) + * Instruction: MCR p15, 0, , c7, c5, 6 + * CP15 Register: BPIMVA + * Description: Invalidate VA from branch predictor array. + * Register Format: Should be zero (SBZ) + * Instruction: MCR p15, 0, , c7, c5, 7 + * CP15 Register: DCIMVAC + * Description: Invalidate data cache line by VA to PoC. + * Register Format: VA + * Instruction: MCR p15, 0, , c7, c6, 1 + * CP15 Register: DCISW + * Description: Invalidate data cache line by Set/Way. + * Register Format: Set/Way + * Instruction: MCR p15, 0, , c7, c6, 2 + * CP15 Register: DCCMVAC + * Description: Clean data cache line to PoC by VA. + * Register Format: VA + * Instruction: MCR p15, 0, , c7, c10, 1 + * CP15 Register: DCCSW + * Description: Clean data cache line by Set/Way. + * Register Format: Set/Way + * Instruction: MCR p15, 0, , c7, c10, 2 + * CP15 Register: DCCMVAU + * Description: Clean data or unified cache line by VA to PoU. + * Register Format: VA + * Instruction: MCR p15, 0, , c7, c11, 1 + * CP15 Register: DCCIMVAC + * Description: Clean and invalidate data cache line by VA to PoC. + * Register Format: VA + * Instruction: MCR p15, 0, , c7, c14, 1 + * CP15 Register: DCCISW + * Description: Clean and invalidate data cache line by Set/Way. + * Register Format: Set/Way + * Instruction: MCR p15, 0, , c7, c14, 2 + */ + +/* Set/way format */ + +#define CACHE_WAY_SHIFT (3) /* Bits 30-31: Way in set being accessed */ +#define CACHE_WAY_MASK (3 << CACHE_WAY_SHIFT) +#define CACHE_SET_SHIFT (5) /* Bits 5-(S+4): Way in set being accessed */ + /* For 4KB cache size: S=5 */ +#define CACHE_SET4KB_MASK (0x1f << CACHE_SET_SHIFT) + /* Bits 10-29: Reserved */ + /* For 8KB cache size: S=6 */ +#define CACHE_SET8KB_MASK (0x3f << CACHE_SET_SHIFT) + /* Bits 11-29: Reserved */ + /* For 16KB cache size: S=7 */ +#define CACHE_SET16KB_MASK (0x7f << CACHE_SET_SHIFT) + /* Bits 12-29: Reserved */ + /* For 32KB cache size: S=8 */ +#define CACHE_SET32KB_MASK (0xff << CACHE_SET_SHIFT) + /* Bits 13-29: Reserved */ + /* For 64KB cache size: S=9 */ +#define CACHE_SET64KB_MASK (0x1fff << CACHE_SET_SHIFT) + /* Bits 14-29: Reserved */ + +/* VA and SBZ format */ + +#define CACHE_SBZ_SHIFT (4) /* Bits 0-4: Should be zero (SBZ) */ +#define CACHE_SBZ_MASK (31 << TLB_SBZ_SHIFT) +#define CACHE_VA_MASK (0xfffffffe0) /* Bits 5-31: Virtual address */ + +/**************************************************************************** + * Assembly Macros + ****************************************************************************/ + +/* cp15_cache Cache Operations + * + * Usage + * + * They are performed as MCR instructions and only operate on a level 1 cache + * associated with ARM v7 processor. + * + * The supported operations are: + * + * 1. Any of these operations can be applied to any data cache or any + * unified cache. + * 2. Invalidate by MVA. Performs an invalidate of a data or unified cache + * line + * based on the address it contains. + * 3. Invalidate by set/way. Performs an invalidate of a data or unified + * cache line based on its location in the cache hierarchy. + * 4. Clean by MVA. Performs a clean of a data or unified cache line based + * on the address it contains. + * 5. Clean by set/way. Performs a clean of a data or unified cache line + * based on its location in the cache hierarchy. + * 6. Clean and Invalidate by MVA. Performs a clean and invalidate of a + * data or unified cache line based on the address it contains. + * 7. Clean and Invalidate by set/way. Performs a clean and invalidate of + * a data or unified cache line based on its location in the cache + * hierarchy. + * + * NOTE: Many of these operations are implemented as assembly language + * macros or as C inline functions in the file cache.h. The larger functions + * are implemented here as C-callable functions. + */ + +#ifdef __ASSEMBLY__ + +/**************************************************************************** + * Name: cp15_enable_dcache + * + * Description: + * Enable L1 D Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +.macro cp15_enable_dcache, tmp + mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ + orr \tmp, \tmp, #(0x1 << 2) /* Enable D cache */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ +.endm + +/**************************************************************************** + * Name: cp15_disable_dcache + * + * Description: + * Disable L1 D Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +.macro cp15_disable_dcache, tmp + mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ + bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ +.endm + +/**************************************************************************** + * Name: cp15_enable_icache + * + * Description: + * Enable L1 I Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +.macro cp15_enable_icache, tmp + mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ + orr \tmp, \tmp, #(0x1 << 12) /* Enable I cache */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ +.endm + +/**************************************************************************** + * Name: cp15_disable_icache + * + * Description: + * Disable L1 I Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +.macro cp15_disable_icache, tmp + mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ + bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */ + mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ +.endm + +/**************************************************************************** + * Name: cp15_invalidate_icache_inner_sharable + * + * Description: + * Invalidate I cache predictor array inner shareable + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +.macro cp15_invalidate_icache_inner_sharable, tmp + mov \tmp, #0 + mrc p15, 0, \tmp, c7, c1, 0 /* ICIALLUIS */ +.endm + +/**************************************************************************** + * Name: cp15_invalidate_btb_inner_sharable + * + * Description: + * Invalidate entire branch predictor array inner shareable + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +.macro cp15_invalidate_btb_inner_sharable, tmp + mov \tmp, #0 + mrc p15, 0, \tmp, c7, c1, 6 /* BPIALLIS */ +.endm + +/**************************************************************************** + * Name: cp15_invalidate_icache + * + * Description: + * Invalidate all instruction caches to PoU, also flushes branch target + * cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +.macro cp15_invalidate_icache, tmp + mov \tmp, #0 + mrc p15, 0, \tmp, c7, c5, 0 /* ICIALLU */ +.endm + +/**************************************************************************** + * Name: cp15_invalidate_icache_bymva + * + * Description: + * Invalidate instruction caches by VA to PoU + * + * Input Parameters: + * va - Register with VA format + * + * Returned Value: + * None + * + ****************************************************************************/ + +.macro cp15_invalidate_icache_bymva, va + mrc p15, 0, \va, c7, c5, 1 /* ICIMVAU */ +.endm + +/**************************************************************************** + * Name: cp15_flush_btb + * + * Description: + * Invalidate entire branch predictor array + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +.macro cp15_flush_btb, tmp + mov \tmp, #0 + mrc p15, 0, \tmp, c7, c5, 6 /* BPIALL */ +.endm + +/**************************************************************************** + * Name: cp15_flush_btb_bymva + * + * Description: + * Invalidate branch predictor array entry by MVA + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +.macro cp15_flush_btb_bymva, tmp + mov \tmp, #0 + mrc p15, 0, \tmp, c7, c5, 7 /* BPIMVA */ +.endm + +/**************************************************************************** + * Name: cp15_invalidate_dcacheline_bymva + * + * Description: + * Invalidate data cache line by VA to PoC + * + * Input Parameters: + * va - Register with VA format + * + * Returned Value: + * None + * + ****************************************************************************/ + +.macro cp15_invalidate_dcacheline_bymva, va + mrc p15, 0, \va, c7, c6, 1 /* DCIMVAC */ +.endm + +/**************************************************************************** + * Name: cp15_invalidate_dcacheline_bysetway + * + * Description: + * Invalidate data cache line by set/way + * + * Input Parameters: + * setway - Register with Set/Way format + * + * Returned Value: + * None + * + ****************************************************************************/ + +.macro cp15_invalidate_dcacheline_bysetway, setway + mrc p15, 0, \setway, c7, c6, 2 /* DCISW */ +.endm + +/**************************************************************************** + * Name: cp15_clean_dcache_bymva + * + * Description: + * Clean data cache line by MVA + * + * Input Parameters: + * va - Register with VA format + * + * Returned Value: + * None + * + ****************************************************************************/ + +.macro cp15_clean_dcache_bymva, va + mrc p15, 0, \va, c7, c10, 1 /* DCCMVAC */ +.endm + +/**************************************************************************** + * Name: cp15_clean_dcache_bysetway + * + * Description: + * Clean data cache line by Set/way + * + * Input Parameters: + * setway - Register with Set/Way format + * + * Returned Value: + * None + * + ****************************************************************************/ + +.macro cp15_clean_dcache_bysetway, setway + mrc p15, 0, \setway, c7, c10, 2 /* DCCSW */ +.endm + +/**************************************************************************** + * Name: cp15_clean_ucache_bymva + * + * Description: + * Clean unified cache line by MVA + * + * Input Parameters: + * setway - Register with VA format + * + * Returned Value: + * None + * + ****************************************************************************/ + +.macro cp15_clean_ucache_bymva, setway + mrc p15, 0, \setway, c7, c11, 1 /* DCCMVAU */ +.endm + +/**************************************************************************** + * Name: cp15_cleaninvalidate_dcacheline_bymva + * + * Description: + * Clean and invalidate data cache line by VA to PoC + * + * Input Parameters: + * va - Register with VA format + * + * Returned Value: + * None + * + ****************************************************************************/ + +.macro cp15_cleaninvalidate_dcacheline_bymva, va + mrc p15, 0, \va, c7, c14, 1 /* DCCIMVAC */ +.endm + +/**************************************************************************** + * Name: cp15_cleaninvalidate_dcacheline + * + * Description: + * Clean and Incalidate data cache line by Set/Way + * + * Input Parameters: + * setway - Register with Set/Way format + * + * Returned Value: + * None + * + ****************************************************************************/ + +.macro cp15_cleaninvalidate_dcacheline, setway + mrc p15, 0, \setway, c7, c14, 2 /* DCCISW */ +.endm + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Name: cp15_enable_dcache + * + * Description: + * Enable L1 D Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp15_enable_dcache(void) +{ + __asm__ __volatile__ + ( + "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ + "\torr r0, r0, #(1 << 2)\n" /* Enable D cache */ + "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ + : + : + : "r0", "memory" + ); +} + +/**************************************************************************** + * Name: cp15_disable_dcache + * + * Description: + * Disable L1 D Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp15_disable_dcache(void) +{ + __asm__ __volatile__ + ( + "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ + "\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */ + "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ + : + : + : "r0", "memory" + ); +} + +/**************************************************************************** + * Name: cp15_enable_icache + * + * Description: + * Enable L1 I Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp15_enable_icache(void) +{ + __asm__ __volatile__ + ( + "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ + "\torr r0, r0, #(1 << 12)\n" /* Enable I cache */ + "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ + : + : + : "r0", "memory" + ); +} + +/**************************************************************************** + * Name: cp15_disable_icache + * + * Description: + * Disable L1 I Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp15_disable_icache(void) +{ + __asm__ __volatile__ + ( + "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ + "\tbic r0, r0, #(1 << 12)\n" /* Disable I cache */ + "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ + : + : + : "r0", "memory" + ); +} + +/**************************************************************************** + * Name: cp15_invalidate_icache_inner_sharable + * + * Description: + * Invalidate I cache predictor array inner shareable + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp15_invalidate_icache_inner_sharable(void) +{ + __asm__ __volatile__ + ( + "\tmov r0, #0\n" + "\tmcr p15, 0, r0, c7, c1, 0\n" /* ICIALLUIS */ + : + : + : "r0", "memory" + ); +} + +/**************************************************************************** + * Name: cp15_invalidate_btb_inner_sharable + * + * Description: + * Invalidate entire branch predictor array inner shareable + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp15_invalidate_btb_inner_sharable(void) +{ + __asm__ __volatile__ + ( + "\tmov r0, #0\n" + "\tmcr p15, 0, r0, c7, c1, 6\n" /* BPIALLIS */ + : + : + : "r0", "memory" + ); +} + +/**************************************************************************** + * Name: cp15_invalidate_icache + * + * Description: + * Invalidate all instruction caches to PoU, also flushes branch target + * cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp15_invalidate_icache(void) +{ + __asm__ __volatile__ + ( + "\tmov r0, #0\n" + "\tmcr p15, 0, r0, c7, c5, 0\n" /* ICIALLU */ + : + : + : "r0", "memory" + ); +} + +/**************************************************************************** + * Name: cp15_invalidate_icache_bymva + * + * Description: + * Invalidate instruction caches by VA to PoU + * + * Input Parameters: + * va - 32-bit value with VA format + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp15_invalidate_icache_bymva(unsigned int va) +{ + __asm__ __volatile__ + ( + "\tmcr p15, 0, %0, c7, c5, 1\n" /* ICIMVAU */ + : + : "r" (va) + : "memory" + ); +} + +/**************************************************************************** + * Name: cp15_flush_btb + * + * Description: + * Invalidate entire branch predictor array + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp15_flush_btb(void) +{ + __asm__ __volatile__ + ( + "\tmov r0, #0\n" + "\tmcr p15, 0, r0, c7, c5, 6\n" /* BPIALL */ + : + : + : "r0", "memory" + ); +} + +/**************************************************************************** + * Name: cp15_flush_btb_bymva + * + * Description: + * Invalidate branch predictor array entry by MVA + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp15_flush_btb_bymva(void) +{ + __asm__ __volatile__ + ( + "\tmov r0, #0\n" + "\tmcr p15, 0, r0, c7, c5, 7\n" /* BPIMVA */ + : + : + : "r0", "memory" + ); +} + +/**************************************************************************** + * Name: cp15_invalidate_dcacheline_bymva + * + * Description: + * Invalidate data cache line by VA to PoC + * + * Input Parameters: + * va - 32-bit value with VA format + * + * Returned Value: + * None + * + ****************************************************************************/ + +/* Invalidate data cache line by VA to PoC */ + +static inline void cp15_invalidate_dcacheline_bymva(unsigned int va) +{ + __asm__ __volatile__ + ( + "\tmcr p15, 0, %0, c7, c6, 1\n" /* DCIMVAC */ + : + : "r" (va) + : "memory" + ); +} + +/**************************************************************************** + * Name: cp15_invalidate_dcacheline_bysetway + * + * Description: + * Invalidate data cache line by set/way + * + * Input Parameters: + * setway - 32-bit value with Set/Way format + * + * Returned Value: + * None + * + ****************************************************************************/ + +/* Invalidate data cache line by set/way */ + +static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway) +{ + __asm__ __volatile__ + ( + "\tmcr p15, 0, %0, c7, c6, 2\n" /* DCISW */ + : + : "r" (setway) + : "memory" + ); +} + +/**************************************************************************** + * Name: cp15_clean_dcache_bymva + * + * Description: + * Clean data cache line by MVA + * + * Input Parameters: + * va - 32-bit value with VA format + * + * Returned Value: + * None + * + ****************************************************************************/ + +/* Clean data cache line by MVA */ + +static inline void cp15_clean_dcache_bymva(unsigned int va) +{ + __asm__ __volatile__ + ( + "\tmcr p15, 0, %0, c7, c10, 1\n" /* DCCMVAC */ + : + : "r" (va) + : "memory" + ); +} + +/**************************************************************************** + * Name: cp15_clean_dcache_bysetway + * + * Description: + * Clean data cache line by Set/way + * + * Input Parameters: + * setway - 32-bit value with Set/Way format + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp15_clean_dcache_bysetway(unsigned int setway) +{ + __asm__ __volatile__ + ( + "\tmcr p15, 0, %0, c7, c10, 2\n" /* DCCSW */ + : + : "r" (setway) + : "memory" + ); +} + +/**************************************************************************** + * Name: cp15_clean_ucache_bymva + * + * Description: + * Clean unified cache line by MVA + * + * Input Parameters: + * setway - 32-bit value with VA format + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp15_clean_ucache_bymva(unsigned int setway) +{ + __asm__ __volatile__ + ( + "\tmcr p15, 0, %0, c7, c11, 1\n" /* DCCMVAU */ + : + : "r" (setway) + : "memory" + ); +} + +/**************************************************************************** + * Name: cp15_cleaninvalidate_dcacheline_bymva + * + * Description: + * Clean and invalidate data cache line by VA to PoC + * + * Input Parameters: + * va - 32-bit value with VA format + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va) +{ + __asm__ __volatile__ + ( + "\tmcr p15, 0, r0, c7, c14, 1\n" /* DCCIMVAC */ + : + : "r" (va) + : "memory" + ); +} + +/**************************************************************************** + * Name: cp15_cleaninvalidate_dcacheline + * + * Description: + * Clean and Incalidate data cache line by Set/Way + * + * Input Parameters: + * setway - 32-bit value with Set/Way format + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp15_cleaninvalidate_dcacheline(unsigned int setway) +{ + __asm__ __volatile__ + ( + "\tmcr p15, 0, %0, c7, c14, 2\n" /* DCCISW */ + : + : "r" (setway) + : "memory" + ); +} + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: cp15_coherent_dcache + * + * Description: + * Ensure that the I and D caches are coherent within specified region + * by cleaning the D cache (i.e., flushing the D cache contents to memory + * and invalidating the I cache). This is typically used when code has been + * written to a memory region, and will be executed. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + +void cp15_coherent_dcache(uintptr_t start, uintptr_t end); + +/**************************************************************************** + * Name: cp15_invalidate_dcache + * + * Description: + * Invalidate the data cache within the specified region; we will be + * performing a DMA operation in this region and we want to purge old data + * in the cache. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + +void cp15_invalidate_dcache(uintptr_t start, uintptr_t end); + +/**************************************************************************** + * Name: cp15_invalidate_dcache_all + * + * Description: + * Invalidate the entire contents of D cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void cp15_invalidate_dcache_all(void); + +/**************************************************************************** + * Name: cp15_clean_dcache + * + * Description: + * Clean the data cache within the specified region by flushing the + * contents of the data cache to memory. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + +void cp15_clean_dcache(uintptr_t start, uintptr_t end); + +/**************************************************************************** + * Name: cp15_clean_dcache_all + * + * Description: + * Clean the entire contents of D cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void cp15_clean_dcache_all(void); + +/**************************************************************************** + * Name: cp15_flush_dcache + * + * Description: + * Flush the data cache within the specified region by cleaning and + * invalidating the D cache. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + +void cp15_flush_dcache(uintptr_t start, uintptr_t end); + +/**************************************************************************** + * Name: cp15_flush_dcache_all + * + * Description: + * Flush the entire contents of D cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void cp15_flush_dcache_all(void); + +/**************************************************************************** + * Name: cp15_cache_size + * + * Description: + * Get cp15 cache size in byte + * + * Input Parameters: + * None + * + * Returned Value: + * Cache size in byte + * + ****************************************************************************/ + +uint32_t cp15_cache_size(void); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_ARMV7_A_CP15_CACHEOPS_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cp15_coherent_dcache.S b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cp15_coherent_dcache.S new file mode 100644 index 000000000..88c5feb4c --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cp15_coherent_dcache.S @@ -0,0 +1,138 @@ +/**************************************************************************** + * arch/arm/src/armv7-a/cp15_coherent_dcache.S + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Portions of this file derive from Atmel sample code for the SAMA5D3 + * Cortex-A5 which also has a modified BSD-style license: + * + * Copyright (c) 2012, Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor Atmel nor the names of the contributors may + * be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* References: + * + * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1, + * Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810) + * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition", + * Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM + * DDI 0406C.b (ID072512) + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "cp15.h" + + .file "cp15_coherent_dcache.S" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + .globl cp15_coherent_dcache + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + + .text + +/**************************************************************************** + * Name: cp15_coherent_dcache + * + * Description: + * Ensure that the I and D caches are coherent within specified region + * by cleaning the D cache (i.e., flushing the D cache contents to memory + * and invalidating the I cache. This is typically used when code has been + * written to a memory region, and will be executed. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + + .globl cp15_coherent_dcache + .type cp15_coherent_dcache, function + +cp15_coherent_dcache: + mrc CP15_CTR(r3) /* Read the Cache Type Register */ + lsr r3, r3, #16 /* Isolate the DMinLine field */ + and r3, r3, #0xf + mov r2, #4 + mov r2, r2, lsl r3 /* Get the cache line size in bytes */ + + sub r3, r2, #1 /* R3=Cache line size mask */ + bic r12, r0, r3 /* R12=aligned start address */ + + /* Loop, flushing each D cache line to memory */ +1: + mcr CP15_DCCMVAU(r12) /* Clean data or unified cache line by VA to PoU */ + add r12, r12, r2 /* R12=Next cache line */ + cmp r12, r1 /* Loop until all cache lines have been cleaned */ + blo 1b + + dsb + + mrc CP15_CTR(r3) /* Read the Cache Type Register */ + and r3, r3, #0xf /* Isolate the IminLine field */ + mov r2, #4 + mov r2, r2, lsl r3 /* Get the cache line size in bytes */ + + sub r3, r2, #1 /* R3=Cache line size mask */ + bic r12, r0, r3 /* R12=aligned start address */ + + /* Loop, invalidating each I cache line to memory */ +1: + mcr CP15_ICIMVAU(r12) /* Invalidate instruction cache by VA to PoU */ + add r12, r12, r2 /* R12=Next cache line */ + cmp r12, r1 /* Loop until all cache lines have been invalidated */ + blo 1b + + mov r0, #0 + mcr CP15_BPIALLIS(r0) /* Invalidate entire branch predictor array Inner Shareable */ + mcr CP15_BPIALL(r0) /* Invalidate entire branch predictor array Inner Shareable */ + + dsb + isb + bx lr + .size cp15_coherent_dcache, . - cp15_coherent_dcache + .end diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.c new file mode 100644 index 000000000..2e2be4d97 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.c @@ -0,0 +1,279 @@ +#include "l1cache.h" +#include "cp15_cacheops.h" +#include "barriers.h" + +void InvalidateL1Dcache(uintptr_t start, uintptr_t end) +{ + size_t length=end-start; + void* addr=start; + + uint32_t va; + uint32_t csidr = 0, line_size = 0; + + // get the cache line size + _ARM_MRC(15, 1, csidr, 0, 0, 0); + line_size = 1 << ((csidr & 0x7) + 4); + + // align the address with line + const void * end_addr = (const void *)((uint32_t)addr + length); + + do + { + // Clean data cache line to PoC (Point of Coherence) by va. + va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK + _ARM_MCR(15, 0, va, 7, 6, 1); + // increment addres to next line and decrement lenght + addr = (const void *) ((uint32_t)addr + line_size); + } while (addr < end_addr); + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + _ARM_DSB(); +} + +void InvalidateL1DcacheAll(void) +{ + uint32_t csid; // Cache Size ID + uint32_t wayset; // wayset parameter + int num_sets; // number of sets + int num_ways; // number of ways + + _ARM_MRC(15, 1, csid, 0, 0, 0); // Read Cache Size ID + + // Fill number of sets and number of ways from csid register This walues are decremented by 1 + num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT) + + // Invalidation all lines (all Sets in all ways) + while (num_ways >= 0) + { + num_sets = (csid >> 0x0D) & 0x7FFFu; //((csid & csid_NUMSETS_MASK) >> csid_NUMSETS_SHIFT) + while (num_sets >= 0 ) + { + wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_sets << 3SETWAY_WAY_SHIFT) + // invalidate line if we know set and way + _ARM_MCR(15, 0, wayset, 7, 6, 2); + num_sets--; + } + num_ways--; + } + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + _ARM_DSB(); +} + + +void CleanL1Dcache(uintptr_t start, uintptr_t end) +{ + void* addr=start; + size_t length=end-start; + uint32_t va; + uint32_t csidr = 0, line_size = 0; + const void * end_addr = (const void *)((uint32_t)addr + length); + + // get the cache line size + _ARM_MRC(15, 1, csidr, 0, 0, 0); + line_size = 1 << ((csidr & 0x7) + 4); + + do + { + // Clean data cache line to PoC (Point of Coherence) by va. + va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK + _ARM_MCR(15, 0, va, 7, 10, 1); + + // increment addres to next line and decrement lenght + addr = (const void *) ((uint32_t)addr + line_size); + } while (addr < end_addr); + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + _ARM_DSB(); +} + +void CleanL1DcacheAll(void) +{ + uint32_t csid; // Cache Size ID + uint32_t wayset; // wayset parameter + int num_sets; // number of sets + int num_ways; // number of ways + + _ARM_MRC(15, 1, csid, 0, 0, 0); // Read Cache Size ID + + // Fill number of sets and number of ways from csid register This walues are decremented by 1 + num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT`) + while (num_ways >= 0) + { + num_sets = (csid >> 0x0D) & 0x7FFFu; //((csid & csid_NUMSETS_MASK) >> csid_NUMSETS_SHIFT ) + while (num_sets >= 0 ) + { + wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_ways << 3SETWAY_WAY_SHIFT) + // FLUSH (clean) line if we know set and way + _ARM_MCR(15, 0, wayset, 7, 10, 2); + num_sets--; + } + num_ways--; + } + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + _ARM_DSB(); +} + +void FlushL1Dcache(uintptr_t start, uintptr_t end) +{ + void* addr=start; + size_t length=end-start; + uint32_t va; + uint32_t csidr = 0, line_size = 0; + const void * end_addr = (const void *)((uint32_t)end); + + // get the cache line size + _ARM_MRC(15, 1, csidr, 0, 0, 0); + line_size = 1 << ((csidr & 0x7) + 4); + + do + { + // Clean data cache line to PoC (Point of Coherence) by va. + va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK + _ARM_MCR(15, 0, va, 7, 14, 1); + + // increment addres to next line and decrement lenght + addr = (const void *) ((uint32_t)addr + line_size); + } while (addr < end_addr); + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + _ARM_DSB(); +} + +void FlushL1DcacheAll(void) +{ + uint32_t csid; // Cache Size ID + uint32_t wayset; // wayset parameter + int num_sets; // number of sets + int num_ways; // number of ways + + _ARM_MRC(15, 1, csid, 0, 0, 0); // Read Cache Size ID + + // Fill number of sets and number of ways from csid register This walues are decremented by 1 + num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT`) + while (num_ways >= 0) + { + num_sets = (csid >> 0x0D) & 0x7FFFu; //((csid & csid_NUMSETS_MASK) >> csid_NUMSETS_SHIFT ) + while (num_sets >= 0 ) + { + wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_ways << 3SETWAY_WAY_SHIFT) + // FLUSH (clean) line if we know set and way + _ARM_MCR(15, 0, wayset, 7, 14, 2); + num_sets--; + } + num_ways--; + } + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + _ARM_DSB(); +} + +void InvalidateL1IcacheAll() +{ + uint32_t SBZ = 0x0u; + + _ARM_MCR(15, 0, SBZ, 7, 5, 0); + + // synchronize context on this processor + _ARM_ISB(); +} + +void InvalidateL1Icache(uintptr_t start, uintptr_t end) +{ + void* addr=start; + uint32_t va; + uint32_t csidr = 0, line_size = 0; + const void * end_addr = (const void *)((uint32_t)end); + + // get the cache line size + _ARM_MRC(15, 1, csidr, 0, 0, 0); + line_size = 1 << ((csidr & 0x7) + 4); + + do + { + // Clean data cache line to PoC (Point of Coherence) by va. + va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK + _ARM_MCR(15, 0, va, 7, 5, 1); + // increment addres to next line and decrement lenght + addr = (const void *) ((uint32_t)addr + line_size); + } while (addr < end_addr); + + // synchronize context on this processor + _ARM_ISB(); +} + +void EnableL1Icache(void) +{ + uint32_t sctlr ;// System Control Register + + // read sctlr + _ARM_MRC(15, 0, sctlr, 1, 0, 0); + + // ignore the operation if I is enabled already + if(!(sctlr & BM_SCTLR_I)) + { + // set I bit (instruction caching enable) + sctlr |= BM_SCTLR_I; + + // write modified sctlr + _ARM_MCR(15, 0, sctlr, 1, 0, 0); + + // synchronize context on this processor + _ARM_ISB(); + } +} + +void DisableL1Icache() +{ + uint32_t sctlr ;// System Control Register + + // read sctlr + _ARM_MRC(15, 0, sctlr, 1, 0, 0); + + // Clear I bit (instruction caching enable) + sctlr &= ~BM_SCTLR_I; + + // write modified sctlr + _ARM_MCR(15, 0, sctlr, 1, 0, 0); + + // synchronize context on this processor + _ARM_ISB(); +} + +void EnableL1Dcache() +{ + uint32_t sctlr; // System Control Register + + // read sctlr + _ARM_MRC(15, 0, sctlr, 1, 0, 0); + + if (!(sctlr & BM_SCTLR_C)) + { + // set C bit (data caching enable) + sctlr |= BM_SCTLR_C; + + // write modified sctlr + _ARM_MCR(15, 0, sctlr, 1, 0, 0); + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + _ARM_DSB(); + } +} + +void DisableL1Dcache() +{ + uint32_t sctlr; // System Control Register + + // read sctlr + _ARM_MRC(15, 0, sctlr, 1, 0, 0); + + // set C bit (data caching enable) + sctlr &= ~BM_SCTLR_C; + + // write modified sctlr + _ARM_MCR(15, 0, sctlr, 1, 0, 0); + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + _ARM_DSB(); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.h new file mode 100644 index 000000000..757157cae --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.h @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2022 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file l1cache.c + * @brief PLC inovance am401 app + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.8.10 + */ + +#include +#include +#include "cortex_a9.h" + +/* Terms: + * 1) Point of coherency (PoC) + * The PoC is the point at which all agents that can access memory are + * guaranteed to see the same copy of a memory location + * 2) Point of unification (PoU) + * The PoU is the point by which the instruction and data caches and the + * translation table walks of the processor are guaranteed to see the same + * copy of a memory location. + * + * L1 Cache Operations: + * + * CP15 Register: ICIALLUIS + * Description: Invalidate entire instruction cache Inner Shareable. + * Register Format: Should be zero (SBZ) + * Instruction: MCR p15, 0, , c7, c1, 0 + * CP15 Register: BPIALLIS + * Description: Invalidate entire branch predictor array Inner + * Shareable. + * Register Format: Should be zero (SBZ) + * Instruction: MCR p15, 0, , c7, c1, 6 + * CP15 Register: ICIALLU + * Description: Invalidate all instruction caches to PoU. Also flushes + * branch target cache. + * Register Format: Should be zero (SBZ) + * Instruction: MCR p15, 0, , c7, c5, 0 + * CP15 Register: ICIMVAU + * Description: Invalidate instruction cache by VA to PoU. + * Register Format: VA + * Instruction: MCR p15, 0, , c7, c5, 1 + * CP15 Register: CP15ISB + * Description: Instruction Synchronization Barrier operation + * NOTE: Deprecated and no longer documented + * Instruction: MCR p15, 0, , c7, c5, 4 + * CP15 Register: BPIALL + * Description: Invalidate entire branch predictor array. + * Register Format: Should be zero (SBZ) + * Instruction: MCR p15, 0, , c7, c5, 6 + * CP15 Register: BPIMVA + * Description: Invalidate VA from branch predictor array. + * Register Format: Should be zero (SBZ) + * Instruction: MCR p15, 0, , c7, c5, 7 + * CP15 Register: DCIMVAC + * Description: Invalidate data cache line by VA to PoC. + * Register Format: VA + * Instruction: MCR p15, 0, , c7, c6, 1 + * CP15 Register: DCISW + * Description: Invalidate data cache line by Set/Way. + * Register Format: Set/Way + * Instruction: MCR p15, 0, , c7, c6, 2 + * CP15 Register: DCCMVAC + * Description: Clean data cache line to PoC by VA. + * Register Format: VA + * Instruction: MCR p15, 0, , c7, c10, 1 + * CP15 Register: DCCSW + * Description: Clean data cache line by Set/Way. + * Register Format: Set/Way + * Instruction: MCR p15, 0, , c7, c10, 2 + * CP15 Register: CP15DSB + * Description: Data Synchronization Barrier operation + * NOTE: Deprecated and no longer documented + * Instruction: MCR p15, 0, , c7, c10, 4 + * CP15 Register: CP15DMB + * Description: Data Memory Barrier operation + * NOTE: Deprecated and no longer documented + * Instruction: MCR p15, 0, , c7, c10, 5 + * CP15 Register: DCCMVAU + * Description: Clean data or unified cache line by VA to PoU. + * Register Format: VA + * Instruction: MCR p15, 0, , c7, c11, 1 + * CP15 Register: DCCIMVAC + * Description: Clean and invalidate data cache line by VA to PoC. + * Register Format: VA + * Instruction: MCR p15, 0, , c7, c14, 1 + * CP15 Register: DCCISW + * Description: Clean and invalidate data cache line by Set/Way. + * Register Format: Set/Way + * Instruction: MCR p15, 0, , c7, c14, 2 + */ + +#define BM_SCTLR_I (1 << 12) //!< Instruction cache enable +#define BM_SCTLR_C (1 << 2) //!< Data cache enable + +void InvalidateL1Dcache(uintptr_t start, uintptr_t end); + +void InvalidateL1DcacheAll(void); + + +void CleanL1Dcache(uintptr_t start, uintptr_t end); + +void CleanL1DcacheAll(void); + +void FlushL1Dcache(uintptr_t start, uintptr_t end); + +void FlushL1DcacheAll(void); + + +void InvalidateL1IcacheAll(void); + +void InvalidateL1Icache(uintptr_t start, uintptr_t end); + +void EnableL1Icache(void); +void DisableL1Icache(); + +void EnableL1Dcache(); + +void DisableL1Dcache(); \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc.h new file mode 100644 index 000000000..5b858e3a3 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc.h @@ -0,0 +1,243 @@ +/**************************************************************************** + * arch/arm/src/armv7-a/l2cc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_ARMV7_A_L2CC_H +#define __ARCH_ARM_SRC_ARMV7_A_L2CC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#define CONFIG_ARCH_L2CACHE + +#ifdef CONFIG_ARCH_L2CACHE + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_l2ccinitialize + * + * Description: + * One time configuration of the L2 cache. The L2 cache will be enabled + * upon return. + * + * Input Parameters: + * None. The L2 cache configuration is controlled by configuration + * settings. + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if 0 /* Prototyped in arm_internal.h */ +void arm_l2ccinitialize(void); +#endif + +/**************************************************************************** + * Name: l2cc_enable + * + * Description: + * Re-enable the L2CC-P310 L2 cache by setting the enable bit in the + * Control Register (CR) + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void EnableL2Cache(void); + +/**************************************************************************** + * Name: l2cc_disable + * + * Description: + * Disable the L2 cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void DisableL2Cache(void); + +/**************************************************************************** + * Name: l2cc_sync + * + * Description: + * Drain the L2 cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void SyncL2Cache(void); + +/**************************************************************************** + * Name: l2cc_invalidate_all + * + * Description: + * Invalidate the entire L2 cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void InvalidateL2CacheAll(void); + +/**************************************************************************** + * Name: l2cc_invalidate + * + * Description: + * Invalidate a range of addresses in the L2 cache + * + * Input Parameters: + * startaddr - The first address to be invalidated + * endaddr - The last address to be invalidated + * + * Returned Value: + * None + * + ****************************************************************************/ + +void InvalidateL2Cache(uintptr_t startaddr, uintptr_t endaddr); + +/**************************************************************************** + * Name: l2cc_clean_all + * + * Description: + * Clean the entire L2 cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void CleanL2CacheAll(void); + +/**************************************************************************** + * Name: l2cc_clean + * + * Description: + * Clean a range of address within the L2 cache. + * + * Input Parameters: + * startaddr - The first address to be cleaned + * endaddr - The last address to be cleaned + * + * Returned Value: + * None + * + ****************************************************************************/ + +void CleanL2Cache(uintptr_t startaddr, uintptr_t endaddr); + +/**************************************************************************** + * Name: l2cc_flush_all + * + * Description: + * Flush the entire L2 cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void FlushL2CacheAll(void); + +/**************************************************************************** + * Name: l2cc_flush + * + * Description: + * Flush a range of address within the L2 cache. + * + * Input Parameters: + * startaddr - The first address to be flushed + * endaddr - The last address to be flushed + * + * Returned Value: + * None + * + ****************************************************************************/ + +void FlushL2Cache(uint32_t startaddr, uint32_t endaddr); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#else /* CONFIG_ARCH_L2CACHE */ + /* Provide simple definitions to concentrate the inline conditional + * compilation in one place. + */ + +# define EnableL2Cache() +# define DisableL2Cache() +# define SyncL2Cache() +# define InvalidateL2CacheAll() +# define InvalidateL2Cache(s,e) +# define CleanL2CacheAll() +# define CleanL2Cache(s,e) +# define FlushL2CacheAll() +# define FlushL2Cache(s,e) + +#endif /* CONFIG_ARCH_L2CACHE */ +#endif /* __ARCH_ARM_SRC_ARMV7_A_L2CC_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.c new file mode 100644 index 000000000..0bc4712a1 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.c @@ -0,0 +1,866 @@ +/* + * Copyright (c) 2022 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file l2cc_pl310.c + * @brief PLC inovance am401 app + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.8.10 + */ + + + +#include +#include +#include + + +#include "l2cc.h" +#include "l2cc_pl310.h" + + +#define CONFIG_ARMV7A_ASSOCIATIVITY_8WAY +#define CONFIG_ARMV7A_WAYSIZE_16KB + +#define getreg8(a) (*(volatile uint8_t *)(a)) +#define putreg8(v,a) (*(volatile uint8_t *)(a) = (v)) +#define getreg16(a) (*(volatile uint16_t *)(a)) +#define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) +#define getreg32(a) (*(volatile uint32_t *)(a)) +#define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) + +#ifdef CONFIG_HAVE_FILENAME +# define PANIC() _assert(__FILE__, __LINE__) +#else +# define PANIC() _assert("unknown", 0) +#endif + +#define ASSERT(f) do { if (!(f)) PANIC(); } while (0) +#define VERIFY(f) do { if ((f) < 0) PANIC(); } while (0) + +#ifdef CONFIG_DEBUG_ASSERTIONS +# define DEBUGPANIC() PANIC() +# define DEBUGASSERT(f) ASSERT(f) +# define DEBUGVERIFY(f) VERIFY(f) +#else +# define DEBUGPANIC() +# define DEBUGASSERT(f) ((void)(1 || (f))) +# define DEBUGVERIFY(f) ((void)(f)) +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Number of ways depends on ARM configuration */ + +#if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY) +# define PL310_NWAYS 8 +# define PL310_WAY_MASK 0x000000ff +#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY) +# define PL310_NWAYS 16 +# define PL310_WAY_MASK 0x0000ffff +#else +# error "Number of ways not selected" +#endif + +/* The size of one depends on ARM configuration */ + +#if defined(CONFIG_ARMV7A_WAYSIZE_16KB) +# define PL310_WAYSIZE (16 * 1024) +#elif defined(CONFIG_ARMV7A_WAYSIZE_32KB) +# define PL310_WAYSIZE (32 * 1024) +#elif defined(CONFIG_ARMV7A_WAYSIZE_64KB) +# define PL310_WAYSIZE (64 * 1024) +#elif defined(CONFIG_ARMV7A_WAYSIZE_128KB) +# define PL310_WAYSIZE (128 * 1024) +#elif defined(CONFIG_ARMV7A_WAYSIZE_256KB) +# define PL310_WAYSIZE (256 * 1024) +#elif defined(CONFIG_ARMV7A_WAYSIZE_512KB) +# define PL310_WAYSIZE (512 * 1024) +#else +# error "Way size not selected" +#endif + +/* The size of the cache is then the product of the number of ways times + * the size of each way. + */ + +#define PL310_CACHE_SIZE (PL310_NWAYS * PL310_WAYSIZE) + +/* Use for aligning addresses to a cache line boundary */ + +#define PL310_CACHE_LINE_MASK (PL310_CACHE_LINE_SIZE - 1) + +/* Configurable options + * + * REVISIT: Currently there are not configuration options. All values + * are just set to the default. + */ + +/* Bit 0: Full line zero enable + * + * Default: 0=Full line of write zero behavior disabled + */ + +#define L2CC_ACR_FLZE_CONFIG (0) /* 0=Full line of write zero behavior disabled */ + +/* Bit 10: High Priority for SO and Dev Reads Enable + * + * Default: 0=Strongly Ordered and Device reads have lower priority than + * cacheable accesses + */ + +#define L2CC_ACR_HPSO_CONFIG (0) /* 0=Have lower priority than cache */ + +/* Bit 11: Store Buffer Device Limitation Enable + * + * Default: 0=Store buffer device limitation disabled + */ + +#define L2CC_ACR_SBDLE_CONFIG (0) /* 0=Store buffer device limitation disabled */ + +/* Bit 12: Exclusive Cache Configuration + * + * Default: 0=Disabled + */ + +#define L2CC_ACR_EXCC_CONFIG (0) /* 0=Disabled */ + +/* Bit 13: Shared Attribute Invalidate Enable + * + * Default: 0=Shared invalidate behavior disabled + */ + +#define L2CC_ACR_SAIE_CONFIG (0) /* 0=Shared invalidate behavior disabled */ + +/* Bit 20: Event Monitor Bus Enable + * + * Default: 0=Disabled + */ + +#define L2CC_ACR_EMBEN_CONFIG (0) /* 0=Disabled */ + +/* Bit 21: Parity Enable + * + * Default: 0=Disabled + */ + +#define L2CC_ACR_PEN_CONFIG (0) /* 0=Disabled */ + +/* Bit 22: Shared Attribute Override Enable + * + * Default: 0=Treats shared accesses as specified in the TRM + */ + +#define L2CC_ACR_SAOEN_CONFIG (0) /* 0=As specified in the TRM */ + +/* Bits 23-24: Force Write Allocate + * + * Default: 0=Use AWCACHE attributes for WA + */ + +#define L2CC_ACR_FWA_CONFIG L2CC_ACR_FWA_AWCACHE /* Use AWCACHE attributes for WA */ + +/* Bit 25: Cache Replacement Policy + * + * Default: 1=Round robin replacement policy + */ + +#define L2CC_ACR_CRPOL_CONFIG L2CC_ACR_CRPOL /* 1=Round robin replacement policy */ + +/* Bit 26: Non-Secure Lockdown Enable + * + * Default: 0=Lockdown registers cannot be modified using non-secure accesses + */ + +#define L2CC_ACR_NSLEN_CONFIG (0) /* 0=Secure access only */ + +/* Bit 27: Non-Secure Interrupt Access Control + * + * Default: 0=Interrupt Clear and Mask can only be modified or read with + * secure accesses + */ + +#define L2CC_ACR_NSIAC_CONFIG (0) /* 0=Secure access only */ + +/* Bit 28: Data Prefetch Enable + * + * Default: 0=Data prefetching disabled + */ + +#define L2CC_ACR_DPEN_CONFIG (0) /* 0=Data prefetching disabled */ + +/* Bit 29: Instruction Prefetch Enable + * + * Default: 0=Instruction prefetching disabled + */ + +#define L2CC_ACR_IPEN_CONFIG (0) /* 0=Instruction prefetching disabled */ + +/* Bit 30: Early BRESP enable + * + * Default: 0=Early BRESP disabled + */ + +#define L2CC_ACR_EBRESP_CONFIG (0) /* 0=Early BRESP disabled */ + +#define L2CC_ACR_CONFIG \ + (L2CC_ACR_FLZE_CONFIG | L2CC_ACR_HPSO_CONFIG | L2CC_ACR_SBDLE_CONFIG | \ + L2CC_ACR_EXCC_CONFIG | L2CC_ACR_SAIE_CONFIG | L2CC_ACR_EMBEN_CONFIG | \ + L2CC_ACR_PEN_CONFIG | L2CC_ACR_SAOEN_CONFIG | L2CC_ACR_FWA_CONFIG | \ + L2CC_ACR_CRPOL_CONFIG | L2CC_ACR_NSLEN_CONFIG | L2CC_ACR_NSIAC_CONFIG | \ + L2CC_ACR_DPEN_CONFIG | L2CC_ACR_IPEN_CONFIG | L2CC_ACR_EBRESP_CONFIG) + +#define L2CC_ACR_ALLCONFIGS (0x7f303c01) +#define L2CC_ACR_CONFIGMASK (L2CC_ACR_SBZ | L2CC_ACR_ALLCONFIGS) + +/* Filter end address */ + +#define CONFIG_PL310_FLEND (CONFIG_PL310_FLSTRT + CONFIG_PL310_FLSIZE) + +/* Block size. Used to break up long operations so that interrupts are not + * disabled for a long time. + */ + +#define PL310_GULP_SIZE 4096 + +/* Misc commoly defined and re-defined things */ + +#ifndef MIN +# define MIN(a,b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef MAX +# define MAX(a,b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifndef OK +# define OK 0 +#endif + +/* Data synchronization barrier */ + +#define dsb(a) __asm__ __volatile__ ("dsb " #a : : : "memory") + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pl310_flush_all + * + * Description: + * Flush all ways using the Clean Invalidate Way Register (CIWR). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void pl310_flush_all(void) +{ + /* Flush all ways by writing the set of ways to be cleaned to the Clean + * Invalidate Way Register (CIWR). + */ + + putreg32(PL310_WAY_MASK, L2CC_CIWR); + + /* Wait for cache operation by way to complete */ + + while ((getreg32(L2CC_CIWR) & PL310_WAY_MASK) != 0); + + /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and + * EB, are empty. + */ + + putreg32(0, L2CC_CSR); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_l2ccinitialize + * + * Description: + * One time configuration of the L2 cache. The L2 cache will be enabled + * upon return. + * + * Input Parameters: + * None. The L2 cache configuration is controlled by configuration + * settings. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void arm_l2ccinitialize(void) +{ + uint32_t regval; + int i; + + /* Make sure that this is a PL310 cache, version r3p2. + * + * REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which + * is r3p2, but the chip that I have actually* reports 0x410000C9 which + * is some later revision. + */ + + /* DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) == + * L2CC_IDR_REV_R3P2); + */ + + /* Make sure that actual cache configuration agrees with the configured + * cache configuration. + */ + +#if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY) + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 0); +#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY) + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == L2CC_ACR_ASS); +#else +# error No associativity selected +#endif + +#if defined(CONFIG_ARMV7A_WAYSIZE_16KB) + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_16KB); +#elif defined(CONFIG_ARMV7A_WAYSIZE_32KB) + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_32KB); +#elif defined(CONFIG_ARMV7A_WAYSIZE_64KB) + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_64KB); +#elif defined(CONFIG_ARMV7A_WAYSIZE_128KB) + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_128KB); +#elif defined(CONFIG_ARMV7A_WAYSIZE_256KB) + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_256KB); +#elif defined(CONFIG_ARMV7A_WAYSIZE_512KB) + DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == + L2CC_ACR_WAYSIZE_512KB); +#else +# error No way size selected +#endif + + /* L2 configuration can only be changed if the cache is disabled, + * + * NOTE: This register access will fail if we are not in secure more. + */ + + if ((getreg32(L2CC_CR) & L2CC_CR_L2CEN) == 0) + { +#if defined(CONFIG_PL310_TRCR_TSETLAT) && defined(CONFIG_PL310_TRCR_TRDLAT) && \ + defined(CONFIG_PL310_TRCR_TWRLAT) + /* Configure Tag RAM control */ + + regval = ((CONFIG_PL310_TRCR_TSETLAT - 1) << L2CC_TRCR_TSETLAT_SHIFT) + ((CONFIG_PL310_TRCR_TRDLAT - 1) << L2CC_TRCR_TRDLAT_SHIFT) | + ((CONFIG_PL310_TRCR_TWRLAT - 1) << L2CC_TRCR_TWRLAT_SHIFT); + putreg32(regval, L2CC_TRCR); +#endif + +#if defined(CONFIG_PL310_DRCR_DSETLAT) && defined(CONFIG_PL310_DRCR_DRDLAT) && \ + defined(CONFIG_PL310_DRCR_DWRLAT) + /* Configure Data RAM control */ + + regval = ((CONFIG_PL310_DRCR_DSETLAT - 1) << L2CC_DRCR_DSETLAT_SHIFT) | + ((CONFIG_PL310_DRCR_DRDLAT - 1) << L2CC_DRCR_DRDLAT_SHIFT) | + ((CONFIG_PL310_DRCR_DWRLAT - 1) << L2CC_DRCR_DWRLAT_SHIFT); + putreg32(regval, L2CC_DRCR); +#endif + +#ifdef PL310_ADDRESS_FILTERING +#if defined(CONFIG_PL310_FLSTRT) && defined(CONFIG_PL310_FLSIZE) + /* Configure the address filter */ + + regval = (CONFIG_PL310_FLEND + ~L2CC_FLEND_MASK) & L2CC_FLEND_MASK; + putreg32(regval, L2CC_FLEND); + + regval = (CONFIG_PL310_FLSTRT & L2CC_FLSTRT_MASK) | L2CC_FLSTRT_ENABLE; + putreg32(regval | L2X0_ADDR_FILTER_EN, L2CC_FLSTRT); +#endif +#endif + + /* Make sure that the memory is not locked down */ + + for (i = 0; i < PL310_NLOCKREGS; i++) + { + putreg32(0, L2CC_DLKR(i)); + putreg32(0, L2CC_ILKR(i)); + } + + /* Configure the cache properties */ + + regval = getreg32(L2CC_ACR); + regval &= ~L2CC_ACR_CONFIGMASK; + regval |= L2CC_ACR_CONFIG; + putreg32(regval, L2CC_ACR); + + /* Invalidate and enable the cache */ + + InvalidateL2CacheAll(); + putreg32(L2CC_CR_L2CEN, L2CC_CR); + } + + sinfo("(%d ways) * (%d bytes/way) = %d bytes\n", + PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE); +} + +/**************************************************************************** + * Name: l2cc_enable + * + * Description: + * Re-enable the L2CC-P310 L2 cache by setting the enable bit in the + * Control Register (CR) + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void EnableL2Cache(void) +{ + /* Invalidate and enable the cache (must be disabled to do this!) */ + InvalidateL2CacheAll(); + putreg32(L2CC_CR_L2CEN, L2CC_CR); + +} + +/**************************************************************************** + * Name: l2cc_disable + * + * Description: + * Disable the L2CC-P310 L2 cache by clearing the Control Register (CR) + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void DisableL2Cache(void) +{ + + pl310_flush_all(); + + /* Disable the L2CC-P310 L2 cache by clearing the Control Register (CR) */ + + putreg32(0, L2CC_CR); + dsb(); + +} + +/**************************************************************************** + * Name: l2cc_sync + * + * Description: + * Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and + * EB, are empty. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void SyncL2Cache(void) +{ + + putreg32(0, L2CC_CSR); + +} + +/**************************************************************************** + * Name: l2cc_invalidate_all + * + * Description: + * Invalidate all ways using the Invalidate Way Register (IWR). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void InvalidateL2CacheAll(void) +{ + + uint32_t regval; + + /* Invalidate all ways */ + + + /* Disable the L2 cache while we invalidate it */ + + regval = getreg32(L2CC_CR); + DisableL2Cache(); + + /* Invalidate all ways by writing the bit mask of ways to be invalidated + * the Invalidate Way Register (IWR). + */ + + putreg32(PL310_WAY_MASK, L2CC_IWR); + + /* Wait for cache operation by way to complete */ + + while ((getreg32(L2CC_IWR) & PL310_WAY_MASK) != 0); + + /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and + * EB, are empty. + */ + + putreg32(0, L2CC_CSR); + + /* Then re-enable the L2 cache if it was enabled before */ + + putreg32(regval, L2CC_CR); + +} + +/**************************************************************************** + * Name: l2cc_invalidate + * + * Description: + * Invalidate a range of addresses by writing to the Invalidate Physical + * Address Line Register (IPALR) repeatedly. + * + * Input Parameters: + * startaddr - The first address to be invalidated + * endaddr - The last address to be invalidated + * + * Returned Value: + * None + * + ****************************************************************************/ + +void InvalidateL2Cache(uintptr_t startaddr, uintptr_t endaddr) +{ + uintptr_t invalsize; + uintptr_t gulpend; + + + /* Check if the start address is aligned with a cacheline */ + + + if ((startaddr & PL310_CACHE_LINE_MASK) != 0) + { + /* No.. align down and flush the cache line by writing the address to + * the Clean Invalidate Physical Address Line Register (CIPALR). + */ + + startaddr &= ~PL310_CACHE_LINE_MASK; + putreg32(startaddr, L2CC_CIPALR); + + /* Then start invalidating at the next cache line */ + + startaddr += PL310_CACHE_LINE_SIZE; + } + + /* Check if the end address is aligned with a cache line */ + + if ((endaddr & PL310_CACHE_LINE_MASK) != 0) + { + /* No.. align down and flush cache line by writing the address to + * the Clean Invalidate Physical Address Line Register (CIPALR). + */ + + endaddr &= ~PL310_CACHE_LINE_MASK; + putreg32(endaddr, L2CC_CIPALR); + } + + + + /* Loop, invalidated the address range by cache line. Interrupts are re- + * enabled momentarily every PL310_GULP_SIZE bytes. + */ + + while (startaddr < endaddr) + { + /* Get the size of the next gulp of cache lines to invalidate. We do + * this in small chunks so that we do not have to keep interrupts + * disabled throughout the whole flush. + */ + + invalsize = endaddr - startaddr; + gulpend = startaddr + MIN(invalsize, PL310_GULP_SIZE); + + /* Disable interrupts and invalidate the gulp */ + + + while (startaddr < gulpend) + { + /* Invalidate the cache line by writing the address to the + * Invalidate Physical Address Line Register (IPALR). + */ + + putreg32(startaddr, L2CC_IPALR); + + /* Start of the next cache line */ + + startaddr += PL310_CACHE_LINE_SIZE; + } + + /* Enable interrupts momentarily */ + + + } + + /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and + * EB, are empty. + */ + + + putreg32(0, L2CC_CSR); + +} + +/**************************************************************************** + * Name: l2cc_clean_all + * + * Description: + * Clean all ways by using the Clean Ways Register (CWR). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void CleanL2CacheAll(void) +{ + + + + putreg32(PL310_WAY_MASK, L2CC_CWR); + + /* Wait for cache operation by way to complete */ + + while ((getreg32(L2CC_CWR) & PL310_WAY_MASK) != 0); + + /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and + * EB, are empty. + */ + + putreg32(0, L2CC_CSR); + +} + +/**************************************************************************** + * Name: l2cc_clean + * + * Description: + * Clean the cache line over a range of addresses uing the Clean Physical + * Address Line Register (CPALR) repeatedly. + * + * Input Parameters: + * startaddr - The first address to be cleaned + * endaddr - The last address to be cleaned + * + * Returned Value: + * None + * + ****************************************************************************/ + +void CleanL2Cache(uintptr_t startaddr, uintptr_t endaddr) +{ + uintptr_t cleansize; + uintptr_t gulpend; + + + /* If the range of addresses to clean is as large or larger the L2 cache, + * then just clean the whole thing. + */ + + cleansize = endaddr - startaddr; + if (cleansize >= PL310_CACHE_SIZE) + { + CleanL2CacheAll(); + return; + } + + /* Align the starting address to a cache line boundary */ + + startaddr &= ~PL310_CACHE_LINE_MASK; + + /* Clean the L2 cache by cache line, enabling interrupts momentarily + * every PL310_GULP_SIZE bytes. + */ + + while (startaddr < endaddr) + { + /* Get the size of the next gulp of cache lines to flush. We do + * this in small chunks so that we do not have to keep interrupts + * disabled throughout the whole flush. + */ + + cleansize = endaddr - startaddr; + gulpend = startaddr + MIN(cleansize, PL310_GULP_SIZE); + + /* Disable interrupts and clean the gulp */ + + + while (startaddr < gulpend) + { + /* Clean the cache line by writing the address to the Clean + * Physical Address Line Register (CPALR). + */ + + putreg32(startaddr, L2CC_CPALR); + + /* Start of the next cache line */ + + startaddr += PL310_CACHE_LINE_SIZE; + } + + /* Enable interrupts momentarily */ + + + } + + /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and + * EB, are empty. + */ + + + putreg32(0, L2CC_CSR); + +} + +/**************************************************************************** + * Name: l2cc_flush_all + * + * Description: + * Flush all ways using the Clean Invalidate Way Register (CIWR). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void FlushL2CacheAll(void) +{ + + + /* Flush all ways using the Clean Invalidate Way Register (CIWR). */ + + + pl310_flush_all(); + +} + +/**************************************************************************** + * Name: l2cc_flush + * + * Description: + * Flush a range of address by using the Clean Invalidate Physical Address + * Line Register (CIPALR) repeatedly. + * + * Input Parameters: + * startaddr - The first address to be flushed + * endaddr - The last address to be flushed + * + * Returned Value: + * None + * + ****************************************************************************/ + +void FlushL2Cache(uint32_t startaddr, uint32_t endaddr) +{ + uintptr_t flushsize; + uintptr_t gulpend; + + + /* If the range of addresses to flush is as large or larger the L2 cache, + * then just flush the whole thing. + */ + + flushsize = endaddr - startaddr; + if (flushsize >= PL310_CACHE_SIZE) + { + l2cc_flush_all(); + return; + } + + /* Align the starting address to a cache line boundary */ + + startaddr &= ~PL310_CACHE_LINE_MASK; + + /* Flush the L2 cache by cache line, enabling interrupts momentarily + * every PL310_GULP_SIZE bytes. + */ + + while (startaddr < endaddr) + { + /* Get the size of the next gulp of cache lines to flush. We do + * this in small chunks so that we do not have to keep interrupts + * disabled throughout the whole flush. + */ + + flushsize = endaddr - startaddr; + gulpend = startaddr + MIN(flushsize, PL310_GULP_SIZE); + + /* Disable interrupts and flush the gulp */ + + + while (startaddr < gulpend) + { + /* Flush the cache line by writing the address to the Clean + * Invalidate Physical Address Line Register (CIPALR). + */ + + putreg32(startaddr, L2CC_CIPALR); + + /* Start of the next cache line */ + + startaddr += PL310_CACHE_LINE_SIZE; + } + + /* Enable interrupts momentarily */ + + + } + + /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and + * EB, are empty. + */ + + + putreg32(0, L2CC_CSR); + +} + + diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.h new file mode 100644 index 000000000..e5c5c1225 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.h @@ -0,0 +1,483 @@ +/**************************************************************************** + * arch/arm/src/armv7-a/l2cc_pl310.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Reference: "CoreLink� Level 2 Cache Controller L2C-310", Revision r3p2, + * Technical Reference Manual, ARM DDI 0246F (ID011711), ARM + */ + +#ifndef __ARCH_ARM_SRC_ARMV7_A_L2CC_PL310_H +#define __ARCH_ARM_SRC_ARMV7_A_L2CC_PL310_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + + + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* General Definitions ******************************************************/ + +#define PL310_CACHE_LINE_SIZE 32 + +#ifdef CONFIG_PL310_LOCKDOWN_BY_MASTER +# define PL310_NLOCKREGS 8 +#else +# define PL310_NLOCKREGS 1 +#endif + +/* L2CC Register Offsets ****************************************************/ +#define IMX_ARMMP_PSECTION 0x00a00000 /* 00a00000-00afffff 8 KB ARM MP */ +# define IMX_ARMMP_VSECTION IMX_ARMMP_PSECTION /* 8 KB ARM MP */ +#define IMX_PL310_OFFSET 0x00002000 /* 00002000-00002fff 4 KB PL310 (L2 Cache controller) */ +#define IMX_PL310_VBASE (IMX_ARMMP_VSECTION+IMX_PL310_OFFSET) +#define L2CC_VBASE IMX_PL310_VBASE + + +#define L2CC_IDR_OFFSET 0x0000 /* Cache ID Register */ +#define L2CC_TYPR_OFFSET 0x0004 /* Cache Type Register */ +#define L2CC_CR_OFFSET 0x0100 /* Control Register */ +#define L2CC_ACR_OFFSET 0x0104 /* Auxiliary Control Register */ +#define L2CC_TRCR_OFFSET 0x0108 /* Tag RAM Control Register */ +#define L2CC_DRCR_OFFSET 0x010c /* Data RAM Control Register */ + /* 0x0110-0x01fc Reserved */ +#define L2CC_ECR_OFFSET 0x0200 /* Event Counter Control Register */ +#define L2CC_ECFGR1_OFFSET 0x0204 /* Event Counter 1 Configuration Register */ +#define L2CC_ECFGR0_OFFSET 0x0208 /* Event Counter 0 Configuration Register */ +#define L2CC_EVR1_OFFSET 0x020c /* Event Counter 1 Value Register */ +#define L2CC_EVR0_OFFSET 0x0210 /* Event Counter 0 Value Register */ +#define L2CC_IMR_OFFSET 0x0214 /* Interrupt Mask Register */ +#define L2CC_MISR_OFFSET 0x0218 /* Masked Interrupt Status Register */ +#define L2CC_RISR_OFFSET 0x021c /* Raw Interrupt Status Register */ +#define L2CC_ICR_OFFSET 0x0220 /* Interrupt Clear Register */ + /* 0x0224-0x072c Reserved */ +#define L2CC_CSR_OFFSET 0x0730 /* Cache Synchronization Register */ + /* 0x0734-0x076c Reserved */ +#define L2CC_IPALR_OFFSET 0x0770 /* Invalidate Physical Address Line Register */ + /* 0x0774-0x0778 Reserved */ +#define L2CC_IWR_OFFSET 0x077c /* Invalidate Way Register */ + /* 0x0780-0x07af Reserved */ +#define L2CC_CPALR_OFFSET 0x07b0 /* Clean Physical Address Line Register */ + /* 0x07b4 Reserved */ +#define L2CC_CIR_OFFSET 0x07b8 /* Clean Index Register */ +#define L2CC_CWR_OFFSET 0x07bc /* Clean Way Register */ + /* 0x07c0-0x07ec Reserved */ +#define L2CC_CIPALR_OFFSET 0x07f0 /* Clean Invalidate Physical Address Line Register */ + /* 0x07f4 Reserved */ +#define L2CC_CIIR_OFFSET 0x07f8 /* Clean Invalidate Index Register */ +#define L2CC_CIWR_OFFSET 0x07fc /* Clean Invalidate Way Register */ + /* 0x0800-0x08fc Reserved */ + +/* Data and Instruction Lockdown registers where n=0-7. + * The registers for n > 0 are implemented if the option + * pl310_LOCKDOWN_BY_MASTER is enabled. + * Otherwise, they are unused + */ + +#define L2CC_DLKR_OFFSET(n) (0x0900 + ((n) << 3)) /* Data Lockdown Register */ +#define L2CC_ILKR_OFFSET(n) (0x0904 + ((n) << 3)) /* Instruction Lockdown Register */ + /* 0x0940-0x0f4c Reserved */ +#ifdef CONFIG_PL310_LOCKDOWN_BY_LINE +# define L2CC_LKLN_OFFSET 0x0950 /* Lock Line Enable Register */ +# define L2CC_UNLKW_OFFSET 0x0954 /* Unlock Way Register */ +#endif + /* 0x0958-0x0bfc Reserved */ +#define L2CC_FLSTRT_OFFSET 0x0c00 /* Address filter start */ +#define L2CC_FLEND_OFFSET 0x0c04 /* Address filter end */ + /* 0x0c08-0x0f3c Reserved */ +#define L2CC_DCR_OFFSET 0x0f40 /* Debug Control Register */ + /* 0x0f44-0x0f5c Reserved */ +#define L2CC_PCR_OFFSET 0x0f60 /* Prefetch Control Register */ + /* 0x0f64-0x0f7c Reserved */ +#define L2CC_POWCR_OFFSET 0x0f80 /* Power Control Register */ + +/* L2CC Register Addresses **************************************************/ + +#define L2CC_IDR (L2CC_VBASE+L2CC_IDR_OFFSET) +#define L2CC_TYPR (L2CC_VBASE+L2CC_TYPR_OFFSET) +#define L2CC_CR (L2CC_VBASE+L2CC_CR_OFFSET) +#define L2CC_ACR (L2CC_VBASE+L2CC_ACR_OFFSET) +#define L2CC_TRCR (L2CC_VBASE+L2CC_TRCR_OFFSET) +#define L2CC_DRCR (L2CC_VBASE+L2CC_DRCR_OFFSET) +#define L2CC_ECR (L2CC_VBASE+L2CC_ECR_OFFSET) +#define L2CC_ECFGR1 (L2CC_VBASE+L2CC_ECFGR1_OFFSET) +#define L2CC_ECFGR0 (L2CC_VBASE+L2CC_ECFGR0_OFFSET) +#define L2CC_EVR1 (L2CC_VBASE+L2CC_EVR1_OFFSET) +#define L2CC_EVR0 (L2CC_VBASE+L2CC_EVR0_OFFSET) +#define L2CC_IMR (L2CC_VBASE+L2CC_IMR_OFFSET) +#define L2CC_MISR (L2CC_VBASE+L2CC_MISR_OFFSET) +#define L2CC_RISR (L2CC_VBASE+L2CC_RISR_OFFSET) +#define L2CC_ICR (L2CC_VBASE+L2CC_ICR_OFFSET) +#define L2CC_CSR (L2CC_VBASE+L2CC_CSR_OFFSET) +#define L2CC_IPALR (L2CC_VBASE+L2CC_IPALR_OFFSET) +#define L2CC_IWR (L2CC_VBASE+L2CC_IWR_OFFSET) +#define L2CC_CPALR (L2CC_VBASE+L2CC_CPALR_OFFSET) +#define L2CC_CIR (L2CC_VBASE+L2CC_CIR_OFFSET) +#define L2CC_CWR (L2CC_VBASE+L2CC_CWR_OFFSET) +#define L2CC_CIPALR (L2CC_VBASE+L2CC_CIPALR_OFFSET) +#define L2CC_CIIR (L2CC_VBASE+L2CC_CIIR_OFFSET) +#define L2CC_CIWR (L2CC_VBASE+L2CC_CIWR_OFFSET) +#define L2CC_DLKR(n) (L2CC_VBASE+L2CC_DLKR_OFFSET(n)) +#define L2CC_ILKR(n) (L2CC_VBASE+L2CC_ILKR_OFFSET(n)) + +#ifdef CONFIG_PL310_LOCKDOWN_BY_LINE +# define L2CC_LKLN (L2CC_VBASE+L2CC_LKLN_OFFSET) +# define L2CC_UNLKW (L2CC_VBASE+L2CC_UNLKW_OFFSET) +#endif + +#define L2CC_FLSTRT (L2CC_VBASE+L2CC_FLSTRT_OFFSET) +#define L2CC_FLEND (L2CC_VBASE+L2CC_FLEND_OFFSET) +#define L2CC_DCR (L2CC_VBASE+L2CC_DCR_OFFSET) +#define L2CC_PCR (L2CC_VBASE+L2CC_PCR_OFFSET) +#define L2CC_POWCR (L2CC_VBASE+L2CC_POWCR_OFFSET) + +/* L2CC Register Bit Definitions ********************************************/ + +/* Cache ID Register (32-bit ID) */ + +#define L2CC_IDR_REV_MASK 0x0000003f +#define L2CC_IDR_REV_R0P0 0x00000000 +#define L2CC_IDR_REV_R1P0 0x00000002 +#define L2CC_IDR_REV_R2P0 0x00000004 +#define L2CC_IDR_REV_R3P0 0x00000005 +#define L2CC_IDR_REV_R3P1 0x00000006 +#define L2CC_IDR_REV_R3P2 0x00000008 + +/* Cache Type Register */ + +#define L2CC_TYPR_IL2ASS (1 << 6) /* Bit 6: Instruction L2 Cache Associativity */ +#define L2CC_TYPR_IL2WSIZE_SHIFT (8) /* Bits 8-10: Instruction L2 Cache Way Size */ +#define L2CC_TYPR_IL2WSIZE_MASK (7 << L2CC_TYPR_IL2WSIZE_SHIFT) +#define L2CC_TYPR_IL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_IL2WSIZE_SHIFT) +#define L2CC_TYPR_DL2ASS (1 << 18) /* Bit 18: Data L2 Cache Associativity */ +#define L2CC_TYPR_DL2WSIZE_SHIFT (20) /* Bits 20-22: Data L2 Cache Way Size */ +#define L2CC_TYPR_DL2WSIZE_MASK (7 << L2CC_TYPR_DL2WSIZE_SHIFT) +#define L2CC_TYPR_DL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_DL2WSIZE_SHIFT) + +/* Control Register */ + +#define L2CC_CR_L2CEN (1 << 0) /* Bit 0: L2 Cache Enable */ + +/* Auxiliary Control Register */ + +#define L2CC_ACR_FLZE (1 << 0) /* Bit 0: Full line zero enable */ +#define L2CC_ACR_HPSO (1 << 10) /* Bit 10: High Priority for SO and Dev Reads Enable */ +#define L2CC_ACR_SBDLE (1 << 11) /* Bit 11: Store Buffer Device Limitation Enable */ +#define L2CC_ACR_EXCC (1 << 12) /* Bit 12: Exclusive Cache Configuration */ +#define L2CC_ACR_SAIE (1 << 13) /* Bit 13: Shared Attribute Invalidate Enable */ +#define L2CC_ACR_ASS (1 << 16) /* Bit 16: Associativity */ +#define L2CC_ACR_WAYSIZE_SHIFT (17) /* Bits 17-19: Way Size */ +#define L2CC_ACR_WAYSIZE_MASK (7 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_16KB (1 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_32KB (2 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_64KB (3 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_128KB (4 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_256KB (5 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_WAYSIZE_512KB (6 << L2CC_ACR_WAYSIZE_SHIFT) +#define L2CC_ACR_EMBEN (1 << 20) /* Bit 20: Event Monitor Bus Enable */ +#define L2CC_ACR_PEN (1 << 21) /* Bit 21: Parity Enable */ +#define L2CC_ACR_SAOEN (1 << 22) /* Bit 22: Shared Attribute Override Enable */ +#define L2CC_ACR_FWA_SHIFT (23) /* Bits 23-24: Force Write Allocate */ +#define L2CC_ACR_FWA_MASK (3 << L2CC_ACR_FWA_SHIFT) +#define L2CC_ACR_FWA_AWCACHE (0 << L2CC_ACR_FWA_SHIFT) /* Use AWCACHE attributes for WA */ +#define L2CC_ACR_FWA_NOALLOC (1 << L2CC_ACR_FWA_SHIFT) /* No allocate */ +#define L2CC_ACR_FWA_OVERRIDE (2 << L2CC_ACR_FWA_SHIFT) /* Override AWCACHE attributes */ +#define L2CC_ACR_FWA_MAPPED (3 << L2CC_ACR_FWA_SHIFT) /* Internally mapped to 00 */ + +#define L2CC_ACR_CRPOL (1 << 25) /* Bit 25: Cache Replacement Policy */ +#define L2CC_ACR_NSLEN (1 << 26) /* Bit 26: Non-Secure Lockdown Enable */ +#define L2CC_ACR_NSIAC (1 << 27) /* Bit 27: Non-Secure Interrupt Access Control */ +#define L2CC_ACR_DPEN (1 << 28) /* Bit 28: Data Prefetch Enable */ +#define L2CC_ACR_IPEN (1 << 29) /* Bit 29: Instruction Prefetch Enable */ +#define L2CC_ACR_EBRESP (1 << 30) /* Bit 30: Early BRESP enable */ + +#define L2CC_ACR_SBZ (0x8000c1fe) + +/* Tag RAM Control Register */ + +#define L2CC_TRCR_TSETLAT_SHIFT (0) /* Bits 0-2: Setup Latency */ +#define L2CC_TRCR_TSETLAT_MASK (7 << L2CC_TRCR_TSETLAT_SHIFT) +#define L2CC_TRCR_TSETLAT(n) ((uint32_t)(n) << L2CC_TRCR_TSETLAT_SHIFT) +#define L2CC_TRCR_TRDLAT_SHIFT (4) /* Bits 4-6: Read Access Latency */ +#define L2CC_TRCR_TRDLAT_MASK (7 << L2CC_TRCR_TRDLAT_SHIFT) +#define L2CC_TRCR_TRDLAT(n) ((uint32_t)(n) << L2CC_TRCR_TRDLAT_SHIFT) +#define L2CC_TRCR_TWRLAT_SHIFT (8) /* Bits 8-10: Write Access Latency */ +#define L2CC_TRCR_TWRLAT_MASK (7 << L2CC_TRCR_TWRLAT_SHIFT) +#define L2CC_TRCR_TWRLAT(n) ((uint32_t)(n) << L2CC_TRCR_TWRLAT_SHIFT) + +/* Data RAM Control Register */ + +#define L2CC_DRCR_DSETLAT_SHIFT (0) /* Bits 0-2: Setup Latency */ +#define L2CC_DRCR_DSETLAT_MASK (7 << L2CC_DRCR_DSETLAT_SHIFT) +#define L2CC_DRCR_DSETLAT(n) ((uint32_t)(n) << L2CC_DRCR_DSETLAT_SHIFT) +#define L2CC_DRCR_DRDLAT_SHIFT (4) /* Bits 4-6: Read Access Latency */ +#define L2CC_DRCR_DRDLAT_MASK (7 << L2CC_DRCR_DRDLAT_SHIFT) +#define L2CC_DRCR_DRDLAT(n) ((uint32_t)(n) << L2CC_DRCR_DRDLAT_SHIFT) +#define L2CC_DRCR_DWRLAT_SHIFT (8) /* Bits 8-10: Write Access Latency */ +#define L2CC_DRCR_DWRLAT_MASK (7 << L2CC_DRCR_DWRLAT_SHIFT) +#define L2CC_DRCR_DWRLAT(n) ((uint32_t)(n) << L2CC_DRCR_DWRLAT_SHIFT) + +/* Event Counter Control Register */ + +#define L2CC_ECR_EVCEN (1 << 0) /* Bit 0: Event Counter Enable */ +#define L2CC_ECR_EVC0RST (1 << 1) /* Bit 1: Event Counter 0 Reset */ +#define L2CC_ECR_EVC1RST (1 << 2) /* Bit 2: Event Counter 1 Reset */ + +/* Event Counter 1 Configuration Register */ + +#define L2CC_ECFGR1_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */ +#define L2CC_ECFGR1_EIGEN_MASK (3 << L2CC_ECFGR1_EIGEN_SHIFT) +#define L2CC_ECFGR1_EIGEN_INTDIS (0 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables (default) */ +#define L2CC_ECFGR1_EIGEN_INTENINCR (1 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Increment condition */ +#define L2CC_ECFGR1_EIGEN_INTENOVER (2 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Overflow condition */ +#define L2CC_ECFGR1_EIGEN_INTGENDIS (3 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables Interrupt generation */ +#define L2CC_ECFGR1_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */ +#define L2CC_ECFGR1_ESRC_MASK (15 << L2CC_ECFGR1_ESRC_SHIFT) +#define L2CC_ECFGR1_ESRC_CNTDIS (0 << L2CC_ECFGR1_ESRC_SHIFT) /* Counter Disabled */ +#define L2CC_ECFGR1_ESRC_CO (1 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is CO */ +#define L2CC_ECFGR1_ESRC_DRHIT (2 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRHIT */ +#define L2CC_ECFGR1_ESRC_DRREQ (3 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRREQ */ +#define L2CC_ECFGR1_ESRC_DWHIT (4 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWHIT */ +#define L2CC_ECFGR1_ESRC_DWREQ (5 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWREQ */ +#define L2CC_ECFGR1_ESRC_DWTREQ (6 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWTREQ */ +#define L2CC_ECFGR1_ESRC_IRHIT (7 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRHIT */ +#define L2CC_ECFGR1_ESRC_IRREQ (8 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRREQ */ +#define L2CC_ECFGR1_ESRC_WA (9 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is WA */ +#define L2CC_ECFGR1_ESRC_IPFALLOC (10 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IPFALLOC */ +#define L2CC_ECFGR1_ESRC_EPFHIT (11 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFHIT */ +#define L2CC_ECFGR1_ESRC_EPFALLOC (12 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFALLOC */ +#define L2CC_ECFGR1_ESRC_SRRCVD (13 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRRCVD */ +#define L2CC_ECFGR1_ESRC_SRCONF (14 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRCONF */ +#define L2CC_ECFGR1_ESRC_EPFRCVD (15 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFRCVD */ + +/* Event Counter 0 Configuration Register */ + +#define L2CC_ECFGR0_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */ +#define L2CC_ECFGR0_EIGEN_MASK (3 << L2CC_ECFGR0_EIGEN_SHIFT) +#define L2CC_ECFGR0_EIGEN_INTDIS (0 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables (default) */ +#define L2CC_ECFGR0_EIGEN_INTENINCR (1 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Increment condition */ +#define L2CC_ECFGR0_EIGEN_INTENOVER (2 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Overflow condition */ +#define L2CC_ECFGR0_EIGEN_INTGENDIS (3 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables Interrupt generation */ +#define L2CC_ECFGR0_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */ +#define L2CC_ECFGR0_ESRC_MASK (15 << L2CC_ECFGR0_ESRC_SHIFT) +#define L2CC_ECFGR0_ESRC_CNTDIS (0 << L2CC_ECFGR0_ESRC_SHIFT) /* Counter Disabled */ +#define L2CC_ECFGR0_ESRC_CO (1 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is CO */ +#define L2CC_ECFGR0_ESRC_DRHIT (2 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRHIT */ +#define L2CC_ECFGR0_ESRC_DRREQ (3 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRREQ */ +#define L2CC_ECFGR0_ESRC_DWHIT (4 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWHIT */ +#define L2CC_ECFGR0_ESRC_DWREQ (5 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWREQ */ +#define L2CC_ECFGR0_ESRC_DWTREQ (6 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWTREQ */ +#define L2CC_ECFGR0_ESRC_IRHIT (7 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRHIT */ +#define L2CC_ECFGR0_ESRC_IRREQ (8 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRREQ */ +#define L2CC_ECFGR0_ESRC_WA (9 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is WA */ +#define L2CC_ECFGR0_ESRC_IPFALLOC (10 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IPFALLOC */ +#define L2CC_ECFGR0_ESRC_EPFHIT (11 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFHIT */ +#define L2CC_ECFGR0_ESRC_EPFALLOC (12 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFALLOC */ +#define L2CC_ECFGR0_ESRC_SRRCVD (13 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRRCVD */ +#define L2CC_ECFGR0_ESRC_SRCONF (14 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRCONF */ +#define L2CC_ECFGR0_ESRC_EPFRCVD (15 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFRCVD */ + +/* Event Counter 1 Value Register (32-bit value) */ + +/* Event Counter 0 Value Register (32-bit value) */ + +/* Interrupt Mask Register, Masked Interrupt Status Register, + * Raw Interrupt Status Register, and Interrupt Clear Register. + */ + +#define L2CC_INT_ECNTR (1 << 0) /* Bit 0: Event Counter 1/0 Overflow Increment */ +#define L2CC_INT_PARRT (1 << 1) /* Bit 1: Parity Error on L2 Tag RAM, Read */ +#define L2CC_INT_PARRD (1 << 2) /* Bit 2: Parity Error on L2 Data RAM, Read */ +#define L2CC_INT_ERRWT (1 << 3) /* Bit 3: Error on L2 Tag RAM, Write */ +#define L2CC_INT_ERRWD (1 << 4) /* Bit 4: Error on L2 Data RAM, Write */ +#define L2CC_INT_ERRRT (1 << 5) /* Bit 5: Error on L2 Tag RAM, Read */ +#define L2CC_INT_ERRRD (1 << 6) /* Bit 6: Error on L2 Data RAM, Read */ +#define L2CC_INT_SLVERR (1 << 7) /* Bit 7: SLVERR from L3 Memory */ +#define L2CC_INT_DECERR (1 << 8) /* Bit 8: DECERR from L3 Memory */ + +/* Cache Synchronization Register */ + +#define L2CC_CSR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ + +/* Invalidate Physical Address Line Register */ + +#define L2CC_IPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ +#define L2CC_IPALR_IDX_SHIFT (5) /* Bits 5-13: Index Number */ +#define L2CC_IPALR_IDX_MASK (0x1ff << L2CC_IPALR_IDX_SHIFT) +#define L2CC_IPALR_IDX(n) ((uint32_t)(n) << L2CC_IPALR_IDX_SHIFT) +#define L2CC_IPALR_TAG_SHIFT (14) /* Bits 14-31: Tag Number */ +#define L2CC_IPALR_TAG_MASK (0x3ffff << L2CC_IPALR_TAG_SHIFT) +#define L2CC_IPALR_TAG(n) ((uint32_t)(n) << L2CC_IPALR_TAG_SHIFT) + +/* Invalidate Way Register */ + +#define L2CC_IWR_WAY(n) (1 << (n)) /* Bist 0-7: Invalidate Way Number n, n=0..7 */ +#define L2CC_IWR_WAY0 (1 << 0) /* Bit 0: Invalidate Way Number 0 */ +#define L2CC_IWR_WAY1 (1 << 1) /* Bit 1: Invalidate Way Number 1 */ +#define L2CC_IWR_WAY2 (1 << 2) /* Bit 2: Invalidate Way Number 2 */ +#define L2CC_IWR_WAY3 (1 << 3) /* Bit 3: Invalidate Way Number 3 */ +#define L2CC_IWR_WAY4 (1 << 4) /* Bit 4: Invalidate Way Number 4 */ +#define L2CC_IWR_WAY5 (1 << 5) /* Bit 5: Invalidate Way Number 5 */ +#define L2CC_IWR_WAY6 (1 << 6) /* Bit 6: Invalidate Way Number 6 */ +#define L2CC_IWR_WAY7 (1 << 7) /* Bit 7: Invalidate Way Number 7 */ + +/* Clean Physical Address Line Register */ + +#define L2CC_CPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ +#define L2CC_CPALR_IDX_SHIFT (5) /* Bits 5-13: Index number */ +#define L2CC_CPALR_IDX_MASK (0x1ff << L2CC_CPALR_IDX_SHIFT) +#define L2CC_CPALR_IDX(n) ((uint32_t)(n) << L2CC_CPALR_IDX_SHIFT) +#define L2CC_CPALR_TAG_SHIFT (14) /* Bits 14-31: Tag number */ +#define L2CC_CPALR_TAG_MASK (0x3ffff << L2CC_CPALR_TAG_SHIFT) +#define L2CC_CPALR_TAG(n) ((uint32_t)(n) << L2CC_CPALR_TAG_SHIFT) + +/* Clean Index Register */ + +#define L2CC_CIR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ +#define L2CC_CIR_IDX_SHIFT (5) /* Bits 5-13: Index number */ +#define L2CC_CIR_IDX_MASK (0x1ff << L2CC_CIR_IDX_SHIFT) +#define L2CC_CIR_IDX(n) ((uint32_t)(n) << L2CC_CIR_IDX_SHIFT) +#define L2CC_CIR_WAY_SHIFT (28) /* Bits 28-30: Way number */ +#define L2CC_CIR_WAY_MASK (7 << L2CC_CIR_WAY_SHIFT) +#define L2CC_CIR_WAY(n) ((uint32_t)(n) << L2CC_CIR_WAY_SHIFT) + +/* Clean Way Register */ + +#define L2CC_CWR_WAY(n) (1 << (n)) /* Bits 0-7: Clean Way Number n, n=0..7 */ +#define L2CC_CWR_WAY0 (1 << 0) /* Bit 0: Clean Way Number 0 */ +#define L2CC_CWR_WAY1 (1 << 1) /* Bit 1: Clean Way Number 1 */ +#define L2CC_CWR_WAY2 (1 << 2) /* Bit 2: Clean Way Number 2 */ +#define L2CC_CWR_WAY3 (1 << 3) /* Bit 3: Clean Way Number 3 */ +#define L2CC_CWR_WAY4 (1 << 4) /* Bit 4: Clean Way Number 4 */ +#define L2CC_CWR_WAY5 (1 << 5) /* Bit 5: Clean Way Number 5 */ +#define L2CC_CWR_WAY6 (1 << 6) /* Bit 6: Clean Way Number 6 */ +#define L2CC_CWR_WAY7 (1 << 7) /* Bit 7: Clean Way Number 7 */ + +/* Clean Invalidate Physical Address Line Register */ + +#define L2CC_CIPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ +#define L2CC_CIPALR_IDX_SHIFT (5) /* Bits 5-13: Index Number */ +#define L2CC_CIPALR_IDX_MASK (0x1ff << L2CC_CIPALR_IDX_SHIFT) +#define L2CC_CIPALR_IDX(n) ((uint32_t)(n) << L2CC_CIPALR_IDX_SHIFT) +#define L2CC_CIPALR_TAG_SHIFT (14) /* Bits 14-31: Tag Number */ +#define L2CC_CIPALR_TAG_MASK (0x3ffff << L2CC_CIPALR_TAG_SHIFT) +#define L2CC_CIPALR_TAG(n) ((uint32_t)(n) << L2CC_CIPALR_TAG_SHIFT) + +/* Clean Invalidate Index Register */ + +#define L2CC_CIIR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ +#define L2CC_CIIR_IDX_SHIFT (5) /* Bits 5-13: Index Number */ +#define L2CC_CIIR_IDX_MASK (0x1ff << L2CC_CIIR_IDX_SHIFT) +#define L2CC_CIIR_IDX(n) ((uint32_t)(n) << L2CC_CIIR_IDX_SHIFT) +#define L2CC_CIIR_WAY_SHIFT (28) /* Bits 28-30: Way Number */ +#define L2CC_CIIR_WAY_MASK (7 << L2CC_CIIR_WAY_SHIFT) +#define L2CC_CIIR_WAY(n) ((uint32_t)(n) << L2CC_CIIR_WAY_SHIFT) + +/* Clean Invalidate Way Register */ + +#define L2CC_CIWR_WAY(n) (1 << (n)) /* Bits 0-7: Clean Invalidate Way Number n, n=1..7 */ +#define L2CC_CIWR_WAY0 (1 << 0) /* Bit 0: Clean Invalidate Way Number 0 */ +#define L2CC_CIWR_WAY1 (1 << 1) /* Bit 1: Clean Invalidate Way Number 1 */ +#define L2CC_CIWR_WAY2 (1 << 2) /* Bit 2: Clean Invalidate Way Number 2 */ +#define L2CC_CIWR_WAY3 (1 << 3) /* Bit 3: Clean Invalidate Way Number 3 */ +#define L2CC_CIWR_WAY4 (1 << 4) /* Bit 4: Clean Invalidate Way Number 4 */ +#define L2CC_CIWR_WAY5 (1 << 5) /* Bit 5: Clean Invalidate Way Number 5 */ +#define L2CC_CIWR_WAY6 (1 << 6) /* Bit 6: Clean Invalidate Way Number 6 */ +#define L2CC_CIWR_WAY7 (1 << 7) /* Bit 7: Clean Invalidate Way Number 7 */ + +/* Data Lockdown Register */ + +#define L2CC_DLKR_DLK(n) (1 << (n)) /* Bits 0-7: Data Lockdown in Way Number n, n=0..7 */ +#define L2CC_DLKR_DLK0 (1 << 0) /* Bit 0: Data Lockdown in Way Number 0 */ +#define L2CC_DLKR_DLK1 (1 << 1) /* Bit 1: Data Lockdown in Way Number 1 */ +#define L2CC_DLKR_DLK2 (1 << 2) /* Bit 2: Data Lockdown in Way Number 2 */ +#define L2CC_DLKR_DLK3 (1 << 3) /* Bit 3: Data Lockdown in Way Number 3 */ +#define L2CC_DLKR_DLK4 (1 << 4) /* Bit 4: Data Lockdown in Way Number 4 */ +#define L2CC_DLKR_DLK5 (1 << 5) /* Bit 5: Data Lockdown in Way Number 5 */ +#define L2CC_DLKR_DLK6 (1 << 6) /* Bit 6: Data Lockdown in Way Number 6 */ +#define L2CC_DLKR_DLK7 (1 << 7) /* Bit 7: Data Lockdown in Way Number 7 */ + +/* Instruction Lockdown Register */ + +#define L2CC_ILKR_ILK(n) (1 << (n)) /* Bits 0-7: Instruction Lockdown in Way Number n, n=0..7 */ +#define L2CC_ILKR_ILK0 (1 << 0) /* Bit 0: Instruction Lockdown in Way Number 0 */ +#define L2CC_ILKR_ILK1 (1 << 1) /* Bit 1: Instruction Lockdown in Way Number 1 */ +#define L2CC_ILKR_ILK2 (1 << 2) /* Bit 2: Instruction Lockdown in Way Number 2 */ +#define L2CC_ILKR_ILK3 (1 << 3) /* Bit 3: Instruction Lockdown in Way Number 3 */ +#define L2CC_ILKR_ILK4 (1 << 4) /* Bit 4: Instruction Lockdown in Way Number 4 */ +#define L2CC_ILKR_ILK5 (1 << 5) /* Bit 5: Instruction Lockdown in Way Number 5 */ +#define L2CC_ILKR_ILK6 (1 << 6) /* Bit 6: Instruction Lockdown in Way Number 6 */ +#define L2CC_ILKR_ILK7 (1 << 7) /* Bit 7: Instruction Lockdown in Way Number 7 */ + +/* Lock Line Enable Register */ + +#ifdef CONFIG_PL310_LOCKDOWN_BY_LINE +# define L2CC_LKLN_ENABLE (1 << 0) /* Bit 0: Lockdown by line enable */ +#endif + +/* Unlock Way Register */ + +#ifdef CONFIG_PL310_LOCKDOWN_BY_LINE +# define L2CC_UNLKW_WAY_SHIFT (0) /* Bits 0-15: Unlock line for corresponding way */ +# define L2CC_UNLKW_WAY_MASK (0xffff << L2CC_UNLKW_WAY_SHIFT) +# define L2CC_UNLKW_WAY_SET(n) ((uint32_t)(n) << L2CC_UNLKW_WAY_SHIFT) +# define L2CC_UNLKW_WAY_BIT(n) ((1 << (n)) << L2CC_UNLKW_WAY_SHIFT) +#endif + +/* Address filter start */ + +#ifdef PL310_ADDRESS_FILTERING +# define L2CC_FLSTRT_ENABLE (1 << 0) /* Bit 0: Address filter enable */ +# define L2CC_FLSTRT_MASK (0xfff00000) /* Bits 20-31: Bits 20-31 of address mask */ +#endif + +/* Address filter end */ + +#ifdef PL310_ADDRESS_FILTERING +# define L2CC_FLEND_MASK (0xfff00000) /* Bits 20-31: Bits 20-31 of address mask */ +#endif + +/* Debug Control Register */ + +#define L2CC_DCR_DCL (1 << 0) /* Bit 0: Disable Cache Linefill */ +#define L2CC_DCR_DWB (1 << 1) /* Bit 1: Disable Write-back, Force Write-through */ +#define L2CC_DCR_SPNIDEN (1 << 2) /* Bit 2: SPNIDEN Value */ + +/* Prefetch Control Register */ + +#define L2CC_PCR_SHIFT (0) /* Bits 0-4: Prefetch Offset */ +#define L2CC_PCR_MASK (31 << L2CC_PCR_SHIFT) +#define L2CC_PCR_PREFETCH(n) ((uint32_t)(n) << L2CC_PCR_SHIFT) +#define L2CC_PCR_NSIDEN (1 << 21) /* Bit 21: Not Same ID on Exclusive Sequence Enable */ +#define L2CC_PCR_IDLEN (1 << 23) /* Bit 23: INCR Double Linefill Enable */ +#define L2CC_PCR_PDEN (1 << 24) /* Bit 24: Prefetch Drop Enable */ +#define L2CC_PCR_DLFWRDIS (1 << 27) /* Bit 27: Double Linefill on WRAP Read Disable */ +#define L2CC_PCR_DATPEN (1 << 28) /* Bit 28: Data Prefetch Enable */ +#define L2CC_PCR_INSPEN (1 << 29) /* Bit 29: Instruction Prefetch Enable */ +#define L2CC_PCR_DLEN (1 << 30) /* Bit 30: Double Linefill Enable */ + +/* Power Control Register */ + +#define L2CC_POWCR_STBYEN (1 << 0) /* Bit 0: Standby Mode Enable */ +#define L2CC_POWCR_DCKGATEN (1 << 1) /* Bit 1: Dynamic Clock Gating Enable */ + +#endif /* __ARCH_ARM_SRC_ARMV7_A_L2CC_PL310_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/device.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/device.h new file mode 100644 index 000000000..0b3bde014 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/device.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2022 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file l2cc_pl310.c + * @brief PLC inovance am401 app + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.8.10 + */ + +#include + +struct uart_desc { + uint32_t RXD_ADDR; + uint32_t TXD_ADDR; +}; + +struct arch_desc { + struct gic_desc { + uint32_t GICC_ADDR; + uint32_t GICD_ADDR; + + } gic; + +}; + + +struct page_pool { + uint32_t node; + uint32_t base; + uint32_t size; + uint32_t free; + uint32_t last; + +}; + +struct mem_region { + uint32_t base; + uint32_t size; + struct page_pool page_pool; +}; + + + + + + +struct board_desc{ + + uint32_t cpu_num; + uint32_t region_num; + struct mem_region *regions; + + struct { + uint32_t base_addr; + } console; + + uint32_t uart_num; + struct uart_desc *uarts; + + struct arch_desc arch; +}; \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q_desc.c b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q_desc.c new file mode 100644 index 000000000..b413d364e --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q_desc.c @@ -0,0 +1,56 @@ +#include "device.h" + + +struct board_desc platform = { + .cpu_num = 4, + .region_num = 1, + .regions = (struct mem_region[]) { + { + + .base = 0x10000000, + .size = 0xFFFFFFFF - 0x10000000 + } + }, + + +#define URXD 0x0 /* Receiver Register */ +#define UTXD 0x40 /* Transmitter Register */ + + + + +#define AIPS1_ARB_BASE_ADDR 0x02000000 +#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR +#define UART1_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) + + +#define AIPS2_ARB_BASE_ADDR 0x02100000 +#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR +#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) + + .console = { + .base_addr=AIPS2_OFF_BASE_ADDR + 0x68000, + }, + + .arch = { + .gic = { + .GICD_ADDR = 0x00A01000, + .GICC_ADDR = 0x00A00100, + + }, + }, + + .uart_num=2, + .uarts=(struct uart_desc[]){ + //UART 0 + { + .RXD_ADDR=0xF9010000, + .TXD_ADDR=0xF9010000, + }, + //UART 1 + { + .RXD_ADDR=0xF9010000, + .TXD_ADDR=0xF9010000, + } + } +}; From 5a02b89ffc92c14f7d78eda1c173d092811fde0b Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Wed, 27 Sep 2023 14:13:10 +0800 Subject: [PATCH 10/21] delete mqtt --- .../connection_app/mqtt_demo/Makefile | 12 - .../connection_app/mqtt_demo/lwip_mqtt_demo.c | 728 ------------------ .../connection_app/mqtt_demo/lwip_mqtt_demo.h | 71 -- .../LwIP/include/lwip/apps/MQTT/MQTTConnect.h | 137 ---- .../lwip/apps/MQTT/MQTTConnectClient.c | 214 ----- .../lwip/apps/MQTT/MQTTConnectServer.c | 148 ---- .../lwip/apps/MQTT/MQTTDeserializePublish.c | 107 --- .../LwIP/include/lwip/apps/MQTT/MQTTFormat.c | 262 ------- .../LwIP/include/lwip/apps/MQTT/MQTTFormat.h | 37 - .../LwIP/include/lwip/apps/MQTT/MQTTPacket.c | 412 ---------- .../LwIP/include/lwip/apps/MQTT/MQTTPacket.h | 134 ---- .../LwIP/include/lwip/apps/MQTT/MQTTPublish.h | 38 - .../lwip/apps/MQTT/MQTTSerializePublish.c | 169 ---- .../include/lwip/apps/MQTT/MQTTSubscribe.h | 39 - .../lwip/apps/MQTT/MQTTSubscribeClient.c | 137 ---- .../lwip/apps/MQTT/MQTTSubscribeServer.c | 112 --- .../include/lwip/apps/MQTT/MQTTUnsubscribe.h | 38 - .../lwip/apps/MQTT/MQTTUnsubscribeClient.c | 106 --- .../lwip/apps/MQTT/MQTTUnsubscribeServer.c | 102 --- .../LwIP/include/lwip/apps/MQTT/Makefile | 13 - .../LwIP/include/lwip/apps/MQTT/StackTrace.h | 78 -- .../LwIP/include/lwip/apps/MQTT/transport.c | 102 --- .../LwIP/include/lwip/apps/MQTT/transport.h | 45 -- .../ethernet/LwIP/include/lwip/apps/Makefile | 6 - 24 files changed, 3247 deletions(-) delete mode 100644 APP_Framework/Applications/connection_app/mqtt_demo/Makefile delete mode 100644 APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c delete mode 100644 APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.h delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnect.h delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnectClient.c delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnectServer.c delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTDeserializePublish.c delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTFormat.c delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTFormat.h delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPacket.c delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPacket.h delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPublish.h delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSerializePublish.c delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribe.h delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribeClient.c delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribeServer.c delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribe.h delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribeClient.c delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribeServer.c delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/Makefile delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/StackTrace.h delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/transport.c delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/transport.h delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/Makefile diff --git a/APP_Framework/Applications/connection_app/mqtt_demo/Makefile b/APP_Framework/Applications/connection_app/mqtt_demo/Makefile deleted file mode 100644 index b0e21dc77..000000000 --- a/APP_Framework/Applications/connection_app/mqtt_demo/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -ifeq ($(CONFIG_ADD_XIZI_FEATURES),y) -SRC_FILES += lwip_mqtt_demo.c -include $(KERNEL_ROOT)/compiler.mk -endif - -include $(KERNEL_ROOT)/.config -ifeq ($(CONFIG_ADD_NUTTX_FEATURES),y) - include $(APPDIR)/Make.defs - CSRCS += lwip_mqtt_demo.c - include $(APPDIR)/Application.mk -endif - diff --git a/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c b/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c deleted file mode 100644 index 2d7d6fa29..000000000 --- a/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.c +++ /dev/null @@ -1,728 +0,0 @@ -#include -#include "lwip_mqtt_demo.h" -#include -#ifdef ADD_XIZI_FEATURES -#include -#include -#include "lwip/sys.h" -#include "lwip/api.h" - -#include -#include -#include -#include - -#endif - -#ifdef ADD_NUTTX_FEATURES -#include -#include -#include -#include "stdio.h" -#endif - - -#define MQTT_DEMO_BUF_SIZE 65535 -#define MQTT_DEMO_SEND_TIMES 20 -#define LWIP_MQTT_DEMO_TASK_STACK_SIZE 4096 -#define LWIP_MQTT_DEMO_TASK_PRIO 20 - -static char mqtt_demo_ipaddr[] = {192, 168, 130, 77}; -static char mqtt_demo_netmask[] = {255, 255, 254, 0}; -static char mqtt_demo_gwaddr[] = {192, 168, 130, 1}; - -static pthread_t mqtt_client_task; -static pthread_t mqtt_server_task; - -static uint16_t mqtt_socket_port = 1883; -static char mqtt_ip_str[128] = {192,168,100,1}; - -void MqttSocketConfigParam(char *ip_str) -{ - int ip1, ip2, ip3, ip4, port = 0; - - if(ip_str == NULL) - return; - - if(sscanf(ip_str, "%d.%d.%d.%d:%d", &ip1, &ip2, &ip3, &ip4, &port)) { - printf("config ip %s port %d\n", ip_str, port); - strcpy(mqtt_ip_str, ip_str); - if(port) - mqtt_socket_port = port; - return; - } - - if(sscanf(ip_str, "%d.%d.%d.%d", &ip1, &ip2, &ip3, &ip4)) { - printf("config ip %s\n", ip_str); - strcpy(mqtt_ip_str, ip_str); - } -} - -MQTT_USER_MSG mqtt_user_msg; - -uint8_t MQTT_Connect(void) -{ - MQTTPacket_connectData data = MQTTPacket_connectData_initializer; - uint8_t buf[200]; - int buflen = sizeof(buf); - int len = 0; - data.clientID.cstring = CLIENT_ID; //随机 - data.keepAliveInterval = KEEPLIVE_TIME; //保持活跃 - data.username.cstring = USER_NAME; //用户名 - data.password.cstring = PASSWORD; //密钥 - data.MQTTVersion = MQTT_VERSION; //3表示3.1版本，4表示3.11版本 - data.cleansession = 1; - //组装消息 - len = MQTTSerialize_connect((unsigned char *)buf, buflen, &data); - //发送消息 - transport_sendPacketBuffer(buf, len); - - /* 等待连接响应 */ - if (MQTTPacket_read(buf, buflen, transport_getdata) == CONNACK) - { - unsigned char sessionPresent, connack_rc; - if (MQTTDeserialize_connack(&sessionPresent, &connack_rc, buf, buflen) != 1 || connack_rc != 0) - { - lw_print("无法连接，错误代码是: %d！\n", connack_rc); - return Connect_NOK; - } - else - { - lw_print("用户名与密钥验证成功，MQTT连接成功！\n"); - return Connect_OK; - } - } - else - lw_print("MQTT连接无响应！\n"); - return Connect_NOTACK; -} - - -int32_t MQTT_PingReq(int32_t sock) -{ - int32_t len; - uint8_t buf[200]; - int32_t buflen = sizeof(buf); - fd_set readfd; - struct timeval tv; - tv.tv_sec = 5; - tv.tv_usec = 0; - - FD_ZERO(&readfd); - FD_SET(sock,&readfd); - - len = MQTTSerialize_pingreq(buf, buflen); - transport_sendPacketBuffer(buf, len); - - //等待可读事件 - if(select(sock+1,&readfd,NULL,NULL,&tv) == 0) - return -1; - - //有可读事件 - if(FD_ISSET(sock,&readfd) == 0) - return -2; - - if(MQTTPacket_read(buf, buflen, transport_getdata) != PINGRESP) - return -3; - - return 0; - -} - - -/************************************************************************ -** 函数名称: MQTTSubscribe -** 函数功能: 订阅消息 -** 入口参数: int32_t sock：套接字 -** int8_t *topic：主题 -** enum QoS pos：消息质量 -** 出口参数: >=0:发送成功 <0:发送失败 -** 备 注: -************************************************************************/ -int32_t MQTTSubscribe(int32_t sock,char *topic,enum QoS pos) -{ - static uint32_t PacketID = 0; - uint16_t packetidbk = 0; - int32_t conutbk = 0; - uint8_t buf[100]; - int32_t buflen = sizeof(buf); - MQTTString topicString = MQTTString_initializer; - int32_t len; - int32_t req_qos,qosbk; - - fd_set readfd; - struct timeval tv; - tv.tv_sec = 2; - tv.tv_usec = 0; - - FD_ZERO(&readfd); - FD_SET(sock,&readfd); - - //复制主题 - topicString.cstring = (char *)topic; - //订阅质量 - req_qos = pos; - - //串行化订阅消息 - len = MQTTSerialize_subscribe(buf, buflen, 0, PacketID++, 1, &topicString, &req_qos); - //发送TCP数据 - if(transport_sendPacketBuffer(buf, len) < 0) - return -1; - - //等待可读事件--等待超时 - if(select(sock+1,&readfd,NULL,NULL,&tv) == 0) - return -2; - //有可读事件--没有可读事件 - if(FD_ISSET(sock,&readfd) == 0) - return -3; - - //等待订阅返回--未收到订阅返回 - if(MQTTPacket_read(buf, buflen, transport_getdata) != SUBACK) - return -4; - - //拆订阅回应包 - if(MQTTDeserialize_suback(&packetidbk,1, &conutbk, &qosbk, buf, buflen) != 1) - return -5; - - //检测返回数据的正确性 - if((qosbk == 0x80)||(packetidbk != (PacketID-1))) - return -6; - - //订阅成功 - return 0; -} - -int32_t ReadPacketTimeout(int32_t sock,uint8_t *buf,int32_t buflen,uint32_t timeout) -{ - fd_set readfd; - struct timeval tv; - if(timeout != 0) - { - tv.tv_sec = timeout; - tv.tv_usec = 0; - FD_ZERO(&readfd); - FD_SET(sock,&readfd); - - - if(select(sock+1,&readfd,NULL,NULL,&tv) == 0) - return -1; - - if(FD_ISSET(sock,&readfd) == 0) - return -1; - } - - return MQTTPacket_read(buf, buflen, transport_getdata); -} - -void deliverMessage(MQTTString *TopicName,MQTTMessage *msg,MQTT_USER_MSG *mqtt_user_msg) -{ - //消息质量 - mqtt_user_msg->msgqos = msg->qos; - //保存消息 - memcpy(mqtt_user_msg->msg,msg->payload,msg->payloadlen); - mqtt_user_msg->msg[msg->payloadlen] = 0; - //保存消息长度 - mqtt_user_msg->msglenth = msg->payloadlen; - //消息主题 - memcpy((char *)mqtt_user_msg->topic,TopicName->lenstring.data,TopicName->lenstring.len); - mqtt_user_msg->topic[TopicName->lenstring.len] = 0; - //消息ID - mqtt_user_msg->packetid = msg->id; - //标明消息合法 - mqtt_user_msg->valid = 1; -} - -void UserMsgCtl(MQTT_USER_MSG *msg) -{ - //这里处理数据只是打印，用户可以在这里添加自己的处理方式 - lw_print("****收到订阅的消息******\n"); - //���غ�����Ϣ - switch(msg->msgqos) - { - case 0: - lw_print("MQTT>>消息质量QoS0\n"); - break; - case 1: - lw_print("MQTT>>消息质量QoS1\n"); - break; - case 2: - lw_print("MQTT>>消息质量QoS2\n"); - break; - default: - lw_print("MQTT>>错误的消息质量\n"); - break; - } - lw_print("MQTT>>消息主题：%s\n",msg->topic); - lw_print("MQTT>>消息内容：%s\n",msg->msg); - lw_print("MQTT>>消息长度：%d\n",msg->msglenth); - Proscess(msg->msg); - //处理完后销毁数据 - msg->valid = 0; -} - - -void mqtt_pktype_ctl(uint8_t packtype,uint8_t *buf,uint32_t buflen) -{ - MQTTMessage msg; - int32_t rc; - MQTTString receivedTopic; - uint32_t len; - lw_print("packtype:%d\n",packtype); - switch(packtype) - { - case PUBLISH: - - if(MQTTDeserialize_publish(&msg.dup,(int*)&msg.qos, &msg.retained, &msg.id, &receivedTopic, - (unsigned char **)&msg.payload, &msg.payloadlen, buf, buflen) != 1) - return; - - deliverMessage(&receivedTopic,&msg,&mqtt_user_msg); - - - if(msg.qos == QOS0) - { - //QOS0-不需要ACK - //直接处理数据 - UserMsgCtl(&mqtt_user_msg); - return; - } - //发送PUBACK消息 - if(msg.qos == QOS1) - { - len =MQTTSerialize_puback(buf,buflen,mqtt_user_msg.packetid); - if(len == 0) - return; - //发送返回 - if(transport_sendPacketBuffer(buf,len)<0) - return; - //返回后处理消息 - UserMsgCtl(&mqtt_user_msg); - return; - } - - //对于质量2,只需要发送PUBREC就可以了 - if(msg.qos == QOS2) - { - len = MQTTSerialize_ack(buf, buflen, PUBREC, 0, mqtt_user_msg.packetid); - if(len == 0) - return; - //发送返回 - transport_sendPacketBuffer(buf,len); - } - break; - case PUBREL: - //解析包数据，必须包ID相同才可以 - rc = MQTTDeserialize_ack(&msg.type,&msg.dup, &msg.id, buf,buflen); - if((rc != 1)||(msg.type != PUBREL)||(msg.id != mqtt_user_msg.packetid)) - return ; - //收到PUBREL，需要处理并抛弃数据 - if(mqtt_user_msg.valid == 1) - { - //返回后处理消息 - UserMsgCtl(&mqtt_user_msg); - } - //串行化PUBCMP消息 - len = MQTTSerialize_pubcomp(buf,buflen,msg.id); - if(len == 0) - return; - //发送返回--PUBCOMP - transport_sendPacketBuffer(buf,len); - break; - case PUBACK://等级1客户端推送数据后，服务器返回 - break; - case PUBREC://等级2客户端推送数据后，服务器返回 - break; - case PUBCOMP://等级2客户端推送PUBREL后，服务器返回 - break; - default: - break; - } -} - - -static void *MqttSocketRecvTask(void *arg) -{ -MQTT_START: - lw_print("Recv begin**********\n"); - int fd = -1, clientfd; - int recv_len; - int ret; - char *recv_buf; - struct sockaddr_in mqtt_addr; - socklen_t addr_len; - - fd = socket(AF_INET, SOCK_STREAM, 0); - if (fd < 0) { - lw_print("Socket error\n"); - return NULL; - } - - struct sockaddr_in mqtt_sock; - mqtt_sock.sin_family = AF_INET; - mqtt_sock.sin_port = htons(mqtt_socket_port); - mqtt_sock.sin_addr.s_addr = inet_addr(mqtt_ip_str); - - memset(&(mqtt_sock.sin_zero), 0, sizeof(mqtt_sock.sin_zero)); - - ret = connect(fd, (struct sockaddr *)&mqtt_sock, sizeof(struct sockaddr)); - - if (ret < 0) { - lw_print("Unable to connect %s:%d = %d\n", mqtt_ip_str, mqtt_socket_port, ret); - close(fd); - return NULL; - } - - lw_print("MQTT connect %s:%d success, begin to verify username and password.\n", mqtt_ip_str, mqtt_socket_port); - - if(MQTT_Connect() != Connect_OK) - { - lw_print("MQTT verify failed.\n"); - shutdown(fd, SHUT_WR); - recv(fd, NULL, (size_t)0, 0); - close(fd); - PrivTaskDelay(1000); - goto MQTT_START; - } - - lw_print("MQTT subscribe begin.\n"); - if(MQTTSubscribe(fd,(char *)TOPIC,QOS1) < 0) - { - lw_print("MQTT subscribe failed.\n"); - shutdown(fd, SHUT_WR); - recv(fd, NULL, (size_t)0, 0); - close(fd); - return NULL; - } - - lw_print("subscribe success.\n"); - - fd_set readfd; - uint8_t no_mqtt_msg_exchange = 1; - uint8_t buf[MSG_MAX_LEN]; - int32_t buflen = sizeof(buf); - int32_t type; - struct timeval tv; - tv.tv_sec = 0; - tv.tv_usec = 10; - - int32_t curtick=0; - - while(1) - { - // lw_print("waiting********\n"); - curtick +=1; - no_mqtt_msg_exchange = 1; - - FD_ZERO(&readfd); - FD_SET(fd,&readfd); - select(fd+1,&readfd,NULL,NULL,&tv); - - if(FD_ISSET(fd,&readfd) != 0) - { - - type = ReadPacketTimeout(fd,buf,buflen,0); - if(type != -1) - { - lw_print("ctl***********\n"); - mqtt_pktype_ctl(type,buf,buflen); - - no_mqtt_msg_exchange = 0; - - } - } - - if( curtick >(2*10000)) - { - curtick =0; - //判断是否有数据交换 - if(no_mqtt_msg_exchange == 0) - { - //如果有数据交换，这次就不需要发送PING消息 - continue; - } - - if(MQTT_PingReq(fd) < 0) - { - //重连服务器 - lw_print("发送保持活性ping失败....\n"); - goto CLOSE; - } - - - lw_print("发送保持活性ping作为心跳成功....\n"); - - no_mqtt_msg_exchange = 0; - } - } - -CLOSE: - lw_print("MQTT subscribe failed.\n"); - shutdown(fd, SHUT_WR); - recv(fd, NULL, (size_t)0, 0); - close(fd); - return NULL; - - -} - - - -void MqttSocketRecvTest(int argc, char *argv[]) -{ - if(argc >= 2) { - lw_print("lw: [%s] target ip %s\n", __func__, argv[1]); - MqttSocketConfigParam(argv[1]); - } - - - // ip4_addr_t dns_ip; - // netconn_gethostbyname(HOST_NAME, &dns_ip); - // char* host_ip = ip_ntoa(&dns_ip); - // lw_print("host name : %s , host_ip : %s\n",HOST_NAME,host_ip); - // MqttSocketConfigParam(host_ip); - - -#ifdef ADD_XIZI_FEATURES - lwip_config_tcp(0, mqtt_demo_ipaddr, mqtt_demo_netmask, mqtt_demo_gwaddr); - - pthread_attr_t attr; - attr.schedparam.sched_priority = LWIP_MQTT_DEMO_TASK_PRIO; - attr.stacksize = LWIP_MQTT_DEMO_TASK_STACK_SIZE; -#endif - -#ifdef ADD_NUTTX_FEATURES - pthread_attr_t attr = PTHREAD_ATTR_INITIALIZER; - attr.priority = LWIP_mqtt_DEMO_TASK_PRIO; - attr.stacksize = LWIP_mqtt_DEMO_TASK_STACK_SIZE; -#endif - - PrivTaskCreate(&mqtt_server_task, &attr, &MqttSocketRecvTask, NULL); - PrivTaskStartup(&mqtt_server_task); -} - -PRIV_SHELL_CMD_FUNCTION(MqttSocketRecvTest, a tcp send sample, PRIV_SHELL_CMD_MAIN_ATTR); - - -typedef struct -{ - uint8_t humi_high8bit; //ԭʼ���ݣ�ʪ�ȸ�8λ - uint8_t humi_low8bit; //ԭʼ���ݣ�ʪ�ȵ�8λ - uint8_t temp_high8bit; //ԭʼ���ݣ��¶ȸ�8λ - uint8_t temp_low8bit; //ԭʼ���ݣ��¶ȸ�8λ - uint8_t check_sum; //У��� - double humidity; //ʵ��ʪ�� - double temperature; //ʵ���¶� -} DHT11_Data_TypeDef; - - -uint16_t GetNextPackID(void) -{ - static uint16_t pubpacketid = 0; - return pubpacketid++; -} - -int32_t WaitForPacket(int32_t sock,uint8_t packettype,uint8_t times) -{ - int32_t type; - uint8_t buf[MSG_MAX_LEN]; - uint8_t n = 0; - int32_t buflen = sizeof(buf); - do - { - //读取数据包 - type = ReadPacketTimeout(sock,buf,buflen,2); - if(type != -1) - mqtt_pktype_ctl(type,buf,buflen); - n++; - }while((type != packettype)&&(n < times)); - //收到期望的包 - if(type == packettype) - return 0; - else - return -1; -} - -int32_t MQTTMsgPublish(int32_t sock, char *topic, int8_t qos, uint8_t* msg) -{ - int8_t retained = 0; //保留标志位 - uint32_t msg_len; //数据长度 - uint8_t buf[MSG_MAX_LEN]; - int32_t buflen = sizeof(buf),len; - MQTTString topicString = MQTTString_initializer; - uint16_t packid = 0,packetidbk; - - //填充主题 - topicString.cstring = (char *)topic; - - //填充数据包ID - if((qos == QOS1)||(qos == QOS2)) - { - packid = GetNextPackID(); - } - else - { - qos = QOS0; - retained = 0; - packid = 0; - } - - msg_len = strlen((char *)msg); - - //推送消息 - len = MQTTSerialize_publish(buf, buflen, 0, qos, retained, packid, topicString, (unsigned char*)msg, msg_len); - if(len <= 0) - return -1; - if(transport_sendPacketBuffer(buf, len) < 0) - return -2; - - //质量等级0，不需要返回 - if(qos == QOS0) - { - return 0; - } - - //等级1 - if(qos == QOS1) - { - //等待PUBACK - if(WaitForPacket(sock,PUBACK,5) < 0) - return -3; - return 1; - - } - //等级2 - if(qos == QOS2) - { - //等待PUBREC - if(WaitForPacket(sock,PUBREC,5) < 0) - return -3; - //发送PUBREL - len = MQTTSerialize_pubrel(buf, buflen,0, packetidbk); - if(len == 0) - return -4; - if(transport_sendPacketBuffer(buf, len) < 0) - return -6; - //等待PUBCOMP - if(WaitForPacket(sock,PUBREC,5) < 0) - return -7; - return 2; - } - //等级错误 - return -8; -} - - -static void *MqttSocketSendTask(void *arg) -{ - - int fd = -1, clientfd; - int recv_len; - int ret; - char *recv_buf; - struct sockaddr_in mqtt_addr; - socklen_t addr_len; - - fd = socket(AF_INET, SOCK_STREAM, 0); - if (fd < 0) { - lw_print("Socket error\n"); - return NULL; - } - - struct sockaddr_in mqtt_sock; - mqtt_sock.sin_family = AF_INET; - mqtt_sock.sin_port = htons(mqtt_socket_port); - mqtt_sock.sin_addr.s_addr = inet_addr(mqtt_ip_str); - - memset(&(mqtt_sock.sin_zero), 0, sizeof(mqtt_sock.sin_zero)); - - ret = connect(fd, (struct sockaddr *)&mqtt_sock, sizeof(struct sockaddr)); - - if (ret < 0) { - lw_print("Unable to connect %s:%d = %d\n", mqtt_ip_str, mqtt_socket_port, ret); - close(fd); - return NULL; - } - - lw_print("MQTT connect %s:%d success, begin to verify hostname and password.\n", mqtt_ip_str, mqtt_socket_port); - - if(MQTT_Connect() != Connect_OK) - { - lw_print("MQTT verify failed.\n"); - shutdown(fd, SHUT_WR); - recv(fd, NULL, (size_t)0, 0); - close(fd); - return NULL; - } - - lw_print("MQTT subscribe begin.\n"); - if(MQTTSubscribe(fd,(char *)TOPIC,QOS1) < 0) - { - lw_print("MQTT subscribe failed.\n"); - shutdown(fd, SHUT_WR); - recv(fd, NULL, (size_t)0, 0); - close(fd); - return NULL; - } - - lw_print("subscribe success.\n"); - - - - uint8_t no_mqtt_msg_exchange = 1; - uint32_t curtick=0; - uint8_t res; - - cJSON* cJSON_Data = NULL; - cJSON_Data = cJSON_Data_Init(); - DHT11_Data_TypeDef* recv_data; - - double a,b; - while(1) - { - curtick+=1; - char* p ="Hello,here is hc"; - ret = MQTTMsgPublish(fd,(char*)TOPIC,QOS0,(uint8_t*)p); - if(ret >= 0) - { - no_mqtt_msg_exchange = 0; - PrivTaskDelay(1000); - } - } -} - - -void MqttSocketSendTest(int argc, char *argv[]) -{ - if(argc >= 2) { - lw_print("lw: [%s] target ip %s\n", __func__, argv[1]); - MqttSocketConfigParam(argv[1]); - } - - - // ip4_addr_t dns_ip; - // netconn_gethostbyname(HOST_NAME, &dns_ip); - // char* host_ip = ip_ntoa(&dns_ip); - // lw_print("host name : %s , host_ip : %s\n",HOST_NAME,host_ip); - // MqttSocketConfigParam(host_ip); - - -#ifdef ADD_XIZI_FEATURES - lwip_config_tcp(0, mqtt_demo_ipaddr, mqtt_demo_netmask, mqtt_demo_gwaddr); - - pthread_attr_t attr; - attr.schedparam.sched_priority = LWIP_MQTT_DEMO_TASK_PRIO; - attr.stacksize = LWIP_MQTT_DEMO_TASK_STACK_SIZE; -#endif - -#ifdef ADD_NUTTX_FEATURES - pthread_attr_t attr = PTHREAD_ATTR_INITIALIZER; - attr.priority = LWIP_mqtt_DEMO_TASK_PRIO; - attr.stacksize = LWIP_mqtt_DEMO_TASK_STACK_SIZE; -#endif - - PrivTaskCreate(&mqtt_client_task, &attr, &MqttSocketSendTask, NULL); - PrivTaskStartup(&mqtt_client_task); -} - -PRIV_SHELL_CMD_FUNCTION(MqttSocketSendTest, a tcp send sample, PRIV_SHELL_CMD_MAIN_ATTR); - diff --git a/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.h b/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.h deleted file mode 100644 index a9870fb66..000000000 --- a/APP_Framework/Applications/connection_app/mqtt_demo/lwip_mqtt_demo.h +++ /dev/null @@ -1,71 +0,0 @@ -#include - -#define MSG_MAX_LEN 1024 -#define MSG_TOPIC_LEN 50 -#define KEEPLIVE_TIME 650 -#define MQTT_VERSION 4 - -#ifdef LWIP_DNS -#define HOST_NAME "iot-06z00im0uwa0ki2.mqtt.iothub.aliyuncs.com" //服务器域名 -#else -#define HOST_NAME "iot-06z00im0uwa0ki2.mqtt.iothub.aliyuncs.com" //服务器IP地址 -#endif - - -//#define HOST_IP "129.204.201.235" -#define HOST_PORT 1883 //由于是TCP连接，端口必须是1883 - -#define CLIENT_ID "iw3rn3pa11K.test|securemode=2,signmethod=hmacsha256,timestamp=1689296035604|" //随机的id -#define USER_NAME "test&iw3rn3pa11K" //用户名 -#define PASSWORD "7b948d22fe46f0f63d1a403376d26e7cb298abc227d29e44311d7040307a71f8" //秘钥 - -#define TOPIC "/iw3rn3pa11K/test/user/Test" //订阅的主题 - -#define TEST_MESSAGE "test_message" //发送测试消息 - -enum QoS -{ QOS0 = 0, - QOS1, - QOS2 -}; - -enum MQTT_Connect -{ - Connect_OK = 0, - Connect_NOK, - Connect_NOTACK -}; - -//数据交互结构体 -typedef struct __MQTTMessage -{ - uint32_t qos; - uint8_t retained; - uint8_t dup; - uint16_t id; - uint8_t type; - void *payload; - int32_t payloadlen; -}MQTTMessage; - -//用户接收消息结构体 -typedef struct __MQTT_MSG -{ - uint8_t msgqos; //消息质量 - uint8_t msg[MSG_MAX_LEN]; //消息 - uint32_t msglenth; //消息长度 - uint8_t topic[MSG_TOPIC_LEN]; //主题 - uint16_t packetid; //消息ID - uint8_t valid; //标明消息是否有效 -}MQTT_USER_MSG; - -//发送消息结构体 -typedef struct -{ - int8_t topic[MSG_TOPIC_LEN]; - int8_t qos; - int8_t retained; - - uint8_t msg[MSG_MAX_LEN]; - uint8_t msglen; -} mqtt_recv_msg_t, *p_mqtt_recv_msg_t, mqtt_send_msg_t, *p_mqtt_send_msg_t; \ No newline at end of file diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnect.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnect.h deleted file mode 100644 index 4d247a3c2..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnect.h +++ /dev/null @@ -1,137 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2014, 2017 IBM Corp. - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * and Eclipse Distribution License v1.0 which accompany this distribution. - * - * The Eclipse Public License is available at - * http://www.eclipse.org/legal/epl-v10.html - * and the Eclipse Distribution License is available at - * http://www.eclipse.org/org/documents/edl-v10.php. - * - * Contributors: - * Ian Craggs - initial API and implementation and/or initial documentation - * Xiang Rong - 442039 Add makefile to Embedded C client - * Ian Craggs - fix for issue #64, bit order in connack response - *******************************************************************************/ - -#ifndef MQTTCONNECT_H_ -#define MQTTCONNECT_H_ - -#if !defined(DLLImport) - #define DLLImport -#endif -#if !defined(DLLExport) - #define DLLExport -#endif - - -typedef union -{ - unsigned char all; /**< all connect flags */ -#if defined(REVERSED) - struct - { - unsigned int username : 1; /**< 3.1 user name */ - unsigned int password : 1; /**< 3.1 password */ - unsigned int willRetain : 1; /**< will retain setting */ - unsigned int willQoS : 2; /**< will QoS value */ - unsigned int will : 1; /**< will flag */ - unsigned int cleansession : 1; /**< clean session flag */ - unsigned int : 1; /**< unused */ - } bits; -#else - struct - { - unsigned int : 1; /**< unused */ - unsigned int cleansession : 1; /**< cleansession flag */ - unsigned int will : 1; /**< will flag */ - unsigned int willQoS : 2; /**< will QoS value */ - unsigned int willRetain : 1; /**< will retain setting */ - unsigned int password : 1; /**< 3.1 password */ - unsigned int username : 1; /**< 3.1 user name */ - } bits; -#endif -} MQTTConnectFlags; /**< connect flags byte */ - - - -/** - * Defines the MQTT "Last Will and Testament" (LWT) settings for - * the connect packet. - */ -typedef struct -{ - /** The eyecatcher for this structure. must be MQTW. */ - char struct_id[4]; - /** The version number of this structure. Must be 0 */ - int struct_version; - /** The LWT topic to which the LWT message will be published. */ - MQTTString topicName; - /** The LWT payload. */ - MQTTString message; - /** - * The retained flag for the LWT message (see MQTTAsync_message.retained). - */ - unsigned char retained; - /** - * The quality of service setting for the LWT message (see - * MQTTAsync_message.qos and @ref qos). - */ - char qos; -} MQTTPacket_willOptions; - - -#define MQTTPacket_willOptions_initializer { {'M', 'Q', 'T', 'W'}, 0, {NULL, {0, NULL}}, {NULL, {0, NULL}}, 0, 0 } - - -typedef struct -{ - /** The eyecatcher for this structure. must be MQTC. */ - char struct_id[4]; - /** The version number of this structure. Must be 0 */ - int struct_version; - /** Version of MQTT to be used. 3 = 3.1 4 = 3.1.1 - */ - unsigned char MQTTVersion; - MQTTString clientID; - unsigned short keepAliveInterval; - unsigned char cleansession; - unsigned char willFlag; - MQTTPacket_willOptions will; - MQTTString username; - MQTTString password; -} MQTTPacket_connectData; - -typedef union -{ - unsigned char all; /**< all connack flags */ -#if defined(REVERSED) - struct - { - unsigned int reserved : 7; /**< unused */ - unsigned int sessionpresent : 1; /**< session present flag */ - } bits; -#else - struct - { - unsigned int sessionpresent : 1; /**< session present flag */ - unsigned int reserved: 7; /**< unused */ - } bits; -#endif -} MQTTConnackFlags; /**< connack flags byte */ - -#define MQTTPacket_connectData_initializer { {'M', 'Q', 'T', 'C'}, 0, 4, {NULL, {0, NULL}}, 60, 1, 0, \ - MQTTPacket_willOptions_initializer, {NULL, {0, NULL}}, {NULL, {0, NULL}} } - -DLLExport int MQTTSerialize_connect(unsigned char* buf, int buflen, MQTTPacket_connectData* options); -DLLExport int MQTTDeserialize_connect(MQTTPacket_connectData* data, unsigned char* buf, int len); - -DLLExport int MQTTSerialize_connack(unsigned char* buf, int buflen, unsigned char connack_rc, unsigned char sessionPresent); -DLLExport int MQTTDeserialize_connack(unsigned char* sessionPresent, unsigned char* connack_rc, unsigned char* buf, int buflen); - -DLLExport int MQTTSerialize_disconnect(unsigned char* buf, int buflen); -DLLExport int MQTTSerialize_pingreq(unsigned char* buf, int buflen); - -#endif /* MQTTCONNECT_H_ */ diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnectClient.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnectClient.c deleted file mode 100644 index 5f3cc2963..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnectClient.c +++ /dev/null @@ -1,214 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2014 IBM Corp. - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * and Eclipse Distribution License v1.0 which accompany this distribution. - * - * The Eclipse Public License is available at - * http://www.eclipse.org/legal/epl-v10.html - * and the Eclipse Distribution License is available at - * http://www.eclipse.org/org/documents/edl-v10.php. - * - * Contributors: - * Ian Craggs - initial API and implementation and/or initial documentation - *******************************************************************************/ - -#include "MQTTPacket.h" -#include "StackTrace.h" - -#include - -/** - * Determines the length of the MQTT connect packet that would be produced using the supplied connect options. - * @param options the options to be used to build the connect packet - * @return the length of buffer needed to contain the serialized version of the packet - */ -int MQTTSerialize_connectLength(MQTTPacket_connectData* options) -{ - int len = 0; - - FUNC_ENTRY; - - if (options->MQTTVersion == 3) - len = 12; /* variable depending on MQTT or MQIsdp */ - else if (options->MQTTVersion == 4) - len = 10; - - len += MQTTstrlen(options->clientID)+2; - if (options->willFlag) - len += MQTTstrlen(options->will.topicName)+2 + MQTTstrlen(options->will.message)+2; - if (options->username.cstring || options->username.lenstring.data) - len += MQTTstrlen(options->username)+2; - if (options->password.cstring || options->password.lenstring.data) - len += MQTTstrlen(options->password)+2; - - FUNC_EXIT_RC(len); - return len; -} - - -/** - * Serializes the connect options into the buffer. - * @param buf the buffer into which the packet will be serialized - * @param len the length in bytes of the supplied buffer - * @param options the options to be used to build the connect packet - * @return serialized length, or error if 0 - */ -int MQTTSerialize_connect(unsigned char* buf, int buflen, MQTTPacket_connectData* options) -{ - unsigned char *ptr = buf; - MQTTHeader header = {0}; - MQTTConnectFlags flags = {0}; - int len = 0; - int rc = -1; - - FUNC_ENTRY; - if (MQTTPacket_len(len = MQTTSerialize_connectLength(options)) > buflen) - { - rc = MQTTPACKET_BUFFER_TOO_SHORT; - goto exit; - } - - header.byte = 0; - header.bits.type = CONNECT; - writeChar(&ptr, header.byte); /* write header */ - - ptr += MQTTPacket_encode(ptr, len); /* write remaining length */ - - if (options->MQTTVersion == 4) - { - writeCString(&ptr, "MQTT"); - writeChar(&ptr, (char) 4); - } - else - { - writeCString(&ptr, "MQIsdp"); - writeChar(&ptr, (char) 3); - } - - flags.all = 0; - flags.bits.cleansession = options->cleansession; - flags.bits.will = (options->willFlag) ? 1 : 0; - if (flags.bits.will) - { - flags.bits.willQoS = options->will.qos; - flags.bits.willRetain = options->will.retained; - } - - if (options->username.cstring || options->username.lenstring.data) - flags.bits.username = 1; - if (options->password.cstring || options->password.lenstring.data) - flags.bits.password = 1; - - writeChar(&ptr, flags.all); - writeInt(&ptr, options->keepAliveInterval); - writeMQTTString(&ptr, options->clientID); - if (options->willFlag) - { - writeMQTTString(&ptr, options->will.topicName); - writeMQTTString(&ptr, options->will.message); - } - if (flags.bits.username) - writeMQTTString(&ptr, options->username); - if (flags.bits.password) - writeMQTTString(&ptr, options->password); - - rc = ptr - buf; - - exit: FUNC_EXIT_RC(rc); - return rc; -} - - -/** - * Deserializes the supplied (wire) buffer into connack data - return code - * @param sessionPresent the session present flag returned (only for MQTT 3.1.1) - * @param connack_rc returned integer value of the connack return code - * @param buf the raw buffer data, of the correct length determined by the remaining length field - * @param len the length in bytes of the data in the supplied buffer - * @return error code. 1 is success, 0 is failure - */ -int MQTTDeserialize_connack(unsigned char* sessionPresent, unsigned char* connack_rc, unsigned char* buf, int buflen) -{ - MQTTHeader header = {0}; - unsigned char* curdata = buf; - unsigned char* enddata = NULL; - int rc = 0; - int mylen; - MQTTConnackFlags flags = {0}; - - FUNC_ENTRY; - header.byte = readChar(&curdata); - if (header.bits.type != CONNACK) - goto exit; - - curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ - enddata = curdata + mylen; - if (enddata - curdata < 2) - goto exit; - - flags.all = readChar(&curdata); - *sessionPresent = flags.bits.sessionpresent; - *connack_rc = readChar(&curdata); - - rc = 1; -exit: - FUNC_EXIT_RC(rc); - return rc; -} - - -/** - * Serializes a 0-length packet into the supplied buffer, ready for writing to a socket - * @param buf the buffer into which the packet will be serialized - * @param buflen the length in bytes of the supplied buffer, to avoid overruns - * @param packettype the message type - * @return serialized length, or error if 0 - */ -int MQTTSerialize_zero(unsigned char* buf, int buflen, unsigned char packettype) -{ - MQTTHeader header = {0}; - int rc = -1; - unsigned char *ptr = buf; - - FUNC_ENTRY; - if (buflen < 2) - { - rc = MQTTPACKET_BUFFER_TOO_SHORT; - goto exit; - } - header.byte = 0; - header.bits.type = packettype; - writeChar(&ptr, header.byte); /* write header */ - - ptr += MQTTPacket_encode(ptr, 0); /* write remaining length */ - rc = ptr - buf; -exit: - FUNC_EXIT_RC(rc); - return rc; -} - - -/** - * Serializes a disconnect packet into the supplied buffer, ready for writing to a socket - * @param buf the buffer into which the packet will be serialized - * @param buflen the length in bytes of the supplied buffer, to avoid overruns - * @return serialized length, or error if 0 - */ -int MQTTSerialize_disconnect(unsigned char* buf, int buflen) -{ - return MQTTSerialize_zero(buf, buflen, DISCONNECT); -} - - -/** - * Serializes a disconnect packet into the supplied buffer, ready for writing to a socket - * @param buf the buffer into which the packet will be serialized - * @param buflen the length in bytes of the supplied buffer, to avoid overruns - * @return serialized length, or error if 0 - */ -int MQTTSerialize_pingreq(unsigned char* buf, int buflen) -{ - return MQTTSerialize_zero(buf, buflen, PINGREQ); -} diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnectServer.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnectServer.c deleted file mode 100644 index 07c7cb537..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTConnectServer.c +++ /dev/null @@ -1,148 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2014 IBM Corp. - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * and Eclipse Distribution License v1.0 which accompany this distribution. - * - * The Eclipse Public License is available at - * http://www.eclipse.org/legal/epl-v10.html - * and the Eclipse Distribution License is available at - * http://www.eclipse.org/org/documents/edl-v10.php. - * - * Contributors: - * Ian Craggs - initial API and implementation and/or initial documentation - *******************************************************************************/ - -#include "StackTrace.h" -#include "MQTTPacket.h" -#include - -#define min(a, b) ((a < b) ? a : b) - - -/** - * Validates MQTT protocol name and version combinations - * @param protocol the MQTT protocol name as an MQTTString - * @param version the MQTT protocol version number, as in the connect packet - * @return correct MQTT combination? 1 is true, 0 is false - */ -int MQTTPacket_checkVersion(MQTTString* protocol, int version) -{ - int rc = 0; - - if (version == 3 && memcmp(protocol->lenstring.data, "MQIsdp", - min(6, protocol->lenstring.len)) == 0) - rc = 1; - else if (version == 4 && memcmp(protocol->lenstring.data, "MQTT", - min(4, protocol->lenstring.len)) == 0) - rc = 1; - return rc; -} - - -/** - * Deserializes the supplied (wire) buffer into connect data structure - * @param data the connect data structure to be filled out - * @param buf the raw buffer data, of the correct length determined by the remaining length field - * @param len the length in bytes of the data in the supplied buffer - * @return error code. 1 is success, 0 is failure - */ -int MQTTDeserialize_connect(MQTTPacket_connectData* data, unsigned char* buf, int len) -{ - MQTTHeader header = {0}; - MQTTConnectFlags flags = {0}; - unsigned char* curdata = buf; - unsigned char* enddata = &buf[len]; - int rc = 0; - MQTTString Protocol; - int version; - int mylen = 0; - - FUNC_ENTRY; - header.byte = readChar(&curdata); - if (header.bits.type != CONNECT) - goto exit; - - curdata += MQTTPacket_decodeBuf(curdata, &mylen); /* read remaining length */ - - if (!readMQTTLenString(&Protocol, &curdata, enddata) || - enddata - curdata < 0) /* do we have enough data to read the protocol version byte? */ - goto exit; - - version = (int)readChar(&curdata); /* Protocol version */ - /* If we don't recognize the protocol version, we don't parse the connect packet on the - * basis that we don't know what the format will be. - */ - if (MQTTPacket_checkVersion(&Protocol, version)) - { - flags.all = readChar(&curdata); - data->cleansession = flags.bits.cleansession; - data->keepAliveInterval = readInt(&curdata); - if (!readMQTTLenString(&data->clientID, &curdata, enddata)) - goto exit; - data->willFlag = flags.bits.will; - if (flags.bits.will) - { - data->will.qos = flags.bits.willQoS; - data->will.retained = flags.bits.willRetain; - if (!readMQTTLenString(&data->will.topicName, &curdata, enddata) || - !readMQTTLenString(&data->will.message, &curdata, enddata)) - goto exit; - } - if (flags.bits.username) - { - if (enddata - curdata < 3 || !readMQTTLenString(&data->username, &curdata, enddata)) - goto exit; /* username flag set, but no username supplied - invalid */ - if (flags.bits.password && - (enddata - curdata < 3 || !readMQTTLenString(&data->password, &curdata, enddata))) - goto exit; /* password flag set, but no password supplied - invalid */ - } - else if (flags.bits.password) - goto exit; /* password flag set without username - invalid */ - rc = 1; - } -exit: - FUNC_EXIT_RC(rc); - return rc; -} - - -/** - * Serializes the connack packet into the supplied buffer. - * @param buf the buffer into which the packet will be serialized - * @param buflen the length in bytes of the supplied buffer - * @param connack_rc the integer connack return code to be used - * @param sessionPresent the MQTT 3.1.1 sessionPresent flag - * @return serialized length, or error if 0 - */ -int MQTTSerialize_connack(unsigned char* buf, int buflen, unsigned char connack_rc, unsigned char sessionPresent) -{ - MQTTHeader header = {0}; - int rc = 0; - unsigned char *ptr = buf; - MQTTConnackFlags flags = {0}; - - FUNC_ENTRY; - if (buflen < 2) - { - rc = MQTTPACKET_BUFFER_TOO_SHORT; - goto exit; - } - header.byte = 0; - header.bits.type = CONNACK; - writeChar(&ptr, header.byte); /* write header */ - - ptr += MQTTPacket_encode(ptr, 2); /* write remaining length */ - - flags.all = 0; - flags.bits.sessionpresent = sessionPresent; - writeChar(&ptr, flags.all); - writeChar(&ptr, connack_rc); - - rc = ptr - buf; -exit: - FUNC_EXIT_RC(rc); - return rc; -} - diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTDeserializePublish.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTDeserializePublish.c deleted file mode 100644 index 5014c46d3..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTDeserializePublish.c +++ /dev/null @@ -1,107 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2014 IBM Corp. - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * and Eclipse Distribution License v1.0 which accompany this distribution. - * - * The Eclipse Public License is available at - * http://www.eclipse.org/legal/epl-v10.html - * and the Eclipse Distribution License is available at - * http://www.eclipse.org/org/documents/edl-v10.php. - * - * Contributors: - * Ian Craggs - initial API and implementation and/or initial documentation - *******************************************************************************/ - -#include "StackTrace.h" -#include "MQTTPacket.h" -#include - -#define min(a, b) ((a < b) ? 1 : 0) - -/** - * Deserializes the supplied (wire) buffer into publish data - * @param dup returned integer - the MQTT dup flag - * @param qos returned integer - the MQTT QoS value - * @param retained returned integer - the MQTT retained flag - * @param packetid returned integer - the MQTT packet identifier - * @param topicName returned MQTTString - the MQTT topic in the publish - * @param payload returned byte buffer - the MQTT publish payload - * @param payloadlen returned integer - the length of the MQTT payload - * @param buf the raw buffer data, of the correct length determined by the remaining length field - * @param buflen the length in bytes of the data in the supplied buffer - * @return error code. 1 is success - */ -int MQTTDeserialize_publish(unsigned char* dup, int* qos, unsigned char* retained, unsigned short* packetid, MQTTString* topicName, - unsigned char** payload, int32_t* payloadlen, unsigned char* buf, int buflen) -{ - MQTTHeader header = {0}; - unsigned char* curdata = buf; - unsigned char* enddata = NULL; - int rc = 0; - int mylen = 0; - - FUNC_ENTRY; - header.byte = readChar(&curdata); - if (header.bits.type != PUBLISH) - goto exit; - *dup = header.bits.dup; - *qos = header.bits.qos; - *retained = header.bits.retain; - - curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ - enddata = curdata + mylen; - - if (!readMQTTLenString(topicName, &curdata, enddata) || - enddata - curdata < 0) /* do we have enough data to read the protocol version byte? */ - goto exit; - - if (*qos > 0) - *packetid = readInt(&curdata); - - *payloadlen = enddata - curdata; - *payload = curdata; - rc = 1; -exit: - FUNC_EXIT_RC(rc); - return rc; -} - - - -/** - * Deserializes the supplied (wire) buffer into an ack - * @param packettype returned integer - the MQTT packet type - * @param dup returned integer - the MQTT dup flag - * @param packetid returned integer - the MQTT packet identifier - * @param buf the raw buffer data, of the correct length determined by the remaining length field - * @param buflen the length in bytes of the data in the supplied buffer - * @return error code. 1 is success, 0 is failure - */ -int MQTTDeserialize_ack(unsigned char* packettype, unsigned char* dup, unsigned short* packetid, unsigned char* buf, int buflen) -{ - MQTTHeader header = {0}; - unsigned char* curdata = buf; - unsigned char* enddata = NULL; - int rc = 0; - int mylen; - - FUNC_ENTRY; - header.byte = readChar(&curdata); - *dup = header.bits.dup; - *packettype = header.bits.type; - - curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ - enddata = curdata + mylen; - - if (enddata - curdata < 2) - goto exit; - *packetid = readInt(&curdata); - - rc = 1; -exit: - FUNC_EXIT_RC(rc); - return rc; -} - diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTFormat.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTFormat.c deleted file mode 100644 index 2eff31f89..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTFormat.c +++ /dev/null @@ -1,262 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2014 IBM Corp. - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * and Eclipse Distribution License v1.0 which accompany this distribution. - * - * The Eclipse Public License is available at - * http://www.eclipse.org/legal/epl-v10.html - * and the Eclipse Distribution License is available at - * http://www.eclipse.org/org/documents/edl-v10.php. - * - * Contributors: - * Ian Craggs - initial API and implementation and/or initial documentation - *******************************************************************************/ - -#include "StackTrace.h" -#include "MQTTPacket.h" - -#include - - -const char* MQTTPacket_names[] = -{ - "RESERVED", "CONNECT", "CONNACK", "PUBLISH", "PUBACK", "PUBREC", "PUBREL", - "PUBCOMP", "SUBSCRIBE", "SUBACK", "UNSUBSCRIBE", "UNSUBACK", - "PINGREQ", "PINGRESP", "DISCONNECT" -}; - - -const char* MQTTPacket_getName(unsigned short packetid) -{ - return MQTTPacket_names[packetid]; -} - - -int MQTTStringFormat_connect(char* strbuf, int strbuflen, MQTTPacket_connectData* data) -{ - int strindex = 0; - - strindex = snprintf(strbuf, strbuflen, - "CONNECT MQTT version %d, client id %.*s, clean session %d, keep alive %d", - (int)data->MQTTVersion, data->clientID.lenstring.len, data->clientID.lenstring.data, - (int)data->cleansession, data->keepAliveInterval); - if (data->willFlag) - strindex += snprintf(&strbuf[strindex], strbuflen - strindex, - ", will QoS %d, will retain %d, will topic %.*s, will message %.*s", - data->will.qos, data->will.retained, - data->will.topicName.lenstring.len, data->will.topicName.lenstring.data, - data->will.message.lenstring.len, data->will.message.lenstring.data); - if (data->username.lenstring.data && data->username.lenstring.len > 0) - strindex += snprintf(&strbuf[strindex], strbuflen - strindex, - ", user name %.*s", data->username.lenstring.len, data->username.lenstring.data); - if (data->password.lenstring.data && data->password.lenstring.len > 0) - strindex += snprintf(&strbuf[strindex], strbuflen - strindex, - ", password %.*s", data->password.lenstring.len, data->password.lenstring.data); - return strindex; -} - - -int MQTTStringFormat_connack(char* strbuf, int strbuflen, unsigned char connack_rc, unsigned char sessionPresent) -{ - int strindex = snprintf(strbuf, strbuflen, "CONNACK session present %d, rc %d", sessionPresent, connack_rc); - return strindex; -} - - -int MQTTStringFormat_publish(char* strbuf, int strbuflen, unsigned char dup, int qos, unsigned char retained, - unsigned short packetid, MQTTString topicName, unsigned char* payload, int payloadlen) -{ - int strindex = snprintf(strbuf, strbuflen, - "PUBLISH dup %d, QoS %d, retained %d, packet id %d, topic %.*s, payload length %d, payload %.*s", - dup, qos, retained, packetid, - (topicName.lenstring.len < 20) ? topicName.lenstring.len : 20, topicName.lenstring.data, - payloadlen, (payloadlen < 20) ? payloadlen : 20, payload); - return strindex; -} - - -int MQTTStringFormat_ack(char* strbuf, int strbuflen, unsigned char packettype, unsigned char dup, unsigned short packetid) -{ - int strindex = snprintf(strbuf, strbuflen, "%s, packet id %d", MQTTPacket_names[packettype], packetid); - if (dup) - strindex += snprintf(strbuf + strindex, strbuflen - strindex, ", dup %d", dup); - return strindex; -} - - -int MQTTStringFormat_subscribe(char* strbuf, int strbuflen, unsigned char dup, unsigned short packetid, int count, - MQTTString topicFilters[], int requestedQoSs[]) -{ - return snprintf(strbuf, strbuflen, - "SUBSCRIBE dup %d, packet id %d count %d topic %.*s qos %d", - dup, packetid, count, - topicFilters[0].lenstring.len, topicFilters[0].lenstring.data, - requestedQoSs[0]); -} - - -int MQTTStringFormat_suback(char* strbuf, int strbuflen, unsigned short packetid, int count, int* grantedQoSs) -{ - return snprintf(strbuf, strbuflen, - "SUBACK packet id %d count %d granted qos %d", packetid, count, grantedQoSs[0]); -} - - -int MQTTStringFormat_unsubscribe(char* strbuf, int strbuflen, unsigned char dup, unsigned short packetid, - int count, MQTTString topicFilters[]) -{ - return snprintf(strbuf, strbuflen, - "UNSUBSCRIBE dup %d, packet id %d count %d topic %.*s", - dup, packetid, count, - topicFilters[0].lenstring.len, topicFilters[0].lenstring.data); -} - - -#if defined(MQTT_CLIENT) -char* MQTTFormat_toClientString(char* strbuf, int strbuflen, unsigned char* buf, int buflen) -{ - int index = 0; - int rem_length = 0; - MQTTHeader header = {0}; - int strindex = 0; - - header.byte = buf[index++]; - index += MQTTPacket_decodeBuf(&buf[index], &rem_length); - - switch (header.bits.type) - { - - case CONNACK: - { - unsigned char sessionPresent, connack_rc; - if (MQTTDeserialize_connack(&sessionPresent, &connack_rc, buf, buflen) == 1) - strindex = MQTTStringFormat_connack(strbuf, strbuflen, connack_rc, sessionPresent); - } - break; - case PUBLISH: - { - unsigned char dup, retained, *payload; - unsigned short packetid; - int qos, payloadlen; - MQTTString topicName = MQTTString_initializer; - if (MQTTDeserialize_publish(&dup, &qos, &retained, &packetid, &topicName, - &payload, &payloadlen, buf, buflen) == 1) - strindex = MQTTStringFormat_publish(strbuf, strbuflen, dup, qos, retained, packetid, - topicName, payload, payloadlen); - } - break; - case PUBACK: - case PUBREC: - case PUBREL: - case PUBCOMP: - { - unsigned char packettype, dup; - unsigned short packetid; - if (MQTTDeserialize_ack(&packettype, &dup, &packetid, buf, buflen) == 1) - strindex = MQTTStringFormat_ack(strbuf, strbuflen, packettype, dup, packetid); - } - break; - case SUBACK: - { - unsigned short packetid; - int maxcount = 1, count = 0; - int grantedQoSs[1]; - if (MQTTDeserialize_suback(&packetid, maxcount, &count, grantedQoSs, buf, buflen) == 1) - strindex = MQTTStringFormat_suback(strbuf, strbuflen, packetid, count, grantedQoSs); - } - break; - case UNSUBACK: - { - unsigned short packetid; - if (MQTTDeserialize_unsuback(&packetid, buf, buflen) == 1) - strindex = MQTTStringFormat_ack(strbuf, strbuflen, UNSUBACK, 0, packetid); - } - break; - case PINGREQ: - case PINGRESP: - case DISCONNECT: - strindex = snprintf(strbuf, strbuflen, "%s", MQTTPacket_names[header.bits.type]); - break; - } - return strbuf; -} -#endif - -#if defined(MQTT_SERVER) -char* MQTTFormat_toServerString(char* strbuf, int strbuflen, unsigned char* buf, int buflen) -{ - int index = 0; - int rem_length = 0; - MQTTHeader header = {0}; - int strindex = 0; - - header.byte = buf[index++]; - index += MQTTPacket_decodeBuf(&buf[index], &rem_length); - - switch (header.bits.type) - { - case CONNECT: - { - MQTTPacket_connectData data; - int rc; - if ((rc = MQTTDeserialize_connect(&data, buf, buflen)) == 1) - strindex = MQTTStringFormat_connect(strbuf, strbuflen, &data); - } - break; - case PUBLISH: - { - unsigned char dup, retained, *payload; - unsigned short packetid; - int qos, payloadlen; - MQTTString topicName = MQTTString_initializer; - if (MQTTDeserialize_publish(&dup, &qos, &retained, &packetid, &topicName, - &payload, &payloadlen, buf, buflen) == 1) - strindex = MQTTStringFormat_publish(strbuf, strbuflen, dup, qos, retained, packetid, - topicName, payload, payloadlen); - } - break; - case PUBACK: - case PUBREC: - case PUBREL: - case PUBCOMP: - { - unsigned char packettype, dup; - unsigned short packetid; - if (MQTTDeserialize_ack(&packettype, &dup, &packetid, buf, buflen) == 1) - strindex = MQTTStringFormat_ack(strbuf, strbuflen, packettype, dup, packetid); - } - break; - case SUBSCRIBE: - { - unsigned char dup; - unsigned short packetid; - int maxcount = 1, count = 0; - MQTTString topicFilters[1]; - int requestedQoSs[1]; - if (MQTTDeserialize_subscribe(&dup, &packetid, maxcount, &count, - topicFilters, requestedQoSs, buf, buflen) == 1) - strindex = MQTTStringFormat_subscribe(strbuf, strbuflen, dup, packetid, count, topicFilters, requestedQoSs);; - } - break; - case UNSUBSCRIBE: - { - unsigned char dup; - unsigned short packetid; - int maxcount = 1, count = 0; - MQTTString topicFilters[1]; - if (MQTTDeserialize_unsubscribe(&dup, &packetid, maxcount, &count, topicFilters, buf, buflen) == 1) - strindex = MQTTStringFormat_unsubscribe(strbuf, strbuflen, dup, packetid, count, topicFilters); - } - break; - case PINGREQ: - case PINGRESP: - case DISCONNECT: - strindex = snprintf(strbuf, strbuflen, "%s", MQTTPacket_names[header.bits.type]); - break; - } - strbuf[strbuflen] = '\0'; - return strbuf; -} -#endif diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTFormat.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTFormat.h deleted file mode 100644 index 47b0c4143..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTFormat.h +++ /dev/null @@ -1,37 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2014 IBM Corp. - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * and Eclipse Distribution License v1.0 which accompany this distribution. - * - * The Eclipse Public License is available at - * http://www.eclipse.org/legal/epl-v10.html - * and the Eclipse Distribution License is available at - * http://www.eclipse.org/org/documents/edl-v10.php. - * - * Contributors: - * Ian Craggs - initial API and implementation and/or initial documentation - *******************************************************************************/ - -#if !defined(MQTTFORMAT_H) -#define MQTTFORMAT_H - -#include "StackTrace.h" -#include "MQTTPacket.h" - -const char* MQTTPacket_getName(unsigned short packetid); -int MQTTStringFormat_connect(char* strbuf, int strbuflen, MQTTPacket_connectData* data); -int MQTTStringFormat_connack(char* strbuf, int strbuflen, unsigned char connack_rc, unsigned char sessionPresent); -int MQTTStringFormat_publish(char* strbuf, int strbuflen, unsigned char dup, int qos, unsigned char retained, - unsigned short packetid, MQTTString topicName, unsigned char* payload, int payloadlen); -int MQTTStringFormat_ack(char* strbuf, int strbuflen, unsigned char packettype, unsigned char dup, unsigned short packetid); -int MQTTStringFormat_subscribe(char* strbuf, int strbuflen, unsigned char dup, unsigned short packetid, int count, - MQTTString topicFilters[], int requestedQoSs[]); -int MQTTStringFormat_suback(char* strbuf, int strbuflen, unsigned short packetid, int count, int* grantedQoSs); -int MQTTStringFormat_unsubscribe(char* strbuf, int strbuflen, unsigned char dup, unsigned short packetid, - int count, MQTTString topicFilters[]); -char* MQTTFormat_toClientString(char* strbuf, int strbuflen, unsigned char* buf, int buflen); -char* MQTTFormat_toServerString(char* strbuf, int strbuflen, unsigned char* buf, int buflen); - -#endif diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPacket.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPacket.c deleted file mode 100644 index 4f1f95a78..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPacket.c +++ /dev/null @@ -1,412 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2014 IBM Corp. - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * and Eclipse Distribution License v1.0 which accompany this distribution. - * - * The Eclipse Public License is available at - * http://www.eclipse.org/legal/epl-v10.html - * and the Eclipse Distribution License is available at - * http://www.eclipse.org/org/documents/edl-v10.php. - * - * Contributors: - * Ian Craggs - initial API and implementation and/or initial documentation - * Sergio R. Caprile - non-blocking packet read functions for stream transport - *******************************************************************************/ - -#include "StackTrace.h" -#include "MQTTPacket.h" - -#include - -/** - * Encodes the message length according to the MQTT algorithm - * @param buf the buffer into which the encoded data is written - * @param length the length to be encoded - * @return the number of bytes written to buffer - */ -int MQTTPacket_encode(unsigned char* buf, int length) -{ - int rc = 0; - - FUNC_ENTRY; - do - { - char d = length % 128; - length /= 128; - /* if there are more digits to encode, set the top bit of this digit */ - if (length > 0) - d |= 0x80; - buf[rc++] = d; - } while (length > 0); - FUNC_EXIT_RC(rc); - return rc; -} - - -/** - * Decodes the message length according to the MQTT algorithm - * @param getcharfn pointer to function to read the next character from the data source - * @param value the decoded length returned - * @return the number of bytes read from the socket - */ -int MQTTPacket_decode(int (*getcharfn)(unsigned char*, int), int* value) -{ - unsigned char c; - int multiplier = 1; - int len = 0; -#define MAX_NO_OF_REMAINING_LENGTH_BYTES 4 - - FUNC_ENTRY; - *value = 0; - do - { - int rc = MQTTPACKET_READ_ERROR; - - if (++len > MAX_NO_OF_REMAINING_LENGTH_BYTES) - { - rc = MQTTPACKET_READ_ERROR; /* bad data */ - goto exit; - } - rc = (*getcharfn)(&c, 1); - if (rc != 1) - goto exit; - *value += (c & 127) * multiplier; - multiplier *= 128; - } while ((c & 128) != 0); -exit: - FUNC_EXIT_RC(len); - return len; -} - - -int MQTTPacket_len(int rem_len) -{ - rem_len += 1; /* header byte */ - - /* now remaining_length field */ - if (rem_len < 128) - rem_len += 1; - else if (rem_len < 16384) - rem_len += 2; - else if (rem_len < 2097151) - rem_len += 3; - else - rem_len += 4; - return rem_len; -} - - -static unsigned char* bufptr; - -int bufchar(unsigned char* c, int count) -{ - int i; - - for (i = 0; i < count; ++i) - *c = *bufptr++; - return count; -} - - -int MQTTPacket_decodeBuf(unsigned char* buf, int* value) -{ - bufptr = buf; - return MQTTPacket_decode(bufchar, value); -} - - -/** - * Calculates an integer from two bytes read from the input buffer - * @param pptr pointer to the input buffer - incremented by the number of bytes used & returned - * @return the integer value calculated - */ -int readInt(unsigned char** pptr) -{ - unsigned char* ptr = *pptr; - int len = 256*(*ptr) + (*(ptr+1)); - *pptr += 2; - return len; -} - - -/** - * Reads one character from the input buffer. - * @param pptr pointer to the input buffer - incremented by the number of bytes used & returned - * @return the character read - */ -char readChar(unsigned char** pptr) -{ - char c = **pptr; - (*pptr)++; - return c; -} - - -/** - * Writes one character to an output buffer. - * @param pptr pointer to the output buffer - incremented by the number of bytes used & returned - * @param c the character to write - */ -void writeChar(unsigned char** pptr, char c) -{ - **pptr = c; - (*pptr)++; -} - - -/** - * Writes an integer as 2 bytes to an output buffer. - * @param pptr pointer to the output buffer - incremented by the number of bytes used & returned - * @param anInt the integer to write - */ -void writeInt(unsigned char** pptr, int anInt) -{ - **pptr = (unsigned char)(anInt / 256); - (*pptr)++; - **pptr = (unsigned char)(anInt % 256); - (*pptr)++; -} - - -/** - * Writes a "UTF" string to an output buffer. Converts C string to length-delimited. - * @param pptr pointer to the output buffer - incremented by the number of bytes used & returned - * @param string the C string to write - */ -void writeCString(unsigned char** pptr, const char* string) -{ - int len = strlen(string); - writeInt(pptr, len); - memcpy(*pptr, string, len); - *pptr += len; -} - - -int getLenStringLen(char* ptr) -{ - int len = 256*((unsigned char)(*ptr)) + (unsigned char)(*(ptr+1)); - return len; -} - - -void writeMQTTString(unsigned char** pptr, MQTTString mqttstring) -{ - if (mqttstring.lenstring.len > 0) - { - writeInt(pptr, mqttstring.lenstring.len); - memcpy(*pptr, mqttstring.lenstring.data, mqttstring.lenstring.len); - *pptr += mqttstring.lenstring.len; - } - else if (mqttstring.cstring) - writeCString(pptr, mqttstring.cstring); - else - writeInt(pptr, 0); -} - - -/** - * @param mqttstring the MQTTString structure into which the data is to be read - * @param pptr pointer to the output buffer - incremented by the number of bytes used & returned - * @param enddata pointer to the end of the data: do not read beyond - * @return 1 if successful, 0 if not - */ -int readMQTTLenString(MQTTString* mqttstring, unsigned char** pptr, unsigned char* enddata) -{ - int rc = 0; - - FUNC_ENTRY; - /* the first two bytes are the length of the string */ - if (enddata - (*pptr) > 1) /* enough length to read the integer? */ - { - mqttstring->lenstring.len = readInt(pptr); /* increments pptr to point past length */ - if (&(*pptr)[mqttstring->lenstring.len] <= enddata) - { - mqttstring->lenstring.data = (char*)*pptr; - *pptr += mqttstring->lenstring.len; - rc = 1; - } - } - mqttstring->cstring = NULL; - FUNC_EXIT_RC(rc); - return rc; -} - - -/** - * Return the length of the MQTTstring - C string if there is one, otherwise the length delimited string - * @param mqttstring the string to return the length of - * @return the length of the string - */ -int MQTTstrlen(MQTTString mqttstring) -{ - int rc = 0; - - if (mqttstring.cstring) - rc = strlen(mqttstring.cstring); - else - rc = mqttstring.lenstring.len; - return rc; -} - - -/** - * Compares an MQTTString to a C string - * @param a the MQTTString to compare - * @param bptr the C string to compare - * @return boolean - equal or not - */ -int MQTTPacket_equals(MQTTString* a, char* bptr) -{ - int alen = 0, - blen = 0; - char *aptr; - - if (a->cstring) - { - aptr = a->cstring; - alen = strlen(a->cstring); - } - else - { - aptr = a->lenstring.data; - alen = a->lenstring.len; - } - blen = strlen(bptr); - - return (alen == blen) && (strncmp(aptr, bptr, alen) == 0); -} - - -/** - * Helper function to read packet data from some source into a buffer - * @param buf the buffer into which the packet will be serialized - * @param buflen the length in bytes of the supplied buffer - * @param getfn pointer to a function which will read any number of bytes from the needed source - * @return integer MQTT packet type, or -1 on error - * @note the whole message must fit into the caller's buffer - */ -int MQTTPacket_read(unsigned char* buf, int buflen, int (*getfn)(unsigned char*, int)) -{ - int rc = -1; - MQTTHeader header = {0}; - int len = 0; - int rem_len = 0; - - /* 1. read the header byte. This has the packet type in it */ - if ((*getfn)(buf, 1) != 1) - goto exit; - - len = 1; - /* 2. read the remaining length. This is variable in itself */ - MQTTPacket_decode(getfn, &rem_len); - len += MQTTPacket_encode(buf + 1, rem_len); /* put the original remaining length back into the buffer */ - - /* 3. read the rest of the buffer using a callback to supply the rest of the data */ - if((rem_len + len) > buflen) - goto exit; - if (rem_len && ((*getfn)(buf + len, rem_len) != rem_len)) - goto exit; - - header.byte = buf[0]; - rc = header.bits.type; -exit: - return rc; -} - -/** - * Decodes the message length according to the MQTT algorithm, non-blocking - * @param trp pointer to a transport structure holding what is needed to solve getting data from it - * @param value the decoded length returned - * @return integer the number of bytes read from the socket, 0 for call again, or -1 on error - */ -static int MQTTPacket_decodenb(MQTTTransport *trp) -{ - unsigned char c; - int rc = MQTTPACKET_READ_ERROR; - - FUNC_ENTRY; - if(trp->len == 0){ /* initialize on first call */ - trp->multiplier = 1; - trp->rem_len = 0; - } - do { - int frc; - if (trp->len >= MAX_NO_OF_REMAINING_LENGTH_BYTES) - goto exit; - if ((frc=(*trp->getfn)(trp->sck, &c, 1)) == -1) - goto exit; - if (frc == 0){ - rc = 0; - goto exit; - } - ++(trp->len); - trp->rem_len += (c & 127) * trp->multiplier; - trp->multiplier *= 128; - } while ((c & 128) != 0); - rc = trp->len; -exit: - FUNC_EXIT_RC(rc); - return rc; -} - -/** - * Helper function to read packet data from some source into a buffer, non-blocking - * @param buf the buffer into which the packet will be serialized - * @param buflen the length in bytes of the supplied buffer - * @param trp pointer to a transport structure holding what is needed to solve getting data from it - * @return integer MQTT packet type, 0 for call again, or -1 on error - * @note the whole message must fit into the caller's buffer - */ -int MQTTPacket_readnb(unsigned char* buf, int buflen, MQTTTransport *trp) -{ - int rc = -1, frc; - MQTTHeader header = {0}; - - switch(trp->state){ - default: - trp->state = 0; - /*FALLTHROUGH*/ - case 0: - /* read the header byte. This has the packet type in it */ - if ((frc=(*trp->getfn)(trp->sck, buf, 1)) == -1) - goto exit; - if (frc == 0) - return 0; - trp->len = 0; - ++trp->state; - /*FALLTHROUGH*/ - /* read the remaining length. This is variable in itself */ - case 1: - if((frc=MQTTPacket_decodenb(trp)) == MQTTPACKET_READ_ERROR) - goto exit; - if(frc == 0) - return 0; - trp->len = 1 + MQTTPacket_encode(buf + 1, trp->rem_len); /* put the original remaining length back into the buffer */ - if((trp->rem_len + trp->len) > buflen) - goto exit; - ++trp->state; - /*FALLTHROUGH*/ - case 2: - if(trp->rem_len){ - /* read the rest of the buffer using a callback to supply the rest of the data */ - if ((frc=(*trp->getfn)(trp->sck, buf + trp->len, trp->rem_len)) == -1) - goto exit; - if (frc == 0) - return 0; - trp->rem_len -= frc; - trp->len += frc; - if(trp->rem_len) - return 0; - } - header.byte = buf[0]; - rc = header.bits.type; - break; - } - -exit: - trp->state = 0; - return rc; -} - diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPacket.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPacket.h deleted file mode 100644 index a1c5038d8..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPacket.h +++ /dev/null @@ -1,134 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2014 IBM Corp. - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * and Eclipse Distribution License v1.0 which accompany this distribution. - * - * The Eclipse Public License is available at - * http://www.eclipse.org/legal/epl-v10.html - * and the Eclipse Distribution License is available at - * http://www.eclipse.org/org/documents/edl-v10.php. - * - * Contributors: - * Ian Craggs - initial API and implementation and/or initial documentation - * Xiang Rong - 442039 Add makefile to Embedded C client - *******************************************************************************/ -#include - -#ifndef MQTTPACKET_H_ -#define MQTTPACKET_H_ - -#if defined(__cplusplus) /* If this is a C++ compiler, use C linkage */ -extern "C" { -#endif - -#if defined(WIN32_DLL) || defined(WIN64_DLL) - #define DLLImport __declspec(dllimport) - #define DLLExport __declspec(dllexport) -#elif defined(LINUX_SO) - #define DLLImport extern - #define DLLExport __attribute__ ((visibility ("default"))) -#else - #define DLLImport - #define DLLExport -#endif - -enum errors -{ - MQTTPACKET_BUFFER_TOO_SHORT = -2, - MQTTPACKET_READ_ERROR = -1, - MQTTPACKET_READ_COMPLETE -}; - -enum msgTypes -{ - CONNECT = 1, CONNACK, PUBLISH, PUBACK, PUBREC, PUBREL, - PUBCOMP, SUBSCRIBE, SUBACK, UNSUBSCRIBE, UNSUBACK, - PINGREQ, PINGRESP, DISCONNECT -}; - -/** - * Bitfields for the MQTT header byte. - */ -typedef union -{ - unsigned char byte; /**< the whole byte */ -#if defined(REVERSED) - struct - { - unsigned int type : 4; /**< message type nibble */ - unsigned int dup : 1; /**< DUP flag bit */ - unsigned int qos : 2; /**< QoS value, 0, 1 or 2 */ - unsigned int retain : 1; /**< retained flag bit */ - } bits; -#else - struct - { - unsigned int retain : 1; /**< retained flag bit */ - unsigned int qos : 2; /**< QoS value, 0, 1 or 2 */ - unsigned int dup : 1; /**< DUP flag bit */ - unsigned int type : 4; /**< message type nibble */ - } bits; -#endif -} MQTTHeader; - -typedef struct -{ - int len; - char* data; -} MQTTLenString; - -typedef struct -{ - char* cstring; - MQTTLenString lenstring; -} MQTTString; - -#define MQTTString_initializer {NULL, {0, NULL}} - -int MQTTstrlen(MQTTString mqttstring); - -#include "MQTTConnect.h" -#include "MQTTPublish.h" -#include "MQTTSubscribe.h" -#include "MQTTUnsubscribe.h" -#include "MQTTFormat.h" - -DLLExport int MQTTSerialize_ack(unsigned char* buf, int buflen, unsigned char type, unsigned char dup, unsigned short packetid); -DLLExport int MQTTDeserialize_ack(unsigned char* packettype, unsigned char* dup, unsigned short* packetid, unsigned char* buf, int buflen); - -int MQTTPacket_len(int rem_len); -DLLExport int MQTTPacket_equals(MQTTString* a, char* b); - -DLLExport int MQTTPacket_encode(unsigned char* buf, int length); -int MQTTPacket_decode(int (*getcharfn)(unsigned char*, int), int* value); -int MQTTPacket_decodeBuf(unsigned char* buf, int* value); - -int readInt(unsigned char** pptr); -char readChar(unsigned char** pptr); -void writeChar(unsigned char** pptr, char c); -void writeInt(unsigned char** pptr, int anInt); -int readMQTTLenString(MQTTString* mqttstring, unsigned char** pptr, unsigned char* enddata); -void writeCString(unsigned char** pptr, const char* string); -void writeMQTTString(unsigned char** pptr, MQTTString mqttstring); - -DLLExport int MQTTPacket_read(unsigned char* buf, int buflen, int (*getfn)(unsigned char*, int)); - -typedef struct { - int (*getfn)(void *, unsigned char*, int); /* must return -1 for error, 0 for call again, or the number of bytes read */ - void *sck; /* pointer to whatever the system may use to identify the transport */ - int multiplier; - int rem_len; - int len; - char state; -}MQTTTransport; - -int MQTTPacket_readnb(unsigned char* buf, int buflen, MQTTTransport *trp); - -#ifdef __cplusplus /* If this is a C++ compiler, use C linkage */ -} -#endif - - -#endif /* MQTTPACKET_H_ */ diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPublish.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPublish.h deleted file mode 100644 index 88aca927e..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTPublish.h +++ /dev/null @@ -1,38 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2014 IBM Corp. - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * and Eclipse Distribution License v1.0 which accompany this distribution. - * - * The Eclipse Public License is available at - * http://www.eclipse.org/legal/epl-v10.html - * and the Eclipse Distribution License is available at - * http://www.eclipse.org/org/documents/edl-v10.php. - * - * Contributors: - * Ian Craggs - initial API and implementation and/or initial documentation - * Xiang Rong - 442039 Add makefile to Embedded C client - *******************************************************************************/ - -#ifndef MQTTPUBLISH_H_ -#define MQTTPUBLISH_H_ - -#if !defined(DLLImport) - #define DLLImport -#endif -#if !defined(DLLExport) - #define DLLExport -#endif - -DLLExport int MQTTSerialize_publish(unsigned char* buf, int buflen, unsigned char dup, int qos, unsigned char retained, unsigned short packetid, - MQTTString topicName, unsigned char* payload, int payloadlen); - -DLLExport int MQTTDeserialize_publish(unsigned char* dup, int* qos, unsigned char* retained, unsigned short* packetid, MQTTString* topicName, - unsigned char** payload, int32_t* payloadlen, unsigned char* buf, int len); - -DLLExport int MQTTSerialize_puback(unsigned char* buf, int buflen, unsigned short packetid); -DLLExport int MQTTSerialize_pubrel(unsigned char* buf, int buflen, unsigned char dup, unsigned short packetid); -DLLExport int MQTTSerialize_pubcomp(unsigned char* buf, int buflen, unsigned short packetid); - -#endif /* MQTTPUBLISH_H_ */ diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSerializePublish.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSerializePublish.c deleted file mode 100644 index 77a58b54a..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSerializePublish.c +++ /dev/null @@ -1,169 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2014 IBM Corp. - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * and Eclipse Distribution License v1.0 which accompany this distribution. - * - * The Eclipse Public License is available at - * http://www.eclipse.org/legal/epl-v10.html - * and the Eclipse Distribution License is available at - * http://www.eclipse.org/org/documents/edl-v10.php. - * - * Contributors: - * Ian Craggs - initial API and implementation and/or initial documentation - * Ian Craggs - fix for https://bugs.eclipse.org/bugs/show_bug.cgi?id=453144 - *******************************************************************************/ - -#include "MQTTPacket.h" -#include "StackTrace.h" - -#include - - -/** - * Determines the length of the MQTT publish packet that would be produced using the supplied parameters - * @param qos the MQTT QoS of the publish (packetid is omitted for QoS 0) - * @param topicName the topic name to be used in the publish - * @param payloadlen the length of the payload to be sent - * @return the length of buffer needed to contain the serialized version of the packet - */ -int MQTTSerialize_publishLength(int qos, MQTTString topicName, int payloadlen) -{ - int len = 0; - - len += 2 + MQTTstrlen(topicName) + payloadlen; - if (qos > 0) - len += 2; /* packetid */ - return len; -} - - -/** - * Serializes the supplied publish data into the supplied buffer, ready for sending - * @param buf the buffer into which the packet will be serialized - * @param buflen the length in bytes of the supplied buffer - * @param dup integer - the MQTT dup flag - * @param qos integer - the MQTT QoS value - * @param retained integer - the MQTT retained flag - * @param packetid integer - the MQTT packet identifier - * @param topicName MQTTString - the MQTT topic in the publish - * @param payload byte buffer - the MQTT publish payload - * @param payloadlen integer - the length of the MQTT payload - * @return the length of the serialized data. <= 0 indicates error - */ -int MQTTSerialize_publish(unsigned char* buf, int buflen, unsigned char dup, int qos, unsigned char retained, unsigned short packetid, - MQTTString topicName, unsigned char* payload, int payloadlen) -{ - unsigned char *ptr = buf; - MQTTHeader header = {0}; - int rem_len = 0; - int rc = 0; - - FUNC_ENTRY; - if (MQTTPacket_len(rem_len = MQTTSerialize_publishLength(qos, topicName, payloadlen)) > buflen) - { - rc = MQTTPACKET_BUFFER_TOO_SHORT; - goto exit; - } - - header.bits.type = PUBLISH; - header.bits.dup = dup; - header.bits.qos = qos; - header.bits.retain = retained; - writeChar(&ptr, header.byte); /* write header */ - - ptr += MQTTPacket_encode(ptr, rem_len); /* write remaining length */; - - writeMQTTString(&ptr, topicName); - - if (qos > 0) - writeInt(&ptr, packetid); - - memcpy(ptr, payload, payloadlen); - ptr += payloadlen; - - rc = ptr - buf; - -exit: - FUNC_EXIT_RC(rc); - return rc; -} - - - -/** - * Serializes the ack packet into the supplied buffer. - * @param buf the buffer into which the packet will be serialized - * @param buflen the length in bytes of the supplied buffer - * @param type the MQTT packet type - * @param dup the MQTT dup flag - * @param packetid the MQTT packet identifier - * @return serialized length, or error if 0 - */ -int MQTTSerialize_ack(unsigned char* buf, int buflen, unsigned char packettype, unsigned char dup, unsigned short packetid) -{ - MQTTHeader header = {0}; - int rc = 0; - unsigned char *ptr = buf; - - FUNC_ENTRY; - if (buflen < 4) - { - rc = MQTTPACKET_BUFFER_TOO_SHORT; - goto exit; - } - header.bits.type = packettype; - header.bits.dup = dup; - header.bits.qos = (packettype == PUBREL) ? 1 : 0; - writeChar(&ptr, header.byte); /* write header */ - - ptr += MQTTPacket_encode(ptr, 2); /* write remaining length */ - writeInt(&ptr, packetid); - rc = ptr - buf; -exit: - FUNC_EXIT_RC(rc); - return rc; -} - - -/** - * Serializes a puback packet into the supplied buffer. - * @param buf the buffer into which the packet will be serialized - * @param buflen the length in bytes of the supplied buffer - * @param packetid integer - the MQTT packet identifier - * @return serialized length, or error if 0 - */ -int MQTTSerialize_puback(unsigned char* buf, int buflen, unsigned short packetid) -{ - return MQTTSerialize_ack(buf, buflen, PUBACK, 0, packetid); -} - - -/** - * Serializes a pubrel packet into the supplied buffer. - * @param buf the buffer into which the packet will be serialized - * @param buflen the length in bytes of the supplied buffer - * @param dup integer - the MQTT dup flag - * @param packetid integer - the MQTT packet identifier - * @return serialized length, or error if 0 - */ -int MQTTSerialize_pubrel(unsigned char* buf, int buflen, unsigned char dup, unsigned short packetid) -{ - return MQTTSerialize_ack(buf, buflen, PUBREL, dup, packetid); -} - - -/** - * Serializes a pubrel packet into the supplied buffer. - * @param buf the buffer into which the packet will be serialized - * @param buflen the length in bytes of the supplied buffer - * @param packetid integer - the MQTT packet identifier - * @return serialized length, or error if 0 - */ -int MQTTSerialize_pubcomp(unsigned char* buf, int buflen, unsigned short packetid) -{ - return MQTTSerialize_ack(buf, buflen, PUBCOMP, 0, packetid); -} - - diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribe.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribe.h deleted file mode 100644 index 4b702bd59..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribe.h +++ /dev/null @@ -1,39 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2014 IBM Corp. - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * and Eclipse Distribution License v1.0 which accompany this distribution. - * - * The Eclipse Public License is available at - * http://www.eclipse.org/legal/epl-v10.html - * and the Eclipse Distribution License is available at - * http://www.eclipse.org/org/documents/edl-v10.php. - * - * Contributors: - * Ian Craggs - initial API and implementation and/or initial documentation - * Xiang Rong - 442039 Add makefile to Embedded C client - *******************************************************************************/ - -#ifndef MQTTSUBSCRIBE_H_ -#define MQTTSUBSCRIBE_H_ - -#if !defined(DLLImport) - #define DLLImport -#endif -#if !defined(DLLExport) - #define DLLExport -#endif - -DLLExport int MQTTSerialize_subscribe(unsigned char* buf, int buflen, unsigned char dup, unsigned short packetid, - int count, MQTTString topicFilters[], int32_t requestedQoSs[]); - -DLLExport int MQTTDeserialize_subscribe(unsigned char* dup, unsigned short* packetid, - int maxcount, int* count, MQTTString topicFilters[], int requestedQoSs[], unsigned char* buf, int len); - -DLLExport int MQTTSerialize_suback(unsigned char* buf, int buflen, unsigned short packetid, int count, int* grantedQoSs); - -DLLExport int MQTTDeserialize_suback(unsigned short* packetid, int maxcount, int32_t* count, int32_t grantedQoSs[], unsigned char* buf, int len); - - -#endif /* MQTTSUBSCRIBE_H_ */ diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribeClient.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribeClient.c deleted file mode 100644 index dc131882d..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribeClient.c +++ /dev/null @@ -1,137 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2014 IBM Corp. - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * and Eclipse Distribution License v1.0 which accompany this distribution. - * - * The Eclipse Public License is available at - * http://www.eclipse.org/legal/epl-v10.html - * and the Eclipse Distribution License is available at - * http://www.eclipse.org/org/documents/edl-v10.php. - * - * Contributors: - * Ian Craggs - initial API and implementation and/or initial documentation - *******************************************************************************/ - -#include "MQTTPacket.h" -#include "StackTrace.h" - -#include - -/** - * Determines the length of the MQTT subscribe packet that would be produced using the supplied parameters - * @param count the number of topic filter strings in topicFilters - * @param topicFilters the array of topic filter strings to be used in the publish - * @return the length of buffer needed to contain the serialized version of the packet - */ -int MQTTSerialize_subscribeLength(int count, MQTTString topicFilters[]) -{ - int i; - int len = 2; /* packetid */ - - for (i = 0; i < count; ++i) - len += 2 + MQTTstrlen(topicFilters[i]) + 1; /* length + topic + req_qos */ - return len; -} - - -/** - * Serializes the supplied subscribe data into the supplied buffer, ready for sending - * @param buf the buffer into which the packet will be serialized - * @param buflen the length in bytes of the supplied bufferr - * @param dup integer - the MQTT dup flag - * @param packetid integer - the MQTT packet identifier - * @param count - number of members in the topicFilters and reqQos arrays - * @param topicFilters - array of topic filter names - * @param requestedQoSs - array of requested QoS - * @return the length of the serialized data. <= 0 indicates error - */ -int MQTTSerialize_subscribe(unsigned char* buf, int buflen, unsigned char dup, unsigned short packetid, int count, - MQTTString topicFilters[], int32_t requestedQoSs[]) -{ - unsigned char *ptr = buf; - MQTTHeader header = {0}; - int rem_len = 0; - int rc = 0; - int i = 0; - - FUNC_ENTRY; - if (MQTTPacket_len(rem_len = MQTTSerialize_subscribeLength(count, topicFilters)) > buflen) - { - rc = MQTTPACKET_BUFFER_TOO_SHORT; - goto exit; - } - - header.byte = 0; - header.bits.type = SUBSCRIBE; - header.bits.dup = dup; - header.bits.qos = 1; - writeChar(&ptr, header.byte); /* write header */ - - ptr += MQTTPacket_encode(ptr, rem_len); /* write remaining length */; - - writeInt(&ptr, packetid); - - for (i = 0; i < count; ++i) - { - writeMQTTString(&ptr, topicFilters[i]); - writeChar(&ptr, requestedQoSs[i]); - } - - rc = ptr - buf; -exit: - FUNC_EXIT_RC(rc); - return rc; -} - - - -/** - * Deserializes the supplied (wire) buffer into suback data - * @param packetid returned integer - the MQTT packet identifier - * @param maxcount - the maximum number of members allowed in the grantedQoSs array - * @param count returned integer - number of members in the grantedQoSs array - * @param grantedQoSs returned array of integers - the granted qualities of service - * @param buf the raw buffer data, of the correct length determined by the remaining length field - * @param buflen the length in bytes of the data in the supplied buffer - * @return error code. 1 is success, 0 is failure - */ -int MQTTDeserialize_suback(unsigned short* packetid, int maxcount, int32_t* count, int32_t grantedQoSs[], unsigned char* buf, int buflen) -{ - MQTTHeader header = {0}; - unsigned char* curdata = buf; - unsigned char* enddata = NULL; - int rc = 0; - int mylen; - - FUNC_ENTRY; - header.byte = readChar(&curdata); - if (header.bits.type != SUBACK) - goto exit; - - curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ - enddata = curdata + mylen; - if (enddata - curdata < 2) - goto exit; - - *packetid = readInt(&curdata); - - *count = 0; - while (curdata < enddata) - { - if (*count > maxcount) - { - rc = -1; - goto exit; - } - grantedQoSs[(*count)++] = readChar(&curdata); - } - - rc = 1; -exit: - FUNC_EXIT_RC(rc); - return rc; -} - - diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribeServer.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribeServer.c deleted file mode 100644 index 5579645fe..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTSubscribeServer.c +++ /dev/null @@ -1,112 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2014 IBM Corp. - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * and Eclipse Distribution License v1.0 which accompany this distribution. - * - * The Eclipse Public License is available at - * http://www.eclipse.org/legal/epl-v10.html - * and the Eclipse Distribution License is available at - * http://www.eclipse.org/org/documents/edl-v10.php. - * - * Contributors: - * Ian Craggs - initial API and implementation and/or initial documentation - *******************************************************************************/ - -#include "MQTTPacket.h" -#include "StackTrace.h" - -#include - - -/** - * Deserializes the supplied (wire) buffer into subscribe data - * @param dup integer returned - the MQTT dup flag - * @param packetid integer returned - the MQTT packet identifier - * @param maxcount - the maximum number of members allowed in the topicFilters and requestedQoSs arrays - * @param count - number of members in the topicFilters and requestedQoSs arrays - * @param topicFilters - array of topic filter names - * @param requestedQoSs - array of requested QoS - * @param buf the raw buffer data, of the correct length determined by the remaining length field - * @param buflen the length in bytes of the data in the supplied buffer - * @return the length of the serialized data. <= 0 indicates error - */ -int MQTTDeserialize_subscribe(unsigned char* dup, unsigned short* packetid, int maxcount, int* count, MQTTString topicFilters[], - int requestedQoSs[], unsigned char* buf, int buflen) -{ - MQTTHeader header = {0}; - unsigned char* curdata = buf; - unsigned char* enddata = NULL; - int rc = -1; - int mylen = 0; - - FUNC_ENTRY; - header.byte = readChar(&curdata); - if (header.bits.type != SUBSCRIBE) - goto exit; - *dup = header.bits.dup; - - curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ - enddata = curdata + mylen; - - *packetid = readInt(&curdata); - - *count = 0; - while (curdata < enddata) - { - if (!readMQTTLenString(&topicFilters[*count], &curdata, enddata)) - goto exit; - if (curdata >= enddata) /* do we have enough data to read the req_qos version byte? */ - goto exit; - requestedQoSs[*count] = readChar(&curdata); - (*count)++; - } - - rc = 1; -exit: - FUNC_EXIT_RC(rc); - return rc; -} - - -/** - * Serializes the supplied suback data into the supplied buffer, ready for sending - * @param buf the buffer into which the packet will be serialized - * @param buflen the length in bytes of the supplied buffer - * @param packetid integer - the MQTT packet identifier - * @param count - number of members in the grantedQoSs array - * @param grantedQoSs - array of granted QoS - * @return the length of the serialized data. <= 0 indicates error - */ -int MQTTSerialize_suback(unsigned char* buf, int buflen, unsigned short packetid, int count, int* grantedQoSs) -{ - MQTTHeader header = {0}; - int rc = -1; - unsigned char *ptr = buf; - int i; - - FUNC_ENTRY; - if (buflen < 2 + count) - { - rc = MQTTPACKET_BUFFER_TOO_SHORT; - goto exit; - } - header.byte = 0; - header.bits.type = SUBACK; - writeChar(&ptr, header.byte); /* write header */ - - ptr += MQTTPacket_encode(ptr, 2 + count); /* write remaining length */ - - writeInt(&ptr, packetid); - - for (i = 0; i < count; ++i) - writeChar(&ptr, grantedQoSs[i]); - - rc = ptr - buf; -exit: - FUNC_EXIT_RC(rc); - return rc; -} - - diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribe.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribe.h deleted file mode 100644 index 355ca9a42..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribe.h +++ /dev/null @@ -1,38 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2014 IBM Corp. - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * and Eclipse Distribution License v1.0 which accompany this distribution. - * - * The Eclipse Public License is available at - * http://www.eclipse.org/legal/epl-v10.html - * and the Eclipse Distribution License is available at - * http://www.eclipse.org/org/documents/edl-v10.php. - * - * Contributors: - * Ian Craggs - initial API and implementation and/or initial documentation - * Xiang Rong - 442039 Add makefile to Embedded C client - *******************************************************************************/ - -#ifndef MQTTUNSUBSCRIBE_H_ -#define MQTTUNSUBSCRIBE_H_ - -#if !defined(DLLImport) - #define DLLImport -#endif -#if !defined(DLLExport) - #define DLLExport -#endif - -DLLExport int MQTTSerialize_unsubscribe(unsigned char* buf, int buflen, unsigned char dup, unsigned short packetid, - int count, MQTTString topicFilters[]); - -DLLExport int MQTTDeserialize_unsubscribe(unsigned char* dup, unsigned short* packetid, int max_count, int* count, MQTTString topicFilters[], - unsigned char* buf, int len); - -DLLExport int MQTTSerialize_unsuback(unsigned char* buf, int buflen, unsigned short packetid); - -DLLExport int MQTTDeserialize_unsuback(unsigned short* packetid, unsigned char* buf, int len); - -#endif /* MQTTUNSUBSCRIBE_H_ */ diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribeClient.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribeClient.c deleted file mode 100644 index e7ec53021..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribeClient.c +++ /dev/null @@ -1,106 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2014 IBM Corp. - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * and Eclipse Distribution License v1.0 which accompany this distribution. - * - * The Eclipse Public License is available at - * http://www.eclipse.org/legal/epl-v10.html - * and the Eclipse Distribution License is available at - * http://www.eclipse.org/org/documents/edl-v10.php. - * - * Contributors: - * Ian Craggs - initial API and implementation and/or initial documentation - *******************************************************************************/ - -#include "MQTTPacket.h" -#include "StackTrace.h" - -#include - -/** - * Determines the length of the MQTT unsubscribe packet that would be produced using the supplied parameters - * @param count the number of topic filter strings in topicFilters - * @param topicFilters the array of topic filter strings to be used in the publish - * @return the length of buffer needed to contain the serialized version of the packet - */ -int MQTTSerialize_unsubscribeLength(int count, MQTTString topicFilters[]) -{ - int i; - int len = 2; /* packetid */ - - for (i = 0; i < count; ++i) - len += 2 + MQTTstrlen(topicFilters[i]); /* length + topic*/ - return len; -} - - -/** - * Serializes the supplied unsubscribe data into the supplied buffer, ready for sending - * @param buf the raw buffer data, of the correct length determined by the remaining length field - * @param buflen the length in bytes of the data in the supplied buffer - * @param dup integer - the MQTT dup flag - * @param packetid integer - the MQTT packet identifier - * @param count - number of members in the topicFilters array - * @param topicFilters - array of topic filter names - * @return the length of the serialized data. <= 0 indicates error - */ -int MQTTSerialize_unsubscribe(unsigned char* buf, int buflen, unsigned char dup, unsigned short packetid, - int count, MQTTString topicFilters[]) -{ - unsigned char *ptr = buf; - MQTTHeader header = {0}; - int rem_len = 0; - int rc = -1; - int i = 0; - - FUNC_ENTRY; - if (MQTTPacket_len(rem_len = MQTTSerialize_unsubscribeLength(count, topicFilters)) > buflen) - { - rc = MQTTPACKET_BUFFER_TOO_SHORT; - goto exit; - } - - header.byte = 0; - header.bits.type = UNSUBSCRIBE; - header.bits.dup = dup; - header.bits.qos = 1; - writeChar(&ptr, header.byte); /* write header */ - - ptr += MQTTPacket_encode(ptr, rem_len); /* write remaining length */; - - writeInt(&ptr, packetid); - - for (i = 0; i < count; ++i) - writeMQTTString(&ptr, topicFilters[i]); - - rc = ptr - buf; -exit: - FUNC_EXIT_RC(rc); - return rc; -} - - -/** - * Deserializes the supplied (wire) buffer into unsuback data - * @param packetid returned integer - the MQTT packet identifier - * @param buf the raw buffer data, of the correct length determined by the remaining length field - * @param buflen the length in bytes of the data in the supplied buffer - * @return error code. 1 is success, 0 is failure - */ -int MQTTDeserialize_unsuback(unsigned short* packetid, unsigned char* buf, int buflen) -{ - unsigned char type = 0; - unsigned char dup = 0; - int rc = 0; - - FUNC_ENTRY; - rc = MQTTDeserialize_ack(&type, &dup, packetid, buf, buflen); - if (type == UNSUBACK) - rc = 1; - FUNC_EXIT_RC(rc); - return rc; -} - - diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribeServer.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribeServer.c deleted file mode 100644 index 42b6102a7..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/MQTTUnsubscribeServer.c +++ /dev/null @@ -1,102 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2014 IBM Corp. - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * and Eclipse Distribution License v1.0 which accompany this distribution. - * - * The Eclipse Public License is available at - * http://www.eclipse.org/legal/epl-v10.html - * and the Eclipse Distribution License is available at - * http://www.eclipse.org/org/documents/edl-v10.php. - * - * Contributors: - * Ian Craggs - initial API and implementation and/or initial documentation - *******************************************************************************/ - -#include "MQTTPacket.h" -#include "StackTrace.h" - -#include - - -/** - * Deserializes the supplied (wire) buffer into unsubscribe data - * @param dup integer returned - the MQTT dup flag - * @param packetid integer returned - the MQTT packet identifier - * @param maxcount - the maximum number of members allowed in the topicFilters and requestedQoSs arrays - * @param count - number of members in the topicFilters and requestedQoSs arrays - * @param topicFilters - array of topic filter names - * @param buf the raw buffer data, of the correct length determined by the remaining length field - * @param buflen the length in bytes of the data in the supplied buffer - * @return the length of the serialized data. <= 0 indicates error - */ -int MQTTDeserialize_unsubscribe(unsigned char* dup, unsigned short* packetid, int maxcount, int* count, MQTTString topicFilters[], - unsigned char* buf, int len) -{ - MQTTHeader header = {0}; - unsigned char* curdata = buf; - unsigned char* enddata = NULL; - int rc = 0; - int mylen = 0; - - FUNC_ENTRY; - header.byte = readChar(&curdata); - if (header.bits.type != UNSUBSCRIBE) - goto exit; - *dup = header.bits.dup; - - curdata += (rc = MQTTPacket_decodeBuf(curdata, &mylen)); /* read remaining length */ - enddata = curdata + mylen; - - *packetid = readInt(&curdata); - - *count = 0; - while (curdata < enddata) - { - if (!readMQTTLenString(&topicFilters[*count], &curdata, enddata)) - goto exit; - (*count)++; - } - - rc = 1; -exit: - FUNC_EXIT_RC(rc); - return rc; -} - - -/** - * Serializes the supplied unsuback data into the supplied buffer, ready for sending - * @param buf the buffer into which the packet will be serialized - * @param buflen the length in bytes of the supplied buffer - * @param packetid integer - the MQTT packet identifier - * @return the length of the serialized data. <= 0 indicates error - */ -int MQTTSerialize_unsuback(unsigned char* buf, int buflen, unsigned short packetid) -{ - MQTTHeader header = {0}; - int rc = 0; - unsigned char *ptr = buf; - - FUNC_ENTRY; - if (buflen < 2) - { - rc = MQTTPACKET_BUFFER_TOO_SHORT; - goto exit; - } - header.byte = 0; - header.bits.type = UNSUBACK; - writeChar(&ptr, header.byte); /* write header */ - - ptr += MQTTPacket_encode(ptr, 2); /* write remaining length */ - - writeInt(&ptr, packetid); - - rc = ptr - buf; -exit: - FUNC_EXIT_RC(rc); - return rc; -} - - diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/Makefile b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/Makefile deleted file mode 100644 index 2cc7a23d1..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -SRC_FILES += MQTTPacket.c\ - MQTTConnectClient.c \ - MQTTConnectServer.c \ - MQTTDeserializePublish.c \ - MQTTFormat.c \ - MQTTSerializePublish.c \ - MQTTSubscribeClient.c \ - MQTTSubscribeServer.c \ - MQTTUnsubscribeClient.c \ - MQTTUnsubscribeServer.c \ - transport.c - -include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/StackTrace.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/StackTrace.h deleted file mode 100644 index 2808a0d18..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/StackTrace.h +++ /dev/null @@ -1,78 +0,0 @@ -/******************************************************************************* - * Copyright (c) 2014 IBM Corp. - * - * All rights reserved. This program and the accompanying materials - * are made available under the terms of the Eclipse Public License v1.0 - * and Eclipse Distribution License v1.0 which accompany this distribution. - * - * The Eclipse Public License is available at - * http://www.eclipse.org/legal/epl-v10.html - * and the Eclipse Distribution License is available at - * http://www.eclipse.org/org/documents/edl-v10.php. - * - * Contributors: - * Ian Craggs - initial API and implementation and/or initial documentation - * Ian Craggs - fix for bug #434081 - *******************************************************************************/ - -#ifndef STACKTRACE_H_ -#define STACKTRACE_H_ - -#include -#define NOSTACKTRACE 1 - -#if defined(NOSTACKTRACE) -#define FUNC_ENTRY -#define FUNC_ENTRY_NOLOG -#define FUNC_ENTRY_MED -#define FUNC_ENTRY_MAX -#define FUNC_EXIT -#define FUNC_EXIT_NOLOG -#define FUNC_EXIT_MED -#define FUNC_EXIT_MAX -#define FUNC_EXIT_RC(x) -#define FUNC_EXIT_MED_RC(x) -#define FUNC_EXIT_MAX_RC(x) - -#else - -#if defined(WIN32) -#define inline __inline -#define FUNC_ENTRY StackTrace_entry(__FUNCTION__, __LINE__, TRACE_MINIMUM) -#define FUNC_ENTRY_NOLOG StackTrace_entry(__FUNCTION__, __LINE__, -1) -#define FUNC_ENTRY_MED StackTrace_entry(__FUNCTION__, __LINE__, TRACE_MEDIUM) -#define FUNC_ENTRY_MAX StackTrace_entry(__FUNCTION__, __LINE__, TRACE_MAXIMUM) -#define FUNC_EXIT StackTrace_exit(__FUNCTION__, __LINE__, NULL, TRACE_MINIMUM) -#define FUNC_EXIT_NOLOG StackTrace_exit(__FUNCTION__, __LINE__, -1) -#define FUNC_EXIT_MED StackTrace_exit(__FUNCTION__, __LINE__, NULL, TRACE_MEDIUM) -#define FUNC_EXIT_MAX StackTrace_exit(__FUNCTION__, __LINE__, NULL, TRACE_MAXIMUM) -#define FUNC_EXIT_RC(x) StackTrace_exit(__FUNCTION__, __LINE__, &x, TRACE_MINIMUM) -#define FUNC_EXIT_MED_RC(x) StackTrace_exit(__FUNCTION__, __LINE__, &x, TRACE_MEDIUM) -#define FUNC_EXIT_MAX_RC(x) StackTrace_exit(__FUNCTION__, __LINE__, &x, TRACE_MAXIMUM) -#else -#define FUNC_ENTRY StackTrace_entry(__func__, __LINE__, TRACE_MINIMUM) -#define FUNC_ENTRY_NOLOG StackTrace_entry(__func__, __LINE__, -1) -#define FUNC_ENTRY_MED StackTrace_entry(__func__, __LINE__, TRACE_MEDIUM) -#define FUNC_ENTRY_MAX StackTrace_entry(__func__, __LINE__, TRACE_MAXIMUM) -#define FUNC_EXIT StackTrace_exit(__func__, __LINE__, NULL, TRACE_MINIMUM) -#define FUNC_EXIT_NOLOG StackTrace_exit(__func__, __LINE__, NULL, -1) -#define FUNC_EXIT_MED StackTrace_exit(__func__, __LINE__, NULL, TRACE_MEDIUM) -#define FUNC_EXIT_MAX StackTrace_exit(__func__, __LINE__, NULL, TRACE_MAXIMUM) -#define FUNC_EXIT_RC(x) StackTrace_exit(__func__, __LINE__, &x, TRACE_MINIMUM) -#define FUNC_EXIT_MED_RC(x) StackTrace_exit(__func__, __LINE__, &x, TRACE_MEDIUM) -#define FUNC_EXIT_MAX_RC(x) StackTrace_exit(__func__, __LINE__, &x, TRACE_MAXIMUM) - -void StackTrace_entry(const char* name, int line, int trace); -void StackTrace_exit(const char* name, int line, void* return_value, int trace); - -void StackTrace_printStack(FILE* dest); -char* StackTrace_get(unsigned long); - -#endif - -#endif - - - - -#endif /* STACKTRACE_H_ */ diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/transport.c b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/transport.c deleted file mode 100644 index d2c187091..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/transport.c +++ /dev/null @@ -1,102 +0,0 @@ -#include "transport.h" -#include "lwip/opt.h" -#include "lwip/arch.h" -#include "lwip/api.h" -#include "lwip/inet.h" -#include "lwip/sockets.h" -#include "string.h" - -static int mysock; - -/************************************************************************ -** ��������: transport_sendPacketBuffer -** ��������: ��TCP��ʽ�������� -** ��ڲ���: unsigned char* buf�����ݻ����� -** int buflen�����ݳ��� -** ���ڲ���: <0��������ʧ�� -************************************************************************/ -int32_t transport_sendPacketBuffer( uint8_t* buf, int32_t buflen) -{ - int32_t rc; - rc = write(mysock, buf, buflen); - return rc; -} - -/************************************************************************ -** ��������: transport_getdata -** ��������: �������ķ�ʽ����TCP���� -** ��ڲ���: unsigned char* buf�����ݻ����� -** int count�����ݳ��� -** ���ڲ���: <=0��������ʧ�� -************************************************************************/ -int transport_getdata(unsigned char* buf, int count) -{ - int32_t rc; - - rc = recv(mysock, buf, count, 0); - lw_print("get data : %lx\n",rc); - return rc; -} - - - -/************************************************************************ -** ��������: transport_open -** ��������: ��һ���ӿڣ����Һͷ����� �������� -** ��ڲ���: char* servip:���������� -** int port:�˿ں� -** ���ڲ���: <0������ʧ�� -************************************************************************/ -// int32_t transport_open(int8_t* servip, int32_t port) -// { -// int32_t *sock = &mysock; -// int32_t ret; -// // int32_t opt; -// struct sockaddr_in addr; - -// //��ʼ����������Ϣ -// memset(&addr,0,sizeof(addr)); -// addr.sin_len = sizeof(addr); -// addr.sin_family = AF_INET; -// //��д�������˿ں� -// addr.sin_port = PP_HTONS(port); -// //��д������IP��ַ -// addr.sin_addr.s_addr = inet_addr((const char*)servip); - -// //����SOCK -// *sock = socket(AF_INET,SOCK_STREAM,0); -// //���ӷ����� -// ret = connect(*sock,(struct sockaddr*)&addr,sizeof(addr)); -// if(ret != 0) -// { -// //�ر����� -// close(*sock); -// //����ʧ�� -// return -1; -// } -// //���ӳɹ�,���ó�ʱʱ��1000ms -// // opt = 1000; -// // setsockopt(*sock,SOL_SOCKET,SO_RCVTIMEO,&opt,sizeof(int)); - -// //�����׽��� -// return *sock; -// } - - -/************************************************************************ -** ��������: transport_close -** ��������: �ر��׽��� -** ��ڲ���: unsigned char* buf�����ݻ����� -** int buflen�����ݳ��� -** ���ڲ���: <0��������ʧ�� -************************************************************************/ -int32_t transport_close(void) -{ - - int rc; -// rc = close(mysock); - rc = shutdown(mysock, SHUT_WR); - rc = recv(mysock, NULL, (size_t)0, 0); - rc = close(mysock); - return rc; -} diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/transport.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/transport.h deleted file mode 100644 index a11ef1923..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/MQTT/transport.h +++ /dev/null @@ -1,45 +0,0 @@ -#ifndef __TRANSPORT_H -#define __TRANSPORT_H - -#include - - -/************************************************************************ -** ��������: transport_sendPacketBuffer -** ��������: ��TCP��ʽ�������� -** ��ڲ���: unsigned char* buf�����ݻ����� -** int buflen�����ݳ��� -** ���ڲ���: <0��������ʧ�� -************************************************************************/ -int32_t transport_sendPacketBuffer( uint8_t* buf, int32_t buflen); - -/************************************************************************ -** ��������: transport_getdata -** ��������: �������ķ�ʽ����TCP���� -** ��ڲ���: unsigned char* buf�����ݻ����� -** int count�����ݳ��� -** ���ڲ���: <=0��������ʧ�� -************************************************************************/ -int transport_getdata(unsigned char* buf, int count); - -/************************************************************************ -** ��������: transport_open -** ��������: ��һ���ӿڣ����Һͷ����� �������� -** ��ڲ���: char* servip:���������� -** int port:�˿ں� -** ���ڲ���: <0������ʧ�� -************************************************************************/ -int32_t transport_open(int8_t* servip, int32_t port); - -/************************************************************************ -** ��������: transport_close -** ��������: �ر��׽��� -** ��ڲ���: unsigned char* buf�����ݻ����� -** int buflen�����ݳ��� -** ���ڲ���: <0��������ʧ�� -************************************************************************/ -int32_t transport_close(void); - - - -#endif diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/Makefile b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/Makefile deleted file mode 100644 index a7d676dbc..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/apps/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -SRC_DIR += MQTT - -LWIP_DIR += MQTT - - -include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file From 339ea93b09b039d84b6d6cfea4b2f01afb39e8a9 Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Wed, 27 Sep 2023 14:21:14 +0800 Subject: [PATCH 11/21] delete no need --- APP_Framework/Applications/app_test/Makefile | 2 +- .../Applications/app_test/test_hash.c | 44 ------ .../Applications/connection_app/Makefile | 2 +- Ubiquitous/XiZi_IIoT/kernel/include/xs_hash.h | 144 ------------------ .../resources/ethernet/LwIP/Makefile | 4 +- .../resources/ethernet/LwIP/arch/lwipopts.h | 1 - .../resources/ethernet/LwIP/include/Makefile | 6 - .../ethernet/LwIP/include/lwip/Makefile | 6 - 8 files changed, 4 insertions(+), 205 deletions(-) delete mode 100644 APP_Framework/Applications/app_test/test_hash.c delete mode 100644 Ubiquitous/XiZi_IIoT/kernel/include/xs_hash.h delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/Makefile delete mode 100644 Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/Makefile diff --git a/APP_Framework/Applications/app_test/Makefile b/APP_Framework/Applications/app_test/Makefile index 7b554d013..1e89361c4 100644 --- a/APP_Framework/Applications/app_test/Makefile +++ b/APP_Framework/Applications/app_test/Makefile @@ -24,7 +24,7 @@ endif ifeq ($(CONFIG_ADD_XIZI_FEATURES),y) SRC_FILES := test_shell.c - SRC_FILES += test_hash.c + ifeq ($(CONFIG_USER_TEST_ADC),y) SRC_FILES += test_adc.c endif diff --git a/APP_Framework/Applications/app_test/test_hash.c b/APP_Framework/Applications/app_test/test_hash.c deleted file mode 100644 index 14539fc3e..000000000 --- a/APP_Framework/Applications/app_test/test_hash.c +++ /dev/null @@ -1,44 +0,0 @@ -/* -* Copyright (c) 2020 AIIT XUOS Lab -* XiUOS is licensed under Mulan PSL v2. -* You can use this software according to the terms and conditions of the Mulan PSL v2. -* You may obtain a copy of Mulan PSL v2 at: -* http://license.coscl.org.cn/MulanPSL2 -* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -* See the Mulan PSL v2 for more details. -*/ - -/** -* @file: test_ethernet.c -* @brief: a application of ethernet function -* @version: 1.1 -* @author: AIIT XUOS Lab -* @date: 2022/12/17 -*/ -#include -#include -#include -#include - -int Testhash(void) -{ - Element a[]={{12,1},{2,2},{31,3},{45,4},{8,5},{45,5}}; - - int n = sizeof(a)/sizeof(Element); - Hash_table *h = Creat_Table(n); - int i = 0; - for(i = 0 ; idata->value); //查找key值为12的Element - printf("%d\n",h->length); //打印哈希表的元素个数 - Destroy_Table(h); // 摧毁哈希表 - - return 0; -} - -PRIV_SHELL_CMD_FUNCTION(Testhash, a hash test sample, PRIV_SHELL_CMD_MAIN_ATTR); \ No newline at end of file diff --git a/APP_Framework/Applications/connection_app/Makefile b/APP_Framework/Applications/connection_app/Makefile index 2ed5cc480..8aa357308 100755 --- a/APP_Framework/Applications/connection_app/Makefile +++ b/APP_Framework/Applications/connection_app/Makefile @@ -14,7 +14,7 @@ ifeq ($(CONFIG_ADD_XIZI_FEATURES),y) ifeq ($(CONFIG_RESOURCES_LWIP),y) SRC_DIR += socket_demo endif - SRC_DIR +=mqtt_demo + include $(KERNEL_ROOT)/compiler.mk endif diff --git a/Ubiquitous/XiZi_IIoT/kernel/include/xs_hash.h b/Ubiquitous/XiZi_IIoT/kernel/include/xs_hash.h deleted file mode 100644 index 4423d9573..000000000 --- a/Ubiquitous/XiZi_IIoT/kernel/include/xs_hash.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ - -/** -* @file: xs_hash.h -* @brief: hash table -* @version: 1.0 -* @author: AIIT XUOS Lab -* @date: 2023/7/10 -* -*/ - -#include -#include -#include -#include "xs_base.h" - -#define REMAINDER 11 - -typedef struct element -{ - uint8_t key; - uint8_t value; - uint8_t hash; -}Element; - - -typedef struct Pnode -{ - Element *data; - struct Pnode *next; -}Node; - - -typedef struct hash_table -{ - uint8_t size; - uint8_t length; - struct Pnode *head; -}Hash_table; - - -Hash_table* Creat_Table(int table_size) -{ - Hash_table *h = (Hash_table *)malloc(sizeof(Hash_table)); - h->size = REMAINDER; - h->head = (Node *)malloc((h->size)*sizeof(Node)); - h->length = 0; - int i = 0; - for(i=0 ; isize ; i++) - { - h->head[i].next = NULL; - } - return h; -} - -int hash(int value) -{ - return value%REMAINDER; -} - -Node *lookup(Hash_table *h , int key) -{ - int i; - i = hash(key); - Node * p = h->head[i].next; - while(p && key != p->data->key) - { - p = p->next; - } - - return p; -} - - - -void Insert(Hash_table *h , Element k) -{ - Node * p = lookup(h,k.key); - if(!p) - { - Node *q = (Node *)malloc(sizeof(Node)); - q->data = (Element *)malloc(sizeof(Element)); - (q->data)->key = k.key; - (q->data)->value = k.value; - int position; - position = (q->data)->hash = hash(k.key); - q->next = h->head[position].next; - h->head[position].next = q; - - h->length += 1; - return ; - } - else - { - printf("The keys is exist !\n"); - return ; - } -} - -void Destroy_Table(Hash_table *h) -{ - int i; - Node *p , *q; - for(i=0 ; isize ; i++) - { - p = h->head[i].next; - while(p) - { - q=p->next; - free(p); - p=q; - } - } - free(h->head); - free(h); -} - - -void print_Table(Hash_table *h) -{ - int i = 0; - for (i = 0; i < h->size ; i++) - { - Node * p = h->head[i].next; - while (p) - { - printf("[%d-%d] ",p->data->key, p->data->value); - p = p->next; - } - printf("NULL\n"); - } -} - - diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/Makefile b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/Makefile index d61a6f138..3b2116a85 100644 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/Makefile +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/Makefile @@ -2,7 +2,7 @@ SRC_DIR += api SRC_DIR += arch SRC_DIR += core SRC_DIR += netif -SRC_DIR += include + SRC_DIR += apps @@ -10,7 +10,7 @@ LWIP_DIR += api LWIP_DIR += arch LWIP_DIR += core LWIP_DIR += netif -LWIP_DIR += include + LWIP_DIR += apps diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/arch/lwipopts.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/arch/lwipopts.h index 726e37ea8..7ee9d1273 100644 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/arch/lwipopts.h +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/arch/lwipopts.h @@ -46,7 +46,6 @@ // #define LWIP_API_MSG_DEBUG #endif -// #define LWIP_SOCKETS_DEBUG 1 #ifdef LWIP_DEBUG #ifdef LWIP_SYS_DEBUG diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/Makefile b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/Makefile deleted file mode 100644 index c53e661a4..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -SRC_DIR += lwip - -LWIP_DIR += lwip - - -include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/Makefile b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/Makefile deleted file mode 100644 index 1d8dcd833..000000000 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/include/lwip/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -SRC_DIR += apps - -LWIP_DIR += apps - - -include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file From 014e51c0ad9d7462fcb01d922aeeafa882ee566d Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Wed, 27 Sep 2023 15:47:47 +0800 Subject: [PATCH 12/21] mmodify the liscence --- .../board/cortex-m7-emulator/board.c | 4 +- .../board/cortex-m7-emulator/board.h | 6 +- .../include/V2M/RTE_Components.h | 26 -- .../include/V2M/RTE_Device.h | 50 --- .../include/V2M/USART_V2M-MPS2.h | 11 +- .../third_party_driver/uart/connect_uart.c | 358 ++---------------- 6 files changed, 43 insertions(+), 412 deletions(-) delete mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/RTE_Components.h delete mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/RTE_Device.h diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.c b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.c index 72aac8356..4b7c6b157 100644 --- a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.c +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.c @@ -15,7 +15,7 @@ * @brief support cortex-m7-emulator-board init configure and start-up * @version 1.0 * @author fudan -* @date 2021-08-26 +* @date 2023-09-27 */ /************************************************* @@ -23,7 +23,7 @@ File name: board.c Description: support cortex-m7-emulator-board init configure and driver/task/... init Others: History: -1. Date: 2021-04-25 +1. Date: 2023-09-27 Author: AIIT XUOS Lab Modification: 1. support cortex-m7-emulator-board InitBoardHardware diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.h index 2b4d50398..d8053d385 100644 --- a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.h +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.h @@ -7,7 +7,7 @@ /** * @file board.h -* @brief define imxrt1052-board init configure and start-up function +* @brief definecortex-m7-emulator init configure and start-up function * @version 1.0 * @author AIIT XUOS Lab * @date 2021-05-28 @@ -15,10 +15,10 @@ /************************************************* File name: board.h -Description: define imxrt1052-board board init function and struct +Description: define cortex-m7-emulator init function and struct Others: History: -1. Date: 2021-05-28 +1. Date: 2023-09-27 Author: AIIT XUOS Lab Modification: 1. define imxrt-board InitBoardHardware diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/RTE_Components.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/RTE_Components.h deleted file mode 100644 index 8919484c7..000000000 --- a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/RTE_Components.h +++ /dev/null @@ -1,26 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Configuration File - * *** Do not modify ! *** - * - * Project: 'Blinky' - * Target: 'FastModels' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - - -/* - * Define the Device Header File: - */ -#define CMSIS_device_header "CMSDK_CM7_SP.h" - -/* Keil.ARM Compiler::Compiler:I/O:STDOUT:User:1.2.0 */ -#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ - #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ -/* Keil::CMSIS Driver:USART:1.0.3 */ -#define RTE_Drivers_USART - - -#endif /* RTE_COMPONENTS_H */ diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/RTE_Device.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/RTE_Device.h deleted file mode 100644 index 7584efda3..000000000 --- a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/RTE_Device.h +++ /dev/null @@ -1,50 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2016 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 25. April 2016 - * $Revision: V1.0.0 - * - * Project: RTE Device Configuration for ARM CMSDK_CM device - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART -#define RTE_USART0 1 - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_UART2 0 - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_UART3 0 - -#endif /* __RTE_DEVICE_H */ diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/USART_V2M-MPS2.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/USART_V2M-MPS2.h index 022414ac9..42fed79d7 100644 --- a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/USART_V2M-MPS2.h +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/V2M/USART_V2M-MPS2.h @@ -32,16 +32,9 @@ #include #include "Driver_USART.h" #include "Device.h" -#include "RTE_Device.h" -#include "RTE_Components.h" -#if (defined(RTE_Drivers_USART) \ - && (RTE_USART0 == 0) \ - && (RTE_USART1 == 0) \ - && (RTE_USART2 == 0) \ - && (RTE_USART3 == 0)) - #error "USART not configured in RTE_Device.h!" -#endif + + // USART Flags #define USART_FLAG_INITIALIZED ((uint8_t)(1U)) diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/connect_uart.c b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/connect_uart.c index 5f1a289ec..660ca1d80 100644 --- a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/connect_uart.c +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/uart/connect_uart.c @@ -1,29 +1,46 @@ -/* - * Copyright 2018 NXP - * All rights reserved. +/* ----------------------------------------------------------------------------- + * Copyright (c) 2016 - 2017 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. * * - * SPDX-License-Identifier: BSD-3-Clause - */ + * $Date: 26. October 2017 + * $Revision: V1.0.3 + * + * -------------------------------------------------------------------------- */ /** * @file connect_uart.c -* @brief support imxrt1052-board uart function and register to bus framework -* @version 1.0 +* @brief support cortex-m7-emulator uart function and register to bus framework +* @version 1.0 * @author AIIT XUOS Lab -* @date 2021-05-28 +* @date 2023-09-27 */ /************************************************* File name: connect_uart.c -Description: support imxrt1052-board uart configure and uart bus register function -Others: take SDK_2.6.1_MIMXRT1052xxxxB/components/uart/lpuart_adapter.c for references -History: -1. Date: 2021-05-28 +Description: support cortex-m7-emulator uart function and register to bus framework +Others: take Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\CMSIS\Driver\USART_V2M-MPS2.c for references +History: +1. Date: 2023-09-27 Author: AIIT XUOS Lab -Modification: -1. support imxrt1052-board uart configure, write and read -2. support imxrt1052-board uart bus device and driver register +Modification: +1. support cortex-m7-emulator uart configure, write and read +2. support cortex-m7-emulator uart bus device and driver register *************************************************/ #include @@ -45,7 +62,7 @@ static const ARM_DRIVER_VERSION usart_driver_version = { ARM_USART_API_VERSION, // USART0 -#if (defined (RTE_USART0) && (RTE_USART0 != 0)) +#ifdef BSP_USING_LPUART1 // USART0 Run-Time Information static USART_INFO USART0_Info = { 0U, { 0U, 0U, 0U }, 0U }; @@ -93,146 +110,7 @@ static const USART_RESOURCES USART0_Resources = { #endif -// USART1 -#if (defined (RTE_USART1) && (RTE_USART1 != 0)) -// USART1 Run-Time Information -static USART_INFO USART1_Info = { 0U, { 0U, 0U, 0U }, 0U }; -static USART_TRANSFER_INFO USART1_TransferInfo = { 0U, 0U, 0U, 0U, 0U, 0U }; -static PIN USART1_pin_rx = { CMSDK_GPIO1, 7U }; -static PIN USART1_pin_tx = { CMSDK_GPIO1, 8U }; - -// USART1 Resources -static const USART_RESOURCES USART1_Resources = { - { // Capabilities - 1, // supports UART (Asynchronous) mode - 0, // supports Synchronous Master mode - 0, // supports Synchronous Slave mode - 0, // supports UART Single-wire mode - 0, // supports UART IrDA mode - 0, // supports UART Smart Card mode - 0, // Smart Card Clock generator - 0, // RTS Flow Control available - 0, // CTS Flow Control available - 1, // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE - 1, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT - 0, // RTS Line: 0=not available, 1=available - 0, // CTS Line: 0=not available, 1=available - 0, // DTR Line: 0=not available, 1=available - 0, // DSR Line: 0=not available, 1=available - 0, // DCD Line: 0=not available, 1=available - 0, // RI Line: 0=not available, 1=available - 0, // Signal CTS change event: \ref ARM_USART_EVENT_CTS - 0, // Signal DSR change event: \ref ARM_USART_EVENT_DSR - 0, // Signal DCD change event: \ref ARM_USART_EVENT_DCD - 0, // Signal RI change event: \ref ARM_USART_EVENT_RI - 0 // Reserved (must be zero) - }, - { - &USART1_pin_rx, - &USART1_pin_tx - }, - CMSDK_UART1, - UART1RX_IRQn, - UART1TX_IRQn, - &USART1_Info, - &USART1_TransferInfo -}; -#endif - -// USART2 -#if (defined (RTE_USART2) && (RTE_USART2 != 0)) - -// USART2 Run-Time Information -static USART_INFO USART2_Info = { 0U, { 0U, 0U, 0U }, 0U }; -static USART_TRANSFER_INFO USART2_TransferInfo = { 0U, 0U, 0U, 0U, 0U, 0U }; -static PIN USART2_pin_rx = { CMSDK_GPIO1, 0U }; -static PIN USART2_pin_tx = { CMSDK_GPIO1, 1U }; - -// USART2 Resources -static const USART_RESOURCES USART2_Resources = { - { // Capabilities - 1, // supports UART (Asynchronous) mode - 0, // supports Synchronous Master mode - 0, // supports Synchronous Slave mode - 0, // supports UART Single-wire mode - 0, // supports UART IrDA mode - 0, // supports UART Smart Card mode - 0, // Smart Card Clock generator - 0, // RTS Flow Control available - 0, // CTS Flow Control available - 1, // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE - 1, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT - 0, // RTS Line: 0=not available, 1=available - 0, // CTS Line: 0=not available, 1=available - 0, // DTR Line: 0=not available, 1=available - 0, // DSR Line: 0=not available, 1=available - 0, // DCD Line: 0=not available, 1=available - 0, // RI Line: 0=not available, 1=available - 0, // Signal CTS change event: \ref ARM_USART_EVENT_CTS - 0, // Signal DSR change event: \ref ARM_USART_EVENT_DSR - 0, // Signal DCD change event: \ref ARM_USART_EVENT_DCD - 0, // Signal RI change event: \ref ARM_USART_EVENT_RI - 0 // Reserved (must be zero) - }, - { - &USART2_pin_rx, - &USART2_pin_tx - }, - CMSDK_UART2, - UART2RX_IRQn, - UART2TX_IRQn, - &USART2_Info, - &USART2_TransferInfo -}; -#endif - -// USART3 -#if (defined (RTE_USART3) && (RTE_USART3 != 0)) - -// USART3 Run-Time Information -static USART_INFO USART3_Info = { 0U, { 0U, 0U, 0U }, 0U }; -static USART_TRANSFER_INFO USART3_TransferInfo = { 0U, 0U, 0U, 0U, 0U, 0U }; -static PIN USART3_pin_rx = { CMSDK_GPIO0, 0U }; -static PIN USART3_pin_tx = { CMSDK_GPIO0, 4U }; - -// USART3 Resources -static const USART_RESOURCES USART3_Resources = { - { // Capabilities - 1, // supports UART (Asynchronous) mode - 0, // supports Synchronous Master mode - 0, // supports Synchronous Slave mode - 0, // supports UART Single-wire mode - 0, // supports UART IrDA mode - 0, // supports UART Smart Card mode - 0, // Smart Card Clock generator - 0, // RTS Flow Control available - 0, // CTS Flow Control available - 1, // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE - 1, // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT - 0, // RTS Line: 0=not available, 1=available - 0, // CTS Line: 0=not available, 1=available - 0, // DTR Line: 0=not available, 1=available - 0, // DSR Line: 0=not available, 1=available - 0, // DCD Line: 0=not available, 1=available - 0, // RI Line: 0=not available, 1=available - 0, // Signal CTS change event: \ref ARM_USART_EVENT_CTS - 0, // Signal DSR change event: \ref ARM_USART_EVENT_DSR - 0, // Signal DCD change event: \ref ARM_USART_EVENT_DCD - 0, // Signal RI change event: \ref ARM_USART_EVENT_RI - 0 // Reserved (must be zero) - }, - { - &USART3_pin_rx, - &USART3_pin_tx - }, - CMSDK_UART3, - UART3RX_IRQn, - UART3TX_IRQn, - &USART3_Info, - &USART3_TransferInfo -}; -#endif // USART Driver functions @@ -430,32 +308,6 @@ static int32_t USART_Receive ( void *data, usart->reg->STATE=0; } -// if ((usart->info->flags & USART_FLAG_CONFIGURED) == 0U) { -// // USART is not configured (mode not selected) -// return ARM_DRIVER_ERROR; -// } - -// // Check if receiver is busy -// if ((usart->info->status.rx_busy != 0U) || -// ((usart->reg->STATE & CMSDK_UART_STATE_RXBF_Msk) != 0U)) { -// return ARM_DRIVER_ERROR_BUSY; -// } - -// // Save number of data to be received -// usart->xfer->rx_num = num; - -// // Clear RX status -// usart->info->status.rx_overflow = 0U; - -// // Save receive buffer info -// usart->xfer->rx_buf = (uint8_t *)data; -// usart->xfer->rx_cnt = 0U; - -// // Set RX busy flag -// usart->info->status.rx_busy = 1U; - -// // RX interrupt enable -// usart->reg->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk; return ch; } @@ -667,23 +519,11 @@ static ARM_USART_MODEM_STATUS USART_GetModemStatus (const USART_RESOURCES *usart static void UartIsr(struct SerialBus *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev); + #ifdef BSP_USING_LPUART1 struct SerialBus serial_bus_1; struct SerialDriver serial_driver_1; struct SerialHardwareDevice serial_device_1; - -// void LPUART1_IRQHandler(int irqn, void *arg) -// { - -// DisableIRQ(UART1_IRQn); - -// UartIsr(&serial_bus_1, &serial_driver_1, &serial_device_1); -// // UART0TX_Handler(); -// EnableIRQ(UART1_IRQn); - -// } -// DECLARE_HW_IRQ(UART0TX_IRQn, UART0TX_Handler, NONE); -// DECLARE_HW_IRQ(UART0RX_IRQn, UART0RX_Handler, NONE); #endif @@ -695,10 +535,9 @@ struct SerialHardwareDevice serial_device_1; */ static void USARTRX_IRQHandler (USART_RESOURCES *usart) { uint32_t status; -// // KPrintf("RX Handler\n"); + status = usart->reg->INTSTATUS; -// if (usart->xfer->rx_buf != NULL) -// usart->xfer->rx_buf[usart->xfer->rx_cnt++] = (uint8_t)usart->reg->DATA; + usart->xfer->rx_num = 0U; usart->info->status.rx_busy = 0U; usart->reg->CTRL &= ~CMSDK_UART_CTRL_RXIRQEN_Msk; @@ -793,132 +632,7 @@ extern ARM_DRIVER_USART Driver_USART0; }; #endif -#ifdef BSP_USING_LPUART2 -// USART1 Driver Wrapper functions - void UART1RX_Handler (void); - void UART1TX_Handler (void); -static ARM_USART_CAPABILITIES USART1_GetCapabilities (void) { return USART_GetCapabilities (&USART1_Resources); } -static int32_t USART1_Initialize (ARM_USART_SignalEvent_t cb_event) { return USART_Initialize (cb_event, &USART1_Resources); } -static int32_t USART1_Uninitialize (void) { return USART_Uninitialize (&USART1_Resources); } -static int32_t USART1_PowerControl (ARM_POWER_STATE state) { return USART_PowerControl (state, &USART1_Resources); } -static int32_t USART1_Send (const void *data, uint32_t num) { return USART_Send (data, num, &USART1_Resources); } -static int32_t USART1_Receive (void *data, uint32_t num) { return USART_Receive (data, num, &USART1_Resources); } -static int32_t USART1_Transfer (const void *data_out, void *data_in, uint32_t num) { return USART_Transfer (data_out, data_in, num, &USART1_Resources); } -static uint32_t USART1_GetTxCount (void) { return USART_GetTxCount (&USART1_Resources); } -static uint32_t USART1_GetRxCount (void) { return USART_GetRxCount (&USART1_Resources); } -static int32_t USART1_Control (uint32_t control, uint32_t arg) { return USART_Control (control, arg, &USART1_Resources); } -static ARM_USART_STATUS USART1_GetStatus (void) { return USART_GetStatus (&USART1_Resources); } -static int32_t USART1_SetModemControl (ARM_USART_MODEM_CONTROL control) { return USART_SetModemControl (control, &USART1_Resources); } -static ARM_USART_MODEM_STATUS USART1_GetModemStatus (void) { return USART_GetModemStatus (&USART1_Resources); } - void UART1RX_Handler (void) { USARTRX_IRQHandler (&USART1_Resources); } - void UART1TX_Handler (void) { USARTTX_IRQHandler (&USART1_Resources); } -// USART1 Driver Control Block -extern ARM_DRIVER_USART Driver_USART1; - ARM_DRIVER_USART Driver_USART1 = { - USARTx_GetVersion, - USART1_GetCapabilities, - USART1_Initialize, - USART1_Uninitialize, - USART1_PowerControl, - USART1_Send, - USART1_Receive, - USART1_Transfer, - USART1_GetTxCount, - USART1_GetRxCount, - USART1_Control, - USART1_GetStatus, - USART1_SetModemControl, - USART1_GetModemStatus -}; -#endif - -#ifdef BSP_USING_LPUART3 -// USART2 Driver Wrapper functions - void UART2RX_Handler (void); - void UART2TX_Handler (void); -static ARM_USART_CAPABILITIES USART2_GetCapabilities (void) { return USART_GetCapabilities (&USART2_Resources); } -static int32_t USART2_Initialize (ARM_USART_SignalEvent_t cb_event) { return USART_Initialize (cb_event, &USART2_Resources); } -static int32_t USART2_Uninitialize (void) { return USART_Uninitialize (&USART2_Resources); } -static int32_t USART2_PowerControl (ARM_POWER_STATE state) { return USART_PowerControl (state, &USART2_Resources); } -static int32_t USART2_Send (const void *data, uint32_t num) { return USART_Send (data, num, &USART2_Resources); } -static int32_t USART2_Receive (void *data, uint32_t num) { return USART_Receive (data, num, &USART2_Resources); } -static int32_t USART2_Transfer (const void *data_out, void *data_in, uint32_t num) { return USART_Transfer (data_out, data_in, num, &USART2_Resources); } -static uint32_t USART2_GetTxCount (void) { return USART_GetTxCount (&USART2_Resources); } -static uint32_t USART2_GetRxCount (void) { return USART_GetRxCount (&USART2_Resources); } -static int32_t USART2_Control (uint32_t control, uint32_t arg) { return USART_Control (control, arg, &USART2_Resources); } -static ARM_USART_STATUS USART2_GetStatus (void) { return USART_GetStatus (&USART2_Resources); } -static int32_t USART2_SetModemControl (ARM_USART_MODEM_CONTROL control) { return USART_SetModemControl (control, &USART2_Resources); } -static ARM_USART_MODEM_STATUS USART2_GetModemStatus (void) { return USART_GetModemStatus (&USART2_Resources); } - void UART2RX_Handler (void) { USARTRX_IRQHandler (&USART2_Resources); } - void UART2TX_Handler (void) { USARTTX_IRQHandler (&USART2_Resources); } - -// USART2 Driver Control Block -extern ARM_DRIVER_USART Driver_USART2; - ARM_DRIVER_USART Driver_USART2 = { - USARTx_GetVersion, - USART2_GetCapabilities, - USART2_Initialize, - USART2_Uninitialize, - USART2_PowerControl, - USART2_Send, - USART2_Receive, - USART2_Transfer, - USART2_GetTxCount, - USART2_GetRxCount, - USART2_Control, - USART2_GetStatus, - USART2_SetModemControl, - USART2_GetModemStatus -}; -#endif - -#ifdef BSP_USING_LPUART4 -// USART3 Driver Wrapper functions - void UART3RX_Handler (void); - void UART3TX_Handler (void); -static ARM_USART_CAPABILITIES USART3_GetCapabilities (void) { return USART_GetCapabilities (&USART3_Resources); } -static int32_t USART3_Initialize (ARM_USART_SignalEvent_t cb_event) { return USART_Initialize (cb_event, &USART3_Resources); } -static int32_t USART3_Uninitialize (void) { return USART_Uninitialize (&USART3_Resources); } -static int32_t USART3_PowerControl (ARM_POWER_STATE state) { return USART_PowerControl (state, &USART3_Resources); } -static int32_t USART3_Send (const void *data, uint32_t num) { return USART_Send (data, num, &USART3_Resources); } -static int32_t USART3_Receive (void *data, uint32_t num) { return USART_Receive (data, num, &USART3_Resources); } -static int32_t USART3_Transfer (const void *data_out, void *data_in, uint32_t num) { return USART_Transfer (data_out, data_in, num, &USART3_Resources); } -static uint32_t USART3_GetTxCount (void) { return USART_GetTxCount (&USART3_Resources); } -static uint32_t USART3_GetRxCount (void) { return USART_GetRxCount (&USART3_Resources); } -static int32_t USART3_Control (uint32_t control, uint32_t arg) { return USART_Control (control, arg, &USART3_Resources); } -static ARM_USART_STATUS USART3_GetStatus (void) { return USART_GetStatus (&USART3_Resources); } -static int32_t USART3_SetModemControl (ARM_USART_MODEM_CONTROL control) { return USART_SetModemControl (control, &USART3_Resources); } -static ARM_USART_MODEM_STATUS USART3_GetModemStatus (void) { return USART_GetModemStatus (&USART3_Resources); } - void UART3RX_Handler (void) { USARTRX_IRQHandler (&USART3_Resources); } - void UART3TX_Handler (void) { USARTTX_IRQHandler (&USART3_Resources); } - -// USART3 Driver Control Block -extern ARM_DRIVER_USART Driver_USART3; - ARM_DRIVER_USART Driver_USART3 = { - USARTx_GetVersion, - USART3_GetCapabilities, - USART3_Initialize, - USART3_Uninitialize, - USART3_PowerControl, - USART3_Send, - USART3_Receive, - USART3_Transfer, - USART3_GetTxCount, - USART3_GetRxCount, - USART3_Control, - USART3_GetStatus, - USART3_SetModemControl, - USART3_GetModemStatus -}; -#endif - - -// extern int stdout_init (void); -// extern int stdout_putchar (int ch); -// extern int stdout_receivechar(); -// extern void UART0TX_Handler(); -// extern void UART0RX_Handler(); #define _USART_Driver_(n) Driver_USART##n From e055ffdc2c63d121cb0c2d029d1dfc62122f156e Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Wed, 27 Sep 2023 15:54:00 +0800 Subject: [PATCH 13/21] modify microkernel --- .../XiZi_AIoT/hardkernel/abstraction/TLB.c | 56 ------------------- .../XiZi_AIoT/hardkernel/abstraction/cache.c | 42 +++++++------- .../XiZi_AIoT/hardkernel/abstraction/cache.h | 43 +++++++------- .../hardkernel/abstraction/l1cache.c | 21 +++++++ .../hardkernel/abstraction/l1cache.h | 33 +++++------ .../XiZi_AIoT/hardkernel/abstraction/l2cc.h | 43 +++++++------- .../hardkernel/abstraction/l2cc_pl310.c | 2 +- 7 files changed, 101 insertions(+), 139 deletions(-) delete mode 100755 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/TLB.c diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/TLB.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/TLB.c deleted file mode 100755 index 45ce50e3b..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/TLB.c +++ /dev/null @@ -1,56 +0,0 @@ - - -#define CP15_TLBIALLIS(r) _CP15(0, r, c8, c3, 0) /* Invalidate entire unified TLB Inner Shareable */ -#define CP15_TLBIMVAIS(r) _CP15(0, r, c8, c3, 1) /* Invalidate unified TLB entry by MVA and ASID, Inner Shareable */ -#define CP15_TLBIASIDIS(r) _CP15(0, r, c8, c3, 2) /* Invalidate unified TLB by ASID match Inner Shareable */ -#define CP15_TLBIMVAAIS(r) _CP15(0, r, c8, c3, 3) /* Invalidate unified TLB entry by MVA all ASID Inner Shareable */ -#define CP15_TLBIALL(r,c) _CP15(0, r, c8, c, 0) /* Invalidate entire instruction TLB. CRm = c5, c6, or c7 */ -#define CP15_TLBIMVA(r,c) _CP15(0, r, c8, c, 1) /* Invalidate instruction TLB entry by MVA and ASID. CRm = c5, c6, or c7 */ -#define CP15_TLBIASID(r,c) _CP15(0, r, c8, c, 2) /* Invalidate data TLB by ASID match. CRm = c5, c6, or c7 */ -#define CP15_TLBIMVAA(r,c) _CP15(0, r, c8, c, 3) /* Invalidate unified TLB entry by MVA and ASID. CRm = c5, c6, or c7 */ - -void InvalidateTlbsAll(void) -{ - __asm__ __volatile__ - ( - "\tmcr p15, 0, r0, c8, c7, 0\n" /* TLBIALL */ - : - : - : "r0", "memory" - ); -} - -void InvalidateTlbMVA(uint32_t vaddr) -{ - __asm__ __volatile__ - ( - "\tdsb\n" - - "\tmcr p15, 0, %0, c8, c7, 1\n" /* TLBIMVA */ - - "\tdsb\n" - "\tisb\n" - : - : "r" (vaddr) - : "r1", "memory" - ); -} - - -void InvalidateTlbASID(uint32_t vaddr) -{ - __asm__ __volatile__ - ( - "\tdsb\n" - - "\tmcr p15, 0, %0, c8, c7, 2\n" /* TLBIASID */ - - "\tdsb\n" - "\tisb\n" - : - : "r" (vaddr) - : "r1", "memory" - ); -} - - diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c index 6e613f117..42c0d2c72 100755 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c @@ -1,26 +1,24 @@ -/**************************************************************************** - * arch/arm/src/armv7-a/arm_cache.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: cache.c +* @brief: the general management of cache +* @version: 3.0 +* @author: AIIT XUOS Lab +* @date: 2023/4/27 +* +*/ -/**************************************************************************** - * Included Files - ****************************************************************************/ #include "cache.h" diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.h index fb42509fa..5a8a84ace 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.h @@ -1,25 +1,24 @@ -/**************************************************************************** - * include/nuttx/cache.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: cache.h +* @brief: the general management of cache +* @version: 3.0 +* @author: AIIT XUOS Lab +* @date: 2023/4/27 +* +*/ -#ifndef __INCLUDE_NUTTX_CACHE_H -#define __INCLUDE_NUTTX_CACHE_H #ifndef __ASSEMBLY__ @@ -416,4 +415,4 @@ void coherent_dcache(uintptr_t addr, size_t len); #endif /* __ASSEMBLY__ */ -#endif /* __INCLUDE_NUTTX_CACHE_H */ + diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.c index 2e2be4d97..b74c0ce69 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.c @@ -1,3 +1,24 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: l1cache.c +* @brief: the general management of L1 cache +* @version: 3.0 +* @author: AIIT XUOS Lab +* @date: 2023/4/27 +* +*/ + #include "l1cache.h" #include "cp15_cacheops.h" #include "barriers.h" diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.h index 757157cae..7a507457a 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.h @@ -1,22 +1,23 @@ /* - * Copyright (c) 2022 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ /** - * @file l1cache.c - * @brief PLC inovance am401 app - * @version 3.0 - * @author AIIT XUOS Lab - * @date 2023.8.10 - */ +* @file: l1cache.h +* @brief: the general management of L1 cache +* @version: 3.0 +* @author: AIIT XUOS Lab +* @date: 2023/4/27 +* +*/ #include #include diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc.h index 5b858e3a3..18118e85d 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc.h @@ -1,25 +1,24 @@ -/**************************************************************************** - * arch/arm/src/armv7-a/l2cc.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ +/* + * Copyright (c) 2022 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file l2cc.h + * @brief the general management of L2 cache + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.8.10 + */ + -#ifndef __ARCH_ARM_SRC_ARMV7_A_L2CC_H -#define __ARCH_ARM_SRC_ARMV7_A_L2CC_H /**************************************************************************** * Included Files @@ -240,4 +239,4 @@ void FlushL2Cache(uint32_t startaddr, uint32_t endaddr); # define FlushL2Cache(s,e) #endif /* CONFIG_ARCH_L2CACHE */ -#endif /* __ARCH_ARM_SRC_ARMV7_A_L2CC_H */ + diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.c index 0bc4712a1..981657b57 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.c @@ -12,7 +12,7 @@ /** * @file l2cc_pl310.c - * @brief PLC inovance am401 app + * @brief the general management of L2 cache * @version 3.0 * @author AIIT XUOS Lab * @date 2023.8.10 From cc4106dd111a52ddac28225b0ee6d4d597b50ac0 Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Wed, 27 Sep 2023 15:58:37 +0800 Subject: [PATCH 14/21] imx6q dts --- .../arch/arm/armv7-a/cortex-a9/device.h | 4 ++-- .../arch/arm/armv7-a/cortex-a9/imx6q_desc.c | 21 +++++++++++++++++++ 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/device.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/device.h index 0b3bde014..4a366b2a3 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/device.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/device.h @@ -11,8 +11,8 @@ */ /** - * @file l2cc_pl310.c - * @brief PLC inovance am401 app + * @file device.h + * @brief struct of imx6q devices * @version 3.0 * @author AIIT XUOS Lab * @date 2023.8.10 diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q_desc.c b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q_desc.c index b413d364e..bdca2b4a3 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q_desc.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q_desc.c @@ -1,3 +1,24 @@ +/* + * Copyright (c) 2022 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file imx6q_desc.c + * @brief config imx6q devices + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.8.10 + */ + + #include "device.h" From 6c40800dfe15f86036acf7d51191980a3db4ceb9 Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Wed, 27 Sep 2023 16:04:55 +0800 Subject: [PATCH 15/21] delete cjson process --- APP_Framework/lib/cJSON/Makefile | 1 - APP_Framework/lib/cJSON/cJSON_Process.c | 85 ------------------------- APP_Framework/lib/cJSON/cJSON_Process.h | 23 ------- 3 files changed, 109 deletions(-) delete mode 100644 APP_Framework/lib/cJSON/cJSON_Process.c delete mode 100644 APP_Framework/lib/cJSON/cJSON_Process.h diff --git a/APP_Framework/lib/cJSON/Makefile b/APP_Framework/lib/cJSON/Makefile index 8d2e20e45..79f1fc37d 100755 --- a/APP_Framework/lib/cJSON/Makefile +++ b/APP_Framework/lib/cJSON/Makefile @@ -1,4 +1,3 @@ SRC_FILES := cJSON.c -SRC_FILES += cJSON_Process.c include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/lib/cJSON/cJSON_Process.c b/APP_Framework/lib/cJSON/cJSON_Process.c deleted file mode 100644 index 12490a10b..000000000 --- a/APP_Framework/lib/cJSON/cJSON_Process.c +++ /dev/null @@ -1,85 +0,0 @@ -#include "cJSON_Process.h" -#include - - - - - -cJSON* cJSON_Data_Init(void) -{ - cJSON* cJSON_Root = NULL; //json根节点 - - - cJSON_Root = cJSON_CreateObject(); /*创建项目*/ - if(NULL == cJSON_Root) - { - return NULL; - } - cJSON_AddStringToObject(cJSON_Root, NAME, DEFAULT_NAME); /*添加元素 键值对*/ - cJSON_AddNumberToObject(cJSON_Root, TEMP_NUM, DEFAULT_TEMP_NUM); - cJSON_AddNumberToObject(cJSON_Root, HUM_NUM, DEFAULT_HUM_NUM); - - char* p = cJSON_Print(cJSON_Root); /*p 指向的字符串是json格式的*/ - - p = NULL; - - return cJSON_Root; - -} -uint8_t cJSON_Update(const cJSON * const object,const char * const string,void *d) -{ - cJSON* node = NULL; //json根节点 - node = cJSON_GetObjectItem(object,string); - if(node == NULL) - return 0; - if(cJSON_IsBool(node)) - { - int *b = (int*)d; - - cJSON_GetObjectItem(object,string)->type = *b ? cJSON_True : cJSON_False; - - return 1; - } - else if(cJSON_IsString(node)) - { - cJSON_GetObjectItem(object,string)->valuestring = (char*)d; - - return 1; - } - else if(cJSON_IsNumber(node)) - { - double *num = (double*)d; - - cJSON_GetObjectItem(object,string)->valuedouble = (double)*num; - - return 1; - } - else - return 1; -} - -void Proscess(void* data) -{ - - cJSON *root,*json_name,*json_temp_num,*json_hum_num; - root = cJSON_Parse((char*)data); //解析成json形式 - - json_name = cJSON_GetObjectItem( root , NAME); //获取键值内容 - json_temp_num = cJSON_GetObjectItem( root , TEMP_NUM ); - json_hum_num = cJSON_GetObjectItem( root , HUM_NUM ); - - lw_print("name:%s\n temp_num:%f\n hum_num:%f\n", - json_name->valuestring, - json_temp_num->valuedouble, - json_hum_num->valuedouble); - - cJSON_Delete(root); //释放内存 -} - - - - - - - - diff --git a/APP_Framework/lib/cJSON/cJSON_Process.h b/APP_Framework/lib/cJSON/cJSON_Process.h deleted file mode 100644 index 5dcdd3bf5..000000000 --- a/APP_Framework/lib/cJSON/cJSON_Process.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef _CJSON_PROCESS_H_ -#define _CJSON_PROCESS_H_ -#include "cJSON.h" -#include "stdint.h" - - -#define NAME "name" -#define TEMP_NUM "temp" -#define HUM_NUM "hum" - -#define DEFAULT_NAME "fire" -#define DEFAULT_TEMP_NUM 25.0 -#define DEFAULT_HUM_NUM 50.0 - - -#define UPDATE_SUCCESS 1 -#define UPDATE_FAIL 0 - -cJSON* cJSON_Data_Init(void); -uint8_t cJSON_Update(const cJSON * const object,const char * const string,void * d); -void Proscess(void* data); -#endif - From c17c899ea7d7c2dd1d027a087126fd5699e6f108 Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Wed, 11 Oct 2023 17:08:19 +0800 Subject: [PATCH 16/21] add m7 readme --- APP_Framework/Applications/app_test/Makefile | 2 +- .../board/cortex-m7-emulator/README.md | 208 ++++++++++++++++++ .../board/cortex-m7-emulator/img/main.png | Bin 0 -> 14917 bytes .../cortex-m7-emulator/img/menuconfig.png | Bin 0 -> 30527 bytes .../cortex-m7-emulator/img/menuconfig1.png | Bin 0 -> 17909 bytes .../board/cortex-m7-emulator/img/terminal.png | Bin 0 -> 53801 bytes .../board/cortex-m7-emulator/img/vscode.jpg | Bin 0 -> 57472 bytes 7 files changed, 209 insertions(+), 1 deletion(-) create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/README.md create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/img/main.png create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/img/menuconfig.png create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/img/menuconfig1.png create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/img/terminal.png create mode 100644 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/img/vscode.jpg diff --git a/APP_Framework/Applications/app_test/Makefile b/APP_Framework/Applications/app_test/Makefile index 1e89361c4..7ae722f47 100644 --- a/APP_Framework/Applications/app_test/Makefile +++ b/APP_Framework/Applications/app_test/Makefile @@ -24,7 +24,7 @@ endif ifeq ($(CONFIG_ADD_XIZI_FEATURES),y) SRC_FILES := test_shell.c - + ifeq ($(CONFIG_USER_TEST_ADC),y) SRC_FILES += test_adc.c endif diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/README.md b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/README.md new file mode 100644 index 000000000..53909b165 --- /dev/null +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/README.md @@ -0,0 +1,208 @@ +# 从零开始构建矽璓工业物联操作系统：使用ARM架构的cortex-m7 emulator + +[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓XiUOS是一款面向智慧车间的工业物联网操作系统，主要由一个极简的微型实时操作系统内核和其上的工业物联框架构成，通过高效管理工业物联网设备、支撑工业物联应用，在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”，促进以工业设备和工业控制系统为核心的人、机、物深度互联，帮助提升生产线的数字化和智能化水平。 + + + +## 1. 简介 + +Q‎EMU 是一个通用的开源模拟器和虚拟化工具。目前Q‎EMU已经可以较完整的支持ARM cortex-m4架构。XiUOS同样支持运行在Q‎EMU上 + +| 硬件 | 描述 | +| -------- | ------------- | +| 芯片型号 | mps2-an500 | +| 架构 | cortex-m7 | +| 主频 | 168MHz | +| 片内SRAM | 100+KB | +| 外设支持 | UART、GPIO | + + + +## 2. 开发环境搭建 + +### 推荐使用： + +**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop) + +更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改） + +第一步:打开sources.list文件 + +```c +sudo vim /etc/apt/sources.list +``` + +第二步:将以下内容复制到sources.list文件 + +```c +deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +``` + +第三步:更新源和系统软件 + +```c +sudo apt-get update +sudo apt-get upgrade +``` + +**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb) + +### 依赖包安装： + +``` +$ sudo apt install build-essential pkg-config git +$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev +``` + +**XiUOS操作系统源码下载：** XiUOS [https://www.gitlink.org.cn/xuos/xiuos](https://www.gitlink.org.cn/xuos/xiuos) + +新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下： + +```c +mkdir test && cd test +git clone https://gitlink.org.cn/xuos/xiuos.git +``` + +1、打开XiUOS源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| APP_Framework | 应用代码 | +| Ubiquitous | 板级支持包,支持NuttX、RT-Thread和XiZi内核 | + +2、打开XiZi内核源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| arch | 架构代码 | +| board | 板级支持包 | +| fs | 文件系统 | +| kernel | 内核源码 | +| lib | 第三方库源码 | +| resources | 驱动文件 | +| tool | 系统工具 | + +使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示： + +
+ +
+ + +### 裁减配置工具的下载 + +裁减配置工具： + +**工具地址：** kconfig-frontends [https://www.gitlink.org.cn/xuos/kconfig-frontends](https://www.gitlink.org.cn/xuos/kconfig-frontends)，下载与安装的具体命令如下： + +```c +mkdir kfrontends && cd kfrontends +git clone https://gitlink.org.cn/xuos/kconfig-frontends.git +``` + +下载源码后按以下步骤执行软件安装： + +```c +cd kconfig-frontends +./xs_build.sh +``` + +### 编译工具链： + +ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。 + +```shell +$ sudo apt install gcc-arm-none-eabi +``` + + + +## 3. 编译说明 + +### 编辑环境：`Ubuntu18.04` + +### 编译工具链：`arm-none-eabi-gcc` + +使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目 + + +编译步骤： + +1.在VScode命令终端中执行以下命令，生成配置文件 + +```c +cd ./Ubiquitous/XiZi +make BOARD=cortex-m7-emulator distclean +make BOARD=cortex-m7-emulator menuconfig +``` + +2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置） + +
+ +
+ +退出时选择`yes`保存上面所配置的内容，如下图所示： + +
+ +
+ +3.继续执行以下命令，进行编译 + +``` +make BOARD=cortex-m7-emulator +``` + +4.如果编译正确无误，会产生XiZi-cortex-m7-emulator.elf、XiZi-cortex-m7-emulator.bin文件。 + + + +## 4. 运行 + +### 4.1 安装Q‎EMU + +``` +sudo apt install qemu-system-arm +``` + +### 4.2 运行结果 + +通过以下命令启动Q‎EMU并加载XiUOS ELF文件 + +``` +qemu-system-arm -machine mps2-an500 -nographic -kernel build/XiZi-cortex-m7-emulator.elf +``` + +QEMU运行起来后将会在终端上看到信息打印输出 + +
+ +
+ +### 4.3 调试 + +通过Q‎EMU可以方便的对XiUOS进行调试，首先安装gdb调试工具 + +``` +sudo apt install gdb-multiarch +``` + +并通过以下命令启动Q‎EMU + +``` +qemu-system-arm -machine mps2-an500 -nographic -kernel build/XiZi-cortex-m7-emulator.elf -s -S +``` + +然后要重新开启另一个linux系统终端一个终端，执行`riscv-none-embed-gdb`命令 + +``` +gdb-multiarch build/XiZi-cortex-m7-emulator.elf -ex "target remote localhost:1234" +``` \ No newline at end of file diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/img/main.png b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/img/main.png new file mode 100644 index 0000000000000000000000000000000000000000..9c1102b067524519ccf7b867e61db4e558692907 GIT binary patch literal 14917 zcmbt*byS?qnaQ$sssT6xexvgLVyE*w?;2(fggzWk{V7B z5a`Z-Kagvt#O~nCPtIaLoR#fNo!tx^O(2wQE$j`PoK19a##bRANFct8ep7KzJ6#3* zP%(M#x~%L93qv6xN0Ou;j`A(eqDj_b+>L1!Pj2|ptTH_@U8bwY%Fa4g$El?)1=1ca zlNrgMVPjQR9>rvs64e%R_=t=985;;3t+In2?+Uu#Z)vL790iPDr{Qtk1Ll+m*4N+R zgb_&ns|Y@@>p+nDe-y@~=+^j~!HS+1@KG3nm;8T_G+N#$L+KeBTQAU9Axc9qKa{rb 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zYd?Fp$sbie>do4#|M+ro@w?}DdvY}2rY2ds`Irfr=~Vj#1+HoGOO2|1+oVp_A27dU zcwRn{qvC!%b6mu$|Cbhw@%(E8{>QnjD$QG8gr6qULE8MLc1QB1F7_`b+AK0JIdbA~ zL_4LNKWnPbY=5wEDv2&BGuZ##CRux@+ha_)(CngUe_V;Rh1Cbz8FH|=-)zVNcV zQ~5m^VA$}@_$9pW!*hh8Q_H)7Avpc{*~J^GHMf-Ur`9#UcV1@K@_vuy$K_SBhF{cc zAD-_ubb|(^)_XCa|Mkz$c2D>gobg8P)L(YE3;e!VCBN|deR#f9QZF Date: Wed, 11 Oct 2023 17:20:52 +0800 Subject: [PATCH 17/21] remove aiot --- .../XiZi_AIoT/hardkernel/abstraction/Makefile | 3 - .../hardkernel/abstraction/abstraction_mmu.c | 206 --- .../hardkernel/abstraction/abstraction_mmu.h | 114 -- .../hardkernel/abstraction/barriers.h | 42 - .../XiZi_AIoT/hardkernel/abstraction/cache.c | 363 ------ .../XiZi_AIoT/hardkernel/abstraction/cache.h | 418 ------ .../hardkernel/abstraction/cp15_cacheops.h | 1141 ----------------- .../abstraction/cp15_coherent_dcache.S | 138 -- .../XiZi_AIoT/hardkernel/abstraction/isr.c | 215 ---- .../XiZi_AIoT/hardkernel/abstraction/isr.h | 98 -- .../hardkernel/abstraction/l1cache.c | 300 ----- .../hardkernel/abstraction/l1cache.h | 131 -- .../XiZi_AIoT/hardkernel/abstraction/l2cc.h | 242 ---- .../hardkernel/abstraction/l2cc_pl310.c | 866 ------------- .../hardkernel/abstraction/l2cc_pl310.h | 483 ------- .../arch/arm/armv7-a/cortex-a9/device.h | 72 -- .../arch/arm/armv7-a/cortex-a9/imx6q_desc.c | 77 -- 17 files changed, 4909 deletions(-) delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/Makefile delete mode 100755 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction_mmu.c delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction_mmu.h delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/barriers.h delete mode 100755 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.h delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cp15_cacheops.h delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cp15_coherent_dcache.S delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.c delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.h delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.c delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.h delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc.h delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.c delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.h delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/device.h delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q_desc.c diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/Makefile deleted file mode 100644 index c794367b8..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -SRC_FILES := cache.c isr.c abstraction_mmu.c - -include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction_mmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction_mmu.c deleted file mode 100755 index 6f37b7d6f..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction_mmu.c +++ /dev/null @@ -1,206 +0,0 @@ -/* -* Copyright (c) 2020 AIIT XUOS Lab -* XiUOS is licensed under Mulan PSL v2. -* You can use this software according to the terms and conditions of the Mulan PSL v2. -* You may obtain a copy of Mulan PSL v2 at: -* http://license.coscl.org.cn/MulanPSL2 -* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -* See the Mulan PSL v2 for more details. -*/ - -/** -* @file: abstraction_mmu.c -* @brief: the general management of system mmu -* @version: 3.0 -* @author: AIIT XUOS Lab -* @date: 2023/4/27 -* -*/ - -#include - -AbstractionMmu abstraction_mmu; - -volatile uint32_t global_L1_pte_table[4096]; - -/** - * @description: write cmd to CP15 register - * @param reg_type - CP15 register type - * @param val - ops val pointer - * @return - */ -static void MmuCp15Write(uint8_t reg_type, uint32_t *val) -{ - uint32_t write_val = *val; - switch (reg_type) { - case AM_MMU_CP15_TTBCR: - TTBCR_W(write_val); - AM_ISB; - case AM_MMU_CP15_TTBR0: - TTBR0_W(write_val); - AM_ISB; - default: - break; - } -} - -/** - * @description: read CP15 register from mmu - * @param reg_type - CP15 register type - * @param val - ops val pointer - * @return - */ -static void MmuCp15Read(uint8_t reg_type, uint32_t *val) -{ - uint32_t read_val = 0; - switch (reg_type) { - case AM_MMU_CP15_TTBCR: - TTBCR_R(read_val); - case AM_MMU_CP15_TTBR0: - TTBR0_R(read_val); - default: - break; - } - - *val = read_val; -} - -/** - * @description: write or read CP15 register to set mmu - * @param ops_type - CP15 write or read - * @param reg_type - CP15 register type - * @param val - ops val pointer - * @return - */ -static void MmuRegOps(uint8_t ops_type, uint8_t reg_type, uint32_t *val) -{ - switch (ops_type) { - case AM_MMU_CP15_WRITE: - MmuCp15Write(reg_type, val); - case AM_MMU_CP15_READ: - MmuCp15Read(reg_type, val); - default: - break; - } -} - -/** - * @description: Init abstraction_mmu function - * @param mmu - abstraction mmu pointer - * @param ttb_base - ttb base pointer - * @return success : 0 error : -1 - */ -static int _AbstractionMmuInit(AbstractionMmu *mmu, uint32_t *ttb_base) -{ - mmu_init(); - - return 0; -} - -/** - * @description: map L1 or L2 page table section - * @param mmu - abstraction mmu pointer - * @param section_size - section size - * @return success : 0 error : -1 - */ -static int _AbstractionMmuSectionMap(AbstractionMmu *mmu, uint32_t section_size) -{ - uint32_t vaddr_length = mmu->vaddr_end - mmu->vaddr_start + 1; - - mmu_map_l1_range(mmu->paddr_start, mmu->vaddr_start, vaddr_length, - mmu->mmu_memory_type, mmu->mmu_shareability, mmu->mmu_access); - - mmu->mmu_status = 1; - - return 0; -} - -/** - * @description: unmap L1 or L2 page table section - * @param mmu - abstraction mmu pointer - * @param vaddr_start - virtual address start - * @param vaddr_size - virtual address size - * @return success : 0 error : -1 - */ -static int _AbstractionMmuSectionUnmap(AbstractionMmu *mmu, uint32_t vaddr_start, uint32_t vaddr_size) -{ - uint32_t *l1_umap_ventry = mmu->ttb_vbase + (vaddr_start >> AM_MMU_L1_SECTION_SHIFT); - uint32_t vaddr_end = vaddr_start + vaddr_size - 1; - uint32_t umap_count = (vaddr_end >> AM_MMU_L1_SECTION_SHIFT) - (vaddr_start >> AM_MMU_L1_SECTION_SHIFT) + 1; - - while (umap_count) { - AM_DMB; - *l1_umap_ventry = 0; - AM_DSB; - - umap_count--; - l1_umap_ventry += (1 << AM_MMU_L1_SECTION_SHIFT);//1MB section - } - - AM_DSB; - CLEARTLB(0);//clear TLB data and configure - AM_DSB; - AM_ISB; - mmu->mmu_status = 0; - - return 0; -} - -/** - * @description: switch ttb base by re-write ttbr register - * @param mmu - abstraction mmu pointer - * @return success : 0 error : -1 - */ -static int _AbstractionMmuTtbSwitch(AbstractionMmu *mmu) -{ - uint32_t ttbr, ttbcr; - MmuRegOps(AM_MMU_CP15_READ, AM_MMU_CP15_TTBCR, &ttbcr); - - /* Set TTBR0 with inner/outer write back write allocate and not shareable, [4:3]=01, [1]=0, [6,0]=01 */ - ttbr = ((mmu->ttb_pbase & 0xFFFFC000UL) | 0x9UL); - /* enable TTBR0 */ - ttbcr = 0; - - AM_DSB; - MmuRegOps(AM_MMU_CP15_WRITE, AM_MMU_CP15_TTBR0, &ttbr); - MmuRegOps(AM_MMU_CP15_WRITE, AM_MMU_CP15_TTBCR, &ttbcr); - - return 0; -} - -/** - * @description: get physical address transformed from virtual address - * @param mmu - abstraction mmu pointer - * @param vaddr - virtual address pointer - * @param paddr - physical address pointer - * @return success : 0 error : -1 - */ -static int _AbstracktonMmuTransform(AbstractionMmu *mmu, uint32_t *vaddr, uint32_t *paddr) -{ - uint32_t virtualAddress = *vaddr; - - if (mmu->mmu_status) { - mmu_virtual_to_physical(virtualAddress, paddr); - } - - return 0; -} - -static struct AbstractionMmuDone mmu_done = { - .AbstractionMmuInit = _AbstractionMmuInit, - .AbstractionMmuSectionMap = _AbstractionMmuSectionMap, - .AbstractionMmuSectionUnmap = _AbstractionMmuSectionUnmap, - .AbstractionMmuTtbSwitch = _AbstractionMmuTtbSwitch, - .AbstracktonMmuTransform = _AbstracktonMmuTransform, -}; - -/** - * @description: init abstraciton mmu info when system start - * @return success : 0 error : -1 - */ -int SysInitAbstractionMmu(void) -{ - abstraction_mmu.mmu_done = &mmu_done; -} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction_mmu.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction_mmu.h deleted file mode 100644 index ce3c35d06..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction_mmu.h +++ /dev/null @@ -1,114 +0,0 @@ -/* -* Copyright (c) 2020 AIIT XUOS Lab -* XiUOS is licensed under Mulan PSL v2. -* You can use this software according to the terms and conditions of the Mulan PSL v2. -* You may obtain a copy of Mulan PSL v2 at: -* http://license.coscl.org.cn/MulanPSL2 -* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -* See the Mulan PSL v2 for more details. -*/ - -/** -* @file: mmu.h -* @brief: the general management of system mmu -* @version: 3.0 -* @author: AIIT XUOS Lab -* @date: 2023/5/24 -* -*/ -#include -#include - -#define ARCH_ARM -#ifdef ARCH_ARM -/* ARM System Registers */ -#define AM_DSB __asm__ volatile("dsb" ::: "memory") -#define AM_DMB __asm__ volatile("dmb" ::: "memory") -#define AM_ISB __asm__ volatile("isb" ::: "memory") -#define AM_WFI __asm__ volatile("wfi" ::: "memory") -#define AM_BARRIER __asm__ volatile("":::"memory") -#define AM_WFE __asm__ volatile("wfe" ::: "memory") -#define AM_SEV __asm__ volatile("sev" ::: "memory") - -#define TTBR0_R(val) __asm__ volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(val)) -#define TTBR0_W(val) __asm__ volatile("mcr p15, 0, %0, c2, c0, 0" ::"r"(val)) - -#define TTBCR_R(val) __asm__ volatile("mrc p15, 0, %0, c2, c0, 2" : "=r"(val)) -#define TTBCR_W(val) __asm__ volatile("mcr p15, 0, %0, c2, c0, 2" ::"r"(val)) - -#define CLEARTLB(val) __asm__ volatile("mcr p15, 0, %0, c8, c7, 0" ::"r"(val)) -#endif - -#define AM_MMU_L1_PAGE_TABLE_SIZE (4 * 4096) -#define AM_MMU_L1_SECTION_SHIFT 20 - -typedef enum -{ - AM_MMU_CP15_WRITE = 0, - AM_MMU_CP15_READ, -}MmuCP15OpsType; - -typedef enum -{ - AM_MMU_CP15_TTBCR = 0, - AM_MMU_CP15_TTBR0, - AM_MMU_CP15_CLEARTLB, -}MmuCP15RegType; - -typedef enum -{ - AM_StronglyOrdered = 0, - AM_Device, - AM_OuterInner_WB_WA, - AM_OuterInner_WT, - AM_Noncacheable, -}MmuMemoryType; - -typedef enum -{ - AM_Noaccess = 0, - AM_Read_Write, - AM_Read, -}MmuAccess; - -typedef enum -{ - AM_Shareable = 1, - AM_Nonshareable = 0 -}MmuShareability; - -struct AbstractionMmuDone -{ - int (*AbstractionMmuInit)(AbstractionMmu *mmu, uint32_t *ttb_base); - int (*AbstractionMmuSectionMap)(AbstractionMmu *mmu, uint32_t section_size); - int (*AbstractionMmuSectionUnmap)(AbstractionMmu *mmu, uint32_t vaddr_start, uint32_t vaddr_size); - int (*AbstractionMmuTtbSwitch)(AbstractionMmu *mmu); - int (*AbstracktonMmuTransform)(AbstractionMmu *mmu, uint32_t *vaddr, uint32_t *paddr); -}; - -typedef struct -{ - uint32_t ttb_vbase; - uint32_t ttb_pbase; - - uint32_t vaddr_start; - uint32_t vaddr_end; - uint32_t paddr_start; - uint32_t paddr_end; - - uint32_t vpaddr_offset; - - uint32_t pte_attr; - uint32_t mmu_status; - - MmuMemoryType mmu_memory_type; - MmuAccess mmu_access; - MmuShareability mmu_shareability; - - struct AbstractionMmuDone *mmu_done; - - int lock; - int link_list; -}AbstractionMmu; \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/barriers.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/barriers.h deleted file mode 100644 index 70e98e5d4..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/barriers.h +++ /dev/null @@ -1,42 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-a/barriers.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_ARMV7_A_BARRIERS_H -#define __ARCH_ARM_SRC_ARMV7_A_BARRIERS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* ARMv7-A memory barriers */ - -#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory") -#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory") -#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory") - -#define ARM_DSB() arm_dsb(15) -#define ARM_ISB() arm_isb(15) -#define ARM_DMB() arm_dmb(15) - -#endif /* __ARCH_ARM_SRC_ARMV7_A_BARRIERS_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c deleted file mode 100755 index 42c0d2c72..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c +++ /dev/null @@ -1,363 +0,0 @@ -/* -* Copyright (c) 2020 AIIT XUOS Lab -* XiUOS is licensed under Mulan PSL v2. -* You can use this software according to the terms and conditions of the Mulan PSL v2. -* You may obtain a copy of Mulan PSL v2 at: -* http://license.coscl.org.cn/MulanPSL2 -* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -* See the Mulan PSL v2 for more details. -*/ - -/** -* @file: cache.c -* @brief: the general management of cache -* @version: 3.0 -* @author: AIIT XUOS Lab -* @date: 2023/4/27 -* -*/ - - - -#include "cache.h" -#include "cp15_cacheops.h" -#include "barriers.h" -#include "l1cache.h" -#include "l2cc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ -struct ICacheDone -{ - uint32_t (*enable) (void ); - uint32_t (*disable) (void); - uint32_t (*invalidate) (uintptr_t start, uintptr_t end); - uint32_t (*invalidateall) (void ); -}; - -static const struct ICacheDone icache_done = -{ - .enable = enable_icache, - .disable = disable_icache, - .invalidate = invalidate_icache, - .invalidateall = invalidate_icache_all, -}; - - -struct DCacheDone -{ - uint32_t (*enable) (void ); - uint32_t (*disable) (void); - uint32_t (*clean) (uintptr_t start, uintptr_t end); - uint32_t (*flush) (uintptr_t start, uintptr_t end); - uint32_t (*invalidate) (uintptr_t start, uintptr_t end); - uint32_t (*cleanall) (void); - uint32_t (*flushall) (void); - uint32_t (*invalidateall) (void); -}; - -static const struct DCacheDone dcache_done = -{ - .enable = enable_dcache, - .disable = disable_dcache, - .clean = clean_dcache, - .flush = flush_dcache, - .invalidate = invalidate_dcache, - .cleanall = clean_dcache_all, - .flushall = flush_dcache_all, - .invalidateall = invalidate_dcache_all, -}; - - -/**************************************************************************** - * Name: invalidate_dcache - * - * Description: - * Invalidate the data cache within the specified region; we will be - * performing a DMA operation in this region and we want to purge old data - * in the cache. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -void invalidate_dcache(uintptr_t start, uintptr_t end) -{ - InvalidateL1Dcache(start, end); - InvalidateL2Cache(start, end); -} - -/**************************************************************************** - * Name: invalidate_dcache_all - * - * Description: - * Invalidate the entire contents of D cache. - * - * NOTE: This function forces L1 and L2 cache operations to be atomic - * by disabling interrupts. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void invalidate_dcache_all(void) -{ - InvalidateL1DcacheAll(); - -#ifdef CONFIG_ARCH_L2CACHE - InvalidateL2CacheAll(); -#endif - -} - -/**************************************************************************** - * Name: invalidate_icache - * - * Description: - * Invalidate the instruction cache within the specified region. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ -void invalidate_icache(uintptr_t start, uintptr_t end) -{ - InvalidateL1Icache(start, end); -} - -/**************************************************************************** - * Name: invalidate_icache_all - * - * Description: - * Invalidate all instruction caches to PoU, also flushes branch target - * cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void invalidate_icache_all(void) -{ - InvalidateL1IcacheAll(); -} - -/**************************************************************************** - * Name: clean_dcache - * - * Description: - * Clean the data cache within the specified region by flushing the - * contents of the data cache to memory. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -void clean_dcache(uintptr_t start, uintptr_t end) -{ - - CleanL1Dcache(start, end); - CleanL2Cache(start, end); -} - -/**************************************************************************** - * Name: clean_dcache_all - * - * Description: - * Clean the entire data cache within the specified region by flushing the - * contents of the data cache to memory. - * - * NOTE: This operation is un-necessary if the DCACHE is configured in - * write-through mode. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -void clean_dcache_all(void) -{ - CleanL1DcacheAll(); - CleanL2CacheAll(); -} - -/**************************************************************************** - * Name: flush_dcache - * - * Description: - * Flush the data cache within the specified region by cleaning and - * invalidating the D cache. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -void flush_dcache(uintptr_t start, uintptr_t end) -{ - - FlushL1Dcache(start, end); - - - FlushL2Cache(start, end); -} - -/**************************************************************************** - * Name: flush_dcache_all - * - * Description: - * Flush the entire data cache by cleaning and invalidating the D cache. - * - * NOTE: If DCACHE write-through is configured, then this operation is the - * same as invalidate_cache_all(). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - * Assumptions: - * This operation is not atomic. This function assumes that the caller - * has exclusive access to the address range so that no harm is done if - * the operation is pre-empted. - * - ****************************************************************************/ - -void flush_dcache_all(void) -{ - FlushL1DcacheAll(); - - FlushL2CacheAll(); -} - -/**************************************************************************** - * Name: enable_icache - * - * Description: - * Enable the I-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void enable_icache(void) -{ - EnableL1Icache(); -} - -/**************************************************************************** - * Name: disable_icache - * - * Description: - * Disable the I-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void disable_icache(void) -{ - DisableL1Icache(); -} - -/**************************************************************************** - * Name: enable_dcache - * - * Description: - * Enable the D-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void enable_dcache(void) -{ - EnableL1Dcache(); - EnableL2Cache(); -} - -/**************************************************************************** - * Name: disable_dcache - * - * Description: - * Disable the D-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void disable_dcache(void) -{ - DisableL1Dcache(); - DisableL2Cache(); -} - - diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.h deleted file mode 100644 index 5a8a84ace..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.h +++ /dev/null @@ -1,418 +0,0 @@ -/* -* Copyright (c) 2020 AIIT XUOS Lab -* XiUOS is licensed under Mulan PSL v2. -* You can use this software according to the terms and conditions of the Mulan PSL v2. -* You may obtain a copy of Mulan PSL v2 at: -* http://license.coscl.org.cn/MulanPSL2 -* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -* See the Mulan PSL v2 for more details. -*/ - -/** -* @file: cache.h -* @brief: the general management of cache -* @version: 3.0 -* @author: AIIT XUOS Lab -* @date: 2023/4/27 -* -*/ - - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - - - -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: enable_icache - * - * Description: - * Enable the I-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - * Caution: - * The writable global variables aren't initialized yet. - * - ****************************************************************************/ -void enable_icache(void); - - -/**************************************************************************** - * Name: disable_icache - * - * Description: - * Disable the I-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ -void disable_icache(void); - - -/**************************************************************************** - * Name: invalidate_icache - * - * Description: - * Invalidate the instruction cache within the specified region. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ -void invalidate_icache(uintptr_t start, uintptr_t end); - - -/**************************************************************************** - * Name: invalidate_icache_all - * - * Description: - * Invalidate the entire contents of I cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - - -void invalidate_icache_all(void); - -/**************************************************************************** - * Name: lock_icache - * - * Description: - * Prefetch and lock the instruction cache within the specified region. - * If the specified address if not present in the instruction cache, - * some architectures transfer the line from memory, others wait the - * address be read from memory, and then lock. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ - -void lock_icache(uintptr_t start, uintptr_t end); - - -/**************************************************************************** - * Name: unlock_icache - * - * Description: - * Unlock the instruction cache within the specified region. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ - -void unlock_icache(uintptr_t start, uintptr_t end); - - -/**************************************************************************** - * Name: unlock_icache_all - * - * Description: - * Unlock the entire contents of instruction cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - - -void unlock_icache_all(void); - - -/**************************************************************************** - * Name: enable_dcache - * - * Description: - * Enable the D-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - * Caution: - * The writable global variables aren't initialized yet. - * - ****************************************************************************/ - - -void enable_dcache(void); - - -/**************************************************************************** - * Name: disable_dcache - * - * Description: - * Disable the D-Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - - -void disable_dcache(void); - - -/**************************************************************************** - * Name: invalidate_dcache - * - * Description: - * Invalidate the data cache within the specified region; we will be - * performing a DMA operation in this region and we want to purge old data - * in the cache. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ - - -void invalidate_dcache(uintptr_t start, uintptr_t end); - - -/**************************************************************************** - * Name: invalidate_dcache_all - * - * Description: - * Invalidate the entire contents of D cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - - -void invalidate_dcache_all(void); - - -/**************************************************************************** - * Name: clean_dcache - * - * Description: - * Clean the data cache within the specified region by flushing the - * contents of the data cache to memory. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ - - -void clean_dcache(uintptr_t start, uintptr_t end); - - -/**************************************************************************** - * Name: clean_dcache_all - * - * Description: - * Clean the entire data cache within the specified region by flushing the - * contents of the data cache to memory. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - - -void clean_dcache_all(void); - - -/**************************************************************************** - * Name: flush_dcache - * - * Description: - * Flush the data cache within the specified region by cleaning and - * invalidating the D cache. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ - - -void flush_dcache(uintptr_t start, uintptr_t end); - - -/**************************************************************************** - * Name: flush_dcache_all - * - * Description: - * Flush the entire data cache by cleaning and invalidating the D cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - - -void flush_dcache_all(void); - - -/**************************************************************************** - * Name: lock_dcache - * - * Description: - * Prefetch and lock the data cache within the specified region. - * If the specified address is not present in the data cache, - * some architectures transfer the line from memory, others wait the - * address be read from memory, and then lock. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ - - -void lock_dcache(uintptr_t start, uintptr_t end); - - -/**************************************************************************** - * Name: unlock_dcache - * - * Description: - * Unlock the data cache within the specified region. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ - -void unlock_dcache(uintptr_t start, uintptr_t end); - - -/**************************************************************************** - * Name: unlock_dcache_all - * - * Description: - * Unlock the entire contents of data cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - - -void unlock_dcache_all(void); - - -/**************************************************************************** - * Name: coherent_dcache - * - * Description: - * Ensure that the I and D caches are coherent within specified region - * by cleaning the D cache (i.e., flushing the D cache contents to memory - * and invalidating the I cache. This is typically used when code has been - * written to a memory region, and will be executed. - * - * Input Parameters: - * addr - virtual start address of region - * len - Size of the address region in bytes - * - * Returned Value: - * None - * - ****************************************************************************/ - - -void coherent_dcache(uintptr_t addr, size_t len); - - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ - - diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cp15_cacheops.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cp15_cacheops.h deleted file mode 100644 index 18fad4d8c..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cp15_cacheops.h +++ /dev/null @@ -1,1141 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-a/cp15_cacheops.h - * - * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Portions of this file derive from Atmel sample code for the SAMA5D3 - * Cortex-A5 which also has a modified BSD-style license: - * - * Copyright (c) 2012, Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor Atmel nor the names of the contributors may - * be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/* References: - * - * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1, - * Copyright 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810) - * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition", - * Copyright 1996-1998, 2000, 2004-2012 ARM. - * All rights reserved. ARM DDI 0406C.b (ID072512) - */ - -#ifndef __ARCH_ARM_SRC_ARMV7_A_CP15_CACHEOPS_H -#define __ARCH_ARM_SRC_ARMV7_A_CP15_CACHEOPS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Cache definitions ********************************************************/ - -/* L1 Memory */ - -#define CP15_L1_LINESIZE 32 - -/* CP15 Registers ***********************************************************/ - -/* Reference: Cortex-A5 MPCore - * Paragraph 4.1.5, "Cache Operations Registers." - * - * Terms: - * 1) Point of coherency (PoC) - * The PoC is the point at which all agents that can access memory are - * guaranteed to see the same copy of a memory location - * 2) Point of unification (PoU) - * The PoU is the point by which the instruction and data caches and the - * translation table walks of the processor are guaranteed to see the same - * copy of a memory location. - * - * Cache Operations: - * - * CP15 Register: ICIALLUIS - * Description: Invalidate entire instruction cache Inner Shareable. - * Register Format: Should be zero (SBZ) - * Instruction: MCR p15, 0, , c7, c1, 0 - * CP15 Register: BPIALLIS - * Description: Invalidate entire branch predictor array Inner - * Shareable. - * Register Format: Should be zero (SBZ) - * Instruction: MCR p15, 0, , c7, c1, 6 - * CP15 Register: ICIALLU - * Description: Invalidate all instruction caches to PoU. Also flushes - * branch target cache. - * Register Format: Should be zero (SBZ) - * Instruction: MCR p15, 0, , c7, c5, 0 - * CP15 Register: ICIMVAU - * Description: Invalidate instruction cache by VA to PoU. - * Register Format: VA - * Instruction: MCR p15, 0, , c7, c5, 1 - * CP15 Register: BPIALL - * Description: Invalidate entire branch predictor array. - * Register Format: Should be zero (SBZ) - * Instruction: MCR p15, 0, , c7, c5, 6 - * CP15 Register: BPIMVA - * Description: Invalidate VA from branch predictor array. - * Register Format: Should be zero (SBZ) - * Instruction: MCR p15, 0, , c7, c5, 7 - * CP15 Register: DCIMVAC - * Description: Invalidate data cache line by VA to PoC. - * Register Format: VA - * Instruction: MCR p15, 0, , c7, c6, 1 - * CP15 Register: DCISW - * Description: Invalidate data cache line by Set/Way. - * Register Format: Set/Way - * Instruction: MCR p15, 0, , c7, c6, 2 - * CP15 Register: DCCMVAC - * Description: Clean data cache line to PoC by VA. - * Register Format: VA - * Instruction: MCR p15, 0, , c7, c10, 1 - * CP15 Register: DCCSW - * Description: Clean data cache line by Set/Way. - * Register Format: Set/Way - * Instruction: MCR p15, 0, , c7, c10, 2 - * CP15 Register: DCCMVAU - * Description: Clean data or unified cache line by VA to PoU. - * Register Format: VA - * Instruction: MCR p15, 0, , c7, c11, 1 - * CP15 Register: DCCIMVAC - * Description: Clean and invalidate data cache line by VA to PoC. - * Register Format: VA - * Instruction: MCR p15, 0, , c7, c14, 1 - * CP15 Register: DCCISW - * Description: Clean and invalidate data cache line by Set/Way. - * Register Format: Set/Way - * Instruction: MCR p15, 0, , c7, c14, 2 - */ - -/* Set/way format */ - -#define CACHE_WAY_SHIFT (3) /* Bits 30-31: Way in set being accessed */ -#define CACHE_WAY_MASK (3 << CACHE_WAY_SHIFT) -#define CACHE_SET_SHIFT (5) /* Bits 5-(S+4): Way in set being accessed */ - /* For 4KB cache size: S=5 */ -#define CACHE_SET4KB_MASK (0x1f << CACHE_SET_SHIFT) - /* Bits 10-29: Reserved */ - /* For 8KB cache size: S=6 */ -#define CACHE_SET8KB_MASK (0x3f << CACHE_SET_SHIFT) - /* Bits 11-29: Reserved */ - /* For 16KB cache size: S=7 */ -#define CACHE_SET16KB_MASK (0x7f << CACHE_SET_SHIFT) - /* Bits 12-29: Reserved */ - /* For 32KB cache size: S=8 */ -#define CACHE_SET32KB_MASK (0xff << CACHE_SET_SHIFT) - /* Bits 13-29: Reserved */ - /* For 64KB cache size: S=9 */ -#define CACHE_SET64KB_MASK (0x1fff << CACHE_SET_SHIFT) - /* Bits 14-29: Reserved */ - -/* VA and SBZ format */ - -#define CACHE_SBZ_SHIFT (4) /* Bits 0-4: Should be zero (SBZ) */ -#define CACHE_SBZ_MASK (31 << TLB_SBZ_SHIFT) -#define CACHE_VA_MASK (0xfffffffe0) /* Bits 5-31: Virtual address */ - -/**************************************************************************** - * Assembly Macros - ****************************************************************************/ - -/* cp15_cache Cache Operations - * - * Usage - * - * They are performed as MCR instructions and only operate on a level 1 cache - * associated with ARM v7 processor. - * - * The supported operations are: - * - * 1. Any of these operations can be applied to any data cache or any - * unified cache. - * 2. Invalidate by MVA. Performs an invalidate of a data or unified cache - * line - * based on the address it contains. - * 3. Invalidate by set/way. Performs an invalidate of a data or unified - * cache line based on its location in the cache hierarchy. - * 4. Clean by MVA. Performs a clean of a data or unified cache line based - * on the address it contains. - * 5. Clean by set/way. Performs a clean of a data or unified cache line - * based on its location in the cache hierarchy. - * 6. Clean and Invalidate by MVA. Performs a clean and invalidate of a - * data or unified cache line based on the address it contains. - * 7. Clean and Invalidate by set/way. Performs a clean and invalidate of - * a data or unified cache line based on its location in the cache - * hierarchy. - * - * NOTE: Many of these operations are implemented as assembly language - * macros or as C inline functions in the file cache.h. The larger functions - * are implemented here as C-callable functions. - */ - -#ifdef __ASSEMBLY__ - -/**************************************************************************** - * Name: cp15_enable_dcache - * - * Description: - * Enable L1 D Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -.macro cp15_enable_dcache, tmp - mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ - orr \tmp, \tmp, #(0x1 << 2) /* Enable D cache */ - mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ -.endm - -/**************************************************************************** - * Name: cp15_disable_dcache - * - * Description: - * Disable L1 D Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -.macro cp15_disable_dcache, tmp - mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ - bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */ - mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ -.endm - -/**************************************************************************** - * Name: cp15_enable_icache - * - * Description: - * Enable L1 I Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -.macro cp15_enable_icache, tmp - mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ - orr \tmp, \tmp, #(0x1 << 12) /* Enable I cache */ - mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ -.endm - -/**************************************************************************** - * Name: cp15_disable_icache - * - * Description: - * Disable L1 I Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -.macro cp15_disable_icache, tmp - mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ - bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */ - mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ -.endm - -/**************************************************************************** - * Name: cp15_invalidate_icache_inner_sharable - * - * Description: - * Invalidate I cache predictor array inner shareable - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -.macro cp15_invalidate_icache_inner_sharable, tmp - mov \tmp, #0 - mrc p15, 0, \tmp, c7, c1, 0 /* ICIALLUIS */ -.endm - -/**************************************************************************** - * Name: cp15_invalidate_btb_inner_sharable - * - * Description: - * Invalidate entire branch predictor array inner shareable - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -.macro cp15_invalidate_btb_inner_sharable, tmp - mov \tmp, #0 - mrc p15, 0, \tmp, c7, c1, 6 /* BPIALLIS */ -.endm - -/**************************************************************************** - * Name: cp15_invalidate_icache - * - * Description: - * Invalidate all instruction caches to PoU, also flushes branch target - * cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -.macro cp15_invalidate_icache, tmp - mov \tmp, #0 - mrc p15, 0, \tmp, c7, c5, 0 /* ICIALLU */ -.endm - -/**************************************************************************** - * Name: cp15_invalidate_icache_bymva - * - * Description: - * Invalidate instruction caches by VA to PoU - * - * Input Parameters: - * va - Register with VA format - * - * Returned Value: - * None - * - ****************************************************************************/ - -.macro cp15_invalidate_icache_bymva, va - mrc p15, 0, \va, c7, c5, 1 /* ICIMVAU */ -.endm - -/**************************************************************************** - * Name: cp15_flush_btb - * - * Description: - * Invalidate entire branch predictor array - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -.macro cp15_flush_btb, tmp - mov \tmp, #0 - mrc p15, 0, \tmp, c7, c5, 6 /* BPIALL */ -.endm - -/**************************************************************************** - * Name: cp15_flush_btb_bymva - * - * Description: - * Invalidate branch predictor array entry by MVA - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -.macro cp15_flush_btb_bymva, tmp - mov \tmp, #0 - mrc p15, 0, \tmp, c7, c5, 7 /* BPIMVA */ -.endm - -/**************************************************************************** - * Name: cp15_invalidate_dcacheline_bymva - * - * Description: - * Invalidate data cache line by VA to PoC - * - * Input Parameters: - * va - Register with VA format - * - * Returned Value: - * None - * - ****************************************************************************/ - -.macro cp15_invalidate_dcacheline_bymva, va - mrc p15, 0, \va, c7, c6, 1 /* DCIMVAC */ -.endm - -/**************************************************************************** - * Name: cp15_invalidate_dcacheline_bysetway - * - * Description: - * Invalidate data cache line by set/way - * - * Input Parameters: - * setway - Register with Set/Way format - * - * Returned Value: - * None - * - ****************************************************************************/ - -.macro cp15_invalidate_dcacheline_bysetway, setway - mrc p15, 0, \setway, c7, c6, 2 /* DCISW */ -.endm - -/**************************************************************************** - * Name: cp15_clean_dcache_bymva - * - * Description: - * Clean data cache line by MVA - * - * Input Parameters: - * va - Register with VA format - * - * Returned Value: - * None - * - ****************************************************************************/ - -.macro cp15_clean_dcache_bymva, va - mrc p15, 0, \va, c7, c10, 1 /* DCCMVAC */ -.endm - -/**************************************************************************** - * Name: cp15_clean_dcache_bysetway - * - * Description: - * Clean data cache line by Set/way - * - * Input Parameters: - * setway - Register with Set/Way format - * - * Returned Value: - * None - * - ****************************************************************************/ - -.macro cp15_clean_dcache_bysetway, setway - mrc p15, 0, \setway, c7, c10, 2 /* DCCSW */ -.endm - -/**************************************************************************** - * Name: cp15_clean_ucache_bymva - * - * Description: - * Clean unified cache line by MVA - * - * Input Parameters: - * setway - Register with VA format - * - * Returned Value: - * None - * - ****************************************************************************/ - -.macro cp15_clean_ucache_bymva, setway - mrc p15, 0, \setway, c7, c11, 1 /* DCCMVAU */ -.endm - -/**************************************************************************** - * Name: cp15_cleaninvalidate_dcacheline_bymva - * - * Description: - * Clean and invalidate data cache line by VA to PoC - * - * Input Parameters: - * va - Register with VA format - * - * Returned Value: - * None - * - ****************************************************************************/ - -.macro cp15_cleaninvalidate_dcacheline_bymva, va - mrc p15, 0, \va, c7, c14, 1 /* DCCIMVAC */ -.endm - -/**************************************************************************** - * Name: cp15_cleaninvalidate_dcacheline - * - * Description: - * Clean and Incalidate data cache line by Set/Way - * - * Input Parameters: - * setway - Register with Set/Way format - * - * Returned Value: - * None - * - ****************************************************************************/ - -.macro cp15_cleaninvalidate_dcacheline, setway - mrc p15, 0, \setway, c7, c14, 2 /* DCCISW */ -.endm - -#endif /* __ASSEMBLY__ */ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Name: cp15_enable_dcache - * - * Description: - * Enable L1 D Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void cp15_enable_dcache(void) -{ - __asm__ __volatile__ - ( - "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ - "\torr r0, r0, #(1 << 2)\n" /* Enable D cache */ - "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ - : - : - : "r0", "memory" - ); -} - -/**************************************************************************** - * Name: cp15_disable_dcache - * - * Description: - * Disable L1 D Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void cp15_disable_dcache(void) -{ - __asm__ __volatile__ - ( - "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ - "\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */ - "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ - : - : - : "r0", "memory" - ); -} - -/**************************************************************************** - * Name: cp15_enable_icache - * - * Description: - * Enable L1 I Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void cp15_enable_icache(void) -{ - __asm__ __volatile__ - ( - "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ - "\torr r0, r0, #(1 << 12)\n" /* Enable I cache */ - "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ - : - : - : "r0", "memory" - ); -} - -/**************************************************************************** - * Name: cp15_disable_icache - * - * Description: - * Disable L1 I Cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void cp15_disable_icache(void) -{ - __asm__ __volatile__ - ( - "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */ - "\tbic r0, r0, #(1 << 12)\n" /* Disable I cache */ - "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */ - : - : - : "r0", "memory" - ); -} - -/**************************************************************************** - * Name: cp15_invalidate_icache_inner_sharable - * - * Description: - * Invalidate I cache predictor array inner shareable - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void cp15_invalidate_icache_inner_sharable(void) -{ - __asm__ __volatile__ - ( - "\tmov r0, #0\n" - "\tmcr p15, 0, r0, c7, c1, 0\n" /* ICIALLUIS */ - : - : - : "r0", "memory" - ); -} - -/**************************************************************************** - * Name: cp15_invalidate_btb_inner_sharable - * - * Description: - * Invalidate entire branch predictor array inner shareable - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void cp15_invalidate_btb_inner_sharable(void) -{ - __asm__ __volatile__ - ( - "\tmov r0, #0\n" - "\tmcr p15, 0, r0, c7, c1, 6\n" /* BPIALLIS */ - : - : - : "r0", "memory" - ); -} - -/**************************************************************************** - * Name: cp15_invalidate_icache - * - * Description: - * Invalidate all instruction caches to PoU, also flushes branch target - * cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void cp15_invalidate_icache(void) -{ - __asm__ __volatile__ - ( - "\tmov r0, #0\n" - "\tmcr p15, 0, r0, c7, c5, 0\n" /* ICIALLU */ - : - : - : "r0", "memory" - ); -} - -/**************************************************************************** - * Name: cp15_invalidate_icache_bymva - * - * Description: - * Invalidate instruction caches by VA to PoU - * - * Input Parameters: - * va - 32-bit value with VA format - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void cp15_invalidate_icache_bymva(unsigned int va) -{ - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c5, 1\n" /* ICIMVAU */ - : - : "r" (va) - : "memory" - ); -} - -/**************************************************************************** - * Name: cp15_flush_btb - * - * Description: - * Invalidate entire branch predictor array - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void cp15_flush_btb(void) -{ - __asm__ __volatile__ - ( - "\tmov r0, #0\n" - "\tmcr p15, 0, r0, c7, c5, 6\n" /* BPIALL */ - : - : - : "r0", "memory" - ); -} - -/**************************************************************************** - * Name: cp15_flush_btb_bymva - * - * Description: - * Invalidate branch predictor array entry by MVA - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void cp15_flush_btb_bymva(void) -{ - __asm__ __volatile__ - ( - "\tmov r0, #0\n" - "\tmcr p15, 0, r0, c7, c5, 7\n" /* BPIMVA */ - : - : - : "r0", "memory" - ); -} - -/**************************************************************************** - * Name: cp15_invalidate_dcacheline_bymva - * - * Description: - * Invalidate data cache line by VA to PoC - * - * Input Parameters: - * va - 32-bit value with VA format - * - * Returned Value: - * None - * - ****************************************************************************/ - -/* Invalidate data cache line by VA to PoC */ - -static inline void cp15_invalidate_dcacheline_bymva(unsigned int va) -{ - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c6, 1\n" /* DCIMVAC */ - : - : "r" (va) - : "memory" - ); -} - -/**************************************************************************** - * Name: cp15_invalidate_dcacheline_bysetway - * - * Description: - * Invalidate data cache line by set/way - * - * Input Parameters: - * setway - 32-bit value with Set/Way format - * - * Returned Value: - * None - * - ****************************************************************************/ - -/* Invalidate data cache line by set/way */ - -static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway) -{ - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c6, 2\n" /* DCISW */ - : - : "r" (setway) - : "memory" - ); -} - -/**************************************************************************** - * Name: cp15_clean_dcache_bymva - * - * Description: - * Clean data cache line by MVA - * - * Input Parameters: - * va - 32-bit value with VA format - * - * Returned Value: - * None - * - ****************************************************************************/ - -/* Clean data cache line by MVA */ - -static inline void cp15_clean_dcache_bymva(unsigned int va) -{ - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c10, 1\n" /* DCCMVAC */ - : - : "r" (va) - : "memory" - ); -} - -/**************************************************************************** - * Name: cp15_clean_dcache_bysetway - * - * Description: - * Clean data cache line by Set/way - * - * Input Parameters: - * setway - 32-bit value with Set/Way format - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void cp15_clean_dcache_bysetway(unsigned int setway) -{ - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c10, 2\n" /* DCCSW */ - : - : "r" (setway) - : "memory" - ); -} - -/**************************************************************************** - * Name: cp15_clean_ucache_bymva - * - * Description: - * Clean unified cache line by MVA - * - * Input Parameters: - * setway - 32-bit value with VA format - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void cp15_clean_ucache_bymva(unsigned int setway) -{ - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c11, 1\n" /* DCCMVAU */ - : - : "r" (setway) - : "memory" - ); -} - -/**************************************************************************** - * Name: cp15_cleaninvalidate_dcacheline_bymva - * - * Description: - * Clean and invalidate data cache line by VA to PoC - * - * Input Parameters: - * va - 32-bit value with VA format - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va) -{ - __asm__ __volatile__ - ( - "\tmcr p15, 0, r0, c7, c14, 1\n" /* DCCIMVAC */ - : - : "r" (va) - : "memory" - ); -} - -/**************************************************************************** - * Name: cp15_cleaninvalidate_dcacheline - * - * Description: - * Clean and Incalidate data cache line by Set/Way - * - * Input Parameters: - * setway - 32-bit value with Set/Way format - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void cp15_cleaninvalidate_dcacheline(unsigned int setway) -{ - __asm__ __volatile__ - ( - "\tmcr p15, 0, %0, c7, c14, 2\n" /* DCCISW */ - : - : "r" (setway) - : "memory" - ); -} - -#endif /* __ASSEMBLY__ */ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: cp15_coherent_dcache - * - * Description: - * Ensure that the I and D caches are coherent within specified region - * by cleaning the D cache (i.e., flushing the D cache contents to memory - * and invalidating the I cache). This is typically used when code has been - * written to a memory region, and will be executed. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ - -void cp15_coherent_dcache(uintptr_t start, uintptr_t end); - -/**************************************************************************** - * Name: cp15_invalidate_dcache - * - * Description: - * Invalidate the data cache within the specified region; we will be - * performing a DMA operation in this region and we want to purge old data - * in the cache. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ - -void cp15_invalidate_dcache(uintptr_t start, uintptr_t end); - -/**************************************************************************** - * Name: cp15_invalidate_dcache_all - * - * Description: - * Invalidate the entire contents of D cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void cp15_invalidate_dcache_all(void); - -/**************************************************************************** - * Name: cp15_clean_dcache - * - * Description: - * Clean the data cache within the specified region by flushing the - * contents of the data cache to memory. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ - -void cp15_clean_dcache(uintptr_t start, uintptr_t end); - -/**************************************************************************** - * Name: cp15_clean_dcache_all - * - * Description: - * Clean the entire contents of D cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void cp15_clean_dcache_all(void); - -/**************************************************************************** - * Name: cp15_flush_dcache - * - * Description: - * Flush the data cache within the specified region by cleaning and - * invalidating the D cache. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ - -void cp15_flush_dcache(uintptr_t start, uintptr_t end); - -/**************************************************************************** - * Name: cp15_flush_dcache_all - * - * Description: - * Flush the entire contents of D cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void cp15_flush_dcache_all(void); - -/**************************************************************************** - * Name: cp15_cache_size - * - * Description: - * Get cp15 cache size in byte - * - * Input Parameters: - * None - * - * Returned Value: - * Cache size in byte - * - ****************************************************************************/ - -uint32_t cp15_cache_size(void); - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_SRC_ARMV7_A_CP15_CACHEOPS_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cp15_coherent_dcache.S b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cp15_coherent_dcache.S deleted file mode 100644 index 88c5feb4c..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cp15_coherent_dcache.S +++ /dev/null @@ -1,138 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-a/cp15_coherent_dcache.S - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Portions of this file derive from Atmel sample code for the SAMA5D3 - * Cortex-A5 which also has a modified BSD-style license: - * - * Copyright (c) 2012, Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor Atmel nor the names of the contributors may - * be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/* References: - * - * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1, - * Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810) - * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition", - * Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM - * DDI 0406C.b (ID072512) - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "cp15.h" - - .file "cp15_coherent_dcache.S" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - - .globl cp15_coherent_dcache - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - - .text - -/**************************************************************************** - * Name: cp15_coherent_dcache - * - * Description: - * Ensure that the I and D caches are coherent within specified region - * by cleaning the D cache (i.e., flushing the D cache contents to memory - * and invalidating the I cache. This is typically used when code has been - * written to a memory region, and will be executed. - * - * Input Parameters: - * start - virtual start address of region - * end - virtual end address of region + 1 - * - * Returned Value: - * None - * - ****************************************************************************/ - - .globl cp15_coherent_dcache - .type cp15_coherent_dcache, function - -cp15_coherent_dcache: - mrc CP15_CTR(r3) /* Read the Cache Type Register */ - lsr r3, r3, #16 /* Isolate the DMinLine field */ - and r3, r3, #0xf - mov r2, #4 - mov r2, r2, lsl r3 /* Get the cache line size in bytes */ - - sub r3, r2, #1 /* R3=Cache line size mask */ - bic r12, r0, r3 /* R12=aligned start address */ - - /* Loop, flushing each D cache line to memory */ -1: - mcr CP15_DCCMVAU(r12) /* Clean data or unified cache line by VA to PoU */ - add r12, r12, r2 /* R12=Next cache line */ - cmp r12, r1 /* Loop until all cache lines have been cleaned */ - blo 1b - - dsb - - mrc CP15_CTR(r3) /* Read the Cache Type Register */ - and r3, r3, #0xf /* Isolate the IminLine field */ - mov r2, #4 - mov r2, r2, lsl r3 /* Get the cache line size in bytes */ - - sub r3, r2, #1 /* R3=Cache line size mask */ - bic r12, r0, r3 /* R12=aligned start address */ - - /* Loop, invalidating each I cache line to memory */ -1: - mcr CP15_ICIMVAU(r12) /* Invalidate instruction cache by VA to PoU */ - add r12, r12, r2 /* R12=Next cache line */ - cmp r12, r1 /* Loop until all cache lines have been invalidated */ - blo 1b - - mov r0, #0 - mcr CP15_BPIALLIS(r0) /* Invalidate entire branch predictor array Inner Shareable */ - mcr CP15_BPIALL(r0) /* Invalidate entire branch predictor array Inner Shareable */ - - dsb - isb - bx lr - .size cp15_coherent_dcache, . - cp15_coherent_dcache - .end diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.c deleted file mode 100644 index 94dbc9fb1..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.c +++ /dev/null @@ -1,215 +0,0 @@ -/* -* Copyright (c) 2020 AIIT XUOS Lab -* XiUOS is licensed under Mulan PSL v2. -* You can use this software according to the terms and conditions of the Mulan PSL v2. -* You may obtain a copy of Mulan PSL v2 at: -* http://license.coscl.org.cn/MulanPSL2 -* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -* See the Mulan PSL v2 for more details. -*/ - -/** -* @file: isr.c -* @brief: the general management of system isr -* @version: 1.0 -* @author: AIIT XUOS Lab -* @date: 2020/3/15 -* -*/ -#include -#include "isr.h" - -struct InterruptServiceRoutines isrManager = {0} ; - -#ifdef ARCH_SMP -extern int GetCpuId(void); -#endif -/** - * This functionwill get the isr nest level. - * - * @return isr nest level - */ -static uint16_t GetIsrCounter() -{ - uint16_t ret = 0; - -#ifdef ARCH_SMP - ret = isrManager.isr_count[GetCpuId()]; -#else - ret = isrManager.isr_count; -#endif - return ret; -} - -static void IncIsrCounter() -{ -#ifdef ARCH_SMP - isrManager.isr_count[GetCpuId()] ++ ; -#else - isrManager.isr_count ++; -#endif - return ; -} - -static void DecIsrCounter() -{ - -#ifdef ARCH_SMP - isrManager.isr_count[GetCpuId()] -- ; -#else - isrManager.isr_count --; -#endif - return ; -} - -bool IsInIsr() -{ -#ifdef ARCH_SMP - return ( isrManager.isr_count[GetCpuId()] != 0 ? TRUE : FALSE ) ; -#else - return ( isrManager.isr_count != 0 ? TRUE : FALSE ) ; -#endif - -} -/** - * This function will register a new irq. - * - * @param irq_num the number of the irq - * @param handler the callback of the interrupt - * @param arg param of thge callback - * - * @return 0 on success; -1 on failure - */ -static int32_t RegisterHwIrq(uint32_t irq_num, IsrHandlerType handler, void *arg) -{ - if (irq_num >= ARCH_MAX_IRQ_NUM ) - return -1; - - struct IrqDesc *desc = &isrManager.irq_table[irq_num]; - - desc->handler = handler; - desc->param = arg; - - return 0; -} -/** - * This function will free a irq. - * - * @param irq_num the number of the irq - * - * @return 0 on success; -1 on failure - */ -static int32_t FreeHwIrq(uint32_t irq_num) -{ - if (irq_num >= ARCH_MAX_IRQ_NUM ) - return -1; - - memset(&isrManager.irq_table[irq_num], 0, sizeof(struct IrqDesc)); - - return 0; -} - -/** - * This function will enable a irq. - * - * @param irq_num the number of the irq - * - * @return 0 on success; -1 on failure - */ -static int32_t EnableHwIrq(uint32_t irq_num, uint32_t cpu_id) -{ - if (irq_num >= ARCH_MAX_IRQ_NUM ) - return -1; - - return ArchEnableHwIrq(irq_num, cpu_id); -} -/** - * This function will disable a irq. - * - * @param irq_num the number of the irq - * - * @return 0 on success; -1 on failure - */ - -static int32_t DisableHwIrq(uint32_t irq_num, uint32_t cpu_id) -{ - if (irq_num >= ARCH_MAX_IRQ_NUM ) - return -1; - - return ArchDisableHwIrq(irq_num, cpu_id); -} - -/* called from arch-specific ISR wrapper */ -static void IsrCommon(uint32_t irq_num) -{ - struct IrqDesc *desc = &isrManager.irq_table[irq_num]; - - if (desc->handler == NULL) { - // SYS_KDEBUG_LOG(KDBG_IRQ, ("Spurious interrupt: IRQ No. %d\n", irq_num)); - while (1) {} - } - desc->handler(irq_num, desc->param); - -} - -static void SetIsrSwitchTrigerFlag() -{ - -#ifdef ARCH_SMP - isrManager.isr_switch_trigger_flag[GetCpuId()] = 1; -#else - isrManager.isr_switch_trigger_flag = 1; -#endif -} - -static void ClearIsrSwitchTrigerFlag() -{ - -#ifdef ARCH_SMP - isrManager.isr_switch_trigger_flag[GetCpuId()] = 0; -#else - isrManager.isr_switch_trigger_flag = 0; -#endif -} - -static uint8_t GetIsrSwitchTrigerFlag() -{ - -#ifdef ARCH_SMP - return isrManager.isr_switch_trigger_flag[GetCpuId()]; -#else - return isrManager.isr_switch_trigger_flag ; -#endif -} - -struct IsrDone isrDone = { - IsInIsr, - RegisterHwIrq , - FreeHwIrq, - EnableHwIrq, - DisableHwIrq, - IsrCommon, - GetIsrCounter, - IncIsrCounter, - DecIsrCounter, - GetIsrSwitchTrigerFlag, - SetIsrSwitchTrigerFlag, - ClearIsrSwitchTrigerFlag -}; - -void SysInitIsrManager() -{ - extern int __isrtbl_idx_start; - extern int __isrtbl_start; - extern int __isrtbl_end; - memset(&isrManager,0,sizeof(struct InterruptServiceRoutines)); - isrManager.done = &isrDone; - - uint32_t *index = (uint32_t *)&__isrtbl_idx_start; - struct IrqDesc *desc = (struct IrqDesc *)&__isrtbl_start; - - while (desc != (struct IrqDesc *)&__isrtbl_end) - isrManager.irq_table[*index++] = *desc++; -} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.h deleted file mode 100644 index 1e0ddcfbf..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.h +++ /dev/null @@ -1,98 +0,0 @@ -/* -* Copyright (c) 2020 AIIT XUOS Lab -* XiUOS is licensed under Mulan PSL v2. -* You can use this software according to the terms and conditions of the Mulan PSL v2. -* You may obtain a copy of Mulan PSL v2 at: -* http://license.coscl.org.cn/MulanPSL2 -* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -* See the Mulan PSL v2 for more details. -*/ - -/** -* @file: isr.h -* @brief: function declaration and structure defintion of isr -* @version: 1.0 -* @author: AIIT XUOS Lab -* @date: 2020/3/10 -* -*/ - -#ifndef __ISR_H__ -#define __ISR_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - - -#define DECLARE_HW_IRQ(_irq_num, _handler, _arg) \ - const uint32_t __irq_desc_idx_##_handler SECTION(".isrtbl.idx") = _irq_num + ARCH_IRQ_NUM_OFFSET ; \ - const struct IrqDesc __irq_desc_##_handler SECTION(".isrtbl") = { \ - .handler = _handler, \ - .param = _arg, \ - } - -typedef void (*IsrHandlerType)(int vector, void *param); - -struct IrqDesc -{ - IsrHandlerType handler; - void *param; - -#ifdef CONFIG_INTERRUPT_INFO - char name[NAME_NUM_MAX]; - uint32_t counter; -#endif -}; - -struct IsrDone -{ - bool (*isInIsr)(); - int32_t (*registerIrq)(uint32_t irq_num, IsrHandlerType handler, void *arg); - int32_t (*freeIrq)(uint32_t irq_num); - int32_t (*enableIrq)(uint32_t irq_num, uint32_t cpu_id); - int32_t (*disableIrq)(uint32_t irq_num, uint32_t cpu_id); - void (*handleIrq)(uint32_t irq_num); - uint16_t (*getCounter)() ; - void (*incCounter)(); - void (*decCounter)(); - uint8_t (*getSwitchTrigerFlag)(); - void (*setSwitchTrigerFlag)(); - void (*clearSwitchTrigerFlag)(); -}; - -struct InterruptServiceRoutines { - -#ifdef ARCH_SMP - volatile uint16_t isr_count[CPU_NUMBERS]; - volatile uint8_t isr_switch_trigger_flag[CPU_NUMBERS]; -#else - volatile uint16_t isr_count ; - volatile uint8_t isr_switch_trigger_flag; -#endif - struct IrqDesc irq_table[ARCH_MAX_IRQ_NUM]; - struct IsrDone *done; -}; - -extern struct InterruptServiceRoutines isrManager ; - -uint32_t DisableLocalInterrupt(); -void EnableLocalInterrupt(unsigned long level); - -#define DISABLE_INTERRUPT DisableLocalInterrupt -#define ENABLE_INTERRUPT EnableLocalInterrupt - -void SysInitIsrManager(); -void InitHwinterrupt(void); - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.c deleted file mode 100644 index b74c0ce69..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.c +++ /dev/null @@ -1,300 +0,0 @@ -/* -* Copyright (c) 2020 AIIT XUOS Lab -* XiUOS is licensed under Mulan PSL v2. -* You can use this software according to the terms and conditions of the Mulan PSL v2. -* You may obtain a copy of Mulan PSL v2 at: -* http://license.coscl.org.cn/MulanPSL2 -* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -* See the Mulan PSL v2 for more details. -*/ - -/** -* @file: l1cache.c -* @brief: the general management of L1 cache -* @version: 3.0 -* @author: AIIT XUOS Lab -* @date: 2023/4/27 -* -*/ - -#include "l1cache.h" -#include "cp15_cacheops.h" -#include "barriers.h" - -void InvalidateL1Dcache(uintptr_t start, uintptr_t end) -{ - size_t length=end-start; - void* addr=start; - - uint32_t va; - uint32_t csidr = 0, line_size = 0; - - // get the cache line size - _ARM_MRC(15, 1, csidr, 0, 0, 0); - line_size = 1 << ((csidr & 0x7) + 4); - - // align the address with line - const void * end_addr = (const void *)((uint32_t)addr + length); - - do - { - // Clean data cache line to PoC (Point of Coherence) by va. - va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK - _ARM_MCR(15, 0, va, 7, 6, 1); - // increment addres to next line and decrement lenght - addr = (const void *) ((uint32_t)addr + line_size); - } while (addr < end_addr); - - // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete - _ARM_DSB(); -} - -void InvalidateL1DcacheAll(void) -{ - uint32_t csid; // Cache Size ID - uint32_t wayset; // wayset parameter - int num_sets; // number of sets - int num_ways; // number of ways - - _ARM_MRC(15, 1, csid, 0, 0, 0); // Read Cache Size ID - - // Fill number of sets and number of ways from csid register This walues are decremented by 1 - num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT) - - // Invalidation all lines (all Sets in all ways) - while (num_ways >= 0) - { - num_sets = (csid >> 0x0D) & 0x7FFFu; //((csid & csid_NUMSETS_MASK) >> csid_NUMSETS_SHIFT) - while (num_sets >= 0 ) - { - wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_sets << 3SETWAY_WAY_SHIFT) - // invalidate line if we know set and way - _ARM_MCR(15, 0, wayset, 7, 6, 2); - num_sets--; - } - num_ways--; - } - - // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete - _ARM_DSB(); -} - - -void CleanL1Dcache(uintptr_t start, uintptr_t end) -{ - void* addr=start; - size_t length=end-start; - uint32_t va; - uint32_t csidr = 0, line_size = 0; - const void * end_addr = (const void *)((uint32_t)addr + length); - - // get the cache line size - _ARM_MRC(15, 1, csidr, 0, 0, 0); - line_size = 1 << ((csidr & 0x7) + 4); - - do - { - // Clean data cache line to PoC (Point of Coherence) by va. - va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK - _ARM_MCR(15, 0, va, 7, 10, 1); - - // increment addres to next line and decrement lenght - addr = (const void *) ((uint32_t)addr + line_size); - } while (addr < end_addr); - - // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete - _ARM_DSB(); -} - -void CleanL1DcacheAll(void) -{ - uint32_t csid; // Cache Size ID - uint32_t wayset; // wayset parameter - int num_sets; // number of sets - int num_ways; // number of ways - - _ARM_MRC(15, 1, csid, 0, 0, 0); // Read Cache Size ID - - // Fill number of sets and number of ways from csid register This walues are decremented by 1 - num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT`) - while (num_ways >= 0) - { - num_sets = (csid >> 0x0D) & 0x7FFFu; //((csid & csid_NUMSETS_MASK) >> csid_NUMSETS_SHIFT ) - while (num_sets >= 0 ) - { - wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_ways << 3SETWAY_WAY_SHIFT) - // FLUSH (clean) line if we know set and way - _ARM_MCR(15, 0, wayset, 7, 10, 2); - num_sets--; - } - num_ways--; - } - - // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete - _ARM_DSB(); -} - -void FlushL1Dcache(uintptr_t start, uintptr_t end) -{ - void* addr=start; - size_t length=end-start; - uint32_t va; - uint32_t csidr = 0, line_size = 0; - const void * end_addr = (const void *)((uint32_t)end); - - // get the cache line size - _ARM_MRC(15, 1, csidr, 0, 0, 0); - line_size = 1 << ((csidr & 0x7) + 4); - - do - { - // Clean data cache line to PoC (Point of Coherence) by va. - va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK - _ARM_MCR(15, 0, va, 7, 14, 1); - - // increment addres to next line and decrement lenght - addr = (const void *) ((uint32_t)addr + line_size); - } while (addr < end_addr); - - // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete - _ARM_DSB(); -} - -void FlushL1DcacheAll(void) -{ - uint32_t csid; // Cache Size ID - uint32_t wayset; // wayset parameter - int num_sets; // number of sets - int num_ways; // number of ways - - _ARM_MRC(15, 1, csid, 0, 0, 0); // Read Cache Size ID - - // Fill number of sets and number of ways from csid register This walues are decremented by 1 - num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT`) - while (num_ways >= 0) - { - num_sets = (csid >> 0x0D) & 0x7FFFu; //((csid & csid_NUMSETS_MASK) >> csid_NUMSETS_SHIFT ) - while (num_sets >= 0 ) - { - wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_ways << 3SETWAY_WAY_SHIFT) - // FLUSH (clean) line if we know set and way - _ARM_MCR(15, 0, wayset, 7, 14, 2); - num_sets--; - } - num_ways--; - } - - // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete - _ARM_DSB(); -} - -void InvalidateL1IcacheAll() -{ - uint32_t SBZ = 0x0u; - - _ARM_MCR(15, 0, SBZ, 7, 5, 0); - - // synchronize context on this processor - _ARM_ISB(); -} - -void InvalidateL1Icache(uintptr_t start, uintptr_t end) -{ - void* addr=start; - uint32_t va; - uint32_t csidr = 0, line_size = 0; - const void * end_addr = (const void *)((uint32_t)end); - - // get the cache line size - _ARM_MRC(15, 1, csidr, 0, 0, 0); - line_size = 1 << ((csidr & 0x7) + 4); - - do - { - // Clean data cache line to PoC (Point of Coherence) by va. - va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK - _ARM_MCR(15, 0, va, 7, 5, 1); - // increment addres to next line and decrement lenght - addr = (const void *) ((uint32_t)addr + line_size); - } while (addr < end_addr); - - // synchronize context on this processor - _ARM_ISB(); -} - -void EnableL1Icache(void) -{ - uint32_t sctlr ;// System Control Register - - // read sctlr - _ARM_MRC(15, 0, sctlr, 1, 0, 0); - - // ignore the operation if I is enabled already - if(!(sctlr & BM_SCTLR_I)) - { - // set I bit (instruction caching enable) - sctlr |= BM_SCTLR_I; - - // write modified sctlr - _ARM_MCR(15, 0, sctlr, 1, 0, 0); - - // synchronize context on this processor - _ARM_ISB(); - } -} - -void DisableL1Icache() -{ - uint32_t sctlr ;// System Control Register - - // read sctlr - _ARM_MRC(15, 0, sctlr, 1, 0, 0); - - // Clear I bit (instruction caching enable) - sctlr &= ~BM_SCTLR_I; - - // write modified sctlr - _ARM_MCR(15, 0, sctlr, 1, 0, 0); - - // synchronize context on this processor - _ARM_ISB(); -} - -void EnableL1Dcache() -{ - uint32_t sctlr; // System Control Register - - // read sctlr - _ARM_MRC(15, 0, sctlr, 1, 0, 0); - - if (!(sctlr & BM_SCTLR_C)) - { - // set C bit (data caching enable) - sctlr |= BM_SCTLR_C; - - // write modified sctlr - _ARM_MCR(15, 0, sctlr, 1, 0, 0); - - // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete - _ARM_DSB(); - } -} - -void DisableL1Dcache() -{ - uint32_t sctlr; // System Control Register - - // read sctlr - _ARM_MRC(15, 0, sctlr, 1, 0, 0); - - // set C bit (data caching enable) - sctlr &= ~BM_SCTLR_C; - - // write modified sctlr - _ARM_MCR(15, 0, sctlr, 1, 0, 0); - - // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete - _ARM_DSB(); -} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.h deleted file mode 100644 index 7a507457a..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l1cache.h +++ /dev/null @@ -1,131 +0,0 @@ -/* -* Copyright (c) 2020 AIIT XUOS Lab -* XiUOS is licensed under Mulan PSL v2. -* You can use this software according to the terms and conditions of the Mulan PSL v2. -* You may obtain a copy of Mulan PSL v2 at: -* http://license.coscl.org.cn/MulanPSL2 -* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -* See the Mulan PSL v2 for more details. -*/ - -/** -* @file: l1cache.h -* @brief: the general management of L1 cache -* @version: 3.0 -* @author: AIIT XUOS Lab -* @date: 2023/4/27 -* -*/ - -#include -#include -#include "cortex_a9.h" - -/* Terms: - * 1) Point of coherency (PoC) - * The PoC is the point at which all agents that can access memory are - * guaranteed to see the same copy of a memory location - * 2) Point of unification (PoU) - * The PoU is the point by which the instruction and data caches and the - * translation table walks of the processor are guaranteed to see the same - * copy of a memory location. - * - * L1 Cache Operations: - * - * CP15 Register: ICIALLUIS - * Description: Invalidate entire instruction cache Inner Shareable. - * Register Format: Should be zero (SBZ) - * Instruction: MCR p15, 0, , c7, c1, 0 - * CP15 Register: BPIALLIS - * Description: Invalidate entire branch predictor array Inner - * Shareable. - * Register Format: Should be zero (SBZ) - * Instruction: MCR p15, 0, , c7, c1, 6 - * CP15 Register: ICIALLU - * Description: Invalidate all instruction caches to PoU. Also flushes - * branch target cache. - * Register Format: Should be zero (SBZ) - * Instruction: MCR p15, 0, , c7, c5, 0 - * CP15 Register: ICIMVAU - * Description: Invalidate instruction cache by VA to PoU. - * Register Format: VA - * Instruction: MCR p15, 0, , c7, c5, 1 - * CP15 Register: CP15ISB - * Description: Instruction Synchronization Barrier operation - * NOTE: Deprecated and no longer documented - * Instruction: MCR p15, 0, , c7, c5, 4 - * CP15 Register: BPIALL - * Description: Invalidate entire branch predictor array. - * Register Format: Should be zero (SBZ) - * Instruction: MCR p15, 0, , c7, c5, 6 - * CP15 Register: BPIMVA - * Description: Invalidate VA from branch predictor array. - * Register Format: Should be zero (SBZ) - * Instruction: MCR p15, 0, , c7, c5, 7 - * CP15 Register: DCIMVAC - * Description: Invalidate data cache line by VA to PoC. - * Register Format: VA - * Instruction: MCR p15, 0, , c7, c6, 1 - * CP15 Register: DCISW - * Description: Invalidate data cache line by Set/Way. - * Register Format: Set/Way - * Instruction: MCR p15, 0, , c7, c6, 2 - * CP15 Register: DCCMVAC - * Description: Clean data cache line to PoC by VA. - * Register Format: VA - * Instruction: MCR p15, 0, , c7, c10, 1 - * CP15 Register: DCCSW - * Description: Clean data cache line by Set/Way. - * Register Format: Set/Way - * Instruction: MCR p15, 0, , c7, c10, 2 - * CP15 Register: CP15DSB - * Description: Data Synchronization Barrier operation - * NOTE: Deprecated and no longer documented - * Instruction: MCR p15, 0, , c7, c10, 4 - * CP15 Register: CP15DMB - * Description: Data Memory Barrier operation - * NOTE: Deprecated and no longer documented - * Instruction: MCR p15, 0, , c7, c10, 5 - * CP15 Register: DCCMVAU - * Description: Clean data or unified cache line by VA to PoU. - * Register Format: VA - * Instruction: MCR p15, 0, , c7, c11, 1 - * CP15 Register: DCCIMVAC - * Description: Clean and invalidate data cache line by VA to PoC. - * Register Format: VA - * Instruction: MCR p15, 0, , c7, c14, 1 - * CP15 Register: DCCISW - * Description: Clean and invalidate data cache line by Set/Way. - * Register Format: Set/Way - * Instruction: MCR p15, 0, , c7, c14, 2 - */ - -#define BM_SCTLR_I (1 << 12) //!< Instruction cache enable -#define BM_SCTLR_C (1 << 2) //!< Data cache enable - -void InvalidateL1Dcache(uintptr_t start, uintptr_t end); - -void InvalidateL1DcacheAll(void); - - -void CleanL1Dcache(uintptr_t start, uintptr_t end); - -void CleanL1DcacheAll(void); - -void FlushL1Dcache(uintptr_t start, uintptr_t end); - -void FlushL1DcacheAll(void); - - -void InvalidateL1IcacheAll(void); - -void InvalidateL1Icache(uintptr_t start, uintptr_t end); - -void EnableL1Icache(void); -void DisableL1Icache(); - -void EnableL1Dcache(); - -void DisableL1Dcache(); \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc.h deleted file mode 100644 index 18118e85d..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc.h +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright (c) 2022 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ - -/** - * @file l2cc.h - * @brief the general management of L2 cache - * @version 3.0 - * @author AIIT XUOS Lab - * @date 2023.8.10 - */ - - - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#define CONFIG_ARCH_L2CACHE - -#ifdef CONFIG_ARCH_L2CACHE - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_l2ccinitialize - * - * Description: - * One time configuration of the L2 cache. The L2 cache will be enabled - * upon return. - * - * Input Parameters: - * None. The L2 cache configuration is controlled by configuration - * settings. - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if 0 /* Prototyped in arm_internal.h */ -void arm_l2ccinitialize(void); -#endif - -/**************************************************************************** - * Name: l2cc_enable - * - * Description: - * Re-enable the L2CC-P310 L2 cache by setting the enable bit in the - * Control Register (CR) - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void EnableL2Cache(void); - -/**************************************************************************** - * Name: l2cc_disable - * - * Description: - * Disable the L2 cache - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void DisableL2Cache(void); - -/**************************************************************************** - * Name: l2cc_sync - * - * Description: - * Drain the L2 cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void SyncL2Cache(void); - -/**************************************************************************** - * Name: l2cc_invalidate_all - * - * Description: - * Invalidate the entire L2 cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void InvalidateL2CacheAll(void); - -/**************************************************************************** - * Name: l2cc_invalidate - * - * Description: - * Invalidate a range of addresses in the L2 cache - * - * Input Parameters: - * startaddr - The first address to be invalidated - * endaddr - The last address to be invalidated - * - * Returned Value: - * None - * - ****************************************************************************/ - -void InvalidateL2Cache(uintptr_t startaddr, uintptr_t endaddr); - -/**************************************************************************** - * Name: l2cc_clean_all - * - * Description: - * Clean the entire L2 cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void CleanL2CacheAll(void); - -/**************************************************************************** - * Name: l2cc_clean - * - * Description: - * Clean a range of address within the L2 cache. - * - * Input Parameters: - * startaddr - The first address to be cleaned - * endaddr - The last address to be cleaned - * - * Returned Value: - * None - * - ****************************************************************************/ - -void CleanL2Cache(uintptr_t startaddr, uintptr_t endaddr); - -/**************************************************************************** - * Name: l2cc_flush_all - * - * Description: - * Flush the entire L2 cache. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void FlushL2CacheAll(void); - -/**************************************************************************** - * Name: l2cc_flush - * - * Description: - * Flush a range of address within the L2 cache. - * - * Input Parameters: - * startaddr - The first address to be flushed - * endaddr - The last address to be flushed - * - * Returned Value: - * None - * - ****************************************************************************/ - -void FlushL2Cache(uint32_t startaddr, uint32_t endaddr); - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#else /* CONFIG_ARCH_L2CACHE */ - /* Provide simple definitions to concentrate the inline conditional - * compilation in one place. - */ - -# define EnableL2Cache() -# define DisableL2Cache() -# define SyncL2Cache() -# define InvalidateL2CacheAll() -# define InvalidateL2Cache(s,e) -# define CleanL2CacheAll() -# define CleanL2Cache(s,e) -# define FlushL2CacheAll() -# define FlushL2Cache(s,e) - -#endif /* CONFIG_ARCH_L2CACHE */ - diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.c deleted file mode 100644 index 981657b57..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.c +++ /dev/null @@ -1,866 +0,0 @@ -/* - * Copyright (c) 2022 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ - -/** - * @file l2cc_pl310.c - * @brief the general management of L2 cache - * @version 3.0 - * @author AIIT XUOS Lab - * @date 2023.8.10 - */ - - - -#include -#include -#include - - -#include "l2cc.h" -#include "l2cc_pl310.h" - - -#define CONFIG_ARMV7A_ASSOCIATIVITY_8WAY -#define CONFIG_ARMV7A_WAYSIZE_16KB - -#define getreg8(a) (*(volatile uint8_t *)(a)) -#define putreg8(v,a) (*(volatile uint8_t *)(a) = (v)) -#define getreg16(a) (*(volatile uint16_t *)(a)) -#define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) -#define getreg32(a) (*(volatile uint32_t *)(a)) -#define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) - -#ifdef CONFIG_HAVE_FILENAME -# define PANIC() _assert(__FILE__, __LINE__) -#else -# define PANIC() _assert("unknown", 0) -#endif - -#define ASSERT(f) do { if (!(f)) PANIC(); } while (0) -#define VERIFY(f) do { if ((f) < 0) PANIC(); } while (0) - -#ifdef CONFIG_DEBUG_ASSERTIONS -# define DEBUGPANIC() PANIC() -# define DEBUGASSERT(f) ASSERT(f) -# define DEBUGVERIFY(f) VERIFY(f) -#else -# define DEBUGPANIC() -# define DEBUGASSERT(f) ((void)(1 || (f))) -# define DEBUGVERIFY(f) ((void)(f)) -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Number of ways depends on ARM configuration */ - -#if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY) -# define PL310_NWAYS 8 -# define PL310_WAY_MASK 0x000000ff -#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY) -# define PL310_NWAYS 16 -# define PL310_WAY_MASK 0x0000ffff -#else -# error "Number of ways not selected" -#endif - -/* The size of one depends on ARM configuration */ - -#if defined(CONFIG_ARMV7A_WAYSIZE_16KB) -# define PL310_WAYSIZE (16 * 1024) -#elif defined(CONFIG_ARMV7A_WAYSIZE_32KB) -# define PL310_WAYSIZE (32 * 1024) -#elif defined(CONFIG_ARMV7A_WAYSIZE_64KB) -# define PL310_WAYSIZE (64 * 1024) -#elif defined(CONFIG_ARMV7A_WAYSIZE_128KB) -# define PL310_WAYSIZE (128 * 1024) -#elif defined(CONFIG_ARMV7A_WAYSIZE_256KB) -# define PL310_WAYSIZE (256 * 1024) -#elif defined(CONFIG_ARMV7A_WAYSIZE_512KB) -# define PL310_WAYSIZE (512 * 1024) -#else -# error "Way size not selected" -#endif - -/* The size of the cache is then the product of the number of ways times - * the size of each way. - */ - -#define PL310_CACHE_SIZE (PL310_NWAYS * PL310_WAYSIZE) - -/* Use for aligning addresses to a cache line boundary */ - -#define PL310_CACHE_LINE_MASK (PL310_CACHE_LINE_SIZE - 1) - -/* Configurable options - * - * REVISIT: Currently there are not configuration options. All values - * are just set to the default. - */ - -/* Bit 0: Full line zero enable - * - * Default: 0=Full line of write zero behavior disabled - */ - -#define L2CC_ACR_FLZE_CONFIG (0) /* 0=Full line of write zero behavior disabled */ - -/* Bit 10: High Priority for SO and Dev Reads Enable - * - * Default: 0=Strongly Ordered and Device reads have lower priority than - * cacheable accesses - */ - -#define L2CC_ACR_HPSO_CONFIG (0) /* 0=Have lower priority than cache */ - -/* Bit 11: Store Buffer Device Limitation Enable - * - * Default: 0=Store buffer device limitation disabled - */ - -#define L2CC_ACR_SBDLE_CONFIG (0) /* 0=Store buffer device limitation disabled */ - -/* Bit 12: Exclusive Cache Configuration - * - * Default: 0=Disabled - */ - -#define L2CC_ACR_EXCC_CONFIG (0) /* 0=Disabled */ - -/* Bit 13: Shared Attribute Invalidate Enable - * - * Default: 0=Shared invalidate behavior disabled - */ - -#define L2CC_ACR_SAIE_CONFIG (0) /* 0=Shared invalidate behavior disabled */ - -/* Bit 20: Event Monitor Bus Enable - * - * Default: 0=Disabled - */ - -#define L2CC_ACR_EMBEN_CONFIG (0) /* 0=Disabled */ - -/* Bit 21: Parity Enable - * - * Default: 0=Disabled - */ - -#define L2CC_ACR_PEN_CONFIG (0) /* 0=Disabled */ - -/* Bit 22: Shared Attribute Override Enable - * - * Default: 0=Treats shared accesses as specified in the TRM - */ - -#define L2CC_ACR_SAOEN_CONFIG (0) /* 0=As specified in the TRM */ - -/* Bits 23-24: Force Write Allocate - * - * Default: 0=Use AWCACHE attributes for WA - */ - -#define L2CC_ACR_FWA_CONFIG L2CC_ACR_FWA_AWCACHE /* Use AWCACHE attributes for WA */ - -/* Bit 25: Cache Replacement Policy - * - * Default: 1=Round robin replacement policy - */ - -#define L2CC_ACR_CRPOL_CONFIG L2CC_ACR_CRPOL /* 1=Round robin replacement policy */ - -/* Bit 26: Non-Secure Lockdown Enable - * - * Default: 0=Lockdown registers cannot be modified using non-secure accesses - */ - -#define L2CC_ACR_NSLEN_CONFIG (0) /* 0=Secure access only */ - -/* Bit 27: Non-Secure Interrupt Access Control - * - * Default: 0=Interrupt Clear and Mask can only be modified or read with - * secure accesses - */ - -#define L2CC_ACR_NSIAC_CONFIG (0) /* 0=Secure access only */ - -/* Bit 28: Data Prefetch Enable - * - * Default: 0=Data prefetching disabled - */ - -#define L2CC_ACR_DPEN_CONFIG (0) /* 0=Data prefetching disabled */ - -/* Bit 29: Instruction Prefetch Enable - * - * Default: 0=Instruction prefetching disabled - */ - -#define L2CC_ACR_IPEN_CONFIG (0) /* 0=Instruction prefetching disabled */ - -/* Bit 30: Early BRESP enable - * - * Default: 0=Early BRESP disabled - */ - -#define L2CC_ACR_EBRESP_CONFIG (0) /* 0=Early BRESP disabled */ - -#define L2CC_ACR_CONFIG \ - (L2CC_ACR_FLZE_CONFIG | L2CC_ACR_HPSO_CONFIG | L2CC_ACR_SBDLE_CONFIG | \ - L2CC_ACR_EXCC_CONFIG | L2CC_ACR_SAIE_CONFIG | L2CC_ACR_EMBEN_CONFIG | \ - L2CC_ACR_PEN_CONFIG | L2CC_ACR_SAOEN_CONFIG | L2CC_ACR_FWA_CONFIG | \ - L2CC_ACR_CRPOL_CONFIG | L2CC_ACR_NSLEN_CONFIG | L2CC_ACR_NSIAC_CONFIG | \ - L2CC_ACR_DPEN_CONFIG | L2CC_ACR_IPEN_CONFIG | L2CC_ACR_EBRESP_CONFIG) - -#define L2CC_ACR_ALLCONFIGS (0x7f303c01) -#define L2CC_ACR_CONFIGMASK (L2CC_ACR_SBZ | L2CC_ACR_ALLCONFIGS) - -/* Filter end address */ - -#define CONFIG_PL310_FLEND (CONFIG_PL310_FLSTRT + CONFIG_PL310_FLSIZE) - -/* Block size. Used to break up long operations so that interrupts are not - * disabled for a long time. - */ - -#define PL310_GULP_SIZE 4096 - -/* Misc commoly defined and re-defined things */ - -#ifndef MIN -# define MIN(a,b) (((a) < (b)) ? (a) : (b)) -#endif - -#ifndef MAX -# define MAX(a,b) (((a) > (b)) ? (a) : (b)) -#endif - -#ifndef OK -# define OK 0 -#endif - -/* Data synchronization barrier */ - -#define dsb(a) __asm__ __volatile__ ("dsb " #a : : : "memory") - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: pl310_flush_all - * - * Description: - * Flush all ways using the Clean Invalidate Way Register (CIWR). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void pl310_flush_all(void) -{ - /* Flush all ways by writing the set of ways to be cleaned to the Clean - * Invalidate Way Register (CIWR). - */ - - putreg32(PL310_WAY_MASK, L2CC_CIWR); - - /* Wait for cache operation by way to complete */ - - while ((getreg32(L2CC_CIWR) & PL310_WAY_MASK) != 0); - - /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and - * EB, are empty. - */ - - putreg32(0, L2CC_CSR); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_l2ccinitialize - * - * Description: - * One time configuration of the L2 cache. The L2 cache will be enabled - * upon return. - * - * Input Parameters: - * None. The L2 cache configuration is controlled by configuration - * settings. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void arm_l2ccinitialize(void) -{ - uint32_t regval; - int i; - - /* Make sure that this is a PL310 cache, version r3p2. - * - * REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which - * is r3p2, but the chip that I have actually* reports 0x410000C9 which - * is some later revision. - */ - - /* DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) == - * L2CC_IDR_REV_R3P2); - */ - - /* Make sure that actual cache configuration agrees with the configured - * cache configuration. - */ - -#if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 0); -#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == L2CC_ACR_ASS); -#else -# error No associativity selected -#endif - -#if defined(CONFIG_ARMV7A_WAYSIZE_16KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == - L2CC_ACR_WAYSIZE_16KB); -#elif defined(CONFIG_ARMV7A_WAYSIZE_32KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == - L2CC_ACR_WAYSIZE_32KB); -#elif defined(CONFIG_ARMV7A_WAYSIZE_64KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == - L2CC_ACR_WAYSIZE_64KB); -#elif defined(CONFIG_ARMV7A_WAYSIZE_128KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == - L2CC_ACR_WAYSIZE_128KB); -#elif defined(CONFIG_ARMV7A_WAYSIZE_256KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == - L2CC_ACR_WAYSIZE_256KB); -#elif defined(CONFIG_ARMV7A_WAYSIZE_512KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == - L2CC_ACR_WAYSIZE_512KB); -#else -# error No way size selected -#endif - - /* L2 configuration can only be changed if the cache is disabled, - * - * NOTE: This register access will fail if we are not in secure more. - */ - - if ((getreg32(L2CC_CR) & L2CC_CR_L2CEN) == 0) - { -#if defined(CONFIG_PL310_TRCR_TSETLAT) && defined(CONFIG_PL310_TRCR_TRDLAT) && \ - defined(CONFIG_PL310_TRCR_TWRLAT) - /* Configure Tag RAM control */ - - regval = ((CONFIG_PL310_TRCR_TSETLAT - 1) << L2CC_TRCR_TSETLAT_SHIFT) - ((CONFIG_PL310_TRCR_TRDLAT - 1) << L2CC_TRCR_TRDLAT_SHIFT) | - ((CONFIG_PL310_TRCR_TWRLAT - 1) << L2CC_TRCR_TWRLAT_SHIFT); - putreg32(regval, L2CC_TRCR); -#endif - -#if defined(CONFIG_PL310_DRCR_DSETLAT) && defined(CONFIG_PL310_DRCR_DRDLAT) && \ - defined(CONFIG_PL310_DRCR_DWRLAT) - /* Configure Data RAM control */ - - regval = ((CONFIG_PL310_DRCR_DSETLAT - 1) << L2CC_DRCR_DSETLAT_SHIFT) | - ((CONFIG_PL310_DRCR_DRDLAT - 1) << L2CC_DRCR_DRDLAT_SHIFT) | - ((CONFIG_PL310_DRCR_DWRLAT - 1) << L2CC_DRCR_DWRLAT_SHIFT); - putreg32(regval, L2CC_DRCR); -#endif - -#ifdef PL310_ADDRESS_FILTERING -#if defined(CONFIG_PL310_FLSTRT) && defined(CONFIG_PL310_FLSIZE) - /* Configure the address filter */ - - regval = (CONFIG_PL310_FLEND + ~L2CC_FLEND_MASK) & L2CC_FLEND_MASK; - putreg32(regval, L2CC_FLEND); - - regval = (CONFIG_PL310_FLSTRT & L2CC_FLSTRT_MASK) | L2CC_FLSTRT_ENABLE; - putreg32(regval | L2X0_ADDR_FILTER_EN, L2CC_FLSTRT); -#endif -#endif - - /* Make sure that the memory is not locked down */ - - for (i = 0; i < PL310_NLOCKREGS; i++) - { - putreg32(0, L2CC_DLKR(i)); - putreg32(0, L2CC_ILKR(i)); - } - - /* Configure the cache properties */ - - regval = getreg32(L2CC_ACR); - regval &= ~L2CC_ACR_CONFIGMASK; - regval |= L2CC_ACR_CONFIG; - putreg32(regval, L2CC_ACR); - - /* Invalidate and enable the cache */ - - InvalidateL2CacheAll(); - putreg32(L2CC_CR_L2CEN, L2CC_CR); - } - - sinfo("(%d ways) * (%d bytes/way) = %d bytes\n", - PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE); -} - -/**************************************************************************** - * Name: l2cc_enable - * - * Description: - * Re-enable the L2CC-P310 L2 cache by setting the enable bit in the - * Control Register (CR) - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void EnableL2Cache(void) -{ - /* Invalidate and enable the cache (must be disabled to do this!) */ - InvalidateL2CacheAll(); - putreg32(L2CC_CR_L2CEN, L2CC_CR); - -} - -/**************************************************************************** - * Name: l2cc_disable - * - * Description: - * Disable the L2CC-P310 L2 cache by clearing the Control Register (CR) - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void DisableL2Cache(void) -{ - - pl310_flush_all(); - - /* Disable the L2CC-P310 L2 cache by clearing the Control Register (CR) */ - - putreg32(0, L2CC_CR); - dsb(); - -} - -/**************************************************************************** - * Name: l2cc_sync - * - * Description: - * Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and - * EB, are empty. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void SyncL2Cache(void) -{ - - putreg32(0, L2CC_CSR); - -} - -/**************************************************************************** - * Name: l2cc_invalidate_all - * - * Description: - * Invalidate all ways using the Invalidate Way Register (IWR). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void InvalidateL2CacheAll(void) -{ - - uint32_t regval; - - /* Invalidate all ways */ - - - /* Disable the L2 cache while we invalidate it */ - - regval = getreg32(L2CC_CR); - DisableL2Cache(); - - /* Invalidate all ways by writing the bit mask of ways to be invalidated - * the Invalidate Way Register (IWR). - */ - - putreg32(PL310_WAY_MASK, L2CC_IWR); - - /* Wait for cache operation by way to complete */ - - while ((getreg32(L2CC_IWR) & PL310_WAY_MASK) != 0); - - /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and - * EB, are empty. - */ - - putreg32(0, L2CC_CSR); - - /* Then re-enable the L2 cache if it was enabled before */ - - putreg32(regval, L2CC_CR); - -} - -/**************************************************************************** - * Name: l2cc_invalidate - * - * Description: - * Invalidate a range of addresses by writing to the Invalidate Physical - * Address Line Register (IPALR) repeatedly. - * - * Input Parameters: - * startaddr - The first address to be invalidated - * endaddr - The last address to be invalidated - * - * Returned Value: - * None - * - ****************************************************************************/ - -void InvalidateL2Cache(uintptr_t startaddr, uintptr_t endaddr) -{ - uintptr_t invalsize; - uintptr_t gulpend; - - - /* Check if the start address is aligned with a cacheline */ - - - if ((startaddr & PL310_CACHE_LINE_MASK) != 0) - { - /* No.. align down and flush the cache line by writing the address to - * the Clean Invalidate Physical Address Line Register (CIPALR). - */ - - startaddr &= ~PL310_CACHE_LINE_MASK; - putreg32(startaddr, L2CC_CIPALR); - - /* Then start invalidating at the next cache line */ - - startaddr += PL310_CACHE_LINE_SIZE; - } - - /* Check if the end address is aligned with a cache line */ - - if ((endaddr & PL310_CACHE_LINE_MASK) != 0) - { - /* No.. align down and flush cache line by writing the address to - * the Clean Invalidate Physical Address Line Register (CIPALR). - */ - - endaddr &= ~PL310_CACHE_LINE_MASK; - putreg32(endaddr, L2CC_CIPALR); - } - - - - /* Loop, invalidated the address range by cache line. Interrupts are re- - * enabled momentarily every PL310_GULP_SIZE bytes. - */ - - while (startaddr < endaddr) - { - /* Get the size of the next gulp of cache lines to invalidate. We do - * this in small chunks so that we do not have to keep interrupts - * disabled throughout the whole flush. - */ - - invalsize = endaddr - startaddr; - gulpend = startaddr + MIN(invalsize, PL310_GULP_SIZE); - - /* Disable interrupts and invalidate the gulp */ - - - while (startaddr < gulpend) - { - /* Invalidate the cache line by writing the address to the - * Invalidate Physical Address Line Register (IPALR). - */ - - putreg32(startaddr, L2CC_IPALR); - - /* Start of the next cache line */ - - startaddr += PL310_CACHE_LINE_SIZE; - } - - /* Enable interrupts momentarily */ - - - } - - /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and - * EB, are empty. - */ - - - putreg32(0, L2CC_CSR); - -} - -/**************************************************************************** - * Name: l2cc_clean_all - * - * Description: - * Clean all ways by using the Clean Ways Register (CWR). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void CleanL2CacheAll(void) -{ - - - - putreg32(PL310_WAY_MASK, L2CC_CWR); - - /* Wait for cache operation by way to complete */ - - while ((getreg32(L2CC_CWR) & PL310_WAY_MASK) != 0); - - /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and - * EB, are empty. - */ - - putreg32(0, L2CC_CSR); - -} - -/**************************************************************************** - * Name: l2cc_clean - * - * Description: - * Clean the cache line over a range of addresses uing the Clean Physical - * Address Line Register (CPALR) repeatedly. - * - * Input Parameters: - * startaddr - The first address to be cleaned - * endaddr - The last address to be cleaned - * - * Returned Value: - * None - * - ****************************************************************************/ - -void CleanL2Cache(uintptr_t startaddr, uintptr_t endaddr) -{ - uintptr_t cleansize; - uintptr_t gulpend; - - - /* If the range of addresses to clean is as large or larger the L2 cache, - * then just clean the whole thing. - */ - - cleansize = endaddr - startaddr; - if (cleansize >= PL310_CACHE_SIZE) - { - CleanL2CacheAll(); - return; - } - - /* Align the starting address to a cache line boundary */ - - startaddr &= ~PL310_CACHE_LINE_MASK; - - /* Clean the L2 cache by cache line, enabling interrupts momentarily - * every PL310_GULP_SIZE bytes. - */ - - while (startaddr < endaddr) - { - /* Get the size of the next gulp of cache lines to flush. We do - * this in small chunks so that we do not have to keep interrupts - * disabled throughout the whole flush. - */ - - cleansize = endaddr - startaddr; - gulpend = startaddr + MIN(cleansize, PL310_GULP_SIZE); - - /* Disable interrupts and clean the gulp */ - - - while (startaddr < gulpend) - { - /* Clean the cache line by writing the address to the Clean - * Physical Address Line Register (CPALR). - */ - - putreg32(startaddr, L2CC_CPALR); - - /* Start of the next cache line */ - - startaddr += PL310_CACHE_LINE_SIZE; - } - - /* Enable interrupts momentarily */ - - - } - - /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and - * EB, are empty. - */ - - - putreg32(0, L2CC_CSR); - -} - -/**************************************************************************** - * Name: l2cc_flush_all - * - * Description: - * Flush all ways using the Clean Invalidate Way Register (CIWR). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void FlushL2CacheAll(void) -{ - - - /* Flush all ways using the Clean Invalidate Way Register (CIWR). */ - - - pl310_flush_all(); - -} - -/**************************************************************************** - * Name: l2cc_flush - * - * Description: - * Flush a range of address by using the Clean Invalidate Physical Address - * Line Register (CIPALR) repeatedly. - * - * Input Parameters: - * startaddr - The first address to be flushed - * endaddr - The last address to be flushed - * - * Returned Value: - * None - * - ****************************************************************************/ - -void FlushL2Cache(uint32_t startaddr, uint32_t endaddr) -{ - uintptr_t flushsize; - uintptr_t gulpend; - - - /* If the range of addresses to flush is as large or larger the L2 cache, - * then just flush the whole thing. - */ - - flushsize = endaddr - startaddr; - if (flushsize >= PL310_CACHE_SIZE) - { - l2cc_flush_all(); - return; - } - - /* Align the starting address to a cache line boundary */ - - startaddr &= ~PL310_CACHE_LINE_MASK; - - /* Flush the L2 cache by cache line, enabling interrupts momentarily - * every PL310_GULP_SIZE bytes. - */ - - while (startaddr < endaddr) - { - /* Get the size of the next gulp of cache lines to flush. We do - * this in small chunks so that we do not have to keep interrupts - * disabled throughout the whole flush. - */ - - flushsize = endaddr - startaddr; - gulpend = startaddr + MIN(flushsize, PL310_GULP_SIZE); - - /* Disable interrupts and flush the gulp */ - - - while (startaddr < gulpend) - { - /* Flush the cache line by writing the address to the Clean - * Invalidate Physical Address Line Register (CIPALR). - */ - - putreg32(startaddr, L2CC_CIPALR); - - /* Start of the next cache line */ - - startaddr += PL310_CACHE_LINE_SIZE; - } - - /* Enable interrupts momentarily */ - - - } - - /* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and - * EB, are empty. - */ - - - putreg32(0, L2CC_CSR); - -} - - diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.h deleted file mode 100644 index e5c5c1225..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/l2cc_pl310.h +++ /dev/null @@ -1,483 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-a/l2cc_pl310.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Reference: "CoreLink� Level 2 Cache Controller L2C-310", Revision r3p2, - * Technical Reference Manual, ARM DDI 0246F (ID011711), ARM - */ - -#ifndef __ARCH_ARM_SRC_ARMV7_A_L2CC_PL310_H -#define __ARCH_ARM_SRC_ARMV7_A_L2CC_PL310_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - - - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* General Definitions ******************************************************/ - -#define PL310_CACHE_LINE_SIZE 32 - -#ifdef CONFIG_PL310_LOCKDOWN_BY_MASTER -# define PL310_NLOCKREGS 8 -#else -# define PL310_NLOCKREGS 1 -#endif - -/* L2CC Register Offsets ****************************************************/ -#define IMX_ARMMP_PSECTION 0x00a00000 /* 00a00000-00afffff 8 KB ARM MP */ -# define IMX_ARMMP_VSECTION IMX_ARMMP_PSECTION /* 8 KB ARM MP */ -#define IMX_PL310_OFFSET 0x00002000 /* 00002000-00002fff 4 KB PL310 (L2 Cache controller) */ -#define IMX_PL310_VBASE (IMX_ARMMP_VSECTION+IMX_PL310_OFFSET) -#define L2CC_VBASE IMX_PL310_VBASE - - -#define L2CC_IDR_OFFSET 0x0000 /* Cache ID Register */ -#define L2CC_TYPR_OFFSET 0x0004 /* Cache Type Register */ -#define L2CC_CR_OFFSET 0x0100 /* Control Register */ -#define L2CC_ACR_OFFSET 0x0104 /* Auxiliary Control Register */ -#define L2CC_TRCR_OFFSET 0x0108 /* Tag RAM Control Register */ -#define L2CC_DRCR_OFFSET 0x010c /* Data RAM Control Register */ - /* 0x0110-0x01fc Reserved */ -#define L2CC_ECR_OFFSET 0x0200 /* Event Counter Control Register */ -#define L2CC_ECFGR1_OFFSET 0x0204 /* Event Counter 1 Configuration Register */ -#define L2CC_ECFGR0_OFFSET 0x0208 /* Event Counter 0 Configuration Register */ -#define L2CC_EVR1_OFFSET 0x020c /* Event Counter 1 Value Register */ -#define L2CC_EVR0_OFFSET 0x0210 /* Event Counter 0 Value Register */ -#define L2CC_IMR_OFFSET 0x0214 /* Interrupt Mask Register */ -#define L2CC_MISR_OFFSET 0x0218 /* Masked Interrupt Status Register */ -#define L2CC_RISR_OFFSET 0x021c /* Raw Interrupt Status Register */ -#define L2CC_ICR_OFFSET 0x0220 /* Interrupt Clear Register */ - /* 0x0224-0x072c Reserved */ -#define L2CC_CSR_OFFSET 0x0730 /* Cache Synchronization Register */ - /* 0x0734-0x076c Reserved */ -#define L2CC_IPALR_OFFSET 0x0770 /* Invalidate Physical Address Line Register */ - /* 0x0774-0x0778 Reserved */ -#define L2CC_IWR_OFFSET 0x077c /* Invalidate Way Register */ - /* 0x0780-0x07af Reserved */ -#define L2CC_CPALR_OFFSET 0x07b0 /* Clean Physical Address Line Register */ - /* 0x07b4 Reserved */ -#define L2CC_CIR_OFFSET 0x07b8 /* Clean Index Register */ -#define L2CC_CWR_OFFSET 0x07bc /* Clean Way Register */ - /* 0x07c0-0x07ec Reserved */ -#define L2CC_CIPALR_OFFSET 0x07f0 /* Clean Invalidate Physical Address Line Register */ - /* 0x07f4 Reserved */ -#define L2CC_CIIR_OFFSET 0x07f8 /* Clean Invalidate Index Register */ -#define L2CC_CIWR_OFFSET 0x07fc /* Clean Invalidate Way Register */ - /* 0x0800-0x08fc Reserved */ - -/* Data and Instruction Lockdown registers where n=0-7. - * The registers for n > 0 are implemented if the option - * pl310_LOCKDOWN_BY_MASTER is enabled. - * Otherwise, they are unused - */ - -#define L2CC_DLKR_OFFSET(n) (0x0900 + ((n) << 3)) /* Data Lockdown Register */ -#define L2CC_ILKR_OFFSET(n) (0x0904 + ((n) << 3)) /* Instruction Lockdown Register */ - /* 0x0940-0x0f4c Reserved */ -#ifdef CONFIG_PL310_LOCKDOWN_BY_LINE -# define L2CC_LKLN_OFFSET 0x0950 /* Lock Line Enable Register */ -# define L2CC_UNLKW_OFFSET 0x0954 /* Unlock Way Register */ -#endif - /* 0x0958-0x0bfc Reserved */ -#define L2CC_FLSTRT_OFFSET 0x0c00 /* Address filter start */ -#define L2CC_FLEND_OFFSET 0x0c04 /* Address filter end */ - /* 0x0c08-0x0f3c Reserved */ -#define L2CC_DCR_OFFSET 0x0f40 /* Debug Control Register */ - /* 0x0f44-0x0f5c Reserved */ -#define L2CC_PCR_OFFSET 0x0f60 /* Prefetch Control Register */ - /* 0x0f64-0x0f7c Reserved */ -#define L2CC_POWCR_OFFSET 0x0f80 /* Power Control Register */ - -/* L2CC Register Addresses **************************************************/ - -#define L2CC_IDR (L2CC_VBASE+L2CC_IDR_OFFSET) -#define L2CC_TYPR (L2CC_VBASE+L2CC_TYPR_OFFSET) -#define L2CC_CR (L2CC_VBASE+L2CC_CR_OFFSET) -#define L2CC_ACR (L2CC_VBASE+L2CC_ACR_OFFSET) -#define L2CC_TRCR (L2CC_VBASE+L2CC_TRCR_OFFSET) -#define L2CC_DRCR (L2CC_VBASE+L2CC_DRCR_OFFSET) -#define L2CC_ECR (L2CC_VBASE+L2CC_ECR_OFFSET) -#define L2CC_ECFGR1 (L2CC_VBASE+L2CC_ECFGR1_OFFSET) -#define L2CC_ECFGR0 (L2CC_VBASE+L2CC_ECFGR0_OFFSET) -#define L2CC_EVR1 (L2CC_VBASE+L2CC_EVR1_OFFSET) -#define L2CC_EVR0 (L2CC_VBASE+L2CC_EVR0_OFFSET) -#define L2CC_IMR (L2CC_VBASE+L2CC_IMR_OFFSET) -#define L2CC_MISR (L2CC_VBASE+L2CC_MISR_OFFSET) -#define L2CC_RISR (L2CC_VBASE+L2CC_RISR_OFFSET) -#define L2CC_ICR (L2CC_VBASE+L2CC_ICR_OFFSET) -#define L2CC_CSR (L2CC_VBASE+L2CC_CSR_OFFSET) -#define L2CC_IPALR (L2CC_VBASE+L2CC_IPALR_OFFSET) -#define L2CC_IWR (L2CC_VBASE+L2CC_IWR_OFFSET) -#define L2CC_CPALR (L2CC_VBASE+L2CC_CPALR_OFFSET) -#define L2CC_CIR (L2CC_VBASE+L2CC_CIR_OFFSET) -#define L2CC_CWR (L2CC_VBASE+L2CC_CWR_OFFSET) -#define L2CC_CIPALR (L2CC_VBASE+L2CC_CIPALR_OFFSET) -#define L2CC_CIIR (L2CC_VBASE+L2CC_CIIR_OFFSET) -#define L2CC_CIWR (L2CC_VBASE+L2CC_CIWR_OFFSET) -#define L2CC_DLKR(n) (L2CC_VBASE+L2CC_DLKR_OFFSET(n)) -#define L2CC_ILKR(n) (L2CC_VBASE+L2CC_ILKR_OFFSET(n)) - -#ifdef CONFIG_PL310_LOCKDOWN_BY_LINE -# define L2CC_LKLN (L2CC_VBASE+L2CC_LKLN_OFFSET) -# define L2CC_UNLKW (L2CC_VBASE+L2CC_UNLKW_OFFSET) -#endif - -#define L2CC_FLSTRT (L2CC_VBASE+L2CC_FLSTRT_OFFSET) -#define L2CC_FLEND (L2CC_VBASE+L2CC_FLEND_OFFSET) -#define L2CC_DCR (L2CC_VBASE+L2CC_DCR_OFFSET) -#define L2CC_PCR (L2CC_VBASE+L2CC_PCR_OFFSET) -#define L2CC_POWCR (L2CC_VBASE+L2CC_POWCR_OFFSET) - -/* L2CC Register Bit Definitions ********************************************/ - -/* Cache ID Register (32-bit ID) */ - -#define L2CC_IDR_REV_MASK 0x0000003f -#define L2CC_IDR_REV_R0P0 0x00000000 -#define L2CC_IDR_REV_R1P0 0x00000002 -#define L2CC_IDR_REV_R2P0 0x00000004 -#define L2CC_IDR_REV_R3P0 0x00000005 -#define L2CC_IDR_REV_R3P1 0x00000006 -#define L2CC_IDR_REV_R3P2 0x00000008 - -/* Cache Type Register */ - -#define L2CC_TYPR_IL2ASS (1 << 6) /* Bit 6: Instruction L2 Cache Associativity */ -#define L2CC_TYPR_IL2WSIZE_SHIFT (8) /* Bits 8-10: Instruction L2 Cache Way Size */ -#define L2CC_TYPR_IL2WSIZE_MASK (7 << L2CC_TYPR_IL2WSIZE_SHIFT) -#define L2CC_TYPR_IL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_IL2WSIZE_SHIFT) -#define L2CC_TYPR_DL2ASS (1 << 18) /* Bit 18: Data L2 Cache Associativity */ -#define L2CC_TYPR_DL2WSIZE_SHIFT (20) /* Bits 20-22: Data L2 Cache Way Size */ -#define L2CC_TYPR_DL2WSIZE_MASK (7 << L2CC_TYPR_DL2WSIZE_SHIFT) -#define L2CC_TYPR_DL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_DL2WSIZE_SHIFT) - -/* Control Register */ - -#define L2CC_CR_L2CEN (1 << 0) /* Bit 0: L2 Cache Enable */ - -/* Auxiliary Control Register */ - -#define L2CC_ACR_FLZE (1 << 0) /* Bit 0: Full line zero enable */ -#define L2CC_ACR_HPSO (1 << 10) /* Bit 10: High Priority for SO and Dev Reads Enable */ -#define L2CC_ACR_SBDLE (1 << 11) /* Bit 11: Store Buffer Device Limitation Enable */ -#define L2CC_ACR_EXCC (1 << 12) /* Bit 12: Exclusive Cache Configuration */ -#define L2CC_ACR_SAIE (1 << 13) /* Bit 13: Shared Attribute Invalidate Enable */ -#define L2CC_ACR_ASS (1 << 16) /* Bit 16: Associativity */ -#define L2CC_ACR_WAYSIZE_SHIFT (17) /* Bits 17-19: Way Size */ -#define L2CC_ACR_WAYSIZE_MASK (7 << L2CC_ACR_WAYSIZE_SHIFT) -#define L2CC_ACR_WAYSIZE_16KB (1 << L2CC_ACR_WAYSIZE_SHIFT) -#define L2CC_ACR_WAYSIZE_32KB (2 << L2CC_ACR_WAYSIZE_SHIFT) -#define L2CC_ACR_WAYSIZE_64KB (3 << L2CC_ACR_WAYSIZE_SHIFT) -#define L2CC_ACR_WAYSIZE_128KB (4 << L2CC_ACR_WAYSIZE_SHIFT) -#define L2CC_ACR_WAYSIZE_256KB (5 << L2CC_ACR_WAYSIZE_SHIFT) -#define L2CC_ACR_WAYSIZE_512KB (6 << L2CC_ACR_WAYSIZE_SHIFT) -#define L2CC_ACR_EMBEN (1 << 20) /* Bit 20: Event Monitor Bus Enable */ -#define L2CC_ACR_PEN (1 << 21) /* Bit 21: Parity Enable */ -#define L2CC_ACR_SAOEN (1 << 22) /* Bit 22: Shared Attribute Override Enable */ -#define L2CC_ACR_FWA_SHIFT (23) /* Bits 23-24: Force Write Allocate */ -#define L2CC_ACR_FWA_MASK (3 << L2CC_ACR_FWA_SHIFT) -#define L2CC_ACR_FWA_AWCACHE (0 << L2CC_ACR_FWA_SHIFT) /* Use AWCACHE attributes for WA */ -#define L2CC_ACR_FWA_NOALLOC (1 << L2CC_ACR_FWA_SHIFT) /* No allocate */ -#define L2CC_ACR_FWA_OVERRIDE (2 << L2CC_ACR_FWA_SHIFT) /* Override AWCACHE attributes */ -#define L2CC_ACR_FWA_MAPPED (3 << L2CC_ACR_FWA_SHIFT) /* Internally mapped to 00 */ - -#define L2CC_ACR_CRPOL (1 << 25) /* Bit 25: Cache Replacement Policy */ -#define L2CC_ACR_NSLEN (1 << 26) /* Bit 26: Non-Secure Lockdown Enable */ -#define L2CC_ACR_NSIAC (1 << 27) /* Bit 27: Non-Secure Interrupt Access Control */ -#define L2CC_ACR_DPEN (1 << 28) /* Bit 28: Data Prefetch Enable */ -#define L2CC_ACR_IPEN (1 << 29) /* Bit 29: Instruction Prefetch Enable */ -#define L2CC_ACR_EBRESP (1 << 30) /* Bit 30: Early BRESP enable */ - -#define L2CC_ACR_SBZ (0x8000c1fe) - -/* Tag RAM Control Register */ - -#define L2CC_TRCR_TSETLAT_SHIFT (0) /* Bits 0-2: Setup Latency */ -#define L2CC_TRCR_TSETLAT_MASK (7 << L2CC_TRCR_TSETLAT_SHIFT) -#define L2CC_TRCR_TSETLAT(n) ((uint32_t)(n) << L2CC_TRCR_TSETLAT_SHIFT) -#define L2CC_TRCR_TRDLAT_SHIFT (4) /* Bits 4-6: Read Access Latency */ -#define L2CC_TRCR_TRDLAT_MASK (7 << L2CC_TRCR_TRDLAT_SHIFT) -#define L2CC_TRCR_TRDLAT(n) ((uint32_t)(n) << L2CC_TRCR_TRDLAT_SHIFT) -#define L2CC_TRCR_TWRLAT_SHIFT (8) /* Bits 8-10: Write Access Latency */ -#define L2CC_TRCR_TWRLAT_MASK (7 << L2CC_TRCR_TWRLAT_SHIFT) -#define L2CC_TRCR_TWRLAT(n) ((uint32_t)(n) << L2CC_TRCR_TWRLAT_SHIFT) - -/* Data RAM Control Register */ - -#define L2CC_DRCR_DSETLAT_SHIFT (0) /* Bits 0-2: Setup Latency */ -#define L2CC_DRCR_DSETLAT_MASK (7 << L2CC_DRCR_DSETLAT_SHIFT) -#define L2CC_DRCR_DSETLAT(n) ((uint32_t)(n) << L2CC_DRCR_DSETLAT_SHIFT) -#define L2CC_DRCR_DRDLAT_SHIFT (4) /* Bits 4-6: Read Access Latency */ -#define L2CC_DRCR_DRDLAT_MASK (7 << L2CC_DRCR_DRDLAT_SHIFT) -#define L2CC_DRCR_DRDLAT(n) ((uint32_t)(n) << L2CC_DRCR_DRDLAT_SHIFT) -#define L2CC_DRCR_DWRLAT_SHIFT (8) /* Bits 8-10: Write Access Latency */ -#define L2CC_DRCR_DWRLAT_MASK (7 << L2CC_DRCR_DWRLAT_SHIFT) -#define L2CC_DRCR_DWRLAT(n) ((uint32_t)(n) << L2CC_DRCR_DWRLAT_SHIFT) - -/* Event Counter Control Register */ - -#define L2CC_ECR_EVCEN (1 << 0) /* Bit 0: Event Counter Enable */ -#define L2CC_ECR_EVC0RST (1 << 1) /* Bit 1: Event Counter 0 Reset */ -#define L2CC_ECR_EVC1RST (1 << 2) /* Bit 2: Event Counter 1 Reset */ - -/* Event Counter 1 Configuration Register */ - -#define L2CC_ECFGR1_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */ -#define L2CC_ECFGR1_EIGEN_MASK (3 << L2CC_ECFGR1_EIGEN_SHIFT) -#define L2CC_ECFGR1_EIGEN_INTDIS (0 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables (default) */ -#define L2CC_ECFGR1_EIGEN_INTENINCR (1 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Increment condition */ -#define L2CC_ECFGR1_EIGEN_INTENOVER (2 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Overflow condition */ -#define L2CC_ECFGR1_EIGEN_INTGENDIS (3 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables Interrupt generation */ -#define L2CC_ECFGR1_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */ -#define L2CC_ECFGR1_ESRC_MASK (15 << L2CC_ECFGR1_ESRC_SHIFT) -#define L2CC_ECFGR1_ESRC_CNTDIS (0 << L2CC_ECFGR1_ESRC_SHIFT) /* Counter Disabled */ -#define L2CC_ECFGR1_ESRC_CO (1 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is CO */ -#define L2CC_ECFGR1_ESRC_DRHIT (2 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRHIT */ -#define L2CC_ECFGR1_ESRC_DRREQ (3 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRREQ */ -#define L2CC_ECFGR1_ESRC_DWHIT (4 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWHIT */ -#define L2CC_ECFGR1_ESRC_DWREQ (5 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWREQ */ -#define L2CC_ECFGR1_ESRC_DWTREQ (6 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWTREQ */ -#define L2CC_ECFGR1_ESRC_IRHIT (7 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRHIT */ -#define L2CC_ECFGR1_ESRC_IRREQ (8 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRREQ */ -#define L2CC_ECFGR1_ESRC_WA (9 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is WA */ -#define L2CC_ECFGR1_ESRC_IPFALLOC (10 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IPFALLOC */ -#define L2CC_ECFGR1_ESRC_EPFHIT (11 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFHIT */ -#define L2CC_ECFGR1_ESRC_EPFALLOC (12 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFALLOC */ -#define L2CC_ECFGR1_ESRC_SRRCVD (13 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRRCVD */ -#define L2CC_ECFGR1_ESRC_SRCONF (14 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRCONF */ -#define L2CC_ECFGR1_ESRC_EPFRCVD (15 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFRCVD */ - -/* Event Counter 0 Configuration Register */ - -#define L2CC_ECFGR0_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */ -#define L2CC_ECFGR0_EIGEN_MASK (3 << L2CC_ECFGR0_EIGEN_SHIFT) -#define L2CC_ECFGR0_EIGEN_INTDIS (0 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables (default) */ -#define L2CC_ECFGR0_EIGEN_INTENINCR (1 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Increment condition */ -#define L2CC_ECFGR0_EIGEN_INTENOVER (2 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Overflow condition */ -#define L2CC_ECFGR0_EIGEN_INTGENDIS (3 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables Interrupt generation */ -#define L2CC_ECFGR0_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */ -#define L2CC_ECFGR0_ESRC_MASK (15 << L2CC_ECFGR0_ESRC_SHIFT) -#define L2CC_ECFGR0_ESRC_CNTDIS (0 << L2CC_ECFGR0_ESRC_SHIFT) /* Counter Disabled */ -#define L2CC_ECFGR0_ESRC_CO (1 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is CO */ -#define L2CC_ECFGR0_ESRC_DRHIT (2 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRHIT */ -#define L2CC_ECFGR0_ESRC_DRREQ (3 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRREQ */ -#define L2CC_ECFGR0_ESRC_DWHIT (4 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWHIT */ -#define L2CC_ECFGR0_ESRC_DWREQ (5 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWREQ */ -#define L2CC_ECFGR0_ESRC_DWTREQ (6 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWTREQ */ -#define L2CC_ECFGR0_ESRC_IRHIT (7 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRHIT */ -#define L2CC_ECFGR0_ESRC_IRREQ (8 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRREQ */ -#define L2CC_ECFGR0_ESRC_WA (9 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is WA */ -#define L2CC_ECFGR0_ESRC_IPFALLOC (10 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IPFALLOC */ -#define L2CC_ECFGR0_ESRC_EPFHIT (11 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFHIT */ -#define L2CC_ECFGR0_ESRC_EPFALLOC (12 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFALLOC */ -#define L2CC_ECFGR0_ESRC_SRRCVD (13 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRRCVD */ -#define L2CC_ECFGR0_ESRC_SRCONF (14 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRCONF */ -#define L2CC_ECFGR0_ESRC_EPFRCVD (15 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFRCVD */ - -/* Event Counter 1 Value Register (32-bit value) */ - -/* Event Counter 0 Value Register (32-bit value) */ - -/* Interrupt Mask Register, Masked Interrupt Status Register, - * Raw Interrupt Status Register, and Interrupt Clear Register. - */ - -#define L2CC_INT_ECNTR (1 << 0) /* Bit 0: Event Counter 1/0 Overflow Increment */ -#define L2CC_INT_PARRT (1 << 1) /* Bit 1: Parity Error on L2 Tag RAM, Read */ -#define L2CC_INT_PARRD (1 << 2) /* Bit 2: Parity Error on L2 Data RAM, Read */ -#define L2CC_INT_ERRWT (1 << 3) /* Bit 3: Error on L2 Tag RAM, Write */ -#define L2CC_INT_ERRWD (1 << 4) /* Bit 4: Error on L2 Data RAM, Write */ -#define L2CC_INT_ERRRT (1 << 5) /* Bit 5: Error on L2 Tag RAM, Read */ -#define L2CC_INT_ERRRD (1 << 6) /* Bit 6: Error on L2 Data RAM, Read */ -#define L2CC_INT_SLVERR (1 << 7) /* Bit 7: SLVERR from L3 Memory */ -#define L2CC_INT_DECERR (1 << 8) /* Bit 8: DECERR from L3 Memory */ - -/* Cache Synchronization Register */ - -#define L2CC_CSR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ - -/* Invalidate Physical Address Line Register */ - -#define L2CC_IPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ -#define L2CC_IPALR_IDX_SHIFT (5) /* Bits 5-13: Index Number */ -#define L2CC_IPALR_IDX_MASK (0x1ff << L2CC_IPALR_IDX_SHIFT) -#define L2CC_IPALR_IDX(n) ((uint32_t)(n) << L2CC_IPALR_IDX_SHIFT) -#define L2CC_IPALR_TAG_SHIFT (14) /* Bits 14-31: Tag Number */ -#define L2CC_IPALR_TAG_MASK (0x3ffff << L2CC_IPALR_TAG_SHIFT) -#define L2CC_IPALR_TAG(n) ((uint32_t)(n) << L2CC_IPALR_TAG_SHIFT) - -/* Invalidate Way Register */ - -#define L2CC_IWR_WAY(n) (1 << (n)) /* Bist 0-7: Invalidate Way Number n, n=0..7 */ -#define L2CC_IWR_WAY0 (1 << 0) /* Bit 0: Invalidate Way Number 0 */ -#define L2CC_IWR_WAY1 (1 << 1) /* Bit 1: Invalidate Way Number 1 */ -#define L2CC_IWR_WAY2 (1 << 2) /* Bit 2: Invalidate Way Number 2 */ -#define L2CC_IWR_WAY3 (1 << 3) /* Bit 3: Invalidate Way Number 3 */ -#define L2CC_IWR_WAY4 (1 << 4) /* Bit 4: Invalidate Way Number 4 */ -#define L2CC_IWR_WAY5 (1 << 5) /* Bit 5: Invalidate Way Number 5 */ -#define L2CC_IWR_WAY6 (1 << 6) /* Bit 6: Invalidate Way Number 6 */ -#define L2CC_IWR_WAY7 (1 << 7) /* Bit 7: Invalidate Way Number 7 */ - -/* Clean Physical Address Line Register */ - -#define L2CC_CPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ -#define L2CC_CPALR_IDX_SHIFT (5) /* Bits 5-13: Index number */ -#define L2CC_CPALR_IDX_MASK (0x1ff << L2CC_CPALR_IDX_SHIFT) -#define L2CC_CPALR_IDX(n) ((uint32_t)(n) << L2CC_CPALR_IDX_SHIFT) -#define L2CC_CPALR_TAG_SHIFT (14) /* Bits 14-31: Tag number */ -#define L2CC_CPALR_TAG_MASK (0x3ffff << L2CC_CPALR_TAG_SHIFT) -#define L2CC_CPALR_TAG(n) ((uint32_t)(n) << L2CC_CPALR_TAG_SHIFT) - -/* Clean Index Register */ - -#define L2CC_CIR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ -#define L2CC_CIR_IDX_SHIFT (5) /* Bits 5-13: Index number */ -#define L2CC_CIR_IDX_MASK (0x1ff << L2CC_CIR_IDX_SHIFT) -#define L2CC_CIR_IDX(n) ((uint32_t)(n) << L2CC_CIR_IDX_SHIFT) -#define L2CC_CIR_WAY_SHIFT (28) /* Bits 28-30: Way number */ -#define L2CC_CIR_WAY_MASK (7 << L2CC_CIR_WAY_SHIFT) -#define L2CC_CIR_WAY(n) ((uint32_t)(n) << L2CC_CIR_WAY_SHIFT) - -/* Clean Way Register */ - -#define L2CC_CWR_WAY(n) (1 << (n)) /* Bits 0-7: Clean Way Number n, n=0..7 */ -#define L2CC_CWR_WAY0 (1 << 0) /* Bit 0: Clean Way Number 0 */ -#define L2CC_CWR_WAY1 (1 << 1) /* Bit 1: Clean Way Number 1 */ -#define L2CC_CWR_WAY2 (1 << 2) /* Bit 2: Clean Way Number 2 */ -#define L2CC_CWR_WAY3 (1 << 3) /* Bit 3: Clean Way Number 3 */ -#define L2CC_CWR_WAY4 (1 << 4) /* Bit 4: Clean Way Number 4 */ -#define L2CC_CWR_WAY5 (1 << 5) /* Bit 5: Clean Way Number 5 */ -#define L2CC_CWR_WAY6 (1 << 6) /* Bit 6: Clean Way Number 6 */ -#define L2CC_CWR_WAY7 (1 << 7) /* Bit 7: Clean Way Number 7 */ - -/* Clean Invalidate Physical Address Line Register */ - -#define L2CC_CIPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ -#define L2CC_CIPALR_IDX_SHIFT (5) /* Bits 5-13: Index Number */ -#define L2CC_CIPALR_IDX_MASK (0x1ff << L2CC_CIPALR_IDX_SHIFT) -#define L2CC_CIPALR_IDX(n) ((uint32_t)(n) << L2CC_CIPALR_IDX_SHIFT) -#define L2CC_CIPALR_TAG_SHIFT (14) /* Bits 14-31: Tag Number */ -#define L2CC_CIPALR_TAG_MASK (0x3ffff << L2CC_CIPALR_TAG_SHIFT) -#define L2CC_CIPALR_TAG(n) ((uint32_t)(n) << L2CC_CIPALR_TAG_SHIFT) - -/* Clean Invalidate Index Register */ - -#define L2CC_CIIR_C (1 << 0) /* Bit 0: Cache Synchronization Status */ -#define L2CC_CIIR_IDX_SHIFT (5) /* Bits 5-13: Index Number */ -#define L2CC_CIIR_IDX_MASK (0x1ff << L2CC_CIIR_IDX_SHIFT) -#define L2CC_CIIR_IDX(n) ((uint32_t)(n) << L2CC_CIIR_IDX_SHIFT) -#define L2CC_CIIR_WAY_SHIFT (28) /* Bits 28-30: Way Number */ -#define L2CC_CIIR_WAY_MASK (7 << L2CC_CIIR_WAY_SHIFT) -#define L2CC_CIIR_WAY(n) ((uint32_t)(n) << L2CC_CIIR_WAY_SHIFT) - -/* Clean Invalidate Way Register */ - -#define L2CC_CIWR_WAY(n) (1 << (n)) /* Bits 0-7: Clean Invalidate Way Number n, n=1..7 */ -#define L2CC_CIWR_WAY0 (1 << 0) /* Bit 0: Clean Invalidate Way Number 0 */ -#define L2CC_CIWR_WAY1 (1 << 1) /* Bit 1: Clean Invalidate Way Number 1 */ -#define L2CC_CIWR_WAY2 (1 << 2) /* Bit 2: Clean Invalidate Way Number 2 */ -#define L2CC_CIWR_WAY3 (1 << 3) /* Bit 3: Clean Invalidate Way Number 3 */ -#define L2CC_CIWR_WAY4 (1 << 4) /* Bit 4: Clean Invalidate Way Number 4 */ -#define L2CC_CIWR_WAY5 (1 << 5) /* Bit 5: Clean Invalidate Way Number 5 */ -#define L2CC_CIWR_WAY6 (1 << 6) /* Bit 6: Clean Invalidate Way Number 6 */ -#define L2CC_CIWR_WAY7 (1 << 7) /* Bit 7: Clean Invalidate Way Number 7 */ - -/* Data Lockdown Register */ - -#define L2CC_DLKR_DLK(n) (1 << (n)) /* Bits 0-7: Data Lockdown in Way Number n, n=0..7 */ -#define L2CC_DLKR_DLK0 (1 << 0) /* Bit 0: Data Lockdown in Way Number 0 */ -#define L2CC_DLKR_DLK1 (1 << 1) /* Bit 1: Data Lockdown in Way Number 1 */ -#define L2CC_DLKR_DLK2 (1 << 2) /* Bit 2: Data Lockdown in Way Number 2 */ -#define L2CC_DLKR_DLK3 (1 << 3) /* Bit 3: Data Lockdown in Way Number 3 */ -#define L2CC_DLKR_DLK4 (1 << 4) /* Bit 4: Data Lockdown in Way Number 4 */ -#define L2CC_DLKR_DLK5 (1 << 5) /* Bit 5: Data Lockdown in Way Number 5 */ -#define L2CC_DLKR_DLK6 (1 << 6) /* Bit 6: Data Lockdown in Way Number 6 */ -#define L2CC_DLKR_DLK7 (1 << 7) /* Bit 7: Data Lockdown in Way Number 7 */ - -/* Instruction Lockdown Register */ - -#define L2CC_ILKR_ILK(n) (1 << (n)) /* Bits 0-7: Instruction Lockdown in Way Number n, n=0..7 */ -#define L2CC_ILKR_ILK0 (1 << 0) /* Bit 0: Instruction Lockdown in Way Number 0 */ -#define L2CC_ILKR_ILK1 (1 << 1) /* Bit 1: Instruction Lockdown in Way Number 1 */ -#define L2CC_ILKR_ILK2 (1 << 2) /* Bit 2: Instruction Lockdown in Way Number 2 */ -#define L2CC_ILKR_ILK3 (1 << 3) /* Bit 3: Instruction Lockdown in Way Number 3 */ -#define L2CC_ILKR_ILK4 (1 << 4) /* Bit 4: Instruction Lockdown in Way Number 4 */ -#define L2CC_ILKR_ILK5 (1 << 5) /* Bit 5: Instruction Lockdown in Way Number 5 */ -#define L2CC_ILKR_ILK6 (1 << 6) /* Bit 6: Instruction Lockdown in Way Number 6 */ -#define L2CC_ILKR_ILK7 (1 << 7) /* Bit 7: Instruction Lockdown in Way Number 7 */ - -/* Lock Line Enable Register */ - -#ifdef CONFIG_PL310_LOCKDOWN_BY_LINE -# define L2CC_LKLN_ENABLE (1 << 0) /* Bit 0: Lockdown by line enable */ -#endif - -/* Unlock Way Register */ - -#ifdef CONFIG_PL310_LOCKDOWN_BY_LINE -# define L2CC_UNLKW_WAY_SHIFT (0) /* Bits 0-15: Unlock line for corresponding way */ -# define L2CC_UNLKW_WAY_MASK (0xffff << L2CC_UNLKW_WAY_SHIFT) -# define L2CC_UNLKW_WAY_SET(n) ((uint32_t)(n) << L2CC_UNLKW_WAY_SHIFT) -# define L2CC_UNLKW_WAY_BIT(n) ((1 << (n)) << L2CC_UNLKW_WAY_SHIFT) -#endif - -/* Address filter start */ - -#ifdef PL310_ADDRESS_FILTERING -# define L2CC_FLSTRT_ENABLE (1 << 0) /* Bit 0: Address filter enable */ -# define L2CC_FLSTRT_MASK (0xfff00000) /* Bits 20-31: Bits 20-31 of address mask */ -#endif - -/* Address filter end */ - -#ifdef PL310_ADDRESS_FILTERING -# define L2CC_FLEND_MASK (0xfff00000) /* Bits 20-31: Bits 20-31 of address mask */ -#endif - -/* Debug Control Register */ - -#define L2CC_DCR_DCL (1 << 0) /* Bit 0: Disable Cache Linefill */ -#define L2CC_DCR_DWB (1 << 1) /* Bit 1: Disable Write-back, Force Write-through */ -#define L2CC_DCR_SPNIDEN (1 << 2) /* Bit 2: SPNIDEN Value */ - -/* Prefetch Control Register */ - -#define L2CC_PCR_SHIFT (0) /* Bits 0-4: Prefetch Offset */ -#define L2CC_PCR_MASK (31 << L2CC_PCR_SHIFT) -#define L2CC_PCR_PREFETCH(n) ((uint32_t)(n) << L2CC_PCR_SHIFT) -#define L2CC_PCR_NSIDEN (1 << 21) /* Bit 21: Not Same ID on Exclusive Sequence Enable */ -#define L2CC_PCR_IDLEN (1 << 23) /* Bit 23: INCR Double Linefill Enable */ -#define L2CC_PCR_PDEN (1 << 24) /* Bit 24: Prefetch Drop Enable */ -#define L2CC_PCR_DLFWRDIS (1 << 27) /* Bit 27: Double Linefill on WRAP Read Disable */ -#define L2CC_PCR_DATPEN (1 << 28) /* Bit 28: Data Prefetch Enable */ -#define L2CC_PCR_INSPEN (1 << 29) /* Bit 29: Instruction Prefetch Enable */ -#define L2CC_PCR_DLEN (1 << 30) /* Bit 30: Double Linefill Enable */ - -/* Power Control Register */ - -#define L2CC_POWCR_STBYEN (1 << 0) /* Bit 0: Standby Mode Enable */ -#define L2CC_POWCR_DCKGATEN (1 << 1) /* Bit 1: Dynamic Clock Gating Enable */ - -#endif /* __ARCH_ARM_SRC_ARMV7_A_L2CC_PL310_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/device.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/device.h deleted file mode 100644 index 4a366b2a3..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/device.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2022 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ - -/** - * @file device.h - * @brief struct of imx6q devices - * @version 3.0 - * @author AIIT XUOS Lab - * @date 2023.8.10 - */ - -#include - -struct uart_desc { - uint32_t RXD_ADDR; - uint32_t TXD_ADDR; -}; - -struct arch_desc { - struct gic_desc { - uint32_t GICC_ADDR; - uint32_t GICD_ADDR; - - } gic; - -}; - - -struct page_pool { - uint32_t node; - uint32_t base; - uint32_t size; - uint32_t free; - uint32_t last; - -}; - -struct mem_region { - uint32_t base; - uint32_t size; - struct page_pool page_pool; -}; - - - - - - -struct board_desc{ - - uint32_t cpu_num; - uint32_t region_num; - struct mem_region *regions; - - struct { - uint32_t base_addr; - } console; - - uint32_t uart_num; - struct uart_desc *uarts; - - struct arch_desc arch; -}; \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q_desc.c b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q_desc.c deleted file mode 100644 index bdca2b4a3..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/imx6q_desc.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2022 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ - -/** - * @file imx6q_desc.c - * @brief config imx6q devices - * @version 3.0 - * @author AIIT XUOS Lab - * @date 2023.8.10 - */ - - -#include "device.h" - - -struct board_desc platform = { - .cpu_num = 4, - .region_num = 1, - .regions = (struct mem_region[]) { - { - - .base = 0x10000000, - .size = 0xFFFFFFFF - 0x10000000 - } - }, - - -#define URXD 0x0 /* Receiver Register */ -#define UTXD 0x40 /* Transmitter Register */ - - - - -#define AIPS1_ARB_BASE_ADDR 0x02000000 -#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR -#define UART1_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) - - -#define AIPS2_ARB_BASE_ADDR 0x02100000 -#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR -#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) - - .console = { - .base_addr=AIPS2_OFF_BASE_ADDR + 0x68000, - }, - - .arch = { - .gic = { - .GICD_ADDR = 0x00A01000, - .GICC_ADDR = 0x00A00100, - - }, - }, - - .uart_num=2, - .uarts=(struct uart_desc[]){ - //UART 0 - { - .RXD_ADDR=0xF9010000, - .TXD_ADDR=0xF9010000, - }, - //UART 1 - { - .RXD_ADDR=0xF9010000, - .TXD_ADDR=0xF9010000, - } - } -}; From 196a8e001ae5d4ba0f299e8a9845b872c2ccbb0f Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Wed, 11 Oct 2023 17:30:56 +0800 Subject: [PATCH 18/21] add some files --- .../abstraction/abstraction/Makefile | 3 + .../abstraction/abstraction/abstraction_mmu.c | 206 +++++++++++++++++ .../abstraction/abstraction/abstraction_mmu.h | 114 ++++++++++ .../abstraction/abstraction/cache.c | 35 +++ .../hardkernel/abstraction/abstraction/isr.c | 215 ++++++++++++++++++ .../hardkernel/abstraction/abstraction/isr.h | 98 ++++++++ 6 files changed, 671 insertions(+) create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/Makefile create mode 100755 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/abstraction_mmu.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/abstraction_mmu.h create mode 100755 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/cache.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/isr.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/isr.h diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/Makefile new file mode 100644 index 000000000..c794367b8 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := cache.c isr.c abstraction_mmu.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/abstraction_mmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/abstraction_mmu.c new file mode 100755 index 000000000..6f37b7d6f --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/abstraction_mmu.c @@ -0,0 +1,206 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: abstraction_mmu.c +* @brief: the general management of system mmu +* @version: 3.0 +* @author: AIIT XUOS Lab +* @date: 2023/4/27 +* +*/ + +#include + +AbstractionMmu abstraction_mmu; + +volatile uint32_t global_L1_pte_table[4096]; + +/** + * @description: write cmd to CP15 register + * @param reg_type - CP15 register type + * @param val - ops val pointer + * @return + */ +static void MmuCp15Write(uint8_t reg_type, uint32_t *val) +{ + uint32_t write_val = *val; + switch (reg_type) { + case AM_MMU_CP15_TTBCR: + TTBCR_W(write_val); + AM_ISB; + case AM_MMU_CP15_TTBR0: + TTBR0_W(write_val); + AM_ISB; + default: + break; + } +} + +/** + * @description: read CP15 register from mmu + * @param reg_type - CP15 register type + * @param val - ops val pointer + * @return + */ +static void MmuCp15Read(uint8_t reg_type, uint32_t *val) +{ + uint32_t read_val = 0; + switch (reg_type) { + case AM_MMU_CP15_TTBCR: + TTBCR_R(read_val); + case AM_MMU_CP15_TTBR0: + TTBR0_R(read_val); + default: + break; + } + + *val = read_val; +} + +/** + * @description: write or read CP15 register to set mmu + * @param ops_type - CP15 write or read + * @param reg_type - CP15 register type + * @param val - ops val pointer + * @return + */ +static void MmuRegOps(uint8_t ops_type, uint8_t reg_type, uint32_t *val) +{ + switch (ops_type) { + case AM_MMU_CP15_WRITE: + MmuCp15Write(reg_type, val); + case AM_MMU_CP15_READ: + MmuCp15Read(reg_type, val); + default: + break; + } +} + +/** + * @description: Init abstraction_mmu function + * @param mmu - abstraction mmu pointer + * @param ttb_base - ttb base pointer + * @return success : 0 error : -1 + */ +static int _AbstractionMmuInit(AbstractionMmu *mmu, uint32_t *ttb_base) +{ + mmu_init(); + + return 0; +} + +/** + * @description: map L1 or L2 page table section + * @param mmu - abstraction mmu pointer + * @param section_size - section size + * @return success : 0 error : -1 + */ +static int _AbstractionMmuSectionMap(AbstractionMmu *mmu, uint32_t section_size) +{ + uint32_t vaddr_length = mmu->vaddr_end - mmu->vaddr_start + 1; + + mmu_map_l1_range(mmu->paddr_start, mmu->vaddr_start, vaddr_length, + mmu->mmu_memory_type, mmu->mmu_shareability, mmu->mmu_access); + + mmu->mmu_status = 1; + + return 0; +} + +/** + * @description: unmap L1 or L2 page table section + * @param mmu - abstraction mmu pointer + * @param vaddr_start - virtual address start + * @param vaddr_size - virtual address size + * @return success : 0 error : -1 + */ +static int _AbstractionMmuSectionUnmap(AbstractionMmu *mmu, uint32_t vaddr_start, uint32_t vaddr_size) +{ + uint32_t *l1_umap_ventry = mmu->ttb_vbase + (vaddr_start >> AM_MMU_L1_SECTION_SHIFT); + uint32_t vaddr_end = vaddr_start + vaddr_size - 1; + uint32_t umap_count = (vaddr_end >> AM_MMU_L1_SECTION_SHIFT) - (vaddr_start >> AM_MMU_L1_SECTION_SHIFT) + 1; + + while (umap_count) { + AM_DMB; + *l1_umap_ventry = 0; + AM_DSB; + + umap_count--; + l1_umap_ventry += (1 << AM_MMU_L1_SECTION_SHIFT);//1MB section + } + + AM_DSB; + CLEARTLB(0);//clear TLB data and configure + AM_DSB; + AM_ISB; + mmu->mmu_status = 0; + + return 0; +} + +/** + * @description: switch ttb base by re-write ttbr register + * @param mmu - abstraction mmu pointer + * @return success : 0 error : -1 + */ +static int _AbstractionMmuTtbSwitch(AbstractionMmu *mmu) +{ + uint32_t ttbr, ttbcr; + MmuRegOps(AM_MMU_CP15_READ, AM_MMU_CP15_TTBCR, &ttbcr); + + /* Set TTBR0 with inner/outer write back write allocate and not shareable, [4:3]=01, [1]=0, [6,0]=01 */ + ttbr = ((mmu->ttb_pbase & 0xFFFFC000UL) | 0x9UL); + /* enable TTBR0 */ + ttbcr = 0; + + AM_DSB; + MmuRegOps(AM_MMU_CP15_WRITE, AM_MMU_CP15_TTBR0, &ttbr); + MmuRegOps(AM_MMU_CP15_WRITE, AM_MMU_CP15_TTBCR, &ttbcr); + + return 0; +} + +/** + * @description: get physical address transformed from virtual address + * @param mmu - abstraction mmu pointer + * @param vaddr - virtual address pointer + * @param paddr - physical address pointer + * @return success : 0 error : -1 + */ +static int _AbstracktonMmuTransform(AbstractionMmu *mmu, uint32_t *vaddr, uint32_t *paddr) +{ + uint32_t virtualAddress = *vaddr; + + if (mmu->mmu_status) { + mmu_virtual_to_physical(virtualAddress, paddr); + } + + return 0; +} + +static struct AbstractionMmuDone mmu_done = { + .AbstractionMmuInit = _AbstractionMmuInit, + .AbstractionMmuSectionMap = _AbstractionMmuSectionMap, + .AbstractionMmuSectionUnmap = _AbstractionMmuSectionUnmap, + .AbstractionMmuTtbSwitch = _AbstractionMmuTtbSwitch, + .AbstracktonMmuTransform = _AbstracktonMmuTransform, +}; + +/** + * @description: init abstraciton mmu info when system start + * @return success : 0 error : -1 + */ +int SysInitAbstractionMmu(void) +{ + abstraction_mmu.mmu_done = &mmu_done; +} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/abstraction_mmu.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/abstraction_mmu.h new file mode 100644 index 000000000..ce3c35d06 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/abstraction_mmu.h @@ -0,0 +1,114 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: mmu.h +* @brief: the general management of system mmu +* @version: 3.0 +* @author: AIIT XUOS Lab +* @date: 2023/5/24 +* +*/ +#include +#include + +#define ARCH_ARM +#ifdef ARCH_ARM +/* ARM System Registers */ +#define AM_DSB __asm__ volatile("dsb" ::: "memory") +#define AM_DMB __asm__ volatile("dmb" ::: "memory") +#define AM_ISB __asm__ volatile("isb" ::: "memory") +#define AM_WFI __asm__ volatile("wfi" ::: "memory") +#define AM_BARRIER __asm__ volatile("":::"memory") +#define AM_WFE __asm__ volatile("wfe" ::: "memory") +#define AM_SEV __asm__ volatile("sev" ::: "memory") + +#define TTBR0_R(val) __asm__ volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(val)) +#define TTBR0_W(val) __asm__ volatile("mcr p15, 0, %0, c2, c0, 0" ::"r"(val)) + +#define TTBCR_R(val) __asm__ volatile("mrc p15, 0, %0, c2, c0, 2" : "=r"(val)) +#define TTBCR_W(val) __asm__ volatile("mcr p15, 0, %0, c2, c0, 2" ::"r"(val)) + +#define CLEARTLB(val) __asm__ volatile("mcr p15, 0, %0, c8, c7, 0" ::"r"(val)) +#endif + +#define AM_MMU_L1_PAGE_TABLE_SIZE (4 * 4096) +#define AM_MMU_L1_SECTION_SHIFT 20 + +typedef enum +{ + AM_MMU_CP15_WRITE = 0, + AM_MMU_CP15_READ, +}MmuCP15OpsType; + +typedef enum +{ + AM_MMU_CP15_TTBCR = 0, + AM_MMU_CP15_TTBR0, + AM_MMU_CP15_CLEARTLB, +}MmuCP15RegType; + +typedef enum +{ + AM_StronglyOrdered = 0, + AM_Device, + AM_OuterInner_WB_WA, + AM_OuterInner_WT, + AM_Noncacheable, +}MmuMemoryType; + +typedef enum +{ + AM_Noaccess = 0, + AM_Read_Write, + AM_Read, +}MmuAccess; + +typedef enum +{ + AM_Shareable = 1, + AM_Nonshareable = 0 +}MmuShareability; + +struct AbstractionMmuDone +{ + int (*AbstractionMmuInit)(AbstractionMmu *mmu, uint32_t *ttb_base); + int (*AbstractionMmuSectionMap)(AbstractionMmu *mmu, uint32_t section_size); + int (*AbstractionMmuSectionUnmap)(AbstractionMmu *mmu, uint32_t vaddr_start, uint32_t vaddr_size); + int (*AbstractionMmuTtbSwitch)(AbstractionMmu *mmu); + int (*AbstracktonMmuTransform)(AbstractionMmu *mmu, uint32_t *vaddr, uint32_t *paddr); +}; + +typedef struct +{ + uint32_t ttb_vbase; + uint32_t ttb_pbase; + + uint32_t vaddr_start; + uint32_t vaddr_end; + uint32_t paddr_start; + uint32_t paddr_end; + + uint32_t vpaddr_offset; + + uint32_t pte_attr; + uint32_t mmu_status; + + MmuMemoryType mmu_memory_type; + MmuAccess mmu_access; + MmuShareability mmu_shareability; + + struct AbstractionMmuDone *mmu_done; + + int lock; + int link_list; +}AbstractionMmu; \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/cache.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/cache.c new file mode 100755 index 000000000..4a71e6c30 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/cache.c @@ -0,0 +1,35 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: cache.c +* @brief: the general management of system cache +* @version: 3.0 +* @author: AIIT XUOS Lab +* @date: 2023/4/27 +* +*/ + +void InvalidInsCache() +{ + PlatInvalidInsCache(); +} + +void InvalidDataCache(unsigned long start, unsigned long end) +{ + PlatInvalidDateCache(start, end); +} + +void CleanDataCache(unsigned long start, unsigned long end) +{ + PlatCleanDateCache(start, end); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/isr.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/isr.c new file mode 100644 index 000000000..94dbc9fb1 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/isr.c @@ -0,0 +1,215 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: isr.c +* @brief: the general management of system isr +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/15 +* +*/ +#include +#include "isr.h" + +struct InterruptServiceRoutines isrManager = {0} ; + +#ifdef ARCH_SMP +extern int GetCpuId(void); +#endif +/** + * This functionwill get the isr nest level. + * + * @return isr nest level + */ +static uint16_t GetIsrCounter() +{ + uint16_t ret = 0; + +#ifdef ARCH_SMP + ret = isrManager.isr_count[GetCpuId()]; +#else + ret = isrManager.isr_count; +#endif + return ret; +} + +static void IncIsrCounter() +{ +#ifdef ARCH_SMP + isrManager.isr_count[GetCpuId()] ++ ; +#else + isrManager.isr_count ++; +#endif + return ; +} + +static void DecIsrCounter() +{ + +#ifdef ARCH_SMP + isrManager.isr_count[GetCpuId()] -- ; +#else + isrManager.isr_count --; +#endif + return ; +} + +bool IsInIsr() +{ +#ifdef ARCH_SMP + return ( isrManager.isr_count[GetCpuId()] != 0 ? TRUE : FALSE ) ; +#else + return ( isrManager.isr_count != 0 ? TRUE : FALSE ) ; +#endif + +} +/** + * This function will register a new irq. + * + * @param irq_num the number of the irq + * @param handler the callback of the interrupt + * @param arg param of thge callback + * + * @return 0 on success; -1 on failure + */ +static int32_t RegisterHwIrq(uint32_t irq_num, IsrHandlerType handler, void *arg) +{ + if (irq_num >= ARCH_MAX_IRQ_NUM ) + return -1; + + struct IrqDesc *desc = &isrManager.irq_table[irq_num]; + + desc->handler = handler; + desc->param = arg; + + return 0; +} +/** + * This function will free a irq. + * + * @param irq_num the number of the irq + * + * @return 0 on success; -1 on failure + */ +static int32_t FreeHwIrq(uint32_t irq_num) +{ + if (irq_num >= ARCH_MAX_IRQ_NUM ) + return -1; + + memset(&isrManager.irq_table[irq_num], 0, sizeof(struct IrqDesc)); + + return 0; +} + +/** + * This function will enable a irq. + * + * @param irq_num the number of the irq + * + * @return 0 on success; -1 on failure + */ +static int32_t EnableHwIrq(uint32_t irq_num, uint32_t cpu_id) +{ + if (irq_num >= ARCH_MAX_IRQ_NUM ) + return -1; + + return ArchEnableHwIrq(irq_num, cpu_id); +} +/** + * This function will disable a irq. + * + * @param irq_num the number of the irq + * + * @return 0 on success; -1 on failure + */ + +static int32_t DisableHwIrq(uint32_t irq_num, uint32_t cpu_id) +{ + if (irq_num >= ARCH_MAX_IRQ_NUM ) + return -1; + + return ArchDisableHwIrq(irq_num, cpu_id); +} + +/* called from arch-specific ISR wrapper */ +static void IsrCommon(uint32_t irq_num) +{ + struct IrqDesc *desc = &isrManager.irq_table[irq_num]; + + if (desc->handler == NULL) { + // SYS_KDEBUG_LOG(KDBG_IRQ, ("Spurious interrupt: IRQ No. %d\n", irq_num)); + while (1) {} + } + desc->handler(irq_num, desc->param); + +} + +static void SetIsrSwitchTrigerFlag() +{ + +#ifdef ARCH_SMP + isrManager.isr_switch_trigger_flag[GetCpuId()] = 1; +#else + isrManager.isr_switch_trigger_flag = 1; +#endif +} + +static void ClearIsrSwitchTrigerFlag() +{ + +#ifdef ARCH_SMP + isrManager.isr_switch_trigger_flag[GetCpuId()] = 0; +#else + isrManager.isr_switch_trigger_flag = 0; +#endif +} + +static uint8_t GetIsrSwitchTrigerFlag() +{ + +#ifdef ARCH_SMP + return isrManager.isr_switch_trigger_flag[GetCpuId()]; +#else + return isrManager.isr_switch_trigger_flag ; +#endif +} + +struct IsrDone isrDone = { + IsInIsr, + RegisterHwIrq , + FreeHwIrq, + EnableHwIrq, + DisableHwIrq, + IsrCommon, + GetIsrCounter, + IncIsrCounter, + DecIsrCounter, + GetIsrSwitchTrigerFlag, + SetIsrSwitchTrigerFlag, + ClearIsrSwitchTrigerFlag +}; + +void SysInitIsrManager() +{ + extern int __isrtbl_idx_start; + extern int __isrtbl_start; + extern int __isrtbl_end; + memset(&isrManager,0,sizeof(struct InterruptServiceRoutines)); + isrManager.done = &isrDone; + + uint32_t *index = (uint32_t *)&__isrtbl_idx_start; + struct IrqDesc *desc = (struct IrqDesc *)&__isrtbl_start; + + while (desc != (struct IrqDesc *)&__isrtbl_end) + isrManager.irq_table[*index++] = *desc++; +} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/isr.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/isr.h new file mode 100644 index 000000000..1e0ddcfbf --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/isr.h @@ -0,0 +1,98 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: isr.h +* @brief: function declaration and structure defintion of isr +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2020/3/10 +* +*/ + +#ifndef __ISR_H__ +#define __ISR_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#define DECLARE_HW_IRQ(_irq_num, _handler, _arg) \ + const uint32_t __irq_desc_idx_##_handler SECTION(".isrtbl.idx") = _irq_num + ARCH_IRQ_NUM_OFFSET ; \ + const struct IrqDesc __irq_desc_##_handler SECTION(".isrtbl") = { \ + .handler = _handler, \ + .param = _arg, \ + } + +typedef void (*IsrHandlerType)(int vector, void *param); + +struct IrqDesc +{ + IsrHandlerType handler; + void *param; + +#ifdef CONFIG_INTERRUPT_INFO + char name[NAME_NUM_MAX]; + uint32_t counter; +#endif +}; + +struct IsrDone +{ + bool (*isInIsr)(); + int32_t (*registerIrq)(uint32_t irq_num, IsrHandlerType handler, void *arg); + int32_t (*freeIrq)(uint32_t irq_num); + int32_t (*enableIrq)(uint32_t irq_num, uint32_t cpu_id); + int32_t (*disableIrq)(uint32_t irq_num, uint32_t cpu_id); + void (*handleIrq)(uint32_t irq_num); + uint16_t (*getCounter)() ; + void (*incCounter)(); + void (*decCounter)(); + uint8_t (*getSwitchTrigerFlag)(); + void (*setSwitchTrigerFlag)(); + void (*clearSwitchTrigerFlag)(); +}; + +struct InterruptServiceRoutines { + +#ifdef ARCH_SMP + volatile uint16_t isr_count[CPU_NUMBERS]; + volatile uint8_t isr_switch_trigger_flag[CPU_NUMBERS]; +#else + volatile uint16_t isr_count ; + volatile uint8_t isr_switch_trigger_flag; +#endif + struct IrqDesc irq_table[ARCH_MAX_IRQ_NUM]; + struct IsrDone *done; +}; + +extern struct InterruptServiceRoutines isrManager ; + +uint32_t DisableLocalInterrupt(); +void EnableLocalInterrupt(unsigned long level); + +#define DISABLE_INTERRUPT DisableLocalInterrupt +#define ENABLE_INTERRUPT EnableLocalInterrupt + +void SysInitIsrManager(); +void InitHwinterrupt(void); + + +#ifdef __cplusplus +} +#endif + +#endif From 341cfd34bd10e171dcd4e088d4e0487e0265d51a Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Wed, 11 Oct 2023 17:34:24 +0800 Subject: [PATCH 19/21] modify location --- .../XiZi_AIoT/hardkernel/abstraction/{abstraction => }/Makefile | 0 .../hardkernel/abstraction/{abstraction => }/abstraction_mmu.c | 0 .../hardkernel/abstraction/{abstraction => }/abstraction_mmu.h | 0 .../XiZi_AIoT/hardkernel/abstraction/{abstraction => }/cache.c | 0 .../XiZi_AIoT/hardkernel/abstraction/{abstraction => }/isr.c | 0 .../XiZi_AIoT/hardkernel/abstraction/{abstraction => }/isr.h | 0 6 files changed, 0 insertions(+), 0 deletions(-) rename Ubiquitous/XiZi_AIoT/hardkernel/abstraction/{abstraction => }/Makefile (100%) rename Ubiquitous/XiZi_AIoT/hardkernel/abstraction/{abstraction => }/abstraction_mmu.c (100%) rename Ubiquitous/XiZi_AIoT/hardkernel/abstraction/{abstraction => }/abstraction_mmu.h (100%) rename Ubiquitous/XiZi_AIoT/hardkernel/abstraction/{abstraction => }/cache.c (100%) rename Ubiquitous/XiZi_AIoT/hardkernel/abstraction/{abstraction => }/isr.c (100%) rename Ubiquitous/XiZi_AIoT/hardkernel/abstraction/{abstraction => }/isr.h (100%) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/Makefile similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/Makefile rename to Ubiquitous/XiZi_AIoT/hardkernel/abstraction/Makefile diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/abstraction_mmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction_mmu.c similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/abstraction_mmu.c rename to Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction_mmu.c diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/abstraction_mmu.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction_mmu.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/abstraction_mmu.h rename to Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction_mmu.h diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/cache.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/cache.c rename to Ubiquitous/XiZi_AIoT/hardkernel/abstraction/cache.c diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/isr.c b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.c similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/isr.c rename to Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.c diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/isr.h b/Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.h similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/abstraction/abstraction/isr.h rename to Ubiquitous/XiZi_AIoT/hardkernel/abstraction/isr.h From 24023fd343932b616e13af690973ceade9ccaba6 Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Wed, 11 Oct 2023 17:51:27 +0800 Subject: [PATCH 20/21] modify description --- Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.c | 7 ++----- Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link.lds | 8 ++++---- Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link_m7.lds | 8 ++++---- .../third_party_driver/include/connect_gpio.h | 4 ++-- .../third_party_driver/include/connect_uart.h | 4 ++-- Ubiquitous/XiZi_IIoT/path_kernel.mk | 2 -- Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/Makefile | 4 ---- .../XiZi_IIoT/resources/ethernet/LwIP/arch/lwipopts.h | 1 - 8 files changed, 14 insertions(+), 24 deletions(-) diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.c b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.c index 4b7c6b157..34051709d 100644 --- a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.c +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/board.c @@ -14,7 +14,7 @@ * @file board.c * @brief support cortex-m7-emulator-board init configure and start-up * @version 1.0 -* @author fudan +* @author AIIT XUOS Lab * @date 2023-09-27 */ @@ -198,8 +198,5 @@ void InitBoardHardware() KPrintf("board init done.\n"); KPrintf("start kernel...\n"); -#ifdef TOOL_USING_OTA - //跳转成功设置lastjumpflag为JUMP_SUCCESS_FLAG - app_clear_jumpflag(); -#endif + } diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link.lds b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link.lds index b71abc9fd..74e24c01a 100644 --- a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link.lds +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link.lds @@ -28,18 +28,18 @@ /** * @file link.lds -* @brief xidatong-arm32 Linker script +* @brief cortex-m7 emulator Linker script * @version 1.0 * @author AIIT XUOS Lab -* @date 2021-05-28 +* @date 2021-09-27 */ /************************************************* File name: link.lds -Description: xidatong-arm32 Linker script +Description: cortex-m7 emulator Linker script Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references History: -1. Date: 2021-05-28 +1. Date: 2021-09-27 Author: AIIT XUOS Lab Modification: 1. add shell cmd table and g_service_table diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link_m7.lds b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link_m7.lds index b71abc9fd..511735325 100644 --- a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link_m7.lds +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/link_m7.lds @@ -28,18 +28,18 @@ /** * @file link.lds -* @brief xidatong-arm32 Linker script +* @brief cortex-m7 emulator Linker script * @version 1.0 * @author AIIT XUOS Lab -* @date 2021-05-28 +* @date 2021-09-27 */ /************************************************* File name: link.lds -Description: xidatong-arm32 Linker script +Description:cortex-m7 emulator Linker script Others: take MIMXRT1052xxxxx_flexspi_nor.ld for references History: -1. Date: 2021-05-28 +1. Date: 2021-09-27 Author: AIIT XUOS Lab Modification: 1. add shell cmd table and g_service_table diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/connect_gpio.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/connect_gpio.h index f9da70b31..6f4316e2e 100644 --- a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/connect_gpio.h +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/connect_gpio.h @@ -12,10 +12,10 @@ /** * @file connect_gpio.h -* @brief define imxrt1052-board gpio function and struct +* @brief define m7 emulator gpio function and struct * @version 2.0 * @author AIIT XUOS Lab -* @date 2022-03-15 +* @date 2023-09-27 */ #ifndef __CONNECT_GPIO_H_ diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/connect_uart.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/connect_uart.h index 4b4c947a8..f9e33e320 100644 --- a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/connect_uart.h +++ b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/connect_uart.h @@ -12,10 +12,10 @@ /** * @file connect_uart.h -* @brief define imxrt1052-board usart function and struct +* @brief define m7 emulator usart function and struct * @version 2.0 * @author AIIT XUOS Lab -* @date 2022-03-15 +* @date 2023-09-27 */ #ifndef CONNECT_UART_H diff --git a/Ubiquitous/XiZi_IIoT/path_kernel.mk b/Ubiquitous/XiZi_IIoT/path_kernel.mk index 23cc92714..6663617b7 100755 --- a/Ubiquitous/XiZi_IIoT/path_kernel.mk +++ b/Ubiquitous/XiZi_IIoT/path_kernel.mk @@ -41,8 +41,6 @@ KERNELPATHS += \ -I$(KERNEL_ROOT)/include \ -I$(KERNEL_ROOT)/resources/include - - ifeq ($(CONFIG_RESOURCES_LWIP),y) KERNELPATHS += \ -I$(KERNEL_ROOT)/resources/ethernet/LwIP/include \ diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/Makefile b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/Makefile index 3b2116a85..b59cbd62e 100644 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/Makefile +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/Makefile @@ -2,16 +2,12 @@ SRC_DIR += api SRC_DIR += arch SRC_DIR += core SRC_DIR += netif - - SRC_DIR += apps LWIP_DIR += api LWIP_DIR += arch LWIP_DIR += core LWIP_DIR += netif - - LWIP_DIR += apps include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/arch/lwipopts.h b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/arch/lwipopts.h index 7ee9d1273..ee9a40abc 100644 --- a/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/arch/lwipopts.h +++ b/Ubiquitous/XiZi_IIoT/resources/ethernet/LwIP/arch/lwipopts.h @@ -46,7 +46,6 @@ // #define LWIP_API_MSG_DEBUG #endif - #ifdef LWIP_DEBUG #ifdef LWIP_SYS_DEBUG #define SYS_DEBUG LWIP_DBG_ON From 1cf3baeb2e9ff1565afdd3659cf41e2571d47227 Mon Sep 17 00:00:00 2001 From: huang <1085210385@qq.com> Date: Wed, 11 Oct 2023 17:57:09 +0800 Subject: [PATCH 21/21] delete clock --- .../cortex-m7-emulator/third_party_driver/include/fsl_clock.h | 0 1 file changed, 0 insertions(+), 0 deletions(-) delete mode 100755 Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/fsl_clock.h diff --git a/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/fsl_clock.h b/Ubiquitous/XiZi_IIoT/board/cortex-m7-emulator/third_party_driver/include/fsl_clock.h deleted file mode 100755 index e69de29bb..000000000