diff --git a/board/aiit-arm32-board/board.c b/board/aiit-arm32-board/board.c
index 5aa161265..b25c2266a 100644
--- a/board/aiit-arm32-board/board.c
+++ b/board/aiit-arm32-board/board.c
@@ -144,11 +144,9 @@ struct InitSequenceDesc _board_init[] =
 #ifdef BSP_USING_SDIO
     {"hw sdcard init",HwSdioInit},
 #endif
-// #ifdef BSP_USING_EXTMEM
-// #ifdef DATA_IN_ExtSRAM
-//     {"hw ext sram",HwSramInit},
-// #endif
-// #endif
+#ifdef BSP_USING_EXTMEM
+    { "hw extern sram", HwSramInit },
+#endif
 	{ " NONE ",NONE },
 };
 
@@ -161,7 +159,7 @@ void InitBoardHardware()
     NVIC_Configuration();
 
     SysTickConfiguration();
-            InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
+    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
 
 #ifdef BSP_USING_UART
 	Stm32HwUsartInit();
@@ -174,13 +172,6 @@ void InitBoardHardware()
     KPrintf("board initialization......\n");
 #endif
 
-#ifdef BSP_USING_EXTMEM
-    extern int HwSramInit(void);
-    HwSramInit();
-#endif
-
-    InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
-
 #ifdef SEPARATE_COMPILE
 
     // init mpu
diff --git a/board/aiit-arm32-board/third_party_driver/Kconfig b/board/aiit-arm32-board/third_party_driver/Kconfig
index b7a22104f..b48232b0d 100755
--- a/board/aiit-arm32-board/third_party_driver/Kconfig
+++ b/board/aiit-arm32-board/third_party_driver/Kconfig
@@ -15,6 +15,7 @@ endif
 menuconfig BSP_USING_EXTMEM
 bool "Using EXTMEM device"
 default n
+select MEM_EXTERN_SRAM
 if BSP_USING_EXTMEM
 source "$BSP_DIR/third_party_driver/extmem/Kconfig"
 endif
diff --git a/board/aiit-arm32-board/third_party_driver/extmem/Kconfig b/board/aiit-arm32-board/third_party_driver/extmem/Kconfig
index 4010be56d..27186cb7c 100644
--- a/board/aiit-arm32-board/third_party_driver/extmem/Kconfig
+++ b/board/aiit-arm32-board/third_party_driver/extmem/Kconfig
@@ -1,22 +1,17 @@
-menu "Extern Sram Config"
-    config DATA_IN_ExtSRAM
-        bool "support extern sram"
+if  BSP_USING_EXTMEM
+    config EXTSRAM_MAX_NUM
+        int
+        default 4
+        
+    config BSP_USING_FSMC_BANK1_NORSRAM3
+        bool "config fsmc bank1 sram3"
         default n
-    if  DATA_IN_ExtSRAM
-        config EXTSRAM_MAX_NUM
-            int
-            default 4
-
-        config BSP_USING_FSMC_BANK1_NORSRAM3
-            bool "config fsmc bank1 sram3"
-            default n
-            if BSP_USING_FSMC_BANK1_NORSRAM3
-                config BANK1_NORSRAM3_SIZE
-                    hex "config sram chip size"
-                    default 0x100000
-                config BANK1_NORSRAM3_DATA_WIDTH
-                    int "sram chip data width"
-                    default 16
-            endif
-    endif
-endmenu
+        if BSP_USING_FSMC_BANK1_NORSRAM3
+            config BANK1_NORSRAM3_SIZE
+                hex "config sram3 chip size"
+                default 0x100000
+            config BANK1_NORSRAM3_DATA_WIDTH
+                int "config sram3 chip data width"
+                default 16 
+        endif
+endif
diff --git a/board/aiit-arm32-board/third_party_driver/extmem/connect_fsmc.c b/board/aiit-arm32-board/third_party_driver/extmem/connect_fsmc.c
index f7f1d2d40..74313937c 100644
--- a/board/aiit-arm32-board/third_party_driver/extmem/connect_fsmc.c
+++ b/board/aiit-arm32-board/third_party_driver/extmem/connect_fsmc.c
@@ -1,133 +1,162 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_fsmc.c
+* @brief support extern memory by fsmc
+* @version 1.0
+* @author AIIT XUOS Lab
+* @date 2021-05-28
+*/
+
+#include "connect_fsmc.h"
 #include "hardware_fsmc.h"
 #include "hardware_gpio.h"
 #include "hardware_rcc.h"
+#include <string.h>
+#include <xs_base.h>
 
-#define SRAM_DATA_WIDTH      16
+#define FSMC_BANK1_NORSRAM3_START_ADDRESS 0x68000000
 
-static FSMC_NORSRAMInitTypeDef hsram;
-static FSMC_NORSRAMTimingInitTypeDef hsram_read;
-static FSMC_NORSRAMTimingInitTypeDef hsram_write;
+static FSMC_NORSRAMInitTypeDef hsram3;
+static FSMC_NORSRAMTimingInitTypeDef hsram_read3;
+static FSMC_NORSRAMTimingInitTypeDef hsram_write3;
+
+extern void ExtSramInitBoardMemory(void *start_phy_address, void *end_phy_address, uint8 extsram_idx);
 
 int HwSramInit(void)
 {
     GPIO_InitTypeDef GPIO_InitStructure;
 
-    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE|RCC_AHB1Periph_GPIOF|RCC_AHB1Periph_GPIOG, ENABLE);
-    RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC,ENABLE);
+	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE|RCC_AHB1Periph_GPIOF|RCC_AHB1Periph_GPIOG, ENABLE);
+	RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC,ENABLE);
 
-    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
-    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
-    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
-    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
-    GPIO_Init(GPIOD, &GPIO_InitStructure);
-      
-    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
-    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
-    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
-    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
-    GPIO_Init(GPIOE, &GPIO_InitStructure);  
-    
-    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
-    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
-    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
-    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
-    GPIO_Init(GPIOF, &GPIO_InitStructure);
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+	GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+	GPIO_Init(GPIOD, &GPIO_InitStructure);
+		
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+	GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+	GPIO_Init(GPIOE, &GPIO_InitStructure);  
+	
+ 	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+	GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+	GPIO_Init(GPIOF, &GPIO_InitStructure);
 
-    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_10 | GPIO_Pin_12;
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
-    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
-    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
-    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
-    GPIO_Init(GPIOG, &GPIO_InitStructure);
-    
-    GPIO_PinAFConfig(GPIOD,GPIO_PinSource0,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOD,GPIO_PinSource1,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOD,GPIO_PinSource4,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOD,GPIO_PinSource5,GPIO_AF_FSMC); 
-    GPIO_PinAFConfig(GPIOD,GPIO_PinSource8,GPIO_AF_FSMC); 
-    GPIO_PinAFConfig(GPIOD,GPIO_PinSource9,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOD,GPIO_PinSource10,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOD,GPIO_PinSource11,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOD,GPIO_PinSource12,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOD,GPIO_PinSource13,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOD,GPIO_PinSource14,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOD,GPIO_PinSource15,GPIO_AF_FSMC);
-  
-    GPIO_PinAFConfig(GPIOE,GPIO_PinSource7,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOE,GPIO_PinSource8,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOE,GPIO_PinSource9,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOE,GPIO_PinSource10,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOE,GPIO_PinSource11,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOE,GPIO_PinSource12,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOE,GPIO_PinSource13,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOE,GPIO_PinSource14,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOE,GPIO_PinSource15,GPIO_AF_FSMC);
-    
-    GPIO_PinAFConfig(GPIOF,GPIO_PinSource0,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOF,GPIO_PinSource1,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOF,GPIO_PinSource2,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOF,GPIO_PinSource3,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOF,GPIO_PinSource4,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOF,GPIO_PinSource5,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOF,GPIO_PinSource12,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOF,GPIO_PinSource13,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOF,GPIO_PinSource14,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOF,GPIO_PinSource15,GPIO_AF_FSMC);
-      
-    GPIO_PinAFConfig(GPIOG,GPIO_PinSource0,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOG,GPIO_PinSource1,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOG,GPIO_PinSource2,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOG,GPIO_PinSource3,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOG,GPIO_PinSource4,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOG,GPIO_PinSource5,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOG,GPIO_PinSource10,GPIO_AF_FSMC);
-    GPIO_PinAFConfig(GPIOG,GPIO_PinSource12,GPIO_AF_FSMC);
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_10 | GPIO_Pin_12;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+	GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+	GPIO_Init(GPIOG, &GPIO_InitStructure);
+	
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource0,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource1,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource4,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource5,GPIO_AF_FSMC); 
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource8,GPIO_AF_FSMC); 
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource9,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource10,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource11,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource12,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource13,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource14,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOD,GPIO_PinSource15,GPIO_AF_FSMC);
+ 
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource7,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource8,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource9,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource10,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource11,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource12,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource13,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource14,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOE,GPIO_PinSource15,GPIO_AF_FSMC);
+	
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource0,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource1,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource2,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource3,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource4,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource5,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource12,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource13,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource14,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOF,GPIO_PinSource15,GPIO_AF_FSMC);
+		
+	GPIO_PinAFConfig(GPIOG,GPIO_PinSource0,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOG,GPIO_PinSource1,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOG,GPIO_PinSource2,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOG,GPIO_PinSource3,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOG,GPIO_PinSource4,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOG,GPIO_PinSource5,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOG,GPIO_PinSource10,GPIO_AF_FSMC);
+	GPIO_PinAFConfig(GPIOG,GPIO_PinSource12,GPIO_AF_FSMC);
 
-    hsram.FSMC_ReadWriteTimingStruct = &hsram_read;
-    hsram.FSMC_WriteTimingStruct = &hsram_write;
+	hsram3.FSMC_ReadWriteTimingStruct = &hsram_read3;
+	hsram3.FSMC_WriteTimingStruct = &hsram_write3;
 
-    /* hsram.Init */
-    hsram.FSMC_Bank = FSMC_Bank1_NORSRAM1;
-    hsram.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
-    hsram.FSMC_MemoryType = FSMC_MemoryType_SRAM;
-#if SRAM_DATA_WIDTH == 8
-    hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
-#elif SRAM_DATA_WIDTH == 16
-    hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+    /* hsram3.Init */
+    hsram3.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+    hsram3.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+    hsram3.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+    hsram3.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+    hsram3.FSMC_WrapMode = FSMC_WrapMode_Disable;
+    hsram3.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+    hsram3.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+    hsram3.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+    hsram3.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+    hsram3.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+
+    hsram_read3.FSMC_AddressSetupTime = 0;
+    hsram_read3.FSMC_AddressHoldTime = 0;
+    hsram_read3.FSMC_DataSetupTime = 8;
+    hsram_read3.FSMC_BusTurnAroundDuration = 0;
+    hsram_read3.FSMC_CLKDivision = 0;
+    hsram_read3.FSMC_DataLatency = 0;
+    hsram_read3.FSMC_AccessMode = FSMC_AccessMode_A;
+
+    hsram_write3.FSMC_AddressSetupTime = 0;
+    hsram_write3.FSMC_AddressHoldTime = 0;
+    hsram_write3.FSMC_DataSetupTime = 8;
+    hsram_write3.FSMC_BusTurnAroundDuration = 0;
+    hsram_write3.FSMC_CLKDivision = 0;
+    hsram_write3.FSMC_DataLatency = 0;
+    hsram_write3.FSMC_AccessMode = FSMC_AccessMode_A;
+
+#ifdef BSP_USING_FSMC_BANK1_NORSRAM3
+    hsram3.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+#if BANK1_NORSRAM3_DATA_WIDTH == 8
+    hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+#elif BANK1_NORSRAM3_DATA_WIDTH == 16
+    hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
 #else
-    hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_32b;
+    hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_32b;
 #endif
-    hsram.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
-    hsram.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
-    hsram.FSMC_WrapMode = FSMC_WrapMode_Disable;
-    hsram.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
-    hsram.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
-    hsram.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
-    hsram.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
-    hsram.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+	FSMC_NORSRAMInit(&hsram3);
+    FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
+	
+	ExtSramInitBoardMemory((void*)(FSMC_BANK1_NORSRAM3_START_ADDRESS), (void*)((FSMC_BANK1_NORSRAM3_START_ADDRESS + BANK1_NORSRAM3_SIZE)), 2);
 
-    hsram_read.FSMC_AddressSetupTime = 1;
-    hsram_read.FSMC_AddressHoldTime = 0;
-    hsram_read.FSMC_DataSetupTime = 2;
-    hsram_read.FSMC_BusTurnAroundDuration = 0;
-    hsram_read.FSMC_CLKDivision = 0;
-    hsram_read.FSMC_DataLatency = 0;
-    hsram_read.FSMC_AccessMode = FSMC_AccessMode_A;
-
-    hsram_write.FSMC_AddressSetupTime = 1;
-    hsram_write.FSMC_AddressHoldTime = 0;
-    hsram_write.FSMC_DataSetupTime = 2;
-    hsram_write.FSMC_BusTurnAroundDuration = 0;
-    hsram_write.FSMC_CLKDivision = 0;
-    hsram_write.FSMC_DataLatency = 0;
-    hsram_write.FSMC_AccessMode = FSMC_AccessMode_A;
-
-    FSMC_NORSRAMInit(&hsram);
-
-    FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);
+#endif
 
     return 0;
 }
\ No newline at end of file
diff --git a/board/aiit-arm32-board/third_party_driver/include/extmem.h b/board/aiit-arm32-board/third_party_driver/include/connect_fsmc.h
similarity index 69%
rename from board/aiit-arm32-board/third_party_driver/include/extmem.h
rename to board/aiit-arm32-board/third_party_driver/include/connect_fsmc.h
index fe9be543c..04c41c191 100644
--- a/board/aiit-arm32-board/third_party_driver/include/extmem.h
+++ b/board/aiit-arm32-board/third_party_driver/include/connect_fsmc.h
@@ -9,20 +9,28 @@
 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
 * See the Mulan PSL v2 for more details.
 */
-
+ 
 /**
-* @file extmem.h
-* @brief support extmem function
+* @file connect_fsmc.h
+* @brief declare stm32f407zgt6-board fsmc function
 * @version 1.0 
 * @author AIIT XUOS Lab
-* @date 2021-04-25
+* @date 2021-05-28
 */
 
-#ifndef EXTMEM_H
-#define EXTMEM_H
+#ifndef CONNECT_FSMC_H
+#define CONNECT_FSMC_H
 
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  void SystemInitExtMemCtl(void); 
+#include <xsconfig.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int HwSramInit(void);
+
+#ifdef __cplusplus
+}
 #endif
 
 #endif
\ No newline at end of file
diff --git a/board/stm32f407-st-discovery/third_party_driver/Kconfig b/board/stm32f407-st-discovery/third_party_driver/Kconfig
index 43448e65a..0e31c526e 100755
--- a/board/stm32f407-st-discovery/third_party_driver/Kconfig
+++ b/board/stm32f407-st-discovery/third_party_driver/Kconfig
@@ -13,13 +13,6 @@ if BSP_USING_DMA
 source "$BSP_DIR/third_party_driver/common/Kconfig"
 endif
 
-menuconfig BSP_USING_EXTMEM
-bool "Using EXTMEM device"
-default n
-if BSP_USING_EXTMEM
-source "$BSP_DIR/third_party_driver/extmem/Kconfig"
-endif
-
 menuconfig BSP_USING_GPIO
 bool "Using GPIO device "
 default y
diff --git a/board/stm32f407-st-discovery/third_party_driver/Makefile b/board/stm32f407-st-discovery/third_party_driver/Makefile
index 3057ed771..09c9310dd 100644
--- a/board/stm32f407-st-discovery/third_party_driver/Makefile
+++ b/board/stm32f407-st-discovery/third_party_driver/Makefile
@@ -5,11 +5,6 @@ ifeq ($(CONFIG_BSP_USING_CAN),y)
   SRC_DIR += can
 endif
 
-
-ifeq ($(CONFIG_BSP_USING_EXTMEM),y)
-  SRC_DIR += extmem
-endif
-
 ifeq ($(CONFIG_BSP_USING_GPIO),y)
   SRC_DIR += gpio
 endif
diff --git a/board/stm32f407-st-discovery/third_party_driver/extmem/Kconfig b/board/stm32f407-st-discovery/third_party_driver/extmem/Kconfig
deleted file mode 100644
index e69de29bb..000000000
diff --git a/board/stm32f407-st-discovery/third_party_driver/extmem/Makefile b/board/stm32f407-st-discovery/third_party_driver/extmem/Makefile
deleted file mode 100644
index 6224e3f93..000000000
--- a/board/stm32f407-st-discovery/third_party_driver/extmem/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-SRC_FILES := extmem.c
-
-include $(KERNEL_ROOT)/compiler.mk
diff --git a/board/stm32f407-st-discovery/third_party_driver/extmem/extmem.c b/board/stm32f407-st-discovery/third_party_driver/extmem/extmem.c
deleted file mode 100644
index 9f7bc63f8..000000000
--- a/board/stm32f407-st-discovery/third_party_driver/extmem/extmem.c
+++ /dev/null
@@ -1,336 +0,0 @@
-/*
-* Copyright (c) 2020 AIIT XUOS Lab
-* XiUOS is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*        http://license.coscl.org.cn/MulanPSL2
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-* See the Mulan PSL v2 for more details.
-*/
-
-/**
-* @file extmem.c
-* @brief support extmem function
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2021-04-25
-*/
-
-#include "stm32f4xx.h"
-#include "extmem.h"
-
-#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)
-void SystemInitExtMemCtl(void)
-{
-  __IO uint32_t tmp = 0x00;
-
-  register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register __IO uint32_t index;
-
-  RCC->AHB1ENR |= 0x000001F8;
-
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
-  
-  GPIOD->AFR[0]  = 0x00CCC0CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  GPIOD->MODER   = 0xAAAA0A8A;
-  GPIOD->OSPEEDR = 0xFFFF0FCF;
-  GPIOD->OTYPER  = 0x00000000;
-  GPIOD->PUPDR   = 0x00000000;
-
-  GPIOE->AFR[0]  = 0xC00CC0CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  GPIOE->MODER   = 0xAAAA828A;
-  GPIOE->OSPEEDR = 0xFFFFC3CF;
-  GPIOE->OTYPER  = 0x00000000;
-  GPIOE->PUPDR   = 0x00000000;
-  
-  GPIOF->AFR[0]  = 0xCCCCCCCC;
-  GPIOF->AFR[1]  = 0xCCCCCCCC;
-  GPIOF->MODER   = 0xAA800AAA;
-  GPIOF->OSPEEDR = 0xAA800AAA;
-  GPIOF->OTYPER  = 0x00000000;
-  GPIOF->PUPDR   = 0x00000000;
-
-  GPIOG->AFR[0]  = 0xCCCCCCCC;
-  GPIOG->AFR[1]  = 0xCCCCCCCC;
-  GPIOG->MODER   = 0xAAAAAAAA;
-  GPIOG->OSPEEDR = 0xAAAAAAAA;
-  GPIOG->OTYPER  = 0x00000000;
-  GPIOG->PUPDR   = 0x00000000;
-  
-  GPIOH->AFR[0]  = 0x00C0CC00;
-  GPIOH->AFR[1]  = 0xCCCCCCCC;
-  GPIOH->MODER   = 0xAAAA08A0;
-  GPIOH->OSPEEDR = 0xAAAA08A0;
-  GPIOH->OTYPER  = 0x00000000;
-  GPIOH->PUPDR   = 0x00000000;
-
-  GPIOI->AFR[0]  = 0xCCCCCCCC;
-  GPIOI->AFR[1]  = 0x00000CC0;
-  GPIOI->MODER   = 0x0028AAAA;
-  GPIOI->OSPEEDR = 0x0028AAAA;
-  GPIOI->OTYPER  = 0x00000000;
-  GPIOI->PUPDR   = 0x00000000;
-  
-  RCC->AHB3ENR |= 0x00000001;
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  FMC_Bank5_6->SDCR[0] = 0x000019E4;
-  FMC_Bank5_6->SDTR[0] = 0x01115351;      
-  
-  FMC_Bank5_6->SDCMR = 0x00000011; 
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-
-  for (index = 0; index<1000; index++);
-  
-  FMC_Bank5_6->SDCMR = 0x00000012;           
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-  
-  FMC_Bank5_6->SDCMR = 0x00000073;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
- 
-  FMC_Bank5_6->SDCMR = 0x00046014;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  } 
-  
-  tmpreg = FMC_Bank5_6->SDRTR;
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
-  
-  tmpreg = FMC_Bank5_6->SDCR[0]; 
-  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-  FMC_Bank1->BTCR[2]  = 0x00001011;
-  FMC_Bank1->BTCR[3]  = 0x00000201;
-  FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif
-#if defined(STM32F469xx) || defined(STM32F479xx)
-  FMC_Bank1->BTCR[2]  = 0x00001091;
-  FMC_Bank1->BTCR[3]  = 0x00110212;
-  FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif
-
-  (void)(tmp); 
-}
-#endif
-#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-void SystemInitExtMemCtl(void)
-{
-  __IO uint32_t tmp = 0x00;
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#if defined (DATA_IN_ExtSDRAM)
-  register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register __IO uint32_t index;
-
-#if defined(STM32F446xx)
-  RCC->AHB1ENR |= 0x0000007D;
-#else
-  RCC->AHB1ENR |= 0x000001F8;
-#endif
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
-  
-#if defined(STM32F446xx)
-  GPIOA->AFR[0]  |= 0xC0000000;
-  GPIOA->AFR[1]  |= 0x00000000;
-  GPIOA->MODER   |= 0x00008000;
-  GPIOA->OSPEEDR |= 0x00008000;
-  GPIOA->OTYPER  |= 0x00000000;
-  GPIOA->PUPDR   |= 0x00000000;
-
-  GPIOC->AFR[0]  |= 0x00CC0000;
-  GPIOC->AFR[1]  |= 0x00000000;
-  GPIOC->MODER   |= 0x00000A00;
-  GPIOC->OSPEEDR |= 0x00000A00;
-  GPIOC->OTYPER  |= 0x00000000;
-  GPIOC->PUPDR   |= 0x00000000;
-#endif
-
-  GPIOD->AFR[0]  = 0x000000CC;
-  GPIOD->AFR[1]  = 0xCC000CCC;
-  GPIOD->MODER   = 0xA02A000A;
-  GPIOD->OSPEEDR = 0xA02A000A;
-  GPIOD->OTYPER  = 0x00000000;
-  GPIOD->PUPDR   = 0x00000000;
-
-  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  GPIOE->MODER   = 0xAAAA800A;
-  GPIOE->OSPEEDR = 0xAAAA800A;
-  GPIOE->OTYPER  = 0x00000000;
-  GPIOE->PUPDR   = 0x00000000;
-
-  GPIOF->AFR[0]  = 0xCCCCCCCC;
-  GPIOF->AFR[1]  = 0xCCCCCCCC;
-  GPIOF->MODER   = 0xAA800AAA;
-  GPIOF->OSPEEDR = 0xAA800AAA;
-  GPIOF->OTYPER  = 0x00000000;
-  GPIOF->PUPDR   = 0x00000000;
-
-  GPIOG->AFR[0]  = 0xCCCCCCCC;
-  GPIOG->AFR[1]  = 0xCCCCCCCC;
-  GPIOG->MODER   = 0xAAAAAAAA;
-  GPIOG->OSPEEDR = 0xAAAAAAAA;
-  GPIOG->OTYPER  = 0x00000000;
-  GPIOG->PUPDR   = 0x00000000;
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx)  
-  GPIOH->AFR[0]  = 0x00C0CC00;
-  GPIOH->AFR[1]  = 0xCCCCCCCC;
-  GPIOH->MODER   = 0xAAAA08A0;
-  GPIOH->OSPEEDR = 0xAAAA08A0;
-  GPIOH->OTYPER  = 0x00000000;
-  GPIOH->PUPDR   = 0x00000000;
-  
-  GPIOI->AFR[0]  = 0xCCCCCCCC;
-  GPIOI->AFR[1]  = 0x00000CC0;
-  GPIOI->MODER   = 0x0028AAAA;
-  GPIOI->OSPEEDR = 0x0028AAAA;
-  GPIOI->OTYPER  = 0x00000000;
-  GPIOI->PUPDR   = 0x00000000;
-#endif
-  
-  RCC->AHB3ENR |= 0x00000001;
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-#if defined(STM32F446xx)
-  FMC_Bank5_6->SDCR[0] = 0x00001954;
-#else  
-  FMC_Bank5_6->SDCR[0] = 0x000019E4;
-#endif
-  FMC_Bank5_6->SDTR[0] = 0x01115351;      
-  
-  FMC_Bank5_6->SDCMR = 0x00000011; 
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-
-  for (index = 0; index<1000; index++);
-  
-  FMC_Bank5_6->SDCMR = 0x00000012;           
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
-  
-#if defined(STM32F446xx)
-  FMC_Bank5_6->SDCMR = 0x000000F3;
-#else  
-  FMC_Bank5_6->SDCMR = 0x00000073;
-#endif
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  }
- 
-#if defined(STM32F446xx)
-  FMC_Bank5_6->SDCMR = 0x00044014;
-#else  
-  FMC_Bank5_6->SDCMR = 0x00046014;
-#endif
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
-  } 
-  
-  tmpreg = FMC_Bank5_6->SDRTR;
-#if defined(STM32F446xx)
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
-#else    
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
-#endif
-  
-  tmpreg = FMC_Bank5_6->SDCR[0]; 
-  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-#endif
-#endif
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
- || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
- || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
-
-#if defined(DATA_IN_ExtSRAM)
-  RCC->AHB1ENR   |= 0x00000078;
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
-  
-  GPIOD->AFR[0]  = 0x00CCC0CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  GPIOD->MODER   = 0xAAAA0A8A;
-  GPIOD->OSPEEDR = 0xFFFF0FCF;
-  GPIOD->OTYPER  = 0x00000000;
-  GPIOD->PUPDR   = 0x00000000;
-
-  GPIOE->AFR[0]  = 0xC00CC0CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  GPIOE->MODER   = 0xAAAA828A;
-  GPIOE->OSPEEDR = 0xFFFFC3CF;
-  GPIOE->OTYPER  = 0x00000000;
-  GPIOE->PUPDR   = 0x00000000;
-
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  GPIOF->MODER   = 0xAA000AAA;
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  GPIOF->OTYPER  = 0x00000000;
-  GPIOF->PUPDR   = 0x00000000;
-
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x000000C0;
-  GPIOG->MODER   = 0x00085AAA;
-  GPIOG->OSPEEDR = 0x000CAFFF;
-  GPIOG->OTYPER  = 0x00000000;
-  GPIOG->PUPDR   = 0x00000000;
-  
-  RCC->AHB3ENR         |= 0x00000001;
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-  FMC_Bank1->BTCR[2]  = 0x00001011;
-  FMC_Bank1->BTCR[3]  = 0x00000201;
-  FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif
-#if defined(STM32F469xx) || defined(STM32F479xx)
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-  FMC_Bank1->BTCR[2]  = 0x00001091;
-  FMC_Bank1->BTCR[3]  = 0x00110212;
-  FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
-   || defined(STM32F412Zx) || defined(STM32F412Vx)
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
-  FSMC_Bank1->BTCR[2]  = 0x00001011;
-  FSMC_Bank1->BTCR[3]  = 0x00000201;
-  FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif
-
-#endif
-#endif
-  (void)(tmp); 
-}
-#endif
\ No newline at end of file
diff --git a/board/stm32f407-st-discovery/third_party_driver/include/extmem.h b/board/stm32f407-st-discovery/third_party_driver/include/extmem.h
deleted file mode 100644
index 00a20ce38..000000000
--- a/board/stm32f407-st-discovery/third_party_driver/include/extmem.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
-* Copyright (c) 2020 AIIT XUOS Lab
-* xiuOS is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*        http://license.coscl.org.cn/MulanPSL2
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-* See the Mulan PSL v2 for more details.
-*/
-
-/**
-* @file extmem.h
-* @brief support extmem function
-* @version 1.0 
-* @author AIIT XUOS Lab
-* @date 2021-04-25
-*/
-
-#ifndef EXTMEM_H
-#define EXTMEM_H
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  void SystemInitExtMemCtl(void); 
-#endif
-
-#endif
\ No newline at end of file
diff --git a/board/stm32f407zgt6/board.c b/board/stm32f407zgt6/board.c
index c672d8243..095ac58fa 100644
--- a/board/stm32f407zgt6/board.c
+++ b/board/stm32f407zgt6/board.c
@@ -35,6 +35,7 @@ Modification:
 #include "board.h"
 #include "connect_usart.h"
 #include "connect_gpio.h"
+#include "connect_fsmc.h"
 #include "misc.h"
 
 extern void entry(void);
@@ -104,6 +105,9 @@ struct InitSequenceDesc _board_init[] =
 {
 #ifdef BSP_USING_GPIO	
     { "hw pin", Stm32HwGpioInit },
+#endif
+#ifdef BSP_USING_EXTMEM
+    { "hw extern sram", HwSramInit },
 #endif
 	{ " NONE ",NONE },
 };
@@ -126,13 +130,6 @@ void InitBoardHardware()
     KPrintf("\nconsole init completed.\n");
     KPrintf("board initialization......\n");
 #endif
-
-#ifdef BSP_USING_EXTMEM
-    extern int HwSramInit(void);
-    HwSramInit();
-#endif
-
-    // InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
     
 #ifdef SEPARATE_COMPILE
 
diff --git a/board/stm32f407zgt6/third_party_driver/Kconfig b/board/stm32f407zgt6/third_party_driver/Kconfig
index 68c67ca19..b83f2ddee 100755
--- a/board/stm32f407zgt6/third_party_driver/Kconfig
+++ b/board/stm32f407zgt6/third_party_driver/Kconfig
@@ -18,6 +18,7 @@ endif
 menuconfig BSP_USING_EXTMEM
 bool "Using extern memory"
 default n
+select MEM_EXTERN_SRAM
 if BSP_USING_EXTMEM
 source "$BSP_DIR/third_party_driver/extmem/Kconfig"
 endif
diff --git a/board/stm32f407zgt6/third_party_driver/extmem/Kconfig b/board/stm32f407zgt6/third_party_driver/extmem/Kconfig
index 4b663fc9f..27186cb7c 100644
--- a/board/stm32f407zgt6/third_party_driver/extmem/Kconfig
+++ b/board/stm32f407zgt6/third_party_driver/extmem/Kconfig
@@ -2,30 +2,6 @@ if  BSP_USING_EXTMEM
     config EXTSRAM_MAX_NUM
         int
         default 4
-
-    config BSP_USING_FSMC_BANK1_NORSRAM1
-        bool "config fsmc bank1 sram1"
-        default n
-        if BSP_USING_FSMC_BANK1_NORSRAM1
-            config BANK1_NORSRAM1_SIZE
-                hex "config sram1 chip size"
-                default 0x100000
-            config BANK1_NORSRAM1_DATA_WIDTH
-                int "config sram1 chip data width"
-                default 16 
-        endif
-
-    config BSP_USING_FSMC_BANK1_NORSRAM2
-        bool "config fsmc bank1 sram2"
-        default n
-        if BSP_USING_FSMC_BANK1_NORSRAM2
-            config BANK1_NORSRAM2_SIZE
-                hex "config sram2 chip size"
-                default 0x100000
-            config BANK1_NORSRAM2_DATA_WIDTH
-                int "config sram2 chip data width"
-                default 16 
-        endif
         
     config BSP_USING_FSMC_BANK1_NORSRAM3
         bool "config fsmc bank1 sram3"
@@ -38,16 +14,4 @@ if  BSP_USING_EXTMEM
                 int "config sram3 chip data width"
                 default 16 
         endif
-
-    config BSP_USING_FSMC_BANK1_NORSRAM4
-        bool "config fsmc bank1 sram4"
-        default n
-        if BSP_USING_FSMC_BANK1_NORSRAM4
-            config BANK1_NORSRAM4_SIZE
-                hex "config sram4 chip size"
-                default 0x100000
-            config BANK1_NORSRAM4_DATA_WIDTH
-                int "config sram4 chip data width"
-                default 16 
-        endif
 endif
diff --git a/board/stm32f407zgt6/third_party_driver/extmem/connect_fsmc.c b/board/stm32f407zgt6/third_party_driver/extmem/connect_fsmc.c
index cbfce3c0c..74313937c 100644
--- a/board/stm32f407zgt6/third_party_driver/extmem/connect_fsmc.c
+++ b/board/stm32f407zgt6/third_party_driver/extmem/connect_fsmc.c
@@ -18,17 +18,20 @@
 * @date 2021-05-28
 */
 
-#include <xs_base.h>
 #include "connect_fsmc.h"
 #include "hardware_fsmc.h"
 #include "hardware_gpio.h"
 #include "hardware_rcc.h"
-#include "cmsis_gcc.h"
 #include <string.h>
+#include <xs_base.h>
 
-static FSMC_NORSRAMInitTypeDef hsram;
-static FSMC_NORSRAMTimingInitTypeDef hsram_read;
-static FSMC_NORSRAMTimingInitTypeDef hsram_write;
+#define FSMC_BANK1_NORSRAM3_START_ADDRESS 0x68000000
+
+static FSMC_NORSRAMInitTypeDef hsram3;
+static FSMC_NORSRAMTimingInitTypeDef hsram_read3;
+static FSMC_NORSRAMTimingInitTypeDef hsram_write3;
+
+extern void ExtSramInitBoardMemory(void *start_phy_address, void *end_phy_address, uint8 extsram_idx);
 
 int HwSramInit(void)
 {
@@ -108,100 +111,51 @@ int HwSramInit(void)
 	GPIO_PinAFConfig(GPIOG,GPIO_PinSource10,GPIO_AF_FSMC);
 	GPIO_PinAFConfig(GPIOG,GPIO_PinSource12,GPIO_AF_FSMC);
 
-	hsram.FSMC_ReadWriteTimingStruct = &hsram_read;
-	hsram.FSMC_WriteTimingStruct = &hsram_write;
+	hsram3.FSMC_ReadWriteTimingStruct = &hsram_read3;
+	hsram3.FSMC_WriteTimingStruct = &hsram_write3;
 
-    /* hsram.Init */
-    hsram.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
-    hsram.FSMC_MemoryType = FSMC_MemoryType_SRAM;
-    hsram.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
-    hsram.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
-    hsram.FSMC_WrapMode = FSMC_WrapMode_Disable;
-    hsram.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
-    hsram.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
-    hsram.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
-    hsram.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
-    hsram.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+    /* hsram3.Init */
+    hsram3.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+    hsram3.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+    hsram3.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+    hsram3.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+    hsram3.FSMC_WrapMode = FSMC_WrapMode_Disable;
+    hsram3.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+    hsram3.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+    hsram3.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+    hsram3.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+    hsram3.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
 
-    hsram_read.FSMC_AddressSetupTime = 0;
-    hsram_read.FSMC_AddressHoldTime = 0;
-    hsram_read.FSMC_DataSetupTime = 8;
-    hsram_read.FSMC_BusTurnAroundDuration = 0;
-    hsram_read.FSMC_CLKDivision = 0;
-    hsram_read.FSMC_DataLatency = 0;
-    hsram_read.FSMC_AccessMode = FSMC_AccessMode_A;
+    hsram_read3.FSMC_AddressSetupTime = 0;
+    hsram_read3.FSMC_AddressHoldTime = 0;
+    hsram_read3.FSMC_DataSetupTime = 8;
+    hsram_read3.FSMC_BusTurnAroundDuration = 0;
+    hsram_read3.FSMC_CLKDivision = 0;
+    hsram_read3.FSMC_DataLatency = 0;
+    hsram_read3.FSMC_AccessMode = FSMC_AccessMode_A;
 
-    hsram_write.FSMC_AddressSetupTime = 0;
-    hsram_write.FSMC_AddressHoldTime = 0;
-    hsram_write.FSMC_DataSetupTime = 8;
-    hsram_write.FSMC_BusTurnAroundDuration = 0;
-    hsram_write.FSMC_CLKDivision = 0;
-    hsram_write.FSMC_DataLatency = 0;
-    hsram_write.FSMC_AccessMode = FSMC_AccessMode_A;
-
-#ifdef BSP_USING_FSMC_BANK1_NORSRAM1
-    hsram.FSMC_Bank = FSMC_Bank1_NORSRAM1;
-#if BANK1_NORSRAM1_DATA_WIDTH == 8
-    hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
-#elif BANK1_NORSRAM1_DATA_WIDTH == 16
-    hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
-#else
-    hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_32b;
-#endif
-	FSMC_NORSRAMInit(&hsram);
-    FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);
-#endif
-
-#ifdef BSP_USING_FSMC_BANK1_NORSRAM2
-    hsram.FSMC_Bank = FSMC_Bank1_NORSRAM2;
-#if BANK1_NORSRAM2_DATA_WIDTH == 8
-    hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
-#elif BANK1_NORSRAM2_DATA_WIDTH == 16
-    hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
-#else
-    hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_32b;
-#endif
-	FSMC_NORSRAMInit(&hsram);
-    FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
-#endif
+    hsram_write3.FSMC_AddressSetupTime = 0;
+    hsram_write3.FSMC_AddressHoldTime = 0;
+    hsram_write3.FSMC_DataSetupTime = 8;
+    hsram_write3.FSMC_BusTurnAroundDuration = 0;
+    hsram_write3.FSMC_CLKDivision = 0;
+    hsram_write3.FSMC_DataLatency = 0;
+    hsram_write3.FSMC_AccessMode = FSMC_AccessMode_A;
 
 #ifdef BSP_USING_FSMC_BANK1_NORSRAM3
-    hsram.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+    hsram3.FSMC_Bank = FSMC_Bank1_NORSRAM3;
 #if BANK1_NORSRAM3_DATA_WIDTH == 8
-    hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+    hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
 #elif BANK1_NORSRAM3_DATA_WIDTH == 16
-    hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+    hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
 #else
-    hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_32b;
+    hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_32b;
 #endif
-	FSMC_NORSRAMInit(&hsram);
+	FSMC_NORSRAMInit(&hsram3);
     FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
-
 	
+	ExtSramInitBoardMemory((void*)(FSMC_BANK1_NORSRAM3_START_ADDRESS), (void*)((FSMC_BANK1_NORSRAM3_START_ADDRESS + BANK1_NORSRAM3_SIZE)), 2);
 
-	extern void ExtSramInitBoardMemory(void *start_phy_address, void *end_phy_address, uint8 extsram_idx);
-	#define START_ADDRESS 0x68000000
-
-	memset((void*)START_ADDRESS,0,BANK1_NORSRAM3_SIZE);
-	__DSB();
-//     __ISB();
-	__DMB();
-
-	ExtSramInitBoardMemory((void*)(START_ADDRESS), (void*)((START_ADDRESS + BANK1_NORSRAM3_SIZE)), 2);
-
-#endif
-
-#ifdef BSP_USING_FSMC_BANK1_NORSRAM4
-    hsram.FSMC_Bank = FSMC_Bank1_NORSRAM4;
-#if BANK1_NORSRAM4_DATA_WIDTH == 8
-    hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
-#elif BANK1_NORSRAM4_DATA_WIDTH == 16
-    hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
-#else
-    hsram.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_32b;
-#endif
-	FSMC_NORSRAMInit(&hsram);
-    FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);
 #endif
 
     return 0;
diff --git a/kernel/Kconfig b/kernel/Kconfig
index 4ffbacbe2..6ad0f72d0 100644
--- a/kernel/Kconfig
+++ b/kernel/Kconfig
@@ -37,6 +37,10 @@ menu "Kernel feature"
             help
                 Alignment size for CPU architecture data access
 
+        config MEM_EXTERN_SRAM
+            bool "Using extern memory"
+            default n
+
         config MM_PAGE_SIZE
             int "Config memory page size"
             default 4096
diff --git a/kernel/include/xs_memory.h b/kernel/include/xs_memory.h
index ad404cdb5..0d9c9f958 100644
--- a/kernel/include/xs_memory.h
+++ b/kernel/include/xs_memory.h
@@ -85,7 +85,7 @@ void FreeBlockMemGather(void *data_block);
 #endif
 
 void InitBoardMemory(void *begin_addr, void *end_addr);
-#ifdef DATA_IN_ExtSRAM
+#ifdef MEM_EXTERN_SRAM
 void ExtSramInitBoardMemory(void *start_phy_address, void *end_phy_address, uint8 extsram_idx);
 #endif
 void *x_malloc(x_size_t nbytes);
diff --git a/kernel/memory/byte_manage.c b/kernel/memory/byte_manage.c
index ce1e21aad..82e3ba9bb 100644
--- a/kernel/memory/byte_manage.c
+++ b/kernel/memory/byte_manage.c
@@ -22,8 +22,6 @@
 #include <xiuos.h>
 #include <string.h>
 
-#define DATA_IN_ExtSRAM
-
 #define MEM_STATS
 
 /* Covert pointer to other structure */
@@ -167,7 +165,7 @@ static struct ByteMemory ByteManager;
 static struct ByteMemory UserByteManager;
 #endif
 
-#ifdef DATA_IN_ExtSRAM
+#ifdef MEM_EXTERN_SRAM
 static struct ByteMemory ExtByteManager[EXTSRAM_MAX_NUM] = {0};
 #endif
 /**
@@ -393,7 +391,7 @@ static void* BigMemMalloc(struct DynamicBuddyMemory *dynamic_buddy, x_size_t siz
 
 	/* failure allocation */
 	if(result == NONE) {
-#ifndef DATA_IN_ExtSRAM
+#ifndef MEM_EXTERN_SRAM
 	    KPrintf("%s: allocation failed, size %d.\n", __func__,allocsize);
 #endif
         return result;
@@ -600,7 +598,7 @@ static void *SmallMemMalloc(struct ByteMemory *byte_memory, x_size_t size)
 
 	/* the static memory block is exhausted, now turn to dynamic buddy memory for allocation. */
     result = byte_memory->dynamic_buddy_manager.done->malloc(&byte_memory->dynamic_buddy_manager, size, DYNAMIC_BLOCK_NO_EXTMEM_MASK);
-#ifdef DATA_IN_ExtSRAM
+#ifdef MEM_EXTERN_SRAM
 	if(NONE == result) {
 		for(i = 0; i < EXTSRAM_MAX_NUM; i++) {
 			if(NONE != ExtByteManager[i].done) {
@@ -637,7 +635,7 @@ void *x_malloc(x_size_t size)
 
 	 /* parameter detection */
 
-#ifdef DATA_IN_ExtSRAM
+#ifdef MEM_EXTERN_SRAM
 		/* parameter detection */
 	if(size == 0 ){
 		 return NONE;
@@ -671,7 +669,7 @@ void *x_malloc(x_size_t size)
 		if(ret != NONE)
         	CHECK(ByteManager.dynamic_buddy_manager.done->JudgeLegal(&ByteManager.dynamic_buddy_manager, ret - SIZEOF_DYNAMICALLOCNODE_MEM));
 try_extmem:
-#ifdef DATA_IN_ExtSRAM
+#ifdef MEM_EXTERN_SRAM
 		if(NONE == ret) {
 			for(i = 0; i < EXTSRAM_MAX_NUM; i++) {
 				if(NONE != ExtByteManager[i].done) {
@@ -798,7 +796,7 @@ void x_free(void *pointer)
 	} else
 #endif
 	{
-#ifdef DATA_IN_ExtSRAM
+#ifdef MEM_EXTERN_SRAM
 	/* judge the pointer is not malloced from extern memory*/
 	if(0 == (node->flag & 0xFF0000)) {
 		ByteManager.dynamic_buddy_manager.done->release(&ByteManager,pointer);
@@ -816,7 +814,7 @@ void x_free(void *pointer)
 	CriticalAreaUnLock(lock);
 }
 
-#ifdef DATA_IN_ExtSRAM
+#ifdef MEM_EXTERN_SRAM
 /**
  * This function initializes the dynamic buddy memory of extern sram.
  *