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change xidatong to xidatong-arm32 on nuttx 10.3.0

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This commit is contained in:
wgzAIIT
2022-06-22 16:35:39 +08:00
parent cac43f78bf
commit 1d1d394125
65 changed files with 146 additions and 146 deletions
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Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/Makefile
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############################################################################
# boards/arm/imxrt/xidatong-arm32/src/Makefile
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include $(TOPDIR)/Make.defs
CSRCS = imxrt_boot.c imxrt_flexspi_nor_boot.c imxrt_flexspi_nor_flash.c
ifeq ($(CONFIG_IMXRT_SDRAMC),y)
CSRCS += imxrt_sdram.c
endif
ifeq ($(CONFIG_BOARDCTL),y)
CSRCS += imxrt_appinit.c imxrt_bringup.c
else ifeq ($(CONFIG_BOARD_LATE_INITIALIZE),y)
CSRCS += imxrt_bringup.c
endif
ifeq ($(CONFIG_BOARDCTL_RESET),y)
CSRCS += imxrt_reset.c
endif
ifeq ($(CONFIG_ARCH_LEDS),y)
CSRCS += imxrt_autoleds.c
else
CSRCS += imxrt_userleds.c
endif
ifeq ($(CONFIG_ARCH_BUTTONS),y)
CSRCS += imxrt_buttons.c
endif
ifeq ($(CONFIG_IMXRT_ENET),y)
CSRCS += imxrt_ethernet.c
endif
ifeq ($(CONFIG_IMXRT_LPSPI),y)
CSRCS += imxrt_spi.c
endif
ifeq ($(CONFIG_IMXRT_LCD),y)
CSRCS += imxrt_lcd.c
endif
ifeq ($(CONFIG_MMCSD_SPI),y)
CSRCS += imxrt_mmcsd_spi.c
endif
ifeq ($(CONFIG_DEV_GPIO),y)
CSRCS += imxrt_gpio.c
endif
ifeq ($(CONFIG_XIDATONG_ARM32_SDRAM),y)
CSRCS += imxrt_sdram_ini_dcd.c
endif
ifeq ($(CONFIG_USBHOST),y)
CSRCS += imxrt_usbhost.c
endif
ifeq ($(CONFIG_IMXRT_USDHC),y)
CSRCS += imxrt_mmcsd.c
endif
ifeq ($(CONFIG_XIDATONG_ARM32_SDIO_AUTOMOUNT),y)
CSRCS += imxrt_mmcsd_automount.c
endif
ifeq ($(CONFIG_INPUT_GT9XX),y)
CSRCS += imxrt_gt9xx.c
endif
ifeq ($(CONFIG_BSP_USING_CH438),y)
CSRCS += imxrt_ch438.c ch438_demo.c
endif
include $(TOPDIR)/boards/Board.mk
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/ch438_demo.c
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file ch438_demo.c
* @brief imxrt board sd card automount
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.04.26
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include "imxrt_ch438.h"
#include <sys/ioctl.h>
#include <nuttx/ioexpander/gpio.h>
void CH438Demo(void)
{
int fd,m0fd,m1fd;
int i;
char sendbuffer1[4] = {0xC0,0x04,0x01,0x09};
char sendbuffer2[6] = {0xC0,0x00,0x03,0x12,0x34,0x61};
char sendbuffer3[3] = {0xC1,0x04,0x01};
char sendbuffer4[3] = {0xC1,0x00,0x03};
char buffer[256];
int readlen;
fd = open("/dev/extuart_dev3", O_RDWR);
ioctl(fd, OPE_INT, (unsigned long)9600);
m0fd = open("/dev/gpout0", O_RDWR);
m1fd = open("/dev/gpout1", O_RDWR);
ioctl(m0fd, GPIOC_WRITE, (unsigned long)1);
ioctl(m1fd, GPIOC_WRITE, (unsigned long)1);
sleep(1);
write(fd, sendbuffer1,4);
sleep(1);
readlen = read(fd, buffer, 256);
printf("readlen1 = %d\n", readlen);
for(i = 0;i< readlen; ++i)
{
printf("0x%x\n", buffer[i]);
}
write(fd, sendbuffer2,6);
sleep(1);
readlen = read(fd, buffer, 256);
printf("readlen1 = %d\n", readlen);
for(i = 0;i< readlen; ++i)
{
printf("0x%x\n", buffer[i]);
}
write(fd, sendbuffer3,3);
sleep(1);
readlen = read(fd, buffer, 256);
printf("readlen1 = %d\n", readlen);
for(i = 0;i< readlen; ++i)
{
printf("0x%x\n", buffer[i]);
}
write(fd, sendbuffer4,3);
sleep(1);
readlen = read(fd, buffer, 256);
printf("readlen1 = %d\n", readlen);
for(i = 0;i< readlen; ++i)
{
printf("0x%x\n", buffer[i]);
}
close(fd);
}
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_appinit.c
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/****************************************************************************
* boards/arm/imxrt/xidatong-arm32/src/imxrt_appinit.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file imxrt_appinit.c
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-23
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <nuttx/board.h>
#include "xidatong-arm32.h"
#ifdef CONFIG_BOARDCTL
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_app_initialize
*
* Description:
* Perform application specific initialization. This function is never
* called directly from application code, but only indirectly via the
* (non-standard) boardctl() interface using the command BOARDIOC_INIT.
*
* Input Parameters:
* arg - The boardctl() argument is passed to the board_app_initialize()
* implementation without modification. The argument has no
* meaning to NuttX; the meaning of the argument is a contract
* between the board-specific initialization logic and the
* matching application logic. The value could be such things as a
* mode enumeration value, a set of DIP switch switch settings, a
* pointer to configuration data read from a file or serial FLASH,
* or whatever you would like to do with it. Every implementation
* should accept zero/NULL as a default configuration.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure to indicate the nature of the failure.
*
****************************************************************************/
int board_app_initialize(uintptr_t arg)
{
#ifndef CONFIG_BOARD_LATE_INITIALIZE
/* Perform board initialization */
return imxrt_bringup();
#else
return OK;
#endif
}
#endif /* CONFIG_BOARDCTL */
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_autoleds.c
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/****************************************************************************
* boards/arm/imxrt/xidatong-arm32/src/imxrt_autoleds.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file imxrt_autoleds.c
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-23
*/
/* There are four LED status indicators located on the EVK Board. The
* functions of these LEDs include:
*
* - Main Power Supply(D3)
* Green: DC 5V main supply is normal.
* Red: J2 input voltage is over 5.6V.
* Off: The board is not powered.
* - Reset RED LED(D15)
* - OpenSDA LED(D16)
* - USER LED(D18)
*
* Only a single LED, D18, is under software control.
*
* This LED is not used by the board port unless CONFIG_ARCH_LEDS is
* defined. In that case, the usage by the board port is defined in
* include/board.h and src/imxrt_autoleds.c. The LED is used to encode
* OS-related events as follows:
*
* -------------------- ----------------------- ------
* SYMBOL Meaning LED
* -------------------- ----------------------- ------
*
* LED_STARTED 0 NuttX has been started OFF
* LED_HEAPALLOCATE 0 Heap has been allocated OFF
* LED_IRQSENABLED 0 Interrupts enabled OFF
* LED_STACKCREATED 1 Idle stack created ON
* LED_INIRQ 2 In an interrupt N/C
* LED_SIGNAL 2 In a signal handler N/C
* LED_ASSERTION 2 An assertion failed N/C
* LED_PANIC 3 The system has crashed FLASH
* LED_IDLE Not used
*
* Thus if the LED is statically on, NuttX has successfully booted and is,
* apparently, running normally. If the LED is flashing at approximately
* 2Hz, then a fatal error has been detected and the system has halted.
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/board.h>
#include "imxrt_gpio.h"
#include "imxrt_iomuxc.h"
#include "xidatong-arm32.h"
#include <arch/board/board.h>
#ifdef CONFIG_ARCH_LEDS
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_autoled_initialize
*
* Description:
* Initialize NuttX-controlled LED logic
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void imxrt_autoled_initialize(void)
{
/* Configure LED GPIO for output */
imxrt_config_gpio(GPIO_LED);
}
/****************************************************************************
* Name: board_autoled_on
*
* Description:
* Turn on the "logical" LED state
*
* Input Parameters:
* led - Identifies the "logical" LED state (see definitions in
* include/board.h)
*
* Returned Value:
* None
*
****************************************************************************/
void board_autoled_on(int led)
{
bool ledoff = false;
switch (led)
{
case 0: /* LED Off */
ledoff = true;
break;
case 2: /* LED No change */
return;
case 1: /* LED On */
case 3: /* LED On */
break;
}
imxrt_gpio_write(GPIO_LED, ledoff); /* Low illuminates */
}
/****************************************************************************
* Name: board_autoled_off
*
* Description:
* Turn off the "logical" LED state
*
* Input Parameters:
* led - Identifies the "logical" LED state (see definitions in
* include/board.h)
*
* Returned Value:
* None
*
****************************************************************************/
void board_autoled_off(int led)
{
switch (led)
{
case 0: /* LED Off */
case 1: /* LED Off */
case 3: /* LED Off */
break;
case 2: /* LED No change */
return;
}
imxrt_gpio_write(GPIO_LED, true); /* Low illuminates */
}
#endif /* CONFIG_ARCH_LEDS */
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_boot.c
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/****************************************************************************
* boards/arm/imxrt/xidatong-arm32/src/imxrt_boot.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file imxrt_boot.c
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-23
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "imxrt_start.h"
#include "xidatong-arm32.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_boardinitialize
*
* Description:
* All i.MX RT architectures must provide the following entry point. This
* entry point is called early in the initialization -- after clocking and
* memory have been configured but before caches have been enabled and
* before any devices have been initialized.
*
****************************************************************************/
void imxrt_boardinitialize(void)
{
/* Configure on-board LEDs if LED support has been selected. */
#ifdef CONFIG_ARCH_LEDS
imxrt_autoled_initialize();
#endif
}
/****************************************************************************
* Name: board_late_initialize
*
* Description:
* If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
* initialization call will be performed in the boot-up sequence to a
* function called board_late_initialize(). board_late_initialize() will be
* called immediately after up_intitialize() is called and just before the
* initial application is started. This additional initialization phase
* may be used, for example, to initialize board-specific device drivers.
*
****************************************************************************/
#ifdef CONFIG_BOARD_LATE_INITIALIZE
void board_late_initialize(void)
{
/* Perform board initialization */
imxrt_bringup();
}
#endif /* CONFIG_BOARD_LATE_INITIALIZE */
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_bringup.c
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/****************************************************************************
* boards/arm/imxrt/xidatong-arm32/src/imxrt_bringup.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file imxrt_bringup.c
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-23
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <debug.h>
#include <syslog.h>
#include <nuttx/fs/fs.h>
#include <nuttx/i2c/i2c_master.h>
#include <nuttx/video/fb.h>
#include <imxrt_lpi2c.h>
#include <imxrt_lpspi.h>
#ifdef CONFIG_USBMONITOR
# include <nuttx/usb/usbmonitor.h>
#endif
#ifdef CONFIG_BSP_USING_CH438
# include "imxrt_ch438.h"
#endif
#ifdef CONFIG_INPUT_GT9XX
#include "imxrt_gt9xx.h"
#endif
#include "xidatong-arm32.h"
#include <arch/board/board.h> /* Must always be included last */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Checking needed by MMC/SDCard */
#ifdef CONFIG_NSH_MMCSDMINOR
# define MMCSD_MINOR CONFIG_NSH_MMCSDMINOR
#else
# define MMCSD_MINOR 0
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
#if defined(CONFIG_I2C_DRIVER) && defined(CONFIG_IMXRT_LPI2C)
static void imxrt_i2c_register(int bus)
{
FAR struct i2c_master_s *i2c;
int ret;
i2c = imxrt_i2cbus_initialize(bus);
if (i2c == NULL)
{
serr("ERROR: Failed to get I2C%d interface\n", bus);
}
else
{
ret = i2c_register(i2c, bus);
if (ret < 0)
{
serr("ERROR: Failed to register I2C%d driver: %d\n", bus, ret);
imxrt_i2cbus_uninitialize(i2c);
}
}
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_bringup
*
* Description:
* Bring up board features
*
****************************************************************************/
int imxrt_bringup(void)
{
int ret;
/* If we got here then perhaps not all initialization was successful, but
* at least enough succeeded to bring-up NSH with perhaps reduced
* capabilities.
*/
#ifdef CONFIG_FS_PROCFS
/* Mount the procfs file system */
ret = nx_mount(NULL, "/proc", "procfs", 0, NULL);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret);
}
#endif
#if defined(CONFIG_I2C_DRIVER) && defined(CONFIG_IMXRT_LPI2C1)
imxrt_i2c_register(1);
#endif
#ifdef CONFIG_IMXRT_USDHC
/* Initialize SDHC-base MMC/SD card support */
nsh_sdmmc_initialize();
#endif
#ifdef CONFIG_MMCSD_SPI
/* Initialize SPI-based MMC/SD card support */
imxrt_spidev_initialize();
ret = imxrt_mmcsd_spi_initialize(MMCSD_MINOR);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Failed to initialize SD slot %d: %d\n", ret);
}
#endif
#if defined(CONFIG_IMXRT_USBOTG) || defined(CONFIG_USBHOST)
ret = imxrt_usbhost_initialize();
if (ret != OK)
{
syslog(LOG_ERR, "ERROR: Failed to start USB host services: %d\n", ret);
}
#endif
#ifdef CONFIG_USBMONITOR
/* Start the USB Monitor */
ret = usbmonitor_start();
if (ret != OK)
{
syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret);
}
#endif
#ifdef CONFIG_DEV_GPIO
ret = imxrt_gpio_initialize();
if (ret < 0)
{
syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret);
}
#endif
#ifdef CONFIG_VIDEO_FB
/* Initialize and register the framebuffer driver */
ret = fb_register(0, 0);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret);
}
#endif
#ifdef CONFIG_BSP_USING_CH438
board_ch438_initialize();
#endif
#ifdef CONFIG_INPUT_GT9XX
/* Initialize the GT9XX touchscreen driver */
ret = imxrt_gt9xx_register();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: imxrt_ft5x06_register() failed: %d\n", ret);
}
syslog(LOG_NOTICE, "Start initialize %d ok ...\n", ret);
#endif
UNUSED(ret);
return OK;
}
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_buttons.c
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/****************************************************************************
* boards/arm/imxrt/xidatong-arm32/src/imxrt_buttons.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file imxrt_buttons.c
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-23
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <errno.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "imxrt_config.h"
#include "imxrt_irq.h"
#include "imxrt_gpio.h"
#include "xidatong-arm32.h"
#ifdef CONFIG_ARCH_BUTTONS
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The IMXRT has 1 user button (SW8)):
*
* 1. SW8 (IRQ88) GPIO5-00
*/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_button_initialize
*
* Description:
* board_button_initialize() must be called to initialize button resources.
* After that, board_buttons() may be called to collect the current state
* of all buttons or board_button_irq() may be called to register button
* interrupt handlers.
*
****************************************************************************/
uint32_t board_button_initialize(void)
{
/* Configure the button as input */
imxrt_config_gpio(GPIO_SW8);
return 1;
}
/****************************************************************************
* Name: board_buttons
*
* Description:
* After board_button_initialize() has been called, board_buttons() may be
* called to collect the state of all buttons. board_buttons() returns an
* 8-bit bit set with each bit associated with a button. See the
* BUTTON_*_BIT definitions in board.h for the meaning of each bit.
*
****************************************************************************/
uint8_t board_buttons(void)
{
uint8_t ret = 0;
if (!imxrt_gpio_read(GPIO_SW8))
{
ret |= BUTTON_SW8_BIT;
}
return ret;
}
/****************************************************************************
* Name: board_button_irq
*
* Description:
* board_button_irq() may be called to register an interrupt handler that
* will be called when a button is depressed or released. The ID value is
* a button enumeration value that uniquely identifies a button resource.
* See the BUTTON_* definitions in board.h for the meaning of enumeration
* value.
*
****************************************************************************/
#ifdef CONFIG_ARCH_IRQBUTTONS
int board_button_irq(int id, xcpt_t irqhandler)
{
int ret = -EINVAL;
/* The button has already been configured as an interrupting input (by
* board_button_initialize() above).
*
* Attach the new button handler.
*/
ret = irq_attach(id, irqhandler, NULL);
/* Then make sure that interrupts are enabled on the pin */
up_enable_irq(id);
return ret;
}
#endif
#endif /* CONFIG_ARCH_BUTTONS */
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_ch438.c
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file imxrt_ch438.c
* @brief imxrt board sd card automount
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.04.26
*/
#include "imxrt_ch438.h"
#define CH438PORTNUM 8
#define CH438_BUFFSIZE 256
#define CH438_INCREMENT MSEC2TICK(33)
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static FAR void getInterruptStatus(FAR void *arg);
static void CH438SetOutput(void);
static void CH438SetInput(void);
static uint8_t ReadCH438Data(uint8_t addr);
static void WriteCH438Data(uint8_t addr, const uint8_t dat);
static void WriteCH438Block(uint8_t mAddr, uint8_t mLen, const uint8_t *mBuf);
static void Ch438UartSend(uint8_t ext_uart_no, const uint8_t *Data, uint16_t Num);
uint8_t CH438UARTRcv(uint8_t ext_uart_no, uint8_t *buf, size_t size);
static void ImxrtCH438Init(void);
static void CH438PortInit(uint8_t ext_uart_no, uint32_t baud_rate);
static int ImxrtCh438WriteData(uint8_t ext_uart_no, const uint8_t *write_buffer, size_t size);
static size_t ImxrtCh438ReadData(uint8_t ext_uart_no, size_t size);
static void Ch438InitDefault(void);
static int ch438_open(FAR struct file *filep);
static int ch438_close(FAR struct file *filep);
static ssize_t ch438_read(FAR struct file *filep, FAR char *buffer, size_t buflen);
static ssize_t ch438_write(FAR struct file *filep, FAR const char *buffer, size_t buflen);
static int ch438_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
static int ch438_register(FAR const char *devpath, uint8_t ext_uart_no);
/****************************************************************************
* Private type
****************************************************************************/
struct ch438_dev_s
{
sem_t devsem; /* ch438 port devsem */
uint8_t port; /* ch438 port number*/
};
/****************************************************************************
* Private Data
****************************************************************************/
/*mutex of corresponding port*/
static pthread_mutex_t mutex[CH438PORTNUM] =
{
PTHREAD_MUTEX_INITIALIZER,
PTHREAD_MUTEX_INITIALIZER,
PTHREAD_MUTEX_INITIALIZER,
PTHREAD_MUTEX_INITIALIZER,
PTHREAD_MUTEX_INITIALIZER,
PTHREAD_MUTEX_INITIALIZER,
PTHREAD_MUTEX_INITIALIZER,
PTHREAD_MUTEX_INITIALIZER
};
/* Condition variable of corresponding port */
static pthread_cond_t cond[CH438PORTNUM] =
{
PTHREAD_COND_INITIALIZER,
PTHREAD_COND_INITIALIZER,
PTHREAD_COND_INITIALIZER,
PTHREAD_COND_INITIALIZER,
PTHREAD_COND_INITIALIZER,
PTHREAD_COND_INITIALIZER,
PTHREAD_COND_INITIALIZER,
PTHREAD_COND_INITIALIZER
};
/* This array shows whether the current serial port is selected */
static bool const g_uart_selected[CH438PORTNUM] =
{
#ifdef CONFIG_CH438_EXTUART0
[0] = true,
#endif
#ifdef CONFIG_CH438_EXTUART1
[1] = true,
#endif
#ifdef CONFIG_CH438_EXTUART2
[2] = true,
#endif
#ifdef CONFIG_CH438_EXTUART3
[3] = true,
#endif
#ifdef CONFIG_CH438_EXTUART4
[4] = true,
#endif
#ifdef CONFIG_CH438_EXTUART5
[5] = true,
#endif
#ifdef CONFIG_CH438_EXTUART6
[6] = true,
#endif
#ifdef CONFIG_CH438_EXTUART7
[7] = true,
#endif
};
/* ch438 Callback work queue structure */
static struct work_s g_ch438irqwork;
/* there is data available on the corresponding port */
static volatile bool done[CH438PORTNUM] = {false,false,false,false,false,false,false,false};
/* Eight port data buffer */
static uint8_t buff[CH438PORTNUM][CH438_BUFFSIZE];
/* the value of interrupt number of SSR register */
static uint8_t Interruptnum[CH438PORTNUM] = {0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,};
/* Offset address of serial port number */
static uint8_t offsetadd[CH438PORTNUM] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,};
/* port open status global variable */
static volatile bool g_ch438open[CH438PORTNUM] = {false,false,false,false,false,false,false,false};
/* Ch438 POSIX interface */
static const struct file_operations g_ch438fops =
{
ch438_open,
ch438_close,
ch438_read,
ch438_write,
NULL,
ch438_ioctl,
NULL
};
/****************************************************************************
* Name: getInterruptStatus
*
* Description:
* thread task getInterruptStatus
*
****************************************************************************/
static FAR void getInterruptStatus(FAR void *arg)
{
uint8_t i;
uint8_t gInterruptStatus; /* Interrupt register status */
gInterruptStatus = ReadCH438Data(REG_SSR_ADDR);
if(gInterruptStatus)
{
for(i = 0; i < CH438PORTNUM; i++)
{
if(g_uart_selected[i] && (gInterruptStatus & Interruptnum[i]))
{
pthread_mutex_lock(&mutex[i]);
done[i] = true;
pthread_cond_signal(&cond[i]);
pthread_mutex_unlock(&mutex[i]);
}
}
}
work_queue(HPWORK, &g_ch438irqwork, getInterruptStatus, NULL, CH438_INCREMENT);
}
/****************************************************************************
* Name: CH438SetOutput
*
* Description:
* Configure pin mode to output
*
****************************************************************************/
static void CH438SetOutput(void)
{
imxrt_config_gpio(CH438_D0_PIN_OUT);
imxrt_config_gpio(CH438_D1_PIN_OUT);
imxrt_config_gpio(CH438_D2_PIN_OUT);
imxrt_config_gpio(CH438_D3_PIN_OUT);
imxrt_config_gpio(CH438_D4_PIN_OUT);
imxrt_config_gpio(CH438_D5_PIN_OUT);
imxrt_config_gpio(CH438_D6_PIN_OUT);
imxrt_config_gpio(CH438_D7_PIN_OUT);
}
/****************************************************************************
* Name: CH438SetInput
*
* Description:
* Configure pin mode to input
*
****************************************************************************/
static void CH438SetInput(void)
{
imxrt_config_gpio(CH438_D0_PIN_INPUT);
imxrt_config_gpio(CH438_D1_PIN_INPUT);
imxrt_config_gpio(CH438_D2_PIN_INPUT);
imxrt_config_gpio(CH438_D3_PIN_INPUT);
imxrt_config_gpio(CH438_D4_PIN_INPUT);
imxrt_config_gpio(CH438_D5_PIN_INPUT);
imxrt_config_gpio(CH438_D6_PIN_INPUT);
imxrt_config_gpio(CH438_D7_PIN_INPUT);
}
/****************************************************************************
* Name: ReadCH438Data
*
* Description:
* Read data from ch438 address
*
****************************************************************************/
static uint8_t ReadCH438Data(uint8_t addr)
{
uint8_t dat = 0;
imxrt_gpio_write(CH438_NWR_PIN, true);
imxrt_gpio_write(CH438_NRD_PIN, true);
imxrt_gpio_write(CH438_ALE_PIN, true);
CH438SetOutput();
up_udelay(1);
if(addr &0x80) imxrt_gpio_write(CH438_D7_PIN_OUT, true); else imxrt_gpio_write(CH438_D7_PIN_OUT, false);
if(addr &0x40) imxrt_gpio_write(CH438_D6_PIN_OUT, true); else imxrt_gpio_write(CH438_D6_PIN_OUT, false);
if(addr &0x20) imxrt_gpio_write(CH438_D5_PIN_OUT, true); else imxrt_gpio_write(CH438_D5_PIN_OUT, false);
if(addr &0x10) imxrt_gpio_write(CH438_D4_PIN_OUT, true); else imxrt_gpio_write(CH438_D4_PIN_OUT, false);
if(addr &0x08) imxrt_gpio_write(CH438_D3_PIN_OUT, true); else imxrt_gpio_write(CH438_D3_PIN_OUT, false);
if(addr &0x04) imxrt_gpio_write(CH438_D2_PIN_OUT, true); else imxrt_gpio_write(CH438_D2_PIN_OUT, false);
if(addr &0x02) imxrt_gpio_write(CH438_D1_PIN_OUT, true); else imxrt_gpio_write(CH438_D1_PIN_OUT, false);
if(addr &0x01) imxrt_gpio_write(CH438_D0_PIN_OUT, true); else imxrt_gpio_write(CH438_D0_PIN_OUT, false);
up_udelay(1);
imxrt_gpio_write(CH438_ALE_PIN, false);
up_udelay(1);
CH438SetInput();
up_udelay(1);
imxrt_gpio_write(CH438_NRD_PIN, false);
up_udelay(1);
if (imxrt_gpio_read(CH438_D7_PIN_INPUT)) dat |= 0x80;
if (imxrt_gpio_read(CH438_D6_PIN_INPUT)) dat |= 0x40;
if (imxrt_gpio_read(CH438_D5_PIN_INPUT)) dat |= 0x20;
if (imxrt_gpio_read(CH438_D4_PIN_INPUT)) dat |= 0x10;
if (imxrt_gpio_read(CH438_D3_PIN_INPUT)) dat |= 0x08;
if (imxrt_gpio_read(CH438_D2_PIN_INPUT)) dat |= 0x04;
if (imxrt_gpio_read(CH438_D1_PIN_INPUT)) dat |= 0x02;
if (imxrt_gpio_read(CH438_D0_PIN_INPUT)) dat |= 0x01;
imxrt_gpio_write(CH438_NRD_PIN, true);
imxrt_gpio_write(CH438_ALE_PIN, true);
up_udelay(1);
return dat;
}
/****************************************************************************
* Name: WriteCH438Data
*
* Description:
* write data to ch438 address
*
****************************************************************************/
static void WriteCH438Data(uint8_t addr, const uint8_t dat)
{
imxrt_gpio_write(CH438_ALE_PIN, true);
imxrt_gpio_write(CH438_NRD_PIN, true);
imxrt_gpio_write(CH438_NWR_PIN, true);
CH438SetOutput();
up_udelay(1);
if(addr &0x80) imxrt_gpio_write(CH438_D7_PIN_OUT, true); else imxrt_gpio_write(CH438_D7_PIN_OUT, false);
if(addr &0x40) imxrt_gpio_write(CH438_D6_PIN_OUT, true); else imxrt_gpio_write(CH438_D6_PIN_OUT, false);
if(addr &0x20) imxrt_gpio_write(CH438_D5_PIN_OUT, true); else imxrt_gpio_write(CH438_D5_PIN_OUT, false);
if(addr &0x10) imxrt_gpio_write(CH438_D4_PIN_OUT, true); else imxrt_gpio_write(CH438_D4_PIN_OUT, false);
if(addr &0x08) imxrt_gpio_write(CH438_D3_PIN_OUT, true); else imxrt_gpio_write(CH438_D3_PIN_OUT, false);
if(addr &0x04) imxrt_gpio_write(CH438_D2_PIN_OUT, true); else imxrt_gpio_write(CH438_D2_PIN_OUT, false);
if(addr &0x02) imxrt_gpio_write(CH438_D1_PIN_OUT, true); else imxrt_gpio_write(CH438_D1_PIN_OUT, false);
if(addr &0x01) imxrt_gpio_write(CH438_D0_PIN_OUT, true); else imxrt_gpio_write(CH438_D0_PIN_OUT, false);
up_udelay(1);
imxrt_gpio_write(CH438_ALE_PIN, false);
up_udelay(1);
if(dat &0x80) imxrt_gpio_write(CH438_D7_PIN_OUT, true); else imxrt_gpio_write(CH438_D7_PIN_OUT, false);
if(dat &0x40) imxrt_gpio_write(CH438_D6_PIN_OUT, true); else imxrt_gpio_write(CH438_D6_PIN_OUT, false);
if(dat &0x20) imxrt_gpio_write(CH438_D5_PIN_OUT, true); else imxrt_gpio_write(CH438_D5_PIN_OUT, false);
if(dat &0x10) imxrt_gpio_write(CH438_D4_PIN_OUT, true); else imxrt_gpio_write(CH438_D4_PIN_OUT, false);
if(dat &0x08) imxrt_gpio_write(CH438_D3_PIN_OUT, true); else imxrt_gpio_write(CH438_D3_PIN_OUT, false);
if(dat &0x04) imxrt_gpio_write(CH438_D2_PIN_OUT, true); else imxrt_gpio_write(CH438_D2_PIN_OUT, false);
if(dat &0x02) imxrt_gpio_write(CH438_D1_PIN_OUT, true); else imxrt_gpio_write(CH438_D1_PIN_OUT, false);
if(dat &0x01) imxrt_gpio_write(CH438_D0_PIN_OUT, true); else imxrt_gpio_write(CH438_D0_PIN_OUT, false);
up_udelay(1);
imxrt_gpio_write(CH438_NWR_PIN, false);
up_udelay(1);
imxrt_gpio_write(CH438_NWR_PIN, true);
imxrt_gpio_write(CH438_ALE_PIN, true);
up_udelay(1);
CH438SetInput();
return;
}
/****************************************************************************
* Name: WriteCH438Block
*
* Description:
* Write data block from ch438 address
*
****************************************************************************/
static void WriteCH438Block(uint8_t mAddr, uint8_t mLen, const uint8_t *mBuf)
{
while(mLen--)
WriteCH438Data(mAddr, *mBuf++);
}
/****************************************************************************
* Name: CH438UARTSend
*
* Description:
* Enable FIFO mode, which is used for ch438 serial port to send multi byte data,
* with a maximum of 128 bytes of data sent at a time
*
****************************************************************************/
static void Ch438UartSend(uint8_t ext_uart_no, const uint8_t *Data, uint16_t Num)
{
uint8_t REG_LSR_ADDR,REG_THR_ADDR;
REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
while(1)
{
while((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_TEMT) == 0); /* wait for sending data done, THR and TSR is NULL */
if(Num <= 128)
{
WriteCH438Block(REG_THR_ADDR, Num, Data);
break;
}
else
{
WriteCH438Block(REG_THR_ADDR, 128, Data);
Num -= 128;
Data += 128;
}
}
}
/****************************************************************************
* Name: CH438UARTRcv
*
* Description:
* Disable FIFO mode for ch438 serial port to receive multi byte data
*
****************************************************************************/
uint8_t CH438UARTRcv(uint8_t ext_uart_no, uint8_t *buf, size_t size)
{
uint8_t rcv_num = 0;
uint8_t dat = 0;
uint8_t REG_LSR_ADDR,REG_RBR_ADDR;
uint8_t *read_buffer;
size_t buffer_index = 0;
read_buffer = buf;
REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
/* Wait for the data to be ready */
while ((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0);
while (((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0x01) && (size != 0))
{
dat = ReadCH438Data(REG_RBR_ADDR);
*read_buffer = dat;
read_buffer++;
buffer_index++;
if (255 == buffer_index) {
buffer_index = 0;
read_buffer = buf;
}
++rcv_num;
--size;
}
return rcv_num;
}
/****************************************************************************
* Name: ImxrtCH438Init
*
* Description:
* ch438 initialization
*
****************************************************************************/
static void ImxrtCH438Init(void)
{
CH438SetOutput();
imxrt_config_gpio(CH438_NWR_PIN);
imxrt_config_gpio(CH438_NRD_PIN);
imxrt_config_gpio(CH438_ALE_PIN);
imxrt_gpio_write(CH438_NWR_PIN,true);
imxrt_gpio_write(CH438_NRD_PIN,true);
imxrt_gpio_write(CH438_ALE_PIN,true);
}
/****************************************************************************
* Name: CH438PortInit
*
* Description:
* ch438 port initialization
*
****************************************************************************/
static void CH438PortInit(uint8_t ext_uart_no, uint32_t baud_rate)
{
uint32_t div;
uint8_t DLL,DLM,dlab;
uint8_t REG_LCR_ADDR;
uint8_t REG_DLL_ADDR;
uint8_t REG_DLM_ADDR;
uint8_t REG_IER_ADDR;
uint8_t REG_MCR_ADDR;
uint8_t REG_FCR_ADDR;
REG_LCR_ADDR = offsetadd[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offsetadd[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offsetadd[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offsetadd[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offsetadd[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offsetadd[ext_uart_no] | REG_FCR0_ADDR;
/* reset the uart */
WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET);
up_mdelay(50);
dlab = ReadCH438Data(REG_IER_ADDR);
dlab &= 0xDF;
WriteCH438Data(REG_IER_ADDR, dlab);
/* set LCR register DLAB bit 1 */
dlab = ReadCH438Data(REG_LCR_ADDR);
dlab |= 0x80;
WriteCH438Data(REG_LCR_ADDR, dlab);
div = (Fpclk >> 4) / baud_rate;
DLM = div >> 8;
DLL = div & 0xff;
/* set bps */
WriteCH438Data(REG_DLL_ADDR, DLL);
WriteCH438Data(REG_DLM_ADDR, DLM);
/* set FIFO mode, 112 bytes */
WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN);
/* 8 bit word size, 1 bit stop bit, no crc */
WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0);
/* enable interrupt */
WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV);
/* allow interrupt output, DTR and RTS is 1 */
WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2);
/* release the data in FIFO */
WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR)| BIT_FCR_TFIFORST);
}
/****************************************************************************
* Name: ImxrtCh438ReadData
*
* Description:
* Read data from ch438 port
*
****************************************************************************/
static int ImxrtCh438WriteData(uint8_t ext_uart_no, const uint8_t *write_buffer, size_t size)
{
int write_len, write_len_continue;
int i, write_index;
DEBUGASSERT(write_buffer != NULL);
write_len = size;
write_len_continue = size;
if(write_len > 256)
{
if(0 == write_len % 256)
{
write_index = write_len / 256;
for(i = 0; i < write_index; i ++)
{
Ch438UartSend(ext_uart_no, write_buffer + i * 256, 256);
}
}
else
{
write_index = 0;
while(write_len_continue > 256)
{
Ch438UartSend(ext_uart_no, write_buffer + write_index * 256, 256);
write_index++;
write_len_continue = write_len - write_index * 256;
}
Ch438UartSend(ext_uart_no, write_buffer + write_index * 256, write_len_continue);
}
}
else
{
Ch438UartSend(ext_uart_no, write_buffer, write_len);
}
return OK;
}
/****************************************************************************
* Name: ImxrtCh438ReadData
*
* Description:
* Read data from ch438 port
*
****************************************************************************/
static size_t ImxrtCh438ReadData(uint8_t ext_uart_no, size_t size)
{
size_t RevLen = 0;
uint8_t InterruptStatus;
uint8_t REG_IIR_ADDR;
uint8_t REG_LSR_ADDR;
uint8_t REG_MSR_ADDR;
pthread_mutex_lock(&mutex[ext_uart_no]);
while(done[ext_uart_no] == false)
pthread_cond_wait(&cond[ext_uart_no], &mutex[ext_uart_no]);
if(done[ext_uart_no] == true)
{
REG_IIR_ADDR = offsetadd[ext_uart_no] | REG_IIR0_ADDR;
REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
REG_MSR_ADDR = offsetadd[ext_uart_no] | REG_MSR0_ADDR;
/* Read the interrupt status of the serial port */
InterruptStatus = ReadCH438Data(REG_IIR_ADDR) & 0x0f;
ch438info("InterruptStatus is %d\n", InterruptStatus);
switch(InterruptStatus)
{
case INT_NOINT: /* no interrupt */
break;
case INT_THR_EMPTY: /* the transmit hold register is not interrupted */
break;
case INT_RCV_OVERTIME: /* receive data timeout interrupt */
case INT_RCV_SUCCESS: /* receive data available interrupt */
RevLen = CH438UARTRcv(ext_uart_no, buff[ext_uart_no], size);
break;
case INT_RCV_LINES: /* receive line status interrupt */
ReadCH438Data(REG_LSR_ADDR);
break;
case INT_MODEM_CHANGE: /* modem input change interrupt */
ReadCH438Data(REG_MSR_ADDR);
break;
default:
break;
}
done[ext_uart_no] = false;
}
pthread_mutex_unlock(&mutex[ext_uart_no]);
return RevLen;
}
/****************************************************************************
* Name: Ch438InitDefault
*
* Description:
* Ch438 default initialization function
*
****************************************************************************/
static void Ch438InitDefault(void)
{
int ret = 0;
int i;
/* Initialize the mutex */
for(i = 0; i < CH438PORTNUM; i++)
{
if(!g_uart_selected[i])
{
continue;
}
ret = pthread_mutex_init(&mutex[i], NULL);
if(ret != 0)
{
ch438err("pthread_mutex_init failed, status=%d\n", ret);
}
}
/* Initialize the condition variable */
for(i = 0; i < CH438PORTNUM; i++)
{
if(!g_uart_selected[i])
{
continue;
}
ret = pthread_cond_init(&cond[i], NULL);
if(ret != 0)
{
ch438err("pthread_cond_init failed, status=%d\n", ret);
}
}
ImxrtCH438Init();
/* If a port is checked, the port will be initialized. Otherwise, the interrupt of the port will be disabled. */
#ifdef CONFIG_CH438_EXTUART0
CH438PortInit(0, CONFIG_CH438_EXTUART0_BAUD);
#else
WriteCH438Data(REG_IER0_ADDR, 0x00);
#endif
#ifdef CONFIG_CH438_EXTUART1
CH438PortInit(1, CONFIG_CH438_EXTUART1_BAUD);
#else
WriteCH438Data(REG_IER1_ADDR, 0x00);
#endif
#ifdef CONFIG_CH438_EXTUART2
CH438PortInit(2, CONFIG_CH438_EXTUART2_BAUD);
#else
WriteCH438Data(REG_IER2_ADDR, 0x00);
#endif
#ifdef CONFIG_CH438_EXTUART3
CH438PortInit(3, CONFIG_CH438_EXTUART3_BAUD);
#else
WriteCH438Data(REG_IER3_ADDR, 0x00);
#endif
#ifdef CONFIG_CH438_EXTUART4
CH438PortInit(4, CONFIG_CH438_EXTUART4_BAUD);
#else
WriteCH438Data(REG_IER4_ADDR, 0x00);
#endif
#ifdef CONFIG_CH438_EXTUART5
CH438PortInit(5, CONFIG_CH438_EXTUART5_BAUD);
#else
WriteCH438Data(REG_IER5_ADDR, 0x00);
#endif
#ifdef CONFIG_CH438_EXTUART6
CH438PortInit(6, CONFIG_CH438_EXTUART6_BAUD);
#else
WriteCH438Data(REG_IER6_ADDR, 0x00);
#endif
#ifdef CONFIG_CH438_EXTUART7
CH438PortInit(7, CONFIG_CH438_EXTUART7_BAUD);
#else
WriteCH438Data(REG_IER7_ADDR, 0x00);
#endif
up_mdelay(10);
work_queue(HPWORK, &g_ch438irqwork, getInterruptStatus, NULL, CH438_INCREMENT);
}
/****************************************************************************
* Name: ch438_open
****************************************************************************/
static int ch438_open(FAR struct file *filep)
{
FAR struct inode *inode = filep->f_inode;
FAR struct ch438_dev_s *priv = inode->i_private;
uint8_t port = priv->port;
int ret = OK;
DEBUGASSERT(port >= 0 && port < CH438PORTNUM);
ret = nxsem_wait_uninterruptible(&priv->devsem);
if (ret < 0)
{
return ret;
}
if(g_ch438open[port])
{
ch438err("ERROR: ch438 port %d is opened!\n",port);
return -EBUSY;
}
g_ch438open[port] = true;
nxsem_post(&priv->devsem);
return ret;
}
/****************************************************************************
* Name: ch438_close
****************************************************************************/
static int ch438_close(FAR struct file *filep)
{
FAR struct inode *inode = filep->f_inode;
FAR struct ch438_dev_s *priv = inode->i_private;
uint8_t port = priv->port;
int ret = OK;
DEBUGASSERT(port >= 0 && port < CH438PORTNUM);
ret = nxsem_wait_uninterruptible(&priv->devsem);
if (ret < 0)
{
return ret;
}
if(!g_ch438open[port])
{
ch438err("ERROR: ch438 port %d is closed!\n",port);
return -EBUSY;
}
g_ch438open[port] = false;
nxsem_post(&priv->devsem);
return ret;
}
/****************************************************************************
* Name: ch438_read
****************************************************************************/
static ssize_t ch438_read(FAR struct file *filep, FAR char *buffer, size_t buflen)
{
size_t length = 0;
FAR struct inode *inode = filep->f_inode;
FAR struct ch438_dev_s *priv = inode->i_private;
uint8_t port = priv->port;
DEBUGASSERT(port >= 0 && port < CH438PORTNUM);
length = ImxrtCh438ReadData(port, buflen);
memcpy(buffer, buff[port], length);
if(length > buflen)
{
length = buflen;
}
return length;
}
/****************************************************************************
* Name: ch438_write
****************************************************************************/
static ssize_t ch438_write(FAR struct file *filep, FAR const char *buffer, size_t buflen)
{
FAR struct inode *inode = filep->f_inode;
FAR struct ch438_dev_s *priv = inode->i_private;
uint8_t port = priv->port;
DEBUGASSERT(port >= 0 && port < CH438PORTNUM);
ImxrtCh438WriteData(port, (const uint8_t *)buffer, buflen);
return buflen;
}
/****************************************************************************
* Name: ch438_ioctl
****************************************************************************/
static int ch438_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
{
FAR struct inode *inode = filep->f_inode;
FAR struct ch438_dev_s *priv = inode->i_private;
uint8_t port = priv->port;
int ret = OK;
DEBUGASSERT(port >= 0 && port < CH438PORTNUM);
switch(cmd)
{
case OPE_INT:
case OPE_CFG:
CH438PortInit(port, (uint32_t)arg);
break;
default:
ch438info("Unrecognized cmd: %d\n", cmd);
ret = -ENOTTY;
break;
}
return ret;
}
/****************************************************************************
* Name: ch438_register
*
* Description:
* Register /dev/ext_uartN
*
****************************************************************************/
static int ch438_register(FAR const char *devpath, uint8_t port)
{
FAR struct ch438_dev_s *priv;
int ret = 0;
/* port number check */
DEBUGASSERT(port >= 0 && port < CH438PORTNUM);
priv = (FAR struct ch438_dev_s *)kmm_malloc(sizeof(struct ch438_dev_s));
if(priv == NULL)
{
ch438err("ERROR: Failed to allocate instance\n");
return -ENOMEM;
}
priv->port = port;
nxsem_init(&priv->devsem, 0, 1);
/* Register the character driver */
ret = register_driver(devpath, &g_ch438fops, 0666, priv);
if(ret < 0)
{
kmm_free(priv);
}
return ret;
}
/****************************************************************************
* Name: board_ch438_initialize
*
* Description:
* ch438 initialize
*
****************************************************************************/
void board_ch438_initialize(void)
{
Ch438InitDefault();
#ifdef CONFIG_CH438_EXTUART0
ch438_register("/dev/extuart_dev0", 0);
#endif
#ifdef CONFIG_CH438_EXTUART1
ch438_register("/dev/extuart_dev1", 1);
#endif
#ifdef CONFIG_CH438_EXTUART2
ch438_register("/dev/extuart_dev2", 2);
#endif
#ifdef CONFIG_CH438_EXTUART3
ch438_register("/dev/extuart_dev3", 3);
#endif
#ifdef CONFIG_CH438_EXTUART4
ch438_register("/dev/extuart_dev4", 4);
#endif
#ifdef CONFIG_CH438_EXTUART5
ch438_register("/dev/extuart_dev5", 5);
#endif
#ifdef CONFIG_CH438_EXTUART6
ch438_register("/dev/extuart_dev6", 6);
#endif
#ifdef CONFIG_CH438_EXTUART7
ch438_register("/dev/extuart_dev7", 7);
#endif
}
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_ch438.h
+369
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@@ -0,0 +1,369 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file imxrt_ch438.h
* @brief imxrt board sd card automount
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.04.26
*/
#ifndef __BOARDS_ARM_IMXRT_XIDATONG_ARM32_SRC_IMXRT_CH438_H
#define __BOARDS_ARM_IMXRT_XIDATONG_ARM32_SRC_IMXRT_CH438_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/kmalloc.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <nuttx/pthread.h>
#include <nuttx/semaphore.h>
#include <nuttx/wqueue.h>
#include <nuttx/wdog.h>
#include <nuttx/clock.h>
#include <nuttx/time.h>
#include <nuttx/fs/fs.h>
#include <nuttx/fs/ioctl.h>
#include <nuttx/arch.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <errno.h>
#include <stddef.h>
#include <stdint.h>
#include <stdio.h>
#include <sched.h>
#include <debug.h>
#include <assert.h>
#include <unistd.h>
#include <stdbool.h>
#include <string.h>
#include <stdlib.h>
#include <fcntl.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "imxrt_config.h"
#include "imxrt_irq.h"
#include "imxrt_gpio.h"
#include "xidatong-arm32.h"
/******************************************************************************************/
/* chip definition */
/* CH438serial port0 register address */
#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */
#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */
#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */
#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */
#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */
#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */
#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */
#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */
#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */
#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */
#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port1 register address */
#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */
#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */
#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */
#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */
#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */
#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */
#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */
#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */
#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */
#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */
#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port2 register address */
#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */
#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */
#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */
#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */
#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */
#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */
#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */
#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */
#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */
#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */
#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port3 register address */
#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */
#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */
#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */
#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */
#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */
#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */
#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */
#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */
#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */
#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */
#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port4 register address */
#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */
#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */
#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */
#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */
#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */
#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */
#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */
#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */
#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */
#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */
#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port5 register address */
#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */
#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */
#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */
#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */
#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */
#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */
#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */
#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */
#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */
#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */
#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port6 register address */
#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */
#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */
#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */
#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */
#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */
#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */
#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */
#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */
#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */
#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */
#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port7 register address */
#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */
#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */
#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */
#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */
#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */
#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */
#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */
#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */
#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */
#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */
#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */
#define REG_SSR_ADDR 0x4F /* pecial status register address */
/* IER register bit */
#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */
#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */
#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */
#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal */
#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */
#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */
#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */
#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */
/* IIR register bit */
#define BIT_IIR_FIFOENS1 0x80
#define BIT_IIR_FIFOENS0 0x40 /* The two is 1 said use FIFO */
/* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted,
1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */
#define BIT_IIR_IID3 0x08
#define BIT_IIR_IID2 0x04
#define BIT_IIR_IID1 0x02
#define BIT_IIR_NOINT 0x01
/* FCR register bit */
/* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */
#define BIT_FCR_RECVTG1 0x80 /* Set the trigger point for FIFO interruption and automatic hardware flow control */
#define BIT_FCR_RECVTG0 0x40 /* Set the trigger point for FIFO interruption and automatic hardware flow control */
#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */
#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */
#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */
/* LCR register bit */
#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */
#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/
/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */
#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */
#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */
#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */
#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */
/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */
#define BIT_LCR_WORDSZ1 0x02 /* Set the word length length */
#define BIT_LCR_WORDSZ0 0x01
/* MCR register bit */
#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */
#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */
#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */
#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */
#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */
#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */
/* LSR register bit */
#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */
#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */
#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/
#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/
#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */
#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */
#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */
#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */
/* MSR register bit */
#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */
#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */
#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */
#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */
#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */
#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */
#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */
#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */
/* Interrupt status code */
#define INT_NOINT 0x01 /* There is no interruption */
#define INT_THR_EMPTY 0x02 /* THR empty interruption */
#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */
#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */
#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */
#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */
#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */
#define Fpclk 1843200 /* Define the internal clock frequency*/
// #define IOMUX_CH438OUT_DEFAULT
#define CH438_D0_PIN_OUT (GPIO_OUTPUT | IOMUX_GOUT_DEFAULT | \
GPIO_PORT1 | GPIO_PIN25)
#define CH438_D1_PIN_OUT (GPIO_OUTPUT | IOMUX_GOUT_DEFAULT | \
GPIO_PORT1 | GPIO_PIN24)
#define CH438_D2_PIN_OUT (GPIO_OUTPUT | IOMUX_GOUT_DEFAULT | \
GPIO_PORT1 | GPIO_PIN20)
#define CH438_D3_PIN_OUT (GPIO_OUTPUT | IOMUX_GOUT_DEFAULT | \
GPIO_PORT1 | GPIO_PIN21)
#define CH438_D4_PIN_OUT (GPIO_OUTPUT | IOMUX_GOUT_DEFAULT | \
GPIO_PORT1 | GPIO_PIN31)
#define CH438_D5_PIN_OUT (GPIO_OUTPUT | IOMUX_GOUT_DEFAULT | \
GPIO_PORT1 | GPIO_PIN28)
#define CH438_D6_PIN_OUT (GPIO_OUTPUT | IOMUX_GOUT_DEFAULT | \
GPIO_PORT1 | GPIO_PIN30)
#define CH438_D7_PIN_OUT (GPIO_OUTPUT | IOMUX_GOUT_DEFAULT | \
GPIO_PORT1 | GPIO_PIN29)
#define CH438_NWR_PIN (GPIO_OUTPUT | IOMUX_GOUT_DEFAULT | \
GPIO_PORT3 | GPIO_PIN4)
#define CH438_NRD_PIN (GPIO_OUTPUT | IOMUX_GOUT_DEFAULT | \
GPIO_PORT3 | GPIO_PIN5)
#define CH438_ALE_PIN (GPIO_OUTPUT | IOMUX_GOUT_DEFAULT | \
GPIO_PORT3 | GPIO_PIN2)
#define CH438_INT_PIN (GPIO_INTERRUPT | GPIO_INT_FALLINGEDGE | IOMUX_SW_DEFAULT | \
GPIO_PORT3 | GPIO_PIN3)
#define CH438_D0_PIN_INPUT (GPIO_INPUT | \
GPIO_PORT1 | GPIO_PIN25)
#define CH438_D1_PIN_INPUT (GPIO_INPUT | \
GPIO_PORT1 | GPIO_PIN24)
#define CH438_D2_PIN_INPUT (GPIO_INPUT | \
GPIO_PORT1 | GPIO_PIN20)
#define CH438_D3_PIN_INPUT (GPIO_INPUT | \
GPIO_PORT1 | GPIO_PIN21)
#define CH438_D4_PIN_INPUT (GPIO_INPUT | \
GPIO_PORT1 | GPIO_PIN31)
#define CH438_D5_PIN_INPUT (GPIO_INPUT | \
GPIO_PORT1 | GPIO_PIN28)
#define CH438_D6_PIN_INPUT (GPIO_INPUT | \
GPIO_PORT1 | GPIO_PIN30)
#define CH438_D7_PIN_INPUT (GPIO_INPUT | \
GPIO_PORT1 | GPIO_PIN29)
/* ch438 debug */
#ifdef CONFIG_DEBUG_CH438_ERROR
# define ch438err _err
#else
# define ch438err _none
#endif
#ifdef CONFIG_DEBUG_CH438_WARN
# define ch438warn _warn
#else
# define ch438warn _none
#endif
#ifdef CONFIG_DEBUG_CH438_INFO
# define ch438info _info
#else
# define ch438info _none
#endif
/* ioctl cmd */
#define OPE_INT 0x0000
#define OPE_CFG 0x0001
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef CONFIG_BSP_USING_CH438
void board_ch438_initialize(void);
#endif
#endif /* __BOARDS_ARM_IMXRT_XIDATONG_ARM32_SRC_IMXRT_CH438_H */
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_ethernet.c
+293
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@@ -0,0 +1,293 @@
/****************************************************************************
* boards/arm/imxrt/xidatong-arm32/src/imxrt_ethernet.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file imxrt_ethernet.c
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-23
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Force verbose debug on in this file only to support unit-level testing. */
#ifdef CONFIG_NETDEV_PHY_DEBUG
# undef CONFIG_DEBUG_INFO
# define CONFIG_DEBUG_INFO 1
# undef CONFIG_DEBUG_NET
# define CONFIG_DEBUG_NET 1
#endif
#include <string.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include "imxrt_gpio.h"
#include "imxrt_enet.h"
#include "xidatong-arm32.h"
#include <arch/board/board.h>
#ifdef CONFIG_IMXRT_ENET
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IMXRT_ENET_DEVNAME "eth0"
/* Debug ********************************************************************/
/* Extra, in-depth debug output that is only available if
* CONFIG_NETDEV_PHY_DEBUG us defined.
*/
#ifdef CONFIG_NETDEV_PHY_DEBUG
# define phyerr _err
# define phywarn _warn
# define phyinfo _info
#else
# define phyerr(x...)
# define phywarn(x...)
# define phyinfo(x...)
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_enet_phy_enable
****************************************************************************/
#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ
static void imxrt_enet_phy_enable(bool enable)
{
phyinfo("IRQ%d: enable=%d\n", GPIO_ENET_INT, enable);
if (enable)
{
up_enable_irq(GPIO_ENET_IRQ);
}
else
{
up_disable_irq(GPIO_ENET_IRQ);
}
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: imxrt_phy_boardinitialize
*
* Description:
* Some boards require specialized initialization of the PHY before it can
* be used.
* This may include such things as configuring GPIOs, resetting the PHY,
* etc.
* If CONFIG_IMXRT_ENET_PHYINIT is defined in the configuration then the
* board specific logic must provide imxrt_phyinitialize();
* The i.MX RT Ethernet driver will call this function one time before it
* first uses the PHY.
*
* Input Parameters:
* intf - Always zero for now.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
****************************************************************************/
int imxrt_phy_boardinitialize(int intf)
{
#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ
/* Configure the PHY interrupt pin */
phyinfo("Configuring interrupt: %08x\n", GPIO_ENET_INT);
imxrt_config_gpio(GPIO_ENET_INT);
#endif
/* Configure the PHY reset pin.
*
* The #RST uses inverted logic. The initial value of zero will put the
* PHY into the reset state.
*/
#ifdef GPIO_ENET_RST
/* On the EVK the RST pin is combined with LED, so sometimes can't be
* accessed. Only stress about it if we've got a definition.
*/
phyinfo("Configuring reset: %08x\n", GPIO_ENET_RST);
imxrt_config_gpio(GPIO_ENET_RST);
/* Take the PHY out of reset. */
imxrt_gpio_write(GPIO_ENET_RST, true);
#endif
return OK;
}
/****************************************************************************
* Name: arch_phy_irq
*
* Description:
* This function may be called to register an interrupt handler that will
* be called when a PHY interrupt occurs. This function both attaches
* the interrupt handler and enables the interrupt if 'handler' is non-
* NULL. If handler is NULL, then the interrupt is detached and disabled
* instead.
*
* The PHY interrupt is always disabled upon return. The caller must
* call back through the enable function point to control the state of
* the interrupt.
*
* This interrupt may or may not be available on a given platform depending
* on how the network hardware architecture is implemented. In a typical
* case, the PHY interrupt is provided to board-level logic as a GPIO
* interrupt (in which case this is a board-specific interface and really
* should be called board_phy_irq()); In other cases, the PHY interrupt
* may be cause by the chip's MAC logic (in which case arch_phy_irq()) is
* an appropriate name. Other other boards, there may be no PHY interrupts
* available at all. If client attachable PHY interrupts are available
* from the board or from the chip, then CONFIG_ARCH_PHY_INTERRUPT should
* be defined to indicate that fact.
*
* Typical usage:
* a. OS service logic (not application logic*) attaches to the PHY
* PHY interrupt and enables the PHY interrupt.
* b. When the PHY interrupt occurs: (1) the interrupt should be
* disabled and () work should be scheduled on the worker thread (or
* perhaps a dedicated application thread).
* c. That worker thread should use the SIOCGMIIPHY, SIOCGMIIREG,
* and SIOCSMIIREG ioctl calls** to communicate with the PHY,
* determine what network event took place (Link Up/Down?), and
* take the appropriate actions.
* d. It should then interact the PHY to clear any pending
* interrupts, then re-enable the PHY interrupt.
*
* * This is an OS internal interface and should not be used from
* application space. Rather applications should use the SIOCMIISIG
* ioctl to receive a signal when a PHY event occurs.
* ** This interrupt is really of no use if the Ethernet MAC driver
* does not support these ioctl calls.
*
* Input Parameters:
* intf - Identifies the network interface. For example "eth0". Only
* useful on platforms that support multiple Ethernet interfaces
* and, hence, multiple PHYs and PHY interrupts.
* handler - The client interrupt handler to be invoked when the PHY
* asserts an interrupt. Must reside in OS space, but can
* signal tasks in user space. A value of NULL can be passed
* in order to detach and disable the PHY interrupt.
* arg - The argument that will accompany the interrupt
* enable - A function pointer that be unused to enable or disable the
* PHY interrupt.
*
* Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
****************************************************************************/
#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ
int arch_phy_irq(FAR const char *intf, xcpt_t handler, void *arg,
phy_enable_t *enable)
{
irqstate_t flags;
phy_enable_t enabler;
int irq;
DEBUGASSERT(intf);
ninfo("%s: handler=%p\n", intf, handler);
phyinfo("EMAC: devname=%s\n", IMXRT_ENET_DEVNAME);
if (strcmp(intf, IMXRT_ENET_DEVNAME) == 0)
{
irq = GPIO_ENET_IRQ;
enabler = imxrt_enet_phy_enable;
}
else
{
nerr("ERROR: Unsupported interface: %s\n", intf);
return -EINVAL;
}
/* Disable interrupts until we are done. This guarantees that the
* following operations are atomic.
*/
flags = spin_lock_irqsave(NULL);
/* Configure the interrupt */
if (handler)
{
/* The interrupt pin has already been configured as an interrupting
* input (by imxrt_phy_boardinitialize() above).
*
* Attach the new button handler.
*/
phyinfo("Attach IRQ%d\n", irq);
irq_attach(irq, handler, arg);
}
else
{
phyinfo("Detach IRQ%d\n", irq);
irq_detach(irq);
enabler = NULL;
}
/* Return with the interrupt disabled in either case */
up_disable_irq(GPIO_ENET_IRQ);
/* Return the enabling function pointer */
if (enable)
{
*enable = enabler;
}
/* Return the old handler (so that it can be restored) */
spin_unlock_irqrestore(NULL, flags);
return OK;
}
#endif /* CONFIG_IMXRT_GPIO1_0_15_IRQ */
#endif /* CONFIG_IMXRT_ENET */
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_flexspi_nor_boot.c
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/****************************************************************************
* boards/arm/imxrt/xidatong-arm32/src/imxrt_flexspi_nor_boot.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file imxrt_flexspi_nor_boot.c
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-23
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include "imxrt_flexspi_nor_boot.h"
/****************************************************************************
* Public Data
****************************************************************************/
locate_data(".boot_hdr.ivt")
const struct ivt_s g_image_vector_table =
{
IVT_HEADER, /* IVT Header */
0x60002000, /* Image Entry Function */
IVT_RSVD, /* Reserved = 0 */
(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
(uint32_t)&g_image_vector_table, /* Pointer to IVT Self (absolute address */
(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
IVT_RSVD /* Reserved = 0 */
};
locate_data(".boot_hdr.boot_data")
const struct boot_data_s g_boot_data =
{
FLASH_BASE, /* boot start location */
(FLASH_END - FLASH_BASE), /* size */
PLUGIN_FLAG, /* Plugin flag */
0xffffffff /* empty - extra data word */
};
/****************************************************************************
* Public Functions
****************************************************************************/
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_flexspi_nor_boot.h
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/****************************************************************************
* boards/arm/imxrt/xidatong-arm32/src/imxrt_flexspi_nor_boot.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file imxrt_flexspi_nor_boot.h
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-23
*/
#ifndef __BOARDS_ARM_IMXRT_XIDATONG_ARM32_SRC_IMXRT_FLEXSPI_NOR_BOOT_H
#define __BOARDS_ARM_IMXRT_XIDATONG_ARM32_SRC_IMXRT_FLEXSPI_NOR_BOOT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IVT Data */
#define IVT_MAJOR_VERSION 0x4
#define IVT_MAJOR_VERSION_SHIFT 0x4
#define IVT_MAJOR_VERSION_MASK 0xf
#define IVT_MINOR_VERSION 0x1
#define IVT_MINOR_VERSION_SHIFT 0x0
#define IVT_MINOR_VERSION_MASK 0xf
#define IVT_VERSION(major, minor) \
((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \
(((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT))
#define IVT_TAG_HEADER (0xd1) /* Image Vector Table */
#define IVT_SIZE 0x2000
#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION)
#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24))
#define IVT_RSVD (uint32_t)(0x00000000)
/* DCD Data */
#define DCD_TAG_HEADER (0xd2)
#define DCD_TAG_HEADER_SHIFT (24)
#define DCD_VERSION (0x40)
#define DCD_ARRAY_SIZE 1
#define FLASH_BASE 0x60000000
#define FLASH_END 0x7f7fffff
#define SCLK 1
#ifdef CONFIG_XIDATONG_ARM32_SDRAM
# define DCD_ADDRESS &g_dcd_data
#else
# define DCD_ADDRESS 0
#endif
#define BOOT_DATA_ADDRESS &g_boot_data
#define CSF_ADDRESS 0
#define PLUGIN_FLAG (uint32_t)0
/****************************************************************************
* Public Types
****************************************************************************/
/* IVT Data */
struct ivt_s
{
/* Header with tag #HAB_TAG_IVT, length and HAB version fields
* (see data)
*/
uint32_t hdr;
/* Absolute address of the first instruction to execute from the
* image
*/
uint32_t entry;
/* Reserved in this version of HAB: should be NULL. */
uint32_t reserved1;
/* Absolute address of the image DCD: may be NULL. */
uint32_t dcd;
/* Absolute address of the Boot Data: may be NULL, but not interpreted
* any further by HAB
*/
uint32_t boot_data;
/* Absolute address of the IVT. */
uint32_t self;
/* Absolute address of the image CSF. */
uint32_t csf;
/* Reserved in this version of HAB: should be zero. */
uint32_t reserved2;
};
/* Boot Data */
struct boot_data_s
{
uint32_t start; /* boot start location */
uint32_t size; /* size */
uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */
uint32_t placeholder; /* placeholder to make even 0x10 size */
};
/****************************************************************************
* Public Data
****************************************************************************/
extern const struct boot_data_s g_boot_data;
#ifdef CONFIG_XIDATONG_ARM32_SDRAM
extern const uint8_t g_dcd_data[];
#endif
#endif /* __BOARDS_ARM_IMXRT_XIDATONG_ARM32_SRC_IMXRT_FLEXSPI_NOR_BOOT_H */
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_flexspi_nor_flash.c
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/****************************************************************************
* boards/arm/imxrt/xidatong-arm32/src/imxrt_flexspi_nor_flash.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file imxrt_flexspi_nor_flash.c
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-23
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include "imxrt_flexspi_nor_flash.h"
/****************************************************************************
* Public Data
****************************************************************************/
#if defined (CONFIG_XIDATONG_ARM32_HYPER_FLASH)
locate_data(".boot_hdr.conf")
const struct flexspi_nor_config_s g_flash_config =
{
.mem_config =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.read_sample_clksrc = FLASH_READ_SAMPLE_CLK_EXT_INPUT_FROM_DQSPAD,
.cs_hold_time = 3u,
.cs_setup_time = 3u,
.column_address_width = 3u,
/* Enable DDR mode, Word addassable,
* Safe configuration, Differential clock
*/
.controller_misc_option =
(1u << FLEXSPIMISC_OFFSET_DDR_MODE_EN) |
(1u << FLEXSPIMISC_OFFSET_WORD_ADDRESSABLE_EN) |
(1u << FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN) |
(1u << FLEXSPIMISC_OFFSET_DIFFCLKEN),
.sflash_pad_type = SERIAL_FLASH_8PADS,
.serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_133MHz,
.sflash_a1size = 64u * 1024u * 1024u,
.data_valid_time =
{
16u, 16u
},
.lookup_table =
{
/* Read LUTs */
FLEXSPI_LUT_SEQ(CMD_DDR,
FLEXSPI_8PAD, 0xa0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
FLEXSPI_LUT_SEQ(CADDR_DDR,
FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06),
FLEXSPI_LUT_SEQ(READ_DDR,
FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
},
},
.page_size = 512u,
.sector_size = 256u * 1024u,
.blocksize = 256u * 1024u,
.is_uniform_blocksize = 1,
};
#elif defined (CONFIG_XIDATONG_ARM32_QSPI_FLASH)
locate_data(".boot_hdr.conf")
const struct flexspi_nor_config_s g_flash_config =
{
.mem_config =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.read_sample_clksrc = FLASH_READ_SAMPLE_CLK_LOOPBACK_INTERNELLY,
.cs_hold_time = 3u,
.cs_setup_time = 3u,
.device_mode_cfg_enable = true,
.device_mode_type = 1,
.device_mode_seq.seq_num = 1,
.device_mode_seq.seq_id = 4,
.device_mode_arg = 0x000200,
.device_type = FLEXSPI_DEVICE_TYPE_SERIAL_NOR,
.sflash_pad_type = SERIAL_FLASH_4PADS,
.serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_60MHz,
.sflash_a1size = 16u * 1024u * 1024u,
.data_valid_time = {16u, 16u},
/* Enable DDR mode, Word addassable,
* Safe configuration, Differential clock
*/
.lookup_table =
{
/* Read LUTs */
[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
[2] = FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0),
[1*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
//Write Enable
[3*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, 0, 0),
//Write status
[4*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x2),
},
},
.page_size = 256u,
.sector_size = 4u * 1024u,
};
#else
# error Boot Flash type not chosen!
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_flexspi_nor_flash.h
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/****************************************************************************
* boards/arm/imxrt/xidatong-arm32/src/imxrt_flexspi_nor_flash.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file imxrt_flexspi_nor_flash.h
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-23
*/
#ifndef __BOARDS_ARM_IMXRT_XIDATONG_ARM32_SRC_IMXRT_FLEXSPI_NOR_FLASH_H
#define __BOARDS_ARM_IMXRT_XIDATONG_ARM32_SRC_IMXRT_FLEXSPI_NOR_FLASH_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include <stdbool.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* FLEXSPI memory config block related definitions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346ul)
#define FLEXSPI_CFG_BLK_VERSION (0x56010400ul)
#define FLEXSPI_CFG_BLK_SIZE (512)
/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
/* Lookup table related definitions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0a
#define LEARN_DDR 0x2a
#define DATSZ_SDR 0x0b
#define DATSZ_DDR 0x2b
#define DUMMY_SDR 0x0c
#define DUMMY_DDR 0x2c
#define DUMMY_RWDS_SDR 0x0d
#define DUMMY_RWDS_DDR 0x2d
#define JMP_ON_CS 0x1f
#define STOP 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
#define FLEXSPI_LUT_OPERAND0_MASK (0xffu)
#define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t) \
(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & \
FLEXSPI_LUT_OPERAND0_MASK)
#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300u)
#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8u)
#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t) \
(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & \
FLEXSPI_LUT_NUM_PADS0_MASK)
#define FLEXSPI_LUT_OPCODE0_MASK (0xfc00u)
#define FLEXSPI_LUT_OPCODE0_SHIFT (10u)
#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t) \
(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & \
FLEXSPI_LUT_OPCODE0_MASK)
#define FLEXSPI_LUT_OPERAND1_MASK (0xff0000u)
#define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t) \
(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & \
FLEXSPI_LUT_OPERAND1_MASK)
#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000u)
#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24u)
#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t) \
(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & \
FLEXSPI_LUT_NUM_PADS1_MASK)
#define FLEXSPI_LUT_OPCODE1_MASK (0xfc000000u)
#define FLEXSPI_LUT_OPCODE1_SHIFT (26u)
#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & \
FLEXSPI_LUT_OPCODE1_MASK)
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \
FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
#define NOR_CMD_INDEX_READ CMD_INDEX_READ
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE
#define NOR_CMD_INDEX_ERASESECTOR 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE
#define NOR_CMD_INDEX_CHIPERASE 5
#define NOR_CMD_INDEX_DUMMY 6
#define NOR_CMD_INDEX_ERASEBLOCK 7
/* READ LUT sequence id in lookupTable stored in config block */
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ
/* Read Status LUT sequence id in lookupTable stored in config block */
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS
/* 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config
* block
*/
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2
/* 3 Write Enable sequence id in lookupTable stored in config block */
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE
/* 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config
* block
*/
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4
/* 5 Erase Sector sequence id in lookupTable stored in config block */
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
/* 8 Erase Block sequence id in lookupTable stored in config block */
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8
/* 9 Program sequence id in lookupTable stored in config block */
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE
/* 11 Chip Erase sequence in lookupTable id stored in config block */
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
/* 13 Read SFDP sequence in lookupTable id stored in config block */
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13
/* 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config
* block
*/
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14
/* 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config
* blobk
*/
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15
/****************************************************************************
* Public Types
****************************************************************************/
/* Definitions for FlexSPI Serial Clock Frequency */
enum flexspi_serial_clkfreq_e
{
FLEXSPI_SERIAL_CLKFREQ_30MHz = 1,
FLEXSPI_SERIAL_CLKFREQ_50MHz = 2,
FLEXSPI_SERIAL_CLKFREQ_60MHz = 3,
FLEXSPI_SERIAL_CLKFREQ_75MHz = 4,
FLEXSPI_SERIAL_CLKFREQ_80MHz = 5,
FLEXSPI_SERIAL_CLKFREQ_100MHz = 6,
FLEXSPI_SERIAL_CLKFREQ_133MHz = 7,
FLEXSPI_SERIAL_CLKFREQ_166MHz = 8,
FLEXSPI_SERIAL_CLKFREQ_200MHz = 9,
};
/* FlexSPI clock configuration type */
enum flexspi_serial_clockmode_e
{
FLEXSPI_CLKMODE_SDR,
FLEXSPI_CLKMODE_DDR,
};
/* FlexSPI Read Sample Clock Source definition */
enum flash_read_sample_clk_e
{
FLASH_READ_SAMPLE_CLK_LOOPBACK_INTERNELLY = 0,
FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_DQSPAD = 1,
FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_SCKPAD = 2,
FLASH_READ_SAMPLE_CLK_EXT_INPUT_FROM_DQSPAD = 3,
};
/* Misc feature bit definitions */
enum flash_misc_feature_e
{
FLEXSPIMISC_OFFSET_DIFFCLKEN = 0, /* Bit for Differential clock enable */
FLEXSPIMISC_OFFSET_CK2EN = 1, /* Bit for CK2 enable */
FLEXSPIMISC_OFFSET_PARALLELEN = 2, /* Bit for Parallel mode enable */
FLEXSPIMISC_OFFSET_WORD_ADDRESSABLE_EN = 3, /* Bit for Word Addressable enable */
FLEXSPIMISC_OFFSET_SAFECONFIG_FREQ_EN = 4, /* Bit for Safe Configuration Frequency enable */
FLEXSPIMISC_OFFSET_PAD_SETTING_OVERRIDE_EN = 5, /* Bit for Pad setting override enable */
FLEXSPIMISC_OFFSET_DDR_MODE_EN = 6, /* Bit for DDR clock confiuration indication. */
};
/* Flash Type Definition */
enum flash_flash_type_e
{
FLEXSPI_DEVICE_TYPE_SERIAL_NOR = 1, /* Flash devices are Serial NOR */
FLEXSPI_DEVICE_TYPE_SERIAL_NAND = 2, /* Flash devices are Serial NAND */
FLEXSPI_DEVICE_TYPE_SERIAL_RAM = 3, /* Flash devices are Serial RAM/HyperFLASH */
FLEXSPI_DEVICE_TYPE_MCP_NOR_NAND = 0x12, /* Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND */
FLEXSPI_DEVICE_TYPE_MCP_NOR_RAM = 0x13, /* Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs */
};
/* Flash Pad Definitions */
enum flash_flash_pad_e
{
SERIAL_FLASH_1PAD = 1,
SERIAL_FLASH_2PADS = 2,
SERIAL_FLASH_4PADS = 4,
SERIAL_FLASH_8PADS = 8,
};
/* Flash Configuration Command Type */
enum flash_config_cmd_e
{
DEVICE_CONFIG_CMD_TYPE_GENERIC, /* Generic command, for example: configure dummy cycles, drive strength, etc */
DEVICE_CONFIG_CMD_TYPE_QUADENABLE, /* Quad Enable command */
DEVICE_CONFIG_CMD_TYPE_SPI2XPI, /* Switch from SPI to DPI/QPI/OPI mode */
DEVICE_CONFIG_CMD_TYPE_XPI2SPI, /* Switch from DPI/QPI/OPI to SPI mode */
DEVICE_CONFIG_CMD_TYPE_SPI2NO_CMD, /* Switch to 0-4-4/0-8-8 mode */
DEVICE_CONFIG_CMD_TYPE_RESET, /* Reset device command */
};
/* FlexSPI LUT Sequence structure */
struct flexspi_lut_seq_s
{
uint8_t seq_num; /* Sequence Number, valid number: 1-16 */
uint8_t seq_id; /* Sequence Index, valid number: 0-15 */
uint16_t reserved;
};
/* FlexSPI Memory Configuration Block */
struct flexspi_mem_config_s
{
uint32_t tag;
uint32_t version;
uint32_t reserved0;
uint8_t read_sample_clksrc;
uint8_t cs_hold_time;
uint8_t cs_setup_time;
uint8_t column_address_width; /* [0x00f-0x00f] Column Address with, for
* HyperBus protocol, it is fixed to 3, For
* Serial NAND, need to refer to datasheet
*/
uint8_t device_mode_cfg_enable;
uint8_t device_mode_type;
uint16_t wait_time_cfg_commands;
struct flexspi_lut_seq_s device_mode_seq;
uint32_t device_mode_arg;
uint8_t config_cmd_enable;
uint8_t config_mode_type[3];
struct flexspi_lut_seq_s config_cmd_seqs[3];
uint32_t reserved1;
uint32_t config_cmd_args[3];
uint32_t reserved2;
uint32_t controller_misc_option;
uint8_t device_type;
uint8_t sflash_pad_type;
uint8_t serial_clk_freq;
uint8_t lut_custom_seq_enable;
uint32_t reserved3[2];
uint32_t sflash_a1size;
uint32_t sflash_a2size;
uint32_t sflash_b1size;
uint32_t sflash_b2size;
uint32_t cspad_setting_override;
uint32_t sclkpad_setting_override;
uint32_t datapad_setting_override;
uint32_t dqspad_setting_override;
uint32_t timeout_in_ms;
uint32_t command_interval;
uint16_t data_valid_time[2];
uint16_t busy_offset;
uint16_t busybit_polarity;
uint32_t lookup_table[64];
struct flexspi_lut_seq_s lut_customseq[12];
uint32_t reserved4[4];
};
/* Serial NOR configuration block */
struct flexspi_nor_config_s
{
struct flexspi_mem_config_s mem_config; /* Common memory configuration info via FlexSPI */
uint32_t page_size; /* Page size of Serial NOR */
uint32_t sector_size; /* Sector size of Serial NOR */
uint8_t ipcmd_serial_clkfreq; /* Clock frequency for IP command */
uint8_t is_uniform_blocksize; /* Sector/Block size is the same */
uint8_t reserved0[2]; /* Reserved for future use */
uint8_t serial_nor_type; /* Serial NOR Flash type: 0/1/2/3 */
uint8_t need_exit_nocmdmode; /* Need to exit NoCmd mode before other IP command */
uint8_t halfclk_for_nonreadcmd; /* Half the Serial Clock for non-read command: true/false */
uint8_t need_restore_nocmdmode; /* Need to Restore NoCmd mode after IP command execution */
uint32_t blocksize; /* Block size */
uint32_t reserve2[11]; /* Reserved for future use */
};
#endif /* __BOARDS_ARM_IMXRT_XIDATONG_ARM32_SRC_IMXRT_FLEXSPI_NOR_FLASH_H */
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_gpio.c
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/****************************************************************************
* boards/arm/imxrt/xidatong-arm32/src/imxrt_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file imxrt_gpio.c
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-23
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/clock.h>
#include <nuttx/wdog.h>
#include <nuttx/ioexpander/gpio.h>
#include <arch/board/board.h>
#include "chip.h"
#include <imxrt_gpio.h>
#include "xidatong-arm32.h"
#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF)
/****************************************************************************
* Private Types
****************************************************************************/
struct imxrtgpio_dev_s
{
struct gpio_dev_s gpio;
uint8_t id;
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
#if BOARD_NGPIOIN > 0
static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value);
#endif
#if BOARD_NGPIOOUT > 0
static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value);
static int gpout_write(FAR struct gpio_dev_s *dev, bool value);
#endif
/****************************************************************************
* Private Data
****************************************************************************/
#if BOARD_NGPIOIN > 0
static const struct gpio_operations_s gpin_ops =
{
.go_read = gpin_read,
.go_write = NULL,
.go_attach = NULL,
.go_enable = NULL,
};
/* This array maps the GPIO pins used as INPUT */
static const uint32_t g_gpioinputs[BOARD_NGPIOIN] =
{
GPIO_IN1,
};
static struct imxrtgpio_dev_s g_gpin[BOARD_NGPIOIN];
#endif
#if BOARD_NGPIOOUT > 0
static const struct gpio_operations_s gpout_ops =
{
.go_read = gpout_read,
.go_write = gpout_write,
.go_attach = NULL,
.go_enable = NULL,
};
/* This array maps the GPIO pins used as OUTPUT */
static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] =
{
GPIO_E220_M0,
GPIO_E220_M1,
};
static struct imxrtgpio_dev_s g_gpout[BOARD_NGPIOOUT];
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
#if BOARD_NGPIOIN > 0
static int gpin_read(FAR struct gpio_dev_s *dev, FAR bool *value)
{
FAR struct imxrtgpio_dev_s *imxrtgpio = (FAR struct imxrtgpio_dev_s *)dev;
DEBUGASSERT(imxrtgpio != NULL && value != NULL);
DEBUGASSERT(imxrtgpio->id < BOARD_NGPIOIN);
gpioinfo("Reading...\n");
*value = imxrt_gpio_read(g_gpioinputs[imxrtgpio->id]);
return OK;
}
#endif
#if BOARD_NGPIOOUT > 0
static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value)
{
FAR struct imxrtgpio_dev_s *imxrtgpio = (FAR struct imxrtgpio_dev_s *)dev;
DEBUGASSERT(imxrtgpio != NULL && value != NULL);
DEBUGASSERT(imxrtgpio->id < BOARD_NGPIOOUT);
gpioinfo("Reading...\n");
*value = imxrt_gpio_read(g_gpiooutputs[imxrtgpio->id]);
return OK;
}
static int gpout_write(FAR struct gpio_dev_s *dev, bool value)
{
FAR struct imxrtgpio_dev_s *imxrtgpio = (FAR struct imxrtgpio_dev_s *)dev;
DEBUGASSERT(imxrtgpio != NULL);
DEBUGASSERT(imxrtgpio->id < BOARD_NGPIOOUT);
gpioinfo("Writing %d\n", (int)value);
imxrt_gpio_write(g_gpiooutputs[imxrtgpio->id], value);
return OK;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_gpio_initialize
*
* Description:
* Initialize GPIO drivers for use with /apps/examples/gpio
*
****************************************************************************/
int imxrt_gpio_initialize(void)
{
int pincount;
int i;
#if BOARD_NGPIOIN > 0
pincount = 0;
for (i = 0; i < BOARD_NGPIOIN; i++)
{
/* Setup and register the GPIO pin */
g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN;
g_gpin[i].gpio.gp_ops = &gpin_ops;
g_gpin[i].id = i;
gpio_pin_register(&g_gpin[i].gpio, pincount);
/* Configure the pin that will be used as input */
imxrt_config_gpio(g_gpioinputs[i]);
pincount++;
}
#endif
#if BOARD_NGPIOOUT > 0
pincount = 0;
for (i = 0; i < BOARD_NGPIOOUT; i++)
{
/* Setup and register the GPIO pin */
g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN;
g_gpout[i].gpio.gp_ops = &gpout_ops;
g_gpout[i].id = i;
gpio_pin_register(&g_gpout[i].gpio, pincount);
/* Configure the pin that will be used as output */
imxrt_gpio_write(g_gpiooutputs[i], 0);
imxrt_config_gpio(g_gpiooutputs[i]);
pincount++;
}
#endif
return 0;
}
#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_gt9xx.c
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/****************************************************************************
* boards/arm/imxrt/xidatong-arm32/src/imxrt_gt9xx.c
*
* Copyright 2019 ElFaro LAB S.L. All rights reserved.
* Author: Fabio Balzano <fabio@elfarolab.com>
*
* Based on boards/arm/lpc54xx/lpcxpresso-lpc54628/src/lpc54_ft5x06.c
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/**
* @file imxrt_gt9xx.c
* @brief gt9xx touch driver refer to imxrt_ft5x06.c
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.5.31
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <syslog.h>
#include <assert.h>
#include <errno.h>
#include <nuttx/arch.h>
#include <nuttx/i2c/i2c_master.h>
#include <nuttx/input/gt9xx.h>
#include "imxrt_config.h"
#include "imxrt_gpio.h"
#include "imxrt_lpi2c.h"
#include "arch/chip/irq.h"
#include "imxrt_iomuxc.h"
#define gt_print printf
#define GT9XX_I2C_ADDRESS 0x5D
#define GPIO_GT9XX_INTR IMXRT_IRQ_GPIO2_30
#define IOMUX_GT9XX_RST (IOMUX_PULL_NONE | IOMUX_CMOS_OUTPUT | \
IOMUX_DRIVE_40OHM | IOMUX_SPEED_MEDIUM | \
IOMUX_SLEW_SLOW)
#define GPIO_GT9XX_CTRSTN (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | \
GPIO_PORT2 | GPIO_PIN30 | IOMUX_GT9XX_RST)
#define GPIO_GT9XX_CTINTN (GPIO_INTERRUPT | GPIO_INT_RISINGEDGE | \
IOMUX_SW_DEFAULT | GPIO_PORT2 | GPIO_PIN30 )
#ifdef CONFIG_INPUT_GT9XX
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define GT9XX_FREQUENCY 400000
/****************************************************************************
* Private Function Ptototypes
****************************************************************************/
#ifndef CONFIG_GT9XX_POLLMODE
static int imxrt_gt9xx_attach(FAR const struct gt9xx_config_s *config,
xcpt_t isr, FAR void *arg);
static void imxrt_gt9xx_enable(FAR const struct gt9xx_config_s *config,
bool enable);
static void imxrt_gt9xx_clear(FAR const struct gt9xx_config_s *config);
#endif
static void imxrt_gt9xx_wakeup(FAR const struct gt9xx_config_s *config);
static void imxrt_gt9xx_nreset(FAR const struct gt9xx_config_s *config,
bool state);
/****************************************************************************
* Private Data
****************************************************************************/
static const struct gt9xx_config_s g_gt9xx_config =
{
.address = GT9XX_I2C_ADDRESS,
.frequency = GT9XX_FREQUENCY,
#ifndef CONFIG_GT9XX_POLLMODE
.attach = imxrt_gt9xx_attach,
.enable = imxrt_gt9xx_enable,
.clear = imxrt_gt9xx_clear,
#endif
.wakeup = imxrt_gt9xx_wakeup,
.nreset = imxrt_gt9xx_nreset
};
#ifndef CONFIG_GT9XX_POLLMODE
static uint8_t g_gt9xx_irq;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_gt9xx_attach
*
* Description:
* Attach an GT9XX interrupt handler to a GPIO interrupt
*
****************************************************************************/
#ifndef CONFIG_GT9XX_POLLMODE
static int imxrt_gt9xx_attach(FAR const struct gt9xx_config_s *config,
xcpt_t isr, FAR void *arg)
{
return irq_attach(g_gt9xx_irq, isr, arg);
}
#endif
/****************************************************************************
* Name: imxrt_gt9xx_enable
*
* Description:
* Enable or disable a GPIO interrupt
*
****************************************************************************/
#ifndef CONFIG_GT9XX_POLLMODE
static void imxrt_gt9xx_enable(FAR const struct gt9xx_config_s *config,
bool enable)
{
if (enable)
{
up_enable_irq(g_gt9xx_irq);
}
else
{
up_disable_irq(g_gt9xx_irq);
}
}
#endif
/****************************************************************************
* Name: imxrt_gt9xx_clear
*
* Description:
* Acknowledge/clear any pending GPIO interrupt
*
****************************************************************************/
#ifndef CONFIG_GT9XX_POLLMODE
static void imxrt_gt9xx_clear(FAR const struct gt9xx_config_s *config)
{
imxrt_gpioirq_disable(g_gt9xx_irq);
}
#endif
/****************************************************************************
* Name: imxrt_gt9xx_wakeup
*
* Description:
* Issue WAKE interrupt to GT9XX to change the GT9XX from Hibernate to
* Active mode.
*
****************************************************************************/
static void imxrt_gt9xx_wakeup(FAR const struct gt9xx_config_s *config)
{
/* We do not have access to the WAKE pin in the implementation */
}
/****************************************************************************
* Name: imxrt_gt9xx_nreset
*
* Description:
* Control the chip reset pin (active low)
*
****************************************************************************/
static void imxrt_gt9xx_nreset(FAR const struct gt9xx_config_s *config,
bool nstate)
{
imxrt_gpio_write(GPIO_GT9XX_CTRSTN, nstate);
}
/****************************************************************************
* Public Functions
****************************************************************************/
#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U)
#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)
#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)
#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
#define IOMUXC_GPIO_B1_14_GPIO2_IO30 0x401F81B4U, 0x5U, 0, 0, 0x401F83A4U
static inline void IOMUXC_SetPinMux(uint32_t muxRegister,
uint32_t muxMode,
uint32_t inputRegister,
uint32_t inputDaisy,
uint32_t configRegister,
uint32_t inputOnfield)
{
*((volatile uint32_t *)muxRegister) =
IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
if (inputRegister)
{
*((volatile uint32_t *)inputRegister) = inputDaisy;
}
}
static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
uint32_t muxMode,
uint32_t inputRegister,
uint32_t inputDaisy,
uint32_t configRegister,
uint32_t configValue)
{
if (configRegister)
{
*((volatile uint32_t *)configRegister) = configValue;
}
}
void imxrt_config_gt9xx_pins(void)
{
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_14_GPIO2_IO30, /* WAKEUP is configured as GPIO5_IO00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_14_GPIO2_IO30,
0x10B0u);
}
/****************************************************************************
* Name: imxrt_gt9xx_register
*
* Description:
* Register the GT9XX touch panel driver
*
****************************************************************************/
int imxrt_gt9xx_register(void)
{
FAR struct i2c_master_s *i2c;
int ret;
/* Initialize CTRSTN pin */
imxrt_config_gpio(GPIO_GT9XX_CTRSTN);
imxrt_gpio_write(GPIO_GT9XX_CTRSTN, false);
#ifndef CONFIG_GT9XX_POLLMODE
int irq;
/* Initialize GPIO interrupt pin. */
imxrt_config_gpio(GPIO_GT9XX_CTINTN);
irq = GPIO_GT9XX_INTR;
DEBUGASSERT(irq > 0 && irq < UINT8_MAX);
g_gt9xx_irq = (uint8_t)irq;
/* Make sure that the interrupt is disabled at the NVIC */
imxrt_gpioirq_disable(irq);
up_disable_irq(irq);
#endif
/* Take the GT9XX out of reset */
/* The GT9XX is on LPI2C1. Get the handle and register the GT9XX device */
i2c = imxrt_i2cbus_initialize(1);
if (i2c == NULL)
{
syslog(LOG_ERR, "ERROR: Failed to get LPI2C1 interface\n");
return -ENODEV;
}
else
{
ret = gt9xx_register(i2c, &g_gt9xx_config, 0);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Failed to register GT9XX driver: %d\n", ret);
imxrt_gpio_write(GPIO_GT9XX_CTRSTN, false);
imxrt_i2cbus_uninitialize(i2c);
return ret;
}
}
return OK;
}
#endif /* CONFIG_INPUT_GT9XX*/
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_gt9xx.h
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/*
* Copyright (c) 2022 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file imxrt_gt9xx.h
* @brief API for imxrt gt9xx.
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.5.31
*/
#ifndef __IMXRT_GT9XX_H_
#define __IMXRT_GT9XX_H_
int imxrt_gt9xx_register(void);
#endif /* __IMXRT_GT9XX_H__ */
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_lcd.c
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/****************************************************************************
* boards/arm/imxrt/xidatong-arm32/src/imxrt_lcd.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file imxrt_lcd.c
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-23
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <debug.h>
#include "imxrt_lcd.h"
#include "imxrt_gpio.h"
#include "xidatong-arm32.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_lcd_initialize
*
* Description:
* Initialize the LCD. Setup backlight (initially off)
*
****************************************************************************/
void imxrt_lcd_initialize(void)
{
/* Configure the LCD backlight (and turn the backlight off) */
imxrt_config_gpio(GPIO_LCD_BL);
}
/****************************************************************************
* Name: imxrt_backlight
*
* Description:
* If CONFIG_IMXRT_LCD_BACKLIGHT is defined, then the board-specific
* logic must provide this interface to turn the backlight on and off.
*
****************************************************************************/
#ifdef CONFIG_IMXRT_LCD_BACKLIGHT
void imxrt_backlight(bool blon)
{
imxrt_gpio_write(GPIO_LCD_BL, blon); /* High illuminates */
}
#endif
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_mmcsd.c
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file imxrt_sdhc_automount.c
* @brief imxrt board sd card automount
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.04.12
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdio.h>
#include <debug.h>
#include <errno.h>
#include <debug.h>
#include "xidatong-arm32.h"
#ifdef CONFIG_IMXRT_USDHC
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: nsh_sdmmc_initialize
*
* Description:
* Initialize the SDHC SD card slot
*
****************************************************************************/
int nsh_sdmmc_initialize(void)
{
struct sdio_dev_s *sdmmc;
int ret = 0;
/* Get an instance of the SDIO interface */
sdmmc = imxrt_usdhc_initialize(0);
if (!sdmmc)
{
syslog(LOG_ERR, "ERROR: Failed to initialize SD/MMC\n");
return -ENODEV;
}
/* Bind the SDIO interface to the MMC/SD driver */
ret = mmcsd_slotinitialize(0, sdmmc);
if (ret != OK)
{
syslog(LOG_ERR, "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret);
return ret;
}
#ifdef CONFIG_XIDATONG_ARM32_SDIO_AUTOMOUNT
imxrt_automount_initialize();
imxrt_usdhc_set_sdio_card_isr(sdmmc, imxrt_sdhc_automount_event, NULL);
#else
imxrt_usdhc_set_sdio_card_isr(sdmmc, NULL, NULL);
#endif
return OK;
}
#endif
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_mmcsd_automount.c
+330
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file imxrt_sdhc_automount.c
* @brief imxrt board sd card automount
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.04.07
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_FS_AUTOMOUNTER_DEBUG) && !defined(CONFIG_DEBUG_FS)
# define CONFIG_DEBUG_FS 1
#endif
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/clock.h>
#include <nuttx/fs/automount.h>
#include "hardware/imxrt_pinmux.h"
#include "xidatong-arm32.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef NULL
# define NULL (FAR void *)0
#endif
#ifndef OK
# define OK 0
#endif
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure represents the changeable state of the automounter */
struct imxrt_automount_state_s
{
volatile automount_handler_t handler; /* Upper half handler */
FAR void *arg; /* Handler argument */
bool enable; /* Fake interrupt enable */
bool pending; /* Set if there an event while disabled */
};
/* This structure represents the static configuration of an automounter */
struct imxrt_automount_config_s
{
/* This must be first thing in structure so that we can simply cast from
* struct automount_lower_s to struct imxrt_automount_config_s
*/
struct automount_lower_s lower; /* Publicly visible part */
FAR struct imxrt_automount_state_s *state; /* Changeable state */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static int imxrt_sdhc_attach(FAR const struct automount_lower_s *lower,
automount_handler_t isr, FAR void *arg);
static void imxrt_sdhc_enable(FAR const struct automount_lower_s *lower,
bool enable);
static bool imxrt_sdhc_inserted(FAR const struct automount_lower_s *lower);
/****************************************************************************
* Private Data
****************************************************************************/
static struct imxrt_automount_state_s g_sdhc_state;
static const struct imxrt_automount_config_s g_sdhc_config =
{
.lower =
{
.fstype = CONFIG_XIDATONG_ARM32_SDIO_AUTOMOUNT_FSTYPE,
.blockdev = CONFIG_XIDATONG_ARM32_SDIO_AUTOMOUNT_BLKDEV,
.mountpoint = CONFIG_XIDATONG_ARM32_SDIO_AUTOMOUNT_MOUNTPOINT,
.ddelay = MSEC2TICK(CONFIG_XIDATONG_ARM32_SDIO_AUTOMOUNT_DDELAY),
.udelay = MSEC2TICK(CONFIG_XIDATONG_ARM32_SDIO_AUTOMOUNT_UDELAY),
.attach = imxrt_sdhc_attach,
.enable = imxrt_sdhc_enable,
.inserted = imxrt_sdhc_inserted
},
.state = &g_sdhc_state
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_sdhc_attach
*
* Description:
* Attach a new SDHC event handler
*
* Input Parameters:
* lower - An instance of the auto-mounter lower half state structure
* isr - The new event handler to be attach
* arg - Client data to be provided when the event handler is invoked.
*
* Returned Value:
* Always returns OK
*
****************************************************************************/
static int imxrt_sdhc_attach(FAR const struct automount_lower_s *lower,
automount_handler_t isr, FAR void *arg)
{
FAR const struct imxrt_automount_config_s *config;
FAR struct imxrt_automount_state_s *state;
/* Recover references to our structure */
config = (FAR struct imxrt_automount_config_s *)lower;
DEBUGASSERT(config != NULL && config->state != NULL);
state = config->state;
/* Save the new handler info (clearing the handler first to eliminate race
* conditions).
*/
state->handler = NULL;
state->pending = false;
state->arg = arg;
state->handler = isr;
return OK;
}
/****************************************************************************
* Name: imxrt_sdhc_enable
*
* Description:
* Enable card insertion/removal event detection
*
* Input Parameters:
* lower - An instance of the auto-mounter lower half state structure
* enable - True: enable event detection; False: disable
*
* Returned Value:
* None
*
****************************************************************************/
static void imxrt_sdhc_enable(FAR const struct automount_lower_s *lower,
bool enable)
{
FAR const struct imxrt_automount_config_s *config;
FAR struct imxrt_automount_state_s *state;
irqstate_t flags;
/* Recover references to our structure */
config = (FAR struct imxrt_automount_config_s *)lower;
DEBUGASSERT(config != NULL && config->state != NULL);
state = config->state;
/* Save the fake enable setting */
flags = enter_critical_section();
state->enable = enable;
/* Did an interrupt occur while interrupts were disabled? */
if (enable && state->pending)
{
/* Yes.. perform the fake interrupt if the interrutp is attached */
if (state->handler)
{
uint8_t inserted = imxrt_gpio_read(PIN_USDHC1_CD);
if (0 == inserted)
{
state->handler(&config->lower, state->arg, true);
}
else
{
state->handler(&config->lower, state->arg, false);
}
}
state->pending = false;
}
leave_critical_section(flags);
}
/****************************************************************************
* Name: imxrt_sdhc_inserted
*
* Description:
* Check if a card is inserted into the slot.
*
* Input Parameters:
* lower - An instance of the auto-mounter lower half state structure
*
* Returned Value:
* True if the card is inserted; False otherwise
*
****************************************************************************/
static bool imxrt_sdhc_inserted(FAR const struct automount_lower_s *lower)
{
uint8_t inserted = imxrt_gpio_read(PIN_USDHC1_CD);
if (0 == inserted)
{
return true;
}
return false;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_sdhc_automount_event
*
* Description:
* The SDHC card detection logic has detected an insertion or removal
* event.
* It has already scheduled the MMC/SD block driver operations.
* Now we need to schedule the auto-mount event which will occur with a
* substantial delay to make sure that everything has settle down.
*
* Input Parameters:
* slotno - Identifies the SDHC0 slot: SDHC0_SLOTNO or SDHC1_SLOTNO.
* There is a terminology problem here: Each SDHC supports two slots,
* slot A and slot B. Only slot A is used.
* So this is not a really a slot, but an HSCMI peripheral number.
* inserted - True if the card is inserted in the slot. False otherwise.
*
* Returned Value:
* None
*
* Assumptions:
* Interrupts are disabled.
*
****************************************************************************/
int imxrt_sdhc_automount_event(void *arg)
{
FAR const struct imxrt_automount_config_s *config = &g_sdhc_config;
FAR struct imxrt_automount_state_s *state = &g_sdhc_state;
/* Is the auto-mounter interrupt attached? */
if (state->handler)
{
/* Yes.. Have we been asked to hold off interrupts? */
if (!state->enable)
{
/* Yes.. just remember that there is a pending interrupt. We will
* deliver the interrupt when interrupts are "re-enabled."
*/
state->pending = true;
}
else
{
/* No.. forward the event to the handler */
uint8_t inserted = imxrt_gpio_read(PIN_USDHC1_CD);
if (0 == inserted)
{
state->handler(&config->lower, state->arg, true);
}
else
{
state->handler(&config->lower, state->arg, false);
}
}
}
return 0;
}
/****************************************************************************
* Name: imxrt_automount_initialize
*
* Description:
* Configure auto-mounters for each enable and so configured SDHC
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void imxrt_automount_initialize(void)
{
FAR void *handle;
finfo("Initializing automounter(s)\n");
/* Initialize the SDHC0 auto-mounter */
handle = automount_initialize(&g_sdhc_config.lower);
if (!handle)
{
ferr("ERROR: Failed to initialize auto-mounter for SDHC0\n");
}
}
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_mmcsd_spi.c
+131
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/****************************************************************************
* boards/arm/imxrt/xidatong-arm32/src/imxrt_mmcsd_spi.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file imxrt_mmcsd_spi.c
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-23
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <debug.h>
#include <nuttx/config.h>
#include <nuttx/mmcsd.h>
#include <stdint.h>
#include <stdbool.h>
#include <nuttx/spi/spi.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "chip.h"
#include "imxrt_lpspi.h"
#ifdef CONFIG_MMCSD_SPI
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef CONFIG_IMXRT_LPSPI1
# error "SD driver requires CONFIG_IMXRT_LPSPI1 to be enabled"
#endif
#ifdef CONFIG_DISABLE_MOUNTPOINT
# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled"
#endif
/****************************************************************************
* Private Definitions
****************************************************************************/
static const int SD_SPI_PORT = CONFIG_NSH_MMCSDSPIPORTNO; /* SD is connected to SPI1 port */
static const int SD_SLOT_NO = 0; /* There is only one SD slot */
/****************************************************************************
* Private Functions
****************************************************************************/
/* NOTE: We are using a SDCard adapter/module without Card Detect pin!
* Then we don't need to Card Detect callback here.
*/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_spi1register
*
* Description:
* Registers media change callback
****************************************************************************/
#ifdef CONFIG_IMXRT_LPSPI1
int imxrt_lpspi1register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg)
{
spiinfo("INFO: Registering spi1 device\n");
return OK;
}
#endif
/****************************************************************************
* Name: imxrt_mmcsd_spi_initialize
*
* Description:
* Initialize SPI-based SD card and card detect thread.
*
****************************************************************************/
int imxrt_mmcsd_spi_initialize(int minor)
{
struct spi_dev_s *spi;
int rv;
mcinfo("INFO: Initializing mmcsd card\n");
spi = imxrt_lpspibus_initialize(SD_SPI_PORT);
if (spi == NULL)
{
mcerr("ERROR: Failed to initialize SPI port %d\n", SD_SPI_PORT);
return -ENODEV;
}
rv = mmcsd_spislotinitialize(minor, SD_SLOT_NO, spi);
if (rv < 0)
{
mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n",
SD_SPI_PORT, SD_SLOT_NO);
return rv;
}
spiinfo("INFO: mmcsd card has been initialized successfully\n");
return OK;
}
#endif /* CONFIG_MMCSD_SPI */
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_reset.c
+61
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file imxrt_reset.c
* @brief imxrt board sd card automount
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022.04.29
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/board.h>
#include <nuttx/arch.h>
#ifdef CONFIG_BOARDCTL_RESET
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_reset
*
* Description:
* Reset board. Support for this function is required by board-level
* logic if CONFIG_BOARDCTL_RESET is selected.
*
* Input Parameters:
* status - Status information provided with the reset event. This
* meaning of this status information is board-specific. If not
* used by a board, the value zero may be provided in calls to
* board_reset().
*
* Returned Value:
* If this function returns, then it was not possible to power-off the
* board due to some constraints. The return value int this case is a
* board-specific reason for the failure to shutdown.
*
****************************************************************************/
int board_reset(int status)
{
up_systemreset();
return 0;
}
#endif /* CONFIG_BOARDCTL_RESET */
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_sdram_ini_dcd.c
+1266
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Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_spi.c
+220
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/****************************************************************************
* boards/arm/imxrt/xidatong-arm32/src/imxrt_spi.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file imxrt_spi.c
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-23
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/spi/spi.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "imxrt_config.h"
#include "imxrt_lpspi.h"
#include "imxrt_gpio.h"
#include "xidatong-arm32.h"
#if defined(CONFIG_IMXRT_LPSPI1) || defined(CONFIG_IMXRT_LPSPI2) || \
defined(CONFIG_IMXRT_LPSPI3) || defined(CONFIG_IMXRT_LPSPI4)
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_spidev_initialize
*
* Description:
* Called to configure SPI chip select GPIO pins for the xidatong-arm32
* board.
*
****************************************************************************/
void weak_function imxrt_spidev_initialize(void)
{
#ifdef CONFIG_IMXRT_LPSPI1
imxrt_config_gpio(GPIO_LPSPI1_CS); /* LPSPI1 chip select */
imxrt_config_gpio(GPIO_MMCSD_EN);
#endif
#ifdef CONFIG_IMXRT_LPSPI3
imxrt_config_gpio(GPIO_LPSPI3_CS); /* LPSPI3 chip select */
#endif
}
/****************************************************************************
* Name: imxrt_lpspi1/2/3select and imxrt_lpspi1/2/3status
*
* Description:
* The external functions, imxrt_lpspi1/2/3select and
* imxrt_lpspi1/2/3status must be provided by board-specific logic.
* They are implementations of the select and status methods of the SPI
* interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h).
* All other methods (including imxrt_lpspibus_initialize()) are provided
* by common STM32 logic. To use this common SPI logic on your board:
*
* 1. Provide logic in imxrt_boardinitialize() to configure SPI chip select
* pins.
* 2. Provide imxrt_lpspi1/2/3select() and imxrt_lpspi1/2/3status()
* functions in your board-specific logic.
* These functions will perform chip selection and status operations
* using GPIOs in the way your board is configured.
* 3. Add a calls to imxrt_lpspibus_initialize() in your low level
* application initialization logic
* 4. The handle returned by imxrt_lpspibus_initialize() may then be used
* to bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
****************************************************************************/
#ifdef CONFIG_IMXRT_LPSPI1
void imxrt_lpspi1select(FAR struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid,
selected ? "assert" : "de-assert");
imxrt_gpio_write(GPIO_LPSPI1_CS, !selected);
}
uint8_t imxrt_lpspi1status(FAR struct spi_dev_s *dev, uint32_t devid)
{
return 0;
}
#endif
#ifdef CONFIG_IMXRT_LPSPI2
void imxrt_lpspi2select(FAR struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid,
selected ? "assert" : "de-assert");
imxrt_gpio_write(GPIO_LPSPI2_CS, !selected);
}
uint8_t imxrt_lpspi2status(FAR struct spi_dev_s *dev, uint32_t devid)
{
return 0;
}
#endif
#ifdef CONFIG_IMXRT_LPSPI3
void imxrt_lpspi3select(FAR struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid,
selected ? "assert" : "de-assert");
imxrt_gpio_write(GPIO_LPSPI3_CS, !selected);
}
uint8_t imxrt_lpspi3status(FAR struct spi_dev_s *dev, uint32_t devid)
{
return 0;
}
#endif
#ifdef CONFIG_IMXRT_LPSPI4
void imxrt_lpspi4select(FAR struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
spiinfo("devid: %d CS: %s\n", (int)devid,
selected ? "assert" : "de-assert");
imxrt_gpio_write(GPIO_LPSPI4_CS, !selected);
}
uint8_t imxrt_lpspi4status(FAR struct spi_dev_s *dev, uint32_t devid)
{
return 0;
}
#endif
/****************************************************************************
* Name: imxrt_lpspi1cmddata
*
* Description:
* Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true)
* or command (false). This function must be provided by platform-specific
* logic. This is an implementation of the cmddata method of the SPI
* interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h).
*
* Input Parameters:
*
* spi - SPI device that controls the bus the device that requires the CMD/
* DATA selection.
* devid - If there are multiple devices on the bus, this selects which one
* to select cmd or data. NOTE: This design restricts, for example,
* one one SPI display per SPI bus.
* cmd - true: select command; false: select data
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_SPI_CMDDATA
#ifdef CONFIG_IMXRT_LPSPI1
int imxrt_lpspi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_IMXRT_LPSPI2
int imxrt_lpspi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_IMXRT_LPSPI3
int imxrt_lpspi3cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#ifdef CONFIG_IMXRT_LPSPI4
int imxrt_lpspi4cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
{
return -ENODEV;
}
#endif
#endif /* CONFIG_SPI_CMDDATA */
#endif /* CONFIG_IMXRT_LPSPI1 || CONFIG_IMXRT_LPSPI2 */
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_usbhost.c
+467
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/****************************************************************************
* boards/arm/imxrt/imxrt1020-evk/src/imxrt_usbhost.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <sched.h>
#include <errno.h>
#include <assert.h>
#include <debug.h>
#include <sys/mount.h>
#include <nuttx/fs/fs.h>
#include <nuttx/irq.h>
#include <nuttx/kthread.h>
#include <nuttx/usb/usbdev.h>
#include <nuttx/usb/usbhost.h>
#include <nuttx/usb/usbdev_trace.h>
#include <nuttx/usb/ehci.h>
#include <nuttx/wdog.h>
#include <imxrt_ehci.h>
#include "hardware/imxrt_pinmux.h"
#include "hardware/imxrt_usbotg.h"
#include "imxrt_periphclks.h"
#include "xidatong-arm32.h"
#include <arch/board/board.h> /* Must always be included last */
#if defined(CONFIG_IMXRT_USBOTG) || defined(CONFIG_USBHOST)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef CONFIG_USBHOST_DEFPRIO
# define CONFIG_USBHOST_DEFPRIO 50
#endif
#ifndef CONFIG_USBHOST_STACKSIZE
# ifdef CONFIG_USBHOST_HUB
# define CONFIG_USBHOST_STACKSIZE 1536
# else
# define CONFIG_USBHOST_STACKSIZE 1024
# endif
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/* Retained device driver handle */
static struct usbhost_connection_s *g_ehciconn;
#ifdef CONFIG_XIDATONG_ARM32_USB_AUTOMOUNT
/* Unmount retry timer */
static struct wdog_s g_umount_tmr[CONFIG_XIDATONG_ARM32_USB_AUTOMOUNT_NUM_BLKDEV];
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: ehci_waiter
*
* Description:
* Wait for USB devices to be connected to the EHCI root hub.
*
****************************************************************************/
static int ehci_waiter(int argc, char *argv[])
{
FAR struct usbhost_hubport_s *hport;
uinfo("ehci_waiter: Running\n");
for (; ; )
{
/* Wait for the device to change state */
DEBUGVERIFY(CONN_WAIT(g_ehciconn, &hport));
uinfo("ehci_waiter: %s\n", hport->connected ? "connected" : "disconnected");
/* Did we just become connected? */
if (hport->connected)
{
/* Yes.. enumerate the newly connected device */
CONN_ENUMERATE(g_ehciconn, hport);
}
}
/* Keep the compiler from complaining */
return 0;
}
/****************************************************************************
* Public Functions
****************************************************************************/
#ifdef CONFIG_XIDATONG_ARM32_USB_AUTOMOUNT
/****************************************************************************
* Name: usb_msc_connect
*
* Description:
* Mount the USB mass storage device
*
****************************************************************************/
static void usb_msc_connect(FAR void *arg)
{
int index = (int)arg;
char sdchar = 'a' + index;
int ret;
char blkdev[32];
char mntpnt[32];
DEBUGASSERT(index >= 0 &&
index < CONFIG_XIDATONG_ARM32_USB_AUTOMOUNT_NUM_BLKDEV);
wd_cancel(&g_umount_tmr[index]);
/* Resetup the event. */
usbhost_msc_notifier_setup(usb_msc_connect, WORK_USB_MSC_CONNECT,
sdchar, arg);
snprintf(blkdev, sizeof(blkdev), "%s%c",
CONFIG_XIDATONG_ARM32_USB_AUTOMOUNT_BLKDEV, sdchar);
snprintf(mntpnt, sizeof(mntpnt), "%s%c",
CONFIG_XIDATONG_ARM32_USB_AUTOMOUNT_MOUNTPOINT, sdchar);
/* Mount */
ret = nx_mount((FAR const char *)blkdev, (FAR const char *)mntpnt,
CONFIG_XIDATONG_ARM32_USB_AUTOMOUNT_FSTYPE, 0, NULL);
if (ret < 0)
{
ferr("ERROR: Mount failed: %d\n", ret);
}
}
/****************************************************************************
* Name: unmount_retry_timeout
*
* Description:
* A previous unmount failed because the volume was busy... busy meaning
* the volume could not be unmounted because there are open references
* the files or directories in the volume. When this failure occurred,
* the unmount logic setup a delay and this function is called as a result
* of that delay timeout.
*
* This function will attempt the unmount again.
*
* Input Parameters:
* Standard wdog timeout parameters
*
* Returned Value:
* None
*
****************************************************************************/
static void unmount_retry_timeout(wdparm_t arg)
{
int index = arg;
char sdchar = 'a' + index;
finfo("Timeout!\n");
DEBUGASSERT(index >= 0 &&
index < CONFIG_XIDATONG_ARM32_USB_AUTOMOUNT_NUM_BLKDEV);
/* Resend the notification. */
usbhost_msc_notifier_signal(WORK_USB_MSC_DISCONNECT, sdchar);
}
/****************************************************************************
* Name: usb_msc_disconnect
*
* Description:
* Unmount the USB mass storage device
*
****************************************************************************/
static void usb_msc_disconnect(FAR void *arg)
{
int index = (int)arg;
char sdchar = 'a' + index;
int ret;
char mntpnt[32];
DEBUGASSERT(index >= 0 &&
index < CONFIG_XIDATONG_ARM32_USB_AUTOMOUNT_NUM_BLKDEV);
wd_cancel(&g_umount_tmr[index]);
/* Resetup the event. */
usbhost_msc_notifier_setup(usb_msc_disconnect, WORK_USB_MSC_DISCONNECT,
sdchar, arg);
snprintf(mntpnt, sizeof(mntpnt), "%s%c",
CONFIG_XIDATONG_ARM32_USB_AUTOMOUNT_MOUNTPOINT, sdchar);
/* Unmount */
ret = nx_umount2((FAR const char *)mntpnt, MNT_FORCE);
if (ret < 0)
{
/* We expect the error to be EBUSY meaning that the volume could
* not be unmounted because there are currently reference via open
* files or directories.
*/
if (ret == -EBUSY)
{
finfo("WARNING: Volume is busy, try again later\n");
/* Start a timer to retry the umount2 after a delay */
ret = wd_start(&g_umount_tmr[index],
MSEC2TICK(CONFIG_XIDATONG_ARM32_USB_AUTOMOUNT_UDELAY),
unmount_retry_timeout, index);
if (ret < 0)
{
ferr("ERROR: wd_start failed: %d\n", ret);
}
}
/* Other errors are fatal */
else
{
ferr("ERROR: Unmount failed!\n");
}
}
}
#endif /* CONFIG_XIDATONG_ARM32_USB_AUTOMOUNT */
/****************************************************************************
* Name: imxrt_usbhost_initialize
*
* Description:
* Called at application startup time to initialize the USB host
* functionality.
* This function will start a thread that will monitor for device
* connection/disconnection events.
*
****************************************************************************/
int imxrt_usbhost_initialize(void)
{
pid_t pid;
int ret;
#ifdef CONFIG_XIDATONG_ARM32_USB_AUTOMOUNT
int index;
#endif
imxrt_clockall_usboh3();
/* Make sure we don't accidentally switch on USB bus power */
*((uint32_t *)IMXRT_USBNC_USB_OTG2_CTRL) = USBNC_PWR_POL;
*((uint32_t *)0x400d9030) = (1 << 21);
*((uint32_t *)0x400d9000) = 0;
/* Setup pins, with power initially off */
imxrt_config_gpio(GPIO_USBOTG_ID);
/* First, register all of the class drivers needed to support the drivers
* that we care about
*/
#ifdef CONFIG_USBHOST_HUB
/* Initialize USB hub support */
ret = usbhost_hub_initialize();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: usbhost_hub_initialize failed: %d\n", ret);
}
#endif
#ifdef CONFIG_USBHOST_MSC
/* Register the USB host Mass Storage Class */
#ifdef CONFIG_XIDATONG_ARM32_USB_AUTOMOUNT
/* Initialize the notifier listener for automount */
for (index = 0; index < CONFIG_XIDATONG_ARM32_USB_AUTOMOUNT_NUM_BLKDEV; index++)
{
char sdchar = 'a' + index;
usbhost_msc_notifier_setup(usb_msc_connect,
WORK_USB_MSC_CONNECT, sdchar, (FAR void *)(intptr_t)index);
usbhost_msc_notifier_setup(usb_msc_disconnect,
WORK_USB_MSC_DISCONNECT, sdchar, (FAR void *)(intptr_t)index);
}
#endif
ret = usbhost_msc_initialize();
if (ret != OK)
{
syslog(LOG_ERR,
"ERROR: Failed to register the mass storage class: %d\n", ret);
}
#endif
#ifdef CONFIG_USBHOST_CDCACM
/* Register the CDC/ACM serial class */
ret = usbhost_cdcacm_initialize();
if (ret != OK)
{
uerr("ERROR: Failed to register the CDC/ACM serial class\n");
}
#endif
#ifdef CONFIG_USBHOST_HIDKBD
/* Register the USB host HID keyboard class driver */
ret = usbhost_kbdinit();
if (ret != OK)
{
uerr("ERROR: Failed to register the KBD class\n");
}
#endif
/* Then get an instance of the USB EHCI interface. */
g_ehciconn = imxrt_ehci_initialize(0);
if (!g_ehciconn)
{
uerr("ERROR: imxrt_ehci_initialize failed\n");
return -ENODEV;
}
/* Start a thread to handle device connection. */
pid = kthread_create("EHCI Monitor", CONFIG_USBHOST_DEFPRIO,
CONFIG_USBHOST_STACKSIZE,
(main_t)ehci_waiter, (FAR char * const *)NULL);
if (pid < 0)
{
uerr("ERROR: Failed to create ehci_waiter task: %d\n", ret);
return -ENODEV;
}
return OK;
}
/****************************************************************************
* Name: imxrt_usbhost_vbusdrive
*
* Description:
* Enable/disable driving of VBUS 5V output. This function must be
* provided by each platform that implements the OHCI or EHCI host
* interface
*
* Input Parameters:
* rhport - Selects root hub port to be powered host interface.
* Since the IMXRT has only a downstream port, zero is
* the only possible value for this parameter.
* enable - true: enable VBUS power; false: disable VBUS power
*
* Returned Value:
* None
*
****************************************************************************/
#define HCOR ((volatile struct ehci_hcor_s *)IMXRT_USBOTG_HCOR_BASE)
void imxrt_usbhost_vbusdrive(int rhport, bool enable)
{
uint32_t regval;
uinfo("RHPort%d: enable=%d\n", rhport + 1, enable);
/* The IMXRT has only a single root hub port */
if (rhport == 0)
{
/* Then enable or disable VBUS power */
regval = HCOR->portsc[rhport];
regval &= ~EHCI_PORTSC_PP;
if (enable)
{
regval |= EHCI_PORTSC_PP;
}
HCOR->portsc[rhport] = regval;
}
}
/****************************************************************************
* Name: imxrt_setup_overcurrent
*
* Description:
* Setup to receive an interrupt-level callback if an overcurrent condition
* is detected.
*
* Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument that will accompany the interrupt
*
* Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
****************************************************************************/
#if 0 /* Not ready yet */
int imxrt_setup_overcurrent(xcpt_t handler, void *arg)
{
irqstate_t flags;
/* Disable interrupts until we are done. This guarantees that the
* following operations are atomic.
*/
flags = enter_critical_section();
/* Configure the interrupt */
#warning Missing logic
leave_critical_section(flags);
return OK;
}
#endif /* 0 */
#endif /* CONFIG_IMXRT_USBOTG || CONFIG_USBHOST */
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/imxrt_userleds.c
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/****************************************************************************
* boards/arm/imxrt/xidatong-arm32/src/imxrt_userleds.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file imxrt_userleds.c
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-23
*/
/* There are four LED status indicators located on the EVK Board. The
* functions of these LEDs include:
*
* - Main Power Supply(D3)
* Green: DC 5V main supply is normal.
* Red: J2 input voltage is over 5.6V.
* Off: The board is not powered.
* - Reset RED LED(D15)
* - OpenSDA LED(D16)
* - USER LED(D18)
*
* Only a single LED, D18, is under software control.
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "imxrt_gpio.h"
#include "imxrt_iomuxc.h"
#include "xidatong-arm32.h"
#include <arch/board/board.h>
#if !defined(CONFIG_ARCH_LEDS) && defined(GPIO_LED)
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: board_userled_initialize
****************************************************************************/
uint32_t board_userled_initialize(void)
{
/* Configure LED GPIO for output */
imxrt_config_gpio(GPIO_LED);
return BOARD_NLEDS;
}
/****************************************************************************
* Name: board_userled
****************************************************************************/
void board_userled(int led, bool ledon)
{
imxrt_gpio_write(GPIO_LED, !ledon); /* Low illuminates */
}
/****************************************************************************
* Name: board_userled_all
****************************************************************************/
void board_userled_all(uint32_t ledset)
{
/* Low illuminates */
imxrt_gpio_write(GPIO_LED, (ledset & BOARD_USERLED_BIT) == 0);
}
#endif /* !CONFIG_ARCH_LEDS */
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/src/xidatong-arm32.h
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/****************************************************************************
* boards/arm/imxrt/xidatong-arm32/src/xidatong-arm32.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/**
* @file xidatong-arm32.h
* @brief nuttx source code
* https://github.com/apache/incubator-nuttx.git
* @version 10.3.0
* @author AIIT XUOS Lab
* @date 2022-03-23
*/
#ifndef __BOARDS_ARM_IMXRT_XIDATONG_ARM32_SRC_XIDATONG_ARM32_H
#define __BOARDS_ARM_IMXRT_XIDATONG_ARM32_SRC_XIDATONG_ARM32_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <arch/irq.h>
#include <nuttx/irq.h>
#include <nuttx/sdio.h>
#include <nuttx/mmcsd.h>
#include "imxrt_gpio.h"
#include "imxrt_iomuxc.h"
#include "imxrt_usdhc.h"
#include <arch/board/board.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* LEDs */
#define GPIO_LED (GPIO_OUTPUT | IOMUX_LED_DEFAULT | \
GPIO_OUTPUT_ZERO | GPIO_PORT1 | GPIO_PIN9) /* AD_BO_09 */
/* Buttons ******************************************************************/
#define GPIO_SW8 (GPIO_INTERRUPT | GPIO_INT_FALLINGEDGE | \
IOMUX_SW_DEFAULT | \
GPIO_PORT5 | GPIO_PIN0 | ) /* WAKEUP */
/* Test Pins ****************************************************************/
#define BOARD_NGPIOIN 0 /* Amount of GPIO Input pins */
#define BOARD_NGPIOOUT 2 /* Amount of GPIO Output pins */
#define BOARD_NGPIOINT 0 /* Amount of GPIO Input w/ Interruption pins */
#define GPIO_E220_M0 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \
GPIO_PIN9 | GPIO_PORT1)
#define GPIO_E220_M1 (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | IOMUX_GOUT_DEFAULT | \
GPIO_PIN11 | GPIO_PORT1)
/* Backlight */
#define GPIO_LCD_BL (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GPIO_PORT2 | \
GPIO_PIN31 | IOMUX_LCD_BL_DEFAULT)
/* Ethernet */
#define GPIO_ENET_INT (IOMUX_ENET_INT_DEFAULT | \
GPIO_PORT1 | GPIO_PIN10) /* AD_B0_10 */
#define GPIO_ENET_IRQ IMXRT_IRQ_GPIO1_10
#define GPIO_ENET_RST (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | \
GPIO_PORT1 | GPIO_PIN9 | IOMUX_ENET_RST_DEFAULT)
#ifdef CONFIG_ETH0_PHY_KSZ8081
#ifdef GPIO_LED
#warning LED interferes with ETH reset unless R323 is removed.
#endif
#endif
/* LPSPI CS: */
#define IOMUX_LPSPI3_CS (IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | \
IOMUX_SPEED_MEDIUM | IOMUX_PULL_UP_100K | \
_IOMUX_PULL_ENABLE)
#define GPIO_LPSPI3_CS (GPIO_OUTPUT | GPIO_OUTPUT_ONE | \
GPIO_PORT1 | GPIO_PIN3 | IOMUX_LPSPI3_CS) /* GPIO_AD_B0_03 */
/* LPSPI1 CS: GPIO_SD_B0_01 */
#define IOMUX_LPSPI1_CS (IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | \
IOMUX_SPEED_MEDIUM | IOMUX_PULL_UP_100K | \
_IOMUX_PULL_ENABLE)
#define GPIO_LPSPI1_CS (GPIO_OUTPUT | GPIO_OUTPUT_ONE | \
GPIO_PORT3 | GPIO_PIN13 | IOMUX_LPSPI1_CS)
#define IOMUX_MMCSD_EN (IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | \
IOMUX_SPEED_MEDIUM | IOMUX_PULL_UP_100K | \
_IOMUX_PULL_ENABLE)
#define GPIO_MMCSD_EN (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | \
GPIO_PORT3 | GPIO_PIN2 | IOMUX_MMCSD_EN)
/* USB OTG ID Pin： GPIO_AD_B1_01 */
#define GPIO_USBOTG_ID (GPIO_USB_OTG1_ID_2 | IOMUX_USBOTG_ID_DEFAULT) /* GPIO_AD_B1_01 */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Functions Definitions
****************************************************************************/
/****************************************************************************
* Name: imxrt_bringup
*
* Description:
* Bring up board features
*
****************************************************************************/
#if defined(CONFIG_BOARDCTL) || defined(CONFIG_BOARD_LATE_INITIALIZE)
int imxrt_bringup(void);
#endif
/****************************************************************************
* Name: imxrt_spidev_initialize
*
* Description:
* Called to configure SPI chip select GPIO pins for the i.MXRT1050 EVK.
*
****************************************************************************/
void imxrt_spidev_initialize(void);
/****************************************************************************
* Name: imxrt_mmcsd_spi_initialize
*
* Description:
* Initialize SPI-based SD card and card detect thread.
*
****************************************************************************/
#ifdef CONFIG_MMCSD_SPI
int imxrt_mmcsd_spi_initialize(int minor);
#endif
/****************************************************************************
* Name: imxrt_autoled_initialize
*
* Description:
* Initialize NuttX-controlled LED logic
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_ARCH_LEDS
void imxrt_autoled_initialize(void);
#endif
#ifdef CONFIG_DEV_GPIO
/****************************************************************************
* Name: imxrt_gpio_initialize
*
* Description:
* Initialize GPIO drivers for use with /apps/examples/gpio
*
****************************************************************************/
int imxrt_gpio_initialize(void);
#endif
#if defined(CONFIG_IMXRT_USBOTG) || defined(CONFIG_USBHOST)
int imxrt_usbhost_initialize(void);
#endif
#ifdef CONFIG_IMXRT_USDHC
int nsh_sdmmc_initialize(void);
#else
# define nsh_sdmmc_initialize() (OK)
#endif
#if defined(CONFIG_IMXRT_USDHC) && defined(CONFIG_XIDATONG_ARM32_SDIO_AUTOMOUNT)
int imxrt_sdhc_automount_event(void *arg);
void imxrt_automount_initialize(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_ARM_IMXRT_XIDATONG_ARM32_SRC_XIDATONG_ARM32_H */