diff --git a/Ubiquitous/XiZi/board/ok1052-c/Makefile b/Ubiquitous/XiZi/board/ok1052-c/Makefile
index 837118429..c50f207a4 100644
--- a/Ubiquitous/XiZi/board/ok1052-c/Makefile
+++ b/Ubiquitous/XiZi/board/ok1052-c/Makefile
@@ -1,4 +1,4 @@
-SRC_DIR := third_party_driver
+SRC_DIR := third_party_driver xip
 
 SRC_FILES := board.c
 
diff --git a/Ubiquitous/XiZi/board/ok1052-c/README.md b/Ubiquitous/XiZi/board/ok1052-c/README.md
index 81477339f..4e489f05c 100644
--- a/Ubiquitous/XiZi/board/ok1052-c/README.md
+++ b/Ubiquitous/XiZi/board/ok1052-c/README.md
@@ -161,7 +161,10 @@ make BOARD=ok1052-c
 2、ok1052-c开发板支持micro usb口烧写程序，打开NXP MCU Boot Utility后，选择好芯片类型为i.MXRT105x，开发板上电，使用usb线将开发板和PC连接，拨码开关设置为1 on 2 on 3 off 4 off，按下复位键K1后，若连接成功，可见Vendor ID和Product ID均有数字显示，点击reconnect，等待NXP MCU Boot Utility中红色显示变成蓝色显示，则表示已正确识别并连接到了开发板。如下图所示：
 ![NXPBootUtility_1](./img/NXPBootUtility_1.png)
 
-3、选择编译生成的XiZi_ok1052-c.elf文件路径，并选择.out(elf) from GCC ARM烧写选项，最后点击ALL-In-One Action即可烧写程序，若烧写无误，则下列绿色进度条会执行到底。如下图所示：
+3、同时需要匹配ok1052-c开发板所使用的Flash型号，点击Boot Device Configuration，在Use Typical Device中选择Winbond_W25QxxxJV，然后点击ok。如下图所示：
+![flashconfig](./img/flashconfig.png)
+
+4、选择编译生成的XiZi_ok1052-c.elf或bin文件路径，按照图示步骤，将文件烧写至Flash中（link.lds中已构造Flash Bootable image，如有修改Flash相关配置需求，可修改/xip目录内相关文件，无需NXPBootUtility再次构造），若烧写无误，则下列绿色进度条会执行到底。如下图所示：
 ![NXPBootUtility_2](./img/NXPBootUtility_2.png)
 
 ### 3.2 运行结果
diff --git a/Ubiquitous/XiZi/board/ok1052-c/img/NXPBootUtility_2.png b/Ubiquitous/XiZi/board/ok1052-c/img/NXPBootUtility_2.png
index 671bcb0c2..a607ce8e5 100644
Binary files a/Ubiquitous/XiZi/board/ok1052-c/img/NXPBootUtility_2.png and b/Ubiquitous/XiZi/board/ok1052-c/img/NXPBootUtility_2.png differ
diff --git a/Ubiquitous/XiZi/board/ok1052-c/img/flashconfig.png b/Ubiquitous/XiZi/board/ok1052-c/img/flashconfig.png
new file mode 100644
index 000000000..9db4bd312
Binary files /dev/null and b/Ubiquitous/XiZi/board/ok1052-c/img/flashconfig.png differ
diff --git a/Ubiquitous/XiZi/board/ok1052-c/link-usb.lds b/Ubiquitous/XiZi/board/ok1052-c/link-usb.lds
index d98553676..0af5e162f 100755
--- a/Ubiquitous/XiZi/board/ok1052-c/link-usb.lds
+++ b/Ubiquitous/XiZi/board/ok1052-c/link-usb.lds
@@ -54,6 +54,9 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
 /* Specify the memory areas */
 MEMORY
 {
+  m_boot_data           (RX)  : ORIGIN = 0x60000000, LENGTH = 0x00001000
+  m_image_vertor_table  (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00001000  
+    
   m_interrupts          (RX)  : ORIGIN = 0x60002000, LENGTH = 0x00000400
   m_text                (RX)  : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
   m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00020000
@@ -63,6 +66,17 @@ MEMORY
 /* Define output sections */
 SECTIONS
 {
+  .boot_data :
+  {
+    KEEP(*(.boot_hdr.conf))
+  } > m_boot_data
+
+  .image_vertor_table :
+  {
+    KEEP(*(.boot_hdr.ivt))
+    KEEP(*(.boot_hdr.boot_data))
+    KEEP(*(.boot_hdr.dcd_data))
+  } > m_image_vertor_table
 
   /* The startup code goes first into internal RAM */
   .interrupts :
diff --git a/Ubiquitous/XiZi/board/ok1052-c/link.lds b/Ubiquitous/XiZi/board/ok1052-c/link.lds
index 582743f76..d9fce959f 100644
--- a/Ubiquitous/XiZi/board/ok1052-c/link.lds
+++ b/Ubiquitous/XiZi/board/ok1052-c/link.lds
@@ -54,6 +54,9 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
 /* Specify the memory areas */
 MEMORY
 {
+  m_boot_data           (RX)  : ORIGIN = 0x60000000, LENGTH = 0x00001000
+  m_image_vertor_table  (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00001000  
+  
   m_interrupts          (RX)  : ORIGIN = 0x60002000, LENGTH = 0x00000400
   m_text                (RX)  : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
   m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00020000
@@ -63,6 +66,17 @@ MEMORY
 /* Define output sections */
 SECTIONS
 {
+  .boot_data :
+  {
+    KEEP(*(.boot_hdr.conf))
+  } > m_boot_data
+
+  .image_vertor_table :
+  {
+    KEEP(*(.boot_hdr.ivt))
+    KEEP(*(.boot_hdr.boot_data))
+    KEEP(*(.boot_hdr.dcd_data))
+  } > m_image_vertor_table
 
   /* The startup code goes first into internal RAM */
   .interrupts :
diff --git a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/gpio/connect_gpio.c b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/gpio/connect_gpio.c
index a61d7d035..3032b282e 100755
--- a/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/gpio/connect_gpio.c
+++ b/Ubiquitous/XiZi/board/ok1052-c/third_party_driver/gpio/connect_gpio.c
@@ -13,7 +13,7 @@
 * @brief support gpio function using bus driver framework
 * @version 2.0
 * @author AIIT XUOS Lab
-* @date 2022-03-16
+* @date 2022-03-22
 */
 
 /*************************************************
@@ -22,7 +22,7 @@ Description: support gpio configure and register to bus framework
 Others: take RT-Thread v4.0.2/bsp/imxrt/libraries/drivers/drv_gpio.c for references
                 https://github.com/RT-Thread/rt-thread/tree/v4.0.2
 History:
-1. Date: 2022-03-16
+1. Date: 2022-03-22
 Author: AIIT XUOS Lab
 Modification: add bus driver framework support for gpio
 *************************************************/
@@ -215,6 +215,20 @@ struct PinIrqHdr pin_irq_hdr_tab[] =
     {-1, 0, NONE, NONE},
 };
 
+#define MUX_BASE            0x401f8014
+#define CONFIG_BASE         0x401f8204
+
+#define GPIO5_MUX_BASE      0x400A8000
+#define GPIO5_CONFIG_BASE   0x400A8018
+
+const uint8_t reg_offset[] =
+{
+    42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73,
+    74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,103,104,105,
+   112,113,114,115,116,117,118,119,120,121,122,123,106,107,108,109,110,111, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, -1, -1, -1, -1,
+     0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+};
+
 static int GetPin(struct PinIndex *pin_index, uint8_t pin)
 {
     pin_index->index = pin >> 5;//0:GPIO1 1:GPIO2 2:GPIO3 3:GPIO4 4:GPIO5 
@@ -229,39 +243,52 @@ static int GetPin(struct PinIndex *pin_index, uint8_t pin)
     return 0;
 }
 
-static int32 GpioConfigMode(int mode, struct PinIndex *index)
+static int32 GpioConfigMode(int mode, struct PinIndex *pin_index, int32 pin)
 {
     gpio_pin_config_t gpio_config;
-    NULL_PARAM_CHECK(index);
+    uint32_t config_value = 0;
+    NULL_PARAM_CHECK(pin_index);
 
     gpio_config.outputLogic = 0;
+    gpio_config.interruptMode = kGPIO_NoIntmode;
 
     switch (mode)
     {
         case GPIO_CFG_OUTPUT:
             gpio_config.direction = kGPIO_DigitalOutput;
-            gpio_config.interruptMode = kGPIO_NoIntmode;
+            config_value = 0x0030U;    /* Drive Strength R0/6 */
             break;
         case GPIO_CFG_INPUT:
             gpio_config.direction = kGPIO_DigitalInput;
-            gpio_config.interruptMode = kGPIO_NoIntmode;
+            config_value = 0x0830U;    /* Open Drain Enable */
             break;
         case GPIO_CFG_INPUT_PULLUP:
             gpio_config.direction = kGPIO_DigitalInput;
-            gpio_config.interruptMode = kGPIO_NoIntmode;
+            config_value = 0xB030U;    /* 100K Ohm Pull Up */
             break;
         case GPIO_CFG_INPUT_PULLDOWN:
             gpio_config.direction = kGPIO_DigitalInput;
-            gpio_config.interruptMode = kGPIO_NoIntmode;
+            config_value = 0x3030U;    /* 100K Ohm Pull Down */
             break;
         case GPIO_CFG_OUTPUT_OD:
             gpio_config.direction = kGPIO_DigitalOutput;
-            gpio_config.interruptMode = kGPIO_NoIntmode;
+            config_value = 0x0830U;    /* Open Drain Enable */
             break;
         default:
             break;
     }
-    GPIO_PinInit(index->gpio, index->pin, &gpio_config);
+
+    if (pin_mask[pin_index->index].gpio != GPIO5) {
+        CLOCK_EnableClock(kCLOCK_Iomuxc);
+        IOMUXC_SetPinMux(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, 1);
+        IOMUXC_SetPinConfig(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, config_value);
+    } else {
+        CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
+        IOMUXC_SetPinMux(GPIO5_MUX_BASE + pin_index->pin * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_index->pin * 4, 1);
+        IOMUXC_SetPinConfig(GPIO5_MUX_BASE + pin_index->pin * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_index->pin * 4, config_value);
+    }
+
+    GPIO_PinInit(pin_index->gpio, pin_index->pin, &gpio_config);
     return EOK;
 }
 
@@ -385,6 +412,7 @@ static uint32 Imxrt1052PinConfigure(struct PinParam *param)
 
     struct PinIndex pin_index;
 
+    KPrintf("Imxrt1052PinConfigure\n");
     if (GetPin(&pin_index, param->pin) < 0) {
         return ERROR;
     }
@@ -392,7 +420,8 @@ static uint32 Imxrt1052PinConfigure(struct PinParam *param)
     switch(param->cmd)
     {
         case GPIO_CONFIG_MODE:
-            GpioConfigMode(param->mode, &pin_index);
+            KPrintf("GpioConfigMode %u\n", param->pin);
+            GpioConfigMode(param->mode, &pin_index, param->pin);
             break;
         case GPIO_IRQ_REGISTER:
             ret = GpioIrqRegister(param->pin, param->irq_set.irq_mode, param->irq_set.hdr, param->irq_set.args);
@@ -705,21 +734,6 @@ void GpioLedTest(void)
         KPrintf("initialize %s failed!\n", PIN_BUS_NAME);
         return;
     }
-
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,        /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
-        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-                                    /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,        /* GPIO_AD_B0_09 PAD functional properties : */
-        0x10B0u);                               /* Slew Rate Field: Slow Slew Rate
-                                                    Drive Strength Field: R0/6
-                                                    Speed Field: medium(100MHz)
-                                                    Open Drain Enable Field: Open Drain Disabled
-                                                    Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                    Pull / Keep Select Field: Keeper
-                                                    Pull Up / Down Config. Field: 100K Ohm Pull Down
-                                                    Hyst. Enable Field: Hysteresis Disabled */
     
     struct PinParam led_gpio_param;
     struct PinStat led_gpio_stat;
@@ -762,4 +776,3 @@ void GpioLedTest(void)
 SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
                                                 GpioLedTest, GpioLedTest, GpioLedTest GPIO1 IO09 LED);
 #endif
-
diff --git a/Ubiquitous/XiZi/board/ok1052-c/xip/Makefile b/Ubiquitous/XiZi/board/ok1052-c/xip/Makefile
new file mode 100755
index 000000000..e27f9550a
--- /dev/null
+++ b/Ubiquitous/XiZi/board/ok1052-c/xip/Makefile
@@ -0,0 +1,3 @@
+SRC_FILES := fsl_flexspi_nor_boot.c fsl_flexspi_nor_flash.c
+
+include $(KERNEL_ROOT)/compiler.mk
diff --git a/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_boot.c b/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_boot.c
new file mode 100644
index 000000000..503d56845
--- /dev/null
+++ b/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_boot.c
@@ -0,0 +1,1149 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+* @file fsl_flexspi_nor_boot.c
+* @brief support to register flexspi image vector table
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-03-22
+*/
+
+#include "fsl_flexspi_nor_boot.h"
+
+#if defined(__CC_ARM) || defined(__GNUC__)
+    __attribute__((section(".boot_hdr.ivt")))
+#elif defined(__ICCARM__)
+#pragma location=".boot_hdr.ivt"
+#endif
+
+const ivt image_vector_table = {
+  IVT_HEADER,                         /* IVT Header */
+  0x60002000,                         /* Image  Entry Function */
+  IVT_RSVD,                           /* Reserved = 0 */
+  (uint32_t)DCD_ADDRESS,              /* Address where DCD information is stored */
+  (uint32_t)BOOT_DATA_ADDRESS,        /* Address where BOOT Data Structure is stored */
+  (uint32_t)&image_vector_table,      /* Pointer to IVT Self (absolute address */
+  (uint32_t)CSF_ADDRESS,              /* Address where CSF file is stored */
+  IVT_RSVD                            /* Reserved = 0 */
+};
+
+#if defined(__CC_ARM) || defined(__GNUC__)
+    __attribute__((section(".boot_hdr.boot_data")))
+#elif defined(__ICCARM__)
+#pragma location=".boot_hdr.boot_data"
+#endif
+
+const BOOT_DATA_T boot_data = {
+  FLASH_BASE,                 /* boot start location */
+  (FLASH_END-FLASH_BASE),     /* size */
+  PLUGIN_FLAG,                /* Plugin flag*/
+  0xFFFFFFFF  				  /* empty - extra data word */
+};
+
+#if defined(__CC_ARM) || defined(__GNUC__)
+    __attribute__((section(".boot_hdr.dcd_data")))
+#elif defined(__ICCARM__)
+#pragma location=".boot_hdr.dcd_data"
+#endif
+
+const uint8_t dcd_sdram[1072] = {
+	/*0000*/ 0xD2,
+    0x04,
+    0x30,
+    0x41,
+    0xCC,
+    0x03,
+    0xAC,
+    0x04,
+    0x40,
+    0x0F,
+    0xC0,
+    0x68,
+    0xFF,
+    0xFF,
+    0xFF,
+    0xFF,
+    /*0010*/ 0x40,
+    0x0F,
+    0xC0,
+    0x6C,
+    0xFF,
+    0xFF,
+    0xFF,
+    0xFF,
+    0x40,
+    0x0F,
+    0xC0,
+    0x70,
+    0xFF,
+    0xFF,
+    0xFF,
+    0xFF,
+    /*0020*/ 0x40,
+    0x0F,
+    0xC0,
+    0x74,
+    0xFF,
+    0xFF,
+    0xFF,
+    0xFF,
+    0x40,
+    0x0F,
+    0xC0,
+    0x78,
+    0xFF,
+    0xFF,
+    0xFF,
+    0xFF,
+    /*0030*/ 0x40,
+    0x0F,
+    0xC0,
+    0x7C,
+    0xFF,
+    0xFF,
+    0xFF,
+    0xFF,
+    0x40,
+    0x0F,
+    0xC0,
+    0x80,
+    0xFF,
+    0xFF,
+    0xFF,
+    0xFF,
+    /*0040*/ 0x40,
+    0x0D,
+    0x80,
+    0x30,
+    0x00,
+    0x00,
+    0x20,
+    0x01,
+    0x40,
+    0x0D,
+    0x81,
+    0x00,
+    0x00,
+    0x1D,
+    0x00,
+    0x00,
+    /*0050*/ 0x40,
+    0x0F,
+    0xC0,
+    0x14,
+    0x00,
+    0x01,
+    0x0D,
+    0x40,
+    0x40,
+    0x1F,
+    0x80,
+    0x14,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0060*/ 0x40,
+    0x1F,
+    0x80,
+    0x18,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x1C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0070*/ 0x40,
+    0x1F,
+    0x80,
+    0x20,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x24,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0080*/ 0x40,
+    0x1F,
+    0x80,
+    0x28,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x2C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0090*/ 0x40,
+    0x1F,
+    0x80,
+    0x30,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x34,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*00a0*/ 0x40,
+    0x1F,
+    0x80,
+    0x38,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x3C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*00b0*/ 0x40,
+    0x1F,
+    0x80,
+    0x40,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x44,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*00c0*/ 0x40,
+    0x1F,
+    0x80,
+    0x48,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x4C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*00d0*/ 0x40,
+    0x1F,
+    0x80,
+    0x50,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x54,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*00e0*/ 0x40,
+    0x1F,
+    0x80,
+    0x58,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x5C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*00f0*/ 0x40,
+    0x1F,
+    0x80,
+    0x60,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x64,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0100*/ 0x40,
+    0x1F,
+    0x80,
+    0x68,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x6C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0110*/ 0x40,
+    0x1F,
+    0x80,
+    0x70,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x74,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0120*/ 0x40,
+    0x1F,
+    0x80,
+    0x78,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x7C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0130*/ 0x40,
+    0x1F,
+    0x80,
+    0x80,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x84,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0140*/ 0x40,
+    0x1F,
+    0x80,
+    0x88,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x8C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0150*/ 0x40,
+    0x1F,
+    0x80,
+    0x90,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x94,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0160*/ 0x40,
+    0x1F,
+    0x80,
+    0x98,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x9C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0170*/ 0x40,
+    0x1F,
+    0x80,
+    0xA0,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0xA4,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0180*/ 0x40,
+    0x1F,
+    0x80,
+    0xA8,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0xAC,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0190*/ 0x40,
+    0x1F,
+    0x80,
+    0xB0,
+    0x00,
+    0x00,
+    0x00,
+    0x10,
+    0x40,
+    0x1F,
+    0x80,
+    0xB4,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*01a0*/ 0x40,
+    0x1F,
+    0x80,
+    0xB8,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x82,
+    0x04,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*01b0*/ 0x40,
+    0x1F,
+    0x82,
+    0x08,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x0C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*01c0*/ 0x40,
+    0x1F,
+    0x82,
+    0x10,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x14,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*01d0*/ 0x40,
+    0x1F,
+    0x82,
+    0x18,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x1C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*01e0*/ 0x40,
+    0x1F,
+    0x82,
+    0x20,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x24,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*01f0*/ 0x40,
+    0x1F,
+    0x82,
+    0x28,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x2C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0200*/ 0x40,
+    0x1F,
+    0x82,
+    0x30,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x34,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0210*/ 0x40,
+    0x1F,
+    0x82,
+    0x38,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x3C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0220*/ 0x40,
+    0x1F,
+    0x82,
+    0x40,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x44,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0230*/ 0x40,
+    0x1F,
+    0x82,
+    0x48,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x4C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0240*/ 0x40,
+    0x1F,
+    0x82,
+    0x50,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x54,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0250*/ 0x40,
+    0x1F,
+    0x82,
+    0x58,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x5C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0260*/ 0x40,
+    0x1F,
+    0x82,
+    0x60,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x64,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0270*/ 0x40,
+    0x1F,
+    0x82,
+    0x68,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x6C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0280*/ 0x40,
+    0x1F,
+    0x82,
+    0x70,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x74,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0290*/ 0x40,
+    0x1F,
+    0x82,
+    0x78,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x7C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*02a0*/ 0x40,
+    0x1F,
+    0x82,
+    0x80,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x84,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*02b0*/ 0x40,
+    0x1F,
+    0x82,
+    0x88,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x8C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*02c0*/ 0x40,
+    0x1F,
+    0x82,
+    0x90,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x94,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*02d0*/ 0x40,
+    0x1F,
+    0x82,
+    0x98,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x9C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*02e0*/ 0x40,
+    0x1F,
+    0x82,
+    0xA0,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0xA4,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*02f0*/ 0x40,
+    0x1F,
+    0x82,
+    0xA8,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x2F,
+    0x00,
+    0x00,
+    0x10,
+    0x00,
+    0x00,
+    0x04,
+    /*0300*/ 0x40,
+    0x2F,
+    0x00,
+    0x08,
+    0x00,
+    0x03,
+    0x05,
+    0x24,
+    0x40,
+    0x2F,
+    0x00,
+    0x0C,
+    0x06,
+    0x03,
+    0x05,
+    0x24,
+    /*0310*/ 0x40,
+    0x2F,
+    0x00,
+    0x10,
+    0x80,
+    0x00,
+    0x00,
+    0x1B,
+    0x40,
+    0x2F,
+    0x00,
+    0x14,
+    0x82,
+    0x00,
+    0x00,
+    0x1B,
+    /*0320*/ 0x40,
+    0x2F,
+    0x00,
+    0x18,
+    0x84,
+    0x00,
+    0x00,
+    0x1B,
+    0x40,
+    0x2F,
+    0x00,
+    0x1C,
+    0x86,
+    0x00,
+    0x00,
+    0x1B,
+    /*0330*/ 0x40,
+    0x2F,
+    0x00,
+    0x20,
+    0x90,
+    0x00,
+    0x00,
+    0x21,
+    0x40,
+    0x2F,
+    0x00,
+    0x24,
+    0xA0,
+    0x00,
+    0x00,
+    0x19,
+    /*0340*/ 0x40,
+    0x2F,
+    0x00,
+    0x28,
+    0xA8,
+    0x00,
+    0x00,
+    0x17,
+    0x40,
+    0x2F,
+    0x00,
+    0x2C,
+    0xA9,
+    0x00,
+    0x00,
+    0x1B,
+    /*0350*/ 0x40,
+    0x2F,
+    0x00,
+    0x30,
+    0x00,
+    0x00,
+    0x00,
+    0x21,
+    0x40,
+    0x2F,
+    0x00,
+    0x04,
+    0x00,
+    0x00,
+    0x79,
+    0xA8,
+    /*0360*/ 0x40,
+    0x2F,
+    0x00,
+    0x40,
+    0x00,
+    0x00,
+    0x0F,
+    0x31,
+    0x40,
+    0x2F,
+    0x00,
+    0x44,
+    0x00,
+    0x65,
+    0x29,
+    0x22,
+    /*0370*/ 0x40,
+    0x2F,
+    0x00,
+    0x48,
+    0x00,
+    0x01,
+    0x09,
+    0x20,
+    0x40,
+    0x2F,
+    0x00,
+    0x4C,
+    0x50,
+    0x21,
+    0x0A,
+    0x08,
+    /*0380*/ 0x40,
+    0x2F,
+    0x00,
+    0x80,
+    0x00,
+    0x00,
+    0x00,
+    0x21,
+    0x40,
+    0x2F,
+    0x00,
+    0x84,
+    0x00,
+    0x88,
+    0x88,
+    0x88,
+    /*0390*/ 0x40,
+    0x2F,
+    0x00,
+    0x94,
+    0x00,
+    0x00,
+    0x00,
+    0x02,
+    0x40,
+    0x2F,
+    0x00,
+    0x98,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*03a0*/ 0x40,
+    0x2F,
+    0x00,
+    0x90,
+    0x80,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x2F,
+    0x00,
+    0x9C,
+    0xA5,
+    0x5A,
+    0x00,
+    0x0F,
+    /*03b0*/ 0xCF,
+    0x00,
+    0x0C,
+    0x1C,
+    0x40,
+    0x2F,
+    0x00,
+    0x3C,
+    0x00,
+    0x00,
+    0x00,
+    0x01,
+    0xCC,
+    0x00,
+    0x14,
+    0x04,
+    /*03c0*/ 0x40,
+    0x2F,
+    0x00,
+    0x90,
+    0x80,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x2F,
+    0x00,
+    0x9C,
+    0xA5,
+    0x5A,
+    0x00,
+    0x0C,
+    /*03d0*/ 0xCF,
+    0x00,
+    0x0C,
+    0x1C,
+    0x40,
+    0x2F,
+    0x00,
+    0x3C,
+    0x00,
+    0x00,
+    0x00,
+    0x01,
+    0xCC,
+    0x00,
+    0x14,
+    0x04,
+    /*03e0*/ 0x40,
+    0x2F,
+    0x00,
+    0x90,
+    0x80,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x2F,
+    0x00,
+    0x9C,
+    0xA5,
+    0x5A,
+    0x00,
+    0x0C,
+    /*03f0*/ 0xCF,
+    0x00,
+    0x0C,
+    0x1C,
+    0x40,
+    0x2F,
+    0x00,
+    0x3C,
+    0x00,
+    0x00,
+    0x00,
+    0x01,
+    0xCC,
+    0x00,
+    0x1C,
+    0x04,
+    /*0400*/ 0x40,
+    0x2F,
+    0x00,
+    0xA0,
+    0x00,
+    0x00,
+    0x00,
+    0x33,
+    0x40,
+    0x2F,
+    0x00,
+    0x90,
+    0x80,
+    0x00,
+    0x00,
+    0x00,
+    /*0410*/ 0x40,
+    0x2F,
+    0x00,
+    0x9C,
+    0xA5,
+    0x5A,
+    0x00,
+    0x0A,
+    0xCF,
+    0x00,
+    0x0C,
+    0x1C,
+    0x40,
+    0x2F,
+    0x00,
+    0x3C,
+    /*0420*/ 0x00,
+    0x00,
+    0x00,
+    0x01,
+    0xCC,
+    0x00,
+    0x0C,
+    0x04,
+    0x40,
+    0x2F,
+    0x00,
+    0x4C,
+    0x50,
+    0x07,
+    0x0A,
+    0x09,
+};
diff --git a/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_boot.h b/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_boot.h
new file mode 100644
index 000000000..b6677b274
--- /dev/null
+++ b/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_boot.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+* @file fsl_flexspi_nor_boot.h
+* @brief support to register flexspi image vector table
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-03-22
+*/
+
+#ifndef _QUADSPI_BOOT_H_
+#define _QUADSPI_BOOT_H_
+
+#include <stdint.h>
+
+/************************************* 
+ *  IVT Data 
+ *************************************/
+typedef struct _ivt_ {
+    /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields
+     *  (see @ref data)
+     */
+    uint32_t hdr;
+    /** Absolute address of the first instruction to execute from the
+     *  image
+     */
+    uint32_t entry;
+    /** Reserved in this version of HAB: should be NULL. */
+    uint32_t reserved1;
+    /** Absolute address of the image DCD: may be NULL. */
+    uint32_t dcd;
+    /** Absolute address of the Boot Data: may be NULL, but not interpreted
+     *  any further by HAB
+     */
+    uint32_t boot_data;
+    /** Absolute address of the IVT.*/
+    uint32_t self;
+    /** Absolute address of the image CSF.*/
+    uint32_t csf;
+    /** Reserved in this version of HAB: should be zero. */
+    uint32_t reserved2;
+} ivt;
+
+#define IVT_MAJOR_VERSION           0x4
+#define IVT_MAJOR_VERSION_SHIFT     0x4
+#define IVT_MAJOR_VERSION_MASK      0xF
+#define IVT_MINOR_VERSION           0x1
+#define IVT_MINOR_VERSION_SHIFT     0x0
+#define IVT_MINOR_VERSION_MASK      0xF
+
+#define IVT_VERSION(major, minor)   \
+  ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) |  \
+  (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT))
+
+#define IVT_TAG_HEADER        (0xD1)       /**< Image Vector Table */
+#define IVT_SIZE              0x2000
+#define IVT_PAR               IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION)
+
+#define IVT_HEADER          (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24))
+#define IVT_RSVD            (uint32_t)(0x00000000)
+
+
+/************************************* 
+ *  Boot Data 
+ *************************************/
+typedef struct _boot_data_ {
+  uint32_t start;           /* boot start location */
+  uint32_t size;            /* size */
+  uint32_t plugin;          /* plugin flag - 1 if downloaded application is plugin */
+  uint32_t placeholder;		/* placehoder to make even 0x10 size */
+}BOOT_DATA_T;
+
+
+/************************************* 
+ *  DCD Data 
+ *************************************/
+#define DCD_TAG_HEADER            (0xD2)
+#define DCD_TAG_HEADER_SHIFT      (24)
+#define DCD_VERSION               (0x40)
+#define DCD_ARRAY_SIZE             1
+
+#define FLASH_BASE            0x60000000
+#define FLASH_END             0x7F7FFFFF 
+#define SCLK 1
+
+#define DCD_ADDRESS           dcd_sdram
+#define BOOT_DATA_ADDRESS     &boot_data
+#define CSF_ADDRESS           0
+#define PLUGIN_FLAG           (uint32_t)0
+
+/* External Variables */
+//extern const uint8_t dcd_sdram[1044];
+extern const uint8_t dcd_sdram[1072];
+extern const BOOT_DATA_T boot_data;
+
+#endif
diff --git a/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_flash.c b/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_flash.c
new file mode 100644
index 000000000..c5cc52dbc
--- /dev/null
+++ b/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_flash.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+* @file fsl_flexspi_nor_flash.c
+* @brief support to define flexspi flash config
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-03-22
+*/
+
+#include "fsl_flexspi_nor_flash.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(__CC_ARM) || defined(__GNUC__)
+    __attribute__((section(".boot_hdr.conf")))
+#elif defined(__ICCARM__)
+#pragma location=".boot_hdr.conf"
+#endif
+
+const flexspi_nor_config_t Qspiflash_config =
+{
+    .memConfig =
+    {
+        .tag = FLEXSPI_CFG_BLK_TAG,
+        .version = FLEXSPI_CFG_BLK_VERSION,
+        .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally,
+        .csHoldTime = 3u,
+        .csSetupTime = 3u,
+        .deviceModeCfgEnable = true,
+        .deviceModeType = 1,//Quad Enable command
+        .deviceModeSeq.seqNum = 1,
+        .deviceModeSeq.seqId = 4,				
+        .deviceModeArg = 0x000200,//Set QE
+        .deviceType = kFlexSpiDeviceType_SerialNOR,
+        .sflashPadType = kSerialFlash_4Pads,
+        .serialClkFreq = kFlexSpiSerialClk_60MHz,//80MHz for Winbond, 100MHz for GD, 133MHz for ISSI
+        .sflashA1Size = 16u * 1024u * 1024u,//4MBytes
+        .dataValidTime = {16u, 16u},
+        .lookupTable =
+        {
+//         //Fast Read Sequence
+//         [0]  = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B, RADDR_SDR, FLEXSPI_1PAD, 0x18),
+//         [1]  = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 0x08, READ_SDR, FLEXSPI_1PAD, 0x08),
+//         [2]  = FLEXSPI_LUT_SEQ(JMP_ON_CS, 0, 0, 0, 0, 0),
+           //Quad Input/output read sequence
+           [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
+           [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
+           [2] = FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0),
+           //Read Status
+           [1*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
+           //Write Enable
+           [3*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, 0, 0),
+           //Write status
+           [4*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x2),
+	 },
+    },
+    .pageSize = 256u,
+    .sectorSize = 4u * 1024u,
+};
diff --git a/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_flash.h b/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_flash.h
new file mode 100644
index 000000000..73d4547b7
--- /dev/null
+++ b/Ubiquitous/XiZi/board/ok1052-c/xip/fsl_flexspi_nor_flash.h
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this
+ * list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice,
+ * this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+* @file fsl_flexspi_nor_flash.h
+* @brief support to define flexspi flash config
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-03-22
+*/
+
+#ifndef __FLEXSPI_NOR_FLASH_H__
+#define __FLEXSPI_NOR_FLASH_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_common.h"
+
+/* FLEXSPI memory config block related defintions */
+#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
+#define FLEXSPI_CFG_BLK_SIZE (512)
+
+/* FLEXSPI Feature related definitions */
+#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
+
+/* Lookup table related defintions */
+#define CMD_INDEX_READ 0
+#define CMD_INDEX_READSTATUS 1
+#define CMD_INDEX_WRITEENABLE 2
+#define CMD_INDEX_WRITE 4
+
+#define CMD_LUT_SEQ_IDX_READ 0
+#define CMD_LUT_SEQ_IDX_READSTATUS 1
+#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
+#define CMD_LUT_SEQ_IDX_WRITE 9
+
+#define CMD_SDR 0x01
+#define CMD_DDR 0x21
+#define RADDR_SDR 0x02
+#define RADDR_DDR 0x22
+#define CADDR_SDR 0x03
+#define CADDR_DDR 0x23
+#define MODE1_SDR 0x04
+#define MODE1_DDR 0x24
+#define MODE2_SDR 0x05
+#define MODE2_DDR 0x25
+#define MODE4_SDR 0x06
+#define MODE4_DDR 0x26
+#define MODE8_SDR 0x07
+#define MODE8_DDR 0x27
+#define WRITE_SDR 0x08
+#define WRITE_DDR 0x28
+#define READ_SDR 0x09
+#define READ_DDR 0x29
+#define LEARN_SDR 0x0A
+#define LEARN_DDR 0x2A
+#define DATSZ_SDR 0x0B
+#define DATSZ_DDR 0x2B
+#define DUMMY_SDR 0x0C
+#define DUMMY_DDR 0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS 0x1F
+#define STOP 0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
+    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+//!@brief Definitions for FlexSPI Serial Clock Frequency
+typedef enum _FlexSpiSerialClockFreq
+{
+    kFlexSpiSerialClk_30MHz = 1,
+    kFlexSpiSerialClk_50MHz = 2,
+    kFlexSpiSerialClk_60MHz = 3,
+    kFlexSpiSerialClk_75MHz = 4,
+    kFlexSpiSerialClk_80MHz = 5,
+    kFlexSpiSerialClk_100MHz = 6,
+    kFlexSpiSerialClk_133MHz = 7,
+    kFlexSpiSerialClk_166MHz = 8,
+    kFlexSpiSerialClk_200MHz = 9,
+} flexspi_serial_clk_freq_t;
+
+//!@brief FlexSPI clock configuration type
+enum
+{
+    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
+    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
+};
+
+//!@brief FlexSPI Read Sample Clock Source definition
+typedef enum _FlashReadSampleClkSource
+{
+    kFlexSPIReadSampleClk_LoopbackInternally = 0,
+    kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
+    kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
+    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+
+//!@brief Misc feature bit definitions
+enum
+{
+    kFlexSpiMiscOffset_DiffClkEnable = 0,            //!< Bit for Differential clock enable
+    kFlexSpiMiscOffset_Ck2Enable = 1,                //!< Bit for CK2 enable
+    kFlexSpiMiscOffset_ParallelEnable = 2,           //!< Bit for Parallel mode enable
+    kFlexSpiMiscOffset_WordAddressableEnable = 3,    //!< Bit for Word Addressable enable
+    kFlexSpiMiscOffset_SafeConfigFreqEnable = 4,     //!< Bit for Safe Configuration Frequency enable
+    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
+    kFlexSpiMiscOffset_DdrModeEnable = 6,            //!< Bit for DDR clock confiuration indication.
+};
+
+//!@brief Flash Type Definition
+enum
+{
+    kFlexSpiDeviceType_SerialNOR = 1,       //!< Flash devices are Serial NOR
+    kFlexSpiDeviceType_SerialNAND = 2,      //!< Flash devices are Serial NAND
+    kFlexSpiDeviceType_SerialRAM = 3,       //!< Flash devices are Serial RAM/HyperFLASH
+    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
+    kFlexSpiDeviceType_MCP_NOR_RAM = 0x13,  //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+};
+
+//!@brief Flash Pad Definitions
+enum
+{
+    kSerialFlash_1Pad = 1,
+    kSerialFlash_2Pads = 2,
+    kSerialFlash_4Pads = 4,
+    kSerialFlash_8Pads = 8,
+};
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _lut_sequence
+{
+    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
+    uint16_t reserved;
+} flexspi_lut_seq_t;
+
+//!@brief Flash Configuration Command Type
+enum
+{
+    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
+    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
+    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
+    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
+    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
+    kDeviceConfigCmdType_Reset,      //!< Reset device command
+};
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _FlexSPIConfig
+{
+    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
+    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+    uint8_t csHoldTime;       //!< [0x00d-0x00d] CS hold time, default value: 3
+    uint8_t csSetupTime;      //!< [0x00e-0x00e] CS setup time, default value: 3
+    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+    //! Serial NAND, need to refer to datasheet
+    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+    //! Generic configuration, etc.
+    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+    //! DPI/QPI/OPI switch or reset command
+    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+    //! sequence number, [31:16] Reserved
+    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
+    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+    flexspi_lut_seq_t
+        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
+    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
+    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+    //! details
+    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
+    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    //! Chapter for more details
+    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
+    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
+    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
+    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
+    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
+    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
+    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
+    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
+    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
+    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
+    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+    //! busy flag is 0 when flash device is busy
+    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
+    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
+} flexspi_mem_config_t;
+
+/*  */
+#define NOR_CMD_INDEX_READ CMD_INDEX_READ               //!< 0
+#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS   //!< 1
+#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
+#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
+#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
+#define NOR_CMD_INDEX_CHIPERASE 5                       //!< 5
+#define NOR_CMD_INDEX_DUMMY 6                           //!< 6
+#define NOR_CMD_INDEX_ERASEBLOCK 7                      //!< 7
+
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
+    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
+    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8  //!< 8 Erase Block sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
+    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
+
+
+/*
+ *  Serial NOR configuration block
+ */
+typedef struct _flexspi_nor_config
+{
+    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+    uint32_t pageSize;              //!< Page size of Serial NOR
+    uint32_t sectorSize;            //!< Sector size of Serial NOR
+    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
+    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
+    uint8_t reserved0[2];           //!< Reserved for future use
+    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
+    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
+    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint32_t blockSize;             //!< Block size
+    uint32_t reserve2[11];          //!< Reserved for future use
+} flexspi_nor_config_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __FLEXSPI_NOR_FLASH_H__
diff --git a/Ubiquitous/XiZi/board/xidatong/Makefile b/Ubiquitous/XiZi/board/xidatong/Makefile
index 837118429..c50f207a4 100644
--- a/Ubiquitous/XiZi/board/xidatong/Makefile
+++ b/Ubiquitous/XiZi/board/xidatong/Makefile
@@ -1,4 +1,4 @@
-SRC_DIR := third_party_driver
+SRC_DIR := third_party_driver xip
 
 SRC_FILES := board.c
 
diff --git a/Ubiquitous/XiZi/board/xidatong/README.md b/Ubiquitous/XiZi/board/xidatong/README.md
index 3b8e2817b..5eddfd9a1 100644
--- a/Ubiquitous/XiZi/board/xidatong/README.md
+++ b/Ubiquitous/XiZi/board/xidatong/README.md
@@ -156,8 +156,17 @@ make BOARD=xidatong
 ## 3. 烧写及运行
 
 ### 3.1 烧写
+1、烧写工具：NXP MCU Boot Utility，可参考[https://github.com/JayHeng/NXP-MCUBootUtility](https://github.com/JayHeng/NXP-MCUBootUtility)
 
+2、xidatong开发板支持UART串口烧写程序，打开NXP MCU Boot Utility后，选择好芯片类型为i.MXRT105x，开发板上电，使用串口转USB线将开发板和PC连接，拨码开关设置为1 on 2 on 3 off 4 off，重新上电，选择对应的COM口和波特率（需关闭串口终端连接，确保该COM口空闲，否则会导致Utility工具连接失败），连接成功后，点击reconnect，等待NXP MCU Boot Utility中红色显示变成蓝色显示，则表示已正确识别并连接到了开发板。如下图所示：
+![NXPBootUtility_1](./img/NXPBootUtility_1.png)
 
+3、同时需要匹配xidatong开发板所使用的Flash型号，点击Boot Device Configuration，在Use Typical Device中选择Winbond_W25QxxxJV，然后点击ok。如下图所示：
+![flashconfig](./img/flashconfig.png)
+
+4、选择编译生成的XiZi_xidatong.elf或bin文件路径，按照图示步骤，将文件烧写至Flash中（link.lds中已构造Flash Bootable image，如有修改Flash相关配置需求，可修改/xip目录内相关文件，无需NXPBootUtility再次构造），若烧写无误，则下列绿色进度条会执行到底。如下图所示：
+![NXPBootUtility_2](./img/NXPBootUtility_2.png)
 ### 3.2 运行结果
 
-
+按照3.1烧写步骤执行后，将拨码开关设置为1 off 2 off 3 off 4 off，重新上电后，重新打开该COM口串口终端，若程序正常，则串口终端上会显示启动信息打印输出。如下图所示：
+![terminal](./img/terminal.png)
diff --git a/Ubiquitous/XiZi/board/xidatong/board.c b/Ubiquitous/XiZi/board/xidatong/board.c
index 6844ef96f..1d8af975a 100644
--- a/Ubiquitous/XiZi/board/xidatong/board.c
+++ b/Ubiquitous/XiZi/board/xidatong/board.c
@@ -300,22 +300,18 @@ void InitBoardHardware()
     BOARD_InitUartPins();
 #endif
 
-#ifdef BSP_USING_CH438
-    BOARD_InitCh438Pins();
-#endif
-
     InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END);
 
 #ifdef BSP_USING_LPUART
     Imxrt1052HwUartInit();
 #endif
 
+    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
+
 #ifdef BSP_USING_CH438
     Imxrt1052HwCh438Init();
 #endif
 
-    InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
-
 #ifdef BSP_USING_SDIO
     Imxrt1052HwSdioInit();
 #endif
diff --git a/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_1.png b/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_1.png
index 734f03825..939f60f23 100644
Binary files a/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_1.png and b/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_1.png differ
diff --git a/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_2.png b/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_2.png
index 671bcb0c2..df8610a7a 100644
Binary files a/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_2.png and b/Ubiquitous/XiZi/board/xidatong/img/NXPBootUtility_2.png differ
diff --git a/Ubiquitous/XiZi/board/xidatong/img/flashconfig.png b/Ubiquitous/XiZi/board/xidatong/img/flashconfig.png
new file mode 100644
index 000000000..9db4bd312
Binary files /dev/null and b/Ubiquitous/XiZi/board/xidatong/img/flashconfig.png differ
diff --git a/Ubiquitous/XiZi/board/xidatong/img/menuconfig.png b/Ubiquitous/XiZi/board/xidatong/img/menuconfig.png
index ede182cfc..8da38688a 100644
Binary files a/Ubiquitous/XiZi/board/xidatong/img/menuconfig.png and b/Ubiquitous/XiZi/board/xidatong/img/menuconfig.png differ
diff --git a/Ubiquitous/XiZi/board/xidatong/img/menuconfig1.png b/Ubiquitous/XiZi/board/xidatong/img/menuconfig1.png
index 8cb7e6f40..cb8291f00 100644
Binary files a/Ubiquitous/XiZi/board/xidatong/img/menuconfig1.png and b/Ubiquitous/XiZi/board/xidatong/img/menuconfig1.png differ
diff --git a/Ubiquitous/XiZi/board/xidatong/img/terminal.png b/Ubiquitous/XiZi/board/xidatong/img/terminal.png
index 8dad4f4d1..75d214c2f 100644
Binary files a/Ubiquitous/XiZi/board/xidatong/img/terminal.png and b/Ubiquitous/XiZi/board/xidatong/img/terminal.png differ
diff --git a/Ubiquitous/XiZi/board/xidatong/link-usb.lds b/Ubiquitous/XiZi/board/xidatong/link-usb.lds
index 570c10d29..fc005fd55 100755
--- a/Ubiquitous/XiZi/board/xidatong/link-usb.lds
+++ b/Ubiquitous/XiZi/board/xidatong/link-usb.lds
@@ -54,6 +54,9 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
 /* Specify the memory areas */
 MEMORY
 {
+  m_boot_data           (RX)  : ORIGIN = 0x60000000, LENGTH = 0x00001000
+  m_image_vertor_table  (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00001000    
+
   m_interrupts          (RX)  : ORIGIN = 0x60002000, LENGTH = 0x00000400
   m_text                (RX)  : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
   m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00020000
@@ -63,6 +66,17 @@ MEMORY
 /* Define output sections */
 SECTIONS
 {
+  .boot_data :
+  {
+    KEEP(*(.boot_hdr.conf))
+  } > m_boot_data
+
+  .image_vertor_table :
+  {
+    KEEP(*(.boot_hdr.ivt))
+    KEEP(*(.boot_hdr.boot_data))
+    KEEP(*(.boot_hdr.dcd_data))
+  } > m_image_vertor_table
 
   /* The startup code goes first into internal RAM */
   .interrupts :
diff --git a/Ubiquitous/XiZi/board/xidatong/link.lds b/Ubiquitous/XiZi/board/xidatong/link.lds
index b4176b174..38d111b23 100644
--- a/Ubiquitous/XiZi/board/xidatong/link.lds
+++ b/Ubiquitous/XiZi/board/xidatong/link.lds
@@ -54,6 +54,9 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
 /* Specify the memory areas */
 MEMORY
 {
+  m_boot_data           (RX)  : ORIGIN = 0x60000000, LENGTH = 0x00001000
+  m_image_vertor_table  (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00001000  
+    
   m_interrupts          (RX)  : ORIGIN = 0x60002000, LENGTH = 0x00000400
   m_text                (RX)  : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
   m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00020000
@@ -63,7 +66,18 @@ MEMORY
 /* Define output sections */
 SECTIONS
 {
+  .boot_data :
+  {
+    KEEP(*(.boot_hdr.conf))
+  } > m_boot_data
 
+  .image_vertor_table :
+  {
+    KEEP(*(.boot_hdr.ivt))
+    KEEP(*(.boot_hdr.boot_data))
+    KEEP(*(.boot_hdr.dcd_data))
+  } > m_image_vertor_table
+  
   /* The startup code goes first into internal RAM */
   .interrupts :
   {
diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Kconfig b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Kconfig
new file mode 100644
index 000000000..389b67525
--- /dev/null
+++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Kconfig
@@ -0,0 +1,39 @@
+config CH438_BUS_NAME
+    string
+    default "extuart"
+
+config CH438_DRIVER_NAME
+    string
+    default "extuart_drv"
+
+config CH438_DEVICE_NAME_0
+    string
+    default "extuart_dev0"
+
+config CH438_DEVICE_NAME_1
+    string
+    default "extuart_dev1"
+
+config CH438_DEVICE_NAME_2
+    string
+    default "extuart_dev2"
+
+config CH438_DEVICE_NAME_3
+    string
+    default "extuart_dev3"
+
+config CH438_DEVICE_NAME_4
+    string
+    default "extuart_dev4"
+
+config CH438_DEVICE_NAME_5
+    string
+    default "extuart_dev5"
+
+config CH438_DEVICE_NAME_6
+    string
+    default "extuart_dev6"
+
+config CH438_DEVICE_NAME_7
+    string
+    default "extuart_dev7"
diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Makefile b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Makefile
new file mode 100644
index 000000000..47968574c
--- /dev/null
+++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/Makefile
@@ -0,0 +1,4 @@
+SRC_FILES := connect_ch438.c
+
+
+include $(KERNEL_ROOT)/compiler.mk
diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/connect_ch438.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/connect_ch438.c
new file mode 100644
index 000000000..abead660c
--- /dev/null
+++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/connect_ch438.c
@@ -0,0 +1,1296 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_ch438.c
+* @brief support to register ch438 pointer and function
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-03-17
+*/
+
+#include <connect_ch438.h>
+
+static const uint8 offset_addr[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,};		/* uart offset address*/
+static const uint8 interrupt_num[8] = {0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,};	/* SSR register data*/
+static BusType ch438_pin;
+static int ch438_sem = NONE;
+
+static void Ch438Irq(void *parameter)
+{
+	KSemaphoreAbandon(ch438_sem);
+}
+
+/**
+ * The time delay function.
+ *
+ * @param microseconds.
+ */
+static void ImxrtUdelay(uint32 us)
+{
+    uint32 ticks;
+    uint32 told, tnow, tcnt = 0;
+    uint32 reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1) {
+        tnow = SysTick->VAL;
+        if (tnow != told) {
+            if (tnow < told) {
+                tcnt += told - tnow;
+            } else {
+                tcnt += reload - tnow + told;
+            }
+
+            told = tnow;
+            if (tcnt >= ticks) {
+                break;
+            }
+        }
+    }
+}
+
+void CH438SetOutput(void)
+{
+	struct PinParam pin_cfg;	
+	int ret = 0;
+
+	struct BusConfigureInfo configure_info;
+	configure_info.configure_cmd = OPE_CFG;
+	configure_info.private_data = (void *)&pin_cfg;
+
+    pin_cfg.cmd = GPIO_CONFIG_MODE;
+    pin_cfg.pin = CH438_D0_PIN;
+    pin_cfg.mode = GPIO_CFG_OUTPUT;
+
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config CH438_D0_PIN pin %d failed!\n", CH438_D0_PIN);
+        return ;
+    }
+
+	pin_cfg.pin = CH438_D1_PIN;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config CH438_D1_PIN pin %d failed!\n", CH438_D1_PIN);
+        return ;
+    }
+
+	pin_cfg.pin = CH438_D2_PIN;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config CH438_D2_PIN pin %d failed!\n", CH438_D2_PIN);
+        return ;
+    }
+
+	pin_cfg.pin = CH438_D3_PIN;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config CH438_D3_PIN pin %d failed!\n", CH438_D3_PIN);
+        return ;
+    }
+
+	pin_cfg.pin = CH438_D4_PIN;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config CH438_D4_PIN pin %d failed!\n", CH438_D4_PIN);
+        return ;
+    }
+
+	pin_cfg.pin = CH438_D5_PIN;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config CH438_D5_PIN pin %d failed!\n", CH438_D5_PIN);
+        return ;
+    }
+
+	pin_cfg.pin = CH438_D6_PIN;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config CH438_D6_PIN pin %d failed!\n", CH438_D6_PIN);
+        return ;
+    }
+
+	pin_cfg.pin = CH438_D7_PIN;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config CH438_D7_PIN pin %d failed!\n", CH438_D7_PIN);
+        return ;
+    }
+}
+
+void CH438SetInput(void)
+{
+	struct PinParam pin_cfg;	
+	int ret = 0;
+
+	struct BusConfigureInfo configure_info;
+	configure_info.configure_cmd = OPE_CFG;
+	configure_info.private_data = (void *)&pin_cfg;
+
+    pin_cfg.cmd = GPIO_CONFIG_MODE;
+    pin_cfg.pin = CH438_D0_PIN;
+    pin_cfg.mode = GPIO_CFG_INPUT_PULLUP;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config CH438_D0_PIN pin %d INPUT_PULLUP failed!\n", CH438_D0_PIN);
+        return ;
+    }
+
+	pin_cfg.pin = CH438_D1_PIN;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config CH438_D1_PIN pin %d INPUT_PULLUP failed!\n", CH438_D1_PIN);
+        return ;
+    }
+
+	pin_cfg.pin = CH438_D2_PIN;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config CH438_D2_PIN pin %d INPUT_PULLUP failed!\n", CH438_D2_PIN);
+        return ;
+    }
+
+	pin_cfg.pin = CH438_D3_PIN;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config CH438_D3_PIN pin %d INPUT_PULLUP failed!\n", CH438_D3_PIN);
+        return ;
+    }
+
+	pin_cfg.pin = CH438_D4_PIN;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config CH438_D4_PIN pin %d INPUT_PULLUP failed!\n", CH438_D4_PIN);
+        return ;
+    }
+
+	pin_cfg.pin = CH438_D5_PIN;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config CH438_D5_PIN pin %d INPUT_PULLUP failed!\n", CH438_D5_PIN);
+        return ;
+    }
+
+	pin_cfg.pin = CH438_D6_PIN;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config CH438_D6_PIN pin %d INPUT_PULLUP failed!\n", CH438_D6_PIN);
+        return ;
+    }
+
+	pin_cfg.pin = CH438_D7_PIN;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config CH438_D7_PIN pin %d INPUT_PULLUP failed!\n", CH438_D7_PIN);
+        return ;
+    }
+}
+
+/*********************************************************************************************************
+** Function name: ReadCH438Data
+** Function: read data from CH438
+** input: address
+**
+** output: data
+**         
+** date: 2011.8.26
+**-------------------------------------------------------------------------------------------------------
+** modify:
+** date:
+**-------------------------------------------------------------------------------------------------------
+********************************************************************************************************/
+uint8 ReadCH438Data( uint8 addr )
+{
+//read data api
+
+//ALE WR RD is high level when not busy, when reading data, put address on the serial port and put ALE low level for a few clock
+
+//switch input pin, put RD low level, delay a few clock, read the data from the serial port
+
+//put RD and ALE high level
+	uint8 dat;
+	struct PinStat pin_stat;
+	struct BusBlockWriteParam write_param;
+	struct BusBlockReadParam read_param;
+	write_param.buffer = (void *)&pin_stat;
+	read_param.buffer = (void *)&pin_stat;
+	
+	pin_stat.val = GPIO_HIGH;
+
+    pin_stat.pin = CH438_NWR_PIN;
+    BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+
+	pin_stat.pin = CH438_NRD_PIN;
+    BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+
+	pin_stat.pin = CH438_ALE_PIN;
+    BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+
+	CH438SetOutput();
+	ImxrtUdelay(1);
+	
+	if (addr &0x80) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D7_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D7_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (addr &0x40) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D6_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D6_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (addr &0x20) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D5_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D5_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (addr &0x10) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D4_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D4_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (addr &0x08) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D3_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D3_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (addr &0x04) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D2_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D2_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (addr &0x02) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D1_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D1_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (addr &0x01) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D0_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D0_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	ImxrtUdelay(1);
+
+	pin_stat.val = GPIO_LOW;
+    pin_stat.pin = CH438_ALE_PIN;
+    BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+
+	ImxrtUdelay(1);		
+
+	CH438SetInput();
+	ImxrtUdelay(1);
+
+	pin_stat.val = GPIO_LOW;
+    pin_stat.pin = CH438_NRD_PIN;
+    BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	
+	ImxrtUdelay(1);	
+	
+	dat = 0;
+
+    pin_stat.pin = CH438_D7_PIN;
+    if(BusDevReadData(ch438_pin->owner_haldev, &read_param)) 
+		dat |= 0x80;
+
+	pin_stat.pin = CH438_D6_PIN;
+	if (BusDevReadData(ch438_pin->owner_haldev, &read_param))	
+		dat |= 0x40;
+
+	pin_stat.pin = CH438_D5_PIN;
+	if (BusDevReadData(ch438_pin->owner_haldev, &read_param))	
+		dat |= 0x20;
+
+	pin_stat.pin = CH438_D4_PIN;
+	if (BusDevReadData(ch438_pin->owner_haldev, &read_param))	
+		dat |= 0x10;
+
+	pin_stat.pin = CH438_D3_PIN;
+	if (BusDevReadData(ch438_pin->owner_haldev, &read_param))	
+		dat |= 0x08;
+
+	pin_stat.pin = CH438_D2_PIN;
+	if (BusDevReadData(ch438_pin->owner_haldev, &read_param))	
+		dat |= 0x04;
+
+	pin_stat.pin = CH438_D1_PIN;
+	if (BusDevReadData(ch438_pin->owner_haldev, &read_param))	
+		dat |= 0x02;
+
+	pin_stat.pin = CH438_D0_PIN;
+	if (BusDevReadData(ch438_pin->owner_haldev, &read_param))	
+		dat |= 0x01;
+	
+	pin_stat.val = GPIO_HIGH;
+    pin_stat.pin = CH438_NRD_PIN;
+    BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+
+	pin_stat.val = GPIO_HIGH;
+    pin_stat.pin = CH438_ALE_PIN;
+    BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+
+	ImxrtUdelay(1);
+
+	return dat;
+}
+	
+void WriteCH438Data(uint8 addr, uint8 dat)
+{
+	struct PinStat pin_stat;
+	struct BusBlockWriteParam write_param;
+	write_param.buffer = (void *)&pin_stat;
+
+	pin_stat.val = GPIO_HIGH;
+    pin_stat.pin = CH438_ALE_PIN;
+    BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+
+	pin_stat.val = GPIO_HIGH;
+    pin_stat.pin = CH438_NRD_PIN;
+    BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+
+	pin_stat.val = GPIO_HIGH;
+    pin_stat.pin = CH438_NWR_PIN;
+    BusDevWriteData(ch438_pin->owner_haldev, &write_param);	
+
+	CH438SetOutput();
+	ImxrtUdelay(1);	
+	
+	if (addr &0x80) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D7_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D7_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (addr &0x40) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D6_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D6_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (addr &0x20) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D5_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D5_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (addr &0x10) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D4_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D4_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (addr &0x08) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D3_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D3_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (addr &0x04) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D2_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D2_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (addr &0x02) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D1_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D1_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (addr &0x01) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D0_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D0_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	ImxrtUdelay(1);
+
+	pin_stat.val = GPIO_LOW;
+    pin_stat.pin = CH438_ALE_PIN;
+    BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+
+	ImxrtUdelay(1);
+
+	if (dat &0x80) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D7_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D7_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (dat &0x40) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D6_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D6_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (dat &0x20) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D5_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D5_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (dat &0x10) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D4_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D4_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (dat &0x08) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D3_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D3_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (dat &0x04) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D2_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D2_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (dat &0x02) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D1_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D1_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	if (dat &0x01) {
+		pin_stat.val = GPIO_HIGH;
+    	pin_stat.pin = CH438_D0_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	} else {
+		pin_stat.val = GPIO_LOW;
+    	pin_stat.pin = CH438_D0_PIN;
+    	BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	}
+
+	ImxrtUdelay(1);
+
+	pin_stat.val = GPIO_LOW;
+    pin_stat.pin = CH438_NWR_PIN;
+    BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+
+	ImxrtUdelay(1);
+
+	pin_stat.val = GPIO_HIGH;
+    pin_stat.pin = CH438_NWR_PIN;
+    BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+
+	pin_stat.val = GPIO_HIGH;
+    pin_stat.pin = CH438_ALE_PIN;
+    BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+	
+	ImxrtUdelay(1);	
+
+	CH438SetInput();
+
+	return;
+}
+
+/*********************************************************************************************************
+** Function name: WriteCH438Block
+** Function: write data to CH438
+** input: CH438 register address, data block length, data cache address
+**
+** output: 
+**         
+** date: 2011.8.26
+**-------------------------------------------------------------------------------------------------------
+** modify:
+** date:
+**-------------------------------------------------------------------------------------------------------
+********************************************************************************************************/
+void WriteCH438Block(uint8 maddr, uint8 mlen, uint8 *mbuf)   
+{
+    while (mlen--) {
+		WriteCH438Data(maddr, *mbuf++);
+	}
+}
+
+/*********************************************************************************************************
+** Function name: Ch438UartSend
+** Function: active FIFO mode, CH438 send multibyte data by uart 0, max length is 128 bytes a single time
+** input: send data cache address, send data length
+**
+** output: 
+**
+** date: 2011.8.26.
+**-------------------------------------------------------------------------------------------------------
+** modify:
+** date:
+**-------------------------------------------------------------------------------------------------------
+********************************************************************************************************/
+void  Ch438UartSend( uint8	ext_uart_no,uint8 *data, uint8 Num )
+{
+	uint8 REG_LSR_ADDR,REG_THR_ADDR;
+	
+	REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR;
+	REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
+			
+    while (1) {
+        while((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_TEMT) == 0);    /* wait for sending data done, THR and TSR is NULL */
+
+        if (Num <= 128) {
+            WriteCH438Block(REG_THR_ADDR, Num, data);
+            break;
+        } else {
+            WriteCH438Block(REG_THR_ADDR, 128, data);
+            Num -= 128;
+            data += 128;
+        }
+    }
+}
+
+/*********************************************************************************************************
+** Function name: Ch438UartRcv
+** Function: forbidden FIFO mode, CH438 receive multibyte data from uart 0
+** input: recv data address
+**
+** output: recv data length
+**
+** date: 2011.8.26
+**-------------------------------------------------------------------------------------------------------
+** modify:
+** date:
+**-------------------------------------------------------------------------------------------------------
+********************************************************************************************************/
+uint8 Ch438UartRcv(uint8 ext_uart_no, uint8 *buf, x_size_t size)
+{
+    uint8 rcv_num = 0;
+	uint8 dat = 0;
+	uint8 REG_LSR_ADDR,REG_RBR_ADDR;
+	uint8 *read_buffer;
+	x_size_t buffer_index = 0;
+	
+	read_buffer = buf;
+	
+	REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR;
+	REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
+			
+	while ((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0);    /* wait for data is ready */
+
+    while (((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0x01) && (size != 0)) {
+		dat = ReadCH438Data(REG_RBR_ADDR);
+
+		*read_buffer = dat;
+		read_buffer++;
+		buffer_index++;
+
+		if (CH438_BUFFSIZE == buffer_index) {
+			buffer_index = 0;
+			read_buffer = buf;
+		}
+			
+        rcv_num = rcv_num + 1;
+		--size;
+    }
+
+    return rcv_num;
+}
+
+static void Timeout438Proc(void *parameter) 
+{
+	uint8_t	rbr,lsr;
+	
+	while( ( ReadCH438Data( REG_LSR0_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
+		rbr =  ReadCH438Data( REG_RBR0_ADDR );
+		KPrintf("0.RBR=%02x\r\n",rbr);
+	}
+
+	while( ( ReadCH438Data( REG_LSR1_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
+		rbr =  ReadCH438Data( REG_RBR1_ADDR );
+		KPrintf("1.RBR=%02x\r\n",rbr);
+	}
+
+	while( ( ReadCH438Data( REG_LSR2_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
+		rbr =  ReadCH438Data( REG_RBR2_ADDR );
+		KPrintf("2.RBR=%02x\r\n",rbr);
+	}
+
+	while( ( ReadCH438Data( REG_LSR3_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
+		rbr =  ReadCH438Data( REG_RBR3_ADDR );
+		KPrintf("3.RBR=%02x\r\n",rbr);
+	}
+
+	while( ( ReadCH438Data( REG_LSR4_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
+		rbr =  ReadCH438Data( REG_RBR4_ADDR );
+		KPrintf("4.RBR=%02x\r\n",rbr);
+	}
+
+	while( ( ReadCH438Data( REG_LSR5_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
+		rbr =  ReadCH438Data( REG_RBR5_ADDR );
+		KPrintf("5.RBR=%02x\r\n",rbr);
+	}
+
+	while( ( ReadCH438Data( REG_LSR6_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
+		rbr =  ReadCH438Data( REG_RBR6_ADDR );
+		KPrintf("6.RBR=%02x\r\n",rbr);
+	}
+
+	while( ( ReadCH438Data( REG_LSR7_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
+		rbr =  ReadCH438Data( REG_RBR7_ADDR );
+		KPrintf("7.RBR=%02x\r\n",rbr);
+	}
+}
+
+void Ch438PortInit( uint8 ext_uart_no,uint32	BaudRate )
+{
+	uint32 div;
+	uint8 DLL,DLM,dlab;
+	uint8 REG_LCR_ADDR;
+	uint8 REG_DLL_ADDR;
+	uint8 REG_DLM_ADDR;
+	uint8 REG_IER_ADDR;
+	uint8 REG_MCR_ADDR;
+	uint8 REG_FCR_ADDR;
+	uint8 REG_RBR_ADDR;
+	uint8 REG_THR_ADDR;
+	uint8 REG_IIR_ADDR;
+	
+	REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR;
+	REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR;
+	REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR;
+	REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR;
+	REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR;
+	REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR;
+	REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
+	REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
+	REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR;
+			
+    WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET);             /* reset the uart */
+	MdelayKTask(50);
+	
+	dlab = ReadCH438Data(REG_IER_ADDR);
+	dlab &= 0xDF;
+	WriteCH438Data(REG_IER_ADDR, dlab);
+	
+	dlab = ReadCH438Data(REG_LCR_ADDR);
+	dlab |= 0x80;		//set LCR register DLAB bit 1
+	WriteCH438Data(REG_LCR_ADDR, dlab);
+
+    div = (Fpclk >> 4) / BaudRate;
+    DLM = div >> 8;
+    DLL = div & 0xff;
+	WriteCH438Data(REG_DLL_ADDR, DLL);             /* set bps */
+    WriteCH438Data(REG_DLM_ADDR, DLM);
+	WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN);    /* set FIFO mode, 112 bytes */
+
+    WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0);                     /* 8 bit word size, 1 bit stop bit, no crc */
+
+    WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV);    /* enable interrupt */
+
+    WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2);// | BIT_MCR_RTS     | BIT_MCR_DTR 	);              /* allow interrupt output, DTR and RTS is 1 */
+
+	WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR)| BIT_FCR_TFIFORST);  /* release the data in FIFO */
+}
+
+void CH438PortInitParityCheck(uint8 ext_uart_no, uint32 BaudRate)
+{
+	uint32 div;
+	uint8 DLL,DLM,dlab;
+	uint8 REG_LCR_ADDR;
+	uint8 REG_DLL_ADDR;
+	uint8 REG_DLM_ADDR;
+	uint8 REG_IER_ADDR;
+	uint8 REG_MCR_ADDR;
+	uint8 REG_FCR_ADDR;
+	uint8 REG_RBR_ADDR;
+	uint8 REG_THR_ADDR;
+	uint8 REG_IIR_ADDR;
+	
+	REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR;
+	REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR;
+	REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR;
+	REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR;
+	REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR;
+	REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR;
+	REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
+	REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
+	REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR;
+			
+    WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET);             /* reset the uart */
+	MdelayKTask(50);
+	
+	dlab = ReadCH438Data(REG_IER_ADDR);
+	dlab &= 0xDF;
+	WriteCH438Data(REG_IER_ADDR, dlab);
+	
+	dlab = ReadCH438Data(REG_LCR_ADDR);
+	dlab |= 0x80;		//set LCR register DLAB bit 1
+	WriteCH438Data(REG_LCR_ADDR, dlab);
+
+    div = (Fpclk >> 4) / BaudRate;
+    DLM = div >> 8;
+    DLL = div & 0xff;
+	WriteCH438Data(REG_DLL_ADDR, DLL);             /* set bps */
+    WriteCH438Data(REG_DLM_ADDR, DLM);
+	WriteCH438Data(REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_FIFOEN);    /* set FIFO mode, 64 bytes */
+
+	WriteCH438Data(REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0 | BIT_LCR_PAREN | BIT_LCR_PARMODE0);		/* 8 bit work size, 1 bit stop bit, even parity check */
+
+    WriteCH438Data(REG_IER_ADDR, BIT_IER_IERECV);    /* enable interrupt */
+
+    WriteCH438Data(REG_MCR_ADDR, BIT_MCR_OUT2);// | BIT_MCR_RTS     | BIT_MCR_DTR 	);              /* allow interrupt output, DTR and RTS is 1 */
+
+	WriteCH438Data(REG_FCR_ADDR, ReadCH438Data(REG_FCR_ADDR)| BIT_FCR_TFIFORST);  /* release the data in FIFO */
+}
+
+static uint32 ImxrtCh438Configure(struct SerialCfgParam *ext_serial_cfg)
+{
+	NULL_PARAM_CHECK(ext_serial_cfg);
+
+	switch (ext_serial_cfg->data_cfg.port_configure)
+	{
+		case PORT_CFG_INIT:
+			Ch438PortInit(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate);
+			break;
+		case PORT_CFG_PARITY_CHECK:
+			CH438PortInitParityCheck(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate);
+			break;
+		default:
+			KPrintf("ImxrtCh438Configure do not support configure %d\n", ext_serial_cfg->data_cfg.port_configure);
+			return ERROR;
+			break;
+	}
+
+	return EOK;
+}
+
+static uint32 ImxrtCh438Init(struct SerialDriver *serial_drv,  struct SerialCfgParam *ext_serial_cfg)
+{
+	NULL_PARAM_CHECK(serial_drv);
+	
+	struct PinParam pin_cfg;
+	struct PinStat pin_stat;
+	int ret = 0;
+
+	struct BusConfigureInfo configure_info;
+	configure_info.configure_cmd = OPE_CFG;
+	configure_info.private_data = (void *)&pin_cfg;
+
+	struct BusBlockWriteParam write_param;
+	write_param.buffer = (void *)&pin_stat;
+
+	ch438_pin = PinBusInitGet();
+
+	CH438SetOutput();
+
+	/* config NWR pin as output*/
+    pin_cfg.cmd = GPIO_CONFIG_MODE;
+    pin_cfg.pin = CH438_NWR_PIN;
+    pin_cfg.mode = GPIO_CFG_OUTPUT;
+
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config NWR pin %d failed!\n", CH438_NWR_PIN);
+        return ERROR;
+    }
+
+	/* config NRD pin as output*/
+	KPrintf("####TEST CH438_NRD_PIN %u start####\n", CH438_NRD_PIN);
+	pin_cfg.pin = CH438_NRD_PIN;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config NRD pin %d failed!\n", CH438_NRD_PIN);
+        return ERROR;
+    }
+	KPrintf("####TEST CH438_NRD_PIN %u done####\n", CH438_NRD_PIN);
+
+	/* config ALE pin as output*/
+	pin_cfg.pin = CH438_ALE_PIN;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config ALE pin %d failed!\n", CH438_ALE_PIN);
+        return ERROR;
+    }
+
+	/* set NWR pin as high*/
+    pin_stat.pin = CH438_NWR_PIN;
+    pin_stat.val = GPIO_HIGH;
+    BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+
+	/* set NRD pin as high*/
+    pin_stat.pin = CH438_NRD_PIN;
+    pin_stat.val = GPIO_HIGH;
+    BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+
+	/* set ALE pin as high*/
+    pin_stat.pin = CH438_ALE_PIN;
+    pin_stat.val = GPIO_HIGH;
+    BusDevWriteData(ch438_pin->owner_haldev, &write_param);
+
+	return ImxrtCh438Configure(ext_serial_cfg);
+}
+
+static uint32 Ch438DrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+
+    struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
+	struct SerialCfgParam *ext_serial_cfg = (struct SerialCfgParam *)configure_info->private_data;
+
+    switch (configure_info->configure_cmd)
+    {
+		case OPE_INT:
+			ret = ImxrtCh438Init(serial_drv, ext_serial_cfg);
+			break;
+		default:
+			break;
+    }
+
+    return ret;
+}
+
+static uint32 ImxrtCh438WriteData(void *dev, struct BusBlockWriteParam *write_param)
+{
+	NULL_PARAM_CHECK(dev);
+	NULL_PARAM_CHECK(write_param);
+
+	struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev;
+	struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
+
+	Ch438UartSend(dev_param->ext_uart_no, (uint8 *)write_param->buffer, write_param->size);
+
+	return EOK;
+}
+
+static uint32 ImxrtCh438ReadData(void *dev, struct BusBlockReadParam *read_param)
+{
+	NULL_PARAM_CHECK(dev);
+	NULL_PARAM_CHECK(read_param);
+
+	x_err_t result;
+	uint8 rcv_num = 0;
+	uint8 gInterruptStatus;
+	uint8 InterruptStatus;
+	static uint8 dat;
+	uint8 REG_LCR_ADDR;
+	uint8 REG_DLL_ADDR;
+	uint8 REG_DLM_ADDR;
+	uint8 REG_IER_ADDR;
+	uint8 REG_MCR_ADDR;
+	uint8 REG_FCR_ADDR;
+	uint8 REG_RBR_ADDR;
+	uint8 REG_THR_ADDR;
+	uint8 REG_IIR_ADDR;
+	uint8 REG_LSR_ADDR;
+	uint8 REG_MSR_ADDR;
+
+	struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev;
+	struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
+
+	result = KSemaphoreObtain(ch438_sem, WAITING_FOREVER);
+	if (EOK == result) {
+		gInterruptStatus = ReadCH438Data(REG_SSR_ADDR);		
+		if (!gInterruptStatus) { 
+			dat = ReadCH438Data(REG_LCR0_ADDR);	
+			dat = ReadCH438Data(REG_IER0_ADDR);	
+			dat = ReadCH438Data(REG_MCR0_ADDR);	
+			dat = ReadCH438Data(REG_LSR0_ADDR);	
+			dat = ReadCH438Data(REG_MSR0_ADDR);	
+			dat = ReadCH438Data(REG_RBR0_ADDR);	
+			dat = ReadCH438Data(REG_THR0_ADDR);	
+			dat = ReadCH438Data(REG_IIR0_ADDR);	
+			dat = dat ;	
+		} else {
+			if (gInterruptStatus & interrupt_num[dev_param->ext_uart_no]) {   /* check which uart port triggers interrupt*/
+				REG_LCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LCR0_ADDR;
+				REG_DLL_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLL0_ADDR;
+				REG_DLM_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLM0_ADDR;
+				REG_IER_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IER0_ADDR;
+				REG_MCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MCR0_ADDR;
+				REG_FCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_FCR0_ADDR;
+				REG_RBR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_RBR0_ADDR;
+				REG_THR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_THR0_ADDR;
+				REG_IIR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IIR0_ADDR;
+				REG_LSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LSR0_ADDR;
+				REG_MSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MSR0_ADDR;				
+							
+				InterruptStatus = ReadCH438Data( REG_IIR_ADDR ) & 0x0f;    /* read the status of the uart port*/
+
+				switch( InterruptStatus )
+				{
+					case INT_NOINT:			/* NO INTERRUPT */					
+						break;
+					case INT_THR_EMPTY:		/* THR EMPTY INTERRUPT*/							
+						break;
+					case INT_RCV_OVERTIME:	/* RECV OVERTIME INTERRUPT*/
+					case INT_RCV_SUCCESS:	/*  RECV INTERRUPT SUCCESSFULLY*/
+						rcv_num = Ch438UartRcv(dev_param->ext_uart_no, (uint8 *)read_param->buffer, read_param->size);
+						read_param->read_length = rcv_num;
+						break;
+					case INT_RCV_LINES:		/* RECV LINES INTERRUPT */
+						ReadCH438Data( REG_LSR_ADDR );
+						break;
+					case INT_MODEM_CHANGE:	/* MODEM CHANGE INTERRUPT */
+						ReadCH438Data( REG_MSR_ADDR );
+						break;
+					default:
+						break;
+				}
+			}
+		}
+	}
+	return rcv_num;
+}
+
+static const struct SerialDevDone dev_done = 
+{
+    NONE,
+    NONE,
+    ImxrtCh438WriteData,
+    ImxrtCh438ReadData,
+};
+
+static void Ch438InitDefault(struct SerialDriver *serial_drv)
+{
+	struct PinParam PinCfg;
+	BusType ch438_pin;
+
+    struct BusConfigureInfo configure_info;
+
+    int ret = 0;
+	configure_info.configure_cmd = OPE_CFG;
+	configure_info.private_data = (void *)&PinCfg;
+
+	ch438_sem = KSemaphoreCreate(0);
+	if (ch438_sem < 0) {
+		KPrintf("Ch438InitDefault create sem failed .\n");
+		return;
+	}
+
+	ch438_pin = PinBusInitGet();
+
+	PinCfg.cmd = GPIO_CONFIG_MODE;
+    PinCfg.pin = CH438_INT_PIN;
+    PinCfg.mode = GPIO_CFG_INPUT_PULLUP;
+    ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config BSP_CH438_INT_PIN pin %d failed!\n", CH438_INT_PIN);
+        return;
+    }
+
+	PinCfg.cmd = GPIO_IRQ_REGISTER;
+    PinCfg.pin = CH438_INT_PIN;
+    PinCfg.irq_set.irq_mode = GPIO_IRQ_EDGE_FALLING;
+    PinCfg.irq_set.hdr = Ch438Irq;
+    PinCfg.irq_set.args = NONE;
+	ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config BSP_CH438_INT_PIN  %d failed!\n", CH438_INT_PIN);
+        return;
+    }
+
+	PinCfg.cmd = GPIO_IRQ_ENABLE;
+    PinCfg.pin = CH438_INT_PIN;
+    ret = BusDrvConfigure(ch438_pin->owner_driver, &configure_info);
+    if (ret != EOK) {
+        KPrintf("config BSP_CH438_INT_PIN  %d failed!\n", CH438_INT_PIN);
+        return;
+    }
+
+    struct SerialCfgParam serial_cfg;
+    memset(&serial_cfg, 0, sizeof(struct SerialCfgParam));
+    configure_info.configure_cmd = OPE_INT;
+    configure_info.private_data = (void *)&serial_cfg;
+
+    serial_cfg.data_cfg.port_configure = PORT_CFG_INIT;
+
+    serial_cfg.data_cfg.ext_uart_no = 0;
+    serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_115200;
+    BusDrvConfigure(&serial_drv->driver, &configure_info);
+
+    serial_cfg.data_cfg.ext_uart_no = 1;
+    serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600;
+    BusDrvConfigure(&serial_drv->driver, &configure_info);
+
+    serial_cfg.data_cfg.ext_uart_no = 2;
+    serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600;
+    BusDrvConfigure(&serial_drv->driver, &configure_info);
+
+    serial_cfg.data_cfg.ext_uart_no = 3;
+    serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600;
+    BusDrvConfigure(&serial_drv->driver, &configure_info);
+
+    serial_cfg.data_cfg.ext_uart_no = 4;
+    serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600;
+    BusDrvConfigure(&serial_drv->driver, &configure_info);
+
+    serial_cfg.data_cfg.ext_uart_no = 5;
+    serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600;
+    BusDrvConfigure(&serial_drv->driver, &configure_info);
+
+    serial_cfg.data_cfg.ext_uart_no = 6;
+    serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600;
+    BusDrvConfigure(&serial_drv->driver, &configure_info);
+
+    serial_cfg.data_cfg.ext_uart_no = 7;
+    serial_cfg.data_cfg.serial_baud_rate = BAUD_RATE_9600;
+    BusDrvConfigure(&serial_drv->driver, &configure_info);
+}
+
+static uint32 ImxrtCh438DevRegister(struct SerialHardwareDevice *serial_dev, char *dev_name)
+{
+	x_err_t ret = EOK;
+	serial_dev->dev_done = &dev_done;
+	serial_dev->ext_serial_mode = RET_TRUE;
+    ret = SerialDeviceRegister(serial_dev, NONE, dev_name);
+    if (ret != EOK) {
+        KPrintf("ImxrtHwCh438Init Serial device %s register error %d\n", dev_name, ret);
+        return ERROR;
+    }
+
+    ret = SerialDeviceAttachToBus(dev_name, CH438_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("ImxrtHwCh438Init Serial device %s register error %d\n", dev_name, ret);
+        return ERROR;
+    }
+
+	return ret;
+}
+
+int Imxrt1052HwCh438Init(void)
+{
+    static struct SerialBus serial_bus;
+    static struct SerialDriver serial_drv;
+
+    x_err_t ret = EOK;
+    
+    ret = SerialBusInit(&serial_bus, CH438_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("ImxrtHwCh438Init Serial bus init error %d\n", ret);
+        return ERROR;
+    }
+
+    serial_drv.configure = Ch438DrvConfigure;
+    ret = SerialDriverInit(&serial_drv, CH438_DRIVER_NAME);
+    if (ret != EOK) {
+        KPrintf("ImxrtHwCh438Init Serial driver init error %d\n", ret);
+        return ERROR;
+    }
+
+    ret = SerialDriverAttachToBus(CH438_DRIVER_NAME, CH438_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("ImxrtHwCh438Init Serial driver attach error %d\n", ret);
+        return ERROR;
+    }
+
+	static struct SerialHardwareDevice serial_dev_0;
+	static struct SerialDevParam dev_param_0;
+	dev_param_0.ext_uart_no = 0;
+	serial_dev_0.haldev.private_data = (void *)&dev_param_0;
+	ret = ImxrtCh438DevRegister(&serial_dev_0, CH438_DEVICE_NAME_0);
+    if (ret != EOK) {
+        KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret);
+        return ERROR;
+    }
+
+	static struct SerialHardwareDevice serial_dev_1;
+	static struct SerialDevParam dev_param_1;
+	dev_param_1.ext_uart_no = 1;
+	serial_dev_1.haldev.private_data = (void *)&dev_param_1;
+	ret = ImxrtCh438DevRegister(&serial_dev_1, CH438_DEVICE_NAME_1);
+    if (ret != EOK) {
+        KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret);
+        return ERROR;
+    }
+
+	static struct SerialHardwareDevice serial_dev_2;
+	static struct SerialDevParam dev_param_2;
+	dev_param_2.ext_uart_no = 2;
+	serial_dev_2.haldev.private_data = (void *)&dev_param_2;
+	ret = ImxrtCh438DevRegister(&serial_dev_2, CH438_DEVICE_NAME_2);
+    if (ret != EOK) {
+        KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret);
+        return ERROR;
+    }
+
+	static struct SerialHardwareDevice serial_dev_3;
+	static struct SerialDevParam dev_param_3;
+	dev_param_3.ext_uart_no = 3;
+	serial_dev_3.haldev.private_data = (void *)&dev_param_3;
+	ret = ImxrtCh438DevRegister(&serial_dev_3, CH438_DEVICE_NAME_3);
+    if (ret != EOK) {
+        KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret);
+        return ERROR;
+    }
+
+	static struct SerialHardwareDevice serial_dev_4;
+	static struct SerialDevParam dev_param_4;
+	dev_param_4.ext_uart_no = 4;
+	serial_dev_4.haldev.private_data = (void *)&dev_param_4;
+	ret = ImxrtCh438DevRegister(&serial_dev_4, CH438_DEVICE_NAME_4);
+    if (ret != EOK) {
+        KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret);
+        return ERROR;
+    }
+
+	static struct SerialHardwareDevice serial_dev_5;
+	static struct SerialDevParam dev_param_5;
+	dev_param_5.ext_uart_no = 5;
+	serial_dev_5.haldev.private_data = (void *)&dev_param_5;
+	ret = ImxrtCh438DevRegister(&serial_dev_5, CH438_DEVICE_NAME_5);
+    if (ret != EOK) {
+        KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret);
+        return ERROR;
+    }
+
+	static struct SerialHardwareDevice serial_dev_6;
+	static struct SerialDevParam dev_param_6;
+	dev_param_6.ext_uart_no = 6;
+	serial_dev_6.haldev.private_data = (void *)&dev_param_6;
+	ret = ImxrtCh438DevRegister(&serial_dev_6, CH438_DEVICE_NAME_6);
+    if (ret != EOK) {
+        KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret);
+        return ERROR;
+    }
+
+	static struct SerialHardwareDevice serial_dev_7;
+	static struct SerialDevParam dev_param_7;
+	dev_param_7.ext_uart_no = 7;
+	serial_dev_7.haldev.private_data = (void *)&dev_param_7;
+	ret = ImxrtCh438DevRegister(&serial_dev_7, CH438_DEVICE_NAME_7);
+    if (ret != EOK) {
+        KPrintf("ImxrtHwCh438Init ImxrtCh438DevRegister error %d\n", ret);
+        return ERROR;
+    }
+
+	Ch438InitDefault(&serial_drv);
+
+    return ret;
+}
+
+void CH438RegTest(unsigned char num)//for test
+{
+	uint8 dat;
+	
+	KPrintf("current test serilnum:  %02x \r\n",offset_addr[num]);
+	KPrintf("IER: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_IER0_ADDR));//?IER
+	KPrintf("IIR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_IIR0_ADDR));//?IIR
+	KPrintf("LCR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_LCR0_ADDR));//?LCR
+	KPrintf("MCR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_MCR0_ADDR));//?MCR
+	KPrintf("LSR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_LSR0_ADDR));//?LSR
+	KPrintf("MSR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_MSR0_ADDR));//?MSR
+	KPrintf("FCR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_FCR0_ADDR));//?FCR
+	KPrintf("SSR: %02x\r\n",ReadCH438Data( offset_addr[num] | REG_SSR_ADDR ));//?SSR
+	
+	KPrintf("SCR0: %02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//?SCR
+	dat = 0x55;
+	WriteCH438Data(offset_addr[num] | REG_SCR0_ADDR, dat);
+	KPrintf("SCR55: %02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//?SCR
+	dat = 0xAA;
+	WriteCH438Data(offset_addr[num] | REG_SCR0_ADDR, dat);
+	KPrintf("SCRAA: %02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//?SCR
+}
diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/common/pin_mux.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/common/pin_mux.c
index 27013148d..63eed88b2 100755
--- a/Ubiquitous/XiZi/board/xidatong/third_party_driver/common/pin_mux.c
+++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/common/pin_mux.c
@@ -8,9 +8,9 @@
 /**
 * @file pin_mux.c
 * @brief support imxrt1052-board pin configure
-* @version 1.0
+* @version 2.0
 * @author AIIT XUOS Lab
-* @date 2021-05-29
+* @date 2022-03-22
 */
 
 /***********************************************************************************************************************
@@ -749,121 +749,9 @@ BOARD_InitPins:
  * Description   : Configures pin routing and optionally pin electrical features.
  *
  * END ****************************************************************************************************************/
-
-void BOARD_InitSPIPins ( void )
-{
-    IOMUXC_SetPinMux (
-        IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK,        /* GPIO_AD_B0_00 is configured as LPSPI3_SCK */
-        0U );                                   /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinMux (
-        IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO,        /* GPIO_AD_B0_01 is configured as LPSPI3_SDO */
-        0U );                                   /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinMux (
-        IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI,        /* GPIO_AD_B0_02 is configured as LPSPI3_SDI */
-        0U );                                   /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinMux (
-        IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0,       /* GPIO_AD_B0_03 is configured as LPSPI3_PCS0 */
-        0U );                                   /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinMux (
-        IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK,        /* GPIO_SD_B0_00 is configured as LPSPI1_SCK */
-        0U );                                   /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinMux (
-        IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0,       /* GPIO_SD_B0_01 is configured as LPSPI1_PCS0 */
-        0U );                                   /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinMux (
-        IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO,        /* GPIO_SD_B0_02 is configured as LPSPI1_SDO */
-        0U );                                   /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinMux (
-        IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI,        /* GPIO_SD_B0_03 is configured as LPSPI1_SDI */
-        0U );                                   /* Software Input On Field: Input Path is determined by functionality */
-
-    IOMUXC_SetPinConfig (
-        IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK,        /* GPIO_AD_B0_00 PAD functional properties : */
-        0x10B0u );                               /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Keeper
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Down
-                                                 Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig (
-        IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO,        /* GPIO_AD_B0_01 PAD functional properties : */
-        0x10B0u );                               /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Keeper
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Down
-                                                 Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig (
-        IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI,        /* GPIO_AD_B0_02 PAD functional properties : */
-        0x10B0u );                               /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Keeper
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Down
-                                                 Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig (
-        IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0,       /* GPIO_AD_B0_03 PAD functional properties : */
-        0x10B0u );                               /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Keeper
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Down
-                                                 Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig (
-        IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK,        /* GPIO_SD_B0_00 PAD functional properties : */
-        0x10B0u );                               /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Keeper
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Down
-                                                 Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig (
-        IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0,       /* GPIO_SD_B0_01 PAD functional properties : */
-        0x10B0u );                               /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Keeper
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Down
-                                                 Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig (
-        IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO,        /* GPIO_SD_B0_02 PAD functional properties : */
-        0x10B0u );                               /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Keeper
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Down
-                                                 Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig (
-        IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI,        /* GPIO_SD_B0_03 PAD functional properties : */
-        0x10B0u );                               /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Disabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Keeper
-                                                 Pull Up / Down Config. Field: 100K Ohm Pull Down
-                                                 Hyst. Enable Field: Hysteresis Disabled */
-}
 void BOARD_InitPins(void) {
   CLOCK_EnableClock(kCLOCK_Iomuxc);           /* iomuxc clock (iomuxc_clk_enable): 0x03u */
-
-//  IOMUXC_SetPinMux(
-//      IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,        /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
-//      0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+                               /* Software Input On Field: Input Path is determined by functionality */
   SemcPinmuxConfig();
 
   IOMUXC_SetPinMux(
@@ -914,16 +802,6 @@ void BOARD_InitPins(void) {
   IOMUXC_SetPinMux(
       IOMUXC_GPIO_EMC_41_ENET_MDIO,           /* GPIO_EMC_41 is configured as ENET_MDIO */
       0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-//  IOMUXC_SetPinConfig(
-//      IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,        /* GPIO_AD_B0_09 PAD functional properties : */
-//      0xB0A9u);                               /* Slew Rate Field: Fast Slew Rate
-//                                                 Drive Strength Field: R0/5
-//                                                 Speed Field: medium(100MHz)
-//                                                 Open Drain Enable Field: Open Drain Disabled
-//                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-//                                                 Pull / Keep Select Field: Pull
-//                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
-//                                                 Hyst. Enable Field: Hysteresis Disabled */
 
   IOMUXC_SetPinConfig(
       IOMUXC_GPIO_AD_B0_03_GPIO1_IO03,        /* GPIO_AD_B0_09 PAD functional properties : */
@@ -1073,37 +951,6 @@ void BOARD_InitPins(void) {
                                                  Hyst. Enable Field: Hysteresis Disabled */
 }
 
-void BOARD_InitI2C1Pins ( void )
-{
-    CLOCK_EnableClock ( kCLOCK_Iomuxc );        /* iomuxc clock (iomuxc_clk_enable): 0x03u */
-    IOMUXC_SetPinMux (
-        IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL,        /* GPIO_AD_B1_00 is configured as LPI2C1_SCL */
-        1U );                                   /* Software Input On Field: Force input path of pad GPIO_AD_B1_00 */
-    IOMUXC_SetPinMux (
-        IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA,        /* GPIO_AD_B1_01 is configured as LPI2C1_SDA */
-        1U );                                   /* Software Input On Field: Force input path of pad GPIO_AD_B1_01 */
-    IOMUXC_SetPinConfig (
-        IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL,        /* GPIO_AD_B1_00 PAD functional properties : */
-        0xD8B0u );                               /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Enabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Keeper
-                                                 Pull Up / Down Config. Field: 22K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Disabled */
-    IOMUXC_SetPinConfig (
-        IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA,        /* GPIO_AD_B1_01 PAD functional properties : */
-        0xD8B0u );                               /* Slew Rate Field: Slow Slew Rate
-                                                 Drive Strength Field: R0/6
-                                                 Speed Field: medium(100MHz)
-                                                 Open Drain Enable Field: Open Drain Enabled
-                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                 Pull / Keep Select Field: Keeper
-                                                 Pull Up / Down Config. Field: 22K Ohm Pull Up
-                                                 Hyst. Enable Field: Hysteresis Disabled */
-}
-
 void BOARD_InitUartPins(void)
 {
 #ifdef BSP_USING_LPUART1
@@ -1150,94 +997,6 @@ void BOARD_InitUartPins(void)
 #endif
 }
 
-void BOARD_InitCh438Pins(void)
-{
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_AD_B1_09_GPIO1_IO25,        /* GPIO1_IO25 is configured as CH438_DATA0 */
-        0U);
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_AD_B1_08_GPIO1_IO24,        /* GPIO1_IO24 is configured as CH438_DATA1 */
-        0U);
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_AD_B1_04_GPIO1_IO20,        /* GPIO1_IO20 is configured as CH438_DATA2 */
-        0U);
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_AD_B1_05_GPIO1_IO21,        /* GPIO1_IO21 is configured as CH438_DATA3 */
-        0U);
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_AD_B1_15_GPIO1_IO31,        /* GPIO1_IO31 is configured as CH438_DATA4 */
-        0U);
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_AD_B1_12_GPIO1_IO28,        /* GPIO1_IO28 is configured as CH438_DATA5 */
-        0U);
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_AD_B1_14_GPIO1_IO30,        /* GPIO1_IO30 is configured as CH438_DATA6 */
-        0U);
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_AD_B1_13_GPIO1_IO29,        /* GPIO1_IO29 is configured as CH438_DATA7 */
-        0U);
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_SD_B1_04_GPIO3_IO04,        /* GPIO3_IO04 is configured as CH438_nWR */
-        0U);
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_SD_B1_05_GPIO3_IO05,        /* GPIO3_IO05 is configured as CH438_nRD */
-        0U);
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_SD_B1_02_GPIO3_IO02,        /* GPIO3_IO02 is configured as CH438_ALE */
-        0U);
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_SD_B1_03_GPIO3_IO03,        /* GPIO3_IO03 is configured as CH438_INT */
-        0U);
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_AD_B0_02_GPIO1_IO02,        /* GPIO3_IO02 is configured as CH438_485_A_DIR */
-        0U);
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_AD_B0_00_GPIO1_IO00,        /* GPIO1_IO00 is configured as CH438_485_B_DIR */
-        0U);
-
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_AD_B1_09_GPIO1_IO25,        /* GPIO1_IO25 is configured as CH438_DATA0 */
-        0x10B0u);
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_AD_B1_08_GPIO1_IO24,        /* GPIO1_IO24 is configured as CH438_DATA1 */
-        0x10B0u);
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_AD_B1_04_GPIO1_IO20,        /* GPIO1_IO20 is configured as CH438_DATA2 */
-        0x10B0u);
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_AD_B1_05_GPIO1_IO21,        /* GPIO1_IO21 is configured as CH438_DATA3 */
-        0x10B0u);
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_AD_B1_15_GPIO1_IO31,        /* GPIO1_IO31 is configured as CH438_DATA4 */
-        0x10B0u);
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_AD_B1_12_GPIO1_IO28,        /* GPIO1_IO28 is configured as CH438_DATA5 */
-        0x10B0u);
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_AD_B1_14_GPIO1_IO30,        /* GPIO1_IO30 is configured as CH438_DATA6 */
-        0x10B0u);
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_AD_B1_13_GPIO1_IO29,        /* GPIO1_IO29 is configured as CH438_DATA7 */
-        0x10B0u);
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_SD_B1_04_GPIO3_IO04,        /* GPIO3_IO04 is configured as CH438_nWR */
-        0x10B0u);
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_SD_B1_05_GPIO3_IO05,        /* GPIO3_IO05 is configured as CH438_nRD */
-        0x10B0u);
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_SD_B1_02_GPIO3_IO02,        /* GPIO3_IO02 is configured as CH438_ALE */
-        0x10B0u);
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_SD_B1_03_GPIO3_IO03,        /* GPIO3_IO03 is configured as CH438_INT */
-        0x10B0u);
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_AD_B0_02_GPIO1_IO02,        /* GPIO3_IO02 is configured as CH438_485_A_DIR */
-        0x10B0u);
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_AD_B0_00_GPIO1_IO00,        /* GPIO1_IO00 is configured as CH438_485_B_DIR */
-        0x10B0u);
-}
 /***********************************************************************************************************************
  * EOF
  **********************************************************************************************************************/
diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/connect_gpio.c b/Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/connect_gpio.c
index a61d7d035..4e74fb5cb 100755
--- a/Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/connect_gpio.c
+++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/gpio/connect_gpio.c
@@ -215,6 +215,20 @@ struct PinIrqHdr pin_irq_hdr_tab[] =
     {-1, 0, NONE, NONE},
 };
 
+#define MUX_BASE            0x401f8014
+#define CONFIG_BASE         0x401f8204
+
+#define GPIO5_MUX_BASE      0x400A8000
+#define GPIO5_CONFIG_BASE   0x400A8018
+
+const uint8_t reg_offset[] =
+{
+    42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73,
+    74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,103,104,105,
+   112,113,114,115,116,117,118,119,120,121,122,123,106,107,108,109,110,111, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, -1, -1, -1, -1,
+     0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+};
+
 static int GetPin(struct PinIndex *pin_index, uint8_t pin)
 {
     pin_index->index = pin >> 5;//0:GPIO1 1:GPIO2 2:GPIO3 3:GPIO4 4:GPIO5 
@@ -229,39 +243,52 @@ static int GetPin(struct PinIndex *pin_index, uint8_t pin)
     return 0;
 }
 
-static int32 GpioConfigMode(int mode, struct PinIndex *index)
+static int32 GpioConfigMode(int mode, struct PinIndex *pin_index, int32 pin)
 {
     gpio_pin_config_t gpio_config;
-    NULL_PARAM_CHECK(index);
+    uint32_t config_value = 0;
+    NULL_PARAM_CHECK(pin_index);
 
     gpio_config.outputLogic = 0;
+    gpio_config.interruptMode = kGPIO_NoIntmode;
 
     switch (mode)
     {
         case GPIO_CFG_OUTPUT:
             gpio_config.direction = kGPIO_DigitalOutput;
-            gpio_config.interruptMode = kGPIO_NoIntmode;
+            config_value = 0x0030U;    /* Drive Strength R0/6 */
             break;
         case GPIO_CFG_INPUT:
             gpio_config.direction = kGPIO_DigitalInput;
-            gpio_config.interruptMode = kGPIO_NoIntmode;
+            config_value = 0x0830U;    /* Open Drain Enable */
             break;
         case GPIO_CFG_INPUT_PULLUP:
             gpio_config.direction = kGPIO_DigitalInput;
-            gpio_config.interruptMode = kGPIO_NoIntmode;
+            config_value = 0xB030U;    /* 100K Ohm Pull Up */
             break;
         case GPIO_CFG_INPUT_PULLDOWN:
             gpio_config.direction = kGPIO_DigitalInput;
-            gpio_config.interruptMode = kGPIO_NoIntmode;
+            config_value = 0x3030U;    /* 100K Ohm Pull Down */
             break;
         case GPIO_CFG_OUTPUT_OD:
             gpio_config.direction = kGPIO_DigitalOutput;
-            gpio_config.interruptMode = kGPIO_NoIntmode;
+            config_value = 0x0830U;    /* Open Drain Enable */
             break;
         default:
             break;
     }
-    GPIO_PinInit(index->gpio, index->pin, &gpio_config);
+
+    if (pin_mask[pin_index->index].gpio != GPIO5) {
+        CLOCK_EnableClock(kCLOCK_Iomuxc);
+        IOMUXC_SetPinMux(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, 1);
+        IOMUXC_SetPinConfig(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, config_value);
+    } else {
+        CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
+        IOMUXC_SetPinMux(GPIO5_MUX_BASE + pin_index->pin * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_index->pin * 4, 1);
+        IOMUXC_SetPinConfig(GPIO5_MUX_BASE + pin_index->pin * 4, 0x5U, 0, 0, GPIO5_CONFIG_BASE + pin_index->pin * 4, config_value);
+    }
+
+    GPIO_PinInit(pin_index->gpio, pin_index->pin, &gpio_config);
     return EOK;
 }
 
@@ -385,6 +412,7 @@ static uint32 Imxrt1052PinConfigure(struct PinParam *param)
 
     struct PinIndex pin_index;
 
+    KPrintf("Imxrt1052PinConfigure\n");
     if (GetPin(&pin_index, param->pin) < 0) {
         return ERROR;
     }
@@ -392,7 +420,8 @@ static uint32 Imxrt1052PinConfigure(struct PinParam *param)
     switch(param->cmd)
     {
         case GPIO_CONFIG_MODE:
-            GpioConfigMode(param->mode, &pin_index);
+            KPrintf("GpioConfigMode %u\n", param->pin);
+            GpioConfigMode(param->mode, &pin_index, param->pin);
             break;
         case GPIO_IRQ_REGISTER:
             ret = GpioIrqRegister(param->pin, param->irq_set.irq_mode, param->irq_set.hdr, param->irq_set.args);
@@ -705,21 +734,6 @@ void GpioLedTest(void)
         KPrintf("initialize %s failed!\n", PIN_BUS_NAME);
         return;
     }
-
-    IOMUXC_SetPinMux(
-        IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,        /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
-        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
-                                    /* Software Input On Field: Input Path is determined by functionality */
-    IOMUXC_SetPinConfig(
-        IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,        /* GPIO_AD_B0_09 PAD functional properties : */
-        0x10B0u);                               /* Slew Rate Field: Slow Slew Rate
-                                                    Drive Strength Field: R0/6
-                                                    Speed Field: medium(100MHz)
-                                                    Open Drain Enable Field: Open Drain Disabled
-                                                    Pull / Keep Enable Field: Pull/Keeper Enabled
-                                                    Pull / Keep Select Field: Keeper
-                                                    Pull Up / Down Config. Field: 100K Ohm Pull Down
-                                                    Hyst. Enable Field: Hysteresis Disabled */
     
     struct PinParam led_gpio_param;
     struct PinStat led_gpio_stat;
@@ -762,4 +776,3 @@ void GpioLedTest(void)
 SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
                                                 GpioLedTest, GpioLedTest, GpioLedTest GPIO1 IO09 LED);
 #endif
-
diff --git a/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_ch438.h b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_ch438.h
new file mode 100755
index 000000000..2a4f2da60
--- /dev/null
+++ b/Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_ch438.h
@@ -0,0 +1,277 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_ch438.h
+* @brief define imxrt1052-board ch438 function and struct
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-03-15
+*/
+
+#ifndef CONNECT_CH438_H
+#define CONNECT_CH438_H
+
+#include <board.h>
+#include <device.h>
+#include <connect_gpio.h>
+
+#define CH438_BUFFSIZE 255
+
+/******************************************************************************************/
+
+/* chip definition */
+/* CH438serial port0 register address */
+
+#define REG_RBR0_ADDR        0x00      /* serial port0receive buffer register address */
+#define REG_THR0_ADDR        0x00      /* serial port0send hold register address */
+#define REG_IER0_ADDR        0x01      /* serial port0interrupt enable register address */
+#define REG_IIR0_ADDR        0x02      /* serial port0interrupt identifies register address */
+#define REG_FCR0_ADDR        0x02      /* serial port0FIFO controls register address */
+#define REG_LCR0_ADDR        0x03      /* serial port0circuit control register address */
+#define REG_MCR0_ADDR        0x04      /* serial port0MODEM controls register address */
+#define REG_LSR0_ADDR        0x05      /* serial port0line status register address */
+#define REG_MSR0_ADDR        0x06      /* serial port0address of MODEM status register */
+#define REG_SCR0_ADDR        0x07      /* serial port0the user can define the register address */
+#define REG_DLL0_ADDR        0x00      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM0_ADDR        0x01      /* Baud rate divisor latch high 8-bit byte address */
+
+/* CH438serial port1 register address */
+
+#define REG_RBR1_ADDR        0x10      /* serial port1receive buffer register address */
+#define REG_THR1_ADDR        0x10      /* serial port1send hold register address */
+#define REG_IER1_ADDR        0x11      /* serial port1interrupt enable register address */
+#define REG_IIR1_ADDR        0x12      /* serial port1interrupt identifies register address */
+#define REG_FCR1_ADDR        0x12      /* serial port1FIFO controls register address */
+#define REG_LCR1_ADDR        0x13      /* serial port1circuit control register address */
+#define REG_MCR1_ADDR        0x14      /* serial port1MODEM controls register address */
+#define REG_LSR1_ADDR        0x15      /* serial port1line status register address */
+#define REG_MSR1_ADDR        0x16      /* serial port1address of MODEM status register */
+#define REG_SCR1_ADDR        0x17      /* serial port1the user can define the register address */
+#define REG_DLL1_ADDR        0x10      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM1_ADDR        0x11      /* Baud rate divisor latch high 8-bit byte address */
+
+
+/* CH438serial port2 register address */
+
+#define REG_RBR2_ADDR        0x20      /* serial port2receive buffer register address */
+#define REG_THR2_ADDR        0x20      /* serial port2send hold register address */
+#define REG_IER2_ADDR        0x21      /* serial port2interrupt enable register address */
+#define REG_IIR2_ADDR        0x22      /* serial port2interrupt identifies register address */
+#define REG_FCR2_ADDR        0x22      /* serial port2FIFO controls register address */
+#define REG_LCR2_ADDR        0x23      /* serial port2circuit control register address */
+#define REG_MCR2_ADDR        0x24      /* serial port2MODEM controls register address */
+#define REG_LSR2_ADDR        0x25      /* serial port2line status register address */
+#define REG_MSR2_ADDR        0x26      /* serial port2address of MODEM status register */
+#define REG_SCR2_ADDR        0x27      /* serial port2the user can define the register address */
+#define REG_DLL2_ADDR        0x20      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM2_ADDR        0x21      /* Baud rate divisor latch high 8-bit byte address */
+
+
+
+/* CH438serial port3 register address */
+
+#define REG_RBR3_ADDR        0x30      /* serial port3receive buffer register address */
+#define REG_THR3_ADDR        0x30      /* serial port3send hold register address */
+#define REG_IER3_ADDR        0x31      /* serial port3interrupt enable register address */
+#define REG_IIR3_ADDR        0x32      /* serial port3interrupt identifies register address */
+#define REG_FCR3_ADDR        0x32      /* serial port3FIFO controls register address */
+#define REG_LCR3_ADDR        0x33      /* serial port3circuit control register address */
+#define REG_MCR3_ADDR        0x34      /* serial port3MODEM controls register address */
+#define REG_LSR3_ADDR        0x35      /* serial port3line status register address */
+#define REG_MSR3_ADDR        0x36      /* serial port3address of MODEM status register */
+#define REG_SCR3_ADDR        0x37      /* serial port3the user can define the register address */
+#define REG_DLL3_ADDR        0x30      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM3_ADDR        0x31      /* Baud rate divisor latch high 8-bit byte address */
+
+
+/* CH438serial port4 register address */
+
+#define REG_RBR4_ADDR        0x08      /* serial port4receive buffer register address */
+#define REG_THR4_ADDR        0x08      /* serial port4send hold register address */
+#define REG_IER4_ADDR        0x09      /* serial port4interrupt enable register address */
+#define REG_IIR4_ADDR        0x0A      /* serial port4interrupt identifies register address */
+#define REG_FCR4_ADDR        0x0A      /* serial port4FIFO controls register address */
+#define REG_LCR4_ADDR        0x0B      /* serial port4circuit control register address */
+#define REG_MCR4_ADDR        0x0C      /* serial port4MODEM controls register address */
+#define REG_LSR4_ADDR        0x0D      /* serial port4line status register address */
+#define REG_MSR4_ADDR        0x0E      /* serial port4address of MODEM status register */
+#define REG_SCR4_ADDR        0x0F      /* serial port4the user can define the register address */
+#define REG_DLL4_ADDR        0x08      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM4_ADDR        0x09      /* Baud rate divisor latch high 8-bit byte address */
+
+
+
+/* CH438serial port5 register address */
+
+#define REG_RBR5_ADDR        0x18      /* serial port5receive buffer register address */
+#define REG_THR5_ADDR        0x18      /* serial port5send hold register address */
+#define REG_IER5_ADDR        0x19      /* serial port5interrupt enable register address */
+#define REG_IIR5_ADDR        0x1A      /* serial port5interrupt identifies register address */
+#define REG_FCR5_ADDR        0x1A      /* serial port5FIFO controls register address */
+#define REG_LCR5_ADDR        0x1B      /* serial port5circuit control register address */
+#define REG_MCR5_ADDR        0x1C      /* serial port5MODEM controls register address */
+#define REG_LSR5_ADDR        0x1D      /* serial port5line status register address */
+#define REG_MSR5_ADDR        0x1E      /* serial port5address of MODEM status register */
+#define REG_SCR5_ADDR        0x1F      /* serial port5the user can define the register address */
+#define REG_DLL5_ADDR        0x18      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM5_ADDR        0x19      /* Baud rate divisor latch high 8-bit byte address */
+
+
+/* CH438serial port6 register address */
+
+#define REG_RBR6_ADDR        0x28      /* serial port6receive buffer register address */
+#define REG_THR6_ADDR        0x28      /* serial port6send hold register address */
+#define REG_IER6_ADDR        0x29      /* serial port6interrupt enable register address */
+#define REG_IIR6_ADDR        0x2A      /* serial port6interrupt identifies register address */
+#define REG_FCR6_ADDR        0x2A      /* serial port6FIFO controls register address */
+#define REG_LCR6_ADDR        0x2B      /* serial port6circuit control register address */
+#define REG_MCR6_ADDR        0x2C      /* serial port6MODEM controls register address */
+#define REG_LSR6_ADDR        0x2D      /* serial port6line status register address */
+#define REG_MSR6_ADDR        0x2E      /* serial port6address of MODEM status register */
+#define REG_SCR6_ADDR        0x2F      /* serial port6the user can define the register address */
+#define REG_DLL6_ADDR        0x28      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM6_ADDR        0x29      /* Baud rate divisor latch high 8-bit byte address */
+
+
+/* CH438serial port7 register address */
+
+#define REG_RBR7_ADDR        0x38      /* serial port7receive buffer register address */
+#define REG_THR7_ADDR        0x38      /* serial port7send hold register address */
+#define REG_IER7_ADDR        0x39      /* serial port7interrupt enable register address */
+#define REG_IIR7_ADDR        0x3A      /* serial port7interrupt identifies register address */
+#define REG_FCR7_ADDR        0x3A      /* serial port7FIFO controls register address */
+#define REG_LCR7_ADDR        0x3B      /* serial port7circuit control register address */
+#define REG_MCR7_ADDR        0x3C      /* serial port7MODEM controls register address */
+#define REG_LSR7_ADDR        0x3D      /* serial port7line status register address */
+#define REG_MSR7_ADDR        0x3E      /* serial port7address of MODEM status register */
+#define REG_SCR7_ADDR        0x3F      /* serial port7the user can define the register address */
+#define REG_DLL7_ADDR        0x38      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM7_ADDR        0x39      /* Baud rate divisor latch high 8-bit byte address */
+
+
+#define REG_SSR_ADDR         0x4F       /* pecial status register address */
+
+
+/* IER register bit */
+
+#define BIT_IER_RESET        0x80      /* The bit is 1 soft reset serial port */
+#define BIT_IER_LOWPOWER     0x40      /* The bit is 1 close serial port internal reference clock */
+#define BIT_IER_SLP          0x20      /* serial port0 is SLP, 1 close clock vibrator  */
+#define BIT_IER1_CK2X        0x20      /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */
+#define BIT_IER_IEMODEM      0x08      /* The bit is 1 allows MODEM input status to interrupt */
+#define BIT_IER_IELINES      0x04      /* The bit is 1 allow receiving line status to be interrupted */
+#define BIT_IER_IETHRE       0x02      /* The bit is 1 allows the send hold register to break in mid-air */
+#define BIT_IER_IERECV       0x01      /* The bit is 1 allows receiving data interrupts */
+
+/* IIR register bit */
+
+#define BIT_IIR_FIFOENS1     0x80
+#define BIT_IIR_FIFOENS0     0x40      /* The two is 1 said use FIFO */
+
+/* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted,
+1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */
+#define BIT_IIR_IID3         0x08
+#define BIT_IIR_IID2         0x04
+#define BIT_IIR_IID1         0x02
+#define BIT_IIR_NOINT        0x01
+
+/* FCR register bit */
+
+/* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */
+#define BIT_FCR_RECVTG1      0x80      /* Set the trigger point for FIFO interruption and automatic hardware flow control */
+#define BIT_FCR_RECVTG0      0x40      /* Set the trigger point for FIFO interruption and automatic hardware flow control */
+
+#define BIT_FCR_TFIFORST     0x04      /* The bit is 1 empty the data sent in FIFO */
+#define BIT_FCR_RFIFORST     0x02      /* The bit is 1 empty the data sent in FIFO */
+#define BIT_FCR_FIFOEN       0x01      /* The bit is 1 use FIFO, 0 disable FIFO */
+
+/* LCR register bit */
+
+#define BIT_LCR_DLAB         0x80      /* To access DLL, DLM, 0 to access RBR/THR/IER */
+#define BIT_LCR_BREAKEN      0x40      /* 1 forces a BREAK line interval*/
+
+/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */
+#define BIT_LCR_PARMODE1     0x20      /* Sets the parity bit format */
+#define BIT_LCR_PARMODE0     0x10      /* Sets the parity bit format */
+
+#define BIT_LCR_PAREN        0x08      /* A value of 1 allows you to generate and receive parity bits when sending */
+#define BIT_LCR_STOPBIT      0x04      /* If is 1, then two stop bits, is 0, a stop bit */
+
+/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */
+#define BIT_LCR_WORDSZ1      0x02      /* Set the word length length */
+#define BIT_LCR_WORDSZ0      0x01
+
+/* MCR register bit */
+
+#define BIT_MCR_AFE          0x20      /* For 1 allows automatic flow control of CTS and RTS hardware */
+#define BIT_MCR_LOOP         0x10      /* Is the test mode of 1 enabling internal loop */
+#define BIT_MCR_OUT2         0x08      /* 1 Allows an interrupt request for the serial port output  */
+#define BIT_MCR_OUT1         0x04      /* The MODEM control bit defined for the user */
+#define BIT_MCR_RTS          0x02      /* The bit is 1 RTS pin  output  effective  */
+#define BIT_MCR_DTR          0x01      /* The bit is 1 DTR pin  output  effective  */
+
+/* LSR register bit */
+
+#define BIT_LSR_RFIFOERR     0x80      /* 1 said There is at least one error in receiving FIFO */
+#define BIT_LSR_TEMT         0x40      /* 1 said THR and TSR are empty */
+#define BIT_LSR_THRE         0x20      /* 1 said THR is empty*/
+#define BIT_LSR_BREAKINT     0x10      /* The bit is 1 said the BREAK line interval was detected*/
+#define BIT_LSR_FRAMEERR     0x08      /* The bit is 1 said error reading data frame */
+#define BIT_LSR_PARERR       0x04      /* The bit is 1 said parity error */
+#define BIT_LSR_OVERR        0x02      /*  1 said receive FIFO buffer overflow */
+#define BIT_LSR_DATARDY      0x01      /* The bit is 1 said receive data received in FIFO */
+
+/* MSR register bit */
+
+#define BIT_MSR_DCD          0x80      /* The bit is 1 said DCD pin  effective  */
+#define BIT_MSR_RI           0x40      /* The bit is 1 said RI pin  effective  */
+#define BIT_MSR_DSR          0x20      /* The bit is 1 said DSR pin  effective  */
+#define BIT_MSR_CTS          0x10      /* The bit is 1 said CTS pin  effective  */
+#define BIT_MSR_DDCD         0x08      /* The bit is 1 said DCD pin The input state has changed */
+#define BIT_MSR_TERI         0x04      /* The bit is 1 said RI pin The input state has changed */
+#define BIT_MSR_DDSR         0x02      /* The bit is 1 said DSR pin The input state has changed */
+#define BIT_MSR_DCTS         0x01      /* The bit is 1 said CTS pin The input state has changed */
+
+/* Interrupt status code */
+
+#define INT_NOINT            0x01      /* There is no interruption */
+#define INT_THR_EMPTY        0x02      /* THR empty interruption */
+#define INT_RCV_OVERTIME     0x0C      /* Receive timeout interrupt */
+#define INT_RCV_SUCCESS      0x04      /* Interrupts are available to receive data */
+#define INT_RCV_LINES        0x06      /* Receiving line status interrupted */
+#define INT_MODEM_CHANGE     0x00      /* MODEM input changes interrupt */
+
+#define CH438_IIR_FIFOS_ENABLED  0xC0  /* use FIFO */
+
+#define Fpclk           1843200        /* Define the internal clock frequency  */
+
+#define CH438_D0_PIN	       IMXRT_GET_PIN(1, 25)
+#define CH438_D1_PIN	       IMXRT_GET_PIN(1, 24)
+#define CH438_D2_PIN	       IMXRT_GET_PIN(1, 20)
+#define CH438_D3_PIN	       IMXRT_GET_PIN(1, 21)
+#define CH438_D4_PIN	       IMXRT_GET_PIN(1, 31)
+#define CH438_D5_PIN	       IMXRT_GET_PIN(1, 28)
+#define CH438_D6_PIN	       IMXRT_GET_PIN(1, 30)
+#define CH438_D7_PIN	       IMXRT_GET_PIN(1, 29)
+#define CH438_NWR_PIN	       IMXRT_GET_PIN(3, 4)
+#define CH438_NRD_PIN	       IMXRT_GET_PIN(3, 5)
+#define CH438_ALE_PIN	       IMXRT_GET_PIN(3, 2)
+#define CH438_INT_PIN	       IMXRT_GET_PIN(3, 3)
+// #define	DIR_485CH1_PIN
+// #define	DIR_485CH2_PIN     
+
+void CH438RegTest(unsigned char num);
+
+int Imxrt1052HwCh438Init(void);
+
+#endif
diff --git a/Ubiquitous/XiZi/board/xidatong/xip/Makefile b/Ubiquitous/XiZi/board/xidatong/xip/Makefile
new file mode 100755
index 000000000..e27f9550a
--- /dev/null
+++ b/Ubiquitous/XiZi/board/xidatong/xip/Makefile
@@ -0,0 +1,3 @@
+SRC_FILES := fsl_flexspi_nor_boot.c fsl_flexspi_nor_flash.c
+
+include $(KERNEL_ROOT)/compiler.mk
diff --git a/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.c b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.c
new file mode 100644
index 000000000..052813ed6
--- /dev/null
+++ b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.c
@@ -0,0 +1,1219 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+* @file fsl_flexspi_nor_boot.c
+* @brief support to register flexspi image vector table
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-03-22
+*/
+
+#include "fsl_flexspi_nor_boot.h"
+
+#if defined(__CC_ARM) || defined(__GNUC__)
+    __attribute__((section(".boot_hdr.ivt")))
+#elif defined(__ICCARM__)
+#pragma location=".boot_hdr.ivt"
+#endif
+
+const ivt image_vector_table = {
+  IVT_HEADER,                         /* IVT Header */
+  0x60002000,                         /* Image  Entry Function */
+  IVT_RSVD,                           /* Reserved = 0 */
+  (uint32_t)DCD_ADDRESS,              /* Address where DCD information is stored */
+  (uint32_t)BOOT_DATA_ADDRESS,        /* Address where BOOT Data Structure is stored */
+  (uint32_t)&image_vector_table,      /* Pointer to IVT Self (absolute address */
+  (uint32_t)CSF_ADDRESS,              /* Address where CSF file is stored */
+  IVT_RSVD                            /* Reserved = 0 */
+};
+
+#if defined(__CC_ARM) || defined(__GNUC__)
+    __attribute__((section(".boot_hdr.boot_data")))
+#elif defined(__ICCARM__)
+#pragma location=".boot_hdr.boot_data"
+#endif
+
+const BOOT_DATA_T boot_data = {
+  FLASH_BASE,                 /* boot start location */
+  (FLASH_END-FLASH_BASE),     /* size */
+  PLUGIN_FLAG,                /* Plugin flag*/
+  0xFFFFFFFF  				  /* empty - extra data word */
+};
+
+#if defined(__CC_ARM) || defined(__GNUC__)
+    __attribute__((section(".boot_hdr.dcd_data")))
+#elif defined(__ICCARM__)
+#pragma location=".boot_hdr.dcd_data"
+#endif
+//const uint8_t dcd_sdram[1044] = {
+///*0000*/ 0xD2, 0x04, 0x14, 0x41, 0xCC, 0x02, 0xF4, 0x04, 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, 
+///*0010*/ 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, 
+///*0020*/ 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, 
+///*0030*/ 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 
+///*0040*/ 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00, 
+///*0050*/ 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x09, 0x83, 0x40, 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 
+///*0060*/ 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, 
+///*0070*/ 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, 
+///*0080*/ 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, 
+///*0090*/ 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, 
+///*00a0*/ 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, 
+///*00b0*/ 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, 
+///*00c0*/ 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, 
+///*00d0*/ 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, 
+///*00e0*/ 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, 
+///*00f0*/ 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, 
+///*0100*/ 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, 
+///*0110*/ 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, 
+///*0120*/ 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, 
+///*0130*/ 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, 
+///*0140*/ 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, 
+///*0150*/ 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, 
+///*0160*/ 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, 
+///*0170*/ 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, 
+///*0180*/ 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, 
+///*0190*/ 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, 0x40, 0x1F, 0x80, 0xB4, 0x00, 0x00, 0x00, 0x00, 
+///*01a0*/ 0x40, 0x1F, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x82, 0x04, 0x00, 0x00, 0x00, 0xF1, 
+///*01b0*/ 0x40, 0x1F, 0x82, 0x08, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x00, 0x00, 0xF1, 
+///*01c0*/ 0x40, 0x1F, 0x82, 0x10, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x14, 0x00, 0x00, 0x00, 0xF1, 
+///*01d0*/ 0x40, 0x1F, 0x82, 0x18, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x00, 0x00, 0xF1, 
+///*01e0*/ 0x40, 0x1F, 0x82, 0x20, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x24, 0x00, 0x00, 0x00, 0xF1, 
+///*01f0*/ 0x40, 0x1F, 0x82, 0x28, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x00, 0x00, 0xF1, 
+///*0200*/ 0x40, 0x1F, 0x82, 0x30, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x34, 0x00, 0x00, 0x00, 0xF1, 
+///*0210*/ 0x40, 0x1F, 0x82, 0x38, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x00, 0x00, 0xF1, 
+///*0220*/ 0x40, 0x1F, 0x82, 0x40, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x44, 0x00, 0x00, 0x00, 0xF1, 
+///*0230*/ 0x40, 0x1F, 0x82, 0x48, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x00, 0x00, 0xF1, 
+///*0240*/ 0x40, 0x1F, 0x82, 0x50, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x54, 0x00, 0x00, 0x00, 0xF1, 
+///*0250*/ 0x40, 0x1F, 0x82, 0x58, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x00, 0x00, 0xF1, 
+///*0260*/ 0x40, 0x1F, 0x82, 0x60, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x64, 0x00, 0x00, 0x00, 0xF1, 
+///*0270*/ 0x40, 0x1F, 0x82, 0x68, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x00, 0x00, 0xF1, 
+///*0280*/ 0x40, 0x1F, 0x82, 0x70, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x74, 0x00, 0x00, 0x00, 0xF1, 
+///*0290*/ 0x40, 0x1F, 0x82, 0x78, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x00, 0x00, 0xF1, 
+///*02a0*/ 0x40, 0x1F, 0x82, 0x80, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x84, 0x00, 0x00, 0x00, 0xF1, 
+///*02b0*/ 0x40, 0x1F, 0x82, 0x88, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x00, 0x00, 0xF1, 
+///*02c0*/ 0x40, 0x1F, 0x82, 0x90, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x94, 0x00, 0x00, 0x00, 0xF1, 
+///*02d0*/ 0x40, 0x1F, 0x82, 0x98, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x00, 0x00, 0xF1, 
+///*02e0*/ 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x00, 0x00, 0xF1, 0x40, 0x1F, 0x82, 0xA4, 0x00, 0x00, 0x00, 0xF1, 
+///*02f0*/ 0x40, 0x1F, 0x82, 0xA8, 0x00, 0x00, 0x00, 0xF1, 0xCC, 0x00, 0x0C, 0x14, 0x40, 0x2F, 0x00, 0x00, 
+///*0300*/ 0x00, 0x00, 0x00, 0x02, 0xCC, 0x00, 0x9C, 0x04, 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, 
+///*0310*/ 0x40, 0x2F, 0x00, 0x08, 0x00, 0x03, 0x05, 0x24, 0x40, 0x2F, 0x00, 0x0C, 0x06, 0x03, 0x05, 0x24, 
+///*0320*/ 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x14, 0x90, 0x00, 0x00, 0x21, 
+///*0330*/ 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0B, 0x27, 
+///*0340*/ 0x40, 0x2F, 0x00, 0x44, 0x00, 0x10, 0x01, 0x00, 0x40, 0x2F, 0x00, 0x48, 0x00, 0x02, 0x02, 0x01, 
+///*0350*/ 0x40, 0x2F, 0x00, 0x4C, 0x08, 0x19, 0x3D, 0x0E, 0x40, 0x2F, 0x00, 0x74, 0x00, 0x65, 0x29, 0x22, 
+///*0360*/ 0x40, 0x2F, 0x00, 0x78, 0x00, 0x01, 0x09, 0x20, 0x40, 0x2F, 0x00, 0x7C, 0x50, 0x21, 0x0A, 0x08, 
+///*0370*/ 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, 
+///*0380*/ 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, 
+///*0390*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, 
+///*03a0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04, 
+///*03b0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, 
+///*03c0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04, 
+///*03d0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, 
+///*03e0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x1C, 0x04, 
+///*03f0*/ 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x22, 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 
+///*0400*/ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 
+///*0410*/ 0x00, 0x00, 0x00, 0x01, 
+//};
+
+
+
+const uint8_t dcd_sdram[1072] = {
+	/*0000*/ 0xD2,
+    0x04,
+    0x30,
+    0x41,
+    0xCC,
+    0x03,
+    0xAC,
+    0x04,
+    0x40,
+    0x0F,
+    0xC0,
+    0x68,
+    0xFF,
+    0xFF,
+    0xFF,
+    0xFF,
+    /*0010*/ 0x40,
+    0x0F,
+    0xC0,
+    0x6C,
+    0xFF,
+    0xFF,
+    0xFF,
+    0xFF,
+    0x40,
+    0x0F,
+    0xC0,
+    0x70,
+    0xFF,
+    0xFF,
+    0xFF,
+    0xFF,
+    /*0020*/ 0x40,
+    0x0F,
+    0xC0,
+    0x74,
+    0xFF,
+    0xFF,
+    0xFF,
+    0xFF,
+    0x40,
+    0x0F,
+    0xC0,
+    0x78,
+    0xFF,
+    0xFF,
+    0xFF,
+    0xFF,
+    /*0030*/ 0x40,
+    0x0F,
+    0xC0,
+    0x7C,
+    0xFF,
+    0xFF,
+    0xFF,
+    0xFF,
+    0x40,
+    0x0F,
+    0xC0,
+    0x80,
+    0xFF,
+    0xFF,
+    0xFF,
+    0xFF,
+    /*0040*/ 0x40,
+    0x0D,
+    0x80,
+    0x30,
+    0x00,
+    0x00,
+    0x20,
+    0x01,
+    0x40,
+    0x0D,
+    0x81,
+    0x00,
+    0x00,
+    0x1D,
+    0x00,
+    0x00,
+    /*0050*/ 0x40,
+    0x0F,
+    0xC0,
+    0x14,
+    0x00,
+    0x01,
+    0x0D,
+    0x40,
+    0x40,
+    0x1F,
+    0x80,
+    0x14,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0060*/ 0x40,
+    0x1F,
+    0x80,
+    0x18,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x1C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0070*/ 0x40,
+    0x1F,
+    0x80,
+    0x20,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x24,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0080*/ 0x40,
+    0x1F,
+    0x80,
+    0x28,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x2C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0090*/ 0x40,
+    0x1F,
+    0x80,
+    0x30,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x34,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*00a0*/ 0x40,
+    0x1F,
+    0x80,
+    0x38,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x3C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*00b0*/ 0x40,
+    0x1F,
+    0x80,
+    0x40,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x44,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*00c0*/ 0x40,
+    0x1F,
+    0x80,
+    0x48,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x4C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*00d0*/ 0x40,
+    0x1F,
+    0x80,
+    0x50,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x54,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*00e0*/ 0x40,
+    0x1F,
+    0x80,
+    0x58,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x5C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*00f0*/ 0x40,
+    0x1F,
+    0x80,
+    0x60,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x64,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0100*/ 0x40,
+    0x1F,
+    0x80,
+    0x68,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x6C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0110*/ 0x40,
+    0x1F,
+    0x80,
+    0x70,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x74,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0120*/ 0x40,
+    0x1F,
+    0x80,
+    0x78,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x7C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0130*/ 0x40,
+    0x1F,
+    0x80,
+    0x80,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x84,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0140*/ 0x40,
+    0x1F,
+    0x80,
+    0x88,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x8C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0150*/ 0x40,
+    0x1F,
+    0x80,
+    0x90,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x94,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0160*/ 0x40,
+    0x1F,
+    0x80,
+    0x98,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0x9C,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0170*/ 0x40,
+    0x1F,
+    0x80,
+    0xA0,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0xA4,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0180*/ 0x40,
+    0x1F,
+    0x80,
+    0xA8,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x80,
+    0xAC,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*0190*/ 0x40,
+    0x1F,
+    0x80,
+    0xB0,
+    0x00,
+    0x00,
+    0x00,
+    0x10,
+    0x40,
+    0x1F,
+    0x80,
+    0xB4,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*01a0*/ 0x40,
+    0x1F,
+    0x80,
+    0xB8,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x1F,
+    0x82,
+    0x04,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*01b0*/ 0x40,
+    0x1F,
+    0x82,
+    0x08,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x0C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*01c0*/ 0x40,
+    0x1F,
+    0x82,
+    0x10,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x14,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*01d0*/ 0x40,
+    0x1F,
+    0x82,
+    0x18,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x1C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*01e0*/ 0x40,
+    0x1F,
+    0x82,
+    0x20,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x24,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*01f0*/ 0x40,
+    0x1F,
+    0x82,
+    0x28,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x2C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0200*/ 0x40,
+    0x1F,
+    0x82,
+    0x30,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x34,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0210*/ 0x40,
+    0x1F,
+    0x82,
+    0x38,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x3C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0220*/ 0x40,
+    0x1F,
+    0x82,
+    0x40,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x44,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0230*/ 0x40,
+    0x1F,
+    0x82,
+    0x48,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x4C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0240*/ 0x40,
+    0x1F,
+    0x82,
+    0x50,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x54,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0250*/ 0x40,
+    0x1F,
+    0x82,
+    0x58,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x5C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0260*/ 0x40,
+    0x1F,
+    0x82,
+    0x60,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x64,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0270*/ 0x40,
+    0x1F,
+    0x82,
+    0x68,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x6C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0280*/ 0x40,
+    0x1F,
+    0x82,
+    0x70,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x74,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*0290*/ 0x40,
+    0x1F,
+    0x82,
+    0x78,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x7C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*02a0*/ 0x40,
+    0x1F,
+    0x82,
+    0x80,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x84,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*02b0*/ 0x40,
+    0x1F,
+    0x82,
+    0x88,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x8C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*02c0*/ 0x40,
+    0x1F,
+    0x82,
+    0x90,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x94,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*02d0*/ 0x40,
+    0x1F,
+    0x82,
+    0x98,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0x9C,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*02e0*/ 0x40,
+    0x1F,
+    0x82,
+    0xA0,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x1F,
+    0x82,
+    0xA4,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    /*02f0*/ 0x40,
+    0x1F,
+    0x82,
+    0xA8,
+    0x00,
+    0x01,
+    0x10,
+    0xF9,
+    0x40,
+    0x2F,
+    0x00,
+    0x00,
+    0x10,
+    0x00,
+    0x00,
+    0x04,
+    /*0300*/ 0x40,
+    0x2F,
+    0x00,
+    0x08,
+    0x00,
+    0x03,
+    0x05,
+    0x24,
+    0x40,
+    0x2F,
+    0x00,
+    0x0C,
+    0x06,
+    0x03,
+    0x05,
+    0x24,
+    /*0310*/ 0x40,
+    0x2F,
+    0x00,
+    0x10,
+    0x80,
+    0x00,
+    0x00,
+    0x1B,
+    0x40,
+    0x2F,
+    0x00,
+    0x14,
+    0x82,
+    0x00,
+    0x00,
+    0x1B,
+    /*0320*/ 0x40,
+    0x2F,
+    0x00,
+    0x18,
+    0x84,
+    0x00,
+    0x00,
+    0x1B,
+    0x40,
+    0x2F,
+    0x00,
+    0x1C,
+    0x86,
+    0x00,
+    0x00,
+    0x1B,
+    /*0330*/ 0x40,
+    0x2F,
+    0x00,
+    0x20,
+    0x90,
+    0x00,
+    0x00,
+    0x21,
+    0x40,
+    0x2F,
+    0x00,
+    0x24,
+    0xA0,
+    0x00,
+    0x00,
+    0x19,
+    /*0340*/ 0x40,
+    0x2F,
+    0x00,
+    0x28,
+    0xA8,
+    0x00,
+    0x00,
+    0x17,
+    0x40,
+    0x2F,
+    0x00,
+    0x2C,
+    0xA9,
+    0x00,
+    0x00,
+    0x1B,
+    /*0350*/ 0x40,
+    0x2F,
+    0x00,
+    0x30,
+    0x00,
+    0x00,
+    0x00,
+    0x21,
+    0x40,
+    0x2F,
+    0x00,
+    0x04,
+    0x00,
+    0x00,
+    0x79,
+    0xA8,
+    /*0360*/ 0x40,
+    0x2F,
+    0x00,
+    0x40,
+    0x00,
+    0x00,
+    0x0F,
+    0x31,
+    0x40,
+    0x2F,
+    0x00,
+    0x44,
+    0x00,
+    0x65,
+    0x29,
+    0x22,
+    /*0370*/ 0x40,
+    0x2F,
+    0x00,
+    0x48,
+    0x00,
+    0x01,
+    0x09,
+    0x20,
+    0x40,
+    0x2F,
+    0x00,
+    0x4C,
+    0x50,
+    0x21,
+    0x0A,
+    0x08,
+    /*0380*/ 0x40,
+    0x2F,
+    0x00,
+    0x80,
+    0x00,
+    0x00,
+    0x00,
+    0x21,
+    0x40,
+    0x2F,
+    0x00,
+    0x84,
+    0x00,
+    0x88,
+    0x88,
+    0x88,
+    /*0390*/ 0x40,
+    0x2F,
+    0x00,
+    0x94,
+    0x00,
+    0x00,
+    0x00,
+    0x02,
+    0x40,
+    0x2F,
+    0x00,
+    0x98,
+    0x00,
+    0x00,
+    0x00,
+    0x00,
+    /*03a0*/ 0x40,
+    0x2F,
+    0x00,
+    0x90,
+    0x80,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x2F,
+    0x00,
+    0x9C,
+    0xA5,
+    0x5A,
+    0x00,
+    0x0F,
+    /*03b0*/ 0xCF,
+    0x00,
+    0x0C,
+    0x1C,
+    0x40,
+    0x2F,
+    0x00,
+    0x3C,
+    0x00,
+    0x00,
+    0x00,
+    0x01,
+    0xCC,
+    0x00,
+    0x14,
+    0x04,
+    /*03c0*/ 0x40,
+    0x2F,
+    0x00,
+    0x90,
+    0x80,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x2F,
+    0x00,
+    0x9C,
+    0xA5,
+    0x5A,
+    0x00,
+    0x0C,
+    /*03d0*/ 0xCF,
+    0x00,
+    0x0C,
+    0x1C,
+    0x40,
+    0x2F,
+    0x00,
+    0x3C,
+    0x00,
+    0x00,
+    0x00,
+    0x01,
+    0xCC,
+    0x00,
+    0x14,
+    0x04,
+    /*03e0*/ 0x40,
+    0x2F,
+    0x00,
+    0x90,
+    0x80,
+    0x00,
+    0x00,
+    0x00,
+    0x40,
+    0x2F,
+    0x00,
+    0x9C,
+    0xA5,
+    0x5A,
+    0x00,
+    0x0C,
+    /*03f0*/ 0xCF,
+    0x00,
+    0x0C,
+    0x1C,
+    0x40,
+    0x2F,
+    0x00,
+    0x3C,
+    0x00,
+    0x00,
+    0x00,
+    0x01,
+    0xCC,
+    0x00,
+    0x1C,
+    0x04,
+    /*0400*/ 0x40,
+    0x2F,
+    0x00,
+    0xA0,
+    0x00,
+    0x00,
+    0x00,
+    0x33,
+    0x40,
+    0x2F,
+    0x00,
+    0x90,
+    0x80,
+    0x00,
+    0x00,
+    0x00,
+    /*0410*/ 0x40,
+    0x2F,
+    0x00,
+    0x9C,
+    0xA5,
+    0x5A,
+    0x00,
+    0x0A,
+    0xCF,
+    0x00,
+    0x0C,
+    0x1C,
+    0x40,
+    0x2F,
+    0x00,
+    0x3C,
+    /*0420*/ 0x00,
+    0x00,
+    0x00,
+    0x01,
+    0xCC,
+    0x00,
+    0x0C,
+    0x04,
+    0x40,
+    0x2F,
+    0x00,
+    0x4C,
+    0x50,
+    0x07,
+    0x0A,
+    0x09,
+};
diff --git a/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.h b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.h
new file mode 100644
index 000000000..b6677b274
--- /dev/null
+++ b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_boot.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+* @file fsl_flexspi_nor_boot.h
+* @brief support to register flexspi image vector table
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-03-22
+*/
+
+#ifndef _QUADSPI_BOOT_H_
+#define _QUADSPI_BOOT_H_
+
+#include <stdint.h>
+
+/************************************* 
+ *  IVT Data 
+ *************************************/
+typedef struct _ivt_ {
+    /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields
+     *  (see @ref data)
+     */
+    uint32_t hdr;
+    /** Absolute address of the first instruction to execute from the
+     *  image
+     */
+    uint32_t entry;
+    /** Reserved in this version of HAB: should be NULL. */
+    uint32_t reserved1;
+    /** Absolute address of the image DCD: may be NULL. */
+    uint32_t dcd;
+    /** Absolute address of the Boot Data: may be NULL, but not interpreted
+     *  any further by HAB
+     */
+    uint32_t boot_data;
+    /** Absolute address of the IVT.*/
+    uint32_t self;
+    /** Absolute address of the image CSF.*/
+    uint32_t csf;
+    /** Reserved in this version of HAB: should be zero. */
+    uint32_t reserved2;
+} ivt;
+
+#define IVT_MAJOR_VERSION           0x4
+#define IVT_MAJOR_VERSION_SHIFT     0x4
+#define IVT_MAJOR_VERSION_MASK      0xF
+#define IVT_MINOR_VERSION           0x1
+#define IVT_MINOR_VERSION_SHIFT     0x0
+#define IVT_MINOR_VERSION_MASK      0xF
+
+#define IVT_VERSION(major, minor)   \
+  ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) |  \
+  (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT))
+
+#define IVT_TAG_HEADER        (0xD1)       /**< Image Vector Table */
+#define IVT_SIZE              0x2000
+#define IVT_PAR               IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION)
+
+#define IVT_HEADER          (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24))
+#define IVT_RSVD            (uint32_t)(0x00000000)
+
+
+/************************************* 
+ *  Boot Data 
+ *************************************/
+typedef struct _boot_data_ {
+  uint32_t start;           /* boot start location */
+  uint32_t size;            /* size */
+  uint32_t plugin;          /* plugin flag - 1 if downloaded application is plugin */
+  uint32_t placeholder;		/* placehoder to make even 0x10 size */
+}BOOT_DATA_T;
+
+
+/************************************* 
+ *  DCD Data 
+ *************************************/
+#define DCD_TAG_HEADER            (0xD2)
+#define DCD_TAG_HEADER_SHIFT      (24)
+#define DCD_VERSION               (0x40)
+#define DCD_ARRAY_SIZE             1
+
+#define FLASH_BASE            0x60000000
+#define FLASH_END             0x7F7FFFFF 
+#define SCLK 1
+
+#define DCD_ADDRESS           dcd_sdram
+#define BOOT_DATA_ADDRESS     &boot_data
+#define CSF_ADDRESS           0
+#define PLUGIN_FLAG           (uint32_t)0
+
+/* External Variables */
+//extern const uint8_t dcd_sdram[1044];
+extern const uint8_t dcd_sdram[1072];
+extern const BOOT_DATA_T boot_data;
+
+#endif
diff --git a/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.c b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.c
new file mode 100644
index 000000000..c5cc52dbc
--- /dev/null
+++ b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+* @file fsl_flexspi_nor_flash.c
+* @brief support to define flexspi flash config
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-03-22
+*/
+
+#include "fsl_flexspi_nor_flash.h"
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(__CC_ARM) || defined(__GNUC__)
+    __attribute__((section(".boot_hdr.conf")))
+#elif defined(__ICCARM__)
+#pragma location=".boot_hdr.conf"
+#endif
+
+const flexspi_nor_config_t Qspiflash_config =
+{
+    .memConfig =
+    {
+        .tag = FLEXSPI_CFG_BLK_TAG,
+        .version = FLEXSPI_CFG_BLK_VERSION,
+        .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally,
+        .csHoldTime = 3u,
+        .csSetupTime = 3u,
+        .deviceModeCfgEnable = true,
+        .deviceModeType = 1,//Quad Enable command
+        .deviceModeSeq.seqNum = 1,
+        .deviceModeSeq.seqId = 4,				
+        .deviceModeArg = 0x000200,//Set QE
+        .deviceType = kFlexSpiDeviceType_SerialNOR,
+        .sflashPadType = kSerialFlash_4Pads,
+        .serialClkFreq = kFlexSpiSerialClk_60MHz,//80MHz for Winbond, 100MHz for GD, 133MHz for ISSI
+        .sflashA1Size = 16u * 1024u * 1024u,//4MBytes
+        .dataValidTime = {16u, 16u},
+        .lookupTable =
+        {
+//         //Fast Read Sequence
+//         [0]  = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B, RADDR_SDR, FLEXSPI_1PAD, 0x18),
+//         [1]  = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 0x08, READ_SDR, FLEXSPI_1PAD, 0x08),
+//         [2]  = FLEXSPI_LUT_SEQ(JMP_ON_CS, 0, 0, 0, 0, 0),
+           //Quad Input/output read sequence
+           [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
+           [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
+           [2] = FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0),
+           //Read Status
+           [1*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
+           //Write Enable
+           [3*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, 0, 0),
+           //Write status
+           [4*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x2),
+	 },
+    },
+    .pageSize = 256u,
+    .sectorSize = 4u * 1024u,
+};
diff --git a/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.h b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.h
new file mode 100644
index 000000000..73d4547b7
--- /dev/null
+++ b/Ubiquitous/XiZi/board/xidatong/xip/fsl_flexspi_nor_flash.h
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this
+ * list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice,
+ * this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+* @file fsl_flexspi_nor_flash.h
+* @brief support to define flexspi flash config
+* @version 2.0 
+* @author AIIT XUOS Lab
+* @date 2022-03-22
+*/
+
+#ifndef __FLEXSPI_NOR_FLASH_H__
+#define __FLEXSPI_NOR_FLASH_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_common.h"
+
+/* FLEXSPI memory config block related defintions */
+#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
+#define FLEXSPI_CFG_BLK_SIZE (512)
+
+/* FLEXSPI Feature related definitions */
+#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
+
+/* Lookup table related defintions */
+#define CMD_INDEX_READ 0
+#define CMD_INDEX_READSTATUS 1
+#define CMD_INDEX_WRITEENABLE 2
+#define CMD_INDEX_WRITE 4
+
+#define CMD_LUT_SEQ_IDX_READ 0
+#define CMD_LUT_SEQ_IDX_READSTATUS 1
+#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
+#define CMD_LUT_SEQ_IDX_WRITE 9
+
+#define CMD_SDR 0x01
+#define CMD_DDR 0x21
+#define RADDR_SDR 0x02
+#define RADDR_DDR 0x22
+#define CADDR_SDR 0x03
+#define CADDR_DDR 0x23
+#define MODE1_SDR 0x04
+#define MODE1_DDR 0x24
+#define MODE2_SDR 0x05
+#define MODE2_DDR 0x25
+#define MODE4_SDR 0x06
+#define MODE4_DDR 0x26
+#define MODE8_SDR 0x07
+#define MODE8_DDR 0x27
+#define WRITE_SDR 0x08
+#define WRITE_DDR 0x28
+#define READ_SDR 0x09
+#define READ_DDR 0x29
+#define LEARN_SDR 0x0A
+#define LEARN_DDR 0x2A
+#define DATSZ_SDR 0x0B
+#define DATSZ_DDR 0x2B
+#define DUMMY_SDR 0x0C
+#define DUMMY_DDR 0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS 0x1F
+#define STOP 0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
+    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+//!@brief Definitions for FlexSPI Serial Clock Frequency
+typedef enum _FlexSpiSerialClockFreq
+{
+    kFlexSpiSerialClk_30MHz = 1,
+    kFlexSpiSerialClk_50MHz = 2,
+    kFlexSpiSerialClk_60MHz = 3,
+    kFlexSpiSerialClk_75MHz = 4,
+    kFlexSpiSerialClk_80MHz = 5,
+    kFlexSpiSerialClk_100MHz = 6,
+    kFlexSpiSerialClk_133MHz = 7,
+    kFlexSpiSerialClk_166MHz = 8,
+    kFlexSpiSerialClk_200MHz = 9,
+} flexspi_serial_clk_freq_t;
+
+//!@brief FlexSPI clock configuration type
+enum
+{
+    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
+    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
+};
+
+//!@brief FlexSPI Read Sample Clock Source definition
+typedef enum _FlashReadSampleClkSource
+{
+    kFlexSPIReadSampleClk_LoopbackInternally = 0,
+    kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
+    kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
+    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+
+//!@brief Misc feature bit definitions
+enum
+{
+    kFlexSpiMiscOffset_DiffClkEnable = 0,            //!< Bit for Differential clock enable
+    kFlexSpiMiscOffset_Ck2Enable = 1,                //!< Bit for CK2 enable
+    kFlexSpiMiscOffset_ParallelEnable = 2,           //!< Bit for Parallel mode enable
+    kFlexSpiMiscOffset_WordAddressableEnable = 3,    //!< Bit for Word Addressable enable
+    kFlexSpiMiscOffset_SafeConfigFreqEnable = 4,     //!< Bit for Safe Configuration Frequency enable
+    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
+    kFlexSpiMiscOffset_DdrModeEnable = 6,            //!< Bit for DDR clock confiuration indication.
+};
+
+//!@brief Flash Type Definition
+enum
+{
+    kFlexSpiDeviceType_SerialNOR = 1,       //!< Flash devices are Serial NOR
+    kFlexSpiDeviceType_SerialNAND = 2,      //!< Flash devices are Serial NAND
+    kFlexSpiDeviceType_SerialRAM = 3,       //!< Flash devices are Serial RAM/HyperFLASH
+    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
+    kFlexSpiDeviceType_MCP_NOR_RAM = 0x13,  //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+};
+
+//!@brief Flash Pad Definitions
+enum
+{
+    kSerialFlash_1Pad = 1,
+    kSerialFlash_2Pads = 2,
+    kSerialFlash_4Pads = 4,
+    kSerialFlash_8Pads = 8,
+};
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _lut_sequence
+{
+    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
+    uint16_t reserved;
+} flexspi_lut_seq_t;
+
+//!@brief Flash Configuration Command Type
+enum
+{
+    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
+    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
+    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
+    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
+    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
+    kDeviceConfigCmdType_Reset,      //!< Reset device command
+};
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _FlexSPIConfig
+{
+    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
+    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+    uint8_t csHoldTime;       //!< [0x00d-0x00d] CS hold time, default value: 3
+    uint8_t csSetupTime;      //!< [0x00e-0x00e] CS setup time, default value: 3
+    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+    //! Serial NAND, need to refer to datasheet
+    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+    //! Generic configuration, etc.
+    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+    //! DPI/QPI/OPI switch or reset command
+    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+    //! sequence number, [31:16] Reserved
+    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
+    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+    flexspi_lut_seq_t
+        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
+    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
+    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+    //! details
+    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
+    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    //! Chapter for more details
+    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
+    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
+    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
+    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
+    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
+    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
+    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
+    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
+    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
+    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
+    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+    //! busy flag is 0 when flash device is busy
+    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
+    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
+} flexspi_mem_config_t;
+
+/*  */
+#define NOR_CMD_INDEX_READ CMD_INDEX_READ               //!< 0
+#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS   //!< 1
+#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
+#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
+#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
+#define NOR_CMD_INDEX_CHIPERASE 5                       //!< 5
+#define NOR_CMD_INDEX_DUMMY 6                           //!< 6
+#define NOR_CMD_INDEX_ERASEBLOCK 7                      //!< 7
+
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
+    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
+    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8  //!< 8 Erase Block sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
+    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
+
+
+/*
+ *  Serial NOR configuration block
+ */
+typedef struct _flexspi_nor_config
+{
+    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+    uint32_t pageSize;              //!< Page size of Serial NOR
+    uint32_t sectorSize;            //!< Sector size of Serial NOR
+    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
+    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
+    uint8_t reserved0[2];           //!< Reserved for future use
+    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
+    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
+    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint32_t blockSize;             //!< Block size
+    uint32_t reserve2[11];          //!< Reserved for future use
+} flexspi_nor_config_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __FLEXSPI_NOR_FLASH_H__
diff --git a/Ubiquitous/XiZi/path_kernel.mk b/Ubiquitous/XiZi/path_kernel.mk
index 6e90d6c27..2bdbb01f0 100755
--- a/Ubiquitous/XiZi/path_kernel.mk
+++ b/Ubiquitous/XiZi/path_kernel.mk
@@ -18,7 +18,8 @@ KERNELPATHS :=-I$(BSP_ROOT) \
 	-I$(BSP_ROOT)/third_party_driver/CMSIS/Include \
 	-I$(KERNEL_ROOT)/include \
 	-I$(KERNEL_ROOT)/resources/include \
-	-I$(BSP_ROOT)/include #
+	-I$(BSP_ROOT)/include \
+	-I$(BSP_ROOT)/xip #
 endif
 
 ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/kd233)
@@ -225,7 +226,8 @@ KERNELPATHS :=-I$(BSP_ROOT) \
 	-I$(KERNEL_ROOT)/resources/ethernet/LwIP/include/lwip/prot \
 	-I$(KERNEL_ROOT)/resources/ethernet/LwIP/arch \
 	-I$(KERNEL_ROOT)/resources/include \
-	-I$(BSP_ROOT)/include #
+	-I$(BSP_ROOT)/include \
+	-I$(BSP_ROOT)/xip #
 endif
 
 ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/stm32f103-nano)