450 lines
22 KiB
C
450 lines
22 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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#ifndef __SOC_H
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#define __SOC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "hal_conf.h"
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/* IO definitions (access restrictions to peripheral registers) */
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#ifdef __cplusplus
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#define __I volatile /*!< brief Defines 'read only' permissions */
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#else
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#define __I volatile const /*!< brief Defines 'read only' permissions */
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#endif
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#define __O volatile /*!< brief Defines 'write only' permissions */
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#define __IO volatile /*!< brief Defines 'read / write' permissions */
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/* ================================================================================ */
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/* ================ DMA REQ =============== */
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/* ================================================================================ */
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typedef enum {
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DMA_REQ_UART0_TX = 0,
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DMA_REQ_UART0_RX = 1,
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DMA_REQ_UART1_TX = 2,
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DMA_REQ_UART1_RX = 3,
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DMA_REQ_UART2_TX = 4,
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DMA_REQ_UART2_RX = 5,
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DMA_REQ_UART3_TX = 6,
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DMA_REQ_UART3_RX = 7,
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DMA_REQ_UART4_TX = 8,
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DMA_REQ_UART4_RX = 9,
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DMA_REQ_UART5_TX = 10,
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DMA_REQ_UART5_RX = 11,
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DMA_REQ_UART6_TX = 12,
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DMA_REQ_UART6_RX = 13,
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DMA_REQ_UART7_TX = 14,
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DMA_REQ_UART7_RX = 15,
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DMA_REQ_UART8_TX = 16,
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DMA_REQ_UART8_RX = 17,
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DMA_REQ_UART9_TX = 18,
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DMA_REQ_UART9_RX = 19,
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DMA_REQ_SPI0_TX = 20,
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DMA_REQ_SPI0_RX = 21,
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DMA_REQ_SPI1_TX = 22,
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DMA_REQ_SPI1_RX = 23,
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DMA_REQ_SPI2_TX = 24,
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DMA_REQ_SPI2_RX = 25,
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DMA_REQ_SPI3_TX = 26,
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DMA_REQ_SPI3_RX = 27,
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} DMA_REQ_Type;
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/* ================================================================================ */
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/* ================ IRQ ================ */
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/* ================================================================================ */
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#ifdef HAL_MCU_CORE
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#define INTMUX_IRQ_START_NUM 32
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#define INTMUX_OUT_IRQ_START_NUM 0
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#define INTMUX_NUM_INT_PER_OUT 64
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#define INTMUX_NUM_GROUP_PER_CON 8
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#define INTMUX_NUM_GROUP_PER_OUT 8
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#define INTMUX_NUM_INT_PER_GROUP 8
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#define NUM_EXT_INTERRUPTS 320
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typedef enum
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{
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/****** Platform Exceptions Numbers ***************************************************/
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NUM_INTERRUPTS = 0,
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DMAC0_ABORT_IRQn = 45, /*!< DMAC0 Abort Interrupt */
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DMAC0_IRQn = 46, /*!< DMAC0 Interrupt */
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DMAC1_ABORT_IRQn = 47, /*!< DMAC1 Abort Interrupt */
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DMAC1_IRQn = 48, /*!< DMAC1 Interrupt */
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GPIO0_IRQn = 65, /*!< GPIO0 Interrupt */
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GPIO1_IRQn = 66, /*!< GPIO1 Interrupt */
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GPIO2_IRQn = 67, /*!< GPIO2 Interrupt */
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GPIO3_IRQn = 68, /*!< GPIO3 Interrupt */
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GPIO4_IRQn = 69, /*!< GPIO4 Interrupt */
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I2C0_IRQn = 78, /*!< I2C0 Interrupt */
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I2C1_IRQn = 79, /*!< I2C1 Interrupt */
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I2C2_IRQn = 80, /*!< I2C2 Interrupt */
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I2C3_IRQn = 81, /*!< I2C3 Interrupt */
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I2C4_IRQn = 82, /*!< I2C4 Interrupt */
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I2C5_IRQn = 83, /*!< I2C5 Interrupt */
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PWM_PMU_IRQn = 114, /*!< PWM_PMU Interrupt */
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PWM1_IRQn = 115, /*!< PWM1 Interrupt */
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PWM2_IRQn = 116, /*!< PWM2 Interrupt */
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PWM3_IRQn = 117, /*!< PWM3 Interrupt */
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PWM_PMU_PWR_IRQn = 118, /*!< PWM_PMU PWR Interrupt */
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PWM1_PWR_IRQn = 119, /*!< PWM1 PWR Interrupt */
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PWM2_PWR_IRQn = 120, /*!< PWM2 PWR Interrupt */
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PWM3_PWR_IRQn = 121, /*!< PWM3 PWR Interrupt */
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SARADC_IRQn = 125, /*!< SARADC Interrupt */
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FSPI0_IRQn = 133, /*!< FSPI Interrupt */
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SPI0_IRQn = 135, /*!< SPI0 Interrupt */
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SPI1_IRQn = 136, /*!< SPI1 Interrupt */
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SPI2_IRQn = 137, /*!< SPI2 Interrupt */
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SPI3_IRQn = 138, /*!< SPI3 Interrupt */
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TIMER0_IRQn = 141, /*!< TIMER0 Interrupt */
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TIMER1_IRQn = 142, /*!< TIMER1 Interrupt */
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TIMER2_IRQn = 143, /*!< TIMER2 Interrupt */
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TIMER3_IRQn = 144, /*!< TIMER3 Interrupt */
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TIMER4_IRQn = 145, /*!< TIMER4 Interrupt */
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TIMER5_IRQn = 146, /*!< TIMER5 Interrupt */
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UART0_IRQn = 148, /*!< UART0 Interrupt */
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UART1_IRQn = 149, /*!< UART1 Interrupt */
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UART2_IRQn = 150, /*!< UART2 Interrupt */
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UART3_IRQn = 151, /*!< UART3 Interrupt */
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UART4_IRQn = 152, /*!< UART4 Interrupt */
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UART5_IRQn = 153, /*!< UART5 Interrupt */
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UART6_IRQn = 154, /*!< UART6 Interrupt */
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UART7_IRQn = 155, /*!< UART7 Interrupt */
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UART8_IRQn = 156, /*!< UART8 Interrupt */
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UART9_IRQn = 157, /*!< UART9 Interrupt */
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WDT0_IRQn = 181, /*!< WDT0 Interrupt */
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MBOX0_CH0_B2A_IRQn = 215, /*!< MBOX0 CH0 B2A Interrupt */
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MBOX0_CH1_B2A_IRQn = 216, /*!< MBOX0 CH1 B2A Interrupt */
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MBOX0_CH2_B2A_IRQn = 217, /*!< MBOX0 CH2 B2A Interrupt */
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MBOX0_CH3_B2A_IRQn = 218, /*!< MBOX0 CH3 B2A Interrupt */
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MBOX0_CH0_A2B_IRQn = 219, /*!< MBOX0 CH0 A2B Interrupt */
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MBOX0_CH1_A2B_IRQn = 220, /*!< MBOX0 CH1 A2B Interrupt */
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MBOX0_CH2_A2B_IRQn = 221, /*!< MBOX0 CH2 A2B Interrupt */
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MBOX0_CH3_A2B_IRQn = 222, /*!< MBOX0 CH3 A2B Interrupt */
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TOTAL_INTERRUPTS = (INTMUX_IRQ_START_NUM + NUM_INTERRUPTS + NUM_EXT_INTERRUPTS),
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} IRQn_Type;
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#else
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typedef enum
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{
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/* When IPI_SGIs are used in AMP mode, you need to pay attention to whether it conflicts
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* with SMP mode. Especially in the case of Linux OS as The Master Core.
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* IPI_SGI 0~7 for non-secure and IPI_SGI 8~15 for secure.
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*/
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IPI_SGI0 = 0,
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IPI_SGI1 = 1,
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IPI_SGI2 = 2,
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IPI_SGI3 = 3,
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IPI_SGI4 = 4,
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IPI_SGI5 = 5,
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IPI_SGI6 = 6,
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IPI_SGI7 = 7,
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IPI_SGI8 = 8,
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IPI_SGI9 = 9,
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IPI_SGI10 = 10,
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IPI_SGI11 = 11,
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IPI_SGI12 = 12,
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IPI_SGI13 = 13,
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IPI_SGI14 = 14,
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IPI_SGI15 = 15,
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CNTHP_IRQn = 26,
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CNTV_IRQn = 27,
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CNTPS_IRQn = 29,
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CNTPNS_IRQn = 30,
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/****** Platform Exceptions Numbers ***************************************************/
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CAN0_IRQn = 33, /*!< CAN0 Interrupt */
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CAN1_IRQn = 34, /*!< CAN1 Interrupt */
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CAN2_IRQn = 35, /*!< CAN2 Interrupt */
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DMAC0_ABORT_IRQn = 45, /*!< DMAC0 Abort Interrupt */
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DMAC0_IRQn = 46, /*!< DMAC0 Interrupt */
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DMAC1_ABORT_IRQn = 47, /*!< DMAC1 Abort Interrupt */
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DMAC1_IRQn = 48, /*!< DMAC1 Interrupt */
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GMAC0_IRQn = 59, /*!< GMAC0 Interrupt */
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GMAC1_IRQn = 64, /*!< GMAC1 Interrupt */
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GPIO0_IRQn = 65, /*!< GPIO0 Interrupt */
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GPIO1_IRQn = 66, /*!< GPIO1 Interrupt */
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GPIO2_IRQn = 67, /*!< GPIO2 Interrupt */
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GPIO3_IRQn = 68, /*!< GPIO3 Interrupt */
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GPIO4_IRQn = 69, /*!< GPIO4 Interrupt */
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I2C0_IRQn = 78, /*!< I2C0 Interrupt */
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I2C1_IRQn = 79, /*!< I2C1 Interrupt */
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I2C2_IRQn = 80, /*!< I2C2 Interrupt */
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I2C3_IRQn = 81, /*!< I2C3 Interrupt */
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I2C4_IRQn = 82, /*!< I2C4 Interrupt */
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I2C5_IRQn = 83, /*!< I2C5 Interrupt */
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PWM_PMU_IRQn = 114, /*!< PWM_PMU Interrupt */
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PWM1_IRQn = 115, /*!< PWM1 Interrupt */
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PWM2_IRQn = 116, /*!< PWM2 Interrupt */
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PWM3_IRQn = 117, /*!< PWM3 Interrupt */
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PWM_PMU_PWR_IRQn = 118, /*!< PWM_PMU PWR Interrupt */
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PWM1_PWR_IRQn = 119, /*!< PWM1 PWR Interrupt */
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PWM2_PWR_IRQn = 120, /*!< PWM2 PWR Interrupt */
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PWM3_PWR_IRQn = 121, /*!< PWM3 PWR Interrupt */
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SARADC_IRQn = 125, /*!< SARADC Interrupt */
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FSPI0_IRQn = 133, /*!< FSPI Interrupt */
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SPI0_IRQn = 135, /*!< SPI0 Interrupt */
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SPI1_IRQn = 136, /*!< SPI1 Interrupt */
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SPI2_IRQn = 137, /*!< SPI2 Interrupt */
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SPI3_IRQn = 138, /*!< SPI3 Interrupt */
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TIMER0_IRQn = 141, /*!< TIMER0 Interrupt */
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TIMER1_IRQn = 142, /*!< TIMER1 Interrupt */
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TIMER2_IRQn = 143, /*!< TIMER2 Interrupt */
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TIMER3_IRQn = 144, /*!< TIMER3 Interrupt */
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TIMER4_IRQn = 145, /*!< TIMER4 Interrupt */
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TIMER5_IRQn = 146, /*!< TIMER5 Interrupt */
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UART0_IRQn = 148, /*!< UART0 Interrupt */
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UART1_IRQn = 149, /*!< UART1 Interrupt */
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UART2_IRQn = 150, /*!< UART2 Interrupt */
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UART3_IRQn = 151, /*!< UART3 Interrupt */
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UART4_IRQn = 152, /*!< UART4 Interrupt */
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UART5_IRQn = 153, /*!< UART5 Interrupt */
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UART6_IRQn = 154, /*!< UART6 Interrupt */
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UART7_IRQn = 155, /*!< UART7 Interrupt */
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UART8_IRQn = 156, /*!< UART8 Interrupt */
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UART9_IRQn = 157, /*!< UART9 Interrupt */
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WDT0_IRQn = 181, /*!< WDT0 Interrupt */
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PCIE30x2_LEGACY_IRQn = 194, /*!< PCIe3x2_legacy Interrupt */
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DDR_ECC_CE_IRQn = 205, /*!< DDR ECC correctable fault Interrupt */
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DDR_ECC_UE_IRQn = 207, /*!< DDR ECC uncorrectable fault Interrupt */
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MBOX0_CH0_B2A_IRQn = 215, /*!< MBOX0 CH0 B2A Interrupt */
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MBOX0_CH1_B2A_IRQn = 216, /*!< MBOX0 CH1 B2A Interrupt */
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MBOX0_CH2_B2A_IRQn = 217, /*!< MBOX0 CH2 B2A Interrupt */
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MBOX0_CH3_B2A_IRQn = 218, /*!< MBOX0 CH3 B2A Interrupt */
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MBOX0_CH0_A2B_IRQn = 219, /*!< MBOX0 CH0 A2B Interrupt */
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MBOX0_CH1_A2B_IRQn = 220, /*!< MBOX0 CH1 A2B Interrupt */
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MBOX0_CH2_A2B_IRQn = 221, /*!< MBOX0 CH2 A2B Interrupt */
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MBOX0_CH3_A2B_IRQn = 222, /*!< MBOX0 CH3 A2B Interrupt */
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NFAULT0_IRQn = 272, /*!< DSU L3 CACHE ECC FAULT Interrupt */
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NFAULT1_IRQn = 273, /*!< CPU0 L1-L2 CACHE ECC FAULT Interrupt */
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NFAULT2_IRQn = 274, /*!< CPU1 L1-L2 CACHE ECC FAULT Interrupt */
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NFAULT3_IRQn = 275, /*!< CPU2 L1-L2 CACHE ECC FAULT Interrupt */
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NFAULT4_IRQn = 276, /*!< CPU3 L1-L2 CACHE ECC FAULT Interrupt */
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NERR0_IRQn = 277, /*!< DSU L3 CACHE ECC ERROR Interrupt */
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NERR1_IRQn = 278, /*!< CPU0 L1-L2 CACHE ECC ERROR Interrupt */
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NERR2_IRQn = 279, /*!< CPU1 L1-L2 CACHE ECC ERROR Interrupt */
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NERR3_IRQn = 280, /*!< CPU2 L1-L2 CACHE ECC ERROR Interrupt */
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NERR4_IRQn = 281, /*!< CPU3 L1-L2 CACHE ECC ERROR Interrupt */
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RSVD0_IRQn = 283, /*!< RSVD0 Interrupt */
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RPMSG_01_IRQn = 285, /*!< RPMSG 0->1 Interrupt */
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RPMSG_02_IRQn = 286, /*!< RPMSG 0->2 Interrupt */
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RPMSG_03_IRQn = 287, /*!< RPMSG 0->3 Interrupt */
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RPMSG_10_IRQn = 288, /*!< RPMSG 1->0 Interrupt */
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RPMSG_12_IRQn = 289, /*!< RPMSG 1->2 Interrupt */
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RPMSG_13_IRQn = 290, /*!< RPMSG 1->3 Interrupt */
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RPMSG_20_IRQn = 291, /*!< RPMSG 2->0 Interrupt */
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RPMSG_21_IRQn = 292, /*!< RPMSG 2->1 Interrupt */
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RPMSG_23_IRQn = 293, /*!< RPMSG 2->3 Interrupt */
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RPMSG_30_IRQn = 294, /*!< RPMSG 3->0 Interrupt */
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RPMSG_31_IRQn = 295, /*!< RPMSG 3->1 Interrupt */
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RPMSG_32_IRQn = 296, /*!< RPMSG 3->2 Interrupt */
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NUM_INTERRUPTS = 352,
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} IRQn_Type;
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#endif
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#define RSVD_IRQn(_N) (RSVD0_IRQn + (_N))
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#define AMP_CPUOFF_REQ_IRQ(cpu) RSVD_IRQn(11 + (cpu)) /* gic irq: 294 */
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#define GIC_TOUCH_REQ_IRQ(cpu) (AMP_CPUOFF_REQ_IRQ(4) + cpu) /* gic irq: 298 */
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#define GPIO_IRQ_GROUP_DIRQ_BASE RSVD_IRQn(37) /* gic irq: 320 */
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#define GPIO_IRQ_GROUP_DIRQ_NUM (NUM_INTERRUPTS - GPIO_IRQ_GROUP_DIRQ_BASE)
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#define GPIO_IRQ_GROUP_GPIO0_HWIRQ GPIO0_IRQn
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#define GPIO_IRQ_GROUP_GPION_HWIRQ GPIO4_IRQn
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/* ================================================================================ */
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/* ================ Processor and Core Peripheral Section ================ */
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/* ================================================================================ */
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#if defined(HAL_AP_CORE) && defined(HAL_MCU_CORE)
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#error "HAL_AP_CORE and HAL_MCU_CORE only one of them can be enabled"
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#endif
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#if !defined(HAL_AP_CORE) && !defined(HAL_MCU_CORE)
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#error "Please define HAL_AP_CORE or HAL_MCU_CORE on hal_conf.h"
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#endif
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#ifdef HAL_AP_CORE
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#define __CORTEX_A 55U /* Cortex-A55 Core */
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#define __FPU_PRESENT 1U /* FPU present */
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#define __TIM_PRESENT 1U /* Generic Timer */
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#define CACHE_LINE_SHIFT (6U)
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#define CACHE_LINE_SIZE (0x1U << CACHE_LINE_SHIFT)
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#else
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#define __RISC_V
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#endif
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#ifndef __ASSEMBLY__
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// #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
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// #ifdef __CORTEX_A
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// #include "core_ca.h"
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// #endif
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#include "system_rk3568.h"
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#endif /* __ASSEMBLY__ */
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#include "rk3568.h"
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/****************************************************************************************/
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/* */
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/* Module Address Section */
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/* */
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/****************************************************************************************/
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/* Memory Base */
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#define PCIE3X2_DBI_BASE 0xF6000000 /* PCIe dbi base address */
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#define GIC_DISTRIBUTOR_BASE 0xFD400000 /* GICD base address */
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#define GIC_REDISTRIBUTOR_BASE 0xFD460000 /* GICR base address */
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#define PCIE3PHY_GRF_BASE 0xFDCB8000 /* S-PHY_GRF base address */
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#define PCIE3X2_APB_BASE 0xFE280000 /* PCIe apb base address */
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/****************************************************************************************/
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/* */
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/* Register Bitmap Section */
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/* */
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/****************************************************************************************/
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/********************************** CPU Topology ****************************************/
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#define MPIDR_MT_MASK ((1U) << 24)
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#define MPIDR_AFFLVL_MASK (0xFFU)
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#define MPIDR_AFF0_SHIFT (0U)
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#define MPIDR_AFF1_SHIFT (8U)
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#define MPIDR_AFF2_SHIFT (16U)
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#define MPIDR_AFF3_SHIFT (32U)
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#define MPIDR_AFFINITY_MASK (0xFFFFFFU)
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#define PLATFORM_CLUSTER0_CORE_COUNT (4)
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#define PLATFORM_CLUSTER1_CORE_COUNT (0)
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#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
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#define CPU_GET_AFFINITY(cpuId, clusterId) ((cpuId) << MPIDR_AFF1_SHIFT)
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/********************************** CACHE ECC ****************************************/
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#ifndef __ASSEMBLY__
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/** @addtogroup CACHE_ECC_Exported_Definition_Group1
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* @{
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*/
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/** the fault value will be injected */
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typedef enum {
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CACHE_ECC_INJECT_UC = 0x80000002, /**< Uncontainable Error generation */
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CACHE_ECC_INJECT_DE_UER = 0x8000000a, /**< for l1~l2, generate a exception */
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} eCACHE_ECC_InjectFault;
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/** @} */
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#endif
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/******************************************CRU*******************************************/
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#define PLL_INPUT_OSC_RATE (24 * 1000 * 1000)
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#define CRU_SRST_CON_CNT 29
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#define CRU_GATE_CON_CNT 35
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#define CRU_CLK_DIV_CON_CNT 84
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#define CRU_CLK_SEL_CON_CNT 84
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#define CLK(mux, div) \
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(((mux) & 0x0F0F00FFU) | (((div) & 0xFFU) << 8) | (((div) & 0x0F0F0000U) << 4))
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#ifndef __ASSEMBLY__
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typedef enum CLOCK_Name {
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CLK_INVALID = 0U,
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PLL_APLL,
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PLL_CPLL,
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PLL_GPLL,
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PLL_NPLL,
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PLL_VPLL,
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PLL_PPLL,
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PLL_HPLL,
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CLK_WDT,
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CLK_UART0,
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CLK_I2C = CLK(CLK_I2C_SEL, 0U),
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CLK_PWM1 = CLK(CLK_PWM1_SEL, 0U),
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CLK_PWM2 = CLK(CLK_PWM2_SEL, 0U),
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CLK_PWM3 = CLK(CLK_PWM3_SEL, 0U),
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CLK_SPI0 = CLK(CLK_SPI0_SEL, 0U),
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CLK_SPI1 = CLK(CLK_SPI1_SEL, 0U),
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CLK_SPI2 = CLK(CLK_SPI2_SEL, 0U),
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CLK_SPI3 = CLK(CLK_SPI3_SEL, 0U),
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CLK_UART1_SRC = CLK(CLK_UART1_SRC_SEL, CLK_UART1_SRC_DIV),
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CLK_UART1_FRAC = CLK(0U, CLK_UART1_FRAC_DIV),
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CLK_UART1 = CLK(SCLK_UART1_SEL, 0U),
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CLK_UART2_SRC = CLK(CLK_UART2_SRC_SEL, CLK_UART2_SRC_DIV),
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CLK_UART2_FRAC = CLK(0U, CLK_UART2_FRAC_DIV),
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CLK_UART2 = CLK(SCLK_UART2_SEL, 0U),
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CLK_UART3_SRC = CLK(CLK_UART3_SRC_SEL, CLK_UART3_SRC_DIV),
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CLK_UART3_FRAC = CLK(0U, CLK_UART3_FRAC_DIV),
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CLK_UART3 = CLK(SCLK_UART3_SEL, 0U),
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CLK_UART4_SRC = CLK(CLK_UART4_SRC_SEL, CLK_UART4_SRC_DIV),
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CLK_UART4_FRAC = CLK(0U, CLK_UART4_FRAC_DIV),
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CLK_UART4 = CLK(SCLK_UART4_SEL, 0U),
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CLK_UART5_SRC = CLK(CLK_UART5_SRC_SEL, CLK_UART5_SRC_DIV),
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CLK_UART5_FRAC = CLK(0U, CLK_UART5_FRAC_DIV),
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CLK_UART5 = CLK(SCLK_UART5_SEL, 0U),
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CLK_UART6_SRC = CLK(CLK_UART6_SRC_SEL, CLK_UART6_SRC_DIV),
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CLK_UART6_FRAC = CLK(0U, CLK_UART6_FRAC_DIV),
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CLK_UART6 = CLK(SCLK_UART6_SEL, 0U),
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CLK_UART7_SRC = CLK(CLK_UART7_SRC_SEL, CLK_UART7_SRC_DIV),
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CLK_UART7_FRAC = CLK(0U, CLK_UART7_FRAC_DIV),
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CLK_UART7 = CLK(SCLK_UART7_SEL, 0U),
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CLK_UART8_SRC = CLK(CLK_UART8_SRC_SEL, CLK_UART8_SRC_DIV),
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CLK_UART8_FRAC = CLK(0U, CLK_UART8_FRAC_DIV),
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CLK_UART8 = CLK(SCLK_UART8_SEL, 0U),
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CLK_UART9_SRC = CLK(CLK_UART9_SRC_SEL, CLK_UART9_SRC_DIV),
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CLK_UART9_FRAC = CLK(0U, CLK_UART9_FRAC_DIV),
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CLK_UART9 = CLK(SCLK_UART9_SEL, 0U),
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CLK_CAN0 = CLK(CLK_CAN0_SEL, CLK_CAN0_DIV),
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CLK_CAN1 = CLK(CLK_CAN1_SEL, CLK_CAN1_DIV),
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|
CLK_CAN2 = CLK(CLK_CAN2_SEL, CLK_CAN2_DIV),
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|
CLK_TSADC_TSEN = CLK(CLK_TSADC_TSEN_SEL, CLK_TSADC_TSEN_DIV),
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|
CLK_TSADC = CLK(0, CLK_TSADC_DIV),
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|
SCLK_SFC = CLK(SCLK_SFC_SEL, 0U),
|
|
CLK_MAC0_2TOP = CLK(CLK_MAC0_2TOP_SEL, 0U),
|
|
CLK_MAC1_2TOP = CLK(CLK_MAC1_2TOP_SEL, 0U),
|
|
CLK_MAC0_OUT = CLK(CLK_MAC0_OUT_SEL, 0U),
|
|
CLK_MAC1_OUT = CLK(CLK_MAC1_OUT_SEL, 0U),
|
|
CLK_GMAC0_PTP_REF = CLK(CLK_GMAC0_PTP_REF_SEL, 0U),
|
|
CLK_GMAC1_PTP_REF = CLK(CLK_GMAC1_PTP_REF_SEL, 0U),
|
|
SCLK_GMAC0 = CLK(RMII0_EXTCLK_SEL, 0U),
|
|
SCLK_GMAC1 = CLK(RMII1_EXTCLK_SEL, 0U),
|
|
SCLK_GMAC0_RGMII_SPEED = CLK(RGMII0_CLK_SEL, 0U),
|
|
SCLK_GMAC1_RGMII_SPEED = CLK(RGMII1_CLK_SEL, 0U),
|
|
SCLK_GMAC0_RMII_SPEED = CLK(RMII0_CLK_SEL, 0U),
|
|
SCLK_GMAC1_RMII_SPEED = CLK(RMII1_CLK_SEL, 0U),
|
|
SCLK_GMAC0_RX_TX = CLK(CLK_GMAC0_RX_TX_SEL, 0U),
|
|
SCLK_GMAC1_RX_TX = CLK(CLK_GMAC1_RX_TX_SEL, 0U),
|
|
ACLK_PHP = CLK(ACLK_PHP_SEL, 0U),
|
|
HCLK_PHP = CLK(HCLK_PHP_SEL, 0U),
|
|
PCLK_PHP = CLK(0U, PCLK_PHP_DIV),
|
|
ACLK_USB = CLK(ACLK_USB_SEL, 0U),
|
|
HCLK_USB = CLK(HCLK_USB_SEL, 0U),
|
|
PCLK_USB = CLK(0U, PCLK_USB_DIV),
|
|
CLK_SDMMC0 = CLK(CLK_SDMMC0_SEL, 0U),
|
|
} eCLOCK_Name;
|
|
#endif
|
|
/****************************************MBOX********************************************/
|
|
#define MBOX_CNT 2
|
|
#define MBOX_CHAN_CNT 4
|
|
/****************************************GRF*********************************************/
|
|
#define GRF_IOMUX_BIT_PER_PIN (4)
|
|
#define GRF_DS_BIT_PER_PIN (8)
|
|
#define GRF_PULL_BIT_PER_PIN (2)
|
|
/****************************************GPIO********************************************/
|
|
// #ifdef GPIO_VER_ID
|
|
// #undef GPIO_VER_ID
|
|
// #define GPIO_VER_ID (0x01000C2BU)
|
|
// #endif
|
|
/****************************************PMU*********************************************/
|
|
#ifndef __ASSEMBLY__
|
|
typedef enum PD_Id {
|
|
PD_INVALID = 0U,
|
|
} ePD_Id;
|
|
#endif
|
|
/****************************************FSPI********************************************/
|
|
#define FSPI_CHIP_CNT (2)
|
|
|
|
/****************************************WDT*********************************************/
|
|
#define GLB_RST_SND_WDT GLB_RST_SND_WDT0
|
|
#define GLB_RST_FST_WDT GLB_RST_FST_WDT0
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif /* __cplusplus */
|
|
#endif /* __SOC_H */
|