421 lines
8.7 KiB
C
421 lines
8.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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#include "hal_bsp.h"
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#ifdef HAL_PL330_MODULE_ENABLED
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struct HAL_PL330_DEV g_pl330Dev0 =
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{
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.pReg = DMA0,
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.peripReqType = BURST,
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.irq[0] = DMAC0_IRQn,
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.irq[1] = DMAC0_ABORT_IRQn,
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.pd = 0,
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};
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struct HAL_PL330_DEV g_pl330Dev1 =
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{
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.pReg = DMA1,
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.peripReqType = BURST,
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.irq[0] = DMAC1_IRQn,
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.irq[1] = DMAC1_ABORT_IRQn,
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.pd = 0,
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};
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#endif
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#ifdef HAL_SPI_MODULE_ENABLED
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const struct HAL_SPI_DEV g_spi0Dev = {
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.base = SPI0_BASE,
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.clkId = CLK_SPI0,
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.clkGateID = CLK_SPI0_GATE,
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.pclkGateID = PCLK_SPI0_GATE,
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.irqNum = SPI0_IRQn,
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.isSlave = false,
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.txDma = {
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.channel = DMA_REQ_SPI0_TX,
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.direction = DMA_MEM_TO_DEV,
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.addr = SPI0_BASE + 0x400,
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.dmac = DMA0,
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},
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.rxDma = {
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.channel = DMA_REQ_SPI0_RX,
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.direction = DMA_DEV_TO_MEM,
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.addr = SPI0_BASE + 0x800,
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.dmac = DMA0,
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},
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};
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const struct HAL_SPI_DEV g_spi1Dev = {
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.base = SPI1_BASE,
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.clkId = CLK_SPI1,
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.clkGateID = CLK_SPI1_GATE,
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.pclkGateID = PCLK_SPI1_GATE,
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.irqNum = SPI1_IRQn,
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.isSlave = false,
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.txDma = {
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.channel = DMA_REQ_SPI1_TX,
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.direction = DMA_MEM_TO_DEV,
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.addr = SPI1_BASE + 0x400,
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.dmac = DMA0,
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},
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.rxDma = {
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.channel = DMA_REQ_SPI1_RX,
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.direction = DMA_DEV_TO_MEM,
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.addr = SPI1_BASE + 0x800,
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.dmac = DMA0,
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},
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};
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const struct HAL_SPI_DEV g_spi2Dev = {
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.base = SPI2_BASE,
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.clkId = CLK_SPI2,
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.clkGateID = CLK_SPI2_GATE,
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.pclkGateID = PCLK_SPI2_GATE,
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.irqNum = SPI2_IRQn,
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.isSlave = false,
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.txDma = {
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.channel = DMA_REQ_SPI2_TX,
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.direction = DMA_MEM_TO_DEV,
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.addr = SPI2_BASE + 0x400,
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.dmac = DMA0,
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},
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.rxDma = {
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.channel = DMA_REQ_SPI2_RX,
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.direction = DMA_DEV_TO_MEM,
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.addr = SPI2_BASE + 0x800,
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.dmac = DMA0,
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},
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};
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const struct HAL_SPI_DEV g_spi3Dev = {
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.base = SPI3_BASE,
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.clkId = CLK_SPI3,
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.clkGateID = CLK_SPI3_GATE,
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.pclkGateID = PCLK_SPI3_GATE,
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.irqNum = SPI3_IRQn,
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.isSlave = false,
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.txDma = {
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.channel = DMA_REQ_SPI3_TX,
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.direction = DMA_MEM_TO_DEV,
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.addr = SPI3_BASE + 0x400,
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.dmac = DMA0,
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},
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.rxDma = {
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.channel = DMA_REQ_SPI3_RX,
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.direction = DMA_DEV_TO_MEM,
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.addr = SPI3_BASE + 0x800,
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.dmac = DMA0,
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},
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};
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#endif
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#ifdef HAL_UART_MODULE_ENABLED
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const struct HAL_UART_DEV g_uart0Dev =
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{
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.pReg = UART0,
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.sclkID = CLK_UART0,
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.irqNum = UART0_IRQn,
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.isAutoFlow = false,
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};
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const struct HAL_UART_DEV g_uart1Dev =
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{
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.pReg = UART1,
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.sclkID = CLK_UART1,
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.sclkGateID = SCLK_UART1_GATE,
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.pclkGateID = PCLK_UART1_GATE,
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.irqNum = UART1_IRQn,
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.isAutoFlow = false,
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};
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const struct HAL_UART_DEV g_uart2Dev =
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{
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.pReg = UART2,
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.sclkID = CLK_UART2,
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.sclkGateID = SCLK_UART2_GATE,
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.pclkGateID = PCLK_UART2_GATE,
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.irqNum = UART2_IRQn,
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.isAutoFlow = false,
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};
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const struct HAL_UART_DEV g_uart3Dev =
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{
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.pReg = UART3,
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.sclkID = CLK_UART3,
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.sclkGateID = SCLK_UART3_GATE,
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.pclkGateID = PCLK_UART3_GATE,
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.irqNum = UART3_IRQn,
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.isAutoFlow = false,
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};
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const struct HAL_UART_DEV g_uart4Dev =
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{
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.pReg = UART4,
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.sclkID = CLK_UART4,
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.sclkGateID = SCLK_UART4_GATE,
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.pclkGateID = PCLK_UART4_GATE,
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.irqNum = UART4_IRQn,
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.isAutoFlow = false,
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};
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const struct HAL_UART_DEV g_uart5Dev =
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{
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.pReg = UART5,
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.sclkID = CLK_UART5,
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.sclkGateID = SCLK_UART5_GATE,
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.pclkGateID = PCLK_UART5_GATE,
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.irqNum = UART5_IRQn,
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.isAutoFlow = false,
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};
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const struct HAL_UART_DEV g_uart6Dev =
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{
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.pReg = UART6,
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.sclkID = CLK_UART6,
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.sclkGateID = SCLK_UART6_GATE,
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.pclkGateID = PCLK_UART6_GATE,
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.irqNum = UART6_IRQn,
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.isAutoFlow = false,
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};
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const struct HAL_UART_DEV g_uart7Dev =
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{
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.pReg = UART7,
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.sclkID = CLK_UART7,
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.sclkGateID = SCLK_UART7_GATE,
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.pclkGateID = PCLK_UART7_GATE,
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.irqNum = UART7_IRQn,
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.isAutoFlow = false,
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};
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const struct HAL_UART_DEV g_uart8Dev =
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{
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.pReg = UART8,
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.sclkID = CLK_UART8,
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.sclkGateID = SCLK_UART8_GATE,
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.pclkGateID = PCLK_UART8_GATE,
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.irqNum = UART8_IRQn,
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.isAutoFlow = false,
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};
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const struct HAL_UART_DEV g_uart9Dev =
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{
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.pReg = UART9,
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.sclkID = CLK_UART9,
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.sclkGateID = SCLK_UART9_GATE,
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.pclkGateID = PCLK_UART9_GATE,
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.irqNum = UART9_IRQn,
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.isAutoFlow = false,
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};
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#endif
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#ifdef HAL_I2C_MODULE_ENABLED
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const struct HAL_I2C_DEV g_i2c0Dev =
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{
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.pReg = I2C0,
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.irqNum = I2C0_IRQn,
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.clkID = CLK_I2C,
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.clkGateID = CLK_I2C0_GATE,
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.pclkGateID = PCLK_I2C0_GATE,
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.runtimeID = PM_RUNTIME_ID_I2C0,
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};
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const struct HAL_I2C_DEV g_i2c1Dev =
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{
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.pReg = I2C1,
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.irqNum = I2C1_IRQn,
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.clkID = CLK_I2C,
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.clkGateID = CLK_I2C1_GATE,
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.pclkGateID = PCLK_I2C1_GATE,
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.runtimeID = PM_RUNTIME_ID_I2C1,
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};
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const struct HAL_I2C_DEV g_i2c2Dev =
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{
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.pReg = I2C2,
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.irqNum = I2C2_IRQn,
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.clkID = CLK_I2C,
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.clkGateID = CLK_I2C2_GATE,
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.pclkGateID = PCLK_I2C2_GATE,
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.runtimeID = PM_RUNTIME_ID_I2C2,
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};
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const struct HAL_I2C_DEV g_i2c3Dev =
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{
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.pReg = I2C3,
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.irqNum = I2C3_IRQn,
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.clkID = CLK_I2C,
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.clkGateID = CLK_I2C3_GATE,
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.pclkGateID = PCLK_I2C3_GATE,
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.runtimeID = PM_RUNTIME_ID_I2C3,
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};
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const struct HAL_I2C_DEV g_i2c4Dev =
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{
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.pReg = I2C4,
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.irqNum = I2C4_IRQn,
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.clkID = CLK_I2C,
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.clkGateID = CLK_I2C4_GATE,
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.pclkGateID = PCLK_I2C4_GATE,
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.runtimeID = PM_RUNTIME_ID_I2C4,
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};
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const struct HAL_I2C_DEV g_i2c5Dev =
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{
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.pReg = I2C5,
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.irqNum = I2C5_IRQn,
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.clkID = CLK_I2C,
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.clkGateID = CLK_I2C5_GATE,
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.pclkGateID = PCLK_I2C5_GATE,
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.runtimeID = PM_RUNTIME_ID_I2C5,
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};
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#endif
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#ifdef HAL_FSPI_MODULE_ENABLED
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struct HAL_FSPI_HOST g_fspi0Dev =
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{
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.instance = FSPI,
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.sclkGate = SCLK_SFC_GATE,
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.hclkGate = HCLK_SFC_GATE,
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.xipClkGate = 0,
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.sclkID = 0,
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.irqNum = FSPI0_IRQn,
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.xipMemCode = 0,
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.xipMemData = 0,
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.xmmcDev[0] =
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{
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.type = 0,
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},
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};
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#endif
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#ifdef HAL_CANFD_MODULE_ENABLED
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const struct HAL_CANFD_DEV g_can0Dev =
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{
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.pReg = CAN0,
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.sclkID = CLK_CAN0,
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.sclkGateID = CLK_CAN0_GATE,
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.pclkGateID = PCLK_CAN0_GATE,
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.irqNum = CAN0_IRQn,
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};
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const struct HAL_CANFD_DEV g_can1Dev =
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{
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.pReg = CAN1,
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.sclkID = CLK_CAN1,
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.sclkGateID = CLK_CAN1_GATE,
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.pclkGateID = PCLK_CAN1_GATE,
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.irqNum = CAN1_IRQn,
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};
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const struct HAL_CANFD_DEV g_can2Dev =
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{
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.pReg = CAN2,
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.sclkID = CLK_CAN2,
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.sclkGateID = CLK_CAN2_GATE,
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.pclkGateID = PCLK_CAN2_GATE,
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.irqNum = CAN2_IRQn,
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};
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#endif
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#ifdef HAL_GMAC_MODULE_ENABLED
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// const struct HAL_GMAC_DEV g_gmac0Dev =
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// {
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// .pReg = GMAC0,
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// .clkID = CLK_MAC0_2TOP,
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// .clkGateID = CLK_MAC0_2TOP_GATE,
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// .pclkID = PCLK_PHP,
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// .pclkGateID = PCLK_GMAC0_GATE,
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// .irqNum = GMAC0_IRQn,
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// };
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const struct HAL_GMAC_DEV g_gmac0Dev =
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{
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.pReg = GMAC0,
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.clkID125M = CLK_MAC0_2TOP,
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.clkID50M = CLK_MAC0_2TOP,
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.clkGateID125M = CLK_MAC0_2TOP_GATE,
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.clkGateID50M = CLK_MAC0_2TOP_GATE,
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.pclkID = PCLK_PHP,
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.pclkGateID = PCLK_GMAC0_GATE,
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.irqNum = GMAC0_IRQn,
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};
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// const struct HAL_GMAC_DEV g_gmac1Dev =
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// {
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// .pReg = GMAC1,
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// .clkID = CLK_MAC1_2TOP,
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// .clkGateID = CLK_MAC1_2TOP_GATE,
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// .pclkID = PCLK_USB,
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// .pclkGateID = PCLK_GMAC1_GATE,
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// .irqNum = GMAC1_IRQn,
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// };
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const struct HAL_GMAC_DEV g_gmac1Dev =
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{
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.pReg = GMAC1,
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.clkID125M = CLK_MAC1_2TOP,
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.clkID50M = CLK_MAC1_2TOP,
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.clkGateID125M = CLK_MAC1_2TOP_GATE,
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.clkGateID50M = CLK_MAC1_2TOP_GATE,
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.pclkID = PCLK_USB,
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.pclkGateID = PCLK_GMAC1_GATE,
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.irqNum = GMAC1_IRQn,
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};
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#endif
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#ifdef HAL_PCIE_MODULE_ENABLED
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struct HAL_PCIE_DEV g_pcieDev =
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{
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.apbBase = PCIE3X2_APB_BASE,
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.dbiBase = PCIE3X2_DBI_BASE,
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.cfgBase = 0xF0000000,
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.lanes = 2,
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.gen = 3,
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.firstBusNo = 0x20,
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.legacyIrqNum = PCIE30x2_LEGACY_IRQn,
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};
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#endif
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#ifdef HAL_PWM_MODULE_ENABLED
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const struct HAL_PWM_DEV g_pwm0Dev =
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{
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.pReg = PWM0,
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.clkID = 0,
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.clkGateID = CLK_PWM0_GATE,
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.pclkGateID = PCLK_PWM0_GATE,
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.irqNum = PWM_PMU_IRQn,
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};
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const struct HAL_PWM_DEV g_pwm1Dev =
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{
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.pReg = PWM1,
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.clkID = CLK_PWM1,
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.clkGateID = CLK_PWM1_GATE,
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.pclkGateID = PCLK_PWM1_GATE,
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.irqNum = PWM1_IRQn,
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};
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const struct HAL_PWM_DEV g_pwm2Dev =
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{
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.pReg = PWM2,
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.clkID = CLK_PWM2,
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.clkGateID = CLK_PWM2_GATE,
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.pclkGateID = PCLK_PWM2_GATE,
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.irqNum = PWM2_IRQn,
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};
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const struct HAL_PWM_DEV g_pwm3Dev =
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{
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.pReg = PWM3,
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.clkID = CLK_PWM3,
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.clkGateID = CLK_PWM3_GATE,
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.pclkGateID = PCLK_PWM3_GATE,
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.irqNum = PWM3_IRQn,
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};
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#endif
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void BSP_Init(void)
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{
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}
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