426 lines
15 KiB
C
426 lines
15 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
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*/
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/** @addtogroup RK_HAL_Driver
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* @{
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*/
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/** @addtogroup GMAC
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* @{
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*/
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#ifndef __HAL_GMAC_H
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#define __HAL_GMAC_H
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#include "hal_def.h"
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#include "hal_base.h"
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/***************************** MACRO Definition ******************************/
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/** @defgroup GMAC_Exported_Definition_Group1 Basic Definition
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* @{
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*/
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/* GMAC PHY indicates what features are supported by the interface. */
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#define HAL_GMAC_PHY_SUPPORTED_10baseT_Half (1 << 0)
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#define HAL_GMAC_PHY_SUPPORTED_10baseT_Full (1 << 1)
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#define HAL_GMAC_PHY_SUPPORTED_100baseT_Half (1 << 2)
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#define HAL_GMAC_PHY_SUPPORTED_100baseT_Full (1 << 3)
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#define HAL_GMAC_PHY_SUPPORTED_1000baseT_Half (1 << 4)
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#define HAL_GMAC_PHY_SUPPORTED_1000baseT_Full (1 << 5)
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#define HAL_GMAC_PHY_SUPPORTED_Autoneg (1 << 6)
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#define HAL_GMAC_PHY_SUPPORTED_TP (1 << 7)
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#define HAL_GMAC_PHY_SUPPORTED_AUI (1 << 8)
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#define HAL_GMAC_PHY_SUPPORTED_MII (1 << 9)
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#define HAL_GMAC_PHY_SUPPORTED_FIBRE (1 << 10)
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#define HAL_GMAC_PHY_SUPPORTED_BNC (1 << 11)
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#define HAL_GMAC_PHY_SUPPORTED_10000baseT_Full (1 << 12)
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#define HAL_GMAC_PHY_SUPPORTED_Pause (1 << 13)
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#define HAL_GMAC_PHY_SUPPORTED_Asym_Pause (1 << 14)
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#define HAL_GMAC_PHY_SUPPORTED_2500baseX_Full (1 << 15)
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#define HAL_GMAC_PHY_SUPPORTED_Backplane (1 << 16)
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#define HAL_GMAC_PHY_SUPPORTED_1000baseKX_Full (1 << 17)
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#define HAL_GMAC_PHY_SUPPORTED_10000baseKX4_Full (1 << 18)
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#define HAL_GMAC_PHY_SUPPORTED_10000baseKR_Full (1 << 19)
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#define HAL_GMAC_PHY_SUPPORTED_10000baseR_FEC (1 << 20)
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#define HAL_GMAC_PHY_SUPPORTED_1000baseX_Half (1 << 21)
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#define HAL_GMAC_PHY_SUPPORTED_1000baseX_Full (1 << 22)
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#define HAL_GMAC_PHY_DEFAULT_FEATURES (HAL_GMAC_PHY_SUPPORTED_Autoneg | \
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HAL_GMAC_PHY_SUPPORTED_TP | \
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HAL_GMAC_PHY_SUPPORTED_MII)
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#define HAL_GMAC_PHY_10BT_FEATURES (HAL_GMAC_PHY_SUPPORTED_10baseT_Half | \
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HAL_GMAC_PHY_SUPPORTED_10baseT_Full)
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#define HAL_GMAC_PHY_100BT_FEATURES (HAL_GMAC_PHY_SUPPORTED_100baseT_Half | \
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HAL_GMAC_PHY_SUPPORTED_100baseT_Full)
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#define HAL_GMAC_PHY_1000BT_FEATURES (HAL_GMAC_PHY_SUPPORTED_1000baseT_Half | \
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HAL_GMAC_PHY_SUPPORTED_1000baseT_Full)
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#define HAL_GMAC_PHY_BASIC_FEATURES (HAL_GMAC_PHY_10BT_FEATURES | \
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HAL_GMAC_PHY_100BT_FEATURES | \
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HAL_GMAC_PHY_DEFAULT_FEATURES)
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#define HAL_GMAC_PHY_GBIT_FEATURES (HAL_GMAC_PHY_BASIC_FEATURES | \
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HAL_GMAC_PHY_1000BT_FEATURES)
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/* GMAC flow ctrl Definition */
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#define HAL_GMAC_FLOW_OFF 0
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#define HAL_GMAC_FLOW_RX 1
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#define HAL_GMAC_FLOW_TX 2
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#define HAL_GMAC_FLOW_AUTO (HAL_GMAC_FLOW_TX | HAL_GMAC_FLOW_RX)
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/* GMAC descriptions and buffers Definition */
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#define HAL_GMAC_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))
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#define HAL_GMAC_DESCRIPTOR_WORDS 4
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#define HAL_GMAC_DESCRIPTOR_SIZE (HAL_GMAC_DESCRIPTOR_WORDS * 4)
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#define HAL_GMAC_BUFFER_ALIGN 64
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#define HAL_GMAC_MAX_FRAME_SIZE 1518
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#define HAL_GMAC_MAX_PACKET_SIZE HAL_GMAC_ALIGN(HAL_GMAC_MAX_FRAME_SIZE, HAL_GMAC_BUFFER_ALIGN)
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/***************************** Structure Definition **************************/
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struct GMAC_HANDLE;
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/**
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* @brief GMAC PHY Speed
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*/
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typedef enum {
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PHY_SPEED_10M = 10,
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PHY_SPEED_100M = 100,
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PHY_SPEED_1000M = 1000,
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} eGMAC_PHY_SPEED;
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/**
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* @brief GMAC PHY Duplex
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*/
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typedef enum {
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PHY_DUPLEX_HALF = 0,
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PHY_DUPLEX_FULL = 1,
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} eGMAC_PHY_DUPLEX;
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/**
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* @brief GMAC PHY Auto Negrotetion
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*/
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typedef enum {
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PHY_AUTONEG_DISABLE = 0,
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PHY_AUTONEG_ENABLE = 1,
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} eGMAC_PHY_NEGROTETION;
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/**
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* @brief GMAC PHY Interface Mode
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*/
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typedef enum {
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PHY_INTERFACE_MODE_MII,
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PHY_INTERFACE_MODE_RMII,
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PHY_INTERFACE_MODE_RGMII,
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PHY_INTERFACE_MODE_NONE,
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} eGMAC_PHY_Interface;
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/**
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* @brief GMAC DMA IRQ Status
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*/
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typedef enum {
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DMA_UNKNOWN = 0x0,
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DMA_HANLE_RX = 0x1,
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DMA_HANLE_TX = 0x2,
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DMA_TX_ERROR = 0x10,
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DMA_RX_ERROR = 0x20,
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} eGMAC_IRQ_Status;
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/**
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* @brief GMAC PHY OPS Structure Definition
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*/
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struct GMAC_PHY_OPS {
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HAL_Status (*init)(struct GMAC_HANDLE *pGMAC); /**< Will be called during HAL_GMAC_PHYInit(). */
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HAL_Status (*config)(struct GMAC_HANDLE *pGMAC); /**< Called to configure the PHY, and modify the PHY,
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based on the results. Should be called after HAL_GMAC_PHYInit(). */
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HAL_Status (*startup)(struct GMAC_HANDLE *pGMAC); /**< Called when starting up the PHY */
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HAL_Status (*shutdown)(struct GMAC_HANDLE *pGMAC); /**< Called when bringing down the PHY */
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HAL_Status (*reset)(struct GMAC_HANDLE *pGMAC); /**< Called when hardware reset */
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HAL_Status (*softreset)(struct GMAC_HANDLE *pGMAC);/**< Called when soft reset */
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};
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/**
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* @brief GMAC PHY Config Structure Definition
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*/
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struct GMAC_PHY_Config {
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eGMAC_PHY_Interface interface;/**< Ethernet interface mode. */
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int16_t phyAddress; /**< Ethernet PHY address,
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This parameter must be a number between Min = 0 and Max = 31 */
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eGMAC_PHY_NEGROTETION neg; /**< Selects or disable the AutoNegotiation mode for the external PHY,
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The AutoNegotiation allows an automatic setting of the Speed
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(10/100/1000 Mbps) and the mode (half/full-duplex). */
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eGMAC_PHY_SPEED speed; /**< Sets the Ethernet speed: 10/100/1000 Mbps
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while disable AutoNegotiation. */
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eGMAC_PHY_DUPLEX duplexMode; /**< Selects the Ethernet duplex mode: Half-Duplex or
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Full-Duplex mode while disable AutoNegotiation. */
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eGMAC_PHY_SPEED maxSpeed; /**< Sets the Ethernet max speed: 10/100/1000 Mbps. */
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uint32_t features; /**< Sets the Ethernet PHY features. */
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};
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/**
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* @brief GMAC PHY Status Structure Definition
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*/
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struct GMAC_PHY_STATUS {
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eGMAC_PHY_Interface interface; /**< Ethernet interface mode. */
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/* forced speed & duplex (no autoneg)
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* partner speed & duplex & pause (autoneg)
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*/
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eGMAC_PHY_SPEED speed; /**< Ethernet speed. */
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eGMAC_PHY_DUPLEX duplex; /**< Ethernet duplex. */
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eGMAC_PHY_SPEED maxSpeed; /**< Ethernet max speed. */
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eGMAC_PHY_NEGROTETION neg; /**< Ethernet AutoNegotiation or not. */
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/* The most recently read link state */
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int link; /**< Ethernet current link. */
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int oldLink; /**< Store the Ethernet last link. */
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uint32_t features; /**< Ethernet PHY actual features. */
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uint32_t advertising; /**< Ethernet PHY advertising features. */
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uint32_t supported; /**< Ethernet PHY supported features. */
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int16_t addr; /**< Ethernet PHY address. */
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int16_t pause; /**< Ethernet PHY address. */
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uint32_t phyID; /**< Ethernet PHY ID. */
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};
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/**
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* @brief GMAC Link Config Structure Definition
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*/
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struct GMAC_Link {
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uint32_t speedMask;
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uint32_t speed10;
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uint32_t speed100;
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uint32_t speed1000;
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uint32_t duplex;
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};
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/**
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* @brief GMAC DMA Descriptors Data Structure Definition
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*/
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struct GMAC_Desc {
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uint32_t des0; /**< DMA Descriptors first word */
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uint32_t des1; /**< DMA Descriptors second word */
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uint32_t des2; /**< DMA Descriptors third word */
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uint32_t des3; /**< DMA Descriptors four word */
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};
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/**
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* @brief GMAC DMA Transfer Status Structure Definition
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*/
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struct GMAC_DMAStats {
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uint32_t txUndeflowIRQ;
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uint32_t txProcessStoppedIRQ;
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uint32_t txJabberIRQ;
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uint32_t rxOverflowIRQ;
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uint32_t rxBufUnavIRQ;
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uint32_t rxProcessStoppedIRQ;
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uint32_t rxWatchdogIRQ;
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uint32_t txEarlyIRQ;
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uint32_t fatalBusErrorIRQ;
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uint32_t normalIRQN;
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uint32_t rxNormalIRQN;
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uint32_t txNormallIRQN;
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uint32_t rxEarlyIRQ;
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uint32_t thresHold;
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uint32_t txPktN;
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uint32_t rxPktN;
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uint32_t txBytesN;
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uint32_t rxBytesN;
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uint32_t txErrors;
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uint32_t rxErrors;
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};
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/**
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* @brief GMAC device information Structure Definition
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*/
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struct GMAC_DEVICE_INFO {
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uint32_t miiAddrShift;
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uint32_t miiAddrMask;
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uint32_t miiRegShift;
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uint32_t miiRegMask;
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uint32_t clkCsrShift;
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uint32_t clkCsrMask;
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};
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/**
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* @brief GMAC Handle Structure Definition
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*/
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struct GMAC_HANDLE {
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struct GMAC_REG *pReg; /**< Register base address */
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uint32_t clkCSR; /**< clock csr value, div for MDC clock */
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struct GMAC_DEVICE_INFO mac; /**< MAC information */
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struct GMAC_PHY_OPS phyOps; /**< phy ops callback function */
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struct GMAC_PHY_Config phyConfig; /**< phy config provied by user */
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struct GMAC_PHY_STATUS phyStatus; /**< phy status */
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struct GMAC_Link link; /**< GMAC link config */
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struct GMAC_DMAStats extraStatus; /**< GMAC DMA transfer status */
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struct GMAC_Desc *rxDescs; /**< First Rx descriptor pointer */
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struct GMAC_Desc *txDescs; /**< First Tx descriptor pointer */
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uint8_t *txBuf; /**< First Tx buffer pointer */
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uint8_t *rxBuf; /**< First Tx buffer pointer */
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uint32_t txDescIdx; /**< Current Tx descriptor index */
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uint32_t rxDescIdx; /**< Current Rx descriptor pointer */
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uint32_t txSize; /**< Tx descriptor size*/
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uint32_t rxSize; /**< Rx descriptor size */
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};
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#define PM_RUNTIME_TYPE_MUTI_SFT (3)
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#define PM_RUNTIME_PER_TYPE_NUM (8)
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#define PM_RUNTIME_TYPE_TO_FIRST_ID(type) ((type) << PM_RUNTIME_TYPE_MUTI_SFT)
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#define PM_RUNTIME_ID_TO_TYPE(id) ((id) >> PM_RUNTIME_TYPE_MUTI_SFT)
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#define PM_RUNTIME_ID_TO_TYPE_OFFSET(id) ((id) % PM_RUNTIME_PER_TYPE_NUM)
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#define PM_RUNTIME_ID_TYPE_BIT_MSK(id) HAL_BIT(((id) % PM_RUNTIME_PER_TYPE_NUM))
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#define PM_DISPLAY_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_DISPLAY])
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#define PM_UART_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_UART])
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#define PM_I2C_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_I2C])
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#define PM_INTF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_INTF])
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#define PM_HS_INTF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_HS_INTF])
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#define PM_SPI_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_SPI])
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#define PM_CIF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_CIF])
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/* suspend config id */
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#define PM_SLEEP_MODE_CONFIG 0x01
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#define PM_SLEEP_WAKEUP_SOURCE 0x02
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enum {
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PM_RUNTIME_TYPE_INTF = 0, /**< normal interface */
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PM_RUNTIME_TYPE_DISPLAY,
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PM_RUNTIME_TYPE_AUDIO,
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PM_RUNTIME_TYPE_HS_INTF, /**< high speed interface */
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PM_RUNTIME_TYPE_STORAGE,
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PM_RUNTIME_TYPE_UART,
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PM_RUNTIME_TYPE_I2C,
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PM_RUNTIME_TYPE_SPI,
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PM_RUNTIME_TYPE_CIF,
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PM_RUNTIME_TYPE_DEVICE,
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PM_RUNTIME_TYPE_END,
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};
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typedef enum {
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PM_RUNTIME_IDLE_ONLY = 0,
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PM_RUNTIME_IDLE_NORMAL,
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PM_RUNTIME_IDLE_DEEP,
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PM_RUNTIME_IDLE_DEEP1,
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PM_RUNTIME_IDLE_DEEP2,
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} ePM_RUNTIME_idleMode;
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typedef enum {
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PM_RUNTIME_ID_INTF_INVLD = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_INTF), /**< the id = 0, is means invalid */
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PM_RUNTIME_ID_SPI_APB,
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PM_RUNTIME_ID_VOP = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_DISPLAY),
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PM_RUNTIME_ID_MIPI,
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PM_RUNTIME_ID_I2S = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_AUDIO),
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PM_RUNTIME_ID_I2S1,
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PM_RUNTIME_ID_I2S2,
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PM_RUNTIME_ID_ADC,
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PM_RUNTIME_ID_DMA,
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PM_RUNTIME_ID_USB = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_HS_INTF),
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PM_RUNTIME_ID_SDIO,
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PM_RUNTIME_ID_UART0 = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_UART),
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PM_RUNTIME_ID_UART1,
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PM_RUNTIME_ID_UART2,
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PM_RUNTIME_ID_UART3,
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PM_RUNTIME_ID_UART4,
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PM_RUNTIME_ID_UART5,
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PM_RUNTIME_ID_UART6,
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PM_RUNTIME_ID_UART7,
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PM_RUNTIME_ID_UART8,
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PM_RUNTIME_ID_UART9,
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PM_RUNTIME_ID_I2C0 = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_I2C),
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PM_RUNTIME_ID_I2C1,
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PM_RUNTIME_ID_I2C2,
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PM_RUNTIME_ID_I2C3,
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PM_RUNTIME_ID_I2C4,
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PM_RUNTIME_ID_I2C5,
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PM_RUNTIME_ID_SPI = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_SPI),
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PM_RUNTIME_ID_CIF = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_CIF),
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PM_RUNTIME_ID_END,
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} ePM_RUNTIME_ID;
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/**
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* @brief GMAC HW Information Definition
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*/
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struct HAL_GMAC_DEV {
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struct GMAC_REG *pReg;
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eCLOCK_Name clkID;
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uint32_t clkGateID;
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eCLOCK_Name pclkID;
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uint32_t pclkGateID;
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IRQn_Type irqNum;
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ePM_RUNTIME_ID runtimeID;
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};
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/** @} */
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/***************************** Function Declare ******************************/
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/** @defgroup GMAC_Public_Function_Declare Public Function Declare
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* @{
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*/
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HAL_Status HAL_GMAC_Init(struct GMAC_HANDLE *pGMAC, struct GMAC_REG *pReg,
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uint32_t freq, eGMAC_PHY_Interface interface,
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bool extClk);
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HAL_Status HAL_GMAC_DeInit(struct GMAC_HANDLE *pGMAC);
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HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr);
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HAL_Status HAL_GMAC_Stop(struct GMAC_HANDLE *pGMAC);
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void HAL_GMAC_EnableDmaIRQ(struct GMAC_HANDLE *pGMAC);
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void HAL_GMAC_DisableDmaIRQ(struct GMAC_HANDLE *pGMAC);
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HAL_Status HAL_GMAC_DMATxDescInit(struct GMAC_HANDLE *pGMAC,
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struct GMAC_Desc *txDescs,
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uint8_t *txBuff, uint32_t txBuffCount);
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HAL_Status HAL_GMAC_DMARxDescInit(struct GMAC_HANDLE *pGMAC,
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struct GMAC_Desc *rxDescs,
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uint8_t *rxBuff, uint32_t rxBuffCount);
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eGMAC_IRQ_Status HAL_GMAC_IRQHandler(struct GMAC_HANDLE *pGMAC);
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HAL_Status HAL_GMAC_AdjustLink(struct GMAC_HANDLE *pGMAC, int32_t txDelay,
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int32_t rxDelay);
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uint32_t HAL_GMAC_GetTXIndex(struct GMAC_HANDLE *pGMAC);
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uint32_t HAL_GMAC_GetRXIndex(struct GMAC_HANDLE *pGMAC);
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uint8_t *HAL_GMAC_GetTXBuffer(struct GMAC_HANDLE *pGMAC);
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uint8_t *HAL_GMAC_GetRXBuffer(struct GMAC_HANDLE *pGMAC);
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HAL_Status HAL_GMAC_Send(struct GMAC_HANDLE *pGMAC,
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void *packet, uint32_t length);
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uint8_t *HAL_GMAC_Recv(struct GMAC_HANDLE *pGMAC, int32_t *length);
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void HAL_GMAC_CleanRX(struct GMAC_HANDLE *pGMAC);
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void HAL_GMAC_WriteHWAddr(struct GMAC_HANDLE *pGMAC, uint8_t *enetAddr);
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HAL_Status HAL_GMAC_PHYInit(struct GMAC_HANDLE *pGMAC,
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struct GMAC_PHY_Config *config);
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HAL_Status HAL_GMAC_PHYStartup(struct GMAC_HANDLE *pGMAC);
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HAL_Status HAL_GMAC_PHYUpdateLink(struct GMAC_HANDLE *pGMAC);
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HAL_Status HAL_GMAC_PHYParseLink(struct GMAC_HANDLE *pGMAC);
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int32_t HAL_GMAC_MDIORead(struct GMAC_HANDLE *pGMAC, int32_t mdioAddr,
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int32_t mdioReg);
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HAL_Status HAL_GMAC_MDIOWrite(struct GMAC_HANDLE *pGMAC, int32_t mdioAddr,
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int32_t mdioReg, uint16_t mdioVal);
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void HAL_GMAC_SetToRGMII(struct GMAC_HANDLE *pGMAC,
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int32_t txDelay, int32_t rxDelay);
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void HAL_GMAC_SetToRMII(struct GMAC_HANDLE *pGMAC);
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void HAL_GMAC_SetRGMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed);
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void HAL_GMAC_SetRMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed);
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void HAL_GMAC_SetExtclkSrc(struct GMAC_HANDLE *pGMAC, bool extClk);
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/** @} */
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#endif
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/** @} */
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/** @} */
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