modify XiUOS DIR : (1.add plc_demo in APP_Framework/control_app; 2.add industrial_network、industrial_fieldbus and industrial_wlan; 3.add XiZi_AIoT and modify XiZi as XiZi_IIoT.)

2022-09-27 20:39:52 +08:00
parent dbca22a1a6
commit e14fa6ff8e
5009 changed files with 1019 additions and 3084 deletions
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+* @file board.h
+* @brief define imxrt1052-board init configure and start-up function
+* @version 1.0
+* @author AIIT XUOS Lab
+* @date 2021-05-28
+*/
+
+/*************************************************
+File name: board.h
+Description: define imxrt1052-board board init function and struct
+Others:
+History:
+1. Date: 2021-05-28
+Author: AIIT XUOS Lab
+Modification:
+1. define imxrt-board InitBoardHardware
+2. define imxrt-board heap struct
+*************************************************/
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+#include "fsl_clock.h"
+#include "fsl_enet.h"
+#include "clock_config.h"
+#include <xizi.h>
+#include <arch_interrupt.h>
+
+extern int heap_start;
+extern int heap_end;
+#define HEAP_BEGIN          (&heap_start)
+#define HEAP_END            (&heap_end)
+
+#define HEAP_SIZE           ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN)
+
+void InitBoardHardware(void);
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "IMXRT1050"
+
+#define NVIC_PRIORITYGROUP_0         0x00000007U /*!< 0 bits for pre-emption priority
+                                                      4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         0x00000006U /*!< 1 bits for pre-emption priority
+                                                      3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         0x00000005U /*!< 2 bits for pre-emption priority
+                                                      2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         0x00000004U /*!< 3 bits for pre-emption priority
+                                                      1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4         0x00000003U /*!< 4 bits for pre-emption priority*/
+
+/*! @brief The ENET PHY address. */
+#define BOARD_ENET0_PHY_ADDRESS (0x0U) /* Phy address of enet port 0. */
+
+/* USB PHY condfiguration */
+#define BOARD_USB_PHY_D_CAL (0x0CU)
+#define BOARD_USB_PHY_TXCAL45DP (0x06U)
+#define BOARD_USB_PHY_TXCAL45DM (0x06U)
+
+#define BOARD_ARDUINO_INT_IRQ (GPIO1_INT3_IRQn)
+#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
+#define BOARD_ARDUINO_I2C_INDEX (1)
+#define BOARD_USDHC1_BASEADDR USDHC1
+#define BOARD_USDHC2_BASEADDR USDHC2
+#define BOARD_USDHC_CD_GPIO_BASE GPIO2
+#define BOARD_USDHC_CD_GPIO_PIN 28
+#define BOARD_USDHC_CD_PORT_IRQ GPIO2_Combined_16_31_IRQn
+#define BOARD_USDHC_CD_PORT_IRQ_HANDLER GPIO2_Combined_16_31_IRQHandler
+
+#define BOARD_USDHC_CD_STATUS() (GPIO_PinRead(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN))
+
+#define BOARD_USDHC_CD_INTERRUPT_STATUS() (GPIO_PortGetInterruptFlags(BOARD_USDHC_CD_GPIO_BASE))
+#define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) (GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, flag))
+
+#define BOARD_USDHC_CD_GPIO_INIT()                                                          \
+    {                                                                                       \
+        gpio_pin_config_t sw_config = {                                                     \
+            kGPIO_DigitalInput,                                                             \
+            0,                                                                              \
+            kGPIO_IntRisingOrFallingEdge,                                                   \
+        };                                                                                  \
+        GPIO_PinInit(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN, &sw_config);        \
+        GPIO_PortEnableInterrupts(BOARD_USDHC_CD_GPIO_BASE, 1U << BOARD_USDHC_CD_GPIO_PIN); \
+        GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, ~0);                         \
+    }
+#define BOARD_HAS_SDCARD (1U)
+#define BOARD_SD_POWER_RESET_GPIO (GPIO1)
+#define BOARD_SD_POWER_RESET_GPIO_PIN (5U)
+
+#define BOARD_USDHC_CARD_INSERT_CD_LEVEL (0U)
+
+#define BOARD_USDHC_MMCCARD_POWER_CONTROL(state)
+
+#define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT()                                            \
+    {                                                                                       \
+        gpio_pin_config_t sw_config = {                                                     \
+            kGPIO_DigitalOutput,                                                            \
+            0,                                                                              \
+            kGPIO_NoIntmode,                                                                \
+        };                                                                                  \
+        GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
+        GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, true);      \
+    }
+
+#define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT()                                             \
+    {                                                                                       \
+        gpio_pin_config_t sw_config = {                                                     \
+            kGPIO_DigitalOutput,                                                            \
+            0,                                                                              \
+            kGPIO_NoIntmode,                                                                \
+        };                                                                                  \
+        GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
+    }
+
+#define BOARD_USDHC_SDCARD_POWER_CONTROL(state) \
+    (GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, state))
+
+#define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U))
+#define BOARD_USDHC2_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U))
+
+#define BOARD_SD_HOST_BASEADDR BOARD_USDHC1_BASEADDR
+#define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC1_CLK_FREQ
+#define BOARD_SD_HOST_IRQ USDHC1_IRQn
+
+#define BOARD_MMC_HOST_BASEADDR BOARD_USDHC2_BASEADDR
+#define BOARD_MMC_HOST_CLK_FREQ BOARD_USDHC2_CLK_FREQ
+#define BOARD_MMC_HOST_IRQ USDHC2_IRQn
+#define BOARD_MMC_VCCQ_SUPPLY kMMC_VoltageWindow170to195
+#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
+/* we are using the BB SD socket to DEMO the MMC example,but the
+ * SD socket provide 4bit bus only, so we define this macro to avoid
+ * 8bit data bus test
+ */
+#define BOARD_MMC_SUPPORT_8BIT_BUS (1U)
+
+#define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (200000000U)
+#define BOARD_SD_HOST_SUPPORT_HS200_FREQ (180000000U)
+
+/* @Brief Board accelerator sensor configuration */
+#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
+/* Select USB1 PLL (480 MHz) as LPI2C's clock source */
+#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
+/* Clock divider for LPI2C clock source */
+#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
+#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
+
+#define BOARD_CODEC_I2C_BASEADDR LPI2C1
+#define BOARD_CODEC_I2C_INSTANCE 1U
+#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
+#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
+#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+void BOARD_ConfigMPU(void);
+void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength);
+void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+* @file clock_config.h
+* @brief define imxrt1052-board clock configure
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-05-29
+*/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             600000000U  /*!< Core clock frequency: 600000000Hz */
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+* @file pin_mux.h
+* @brief define imxrt1052-board pin configure
+* @version 1.0
+* @author AIIT XUOS Lab
+* @date 2021-05-29
+*/
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
+  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
+  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
+#define BOARD_INITPINS_UART1_RXD_PERIPHERAL                              LPUART1   /*!< Device name: LPUART1 */
+#define BOARD_INITPINS_UART1_RXD_SIGNAL                                       RX   /*!< LPUART1 signal: RX */
+
+/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
+#define BOARD_INITPINS_UART1_TXD_PERIPHERAL                              LPUART1   /*!< Device name: LPUART1 */
+#define BOARD_INITPINS_UART1_TXD_SIGNAL                                       TX   /*!< LPUART1 signal: TX */
+
+/* GPIO_AD_B0_09 (coord F14), BSP_LED */
+#define BOARD_INITPINS_BSP_LED_GPIO                                        GPIO1   /*!< GPIO device name: GPIO1 */
+#define BOARD_INITPINS_BSP_LED_PORT                                        GPIO1   /*!< PORT device name: GPIO1 */
+#define BOARD_INITPINS_BSP_LED_PIN                                            9U   /*!< GPIO1 pin index: 9 */
+
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+void BOARD_InitI2C1Pins(void);
+void BOARD_InitSPIPins(void);
+void BOARD_InitUartPins(void);
+void BOARD_InitCh438Pins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/