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modify XiUOS DIR : (1.add plc_demo in APP_Framework/control_app; 2.add industrial_network、industrial_fieldbus and industrial_wlan; 3.add XiZi_AIoT and modify XiZi as XiZi_IIoT.)

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This commit is contained in:
Liu_Weichao
2022-09-27 20:39:52 +08:00
parent dbca22a1a6
commit e14fa6ff8e
5009 changed files with 1019 additions and 3084 deletions
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Ubiquitous/XiZi_IIoT/arch/risc-v/rv32m1-vega/Makefile
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SRC_FILES := startup_RV32M1_ri5cy.S interrupt_gcc.S system_RV32M1_ri5cy.c interrupt.c
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_IIoT/arch/risc-v/rv32m1-vega/RV32M1_ri5cy.h
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Ubiquitous/XiZi_IIoT/arch/risc-v/rv32m1-vega/RV32M1_ri5cy_features.h
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Ubiquitous/XiZi_IIoT/arch/risc-v/rv32m1-vega/RV32M1_zero_riscy.h
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Ubiquitous/XiZi_IIoT/arch/risc-v/rv32m1-vega/RV32M1_zero_riscy_features.h
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Ubiquitous/XiZi_IIoT/arch/risc-v/rv32m1-vega/arch_interrupt.h
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/**
* @file arch_interrupt.h
* @brief support rv32m1-vega interrupt
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-02-16
*/
#ifndef ARCH_INTERRUPT_H__
#define ARCH_INTERRUPT_H__
#include <RV32M1_ri5cy.h>
#define ARCH_MAX_IRQ_NUM NUMBER_OF_INT_VECTORS
#define ARCH_IRQ_NUM_OFFSET 0
int ArchEnableHwIrq(uint32_t irq_num);
int ArchDisableHwIrq(uint32_t irq_num);
#endif
Ubiquitous/XiZi_IIoT/arch/risc-v/rv32m1-vega/core_riscv32.h
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/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/**
* @file core_riscv32.h
* @brief support interrupt
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-02-16
*/
/*************************************************
File name: core_riscv32.h
Description: support gap8 interrupt and startup
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#ifndef __CORE_RISCV32_H__
#define __CORE_RISCV32_H__
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#define RISCV32
#if defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
#if defined ( __GNUC__ )
#define __BKPT(x) __ASM("ebreak")
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("nop");
}
__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("nop");
}
__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
{
}
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("csrsi mstatus, 8");
}
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("csrci mstatus, 8");
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
return __builtin_bswap32(value);
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
return __builtin_bswap16(value);
}
#else
#error Unknown compiler
#endif
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_RISCV32_H__ */
Ubiquitous/XiZi_IIoT/arch/risc-v/rv32m1-vega/fsl_device_registers.h
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/*
* Copyright 2014-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
/**
* @file fsl_device_registers.h
* @brief support fsl device
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-02-16
*/
/*************************************************
File name: fsl_device_registers.h
Description: support fsl device
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#ifndef __FSL_DEVICE_REGISTERS_H__
#define __FSL_DEVICE_REGISTERS_H__
#define CPU_RV32M1_ri5cy
/*
* Include the cpu specific register header files.
*
* The CPU macro should be declared in the project or makefile.
*/
#if defined(CPU_RV32M1_cm0plus)
#define RV32M1_cm0plus_SERIES
/* CMSIS-style register definitions */
#include "RV32M1_cm0plus.h"
/* CPU specific feature definitions */
#include "RV32M1_cm0plus_features.h"
#elif defined(CPU_RV32M1_cm4)
#define RV32M1_cm4_SERIES
/* CMSIS-style register definitions */
#include "RV32M1_cm4.h"
/* CPU specific feature definitions */
#include "RV32M1_cm4_features.h"
#elif defined(CPU_RV32M1_zero_riscy)
#define RV32M1_zero_riscy_SERIES
/* CMSIS-style register definitions */
#include "RV32M1_zero_riscy.h"
/* CPU specific feature definitions */
#include "RV32M1_zero_riscy_features.h"
#elif defined(CPU_RV32M1_ri5cy)
#define RV32M1_ri5cy_SERIES
/* CMSIS-style register definitions */
#include "RV32M1_ri5cy.h"
/* CPU specific feature definitions */
#include "RV32M1_ri5cy_features.h"
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_DEVICE_REGISTERS_H__ */
/*******************************************************************************
* EOF
******************************************************************************/
Ubiquitous/XiZi_IIoT/arch/risc-v/rv32m1-vega/interrupt.c
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/**
* @file interrupt.c
* @brief support interrupt
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-09-02
*/
#include <arch_interrupt.h>
#include <xs_base.h>
#include <xs_isr.h>
#include "fsl_common.h"
#include <RV32M1_ri5cy.h>
int ArchDisableHwIrq(uint32_t irq_num)
{
DisableIRQ(irq_num);
return 0;
}
int ArchEnableHwIrq(uint32_t irq_num)
{
EnableIRQ(irq_num);
return 0;
}
x_base DisableLocalInterrupt(void)
{
__disable_irq();
return 0;
}
/****************************************************************************
* Name: EnableLocalInterrupt
*
* Description:
* Return the current interrupt state and enable interrupts
*
****************************************************************************/
void EnableLocalInterrupt(x_base oldstat)
{
__enable_irq();
}
typedef void (*irq_handler_t)(void);
extern const irq_handler_t isrTable[];
void SystemIrqHandler(uint32_t mcause)
{
uint32_t intNum;
if (mcause & 0x80000000) /* For external interrupt. */
{
intNum = mcause & 0x1FUL;
/* Clear pending flag in EVENT unit .*/
EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum);
/* Now call the real irq handler for intNum */
isrManager.done->incCounter();
isrTable[intNum]();
isrManager.done->decCounter();
}
}
Ubiquitous/XiZi_IIoT/arch/risc-v/rv32m1-vega/interrupt_gcc.S
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/**
* @file interrupt_gcc.S
* @brief support vega interrupt
* @version 1.0
* @author AIIT XUOS Lab
* @date 2022-02-16
*/
#include "boot.h"
.section .text.entry
.align 2
.global IRQ_Handler
IRQ_Handler:
SAVE_X_REGISTERS
mv fp, sp
/* switch to interrupt stack */
# la sp, __stack
/* interrupt handle */
csrr a0, mcause
csrr a1, mepc
mv a2, sp
call SystemIrqHandler
/* switch to from thread stack */
mv sp, fp
mv a0, fp
call KTaskOsAssignAfterIrq
j SwitchKTaskContextExit
Ubiquitous/XiZi_IIoT/arch/risc-v/rv32m1-vega/startup_RV32M1_ri5cy.S
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/* ------------------------------------------------------------------------- */
/* @file: startup_RV32M1_ri5cy.s */
/* @purpose: RI5CY Core Device Startup File */
/* RV32M1_ri5cy */
/* @version: 1.0 */
/* @date: 2018-10-2 */
/* @build: b180926 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2018 NXP */
/* All rights reserved. */
/* */
/* SPDX-License-Identifier: BSD-3-Clause */
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
/*************************************************
File name: startup_RV32M1_ri5cy.s
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
.extern Rv32m1VgeaStart
#define EXCEPTION_STACK_SIZE 0x58
.text
.section .vectors, "ax"
.option norvc;
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
// reset vector
jal x0, Reset_Handler
// Illegal instrution exception
jal x0, IllegalInstruction_Handler
// ecall handler
jal x0, Ecall_Handler
// LSU error
jal x0, LSU_Handler
.section .startup
/* Reset Handler */
Reset_Handler:
# Disable global interrupt. */
csrci mstatus, 8
# initialize stack pointer
la sp, __StackTop
# initialize global pointer
la gp, __global_pointer
#ifndef __NO_SYSTEM_INIT
jal SystemInit
#endif
# call __libc_init_array
# Enable global interrupt. */
# csrsi mstatus, 8
jal Rv32m1VgeaStart
ebreak
.size Reset_Handler, . - Reset_Handler
.global _init
.global _fini
_init:
_fini:
ret
// saves all caller-saved registers (except return address)
store_regs:
sw x3, 0x00(x2) // gp
sw x4, 0x04(x2) // tp
sw x5, 0x08(x2) // t0
sw x6, 0x0c(x2) // t1
sw x7, 0x10(x2) // t2
sw x10, 0x14(x2) // a0
sw x11, 0x18(x2) // a1
sw x12, 0x1c(x2) // a2
sw x13, 0x20(x2) // a3
sw x14, 0x24(x2) // a4
sw x15, 0x28(x2) // a5
sw x16, 0x2c(x2) // a6
sw x17, 0x30(x2) // a7
csrr a0, 0x7B0
csrr a1, 0x7B1
csrr a2, 0x7B2
sw a0, 0x34(x2) // lpstart[0]
sw a1, 0x38(x2) // lpend[0]
sw a2, 0x3c(x2) // lpcount[0]
csrr a0, 0x7B4
csrr a1, 0x7B5
csrr a2, 0x7B6
sw a0, 0x40(x2) // lpstart[1]
sw a1, 0x44(x2) // lpend[1]
sw a2, 0x48(x2) // lpcount[1]
csrr a0, 0x341
sw a0, 0x4c(x2) // mepc
csrr a1, 0x300
sw a1, 0x50(x2) // mstatus
jalr x0, x1
// load back registers from stack
end_except:
lw a1, 0x50(x2) // mstatus
csrrw x0, 0x300, a1
lw a0, 0x4c(x2) // mepc
csrrw x0, 0x341, a0
lw a0, 0x40(x2) // lpstart[1]
lw a1, 0x44(x2) // lpend[1]
lw a2, 0x48(x2) // lpcount[1]
csrrw x0, 0x7B4, a0
csrrw x0, 0x7B5, a1
csrrw x0, 0x7B6, a2
lw a0, 0x34(x2) // lpstart[0]
lw a1, 0x38(x2) // lpend[0]
lw a2, 0x3c(x2) // lpcount[0]
csrrw x0, 0x7B0, a0
csrrw x0, 0x7B1, a1
csrrw x0, 0x7B2, a2
lw x3, 0x00(x2) // gp
lw x4, 0x04(x2) // tp
lw x5, 0x08(x2) // t0
lw x6, 0x0c(x2) // t1
lw x7, 0x10(x2) // t2
lw x10, 0x14(x2) // a0
lw x11, 0x18(x2) // a1
lw x12, 0x1c(x2) // a2
lw x13, 0x20(x2) // a3
lw x14, 0x24(x2) // a4
lw x15, 0x28(x2) // a5
lw x16, 0x2c(x2) // a6
lw x17, 0x30(x2) // a7
lw x1, 0x54(x2)
addi x2, x2, EXCEPTION_STACK_SIZE
mret
.weak IRQ_Handler
.type IRQ_Handler, %function
IRQ_Handler:
addi x2, x2, -EXCEPTION_STACK_SIZE
sw x1, 0x54(x2)
jal x1, store_regs
la x1, end_except
csrr a0, mcause
jal x0, SystemIrqHandler
.size IRQ_Handler, . - IRQ_Handler
.macro define_exception_entry entry_name handler_name
.weak \entry_name
\entry_name:
addi x2, x2, -EXCEPTION_STACK_SIZE
sw x1, 0x54(x2)
jal x1, store_regs
la x1, end_except
jal x0, \handler_name
.endm
define_exception_entry IllegalInstruction_Handler IllegalInstruction_HandlerFunc
define_exception_entry Ecall_Handler Ecall_HandlerFunc
define_exception_entry LSU_Handler LSU_HandlerFunc
.weak IllegalInstruction_HandlerFunc
.type IllegalInstruction_HandlerFunc, %function
IllegalInstruction_HandlerFunc:
j .
.size IllegalInstruction_HandlerFunc, . - IllegalInstruction_HandlerFunc
.weak Ecall_HandlerFunc
.type Ecall_HandlerFunc, %function
Ecall_HandlerFunc:
j .
.size Ecall_HandlerFunc, . - Ecall_HandlerFunc
.weak LSU_HandlerFunc
.type LSU_HandlerFunc, %function
LSU_HandlerFunc:
j .
.size LSU_HandlerFunc, . - LSU_HandlerFunc
Ubiquitous/XiZi_IIoT/arch/risc-v/rv32m1-vega/startup_RV32M1_zero_riscy.S
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/* ------------------------------------------------------------------------- */
/* @file: startup_RV32M1_zero_riscy.s */
/* @purpose: ZERO_RISCY Core Device Startup File */
/* RV32M1_zero_riscy */
/* @version: 1.0 */
/* @date: 2018-10-2 */
/* @build: b180926 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2018 NXP */
/* All rights reserved. */
/* */
/* SPDX-License-Identifier: BSD-3-Clause */
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
/*************************************************
File name: startup_RV32M1_zero_ri5cy.s
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
.extern Rv32m1VgeaStart
#define EXCEPTION_STACK_SIZE 0x58
.text
.section .vectors, "ax"
.option norvc;
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
// reset vector
jal x0, Reset_Handler
// Illegal instrution exception
jal x0, IllegalInstruction_Handler
// ecall handler
jal x0, Ecall_Handler
// LSU error
jal x0, LSU_Handler
.section .startup
/* Reset Handler */
Reset_Handler:
# Disable global interrupt. */
csrci mstatus, 8
# initialize stack pointer
la sp, __StackTop
# initialize global pointer
la gp, __global_pointer
#ifndef __NO_SYSTEM_INIT
jal SystemInit
#endif
call __libc_init_array
# Enable global interrupt. */
csrsi mstatus, 8
jal Rv32m1VgeaStart
ebreak
.size Reset_Handler, . - Reset_Handler
.global _init
.global _fini
_init:
_fini:
ret
// saves all caller-saved registers (except return address)
store_regs:
sw x3, 0x00(x2) // gp
sw x4, 0x04(x2) // tp
sw x5, 0x08(x2) // t0
sw x6, 0x0c(x2) // t1
sw x7, 0x10(x2) // t2
sw x10, 0x14(x2) // a0
sw x11, 0x18(x2) // a1
sw x12, 0x1c(x2) // a2
sw x13, 0x20(x2) // a3
sw x14, 0x24(x2) // a4
sw x15, 0x28(x2) // a5
sw x16, 0x2c(x2) // a6
sw x17, 0x30(x2) // a7
csrr a0, 0x7B0
csrr a1, 0x7B1
csrr a2, 0x7B2
sw a0, 0x34(x2) // lpstart[0]
sw a1, 0x38(x2) // lpend[0]
sw a2, 0x3c(x2) // lpcount[0]
csrr a0, 0x7B4
csrr a1, 0x7B5
csrr a2, 0x7B6
sw a0, 0x40(x2) // lpstart[1]
sw a1, 0x44(x2) // lpend[1]
sw a2, 0x48(x2) // lpcount[1]
csrr a0, 0x341
sw a0, 0x4c(x2) // mepc
csrr a1, 0x300
sw a1, 0x50(x2) // mstatus
jalr x0, x1
// load back registers from stack
end_except:
lw a1, 0x50(x2) // mstatus
csrrw x0, 0x300, a1
lw a0, 0x4c(x2) // mepc
csrrw x0, 0x341, a0
lw a0, 0x40(x2) // lpstart[1]
lw a1, 0x44(x2) // lpend[1]
lw a2, 0x48(x2) // lpcount[1]
csrrw x0, 0x7B4, a0
csrrw x0, 0x7B5, a1
csrrw x0, 0x7B6, a2
lw a0, 0x34(x2) // lpstart[0]
lw a1, 0x38(x2) // lpend[0]
lw a2, 0x3c(x2) // lpcount[0]
csrrw x0, 0x7B0, a0
csrrw x0, 0x7B1, a1
csrrw x0, 0x7B2, a2
lw x3, 0x00(x2) // gp
lw x4, 0x04(x2) // tp
lw x5, 0x08(x2) // t0
lw x6, 0x0c(x2) // t1
lw x7, 0x10(x2) // t2
lw x10, 0x14(x2) // a0
lw x11, 0x18(x2) // a1
lw x12, 0x1c(x2) // a2
lw x13, 0x20(x2) // a3
lw x14, 0x24(x2) // a4
lw x15, 0x28(x2) // a5
lw x16, 0x2c(x2) // a6
lw x17, 0x30(x2) // a7
lw x1, 0x54(x2)
addi x2, x2, EXCEPTION_STACK_SIZE
mret
.weak IRQ_Handler
.type IRQ_Handler, %function
IRQ_Handler:
addi x2, x2, -EXCEPTION_STACK_SIZE
sw x1, 0x54(x2)
jal x1, store_regs
la x1, end_except
csrr a0, mcause
jal x0, SystemIrqHandler
.size IRQ_Handler, . - IRQ_Handler
.macro define_exception_entry entry_name handler_name
.weak \entry_name
\entry_name:
addi x2, x2, -EXCEPTION_STACK_SIZE
sw x1, 0x54(x2)
jal x1, store_regs
la x1, end_except
jal x0, \handler_name
.endm
define_exception_entry IllegalInstruction_Handler IllegalInstruction_HandlerFunc
define_exception_entry Ecall_Handler Ecall_HandlerFunc
define_exception_entry LSU_Handler LSU_HandlerFunc
.weak IllegalInstruction_HandlerFunc
.type IllegalInstruction_HandlerFunc, %function
IllegalInstruction_HandlerFunc:
j .
.size IllegalInstruction_HandlerFunc, . - IllegalInstruction_HandlerFunc
.weak Ecall_HandlerFunc
.type Ecall_HandlerFunc, %function
Ecall_HandlerFunc:
j .
.size Ecall_HandlerFunc, . - Ecall_HandlerFunc
.weak LSU_HandlerFunc
.type LSU_HandlerFunc, %function
LSU_HandlerFunc:
j .
.size LSU_HandlerFunc, . - LSU_HandlerFunc
Ubiquitous/XiZi_IIoT/arch/risc-v/rv32m1-vega/system_RV32M1_ri5cy.c
+567
View File
@@ -0,0 +1,567 @@
/*
** ###################################################################
** Processors: RV32M1_ri5cy
** RV32M1_ri5cy
**
** Compilers: Keil ARM C/C++ Compiler
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** MCUXpresso Compiler
**
** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
** Version: rev. 1.0, 2018-10-02
** Build: b180926
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2018-10-02)
** Initial version.
**
** ###################################################################
*/
/*!
* @file RV32M1_ri5cy
* @version 1.0
* @date 2018-10-02
* @brief Device specific configuration file for RV32M1_ri5cy
* (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
/*************************************************
File name: RV32M1_ri5cy
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#include <stdint.h>
#include "fsl_device_registers.h"
#include "fsl_common.h"
typedef void (*irq_handler_t)(void);
extern void DMA0_0_4_8_12_DriverIRQHandler(void);
extern void DMA0_1_5_9_13_DriverIRQHandler(void);
extern void DMA0_2_6_10_14_DriverIRQHandler(void);
extern void DMA0_3_7_11_15_DriverIRQHandler(void);
extern void DMA0_Error_IRQHandler(void);
extern void CMC0_IRQHandler(void);
extern void EWM_IRQHandler(void);
extern void FTFE_Command_Complete_IRQHandler(void);
extern void FTFE_Read_Collision_IRQHandler(void);
extern void LLWU0_IRQHandler(void);
extern void MUA_IRQHandler(void);
extern void SPM_IRQHandler(void);
extern void WDOG0_IRQHandler(void);
extern void SCG_IRQHandler(void);
extern void LPIT0_IRQHandler(void);
extern void RTC_IRQHandler(void);
extern void LPTMR0_IRQHandler(void);
extern void LPTMR1_IRQHandler(void);
extern void TPM0_IRQHandler(void);
extern void TPM1_IRQHandler(void);
extern void TPM2_IRQHandler(void);
extern void EMVSIM0_IRQHandler(void);
extern void FLEXIO0_DriverIRQHandler(void);
extern void LPI2C0_DriverIRQHandler(void);
extern void LPI2C1_DriverIRQHandler(void);
extern void LPI2C2_DriverIRQHandler(void);
extern void I2S0_DriverIRQHandler(void);
extern void USDHC0_DriverIRQHandler(void);
extern void LPSPI0_DriverIRQHandler(void);
extern void LPSPI1_DriverIRQHandler(void);
extern void LPSPI2_DriverIRQHandler(void);
extern void LPUART0_DriverIRQHandler(void);
extern void LPUART1_DriverIRQHandler(void);
extern void LPUART2_DriverIRQHandler(void);
extern void USB0_IRQHandler(void);
extern void PORTA_IRQHandler(void);
extern void PORTB_IRQHandler(void);
extern void PORTC_IRQHandler(void);
extern void PORTD_IRQHandler(void);
extern void ADC0_IRQHandler(void);
extern void LPCMP0_IRQHandler(void);
extern void LPDAC0_IRQHandler(void);
extern void CAU3_Task_Complete_IRQHandler(void);
extern void CAU3_Security_Violation_IRQHandler(void);
extern void TRNG_IRQHandler(void);
extern void LPIT1_IRQHandler(void);
extern void LPTMR2_IRQHandler(void);
extern void TPM3_IRQHandler(void);
extern void LPI2C3_DriverIRQHandler(void);
extern void LPSPI3_DriverIRQHandler(void);
extern void LPUART3_DriverIRQHandler(void);
extern void PORTE_IRQHandler(void);
extern void LPCMP1_IRQHandler(void);
extern void RF0_0_IRQHandler(void);
extern void RF0_1_IRQHandler(void);
extern void INTMUX0_0_DriverIRQHandler(void);
extern void INTMUX0_1_DriverIRQHandler(void);
extern void INTMUX0_2_DriverIRQHandler(void);
extern void INTMUX0_3_DriverIRQHandler(void);
extern void INTMUX0_4_DriverIRQHandler(void);
extern void INTMUX0_5_DriverIRQHandler(void);
extern void INTMUX0_6_DriverIRQHandler(void);
extern void INTMUX0_7_DriverIRQHandler(void);
extern void INTMUX0_8_DriverIRQHandler(void);
extern void DMA0_0_4_8_12_IRQHandler(void);
extern void DMA0_1_5_9_13_IRQHandler(void);
extern void DMA0_2_6_10_14_IRQHandler(void);
extern void DMA0_3_7_11_15_IRQHandler(void);
extern void FLEXIO0_IRQHandler(void);
extern void LPI2C0_IRQHandler(void);
extern void LPI2C1_IRQHandler(void);
extern void LPI2C2_IRQHandler(void);
extern void I2S0_IRQHandler(void);
extern void USDHC0_IRQHandler(void);
extern void LPSPI0_IRQHandler(void);
extern void LPSPI1_IRQHandler(void);
extern void LPSPI2_IRQHandler(void);
extern void LPUART0_IRQHandler(void);
extern void LPUART1_IRQHandler(void);
extern void LPUART2_IRQHandler(void);
extern void LPI2C3_IRQHandler(void);
extern void LPSPI3_IRQHandler(void);
extern void LPUART3_IRQHandler(void);
extern void INTMUX0_0_IRQHandler(void);
extern void INTMUX0_1_IRQHandler(void);
extern void INTMUX0_2_IRQHandler(void);
extern void INTMUX0_3_IRQHandler(void);
extern void INTMUX0_4_IRQHandler(void);
extern void INTMUX0_5_IRQHandler(void);
extern void INTMUX0_6_IRQHandler(void);
extern void INTMUX0_7_IRQHandler(void);
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
extern uint32_t __etext;
extern uint32_t __data_start__;
extern uint32_t __data_end__;
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end)
{
while(p_vma <= p_vma_end)
{
*p_vma = *p_load;
++p_load;
++p_vma;
}
}
static void zero_section(uint32_t * start, uint32_t * end)
{
uint32_t * p_zero = start;
while(p_zero <= end)
{
*p_zero = 0;
++p_zero;
}
}
#define DEFINE_IRQ_HANDLER(irq_handler, driver_irq_handler) \
void __attribute__((weak)) irq_handler(void) { driver_irq_handler();}
#define DEFINE_DEFAULT_IRQ_HANDLER(irq_handler) void irq_handler() __attribute__((weak, alias("DefaultIRQHandler")))
DEFINE_DEFAULT_IRQ_HANDLER(DMA0_0_4_8_12_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(DMA0_1_5_9_13_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(DMA0_2_6_10_14_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(DMA0_3_7_11_15_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(DMA0_Error_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(CMC0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(EWM_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Command_Complete_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Read_Collision_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LLWU0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(MUA_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(SPM_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(WDOG0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(SCG_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPIT0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(RTC_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPTMR0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPTMR1_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(TPM0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(TPM1_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(TPM2_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(EMVSIM0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(FLEXIO0_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPI2C0_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPI2C1_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPI2C2_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(I2S0_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(USDHC0_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPSPI0_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPSPI1_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPSPI2_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPUART0_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPUART1_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPUART2_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(USB0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(PORTA_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(PORTB_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(PORTC_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(PORTD_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(ADC0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPCMP0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPDAC0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Task_Complete_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Security_Violation_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(TRNG_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPIT1_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPTMR2_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(TPM3_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPI2C3_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPSPI3_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPUART3_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(PORTE_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPCMP1_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(RF0_0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(RF0_1_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_0_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_1_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_2_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_3_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_4_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_5_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_6_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_7_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_8_DriverIRQHandler);
DEFINE_IRQ_HANDLER(DMA0_0_4_8_12_IRQHandler, DMA0_0_4_8_12_DriverIRQHandler);
DEFINE_IRQ_HANDLER(DMA0_1_5_9_13_IRQHandler, DMA0_1_5_9_13_DriverIRQHandler);
DEFINE_IRQ_HANDLER(DMA0_2_6_10_14_IRQHandler, DMA0_2_6_10_14_DriverIRQHandler);
DEFINE_IRQ_HANDLER(DMA0_3_7_11_15_IRQHandler, DMA0_3_7_11_15_DriverIRQHandler);
DEFINE_IRQ_HANDLER(FLEXIO0_IRQHandler, FLEXIO0_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPI2C0_IRQHandler, LPI2C0_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPI2C1_IRQHandler, LPI2C1_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPI2C2_IRQHandler, LPI2C2_DriverIRQHandler);
DEFINE_IRQ_HANDLER(I2S0_IRQHandler, I2S0_DriverIRQHandler);
DEFINE_IRQ_HANDLER(USDHC0_IRQHandler, USDHC0_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPSPI0_IRQHandler, LPSPI0_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPSPI1_IRQHandler, LPSPI1_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPSPI2_IRQHandler, LPSPI2_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPUART0_IRQHandler, LPUART0_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPUART1_IRQHandler, LPUART1_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPUART2_IRQHandler, LPUART2_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPI2C3_IRQHandler, LPI2C3_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPSPI3_IRQHandler, LPSPI3_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPUART3_IRQHandler, LPUART3_DriverIRQHandler);
DEFINE_IRQ_HANDLER(INTMUX0_0_IRQHandler, INTMUX0_0_DriverIRQHandler);
DEFINE_IRQ_HANDLER(INTMUX0_1_IRQHandler, INTMUX0_1_DriverIRQHandler);
DEFINE_IRQ_HANDLER(INTMUX0_2_IRQHandler, INTMUX0_2_DriverIRQHandler);
DEFINE_IRQ_HANDLER(INTMUX0_3_IRQHandler, INTMUX0_3_DriverIRQHandler);
DEFINE_IRQ_HANDLER(INTMUX0_4_IRQHandler, INTMUX0_4_DriverIRQHandler);
DEFINE_IRQ_HANDLER(INTMUX0_5_IRQHandler, INTMUX0_5_DriverIRQHandler);
DEFINE_IRQ_HANDLER(INTMUX0_6_IRQHandler, INTMUX0_6_DriverIRQHandler);
DEFINE_IRQ_HANDLER(INTMUX0_7_IRQHandler, INTMUX0_7_DriverIRQHandler);
__attribute__((section("user_vectors"))) const irq_handler_t isrTable[] =
{
DMA0_0_4_8_12_IRQHandler,
DMA0_1_5_9_13_IRQHandler,
DMA0_2_6_10_14_IRQHandler,
DMA0_3_7_11_15_IRQHandler,
DMA0_Error_IRQHandler,
CMC0_IRQHandler,
MUA_IRQHandler,
USB0_IRQHandler,
USDHC0_IRQHandler,
I2S0_IRQHandler,
FLEXIO0_IRQHandler,
EMVSIM0_IRQHandler,
LPIT0_IRQHandler,
LPSPI0_IRQHandler,
LPSPI1_IRQHandler,
LPI2C0_IRQHandler,
LPI2C1_IRQHandler,
LPUART0_IRQHandler,
PORTA_IRQHandler,
TPM0_IRQHandler,
LPDAC0_IRQHandler,
ADC0_IRQHandler,
LPCMP0_IRQHandler,
RTC_IRQHandler,
INTMUX0_0_IRQHandler,
INTMUX0_1_IRQHandler,
INTMUX0_2_IRQHandler,
INTMUX0_3_IRQHandler,
INTMUX0_4_IRQHandler,
INTMUX0_5_IRQHandler,
INTMUX0_6_IRQHandler,
INTMUX0_7_IRQHandler,
EWM_IRQHandler,
FTFE_Command_Complete_IRQHandler,
FTFE_Read_Collision_IRQHandler,
LLWU0_IRQHandler,
SPM_IRQHandler,
WDOG0_IRQHandler,
SCG_IRQHandler,
LPTMR0_IRQHandler,
LPTMR1_IRQHandler,
TPM1_IRQHandler,
TPM2_IRQHandler,
LPI2C2_IRQHandler,
LPSPI2_IRQHandler,
LPUART1_IRQHandler,
LPUART2_IRQHandler,
PORTB_IRQHandler,
PORTC_IRQHandler,
PORTD_IRQHandler,
CAU3_Task_Complete_IRQHandler,
CAU3_Security_Violation_IRQHandler,
TRNG_IRQHandler,
LPIT1_IRQHandler,
LPTMR2_IRQHandler,
TPM3_IRQHandler,
LPI2C3_IRQHandler,
LPSPI3_IRQHandler,
LPUART3_IRQHandler,
PORTE_IRQHandler,
LPCMP1_IRQHandler,
RF0_0_IRQHandler,
RF0_1_IRQHandler,
};
extern uint32_t __VECTOR_TABLE[];
static uint32_t irqNesting = 0;
static void DefaultIRQHandler(void)
{
for (;;)
{
}
}
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) {
#if (DISABLE_WDOG)
WDOG0->CNT = 0xD928C520U;
WDOG0->TOVAL = 0xFFFF;
WDOG0->CS = (uint32_t) ((WDOG0->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
#endif /* (DISABLE_WDOG) */
SystemInitHook();
copy_section(&__etext, &__data_start__, &__data_end__);
zero_section(&__bss_start__, &__bss_end__);
/* Setup the vector table address. */
irqNesting = 0;
__ASM volatile("csrw 0x305, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* MTVEC */
__ASM volatile("csrw 0x005, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* UTVEC */
/* Clear all pending flags. */
EVENT_UNIT->INTPTPENDCLEAR = 0xFFFFFFFF;
EVENT_UNIT->EVTPENDCLEAR = 0xFFFFFFFF;
/* Set all interrupt as secure interrupt. */
EVENT_UNIT->INTPTSECURE = 0xFFFFFFFF;
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t SCGOUTClock; /* Variable to store output clock frequency of the SCG module */
uint16_t Divider;
Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1;
switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
case 0x1:
/* System OSC */
SCGOUTClock = CPU_XTAL_CLK_HZ;
break;
case 0x2:
/* Slow IRC */
SCGOUTClock = (((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) ? 8000000 : 2000000);
break;
case 0x3:
/* Fast IRC */
SCGOUTClock = 48000000 + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000;
break;
case 0x5:
/* Low Power FLL */
SCGOUTClock = 48000000 + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000;
break;
default:
return;
}
SystemCoreClock = (SCGOUTClock / Divider);
}
/* ----------------------------------------------------------------------------
-- SystemInitHook()
---------------------------------------------------------------------------- */
__attribute__ ((weak)) void SystemInitHook (void) {
/* Void implementation of the weak function. */
}
#if defined(__IAR_SYSTEMS_ICC__)
#pragma weak SystemIrqHandler
void SystemIrqHandler(uint32_t mcause) {
#elif defined(__GNUC__)
__attribute__((weak)) void SystemIrqHandler(uint32_t mcause) {
#else
#error Not supported compiler type
#endif
uint32_t intNum;
if (mcause & 0x80000000) /* For external interrupt. */
{
intNum = mcause & 0x1FUL;
irqNesting++;
/* Clear pending flag in EVENT unit .*/
EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum);
/* Read back to make sure write finished. */
(void)(EVENT_UNIT->INTPTPENDCLEAR);
__enable_irq(); /* Support nesting interrupt */
/* Now call the real irq handler for intNum */
isrTable[intNum]();
__disable_irq();
irqNesting--;
}
}
/* Use LIPT0 channel 0 for systick. */
#define SYSTICK_LPIT LPIT0
#define SYSTICK_LPIT_CH 0
#define SYSTICK_LPIT_IRQn LPIT0_IRQn
/* Leverage LPIT0 to provide Systick */
void SystemSetupSystick(uint32_t tickRateHz, uint32_t intPriority)
{
/* Init pit module */
CLOCK_EnableClock(kCLOCK_Lpit0);
/* Reset the timer channels and registers except the MCR register */
SYSTICK_LPIT->MCR |= LPIT_MCR_SW_RST_MASK;
SYSTICK_LPIT->MCR &= ~LPIT_MCR_SW_RST_MASK;
/* Setup timer operation in debug and doze modes and enable the module */
SYSTICK_LPIT->MCR = LPIT_MCR_DBG_EN_MASK | LPIT_MCR_DOZE_EN_MASK | LPIT_MCR_M_CEN_MASK;
/* Set timer period for channel 0 */
SYSTICK_LPIT->CHANNEL[SYSTICK_LPIT_CH].TVAL = (CLOCK_GetIpFreq(kCLOCK_Lpit0) / tickRateHz) - 1;
/* Enable timer interrupts for channel 0 */
SYSTICK_LPIT->MIER |= (1U << SYSTICK_LPIT_CH);
/* Set interrupt priority. */
EVENT_SetIRQPriority(SYSTICK_LPIT_IRQn, intPriority);
/* Enable interrupt at the EVENT unit */
EnableIRQ(SYSTICK_LPIT_IRQn);
/* Start channel 0 */
SYSTICK_LPIT->SETTEN |= (LPIT_SETTEN_SET_T_EN_0_MASK << SYSTICK_LPIT_CH);
}
uint32_t SystemGetIRQNestingLevel(void)
{
return irqNesting;
}
void SystemClearSystickFlag(void)
{
/* Channel 0. */
SYSTICK_LPIT->MSR = (1U << SYSTICK_LPIT_CH);
}
void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority)
{
uint8_t regIdx;
uint8_t regOffset;
if ((IRQn < 32) && (intPriority < 8))
{
/*
* 4 priority control registers, each register controls 8 interrupts.
* Bit 0-2: interrupt 0
* Bit 4-7: interrupt 1
* ...
* Bit 28-30: interrupt 7
*/
regIdx = IRQn >> 3U;
regOffset = (IRQn & 0x07U) * 4U;
EVENT_UNIT->INTPTPRI[regIdx] = (EVENT_UNIT->INTPTPRI[regIdx] & ~(0x0F << regOffset)) | (intPriority << regOffset);
}
}
uint8_t EVENT_GetIRQPriority(IRQn_Type IRQn)
{
uint8_t regIdx;
uint8_t regOffset;
int32_t intPriority;
if ((IRQn < 32))
{
/*
* 4 priority control registers, each register controls 8 interrupts.
* Bit 0-2: interrupt 0
* Bit 4-7: interrupt 1
* ...
* Bit 28-30: interrupt 7
*/
regIdx = IRQn >> 3U;
regOffset = (IRQn & 0x07U) << 2U;
intPriority = (EVENT_UNIT->INTPTPRI[regIdx] >> regOffset) & 0xF;
return (uint8_t)intPriority;
}
return 0;
}
bool SystemInISR(void)
{
return ((EVENT_UNIT->INTPTENACTIVE) != 0);;
}
void EVENT_SystemReset(void)
{
EVENT_UNIT->SLPCTRL |= EVENT_SLPCTRL_SYSRSTREQST_MASK;
}
Ubiquitous/XiZi_IIoT/arch/risc-v/rv32m1-vega/system_RV32M1_ri5cy.h
+191
View File
@@ -0,0 +1,191 @@
/*
** ###################################################################
** Processors: RV32M1_ri5cy
** RV32M1_ri5cy
**
** Compilers: Keil ARM C/C++ Compiler
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** MCUXpresso Compiler
**
** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
** Version: rev. 1.0, 2018-10-02
** Build: b180926
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2018-10-02)
** Initial version.
**
** ###################################################################
*/
/*!
* @file RV32M1_ri5cy
* @version 1.0
* @date 2018-10-02
* @brief Device specific configuration file for RV32M1_ri5cy (header file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
/*************************************************
File name: RV32M1_ri5cy
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#ifndef _SYSTEM_RV32M1_ri5cy_H_
#define _SYSTEM_RV32M1_ri5cy_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#ifndef DISABLE_WDOG
#define DISABLE_WDOG 1
#endif
/* Define clock source values */
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
/* Low power mode enable */
/* SMC_PMPROT: AHSRUN=1, AVLP=1,ALLS=1,AVLLS=0x3 */
#define SYSTEM_SMC_PMPROT_VALUE 0xABu /* SMC_PMPROT */
#define SYSTEM_SMC_PMCTRL_VALUE 0x0u /* SMC_PMCTRL */
#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
/**
* @brief SystemInit function hook.
*
* This weak function allows to call specific initialization code during the
* SystemInit() execution.This can be used when an application specific code needs
* to be called as close to the reset entry as possible (for example the Multicore
* Manager MCMGR_EarlyInit() function call).
* NOTE: No global r/w variables can be used in this hook function because the
* initialization of these variables happens after this function.
*/
void SystemInitHook (void);
/**
* @brief System IRQ handler which dispatches specific IRQ to corresponding registered handler.
*
* It is called from IRQ exception context and dispatches to registered handler according to
* MCAUSE interrupt number.
*
* @param mcause IRQ acknowledge value read from MCAUSE
*/
void SystemIrqHandler(uint32_t mcause);
/**
* @brief Get IRQ nesting level of current context.
*
* If the return value is 0, then the context is not ISR, otherwise the context is ISR.
*
* @return IRQ nesting level
*/
uint32_t SystemGetIRQNestingLevel (void);
/**
* @brief Setup systick for RTOS system.
*
* @param tickRateHz Tick number per second
* @param intPriority IRQ interrupt priority (the smaller, the higher priority)
*/
void SystemSetupSystick (uint32_t tickRateHz, uint32_t intPriority);
/**
* @brief Clear systick flag status so that next tick interrupt may occur.
*/
void SystemClearSystickFlag (void);
/**
* @brief Sysem is in ISR or not.
*/
bool SystemInISR(void);
#define SysTick_Handler LPIT0_IRQHandler
/**
* @brief Set interrupt priority in Event unit.
*/
void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority);
/**
* @brief Get interrupt priority in Event unit.
*/
uint8_t EVENT_GetIRQPriority(IRQn_Type IRQn);
/**
* @brief Reset the system.
*/
void EVENT_SystemReset(void);
#define NVIC_SystemReset EVENT_SystemReset
/* Priority setting macro remap. */
#define NVIC_SetPriority EVENT_SetIRQPriority
/* Priority getting macro remap. */
#define NVIC_GetPriority EVENT_GetIRQPriority
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_RV32M1_ri5cy_H_ */
Ubiquitous/XiZi_IIoT/arch/risc-v/rv32m1-vega/system_RV32M1_zero_riscy.c
+546
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@@ -0,0 +1,546 @@
/*
** ###################################################################
** Processors: RV32M1_zero_riscy
** RV32M1_zero_riscy
**
** Compilers: Keil ARM C/C++ Compiler
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** MCUXpresso Compiler
**
** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
** Version: rev. 1.0, 2018-10-02
** Build: b180926
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2018-10-02)
** Initial version.
**
** ###################################################################
*/
/*!
* @file RV32M1_zero_riscy
* @version 1.0
* @date 2018-10-02
* @brief Device specific configuration file for RV32M1_zero_riscy
* (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
/*************************************************
File name: RV32M1_zero_riscy
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#include <stdint.h>
#include "fsl_device_registers.h"
#include "fsl_common.h"
typedef void (*irq_handler_t)(void);
extern void CTI1_IRQHandler(void);
extern void DMA1_04_DriverIRQHandler(void);
extern void DMA1_15_DriverIRQHandler(void);
extern void DMA1_26_DriverIRQHandler(void);
extern void DMA1_37_DriverIRQHandler(void);
extern void DMA1_Error_DriverIRQHandler(void);
extern void CMC1_IRQHandler(void);
extern void LLWU1_IRQHandler(void);
extern void MUB_IRQHandler(void);
extern void WDOG1_IRQHandler(void);
extern void CAU3_Task_Complete_IRQHandler(void);
extern void CAU3_Security_Violation_IRQHandler(void);
extern void TRNG_IRQHandler(void);
extern void LPIT1_IRQHandler(void);
extern void LPTMR2_IRQHandler(void);
extern void TPM3_IRQHandler(void);
extern void LPI2C3_DriverIRQHandler(void);
extern void RF0_0_IRQHandler(void);
extern void RF0_1_IRQHandler(void);
extern void LPSPI3_DriverIRQHandler(void);
extern void LPUART3_DriverIRQHandler(void);
extern void PORTE_IRQHandler(void);
extern void LPCMP1_IRQHandler(void);
extern void RTC_IRQHandler(void);
extern void INTMUX1_0_DriverIRQHandler(void);
extern void INTMUX1_1_DriverIRQHandler(void);
extern void INTMUX1_2_DriverIRQHandler(void);
extern void INTMUX1_3_DriverIRQHandler(void);
extern void INTMUX1_4_DriverIRQHandler(void);
extern void INTMUX1_5_DriverIRQHandler(void);
extern void INTMUX1_6_DriverIRQHandler(void);
extern void INTMUX1_7_DriverIRQHandler(void);
extern void EWM_IRQHandler(void);
extern void FTFE_Command_Complete_IRQHandler(void);
extern void FTFE_Read_Collision_IRQHandler(void);
extern void SPM_IRQHandler(void);
extern void SCG_IRQHandler(void);
extern void LPIT0_IRQHandler(void);
extern void LPTMR0_IRQHandler(void);
extern void LPTMR1_IRQHandler(void);
extern void TPM0_IRQHandler(void);
extern void TPM1_IRQHandler(void);
extern void TPM2_IRQHandler(void);
extern void EMVSIM0_IRQHandler(void);
extern void FLEXIO0_DriverIRQHandler(void);
extern void LPI2C0_DriverIRQHandler(void);
extern void LPI2C1_DriverIRQHandler(void);
extern void LPI2C2_DriverIRQHandler(void);
extern void I2S0_DriverIRQHandler(void);
extern void USDHC0_DriverIRQHandler(void);
extern void LPSPI0_DriverIRQHandler(void);
extern void LPSPI1_DriverIRQHandler(void);
extern void LPSPI2_DriverIRQHandler(void);
extern void LPUART0_DriverIRQHandler(void);
extern void LPUART1_DriverIRQHandler(void);
extern void LPUART2_DriverIRQHandler(void);
extern void USB0_IRQHandler(void);
extern void PORTA_IRQHandler(void);
extern void PORTB_IRQHandler(void);
extern void PORTC_IRQHandler(void);
extern void PORTD_IRQHandler(void);
extern void ADC0_IRQHandler(void);
extern void LPCMP0_IRQHandler(void);
extern void LPDAC0_IRQHandler(void);
extern void DMA1_15_IRQHandler(void);
extern void DMA1_26_IRQHandler(void);
extern void DMA1_37_IRQHandler(void);
extern void DMA1_Error_IRQHandler(void);
extern void LPI2C3_IRQHandler(void);
extern void LPSPI3_IRQHandler(void);
extern void LPUART3_IRQHandler(void);
extern void INTMUX1_0_IRQHandler(void);
extern void INTMUX1_1_IRQHandler(void);
extern void INTMUX1_2_IRQHandler(void);
extern void INTMUX1_3_IRQHandler(void);
extern void INTMUX1_4_IRQHandler(void);
extern void INTMUX1_5_IRQHandler(void);
extern void INTMUX1_6_IRQHandler(void);
extern void INTMUX1_7_IRQHandler(void);
extern void FLEXIO0_IRQHandler(void);
extern void LPI2C0_IRQHandler(void);
extern void LPI2C1_IRQHandler(void);
extern void LPI2C2_IRQHandler(void);
extern void I2S0_IRQHandler(void);
extern void USDHC0_IRQHandler(void);
extern void LPSPI0_IRQHandler(void);
extern void LPSPI1_IRQHandler(void);
extern void LPSPI2_IRQHandler(void);
extern void LPUART0_IRQHandler(void);
extern void LPUART1_IRQHandler(void);
extern void LPUART2_IRQHandler(void);
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
extern uint32_t __etext;
extern uint32_t __data_start__;
extern uint32_t __data_end__;
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end)
{
while(p_vma <= p_vma_end)
{
*p_vma = *p_load;
++p_load;
++p_vma;
}
}
static void zero_section(uint32_t * start, uint32_t * end)
{
uint32_t * p_zero = start;
while(p_zero <= end)
{
*p_zero = 0;
++p_zero;
}
}
#define DEFINE_IRQ_HANDLER(irq_handler, driver_irq_handler) \
void __attribute__((weak)) irq_handler(void) { driver_irq_handler();}
#define DEFINE_DEFAULT_IRQ_HANDLER(irq_handler) void irq_handler() __attribute__((weak, alias("DefaultIRQHandler")))
DEFINE_DEFAULT_IRQ_HANDLER(CTI1_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(DMA1_04_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(DMA1_15_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(DMA1_26_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(DMA1_37_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(DMA1_Error_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(CMC1_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LLWU1_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(MUB_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(WDOG1_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Task_Complete_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Security_Violation_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(TRNG_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPIT1_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPTMR2_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(TPM3_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPI2C3_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(RF0_0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(RF0_1_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPSPI3_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPUART3_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(PORTE_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPCMP1_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(RTC_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_0_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_1_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_2_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_3_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_4_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_5_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_6_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_7_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(EWM_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Command_Complete_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Read_Collision_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(SPM_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(SCG_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPIT0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPTMR0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPTMR1_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(TPM0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(TPM1_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(TPM2_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(EMVSIM0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(FLEXIO0_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPI2C0_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPI2C1_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPI2C2_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(I2S0_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(USDHC0_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPSPI0_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPSPI1_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPSPI2_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPUART0_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPUART1_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPUART2_DriverIRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(USB0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(PORTA_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(PORTB_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(PORTC_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(PORTD_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(ADC0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPCMP0_IRQHandler);
DEFINE_DEFAULT_IRQ_HANDLER(LPDAC0_IRQHandler);
DEFINE_IRQ_HANDLER(DMA1_04_IRQHandler, DMA1_04_DriverIRQHandler);
DEFINE_IRQ_HANDLER(DMA1_15_IRQHandler, DMA1_15_DriverIRQHandler);
DEFINE_IRQ_HANDLER(DMA1_26_IRQHandler, DMA1_26_DriverIRQHandler);
DEFINE_IRQ_HANDLER(DMA1_37_IRQHandler, DMA1_37_DriverIRQHandler);
DEFINE_IRQ_HANDLER(DMA1_Error_IRQHandler, DMA1_Error_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPI2C3_IRQHandler, LPI2C3_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPSPI3_IRQHandler, LPSPI3_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPUART3_IRQHandler, LPUART3_DriverIRQHandler);
DEFINE_IRQ_HANDLER(INTMUX1_0_IRQHandler, INTMUX1_0_DriverIRQHandler);
DEFINE_IRQ_HANDLER(INTMUX1_1_IRQHandler, INTMUX1_1_DriverIRQHandler);
DEFINE_IRQ_HANDLER(INTMUX1_2_IRQHandler, INTMUX1_2_DriverIRQHandler);
DEFINE_IRQ_HANDLER(INTMUX1_3_IRQHandler, INTMUX1_3_DriverIRQHandler);
DEFINE_IRQ_HANDLER(INTMUX1_4_IRQHandler, INTMUX1_4_DriverIRQHandler);
DEFINE_IRQ_HANDLER(INTMUX1_5_IRQHandler, INTMUX1_5_DriverIRQHandler);
DEFINE_IRQ_HANDLER(INTMUX1_6_IRQHandler, INTMUX1_6_DriverIRQHandler);
DEFINE_IRQ_HANDLER(INTMUX1_7_IRQHandler, INTMUX1_7_DriverIRQHandler);
DEFINE_IRQ_HANDLER(FLEXIO0_IRQHandler, FLEXIO0_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPI2C0_IRQHandler, LPI2C0_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPI2C1_IRQHandler, LPI2C1_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPI2C2_IRQHandler, LPI2C2_DriverIRQHandler);
DEFINE_IRQ_HANDLER(I2S0_IRQHandler, I2S0_DriverIRQHandler);
DEFINE_IRQ_HANDLER(USDHC0_IRQHandler, USDHC0_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPSPI0_IRQHandler, LPSPI0_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPSPI1_IRQHandler, LPSPI1_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPSPI2_IRQHandler, LPSPI2_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPUART0_IRQHandler, LPUART0_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPUART1_IRQHandler, LPUART1_DriverIRQHandler);
DEFINE_IRQ_HANDLER(LPUART2_IRQHandler, LPUART2_DriverIRQHandler);
__attribute__((section("user_vectors"))) const irq_handler_t isrTable[] =
{
CTI1_IRQHandler,
DMA1_04_IRQHandler,
DMA1_15_IRQHandler,
DMA1_26_IRQHandler,
DMA1_37_IRQHandler,
DMA1_Error_IRQHandler,
CMC1_IRQHandler,
LLWU1_IRQHandler,
MUB_IRQHandler,
WDOG1_IRQHandler,
CAU3_Task_Complete_IRQHandler,
CAU3_Security_Violation_IRQHandler,
TRNG_IRQHandler,
LPIT1_IRQHandler,
LPTMR2_IRQHandler,
TPM3_IRQHandler,
LPI2C3_IRQHandler,
RF0_0_IRQHandler,
RF0_1_IRQHandler,
LPSPI3_IRQHandler,
LPUART3_IRQHandler,
PORTE_IRQHandler,
LPCMP1_IRQHandler,
RTC_IRQHandler,
INTMUX1_0_IRQHandler,
INTMUX1_1_IRQHandler,
INTMUX1_2_IRQHandler,
INTMUX1_3_IRQHandler,
INTMUX1_4_IRQHandler,
INTMUX1_5_IRQHandler,
INTMUX1_6_IRQHandler,
INTMUX1_7_IRQHandler,
EWM_IRQHandler,
FTFE_Command_Complete_IRQHandler,
FTFE_Read_Collision_IRQHandler,
SPM_IRQHandler,
SCG_IRQHandler,
LPIT0_IRQHandler,
LPTMR0_IRQHandler,
LPTMR1_IRQHandler,
TPM0_IRQHandler,
TPM1_IRQHandler,
TPM2_IRQHandler,
EMVSIM0_IRQHandler,
FLEXIO0_IRQHandler,
LPI2C0_IRQHandler,
LPI2C1_IRQHandler,
LPI2C2_IRQHandler,
I2S0_IRQHandler,
USDHC0_IRQHandler,
LPSPI0_IRQHandler,
LPSPI1_IRQHandler,
LPSPI2_IRQHandler,
LPUART0_IRQHandler,
LPUART1_IRQHandler,
LPUART2_IRQHandler,
USB0_IRQHandler,
PORTA_IRQHandler,
PORTB_IRQHandler,
PORTC_IRQHandler,
PORTD_IRQHandler,
ADC0_IRQHandler,
LPCMP0_IRQHandler,
LPDAC0_IRQHandler,
};
extern uint32_t __VECTOR_TABLE[];
static uint32_t irqNesting = 0;
static void DefaultIRQHandler(void)
{
for (;;)
{
}
}
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) {
#if (DISABLE_WDOG)
WDOG1->CNT = 0xD928C520U;
WDOG1->TOVAL = 0xFFFF;
WDOG1->CS = (uint32_t) ((WDOG1->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
#endif /* (DISABLE_WDOG) */
SystemInitHook();
copy_section(&__etext, &__data_start__, &__data_end__);
zero_section(&__bss_start__, &__bss_end__);
/* Setup the vector table address. */
irqNesting = 0;
__ASM volatile("csrw 0x305, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* MTVEC */
__ASM volatile("csrw 0x005, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* UTVEC */
/* Clear all pending flags. */
EVENT_UNIT->INTPTPENDCLEAR = 0xFFFFFFFF;
EVENT_UNIT->EVTPENDCLEAR = 0xFFFFFFFF;
/* Set all interrupt as secure interrupt. */
EVENT_UNIT->INTPTSECURE = 0xFFFFFFFF;
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t SCGOUTClock; /* Variable to store output clock frequency of the SCG module */
uint16_t Divider;
Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1;
switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
case 0x1:
/* System OSC */
SCGOUTClock = CPU_XTAL_CLK_HZ;
break;
case 0x2:
/* Slow IRC */
SCGOUTClock = (((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) ? 8000000 : 2000000);
break;
case 0x3:
/* Fast IRC */
SCGOUTClock = 48000000 + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000;
break;
case 0x5:
/* Low Power FLL */
SCGOUTClock = 48000000 + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000;
break;
default:
return;
}
SystemCoreClock = (SCGOUTClock / Divider);
}
/* ----------------------------------------------------------------------------
-- SystemInitHook()
---------------------------------------------------------------------------- */
__attribute__ ((weak)) void SystemInitHook (void) {
/* Void implementation of the weak function. */
}
#if defined(__IAR_SYSTEMS_ICC__)
#pragma weak SystemIrqHandler
void SystemIrqHandler(uint32_t mcause) {
#elif defined(__GNUC__)
__attribute__((weak)) void SystemIrqHandler(uint32_t mcause) {
#else
#error Not supported compiler type
#endif
uint32_t intNum;
if (mcause & 0x80000000) /* For external interrupt. */
{
intNum = mcause & 0x1FUL;
irqNesting++;
/* Clear pending flag in EVENT unit .*/
EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum);
/* Read back to make sure write finished. */
(void)(EVENT_UNIT->INTPTPENDCLEAR);
__enable_irq(); /* Support nesting interrupt */
/* Now call the real irq handler for intNum */
isrTable[intNum]();
__disable_irq();
irqNesting--;
}
}
/* Use LIPT1 channel 0 for systick. */
#define SYSTICK_LPIT LPIT1
#define SYSTICK_LPIT_CH 0
#define SYSTICK_LPIT_IRQn LPIT1_IRQn
/* Leverage LPIT0 to provide Systick */
void SystemSetupSystick(uint32_t tickRateHz, uint32_t intPriority)
{
/* Init pit module */
CLOCK_EnableClock(kCLOCK_Lpit1);
/* Reset the timer channels and registers except the MCR register */
SYSTICK_LPIT->MCR |= LPIT_MCR_SW_RST_MASK;
SYSTICK_LPIT->MCR &= ~LPIT_MCR_SW_RST_MASK;
/* Setup timer operation in debug and doze modes and enable the module */
SYSTICK_LPIT->MCR = LPIT_MCR_DBG_EN_MASK | LPIT_MCR_DOZE_EN_MASK | LPIT_MCR_M_CEN_MASK;
/* Set timer period for channel 0 */
SYSTICK_LPIT->CHANNEL[SYSTICK_LPIT_CH].TVAL = (CLOCK_GetIpFreq(kCLOCK_Lpit1) / tickRateHz) - 1;
/* Enable timer interrupts for channel 0 */
SYSTICK_LPIT->MIER |= (1U << SYSTICK_LPIT_CH);
/* Set interrupt priority. */
EVENT_SetIRQPriority(SYSTICK_LPIT_IRQn, intPriority);
/* Enable interrupt at the EVENT unit */
EnableIRQ(SYSTICK_LPIT_IRQn);
/* Start channel 0 */
SYSTICK_LPIT->SETTEN |= (LPIT_SETTEN_SET_T_EN_0_MASK << SYSTICK_LPIT_CH);
}
uint32_t SystemGetIRQNestingLevel(void)
{
return irqNesting;
}
void SystemClearSystickFlag(void)
{
/* Channel 0. */
SYSTICK_LPIT->MSR = (1U << SYSTICK_LPIT_CH);
}
void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority)
{
uint8_t regIdx;
uint8_t regOffset;
if ((IRQn < 32) && (intPriority < 8))
{
/*
* 4 priority control registers, each register controls 8 interrupts.
* Bit 0-2: interrupt 0
* Bit 4-7: interrupt 1
* ...
* Bit 28-30: interrupt 7
*/
regIdx = IRQn >> 3U;
regOffset = (IRQn & 0x07U) * 4U;
EVENT_UNIT->INTPTPRI[regIdx] = (EVENT_UNIT->INTPTPRI[regIdx] & ~(0x0F << regOffset)) | (intPriority << regOffset);
}
}
bool SystemInISR(void)
{
return ((EVENT_UNIT->INTPTENACTIVE) != 0);;
}
void EVENT_SystemReset(void)
{
EVENT_UNIT->SLPCTRL |= EVENT_SLPCTRL_SYSRSTREQST_MASK;
}
Ubiquitous/XiZi_IIoT/arch/risc-v/rv32m1-vega/system_RV32M1_zero_riscy.h
+185
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@@ -0,0 +1,185 @@
/*
** ###################################################################
** Processors: RV32M1_zero_riscy
** RV32M1_zero_riscy
**
** Compilers: Keil ARM C/C++ Compiler
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** MCUXpresso Compiler
**
** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
** Version: rev. 1.0, 2018-10-02
** Build: b180926
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2018-10-02)
** Initial version.
**
** ###################################################################
*/
/*!
* @file RV32M1_zero_riscy
* @version 1.0
* @date 2018-10-02
* @brief Device specific configuration file for RV32M1_zero_riscy (header
* file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
/*************************************************
File name: RV32M1_zero_riscy
Description:
Others: take for references
https://github.com/open-isa-org/open-isa.org
History:
1. Date: 2022-02-16
Author: AIIT XUOS Lab
Modification:
*************************************************/
#ifndef _SYSTEM_RV32M1_zero_riscy_H_
#define _SYSTEM_RV32M1_zero_riscy_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#ifndef DISABLE_WDOG
#define DISABLE_WDOG 1
#endif
/* Define clock source values */
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
/* Low power mode enable */
/* SMC_PMPROT: AHSRUN=1, AVLP=1,ALLS=1,AVLLS=0x3 */
#define SYSTEM_SMC_PMPROT_VALUE 0xABu /* SMC_PMPROT */
#define SYSTEM_SMC_PMCTRL_VALUE 0x0u /* SMC_PMCTRL */
#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
/**
* @brief SystemInit function hook.
*
* This weak function allows to call specific initialization code during the
* SystemInit() execution.This can be used when an application specific code needs
* to be called as close to the reset entry as possible (for example the Multicore
* Manager MCMGR_EarlyInit() function call).
* NOTE: No global r/w variables can be used in this hook function because the
* initialization of these variables happens after this function.
*/
void SystemInitHook (void);
/**
* @brief System IRQ handler which dispatches specific IRQ to corresponding registered handler.
*
* It is called from IRQ exception context and dispatches to registered handler according to
* MCAUSE interrupt number.
*
* @param mcause IRQ acknowledge value read from MCAUSE
*/
void SystemIrqHandler(uint32_t mcause);
/**
* @brief Get IRQ nesting level of current context.
*
* If the return value is 0, then the context is not ISR, otherwise the context is ISR.
*
* @return IRQ nesting level
*/
uint32_t SystemGetIRQNestingLevel (void);
/**
* @brief Setup systick for RTOS system.
*
* @param tickRateHz Tick number per second
* @param intPriority IRQ interrupt priority (the smaller, the higher priority)
*/
void SystemSetupSystick (uint32_t tickRateHz, uint32_t intPriority);
/**
* @brief Clear systick flag status so that next tick interrupt may occur.
*/
void SystemClearSystickFlag (void);
#define SysTick_Handler LPIT1_IRQHandler
/**
* @brief Sysem is in ISR or not.
*/
bool SystemInISR(void);
/**
* @brief Set interrupt priority in Event unit.
*/
void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority);
/* Priority setting macro remap. */
#define NVIC_SetPriority EVENT_SetIRQPriority
/**
* @brief Reset the system.
*/
void EVENT_SystemReset(void);
#define NVIC_SystemReset EVENT_SystemReset
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_RV32M1_zero_riscy_H_ */