diff --git a/APP_Framework/Applications/SConscript b/APP_Framework/Applications/SConscript index f307e3f70..e26d19543 100644 --- a/APP_Framework/Applications/SConscript +++ b/APP_Framework/Applications/SConscript @@ -1,9 +1,15 @@ import os Import('RTT_ROOT') +Import('rtconfig') from building import * cwd = GetCurrentDir() + +SOURCES = ['framework_init.c'] +path = [cwd] objs = [] +group = DefineGroup('sensor', SOURCES, depend = [], CPPPATH = [cwd]) +objs = objs + group list = os.listdir(cwd) for d in list: diff --git a/APP_Framework/Applications/framework_init.c b/APP_Framework/Applications/framework_init.c index d28e95e89..d21aeb7a1 100644 --- a/APP_Framework/Applications/framework_init.c +++ b/APP_Framework/Applications/framework_init.c @@ -11,13 +11,16 @@ */ #include #include -#include +#include extern int SensorFrameworkInit(void); extern int AdapterFrameworkInit(void); extern int Adapter4GInit(void); +extern int AdapterNbiotInit(void); +extern int AdapterBlueToothInit(void); extern int AdapterWifiInit(void); +extern int AdapterZigbeeInit(void); extern int D124VoiceInit(void); extern int Hs300xTemperatureInit(void); @@ -89,10 +92,19 @@ static struct InitDesc sensor_desc[] = static struct InitDesc connection_desc[] = { -#ifdef ADAPTER_4G +#ifdef CONNECTION_ADAPTER_4G { "4G adpter", Adapter4GInit}, #endif -#ifdef ADAPTER_WIFI +#ifdef CONNECTION_ADAPTER_NB + { "NB adpter", AdapterNbiotInit}, +#endif +#ifdef CONNECTION_ADAPTER_ZIGBEE + { "zigbee adpter", AdapterZigbeeInit}, +#endif +#ifdef CONNECTION_ADAPTER_BLUETOOTH + { "BlueTooth adpter", AdapterBlueToothInit}, +#endif +#ifdef CONNECTION_ADAPTER_WIFI { "Wifi adpter", AdapterWifiInit}, #endif { "NULL", NULL }, diff --git a/APP_Framework/Applications/general_functions/list/list.h b/APP_Framework/Applications/general_functions/list/list.h index ebc0c9c17..3eeca2372 100644 --- a/APP_Framework/Applications/general_functions/list/list.h +++ b/APP_Framework/Applications/general_functions/list/list.h @@ -23,7 +23,7 @@ #define __LIST_H__ #include "libc.h" - +#include #ifdef __cplusplus extern "C" { #endif diff --git a/APP_Framework/Applications/knowing_app/Kconfig b/APP_Framework/Applications/knowing_app/Kconfig index 5fa6945be..1387fae5a 100755 --- a/APP_Framework/Applications/knowing_app/Kconfig +++ b/APP_Framework/Applications/knowing_app/Kconfig @@ -9,5 +9,6 @@ menu "knowing app" source "$APP_DIR/Applications/knowing_app/instrusion_detect/Kconfig" source "$APP_DIR/Applications/knowing_app/helmet_detect/Kconfig" source "$APP_DIR/Applications/knowing_app/iris_ml_demo/Kconfig" + source "$APP_DIR/Applications/knowing_app/k210_fft_test/Kconfig" endif endmenu diff --git a/APP_Framework/Applications/knowing_app/face_detect/face_detect.c b/APP_Framework/Applications/knowing_app/face_detect/face_detect.c index 6eca10910..77e4e3efa 100644 --- a/APP_Framework/Applications/knowing_app/face_detect/face_detect.c +++ b/APP_Framework/Applications/knowing_app/face_detect/face_detect.c @@ -7,7 +7,7 @@ #define STACK_SIZE (128 * 1024) #define JSON_FILE_PATH "/kmodel/detect.json" #define JSON_BUFFER_SIZE (4 * 1024) - +static dmac_channel_number_t dma_ch = DMAC_CHANNEL_MAX; // params from json static float anchor[ANCHOR_NUM * 2] = {}; static int net_output_shape[3] = {}; @@ -184,23 +184,23 @@ void face_detect() } _ioctl_set_dvp_reso set_dvp_reso = {sensor_output_size[1], sensor_output_size[0]}; ioctl(g_fd, IOCTRL_CAMERA_SET_DVP_RESO, &set_dvp_reso); - showbuffer = (unsigned char *)malloc(sensor_output_size[0] * sensor_output_size[1] * 2); + showbuffer = (unsigned char *)rt_malloc_align(sensor_output_size[0] * sensor_output_size[1] * 2,64); if (NULL == showbuffer) { close(g_fd); printf("showbuffer apply memory fail !!"); return; } - kpurgbbuffer = (unsigned char *)malloc(net_input_size[0] * net_input_size[1] * 3); + kpurgbbuffer = (unsigned char *)rt_malloc_align(net_input_size[0] * net_input_size[1] * 3,64); if (NULL == kpurgbbuffer) { close(g_fd); - free(showbuffer); + rt_free_align(showbuffer); printf("kpurgbbuffer apply memory fail !!"); return; } model_data = (unsigned char *)malloc(kmodel_size + 255); if (NULL == model_data) { - free(showbuffer); - free(kpurgbbuffer); + rt_free_align(showbuffer); + rt_free_align(kpurgbbuffer); close(g_fd); printf("model_data apply memory fail !!"); return; @@ -296,27 +296,33 @@ static void *thread_face_detcet_entry(void *parameter) pthread_exit(NULL); return NULL; } + if (dmalock_sync_take(&dma_ch, 2000)) + { + printf("Fail to take DMA channel"); + } kpu_run_kmodel(&face_detect_task, kpurgbbuffer, DMAC_CHANNEL5, ai_done, NULL); while (!g_ai_done_flag) ; + dmalock_release(dma_ch); float *output; size_t output_size; kpu_get_output(&face_detect_task, 0, (uint8_t **)&output, &output_size); face_detect_rl.input = output; region_layer_run(&face_detect_rl, &face_detect_info); /* display result */ -#ifdef BSP_USING_LCD + for (int face_cnt = 0; face_cnt < face_detect_info.obj_number; face_cnt++) { draw_edge((uint32_t *)showbuffer, &face_detect_info, face_cnt, 0xF800, (uint16_t)sensor_output_size[1], (uint16_t)sensor_output_size[0]); - printf("%d: (%d, %d, %d, %d) cls: %s conf: %f\t", face_cnt, face_detect_info.obj[face_cnt].x1, - face_detect_info.obj[face_cnt].y1, face_detect_info.obj[face_cnt].x2, face_detect_info.obj[face_cnt].y2, - labels[face_detect_info.obj[face_cnt].class_id], face_detect_info.obj[face_cnt].prob); - } - if (0 != face_detect_info.obj_number) printf("\n"); - lcd_draw_picture(0, 0, (uint16_t)sensor_output_size[1], (uint16_t)sensor_output_size[0], (unsigned int *)showbuffer); + // printf("%d: (%d, %d, %d, %d) cls: %s conf: %f\t", face_cnt, face_detect_info.obj[face_cnt].x1, + // face_detect_info.obj[face_cnt].y1, face_detect_info.obj[face_cnt].x2, face_detect_info.obj[face_cnt].y2, + // labels[face_detect_info.obj[face_cnt].class_id], face_detect_info.obj[face_cnt].prob); + } +#ifdef BSP_USING_LCD + lcd_draw_picture(0, 0, (uint16_t)sensor_output_size[1], (uint16_t)sensor_output_size[0], (uint32_t *)showbuffer); + //lcd_show_image(0, 0, (uint16_t)sensor_output_size[1], (uint16_t)sensor_output_size[0], (unsigned int *)showbuffer); #endif - usleep(1); + usleep(500); if (1 == if_exit) { if_exit = 0; printf("thread_face_detcet_entry exit"); diff --git a/APP_Framework/Applications/knowing_app/instrusion_detect/human.json b/APP_Framework/Applications/knowing_app/instrusion_detect/human.json index 9ef268f5a..feab75aeb 100644 --- a/APP_Framework/Applications/knowing_app/instrusion_detect/human.json +++ b/APP_Framework/Applications/knowing_app/instrusion_detect/human.json @@ -27,7 +27,7 @@ "kmodel_path": "/kmodel/human.kmodel", "kmodel_size": 2713236, "obj_thresh": [ - 0.55 + 0.7 ], "labels": [ "human" diff --git a/APP_Framework/Applications/knowing_app/instrusion_detect/instrusion_detect.c b/APP_Framework/Applications/knowing_app/instrusion_detect/instrusion_detect.c index 5683ec02d..0a48a1841 100644 --- a/APP_Framework/Applications/knowing_app/instrusion_detect/instrusion_detect.c +++ b/APP_Framework/Applications/knowing_app/instrusion_detect/instrusion_detect.c @@ -1,4 +1,5 @@ #include +#include #ifdef LIB_USING_CJSON #include #endif @@ -7,7 +8,9 @@ #define STACK_SIZE (128 * 1024) #define JSON_FILE_PATH "/kmodel/human.json" #define JSON_BUFFER_SIZE (4 * 1024) +static dmac_channel_number_t dma_ch = DMAC_CHANNEL_MAX; +extern void lcd_show_image(int x, int y, int wide, int height,const rt_uint8_t *buf); // params from json static float anchor[ANCHOR_NUM * 2] = {}; static int net_output_shape[3] = {}; @@ -184,23 +187,23 @@ void instrusion_detect() } _ioctl_set_dvp_reso set_dvp_reso = {sensor_output_size[1], sensor_output_size[0]}; ioctl(g_fd, IOCTRL_CAMERA_SET_DVP_RESO, &set_dvp_reso); - showbuffer = (unsigned char *)malloc(sensor_output_size[0] * sensor_output_size[1] * 2); + showbuffer = (unsigned char *)rt_malloc_align(sensor_output_size[0] * sensor_output_size[1] * 2,64); if (NULL == showbuffer) { close(g_fd); printf("showbuffer apply memory fail !!"); return; } - kpurgbbuffer = (unsigned char *)malloc(net_input_size[0] * net_input_size[1] * 3); + kpurgbbuffer = (unsigned char *)rt_malloc_align(net_input_size[0] * net_input_size[1] * 3,64); if (NULL == kpurgbbuffer) { close(g_fd); - free(showbuffer); + rt_free_align(showbuffer); printf("kpurgbbuffer apply memory fail !!"); return; } model_data = (unsigned char *)malloc(kmodel_size + 255); if (NULL == model_data) { - free(showbuffer); - free(kpurgbbuffer); + rt_free_align(showbuffer); + rt_free_align(kpurgbbuffer); close(g_fd); printf("model_data apply memory fail !!"); return; @@ -281,10 +284,12 @@ void instrusion_detect() #ifdef __RT_THREAD_H__ MSH_CMD_EXPORT(instrusion_detect, instrusion detect task); #endif + extern void lcd_draw_picture(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height, uint32_t * ptr); + extern void lcd_show_image(int x, int y, int wide, int height,const rt_uint8_t *buf); + extern void lcd_draw_16_picture(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height, uint32_t * ptr); static void *thread_instrusion_detect_entry(void *parameter) { - extern void lcd_draw_picture(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height, uint32_t * ptr); printf("thread_instrusion_detect_entry start!\n"); int ret = 0; // sysctl_enable_irq(); @@ -299,31 +304,35 @@ static void *thread_instrusion_detect_entry(void *parameter) pthread_exit(NULL); return NULL; } + if (dmalock_sync_take(&dma_ch, 2000)) + { + printf("Fail to take DMA channel"); + } kpu_run_kmodel(&instrusion_detect_task, kpurgbbuffer, DMAC_CHANNEL5, ai_done, NULL); while (!g_ai_done_flag) ; + dmalock_release(dma_ch); float *output; size_t output_size; kpu_get_output(&instrusion_detect_task, 0, (uint8_t **)&output, &output_size); instrusion_detect_rl.input = output; region_layer_run(&instrusion_detect_rl, &instrusion_detect_info); /* display result */ - - for (int instrusion_cnt = 0; instrusion_cnt < instrusion_detect_info.obj_number; instrusion_cnt++) { - // draw_edge((uint32_t *)showbuffer, &instrusion_detect_info, instrusion_cnt, 0xF800, - // (uint16_t)sensor_output_size[1], - // (uint16_t)sensor_output_size[0]); + for (int instrusion_cnt = 0; instrusion_cnt < instrusion_detect_info.obj_number; instrusion_cnt++) + { + draw_edge((uint32_t *)showbuffer, &instrusion_detect_info, instrusion_cnt, 0xF800,(uint16_t)sensor_output_size[1],(uint16_t)sensor_output_size[0]); printf("%d: (%d, %d, %d, %d) cls: %s conf: %f\t", instrusion_cnt, instrusion_detect_info.obj[instrusion_cnt].x1, instrusion_detect_info.obj[instrusion_cnt].y1, instrusion_detect_info.obj[instrusion_cnt].x2, instrusion_detect_info.obj[instrusion_cnt].y2, labels[instrusion_detect_info.obj[instrusion_cnt].class_id], instrusion_detect_info.obj[instrusion_cnt].prob); } +#ifdef BSP_USING_LCD + //lcd_show_image(0, 0,(uint16_t)sensor_output_size[1], (uint16_t)sensor_output_size[0],(unsigned int *)showbuffer); + lcd_draw_picture(0, 0, (uint16_t)sensor_output_size[1], (uint16_t)sensor_output_size[0], (uint32_t *)showbuffer); +#endif if (0 != instrusion_detect_info.obj_number) { printf("\n"); } -#ifdef BSP_USING_LCD - lcd_draw_picture(0, 0, (uint16_t)sensor_output_size[1], (uint16_t)sensor_output_size[0], (unsigned int *)showbuffer); -#endif usleep(1); if (1 == if_exit) { if_exit = 0; diff --git a/APP_Framework/Applications/sensor_app/pm1_0_ps5308.c b/APP_Framework/Applications/sensor_app/pm1_0_ps5308.c index 6ff29ecd4..4f6bda856 100644 --- a/APP_Framework/Applications/sensor_app/pm1_0_ps5308.c +++ b/APP_Framework/Applications/sensor_app/pm1_0_ps5308.c @@ -29,7 +29,7 @@ void Pm10Ps5308(void) { struct SensorQuantity *pm1_0 = SensorQuantityFind(SENSOR_QUANTITY_PS5308_PM1_0, SENSOR_QUANTITY_PM); SensorQuantityOpen(pm1_0); - UserTaskDelay(2000); + PrivTaskDelay(2000); printf("PM1.0 : %d ug/m³\n", SensorQuantityRead(pm1_0)); SensorQuantityClose(pm1_0); } \ No newline at end of file diff --git a/APP_Framework/Applications/sensor_app/voice_d124.c b/APP_Framework/Applications/sensor_app/voice_d124.c index 57bceabdb..b86bf2360 100644 --- a/APP_Framework/Applications/sensor_app/voice_d124.c +++ b/APP_Framework/Applications/sensor_app/voice_d124.c @@ -18,7 +18,7 @@ * @date 2021.04.23 */ -#include +#include #include /** @@ -29,7 +29,7 @@ void VoiceD124(void) { struct SensorQuantity *voice = SensorQuantityFind(SENSOR_QUANTITY_D124_VOICE, SENSOR_QUANTITY_VOICE); SensorQuantityOpen(voice); - UserTaskDelay(2000); + PrivTaskDelay(2000); uint16 result = SensorQuantityRead(voice); printf("voice : %d.%d dB\n", result/(10*voice->value.decimal_places), result%(10*voice->value.decimal_places)); SensorQuantityClose(voice); diff --git a/APP_Framework/Framework/connection/4G/EC200T/Kconfig b/APP_Framework/Framework/connection/4G/EC200T/Kconfig deleted file mode 100644 index a9b0ea2c2..000000000 --- a/APP_Framework/Framework/connection/4G/EC200T/Kconfig +++ /dev/null @@ -1,40 +0,0 @@ -config ADAPTER_4G_EC200T - string "EC200T adapter name" - default "ec200t" - -if ADD_XIUOS_FETURES - config ADAPTER_EC200T_PWRKEY - int "EC200T PWRKEY pin number" - default "97" - - config ADAPTER_EC200T_PIN_DRIVER - string "EC200T device pin driver path" - default "/dev/pin_dev" - - config ADAPTER_EC200T_DRIVER_EXTUART - bool "Using extra uart to support 4G" - default n - - config ADAPTER_EC200T_DRIVER - string "EC200T device uart driver path" - default "/dev/uart2_dev2" - depends on !ADAPTER_EC200T_DRIVER_EXTUART - - if ADAPTER_EC200T_DRIVER_EXTUART - config ADAPTER_EC200T_DRIVER - string "EC200T device extra uart driver path" - default "/dev/extuart_dev5" - - config ADAPTER_EC200T_DRIVER_EXT_PORT - int "if EC200T device using extuart, choose port" - default "5" - endif -endif - -if ADD_NUTTX_FETURES - -endif - -if ADD_RTTHREAD_FETURES - -endif diff --git a/APP_Framework/Framework/connection/4G/EC200T/Makefile b/APP_Framework/Framework/connection/4G/EC200T/Makefile deleted file mode 100644 index 83a948038..000000000 --- a/APP_Framework/Framework/connection/4G/EC200T/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -SRC_FILES := ec200t.c - -include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/4G/EC200T/ec200t.c b/APP_Framework/Framework/connection/4G/EC200T/ec200t.c deleted file mode 100644 index 1ae890b4e..000000000 --- a/APP_Framework/Framework/connection/4G/EC200T/ec200t.c +++ /dev/null @@ -1,270 +0,0 @@ -/* -* Copyright (c) 2020 AIIT XUOS Lab -* XiUOS is licensed under Mulan PSL v2. -* You can use this software according to the terms and conditions of the Mulan PSL v2. -* You may obtain a copy of Mulan PSL v2 at: -* http://license.coscl.org.cn/MulanPSL2 -* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -* See the Mulan PSL v2 for more details. -*/ - -/** - * @file ec200t.c - * @brief Implement the connection 4G adapter function, using EC200T device - * @version 1.1 - * @author AIIT XUOS Lab - * @date 2021.07.08 - */ - -#include -#include - -static void Ec200tPowerSet(void) -{ - int pin_fd; - pin_fd = PrivOpen(ADAPTER_EC200T_PIN_DRIVER, O_RDWR); - - struct PinParam pin_param; - pin_param.cmd = GPIO_CONFIG_MODE; - pin_param.mode = GPIO_CFG_INPUT_PULLUP; - pin_param.pin = ADAPTER_EC200T_PWRKEY; - - struct PrivIoctlCfg ioctl_cfg; - ioctl_cfg.ioctl_driver_type = PIN_TYPE; - ioctl_cfg.args = &pin_param; - PrivIoctl(pin_fd, OPE_CFG, &ioctl_cfg); - - struct PinStat pin_stat; - pin_stat.pin = ADAPTER_EC200T_PWRKEY; - pin_stat.val = GPIO_HIGH; - PrivWrite(pin_fd, &pin_stat, 1); - - PrivTaskDelay(600);//at least 500ms - - pin_stat.val = GPIO_LOW; - PrivWrite(pin_fd, &pin_stat, 1); - - PrivClose(pin_fd); -} - -static int Ec200tOpen(struct Adapter *adapter) -{ - /*step1: open ec200t serial port*/ - adapter->fd = PrivOpen(ADAPTER_EC200T_DRIVER, O_RDWR); - if (adapter->fd < 0) { - printf("Ec200tOpen get serial %s fd error\n", ADAPTER_EC200T_DRIVER); - return -1; - } - - /*step2: init AT agent*/ - if (!adapter->agent) { - char *agent_name = "4G_uart_client"; - if (EOK != InitATAgent(agent_name, adapter->fd, 512)) { - printf("at agent init failed !\n"); - return -1; - } - ATAgentType at_agent = GetATAgent(agent_name); - - adapter->agent = at_agent; - } - - /*step3: serial write "+++", quit transparent mode*/ - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "+++"); - - /*step4: serial write "AT+CCID", get SIM ID*/ - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+CCID\r\n"); - - PrivTaskDelay(2500); - - /*step5: serial write "AT+CPIN?", check SIM status*/ - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+CPIN?\r\n"); - - PrivTaskDelay(2500); - - /*step6: serial write "AT+CREG?", check whether registered to GSM net*/ - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+CREG?\r\n"); - - PrivTaskDelay(2500); - - /*step7: serial write "AT+QICLOSE", close socket connect before open socket*/ - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+QICLOSE=0\r\n"); - - PrivTaskDelay(2500); - - /*step8: serial write "AT+QIDEACT", close TCP net before open socket*/ - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+QIDEACT=1\r\n"); - - PrivTaskDelay(2500); - - ADAPTER_DEBUG("Ec200t open done\n"); - - return 0; -} - -static int Ec200tClose(struct Adapter *adapter) -{ - if (!adapter->agent) { - printf("Ec200tClose AT agent NULL\n"); - return -1; - } - - /*step1: serial write "+++", quit transparent mode*/ - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "+++"); - - /*step2: serial write "AT+QICLOSE", close socket connect before open socket*/ - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+QICLOSE=0\r\n"); - - PrivTaskDelay(2500); - - /*step3: serial write "AT+QIDEACT", close TCP net before open socket*/ - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+QIDEACT=1\r\n"); - - PrivTaskDelay(2500); - - /*step4: close ec200t serial port*/ - PrivClose(adapter->fd); - - /*step5: power down ec200t*/ - Ec200tPowerSet(); - - return 0; -} - -static int Ec200tIoctl(struct Adapter *adapter, int cmd, void *args) -{ - if (OPE_INT != cmd) { - printf("Ec200tIoctl only support OPE_INT, do not support %d\n", cmd); - return -1; - } - - uint32_t baud_rate = *((uint32_t *)args); - - struct SerialDataCfg serial_cfg; - memset(&serial_cfg, 0 ,sizeof(struct SerialDataCfg)); - serial_cfg.serial_baud_rate = baud_rate; - serial_cfg.serial_data_bits = DATA_BITS_8; - serial_cfg.serial_stop_bits = STOP_BITS_1; - serial_cfg.serial_buffer_size = SERIAL_RB_BUFSZ; - serial_cfg.serial_parity_mode = PARITY_NONE; - serial_cfg.serial_bit_order = STOP_BITS_1; - serial_cfg.serial_invert_mode = NRZ_NORMAL; -#ifdef ADAPTER_EC200T_DRIVER_EXT_PORT - serial_cfg.ext_uart_no = ADAPTER_EC200T_DRIVER_EXT_PORT; - serial_cfg.port_configure = PORT_CFG_INIT; -#endif - - struct PrivIoctlCfg ioctl_cfg; - ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; - ioctl_cfg.args = &serial_cfg; - PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg); - - return 0; -} - -static int Ec200tConnect(struct Adapter *adapter, enum NetRoleType net_role, const char *ip, const char *port, enum IpType ip_type) -{ - uint8_t ec200t_cmd[64]; - - /*step1: serial write "AT+QICSGP", connect to China Mobile using ipv4 or ipv6*/ - memset(ec200t_cmd, 0, sizeof(ec200t_cmd)); - - if (IPV4 == ip_type) { - strcpy(ec200t_cmd, "AT+QICSGP=1,1,\"CMNET\",\"\",\"\",1\r\n"); - } else if (IPV6 == ip_type) { - strcpy(ec200t_cmd, "AT+QICSGP=1,2,\"CMNET\",\"\",\"\",1\r\n"); - } - - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, ec200t_cmd); - - PrivTaskDelay(2500); - - /*step2: serial write "AT+QIACT", open TCP net*/ - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+QIACT=1\r\n"); - - PrivTaskDelay(2500); - - /*step3: serial write "AT+QIOPEN", connect socket using TCP*/ - memset(ec200t_cmd, 0, sizeof(ec200t_cmd)); - strcpy(ec200t_cmd, "AT+QIOPEN=1,0,\"TCP\",\""); - strcat(ec200t_cmd, ip); - strcat(ec200t_cmd, "\","); - strcat(ec200t_cmd, port); - strcat(ec200t_cmd, ",0,2\r\n"); - - ADAPTER_DEBUG("Ec200t connect AT CMD :%s\n", ec200t_cmd); - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, ec200t_cmd); - - ADAPTER_DEBUG("Ec200t connect TCP done\n"); - - return 0; -} - -static int Ec200tSend(struct Adapter *adapter, const void *buf, size_t len) -{ - PrivWrite(adapter->fd, buf, len); - return 0; -} - -static int Ec200tRecv(struct Adapter *adapter, void *buf, size_t len) -{ - PrivRead(adapter->fd, buf, len); - return 0; -} - -static int Ec200tDisconnect(struct Adapter *adapter) -{ - uint8_t ec200t_cmd[64]; - - /*step1: serial write "+++", quit transparent mode*/ - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "+++"); - - /*step2: serial write "AT+QICLOSE", close socket connect before open socket*/ - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+QICLOSE=0\r\n"); - - PrivTaskDelay(2500); - - ADAPTER_DEBUG("Ec200t disconnect TCP done\n"); - - return 0; -} - -static const struct IpProtocolDone ec200t_done = -{ - .open = Ec200tOpen, - .close = Ec200tClose, - .ioctl = Ec200tIoctl, - .setup = NULL, - .setdown = NULL, - .setaddr = NULL, - .setdns = NULL, - .setdhcp = NULL, - .ping = NULL, - .netstat = NULL, - .connect = Ec200tConnect, - .send = Ec200tSend, - .recv = Ec200tRecv, - .disconnect = Ec200tDisconnect, -}; - -AdapterProductInfoType Ec200tAttach(struct Adapter *adapter) -{ - struct AdapterProductInfo *product_info = malloc(sizeof(struct AdapterProductInfo)); - if (!product_info) { - printf("Ec200tAttach malloc product_info error\n"); - free(product_info); - return NULL; - } - - product_info->model_name = ADAPTER_4G_EC200T; - - product_info->model_done = (void *)&ec200t_done; - - Ec200tPowerSet(); - - return product_info; -} - - - diff --git a/APP_Framework/Framework/connection/4G/Kconfig b/APP_Framework/Framework/connection/4G/Kconfig deleted file mode 100644 index 81603ff3f..000000000 --- a/APP_Framework/Framework/connection/4G/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -config ADAPTER_4G - bool "Using 4G adapter function" - default y - - if ADAPTER_4G - config ADAPTER_EC200T - bool "Using 4G adapter device EC200T" - default y - - if ADAPTER_EC200T - source "$APP_DIR/Framework/connection/4G/EC200T/Kconfig" - endif - - endif diff --git a/APP_Framework/Framework/connection/4G/Makefile b/APP_Framework/Framework/connection/4G/Makefile deleted file mode 100644 index 1ef3b9279..000000000 --- a/APP_Framework/Framework/connection/4G/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -SRC_FILES := adapter_4G.c - -ifeq ($(CONFIG_ADAPTER_EC200T),y) - SRC_DIR += EC200T -endif - -include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/APP_Framework/Framework/connection/4G/adapter_4G.c b/APP_Framework/Framework/connection/4G/adapter_4G.c deleted file mode 100644 index aaab44248..000000000 --- a/APP_Framework/Framework/connection/4G/adapter_4G.c +++ /dev/null @@ -1,110 +0,0 @@ -/* -* Copyright (c) 2020 AIIT XUOS Lab -* XiUOS is licensed under Mulan PSL v2. -* You can use this software according to the terms and conditions of the Mulan PSL v2. -* You may obtain a copy of Mulan PSL v2 at: -* http://license.coscl.org.cn/MulanPSL2 -* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -* See the Mulan PSL v2 for more details. -*/ - -/** - * @file adapter_4G.c - * @brief Implement the connection 4G adapter function - * @version 1.1 - * @author AIIT XUOS Lab - * @date 2021.06.25 - */ - -#include - -#ifdef ADAPTER_EC200T -extern AdapterProductInfoType Ec200tAttach(struct Adapter *adapter); -#endif - -#define ADAPTER_4G_NAME "4G" - -static int Adapter4GRegister(struct Adapter *adapter) -{ - int ret = 0; - - strncpy(adapter->name, ADAPTER_4G_NAME, NAME_NUM_MAX); - - adapter->net_protocol = IP_PROTOCOL; - adapter->net_role = CLIENT; - adapter->adapter_status = UNREGISTERED; - - ret = AdapterDeviceRegister(adapter); - if (ret < 0) { - printf("Adapter4G register error\n"); - return -1; - } - - return ret; -} - -int Adapter4GInit(void) -{ - int ret = 0; - - struct Adapter *adapter = malloc(sizeof(struct Adapter)); - if (!adapter) { - free(adapter); - return -1; - } - - ret = Adapter4GRegister(adapter); - if (ret < 0) { - printf("Adapter4GInit register 4G adapter error\n"); - free(adapter); - return -1; - } - -#ifdef ADAPTER_EC200T - AdapterProductInfoType product_info = Ec200tAttach(adapter); - if (!product_info) { - printf("Adapter4GInit ec200t attach error\n"); - free(adapter); - return -1; - } - - adapter->product_info_flag = 1; - adapter->info = product_info; - adapter->done = product_info->model_done; - -#endif - - return ret; -} - -/******************4G TEST*********************/ -int Adapter4GTest(void) -{ - const char *send_msg = "SendHeart"; - char recv_msg[128]; - int baud_rate = BAUD_RATE_115200; - - struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_4G_NAME); - -#ifdef ADAPTER_EC200T - //Using DSD server to test 4G Socket connection - uint8 server_addr[64] = "115.238.53.61"; - uint8 server_port[64] = "33333"; - - AdapterDeviceOpen(adapter); - AdapterDeviceControl(adapter, OPE_INT, &baud_rate); - - AdapterDeviceConnect(adapter, CLIENT, server_addr, server_port, IPV4); - - while (1) { - AdapterDeviceSend(adapter, send_msg, strlen(send_msg)); - AdapterDeviceRecv(adapter, recv_msg, 128); - printf("4G recv msg %s\n", recv_msg); - } -#endif - - return 0; -} -SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, Adapter4GTest, Adapter4GTest, show adapter 4G information); diff --git a/APP_Framework/Framework/connection/5G/Makefile b/APP_Framework/Framework/connection/5G/Makefile deleted file mode 100644 index 9ce9e188f..000000000 --- a/APP_Framework/Framework/connection/5G/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -SRC_FILES := adapter_5G.c - -include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/Kconfig b/APP_Framework/Framework/connection/Kconfig index bd062e6f4..a2ef6e64e 100644 --- a/APP_Framework/Framework/connection/Kconfig +++ b/APP_Framework/Framework/connection/Kconfig @@ -18,7 +18,7 @@ if SUPPORT_CONNECTION_FRAMEWORK bool "Using 4G adapter device" default n if CONNECTION_ADAPTER_4G - source "$APP_DIR/Framework/connection/4G/Kconfig" + source "$APP_DIR/Framework/connection/4g/Kconfig" endif menuconfig CONNECTION_ADAPTER_NB @@ -60,6 +60,6 @@ if SUPPORT_CONNECTION_FRAMEWORK bool "Using 5G adapter device" default n if CONNECTION_ADAPTER_5G - source "$APP_DIR/Framework/connection/5G/Kconfig" + source "$APP_DIR/Framework/connection/5g/Kconfig" endif endif diff --git a/APP_Framework/Framework/connection/Makefile b/APP_Framework/Framework/connection/Makefile index cb5c209b5..54ebc25ba 100644 --- a/APP_Framework/Framework/connection/Makefile +++ b/APP_Framework/Framework/connection/Makefile @@ -1,35 +1,35 @@ SRC_FILES := adapter.c adapter_agent.c -ifeq ($(CONFIG_ADAPTER_LORA),y) +ifeq ($(CONFIG_CONNECTION_ADAPTER_LORA),y) SRC_DIR += lora endif -ifeq ($(CONFIG_ADAPTER_4G),y) - SRC_DIR += 4G +ifeq ($(CONFIG_CONNECTION_ADAPTER_4G),y) + SRC_DIR += 4g endif -ifeq ($(CONFIG_ADAPTER_NB),y) +ifeq ($(CONFIG_CONNECTION_ADAPTER_NB),y) SRC_DIR += nbiot endif -ifeq ($(CONFIG_ADAPTER_WIFI),y) +ifeq ($(CONFIG_CONNECTION_ADAPTER_WIFI),y) SRC_DIR += wifi endif -ifeq ($(CONFIG_ADAPTER_ETHERNET),y) +ifeq ($(CONFIG_CONNECTION_ADAPTER_ETHERNET),y) SRC_DIR += ethernet endif -ifeq ($(CONFIG_ADAPTER_BLUETOOTH),y) +ifeq ($(CONFIG_CONNECTION_ADAPTER_BLUETOOTH),y) SRC_DIR += bluetooth endif -ifeq ($(CONFIG_ADAPTER_ZIGBEE),y) +ifeq ($(CONFIG_CONNECTION_ADAPTER_ZIGBEE),y) SRC_DIR += zigbee endif -ifeq ($(CONFIG_ADAPTER_5G),y) - SRC_DIR += 5G +ifeq ($(CONFIG_CONNECTION_ADAPTER_5G),y) + SRC_DIR += 5g endif include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/APP_Framework/Framework/connection/adapter.h b/APP_Framework/Framework/connection/adapter.h index 5713e9ce5..eb492301c 100644 --- a/APP_Framework/Framework/connection/adapter.h +++ b/APP_Framework/Framework/connection/adapter.h @@ -39,19 +39,10 @@ extern "C" { #define ADAPTER_LWIP_OPERATION 2 #define ADAPTER_RAWIP_OPERATION 3 -#define ADAPTER_LORA_FUNC ((uint32_t)(1 << ATAPTER_LORA)) -#define ADAPTER_4G_FUNC ((uint32_t)(1 << ADAPTER_4G)) -#define ADAPTER_NBIOT_FUNC ((uint32_t)(1 << ADAPTER_NBIOT)) -#define ADAPTER_WIFI_FUNC ((uint32_t)(1 << ADAPTER_WIFI)) -#define ADAPTER_ETHERNET_FUNC ((uint32_t)(1 << ADAPTER_ETHERNET)) -#define ADAPTER_BLUETOOTH_FUNC ((uint32_t)(1 << ADAPTER_BLUETOOTH)) -#define ADAPTER_ZIGBEE_FUNC ((uint32_t)(1 << ADAPTER_ZIGBEE)) -#define ADAPTER_5G_FUNC ((uint32_t)(1 << ADAPTER_5G)) - #ifdef CONNECTION_FRAMEWORK_DEBUG #define ADAPTER_DEBUG printf #else -#define ADAPTER_DEBUF +#define ADAPTER_DEBUG #endif struct Adapter; @@ -61,8 +52,14 @@ typedef struct AdapterProductInfo *AdapterProductInfoType; struct Socket { - int id; - struct Adapter *adapter; + uint8_t type; ///< socket type:DGRAM->UDP,STREAM->TCP + uint8_t protocal; ///< udp or tcp + unsigned short listen_port; ///< 0-65535 + uint8_t socket_id; ///< socket id + uint8_t recv_control; ///< receive control + uint8_t af_type; ///< IPv4 or IPv6 + char *src_ip_addr; ///< source P address + char *dst_ip_addr; ///< destination IP address }; enum AdapterType @@ -90,6 +87,9 @@ enum NetRoleType SERVER, MASTER, SLAVE, + COORDINATOR, + ROUTER, + END_DEVICE, ROLE_NONE, }; @@ -110,8 +110,9 @@ enum IpType struct AdapterProductInfo { uint32_t functions; - const char *vendor_name; - const char *model_name; + char vendor_name[NAME_NUM_MAX]; + char model_name[NAME_NUM_MAX]; + uint32_t work_mode; void *model_done; }; @@ -154,14 +155,14 @@ struct PrivProtocolDone struct Adapter { - char *name; + char name[NAME_NUM_MAX]; int fd; int product_info_flag; struct AdapterProductInfo *info; ATAgentType agent; - //struct Socket *socket; + struct Socket socket; enum NetProtocolType net_protocol; enum NetRoleType net_role; diff --git a/APP_Framework/Framework/connection/adapter_agent.c b/APP_Framework/Framework/connection/adapter_agent.c index 60475e84c..5cc8d9d5b 100755 --- a/APP_Framework/Framework/connection/adapter_agent.c +++ b/APP_Framework/Framework/connection/adapter_agent.c @@ -27,7 +27,6 @@ #include #include #include -#include #define AT_CMD_MAX_LEN 128 #define AT_AGENT_MAX 2 @@ -36,18 +35,19 @@ static uint32 last_cmd_len = 0; static struct ATAgent at_agent_table[AT_AGENT_MAX] = {0}; -uint IpTint(char *ipstr){ +unsigned int IpTint(char *ipstr) +{ if (ipstr == NULL) return 0; char *token; - uint i = 3, total = 0, cur; + unsigned int i = 3, total = 0, cur; token = strtok(ipstr, "."); - while (token != NULL){ + while (token != NULL) { cur = atoi(token); - if (cur >= 0 && cur <= 255){ + if (cur >= 0 && cur <= 255) { total += cur * pow(256, i); } i--; @@ -61,8 +61,8 @@ void SwapStr(char *str, int begin, int end) { int i, j; - for (i = begin, j = end; i <= j; i++, j--){ - if (str[i] != str[j]){ + for (i = begin, j = end; i <= j; i++, j--) { + if (str[i] != str[j]) { str[i] = str[i] ^ str[j]; str[j] = str[i] ^ str[j]; str[i] = str[i] ^ str[j]; @@ -70,16 +70,16 @@ void SwapStr(char *str, int begin, int end) } } -char *IpTstr(uint ipint) +char *IpTstr(unsigned int ipint) { int LEN = 16; - char *new = (char *)malloc(LEN); + char *new = (char *)PrivMalloc(LEN); memset(new, '\0', LEN); new[0] = '.'; char token[4]; int bt, ed, len, cur; - while (ipint){ + while (ipint) { cur = ipint % 256; sprintf(token, "%d", cur); strcat(new, token); @@ -91,8 +91,8 @@ char *IpTstr(uint ipint) len = strlen(new); SwapStr(new, 0, len - 1); - for (bt = ed = 0; ed < len;){ - while (ed < len && new[ed] != '.'){ + for (bt = ed = 0; ed < len;) { + while (ed < len && new[ed] != '.') { ed++; } SwapStr(new, bt, ed - 1); @@ -120,17 +120,21 @@ int ParseATReply(char *str, const char *format, ...) uint32 ATSprintf(int fd, const char *format, va_list params) { last_cmd_len = vsnprintf(send_buf, sizeof(send_buf), format, params); - printf("ATSprintf send %s\n",send_buf); + printf("ATSprintf send %s len %u\n",send_buf, last_cmd_len); PrivWrite(fd, send_buf, last_cmd_len); } -int ATOrderSend(ATAgentType agent, uint32 timeout, ATReplyType reply, const char *cmd_expr, ...) +int ATOrderSend(ATAgentType agent, uint32 timeout_s, ATReplyType reply, const char *cmd_expr, ...) { - if (agent == NULL){ + if (agent == NULL) { printf("ATAgent is null"); return -ERROR; } + struct timespec abstime; + + abstime.tv_sec = timeout_s; + agent->receive_mode = AT_MODE; memset(agent->maintain_buffer, 0x00, agent->maintain_max); @@ -147,16 +151,16 @@ int ATOrderSend(ATAgentType agent, uint32 timeout, ATReplyType reply, const char agent->reply = reply; - if(agent->reply != NULL){ + if(agent->reply != NULL) { reply->reply_len = 0; va_start(params, cmd_expr); ATSprintf(agent->fd, cmd_expr, params); va_end(params); - if (UserSemaphoreObtain(agent->rsp_sem, timeout) != EOK){ + if (PrivSemaphoreObtainWait(&agent->rsp_sem, &abstime) != EOK) { result = -ETIMEOUT; goto __out; } - }else{ + } else { va_start(params, cmd_expr); ATSprintf(agent->fd, cmd_expr, params); va_end(params); @@ -166,16 +170,87 @@ int ATOrderSend(ATAgentType agent, uint32 timeout, ATReplyType reply, const char __out: agent->reply = NULL; PrivMutexAbandon(&agent->lock); - agent->receive_mode = ENTM_MODE; + agent->receive_mode = DEFAULT_MODE; return result; } +int AtCmdConfigAndCheck(ATAgentType agent, char *cmd, char *check) +{ + int ret = 0; + char *result = NULL; + if (NULL == agent || NULL == cmd || NULL == check ) { + return -1; + } + + ATReplyType reply = CreateATReply(64); + if (NULL == reply) { + printf("%s %d at_create_resp failed!\n",__func__,__LINE__); + ret = -1; + goto __exit; + } + + ATOrderSend(agent, REPLY_TIME_OUT, reply, cmd); + PrivTaskDelay(3000); + + result = GetReplyText(reply); + if (!result) { + printf("%s %n get reply failed.\n",__func__,__LINE__); + ret = -1; + goto __exit; + } + printf("[reply result :\n"); + printf("%s]\n", result); + if(!strstr(result, check)) { + printf("%s %d check[%s] reply[%s] failed.\n",__func__,__LINE__,check,result); + ret = -1; + goto __exit; + } + +__exit: + DeleteATReply(reply); + return ret; +} + char *GetReplyText(ATReplyType reply) { return reply->reply_buffer; } +int AtSetReplyLrEnd(ATAgentType agent, char enable) +{ + if (!agent) { + return -ERROR; + } + + agent->reply_lr_end = enable; + + return EOK; +} + +int AtSetReplyEndChar(ATAgentType agent, char last_ch, char end_ch) +{ + if (!agent) { + return -ERROR; + } + + agent->reply_end_last_char = last_ch; + agent->reply_end_char = end_ch; + + return EOK; +} + +int AtSetReplyCharNum(ATAgentType agent, unsigned int num) +{ + if (!agent) { + return -ERROR; + } + + agent->reply_char_num = num; + + return EOK; +} + int EntmSend(ATAgentType agent, const char *data, int len) { char send_buf[128]; @@ -185,32 +260,40 @@ int EntmSend(ATAgentType agent, const char *data, int len) memcpy(send_buf, data, len); memcpy(send_buf + len, "!@", 2); - write(agent->fd, send_buf, len + 2); + PrivWrite(agent->fd, send_buf, len + 2); return EOK; } -int EntmRecv(ATAgentType agent, char *rev_buffer, int buffer_len, int time_out) +int EntmRecv(ATAgentType agent, char *rev_buffer, int buffer_len, int timeout_s) { - UserTaskDelay(1000); + struct timespec abstime; + + abstime.tv_sec = timeout_s; + + agent->receive_mode = ENTM_MODE; + + PrivTaskDelay(1000); + + if (PrivSemaphoreObtainWait(&agent->entm_rx_notice, &abstime)) { + return -ERROR; + } + + PrivMutexObtain(&agent->lock); + + if (buffer_len < agent->entm_recv_len) { + return -ERROR; + } + + printf("EntmRecv once len %u.\n", agent->entm_recv_len); + + agent->entm_recv_buf[agent->entm_recv_len - 1] = '\0'; + memcpy(rev_buffer, agent->entm_recv_buf, agent->entm_recv_len - 2); memset(agent->entm_recv_buf, 0, ENTM_RECV_MAX); agent->entm_recv_len = 0; - UserSemaphoreSetValue(agent->entm_rx_notice, 0); - - if (UserSemaphoreObtain(agent->entm_rx_notice, time_out)){ - return ERROR; - } - - if (buffer_len < agent->entm_recv_len){ - return ERROR; - } - - printf("EntmRecv once .\n"); - - agent->entm_recv_buf[agent->entm_recv_len - 2] = '\0'; - memcpy(rev_buffer, agent->entm_recv_buf, agent->entm_recv_len - 2); + PrivMutexAbandon(&agent->lock); return EOK; } @@ -224,42 +307,49 @@ static int GetCompleteATReply(ATAgentType agent) memset(agent->maintain_buffer, 0x00, agent->maintain_max); agent->maintain_len = 0; - while (1){ - read(agent->fd, &ch, 1); - - printf(" %c(0x%x)\n", ch, ch); - + while (1) { + PrivRead(agent->fd, &ch, 1); +#ifdef CONNECTION_FRAMEWORK_DEBUG + printf(" %c (0x%x)\n", ch, ch); +#endif if (agent->receive_mode == ENTM_MODE){ - if (agent->entm_recv_len < ENTM_RECV_MAX){ - agent->entm_recv_buf[agent->entm_recv_len++] = ch; + if (agent->entm_recv_len < ENTM_RECV_MAX) { + PrivMutexObtain(&agent->lock); + + agent->entm_recv_buf[agent->entm_recv_len] = ch; + agent->entm_recv_len++; + + PrivMutexAbandon(&agent->lock); if (last_ch == '!' && ch == '@'){ - UserSemaphoreAbandon(agent->entm_rx_notice); + PrivSemaphoreAbandon(&agent->entm_rx_notice); } last_ch = ch; - } - else{ + } else { printf("entm_recv_buf is_full ...\n"); } - } - else if (agent->receive_mode == AT_MODE){ + } else if (agent->receive_mode == AT_MODE) { if (read_len < agent->maintain_max){ - agent->maintain_buffer[read_len++] = ch; + agent->maintain_buffer[read_len] = ch; + read_len++; agent->maintain_len = read_len; - }else{ + } else { printf("maintain_len is_full ...\n"); is_full = true; } - if ((ch == '\n' && last_ch == '\r')){ - if (is_full){ + if (((ch == '\n') && (last_ch == '\r') && (agent->reply_lr_end)) || + ((ch == agent->reply_end_char) && (agent->reply_end_char) && + (last_ch == agent->reply_end_last_char) && (agent->reply_end_last_char)) || + ((read_len == agent->reply_char_num) && (agent->reply_char_num))){ + if (is_full) { printf("read line failed. The line data length is out of buffer size(%d)!", agent->maintain_max); memset(agent->maintain_buffer, 0x00, agent->maintain_max); agent->maintain_len = 0; return -ERROR; } - printf("GetCompleteATReply get n r ...\n"); + printf("GetCompleteATReply done\n"); break; } last_ch = ch; @@ -272,8 +362,8 @@ static int GetCompleteATReply(ATAgentType agent) ATAgentType GetATAgent(const char *agent_name) { struct ATAgent* result = NULL; - for (int i = 0; i < AT_AGENT_MAX; i++){ - if (strcmp(at_agent_table[i].agent_name, agent_name) == 0){ + for (int i = 0; i < AT_AGENT_MAX; i++) { + if (strcmp(at_agent_table[i].agent_name, agent_name) == 0) { result = &at_agent_table[i]; } } @@ -284,52 +374,51 @@ ATAgentType GetATAgent(const char *agent_name) static int DeleteATAgent(ATAgentType agent) { - if (agent->lock){ + if (agent->lock) { PrivMutexDelete(&agent->lock); } - if (agent->entm_rx_notice){ - UserSemaphoreDelete(agent->entm_rx_notice); + if (agent->entm_rx_notice) { + PrivSemaphoreDelete(&agent->entm_rx_notice); } - if (agent->fd > 0){ - close(agent->fd); + if (agent->fd > 0) { + PrivClose(agent->fd); } - if (agent->rsp_sem){ - UserSemaphoreDelete(agent->rsp_sem); + if (agent->rsp_sem) { + PrivSemaphoreDelete(&agent->rsp_sem); } - if (agent->maintain_buffer){ - free(agent->maintain_buffer); + if (agent->maintain_buffer) { + PrivFree(agent->maintain_buffer); } memset(agent, 0x00, sizeof(struct ATAgent)); } -static void ATAgentReceiveProcess(void *param) +static void *ATAgentReceiveProcess(void *param) { ATAgentType agent = (ATAgentType)param; const struct at_urc *urc; - while (1){ - if (GetCompleteATReply(agent) > 0){ + while (1) { + if (GetCompleteATReply(agent) > 0) { if (agent->reply != NULL){ ATReplyType reply = agent->reply; - agent->maintain_buffer[agent->maintain_len - 1] = '\0'; + agent->maintain_buffer[agent->maintain_len] = '\0'; - if (agent->maintain_len < reply->reply_max_len){ + if (agent->maintain_len < reply->reply_max_len) { memcpy(reply->reply_buffer, agent->maintain_buffer, agent->maintain_len); reply->reply_len = agent->maintain_len; - } - else{ + } else { printf("out of memory (%d)!", reply->reply_max_len); } agent->reply = NULL; - UserSemaphoreAbandon(agent->rsp_sem); + PrivSemaphoreAbandon(&agent->rsp_sem); } } } @@ -339,56 +428,48 @@ static int ATAgentInit(ATAgentType agent) { int result = EOK; UtaskType at_utask; - do - { - agent->maintain_len = 0; - agent->maintain_buffer = (char *)malloc(agent->maintain_max); - if (agent->maintain_buffer == NONE){ - break; - } + agent->maintain_len = 0; + agent->maintain_buffer = (char *)PrivMalloc(agent->maintain_max); - agent->entm_rx_notice = UserSemaphoreCreate(0); - if (agent->entm_rx_notice == 0){ - break; - } + if (agent->maintain_buffer == NONE) { + printf("ATAgentInit malloc maintain_buffer error\n"); + goto __out; + } - agent->rsp_sem = UserSemaphoreCreate(0); - if (agent->rsp_sem == 0){ - break; - } - if(PrivMutexCreate(&agent->lock, 0) < 0) { - printf("AdapterFrameworkInit mutex create failed.\n"); - } - if (agent->lock == 0){ - break; - } + memset(agent->maintain_buffer, 0, agent->maintain_max); - agent->receive_mode = ENTM_MODE; + result = PrivSemaphoreCreate(&agent->entm_rx_notice, 0, 0); + if (result < 0) { + printf("ATAgentInit create entm sem error\n"); + goto __out; + } - strncpy(at_utask.name, "recv_task", strlen("recv_task")); - at_utask.func_entry = ATAgentReceiveProcess; - at_utask.func_param = agent; - at_utask.stack_size = 1024; - at_utask.prio = 18; + result = PrivSemaphoreCreate(&agent->rsp_sem, 0, 0); + if (result < 0) { + printf("ATAgentInit create rsp sem error\n"); + goto __out; + } - agent->at_handler = UserTaskCreate(at_utask); + if(PrivMutexCreate(&agent->lock, 0) < 0) { + printf("AdapterFrameworkInit mutex create failed.\n"); + goto __out; + } - // struct SerialDataCfg data_cfg; - // memset(&data_cfg, 0, sizeof(struct SerialDataCfg)); - // data_cfg.serial_baud_rate = 57600; - // ioctl(agent->fd, OPE_INT, &data_cfg); + agent->receive_mode = ENTM_MODE; - if (agent->at_handler == 0) { - break; - } + pthread_attr_t attr; + attr.schedparam.sched_priority = 18; + attr.stacksize = 2048; - result = EOK; - return result; - } while (1); + PrivTaskCreate(&agent->at_handler, &attr, ATAgentReceiveProcess, agent); + return result; + +__out: DeleteATAgent(agent); result = -ERROR; + return result; } @@ -422,9 +503,8 @@ int InitATAgent(const char *agent_name, int agent_fd, uint32 maintain_max) agent->maintain_max = maintain_max; result = ATAgentInit(agent); - if (result == EOK) - { - UserTaskStartup(agent->at_handler); + if (result == EOK) { + PrivTaskStartup(&agent->at_handler); } return result; @@ -434,38 +514,37 @@ ATReplyType CreateATReply(uint32 reply_max_len) { ATReplyType reply = NULL; - reply = (ATReplyType)malloc(sizeof(struct ATReply)); - if (reply == NULL){ + reply = (ATReplyType)PrivMalloc(sizeof(struct ATReply)); + if (reply == NULL) { printf("no more memory\n"); return NULL; } reply->reply_max_len = reply_max_len; - reply->reply_buffer = (char *)malloc(reply_max_len); - if (reply->reply_buffer == NULL){ + reply->reply_buffer = (char *)PrivMalloc(reply_max_len); + if (reply->reply_buffer == NULL) { printf("no more memory\n"); - free(reply); + PrivFree(reply); return NULL; } + memset(reply->reply_buffer, 0, reply_max_len); + return reply; } void DeleteATReply(ATReplyType reply) { - if (reply){ - if (reply->reply_buffer){ - free(reply->reply_buffer); + if (reply) { + if (reply->reply_buffer) { + PrivFree(reply->reply_buffer); reply->reply_buffer = NULL; } } - if (reply){ - free(reply); + if (reply) { + PrivFree(reply); reply = NULL; } } - - - diff --git a/APP_Framework/Framework/connection/at_agent.h b/APP_Framework/Framework/connection/at_agent.h index 834fb6e63..794c27bb2 100755 --- a/APP_Framework/Framework/connection/at_agent.h +++ b/APP_Framework/Framework/connection/at_agent.h @@ -26,8 +26,11 @@ #include #include +#define REPLY_TIME_OUT 3 + enum ReceiveMode { + DEFAULT_MODE = 0, ENTM_MODE = 1, AT_MODE = 2, }; @@ -52,9 +55,13 @@ struct ATAgent int lock; ATReplyType reply; + char reply_lr_end; + char reply_end_last_char; + char reply_end_char; + uint32 reply_char_num; int rsp_sem; - int32 at_handler; + pthread_t at_handler; #define ENTM_RECV_MAX 256 char entm_recv_buf[ENTM_RECV_MAX]; @@ -65,18 +72,20 @@ struct ATAgent typedef struct ATAgent *ATAgentType; int EntmSend(ATAgentType agent, const char *data, int len); -int EntmRecv(ATAgentType agent, char *rev_buffer, int buffer_len, int time_out); +int EntmRecv(ATAgentType agent, char *rev_buffer, int buffer_len, int timeout_s); char *GetReplyText(ATReplyType reply); +int AtSetReplyEndChar(ATAgentType agent, char last_ch, char end_ch); +int AtSetReplyCharNum(ATAgentType agent, unsigned int num); +int AtSetReplyLrEnd(ATAgentType agent, char enable); ATReplyType CreateATReply(uint32 reply_max_len); -uint IpTint(char *ipstr); +unsigned int IpTint(char *ipstr); void SwapStr(char *str, int begin, int end); -char* IpTstr(uint ipint); +char* IpTstr(unsigned int ipint); ATAgentType GetATAgent(const char *agent_name); int InitATAgent(const char *agent_name, int fd, uint32 maintain_max); int ParseATReply(char* str, const char *format, ...); void DeleteATReply(ATReplyType reply); -int ATOrderSend(ATAgentType agent, uint32 timeout, ATReplyType reply, const char *cmd_expr, ...); - -#define REPLY_TIME_OUT 3000 +int ATOrderSend(ATAgentType agent, uint32 timeout_s, ATReplyType reply, const char *cmd_expr, ...); +int AtCmdConfigAndCheck(ATAgentType agent, char *cmd, char *check); #endif \ No newline at end of file diff --git a/APP_Framework/Framework/connection/bluetooth/HC08/Kconfig b/APP_Framework/Framework/connection/bluetooth/HC08/Kconfig deleted file mode 100644 index d8b858a6d..000000000 --- a/APP_Framework/Framework/connection/bluetooth/HC08/Kconfig +++ /dev/null @@ -1,32 +0,0 @@ -config ADAPTER_BLUETOOTH_HC08 - string "HC08 adapter name" - default "hc08" - -if ADD_XIUOS_FETURES - config ADAPTER_HC08_DRIVER_EXTUART - bool "Using extra uart to support bluetooth" - default n - - config ADAPTER_HC08_DRIVER - string "HC08 device uart driver path" - default "/dev/uart4_dev4" - depends on !ADAPTER_HC08_DRIVER_EXTUART - - if ADAPTER_HC08_DRIVER_EXTUART - config ADAPTER_HC08_DRIVER - string "HC08 device extra uart driver path" - default "/dev/extuart_dev7" - - config ADAPTER_HC08_DRIVER_EXT_PORT - int "if HC08 device using extuart, choose port" - default "7" - endif -endif - -if ADD_NUTTX_FETURES - -endif - -if ADD_RTTHREAD_FETURES - -endif diff --git a/APP_Framework/Framework/connection/bluetooth/HC08/Makefile b/APP_Framework/Framework/connection/bluetooth/HC08/Makefile deleted file mode 100644 index 60932ced2..000000000 --- a/APP_Framework/Framework/connection/bluetooth/HC08/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -SRC_FILES := hc08.c - -include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/bluetooth/HC08/hc08.c b/APP_Framework/Framework/connection/bluetooth/HC08/hc08.c deleted file mode 100644 index e99a499ec..000000000 --- a/APP_Framework/Framework/connection/bluetooth/HC08/hc08.c +++ /dev/null @@ -1,170 +0,0 @@ -/* -* Copyright (c) 2020 AIIT XUOS Lab -* XiUOS is licensed under Mulan PSL v2. -* You can use this software according to the terms and conditions of the Mulan PSL v2. -* You may obtain a copy of Mulan PSL v2 at: -* http://license.coscl.org.cn/MulanPSL2 -* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -* See the Mulan PSL v2 for more details. -*/ - -/** - * @file hc08.c - * @brief Implement the connection Bluetooth adapter function, using HC08 device - * @version 1.1 - * @author AIIT XUOS Lab - * @date 2021.07.12 - */ - -#include -#include - -static int rx_sem; -static sem_t *hc08_sem; -static pthread_t hc08_recv_thread; - -void Hc08RecvThreadEntry(void *parameter) -{ - - while (1) - { - PrivRead(adapter->fd, buf, len); - - UserSemaphoreAbandon(rx_sem); - - } -} - -static int Hc08Open(struct Adapter *adapter) -{ - if (INSTALL == adapter->adapter_status) { - printf("Hc08 has already been open\n"); - return 0; - } - - /*step1: open hc08 serial port*/ - adapter->fd = PrivOpen(ADAPTER_HC08_DRIVER, O_RDWR); - if (adapter->fd < 0) { - printf("Hc08Open get serial %s fd error\n", ADAPTER_HC08_DRIVER); - return -1; - } - - /*step2: init AT agent*/ - if (!adapter->agent) { - char *agent_name = "bluetooth_uart_client"; - if (EOK != InitATAgent(agent_name, adapter->fd, 512)) { - printf("at agent init failed !\n"); - return -1; - } - ATAgentType at_agent = GetATAgent(agent_name); - - adapter->agent = at_agent; - } - - /*step3: create bluetooth receive task*/ - PrivSemaphoreCreate(hc08_sem, 0, rx_sem); - - PrivTaskCreate(&hc08_recv_thread, NULL, Hc08RecvThreadEntry, NULL); - - ADAPTER_DEBUG("Hc08 open done\n"); -} - -static int Hc08Close(struct Adapter *adapter) -{ - return 0; -} - -static int Hc08Ioctl(struct Adapter *adapter, int cmd, void *args) -{ - if (OPE_INT != cmd) { - printf("Hc08Ioctl only support OPE_INT, do not support %d\n", cmd); - return -1; - } - - uint32_t baud_rate = *((uint32_t *)args); - - struct SerialDataCfg serial_cfg; - memset(&serial_cfg, 0 ,sizeof(struct SerialDataCfg)); - serial_cfg.serial_baud_rate = baud_rate; - serial_cfg.serial_data_bits = DATA_BITS_8; - serial_cfg.serial_stop_bits = STOP_BITS_1; - serial_cfg.serial_buffer_size = SERIAL_RB_BUFSZ; - serial_cfg.serial_parity_mode = PARITY_NONE; - serial_cfg.serial_bit_order = STOP_BITS_1; - serial_cfg.serial_invert_mode = NRZ_NORMAL; -#ifdef ADAPTER_HC08_DRIVER_EXT_PORT - serial_cfg.ext_uart_no = ADAPTER_HC08_DRIVER_EXT_PORT; - serial_cfg.port_configure = PORT_CFG_INIT; -#endif - - struct PrivIoctlCfg ioctl_cfg; - ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; - ioctl_cfg.args = &serial_cfg; - PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg); - - ADAPTER_DEBUG("Hc08 ioctl done\n"); - - return 0; -} - -static int Hc08SetAddr(struct Adapter *adapter, const char *ip, const char *gateway, const char *netmask) -{ - -} - -static int Hc08Connect(struct Adapter *adapter, enum NetRoleType net_role, const char *ip, const char *port, enum IpType ip_type) -{ - -} - -static int Hc08Send(struct Adapter *adapter, const void *buf, size_t len) -{ - PrivWrite(adapter->fd, buf, len); - return 0; -} - -static int Hc08Recv(struct Adapter *adapter, void *buf, size_t len) -{ - return 0; -} - -static int Hc08Disconnect(struct Adapter *adapter) -{ - -} - -static const struct IpProtocolDone hc08_done = -{ - .open = Hc08Open, - .close = Hc08Close, - .ioctl = Hc08Ioctl, - .setup = NULL, - .setdown = NULL, - .setaddr = Hc08SetAddr, - .setdns = NULL, - .setdhcp = NULL, - .ping = NULL, - .netstat = NULL, - .connect = Hc08Connect, - .send = Hc08Send, - .recv = Hc08Recv, - .disconnect = Hc08Disconnect, -}; - -AdapterProductInfoType Hc08Attach(struct Adapter *adapter) -{ - struct AdapterProductInfo *product_info = malloc(sizeof(struct AdapterProductInfo)); - if (!product_info) { - printf("Hc08Attach malloc product_info error\n"); - free(product_info); - return NULL; - } - - product_info->model_name = ADAPTER_BLUETOOTH_HC08; - - product_info->model_done = (void *)&hc08_done; - - return product_info; -} \ No newline at end of file diff --git a/APP_Framework/Framework/connection/bluetooth/Kconfig b/APP_Framework/Framework/connection/bluetooth/Kconfig index b22eabe34..cb71df572 100644 --- a/APP_Framework/Framework/connection/bluetooth/Kconfig +++ b/APP_Framework/Framework/connection/bluetooth/Kconfig @@ -1,14 +1,7 @@ -config ADAPTER_BLUETOOTH - bool "Using bluetooth adapter function" +config ADAPTER_HC08 + bool "Using bluetooth adapter device HC08" default y - if ADAPTER_BLUETOOTH - config ADAPTER_HC08 - bool "Using bluetooth adapter device HC08" - default y - - if ADAPTER_HC08 - source "$APP_DIR/Framework/connection/bluetooth/HC08/Kconfig" - endif - - endif +if ADAPTER_HC08 + source "$APP_DIR/Framework/connection/bluetooth/hc08/Kconfig" +endif diff --git a/APP_Framework/Framework/connection/bluetooth/Makefile b/APP_Framework/Framework/connection/bluetooth/Makefile index 29ef7fc31..bb367019f 100644 --- a/APP_Framework/Framework/connection/bluetooth/Makefile +++ b/APP_Framework/Framework/connection/bluetooth/Makefile @@ -1,7 +1,7 @@ SRC_FILES := adapter_bluetooth.c ifeq ($(CONFIG_ADAPTER_HC08),y) - SRC_DIR += HC08 + SRC_DIR += hc08 endif include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/bluetooth/adapter_bluetooth.c b/APP_Framework/Framework/connection/bluetooth/adapter_bluetooth.c index 9ac60d270..0f855a4ae 100644 --- a/APP_Framework/Framework/connection/bluetooth/adapter_bluetooth.c +++ b/APP_Framework/Framework/connection/bluetooth/adapter_bluetooth.c @@ -17,3 +17,96 @@ * @author AIIT XUOS Lab * @date 2021.06.25 */ + +#include + +#ifdef ADAPTER_HC08 +extern AdapterProductInfoType Hc08Attach(struct Adapter *adapter); +#endif + +#define ADAPTER_BLUETOOTH_NAME "BlueTooth" + +static int AdapterBlueToothRegister(struct Adapter *adapter) +{ + int ret = 0; + + strncpy(adapter->name, ADAPTER_BLUETOOTH_NAME, NAME_NUM_MAX); + + adapter->net_protocol = IP_PROTOCOL; + adapter->adapter_status = UNREGISTERED; + + ret = AdapterDeviceRegister(adapter); + if (ret < 0) { + printf("AdapterBlueToothRegister register error\n"); + return -1; + } + + return ret; +} + +int AdapterBlueToothInit(void) +{ + int ret = 0; + + struct Adapter *adapter = PrivMalloc(sizeof(struct Adapter)); + if (!adapter) { + free(adapter); + return -1; + } + + memset(adapter, 0, sizeof(struct Adapter)); + + ret = AdapterBlueToothRegister(adapter); + if (ret < 0) { + printf("AdapterBlueToothInit register BT adapter error\n"); + free(adapter); + return -1; + } + +#ifdef ADAPTER_HC08 + AdapterProductInfoType product_info = Hc08Attach(adapter); + if (!product_info) { + printf("AdapterBlueToothInit hc08 attach error\n"); + free(adapter); + return -1; + } + + adapter->product_info_flag = 1; + adapter->info = product_info; + adapter->done = product_info->model_done; + +#endif + + return ret; +} + +/******************4G TEST*********************/ +int AdapterBlueToothTest(void) +{ + const char *bluetooth_msg = "BT Adapter Test"; + char bluetooth_recv_msg[128]; + int len; + int baud_rate = BAUD_RATE_115200; + + struct Adapter *adapter = AdapterDeviceFindByName(ADAPTER_BLUETOOTH_NAME); + +#ifdef ADAPTER_HC08 + AdapterDeviceOpen(adapter); + AdapterDeviceControl(adapter, OPE_INT, &baud_rate); + + len = strlen(bluetooth_msg); + + while (1) { + AdapterDeviceRecv(adapter, bluetooth_recv_msg, 128); + printf("bluetooth_recv_msg %s\n", bluetooth_recv_msg); + AdapterDeviceSend(adapter, bluetooth_msg, len); + printf("send %s after recv\n", bluetooth_msg); + PrivTaskDelay(100); + memset(bluetooth_recv_msg, 0, 128); + } + +#endif + + return 0; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, AdapterBlueToothTest, AdapterBlueToothTest, show adapter BT information); diff --git a/APP_Framework/Framework/connection/lora/SX1278/Kconfig b/APP_Framework/Framework/connection/lora/SX1278/Kconfig deleted file mode 100644 index e69de29bb..000000000 diff --git a/APP_Framework/Framework/connection/lora/SX1278/Makefile b/APP_Framework/Framework/connection/lora/SX1278/Makefile deleted file mode 100644 index e69de29bb..000000000 diff --git a/APP_Framework/Framework/connection/lora/SX1278/sx1278.c b/APP_Framework/Framework/connection/lora/SX1278/sx1278.c deleted file mode 100644 index e69de29bb..000000000 diff --git a/APP_Framework/Framework/connection/nbiot/BC28/Kconfig b/APP_Framework/Framework/connection/nbiot/BC28/Kconfig deleted file mode 100644 index e69de29bb..000000000 diff --git a/APP_Framework/Framework/connection/nbiot/BC28/Makefile b/APP_Framework/Framework/connection/nbiot/BC28/Makefile deleted file mode 100644 index e69de29bb..000000000 diff --git a/APP_Framework/Framework/connection/nbiot/BC28/bc28.c b/APP_Framework/Framework/connection/nbiot/BC28/bc28.c deleted file mode 100644 index e69de29bb..000000000 diff --git a/APP_Framework/Framework/connection/nbiot/Kconfig b/APP_Framework/Framework/connection/nbiot/Kconfig index e69de29bb..bf9a087df 100644 --- a/APP_Framework/Framework/connection/nbiot/Kconfig +++ b/APP_Framework/Framework/connection/nbiot/Kconfig @@ -0,0 +1,10 @@ +if CONNECTION_ADAPTER_NB + config ADAPTER_BC28 + bool "Using nbiot adapter device BC28" + default y + + if ADAPTER_BC28 + source "$APP_DIR/Framework/connection/nbiot/bc28/Kconfig" + endif + +endif diff --git a/APP_Framework/Framework/connection/nbiot/Makefile b/APP_Framework/Framework/connection/nbiot/Makefile index 3dc3423a2..29f2e7d12 100644 --- a/APP_Framework/Framework/connection/nbiot/Makefile +++ b/APP_Framework/Framework/connection/nbiot/Makefile @@ -1,3 +1,7 @@ SRC_FILES := adapter_nbiot.c +ifeq ($(CONFIG_ADAPTER_BC28),y) + SRC_DIR += bc28 +endif + include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/nbiot/adapter_nbiot.c b/APP_Framework/Framework/connection/nbiot/adapter_nbiot.c index 04f98462b..e4ef085dd 100644 --- a/APP_Framework/Framework/connection/nbiot/adapter_nbiot.c +++ b/APP_Framework/Framework/connection/nbiot/adapter_nbiot.c @@ -17,3 +17,156 @@ * @author AIIT XUOS Lab * @date 2021.06.25 */ +#include + + +#ifdef ADAPTER_BC28 +extern AdapterProductInfoType BC28Attach(struct Adapter *adapter); +#endif + +#define ADAPTER_NBIOT_NAME "nbiot" + +static int AdapterNbiotRegister(struct Adapter *adapter) +{ + int ret = 0; + + strncpy(adapter->name, ADAPTER_NBIOT_NAME, NAME_NUM_MAX); + + adapter->net_protocol = IP_PROTOCOL; + adapter->net_role = CLIENT; + + adapter->adapter_status = UNREGISTERED; + + ret = AdapterDeviceRegister(adapter); + if (ret < 0) { + printf("AdapterNbiot register error\n"); + return -1; + } + + return ret; +} + +int AdapterNbiotInit(void) +{ + int ret = 0; + + struct Adapter *adapter = malloc(sizeof(struct Adapter)); + if (!adapter) { + printf("malloc adapter failed.\n"); + return -1; + } + memset(adapter, 0, sizeof(struct Adapter)); + ret = AdapterNbiotRegister(adapter); + if (ret < 0) { + printf("register nbiot adapter error\n"); + free(adapter); + return -1; + } +#ifdef ADAPTER_BC28 + AdapterProductInfoType product_info = BC28Attach(adapter); + if (!product_info) { + printf("bc28 attach error\n"); + free(adapter); + return -1; + } + + adapter->product_info_flag = 1; + adapter->info = product_info; + adapter->done = product_info->model_done; +#endif + + return ret; +} + +/******************TEST*********************/ +int opennb(void) +{ + int ret = 0; + + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_NBIOT_NAME); + +#ifdef ADAPTER_BC28 + ret = AdapterDeviceOpen(adapter); + if(ret < 0){ + printf("open adapter failed\n"); + return -1; + } + +#endif + + return 0; + } + SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, opennb, opennb, show adapter nb information); +int closenb(void) +{ + int ret = 0; + + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_NBIOT_NAME); + +#ifdef ADAPTER_BC28 + ret = AdapterDeviceClose(adapter); + if(ret < 0){ + printf("open adapter failed\n"); + return -1; + } + +#endif + + return 0; + } + SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, closenb, closenb, show adapter nb information); + + int connectnb(int argc, char *argv[]) + { + const char *send_msg = argv[1]; + int ret = 0; + + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_NBIOT_NAME); + + + ret = AdapterDeviceConnect(adapter, 1, "101.68.82.219","9898",1); + if(ret < 0){ + printf(" adapter send failed\n"); + return -1; + } + + + + return 0; + } + SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(2)|SHELL_CMD_DISABLE_RETURN, connectnb, connectnb, show adapter nb information); + + int sendnb(int argc, char *argv[]) + { + const char *send_msg = argv[1]; + int msg_len = atoi(argv[2]); + int ret = 0; + + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_NBIOT_NAME); + + printf("send argv1 %s len = %d\n",argv[1],msg_len); + ret = AdapterDeviceSend(adapter, send_msg, msg_len); + if(ret < 0){ + printf(" adapter send failed\n"); + return -1; + } + printf("nb send msg %s\n", send_msg); + + + return 0; + } + SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(2)|SHELL_CMD_DISABLE_RETURN, sendnb, sendnb, show adapter nb information); + + int recvnb(void) + { + char recv_msg[128]; + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_NBIOT_NAME); + memset(recv_msg,0,128); + AdapterDeviceRecv(adapter, recv_msg, 128); + PrivTaskDelay(2000); + printf("nb recv msg %s\n", recv_msg); + + return 0; + } + SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, recvnb, recvnb, show adapter nb information); + diff --git a/APP_Framework/Framework/connection/wifi/HFA21/Kconfig b/APP_Framework/Framework/connection/wifi/HFA21/Kconfig deleted file mode 100755 index d61721c79..000000000 --- a/APP_Framework/Framework/connection/wifi/HFA21/Kconfig +++ /dev/null @@ -1,33 +0,0 @@ -config ADAPTER_WIFI_HFA21 - string "HFA21 adapter name" - default "hfa21" - -if ADD_XIUOS_FETURES - - config ADAPTER_HFA21_DRIVER_EXTUART - bool "Using extra uart to support wifi" - default n - - config ADAPTER_HFA21_DRIVER - string "HFA21 device uart driver path" - default "/dev/usart3_dev3" - depends on !ADAPTER_HFA21_DRIVER_EXTUART - - if ADAPTER_HFA21_DRIVER_EXTUART - config ADAPTER_HFA21_DRIVER - string "HFA21 device extra uart driver path" - default "/dev/extuart_dev6" - - config ADAPTER_HFA21_DRIVER_EXT_PORT - int "if HFA21 device using extuart, choose port" - default "6" - endif -endif - -if ADD_NUTTX_FETURES - -endif - -if ADD_RTTHREAD_FETURES - -endif diff --git a/APP_Framework/Framework/connection/wifi/HFA21/Makefile b/APP_Framework/Framework/connection/wifi/HFA21/Makefile deleted file mode 100755 index a5c95324b..000000000 --- a/APP_Framework/Framework/connection/wifi/HFA21/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -SRC_FILES := hfa21.c - -include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/wifi/HFA21/hfa21.c b/APP_Framework/Framework/connection/wifi/HFA21/hfa21.c deleted file mode 100755 index aa8afb32e..000000000 --- a/APP_Framework/Framework/connection/wifi/HFA21/hfa21.c +++ /dev/null @@ -1,516 +0,0 @@ -/* -* Copyright (c) 2020 AIIT XUOS Lab -* XiUOS is licensed under Mulan PSL v2. -* You can use this software according to the terms and conditions of the Mulan PSL v2. -* You may obtain a copy of Mulan PSL v2 at: -* http://license.coscl.org.cn/MulanPSL2 -* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -* See the Mulan PSL v2 for more details. -*/ - -/** - * @file hfa21.c - * @brief Implement the connection wifi adapter function, using HFA21 device - * @version 1.1 - * @author AIIT XUOS Lab - * @date 2021.07.08 - */ - -#include -#include - -#define LEN_PARA_BUF 128 - -static int Hfa21SetDown(struct Adapter *adapter_at); - -/** - * @description: enter AT command mode - * @param at_agent - wifi device agent pointer - * @return success: EOK - */ -static int Hfa21InitAtCmd(ATAgentType at_agent) -{ - ATOrderSend(at_agent, REPLY_TIME_OUT, NULL, "+++"); - PrivTaskDelay(100); - - ATOrderSend(at_agent, REPLY_TIME_OUT, NULL, "a"); - PrivTaskDelay(500); - - return 0; -} - -/** - * @description: Open wifi - * @param adapter - wifi device pointer - * @return success: EOK, failure: ENOMEMORY - */ -static int Hfa21Open(struct Adapter *adapter) -{ - /*step1: open ec200t serial port*/ - adapter->fd = PrivOpen(ADAPTER_HFA21_DRIVER, O_RDWR); - if (adapter->fd < 0) { - printf("Hfa21Open get serial %s fd error\n", ADAPTER_HFA21_DRIVER); - return -1; - } - - /*step2: init AT agent*/ - if (!adapter->agent) { - char *agent_name = "wifi_uart_client"; - if (EOK != InitATAgent(agent_name, adapter->fd, 512)) { - printf("at agent init failed !\n"); - return -1; - } - ATAgentType at_agent = GetATAgent(agent_name); - - adapter->agent = at_agent; - } - - ADAPTER_DEBUG("Hfa21 open done\n"); - - return 0; -} - -/** - * @description: Close wifi - * @param adapter - wifi device pointer - * @return success: EOK - */ -static int Hfa21Close(struct Adapter *adapter) -{ - return Hfa21SetDown(adapter); -} - -/** - * @description: send data to adapter - * @param adapter - wifi device pointer - * @param data - data bufferd - * @param data - data length - * @return success: EOK - */ -static int Hfa21Send(struct Adapter *adapter, const void *data, size_t len) -{ - x_err_t result = EOK; - if (adapter->agent) { - EntmSend(adapter->agent, (const char *)data, len); - }else { - printf("Can not find agent \n"); - } - -__exit: - - return result; -} - -/** - * @description: receive data from adapter - * @param adapter - wifi device pointer - * @param data - data bufferd - * @param data - data length - * @return success: EOK - */ -static int Hfa21Receive(struct Adapter *adapter, void *rev_buffer, size_t buffer_len) -{ - x_err_t result = EOK; - printf("hfa21 receive waiting ... \n"); - - if (adapter->agent) { - return EntmRecv(adapter->agent, (char *)rev_buffer, buffer_len, 40000); - } else { - printf("Can not find agent \n"); - } - -__exit: - - return result; -} - -/** - * @description: connnect wifi to internet - * @param adapter - wifi device pointer - * @return success: EOK - */ -static int Hfa21SetUp(struct Adapter *adapter) -{ - uint8 wifi_ssid[LEN_PARA_BUF] = "AIIT-Guest"; - uint8 wifi_pwd[LEN_PARA_BUF] = ""; - char cmd[LEN_PARA_BUF]; - - //struct at_device_esp8266 *esp8266 = (struct at_device_esp8266 *) device->UserData; - struct ATAgent *agent = adapter->agent; - - /* wait hfa21 device startup finish */ - PrivTaskDelay(5000); - - Hfa21InitAtCmd(agent); - - memset(cmd,0,sizeof(cmd)); - strcpy(cmd,"AT+FCLR\r"); - ATOrderSend(agent, REPLY_TIME_OUT, NULL, cmd); - PrivTaskDelay(20000); - - Hfa21InitAtCmd(agent); - - memset(cmd,0,sizeof(cmd)); - strcpy(cmd,"AT+WSSSID="); - strcat(cmd,wifi_ssid); - strcat(cmd,"\r"); - ATOrderSend(agent, REPLY_TIME_OUT, NULL, cmd); - PrivTaskDelay(2500); - - memset(cmd,0,sizeof(cmd)); - strcpy(cmd,"AT+WSKEY=OPEN,NONE,"); - strcat(cmd,wifi_pwd); - strcat(cmd,"\r"); - ATOrderSend(agent, REPLY_TIME_OUT, NULL, cmd); - PrivTaskDelay(2500); - - memset(cmd,0,sizeof(cmd)); - strcpy(cmd,"AT+WMODE=sta\r"); - ATOrderSend(agent, REPLY_TIME_OUT, NULL, cmd); - PrivTaskDelay(2500); - - memset(cmd,0,sizeof(cmd)); - strcat(cmd,"AT+Z\r"); - ATOrderSend(agent, REPLY_TIME_OUT, NULL, cmd); - PrivTaskDelay(10000); - - return 0; -} - -/** - * @description: disconnnect wifi from internet - * @param adapter - wifi device pointer - * @return success: EOK - */ -static int Hfa21SetDown(struct Adapter *adapter) -{ - Hfa21InitAtCmd(adapter->agent); - - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+FCLR\r"); - PrivTaskDelay(20000); - - return 0; -} - -/** - * @description: set wifi ip/gateway/netmask address(in sta mode) - * @param adapter - wifi device pointer - * @param ip - ip address - * @param gateway - gateway address - * @param netmask - netmask address - * @return success: EOK, failure: ENOMEMORY - */ -static int Hfa21SetAddr(struct Adapter *adapter, const char *ip, const char *gateway, const char *netmask) -{ - #define HFA21_SET_ADDR_EXPRESSION "+ok=%[^,],%[^,],%[^,],%[^,]\r" - char *dhcp_mode =NULL; - char *ip_str = NULL; - char *gw_str = NULL; - char *mask_str = NULL; - - dhcp_mode = (char *) UserCalloc(1, 8); - ip_str = (char *) UserCalloc(1, 17); - gw_str = (char *) UserCalloc(1, 17); - mask_str = (char *) UserCalloc(1, 17); - - Hfa21InitAtCmd(adapter->agent); - - x_err_t result = EOK; - - ATReplyType reply = CreateATReply(64); - if (NULL == reply) { - printf("at_create_resp failed ! \n"); - result = ENOMEMORY; - goto __exit; - } - - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+WANN=%s,%s,%s,%s\r", "dhcp", ip, netmask, gateway); - PrivTaskDelay(2500); - - ATOrderSend(adapter->agent, REPLY_TIME_OUT, reply, "AT+WANN\r"); - PrivTaskDelay(2500); - - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+Z\r"); - PrivTaskDelay(10000); - - const char * result_buf = GetReplyText(reply); - - char* str = strstr(result_buf, "+ok="); - - ParseATReply(str, HFA21_SET_ADDR_EXPRESSION, dhcp_mode,ip_str,mask_str,gw_str); - printf("after configure:\n mode:%s\n ip:%s\n netmask:%s\n gateway:%s\n", dhcp_mode, ip_str, mask_str, gw_str); - -__exit: - if (reply) { - DeleteATReply(reply); - } - - return result; -} - -/** - * @description: ping - * @param adapter - wifi device pointer - * @param destination - domain name or ip address - * @return success: EOK, failure: ENOMEMORY - */ -static int Hfa21Ping(struct Adapter *adapter, const char *destination) -{ - char *ping_result = NONE; - char *dst = NONE; - ping_result = (char *) UserCalloc(1, 17); - dst = (char *) UserCalloc(1, 17); - strcpy(dst, destination); - strcat(dst, "\r"); - - Hfa21InitAtCmd(adapter->agent); - - uint32 result = EOK; - - ATReplyType reply = CreateATReply(64); - if (NULL == reply) { - printf("at_create_resp failed ! \n"); - result = ENOMEMORY; - goto __exit; - } - - //ping baidu.com - ATOrderSend(adapter->agent, REPLY_TIME_OUT, reply, "AT+PING=%s", dst); - - PrivTaskDelay(2500); - - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+Z\r"); - PrivTaskDelay(10000); - - const char * result_buf = GetReplyText(reply); - - char* str = strstr(result_buf, "+ok="); - - ParseATReply(str, "+ok=%s\r", ping_result); - - printf("ping www.baidu.com(36.152.44.95) result is:%s\n", ping_result); - -__exit: - if (reply) { - DeleteATReply(reply); - } - - return result; -} - -/** - * @description: display network configuration - * @param adapter - wifi device pointer - * @return success: EOK, failure: ENOMEMORY - */ -static int Hfa21Netstat(struct Adapter *adapter) -{ - #define HFA21_NETSTAT_RESP_SIZE 320 - #define HFA21_NETSTAT_TYPE_SIZE 10 - #define HFA21_NETSTAT_IPADDR_SIZE 17 - #define HFA21_WANN_EXPRESSION "+ok=%[^,],%[^,],%[^,],%[^,]\r" - #define HFA21_LANN_EXPRESSION "+ok=%[^,],%[^,]\r" - #define HFA21_WMODE_EXPRESSION "+ok=%s\r" - - ATReplyType reply = NULL; - struct ATAgent *agent = adapter->agent; - uint32 result; - char * result_buf = NULL; - char * str = NULL; - - /* sta/ap */ - char *work_mode = NULL; - /* dhcp/static */ - char *ip_mode = NULL; - char *local_ipaddr = NULL; - char *gateway = NULL; - char *netmask = NULL; - local_ipaddr = (char *) UserCalloc(1, HFA21_NETSTAT_IPADDR_SIZE); - gateway = (char *) UserCalloc(1, HFA21_NETSTAT_IPADDR_SIZE); - netmask = (char *) UserCalloc(1, HFA21_NETSTAT_IPADDR_SIZE); - work_mode = (char *) UserCalloc(1, HFA21_NETSTAT_IPADDR_SIZE); - ip_mode = (char *) UserCalloc(1, HFA21_NETSTAT_IPADDR_SIZE); - - reply = CreateATReply(HFA21_NETSTAT_RESP_SIZE); - if (reply == NULL) { - result = ENOMEMORY; - goto __exit; - } - - ATOrderSend(agent, REPLY_TIME_OUT, NULL, "+++"); - PrivTaskDelay(100); - - ATOrderSend(agent, REPLY_TIME_OUT, NULL, "a"); - PrivTaskDelay(2500); - - ATOrderSend(agent, REPLY_TIME_OUT, reply, "AT+WMODE\r"); - PrivTaskDelay(2500); - - result_buf = GetReplyText(reply); - - str = strstr(result_buf, "+ok="); - /* parse the third line of response data, get the network connection information */ - ParseATReply(str, HFA21_WMODE_EXPRESSION, work_mode); - - if (work_mode[0]=='S') { - if (ATOrderSend(agent, REPLY_TIME_OUT, reply, "AT+WANN\r") < 0) { - goto __exit; - } - - PrivTaskDelay(2500); - - GetReplyText(reply); - str = strstr(result_buf, "+ok="); - /* parse the third line of response data, get the network connection information */ - ParseATReply(str, HFA21_WANN_EXPRESSION, ip_mode, local_ipaddr, netmask, gateway); - } else { - ATOrderSend(agent, REPLY_TIME_OUT, reply, "AT+LANN\r"); - PrivTaskDelay(2500); - - GetReplyText(reply); - - str = strstr(result_buf, "+ok="); - /* parse the third line of response data, get the network connection information */ - ParseATReply(str, HFA21_LANN_EXPRESSION, local_ipaddr, netmask); - } - - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+Z\r"); - PrivTaskDelay(10000); - - printf("work mode: %s\n", work_mode); - if (work_mode[0]=='S') - printf("ip mode: %s\nlocal ip: %s\nnetmask: %s\ngateway: %s\n", ip_mode, local_ipaddr, netmask, gateway); - else - printf("local ip: %s\nnetmask: %s\n", local_ipaddr, netmask); - - return EOK; - -__exit: - if (reply) - DeleteATReply(reply); - if (local_ipaddr) - UserFree(local_ipaddr); - if (netmask) - UserFree(netmask); - if (gateway) - UserFree(gateway); - if (work_mode) - UserFree(work_mode); -} - -static int Hfa21Connect(struct Adapter *adapter, enum NetRoleType net_role, const char *ip, const char *port, enum IpType ip_type) -{ - int result = EOK; - ATReplyType reply = NONE; - char cmd[LEN_PARA_BUF]; - struct ATAgent *agent = adapter->agent; - - reply = CreateATReply(64); - if (reply == NONE) { - printf("no memory for reply struct."); - return ENOMEMORY; - } - - Hfa21InitAtCmd(adapter->agent); - - memset(cmd,0,sizeof(cmd)); - strcpy(cmd,"AT+NETP=TCP,"); - if(net_role == CLIENT) - strcat(cmd,"CLIENT,"); - else if(net_role == SERVER) - strcat(cmd,"SERVER,"); - strcat(cmd,port); - strcat(cmd,","); - if(ip_type == IPV4) - strcat(cmd,ip); - else if(ip_type == IPV6) - { - - } - strcat(cmd,"\r"); - ATOrderSend(agent, REPLY_TIME_OUT, NULL, cmd); - PrivTaskDelay(2500); - - ATOrderSend(adapter->agent, REPLY_TIME_OUT, NULL, "AT+Z\r"); - PrivTaskDelay(10000); - - adapter->net_role = net_role; - -__exit: - if (reply) { - DeleteATReply(reply); - } - - return result; -} - -static int Hfa21Ioctl(struct Adapter *adapter, int cmd, void *args) -{ - if (OPE_INT != cmd) { - printf("Hfa21Ioctl only support OPE_INT, do not support %d\n", cmd); - return -1; - } - - uint32_t baud_rate = *((uint32_t *)args); - - struct SerialDataCfg serial_cfg; - memset(&serial_cfg, 0 ,sizeof(struct SerialDataCfg)); - serial_cfg.serial_baud_rate = baud_rate; - serial_cfg.serial_data_bits = DATA_BITS_8; - serial_cfg.serial_stop_bits = STOP_BITS_1; - serial_cfg.serial_buffer_size = SERIAL_RB_BUFSZ; - serial_cfg.serial_parity_mode = PARITY_NONE; - serial_cfg.serial_bit_order = BIT_ORDER_LSB; - serial_cfg.serial_invert_mode = NRZ_NORMAL; -#ifdef ADAPTER_HFA21_DRIVER_EXT_PORT - serial_cfg.ext_uart_no = ADAPTER_HFA21_DRIVER_EXT_PORT; - serial_cfg.port_configure = PORT_CFG_INIT; -#endif - - struct PrivIoctlCfg ioctl_cfg; - ioctl_cfg.ioctl_driver_type = SERIAL_TYPE; - ioctl_cfg.args = &serial_cfg; - PrivIoctl(adapter->fd, OPE_INT, &ioctl_cfg); - printf("Hfa21Ioctl success\n"); - return 0; -} - -static const struct IpProtocolDone hfa21_done = -{ - .open = Hfa21Open, - .close = Hfa21Close, - .ioctl = Hfa21Ioctl, - .setup = Hfa21SetUp, - .setdown = Hfa21SetDown, - .setaddr = Hfa21SetAddr, - .setdns = NULL, - .setdhcp = NULL, - .ping = Hfa21Ping, - .netstat = Hfa21Netstat, - .connect = Hfa21Connect, - .send = Hfa21Send, - .recv = Hfa21Receive, - .disconnect = NULL, -}; - -/** - * @description: Register wifi device hfa21 - * @return success: EOK, failure: ERROR - */ -AdapterProductInfoType Hfa21Attach(struct Adapter *adapter) -{ - struct AdapterProductInfo *product_info = malloc(sizeof(struct AdapterProductInfo)); - if (!product_info) { - printf("Hfa21Attach Attach malloc product_info error\n"); - free(product_info); - return NULL; - } - - product_info->model_name = ADAPTER_WIFI_HFA21; - - product_info->model_done = (void *)&hfa21_done; - - return product_info; -} \ No newline at end of file diff --git a/APP_Framework/Framework/connection/wifi/Kconfig b/APP_Framework/Framework/connection/wifi/Kconfig index 330ff17d9..acda24557 100644 --- a/APP_Framework/Framework/connection/wifi/Kconfig +++ b/APP_Framework/Framework/connection/wifi/Kconfig @@ -1,14 +1,7 @@ -config ADAPTER_WIFI - bool "Using WIFI adapter function" +config ADAPTER_HFA21_WIFI + bool "Using wifi adapter device HFA21" default y - if ADAPTER_WIFI - config ADAPTER_HFA21 - bool "Using wifi adapter device HFA21" - default y - - if ADAPTER_HFA21 - source "$APP_DIR/Framework/connection/wifi/HFA21/Kconfig" - endif - - endif +if ADAPTER_HFA21_WIFI + source "$APP_DIR/Framework/connection/wifi/hfa21_wifi/Kconfig" +endif diff --git a/APP_Framework/Framework/connection/wifi/Makefile b/APP_Framework/Framework/connection/wifi/Makefile index 8c5a0c86a..3e08f0652 100644 --- a/APP_Framework/Framework/connection/wifi/Makefile +++ b/APP_Framework/Framework/connection/wifi/Makefile @@ -1,7 +1,7 @@ SRC_FILES := adapter_wifi.c -ifeq ($(CONFIG_ADAPTER_HFA21),y) - SRC_DIR += HFA21 +ifeq ($(CONFIG_ADAPTER_HFA21_WIFI),y) + SRC_DIR += hfa21_wifi endif include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/wifi/adapter_wifi.c b/APP_Framework/Framework/connection/wifi/adapter_wifi.c index 2f329d0ca..f9c27e48a 100644 --- a/APP_Framework/Framework/connection/wifi/adapter_wifi.c +++ b/APP_Framework/Framework/connection/wifi/adapter_wifi.c @@ -21,7 +21,7 @@ #include #include -#ifdef ADAPTER_HFA21 +#ifdef ADAPTER_HFA21_WIFI extern AdapterProductInfoType Hfa21Attach(struct Adapter *adapter); #endif @@ -49,13 +49,15 @@ int AdapterWifiInit(void) { int ret = 0; - struct Adapter *adapter = malloc(sizeof(struct Adapter)); + struct Adapter *adapter = PrivMalloc(sizeof(struct Adapter)); if (!adapter) { printf("AdapterWifiInit malloc error\n"); free(adapter); return -1; } + memset(adapter, 0, sizeof(struct Adapter)); + ret = AdapterWifiRegister(adapter); if (ret < 0) { printf("AdapterWifiInit register wifi adapter error\n"); @@ -63,7 +65,7 @@ int AdapterWifiInit(void) return -1; } -#ifdef ADAPTER_HFA21 +#ifdef ADAPTER_HFA21_WIFI AdapterProductInfoType product_info = Hfa21Attach(adapter); if (!product_info) { printf("AdapterWifiInit hfa21 attach error\n"); diff --git a/APP_Framework/Framework/connection/zigbee/E18/Kconfig b/APP_Framework/Framework/connection/zigbee/E18/Kconfig deleted file mode 100644 index e69de29bb..000000000 diff --git a/APP_Framework/Framework/connection/zigbee/E18/Makefile b/APP_Framework/Framework/connection/zigbee/E18/Makefile deleted file mode 100644 index e69de29bb..000000000 diff --git a/APP_Framework/Framework/connection/zigbee/E18/e18.c b/APP_Framework/Framework/connection/zigbee/E18/e18.c deleted file mode 100644 index e69de29bb..000000000 diff --git a/APP_Framework/Framework/connection/zigbee/Kconfig b/APP_Framework/Framework/connection/zigbee/Kconfig index e69de29bb..42619008d 100644 --- a/APP_Framework/Framework/connection/zigbee/Kconfig +++ b/APP_Framework/Framework/connection/zigbee/Kconfig @@ -0,0 +1,10 @@ +if CONNECTION_ADAPTER_ZIGBEE + config ADAPTER_E18 + bool "Using zigbee adapter device E18" + default y + + if ADAPTER_E18 + source "$APP_DIR/Framework/connection/zigbee/e18/Kconfig" + endif + +endif diff --git a/APP_Framework/Framework/connection/zigbee/Makefile b/APP_Framework/Framework/connection/zigbee/Makefile index 0311fe302..316cd2d06 100644 --- a/APP_Framework/Framework/connection/zigbee/Makefile +++ b/APP_Framework/Framework/connection/zigbee/Makefile @@ -1,3 +1,7 @@ SRC_FILES := adapter_zigbee.c +ifeq ($(CONFIG_ADAPTER_E18),y) + SRC_DIR += e18 +endif + include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/zigbee/adapter_zigbee.c b/APP_Framework/Framework/connection/zigbee/adapter_zigbee.c index 102830bf4..482ef7566 100644 --- a/APP_Framework/Framework/connection/zigbee/adapter_zigbee.c +++ b/APP_Framework/Framework/connection/zigbee/adapter_zigbee.c @@ -15,5 +15,143 @@ * @brief Implement the connection zigbee adapter function * @version 1.1 * @author AIIT XUOS Lab - * @date 2021.06.25 + * @date 2021.09.15 */ + +#include +#include "adapter_zigbee.h" + + +#ifdef ADAPTER_E18 +extern AdapterProductInfoType E18Attach(struct Adapter *adapter); +#endif + +#define ADAPTER_ZIGBEE_NAME "zigbee" + +static int AdapterZigbeeRegister(struct Adapter *adapter) +{ + int ret = 0; + + strncpy(adapter->name, ADAPTER_ZIGBEE_NAME, NAME_NUM_MAX); + + /* config adapter net protocol as network mode */ + adapter->net_protocol = PRIVATE_PROTOCOL; + + /* config adapter net role as coordinator/router/end_device */ +#ifdef AS_COORDINATOR_ROLE + adapter->net_role = COORDINATOR; +#endif +#ifdef AS_ROUTER_ROLE + adapter->net_role = ROUTER; +#endif +#ifdef AS_END_DEVICE_ROLE + adapter->net_role = END_DEVICE; +#endif + + adapter->adapter_status = UNREGISTERED; + + ret = AdapterDeviceRegister(adapter); + if (ret < 0) { + printf("AdapterZigbee register error\n"); + return -1; + } + + return ret; +} + +int AdapterZigbeeInit(void) +{ + int ret = 0; + + struct Adapter *adapter = malloc(sizeof(struct Adapter)); + if (!adapter) { + printf("malloc adapter failed.\n"); + return -1; + } + memset(adapter, 0, sizeof(struct Adapter)); + ret = AdapterZigbeeRegister(adapter); + if (ret < 0) { + printf("AdapterZigbeeRegister register zigbee adapter error\n"); + free(adapter); + return -1; + } +#ifdef ADAPTER_E18 + AdapterProductInfoType product_info = E18Attach(adapter); + if (!product_info) { + printf("AdapterZigbeeRegister e18 attach error\n"); + free(adapter); + return -1; + } + + adapter->product_info_flag = 1; + adapter->info = product_info; + adapter->done = product_info->model_done; +#endif + + return ret; +} + +/******************TEST*********************/ +int openzigbee(void) +{ + int ret = 0; + + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_ZIGBEE_NAME); + +#ifdef ADAPTER_E18 + ret = AdapterDeviceOpen(adapter); + if(ret < 0){ + printf("open adapter failed\n"); + return -1; + } + + adapter->info->work_mode = 1; + ret = AdapterDeviceControl(adapter, CONFIG_ZIGBEE_NET_MODE,NULL); + if(ret < 0){ + printf("control adapter failed\n"); + return -1; + } + ret = AdapterDeviceJoin(adapter, NULL); + if(ret < 0){ + printf("join adapter failed\n"); + return -1; + } +#endif + + return 0; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, openzigbee, openzigbee, show adapter zigbee information); + +int sendzigbee(int argc, char *argv[]) +{ + const char *send_msg = argv[1]; + int ret = 0; + + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_ZIGBEE_NAME); + + printf("send argv1 %s\n",argv[1]); + ret = AdapterDeviceSend(adapter, send_msg, strlen(send_msg)); + if(ret < 0){ + printf(" adapter send failed\n"); + return -1; + } + printf("zigbee send msg %s\n", send_msg); + + + return 0; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)|SHELL_CMD_PARAM_NUM(2)|SHELL_CMD_DISABLE_RETURN, sendzigbee, sendzigbee, show adapter zigbee information); + +int recvzigbee(void) +{ + char recv_msg[128]; + struct Adapter* adapter = AdapterDeviceFindByName(ADAPTER_ZIGBEE_NAME); + memset(recv_msg,0,128); + AdapterDeviceRecv(adapter, recv_msg, 128); + PrivTaskDelay(2000); + printf("zigbee recv msg %s\n", recv_msg); + + return 0; +} +SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0)|SHELL_CMD_DISABLE_RETURN, recvzigbee, recvzigbee, show adapter zigbee information); + diff --git a/APP_Framework/Framework/sensor/co2/zg09/zg09.c b/APP_Framework/Framework/sensor/co2/zg09/zg09.c index e9d5fd0e3..c5ab95e06 100644 --- a/APP_Framework/Framework/sensor/co2/zg09/zg09.c +++ b/APP_Framework/Framework/sensor/co2/zg09/zg09.c @@ -81,7 +81,7 @@ static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) PrivRead(sdev->fd, &tmp, 1); if ((tmp == 0xFE) || (timeout >= 1000)) break; - UserTaskDelay(10); + PrivTaskDelay(10); ++timeout; } diff --git a/APP_Framework/Framework/sensor/humidity/hs300x_humi/hs300x_humi.c b/APP_Framework/Framework/sensor/humidity/hs300x_humi/hs300x_humi.c index a91d07481..7779db355 100644 --- a/APP_Framework/Framework/sensor/humidity/hs300x_humi/hs300x_humi.c +++ b/APP_Framework/Framework/sensor/humidity/hs300x_humi/hs300x_humi.c @@ -52,7 +52,7 @@ static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) if (PrivWrite(sdev->fd, NULL, 0) != 1) return -1; - UserTaskDelay(50); + PrivTaskDelay(50); if (PrivRead(sdev->fd, sdev->buffer, len) != 1) return -1; diff --git a/APP_Framework/Framework/sensor/pm/ps5308/ps5308.c b/APP_Framework/Framework/sensor/pm/ps5308/ps5308.c index 34fa3fd87..126eb082a 100644 --- a/APP_Framework/Framework/sensor/pm/ps5308/ps5308.c +++ b/APP_Framework/Framework/sensor/pm/ps5308/ps5308.c @@ -21,8 +21,8 @@ #include static struct SensorDevice ps5308; -static int32_t active_task_id; -static int buff_lock; +static pthread_t active_task_id; +static pthread_mutex_t buff_lock; static struct SensorProductInfo info = { @@ -35,13 +35,14 @@ static struct SensorProductInfo info = * @description: Read sensor task * @param sdev - sensor device pointer */ -static void ReadTask(struct SensorDevice *sdev) +static void *ReadTask(void *parameter) { + struct SensorDevice *sdev = (struct SensorDevice *)parameter; while (1) { - UserMutexObtain(buff_lock, WAITING_FOREVER); + PrivMutexObtain(&buff_lock); sdev->done->read(sdev, 32); - UserMutexAbandon(buff_lock); - UserTaskDelay(750); + PrivMutexAbandon(&buff_lock); + PrivTaskDelay(750); } } @@ -54,7 +55,7 @@ static int SensorDeviceOpen(struct SensorDevice *sdev) { int result = 0; - buff_lock = UserMutexCreate(); + PrivMutexCreate(&buff_lock, 0); sdev->fd = open(SENSOR_DEVICE_PS5308_DEV, O_RDWR); @@ -73,17 +74,8 @@ static int SensorDeviceOpen(struct SensorDevice *sdev) result = ioctl(sdev->fd, OPE_INT, &cfg); - UtaskType active_task; - const char name[NAME_NUM_MAX] = "ps5308_task"; - - strncpy(active_task.name, name, strlen(name)); - active_task.func_entry = ReadTask; - active_task.func_param = sdev; - active_task.prio = KTASK_PRIORITY_MAX/2; - active_task.stack_size = 1024; - - active_task_id = UserTaskCreate(active_task); - result = UserTaskStartup(active_task_id); + PrivTaskCreate(&active_task_id, NULL, &ReadTask, sdev); + PrivTaskStartup(&active_task_id); return result; } @@ -95,8 +87,8 @@ static int SensorDeviceOpen(struct SensorDevice *sdev) */ static int SensorDeviceClose(struct SensorDevice *sdev) { - UserTaskDelete(active_task_id); - UserMutexDelete(buff_lock); + PrivTaskDelete(active_task_id, 0); + PrivMutexDelete(&buff_lock); return 0; } @@ -114,7 +106,7 @@ static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) read(sdev->fd, &tmp, 1); if ((tmp == 0x44) || (timeout >= 1000)) break; - UserTaskDelay(10); + PrivTaskDelay(10); ++timeout; } @@ -175,7 +167,7 @@ static int32_t ReadPm1_0(struct SensorQuantity *quant) uint32_t result; if (quant->sdev->done->read != NULL) { uint16_t checksum = 0; - UserMutexObtain(buff_lock, WAITING_FOREVER); + PrivMutexObtain(&buff_lock); for (uint8_t i = 0; i < 30; i++) checksum += quant->sdev->buffer[i]; @@ -242,7 +234,7 @@ static int32_t ReadPm2_5(struct SensorQuantity *quant) uint32_t result; if (quant->sdev->done->read != NULL) { uint16_t checksum = 0; - UserMutexObtain(buff_lock, WAITING_FOREVER); + PrivMutexObtain(&buff_lock); for (uint i = 0; i < 30; i++) checksum += quant->sdev->buffer[i]; @@ -309,7 +301,7 @@ static int32_t ReadPm10(struct SensorQuantity *quant) uint32_t result; if (quant->sdev->done->read != NULL) { uint16_t checksum = 0; - UserMutexObtain(buff_lock, WAITING_FOREVER); + PrivMutexObtain(&buff_lock); for (uint i = 0; i < 30; i++) checksum += quant->sdev->buffer[i]; diff --git a/APP_Framework/Framework/sensor/temperature/hs300x_temp/hs300x_temp.c b/APP_Framework/Framework/sensor/temperature/hs300x_temp/hs300x_temp.c index 0ac49e192..f2b2d1e38 100644 --- a/APP_Framework/Framework/sensor/temperature/hs300x_temp/hs300x_temp.c +++ b/APP_Framework/Framework/sensor/temperature/hs300x_temp/hs300x_temp.c @@ -52,7 +52,7 @@ static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) if (PrivWrite(sdev->fd, NULL, 0) != 1) return -1; - UserTaskDelay(50); + PrivTaskDelay(50); if (PrivRead(sdev->fd, sdev->buffer, len) != 1) return -1; diff --git a/APP_Framework/Framework/sensor/voice/Kconfig b/APP_Framework/Framework/sensor/voice/Kconfig index 17576e323..8726a407f 100644 --- a/APP_Framework/Framework/sensor/voice/Kconfig +++ b/APP_Framework/Framework/sensor/voice/Kconfig @@ -9,7 +9,7 @@ config SENSOR_D124 default "d124_1" config SENSOR_QUANTITY_D124_VOICE - string "D124 quantity PM1.0 name" + string "D124 quantity voice name" default "voice_1" if ADD_XIUOS_FETURES diff --git a/APP_Framework/Framework/sensor/voice/d124/d124.c b/APP_Framework/Framework/sensor/voice/d124/d124.c index 031c1a3d9..6c9b93f4a 100644 --- a/APP_Framework/Framework/sensor/voice/d124/d124.c +++ b/APP_Framework/Framework/sensor/voice/d124/d124.c @@ -21,8 +21,8 @@ #include static struct SensorDevice d124; -static int32_t active_task_id; -static int buff_lock; +static pthread_t active_task_id; +static pthread_mutex_t buff_lock; static struct SensorProductInfo info = { @@ -35,13 +35,14 @@ static struct SensorProductInfo info = * @description: Read sensor task * @param sdev - sensor device pointer */ -static void ReadTask(struct SensorDevice *sdev) +static void *ReadTask(void *parameter) { + struct SensorDevice *sdev = (struct SensorDevice *)parameter; while (1) { - UserMutexObtain(buff_lock, WAITING_FOREVER); + PrivMutexObtain(&buff_lock); sdev->done->read(sdev, 5); - UserMutexAbandon(buff_lock); - UserTaskDelay(750); + PrivMutexAbandon(&buff_lock); + PrivTaskDelay(750); } } @@ -53,8 +54,9 @@ static void ReadTask(struct SensorDevice *sdev) static int SensorDeviceOpen(struct SensorDevice *sdev) { int result = 0; + pthread_attr_t attr; - buff_lock = UserMutexCreate(); + PrivMutexCreate(&buff_lock, 0); sdev->fd = PrivOpen(SENSOR_DEVICE_D124_DEV, O_RDWR); @@ -76,17 +78,11 @@ static int SensorDeviceOpen(struct SensorDevice *sdev) ioctl_cfg.args = &cfg; result = PrivIoctl(sdev->fd, OPE_INT, &ioctl_cfg); - UtaskType active_task; - const char name[NAME_NUM_MAX] = "d124_task"; + attr.schedparam.sched_priority = 20; + attr.stacksize = 2048; - strncpy(active_task.name, name, strlen(name)); - active_task.func_entry = ReadTask; - active_task.func_param = sdev; - active_task.prio = KTASK_PRIORITY_MAX/2; - active_task.stack_size = 2048; - - active_task_id = UserTaskCreate(active_task); - result = UserTaskStartup(active_task_id); + PrivTaskCreate(&active_task_id, &attr, &ReadTask, sdev); + PrivTaskStartup(&active_task_id); return result; } @@ -98,8 +94,8 @@ static int SensorDeviceOpen(struct SensorDevice *sdev) */ static int SensorDeviceClose(struct SensorDevice *sdev) { - UserTaskDelete(active_task_id); - UserMutexDelete(buff_lock); + PrivTaskDelete(active_task_id, 0); + PrivMutexDelete(&buff_lock); return 0; } @@ -117,7 +113,7 @@ static int SensorDeviceRead(struct SensorDevice *sdev, size_t len) PrivRead(sdev->fd, &tmp, 1); if ((tmp == 0xAA) || (timeout >= 1000)) break; - UserTaskDelay(10); + PrivTaskDelay(10); ++timeout; } @@ -176,7 +172,7 @@ static int32_t ReadVoice(struct SensorQuantity *quant) uint32_t result; if (quant->sdev->done->read != NULL) { - UserMutexObtain(buff_lock, WAITING_FOREVER); + PrivMutexObtain(&buff_lock); if (quant->sdev->buffer[3] == quant->sdev->buffer[1] + quant->sdev->buffer[2]) { result = ((uint16_t)quant->sdev->buffer[1] << 8) + (uint16_t)quant->sdev->buffer[2]; diff --git a/APP_Framework/Framework/transform_layer/rtthread/SConscript b/APP_Framework/Framework/transform_layer/rtthread/SConscript index a6582ad2c..c0151255e 100644 --- a/APP_Framework/Framework/transform_layer/rtthread/SConscript +++ b/APP_Framework/Framework/transform_layer/rtthread/SConscript @@ -5,7 +5,7 @@ Import('rtconfig') cwd = GetCurrentDir() DEPENDS = [""] -SOURCES = [] +SOURCES = ['transform.c'] path = [cwd] objs = DefineGroup('transform', src = SOURCES, depend = DEPENDS,CPPPATH = path) Return("objs") \ No newline at end of file diff --git a/APP_Framework/Framework/transform_layer/rtthread/transform.h b/APP_Framework/Framework/transform_layer/rtthread/transform.h index 25cb92117..a6db34732 100644 --- a/APP_Framework/Framework/transform_layer/rtthread/transform.h +++ b/APP_Framework/Framework/transform_layer/rtthread/transform.h @@ -30,26 +30,170 @@ #include #include #include +#include +#include #include #include #include +#include +#include +#include #ifdef RT_USING_POSIX_TERMIOS #include #endif #ifdef DRV_USING_OV2640 #include #endif -#if defined(RT_USING_SAL) +#if defined(RT_USING_SAL)&& defined (RT_USING_LWIP) #include #include -#else +#elif defined RT_USING_LWIP #include #include #endif /* RT_USING_SAL */ +#ifdef BOARD_K210_EVB +#include +#include +#endif + + #ifdef __cplusplus extern "C" { #endif +typedef signed char int8; +typedef signed short int16; +typedef signed int int32; +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned int uint32; + +#ifdef ARCH_CPU_64BIT +typedef signed long int64; +typedef unsigned long uint64; +#else +typedef signed long long int64; +typedef unsigned long long uint64; +#endif + +#define OPE_INT 0x0000 +#define OPE_CFG 0x0001 + +#define NAME_NUM_MAX 32 + +/*********************GPIO define*********************/ +#define GPIO_LOW 0x00 +#define GPIO_HIGH 0x01 + +#define GPIO_CFG_OUTPUT 0x00 +#define GPIO_CFG_INPUT 0x01 +#define GPIO_CFG_INPUT_PULLUP 0x02 +#define GPIO_CFG_INPUT_PULLDOWN 0x03 +#define GPIO_CFG_OUTPUT_OD 0x04 + +#define GPIO_CONFIG_MODE 0xffffffff +#ifndef SERIAL_RB_BUFSZ +#define SERIAL_RB_BUFSZ 128 +#endif + +struct PinDevIrq +{ + int irq_mode;//< RISING/FALLING/HIGH/LOW + void (*hdr) (void *args);//< callback function + void *args;//< the params of callback function +}; + +struct PinParam +{ + int cmd;//< cmd:GPIO_CONFIG_MODE/GPIO_IRQ_REGISTER/GPIO_IRQ_FREE/GPIO_IRQ_DISABLE/GPIO_IRQ_ENABLE + long pin;//< pin number + int mode;//< pin mode: input/output + struct PinDevIrq irq_set;//< pin irq set + uint64_t arg; +}; + +struct PinStat +{ + long pin;//< pin number + uint16_t val;//< pin level +}; + +enum ExtSerialPortConfigure +{ + PORT_CFG_INIT = 0, + PORT_CFG_PARITY_CHECK, + PORT_CFG_DISABLE, + PORT_CFG_DIV, +}; + +struct SerialDataCfg +{ + uint32_t serial_baud_rate; + uint8_t serial_data_bits; + uint8_t serial_stop_bits; + uint8_t serial_parity_mode; + uint8_t serial_bit_order; + uint8_t serial_invert_mode; + uint16_t serial_buffer_size; + + uint8_t ext_uart_no; + enum ExtSerialPortConfigure port_configure; +}; + +enum IoctlDriverType +{ + SERIAL_TYPE = 0, + SPI_TYPE, + I2C_TYPE, + PIN_TYPE, + DEFAULT_TYPE, +}; + +struct PrivIoctlCfg +{ + enum IoctlDriverType ioctl_driver_type; + void *args; +}; + +/**********************mutex**************************/ + +int PrivMutexCreate(pthread_mutex_t *p_mutex, const pthread_mutexattr_t *attr); +int PrivMutexDelete(pthread_mutex_t *p_mutex); +int PrivMutexObtain(pthread_mutex_t *p_mutex); +int PrivMutexAbandon(pthread_mutex_t *p_mutex); + +/*********************semaphore**********************/ + +int PrivSemaphoreCreate(sem_t *sem, int pshared, unsigned int value); +int PrivSemaphoreDelete(sem_t *sem); +int PrivSemaphoreObtainWait(sem_t *sem, const struct timespec *abstime); +int PrivSemaphoreObtainNoWait(sem_t *sem); +int PrivSemaphoreAbandon(sem_t *sem); +int32_t PrivSemaphoreSetValue(int32_t sem, uint16_t val); + +/*********************task**************************/ + +int PrivTaskCreate(pthread_t *thread, const pthread_attr_t *attr, + void *(*start_routine)(void *), void *arg); +int PrivTaskStartup(pthread_t *thread); +int PrivTaskDelete(pthread_t thread, int sig); +void PrivTaskQuit(void *value_ptr); +int PrivTaskDelay(int32_t ms); + +/*********************driver*************************/ + +int PrivOpen(const char *path, int flags); +int PrivRead(int fd, void *buf, size_t len); +int PrivWrite(int fd, const void *buf, size_t len); +int PrivClose(int fd); +int PrivIoctl(int fd, int cmd, void *args); + +/*********************memory***********************/ + +void *PrivMalloc(size_t size); +void *PrivRealloc(void *pointer, size_t size); +void *PrivCalloc(size_t count, size_t size); +void PrivFree(void *pointer); #ifdef __cplusplus diff --git a/APP_Framework/Framework/transform_layer/xiuos/user_api/posix_support/pthread.c b/APP_Framework/Framework/transform_layer/xiuos/user_api/posix_support/pthread.c index a7ab718a7..12a181418 100644 --- a/APP_Framework/Framework/transform_layer/xiuos/user_api/posix_support/pthread.c +++ b/APP_Framework/Framework/transform_layer/xiuos/user_api/posix_support/pthread.c @@ -18,7 +18,8 @@ * @date: 2020/4/20 * */ -#include +#include +#include #include "include/pthread.h" int pthread_create(pthread_t *thread, const pthread_attr_t *attr, @@ -26,12 +27,22 @@ int pthread_create(pthread_t *thread, const pthread_attr_t *attr, { int ret ; int pid ; + char task_name[32] = {0}; + static int utask_id = 0; UtaskType task ; + + if (NULL == attr) { + task.prio = KTASK_PRIORITY_MAX / 2; + task.stack_size = 1024 ; + } else { + task.prio = attr->schedparam.sched_priority ; + task.stack_size = attr->stacksize ; + } + task.func_entry = start_routine ; - task.func_param = arg ; - memcpy(task.name , "utask", 6); - task.prio = 20 ; - task.stack_size = 1024 ; + task.func_param = arg; + snprintf(task_name, sizeof(task_name) - 1, "utask%02d",utask_id++); + memcpy(task.name , task_name, sizeof(task_name) - 1); pid = UserTaskCreate(task); if (pid < 0) diff --git a/APP_Framework/Framework/transform_layer/xiuos/user_api/posix_support/semaphore.c b/APP_Framework/Framework/transform_layer/xiuos/user_api/posix_support/semaphore.c index 1961fbe5d..239770472 100644 --- a/APP_Framework/Framework/transform_layer/xiuos/user_api/posix_support/semaphore.c +++ b/APP_Framework/Framework/transform_layer/xiuos/user_api/posix_support/semaphore.c @@ -24,9 +24,8 @@ int sem_init(sem_t *sem, int pshared, unsigned int value) { - int32 ret = 0; - ret = UserSemaphoreCreate(value); - if (ret < 0) { + *sem = UserSemaphoreCreate(value); + if (*sem < 0) { return -1; } diff --git a/APP_Framework/Framework/transform_layer/xiuos/user_api/switch_api/user_api.h b/APP_Framework/Framework/transform_layer/xiuos/user_api/switch_api/user_api.h index 898a61ab0..161e6add9 100644 --- a/APP_Framework/Framework/transform_layer/xiuos/user_api/switch_api/user_api.h +++ b/APP_Framework/Framework/transform_layer/xiuos/user_api/switch_api/user_api.h @@ -22,6 +22,7 @@ #ifndef XS_USER_API_H #define XS_USER_API_H +#include #include #include #include diff --git a/Ubiquitous/Nuttx/nuttx/boards/Kconfig b/Ubiquitous/Nuttx/nuttx/boards/Kconfig index 86f40d657..48814b8c7 100644 --- a/Ubiquitous/Nuttx/nuttx/boards/Kconfig +++ b/Ubiquitous/Nuttx/nuttx/boards/Kconfig @@ -1748,6 +1748,15 @@ config ARCH_BOARD_STM32F4_DISCOVERY ---help--- STMicro STM32F4-Discovery board based on the STMicro STM32F407VGT6 MCU. +config ARCH_BOARD_STM32F4_AIIT + bool "STMicro STM32F4-AIIT board" + depends on ARCH_CHIP_STM32F407VG + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + STMicro STM32F4-Discovery board based on the STMicro STM32F407VGT6 MCU. + config ARCH_BOARD_STM32F411E_DISCO bool "STMicro STM32F411E-Discovery board" depends on ARCH_CHIP_STM32F411VE @@ -2415,6 +2424,7 @@ config ARCH_BOARD default "stm32f3discovery" if ARCH_BOARD_STM32F3_DISCOVERY default "stm32f334-disco" if ARCH_BOARD_STM32F334_DISCO default "stm32f4discovery" if ARCH_BOARD_STM32F4_DISCOVERY + default "aiit-arm32-board" if ARCH_BOARD_STM32F4_AIIT default "stm32f411e-disco" if ARCH_BOARD_STM32F411E_DISCO default "stm32f429i-disco" if ARCH_BOARD_STM32F429I_DISCO default "stm32f746g-disco" if ARCH_BOARD_STM32F746G_DISCO @@ -2804,6 +2814,9 @@ endif if ARCH_BOARD_STM32H747I_DISCO source "boards/arm/stm32h7/stm32h747i-disco/Kconfig" endif +if ARCH_BOARD_STM32F4_AIIT +source "boards/arm/stm32/aiit-arm32-board/Kconfig" +endif if ARCH_BOARD_NUCLEO_H743ZI source "boards/arm/stm32h7/nucleo-h743zi/Kconfig" endif diff --git a/Ubiquitous/Nuttx/nuttx/boards/README.txt b/Ubiquitous/Nuttx/nuttx/boards/README.txt index 0f0da393a..b085698bf 100644 --- a/Ubiquitous/Nuttx/nuttx/boards/README.txt +++ b/Ubiquitous/Nuttx/nuttx/boards/README.txt @@ -756,6 +756,9 @@ boards/arm/stm32/stm32f103-minimum boards/arm/stm32/stm32f4discovery STMicro STM32F4-Discovery board based on the STMicro STM32F407VGT6 MCU. +boards/arm/stm32/aiit-arm32-board + STMicro STM32F4-AIIT board based on the STMicro STM32F407VGT6 MCU. + boards/arm/stm32/stm32f411e-disco This is a minimal configuration that supports low-level test of the STMicro STM32F411E-Discovery Board. diff --git a/Ubiquitous/RT_Thread/bsp/k210/.config b/Ubiquitous/RT_Thread/bsp/k210/.config index 71a427343..e38931055 100644 --- a/Ubiquitous/RT_Thread/bsp/k210/.config +++ b/Ubiquitous/RT_Thread/bsp/k210/.config @@ -12,6 +12,7 @@ CONFIG_BOARD_K210_EVB=y # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_BIG_ENDIAN is not set # CONFIG_RT_USING_ARCH_DATA_TYPE is not set CONFIG_RT_USING_SMP=y CONFIG_RT_CPUS_NR=2 @@ -20,12 +21,13 @@ CONFIG_RT_ALIGN_SIZE=8 CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_TICK_PER_SECOND=100 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=4096 +CONFIG_SYSTEM_THREAD_STACK_SIZE=4096 # CONFIG_RT_USING_TIMER_SOFT is not set # @@ -33,6 +35,7 @@ CONFIG_IDLE_THREAD_STACK_SIZE=4096 # # CONFIG_RT_KSERVICE_USING_STDLIB is not set # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set CONFIG_RT_DEBUG=y CONFIG_RT_DEBUG_COLOR=y CONFIG_RT_DEBUG_INIT_CONFIG=y @@ -79,6 +82,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uarths" +# CONFIG_RT_PRINTF_LONGLONG is not set CONFIG_RT_VER_NUM=0x40004 CONFIG_ARCH_CPU_64BIT=y # CONFIG_RT_USING_CPU_FFS is not set @@ -99,25 +103,26 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10 # # C++ features # -# CONFIG_RT_USING_CPLUSPLUS is not set +CONFIG_RT_USING_CPLUSPLUS=y +# CONFIG_RT_USING_CPLUSPLUS11 is not set # # Command shell # CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=16384 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y CONFIG_FINSH_USING_DESCRIPTION=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=16384 -CONFIG_FINSH_CMD_SIZE=80 # CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -CONFIG_FINSH_USING_MSH_ONLY=y CONFIG_FINSH_ARG_MAX=10 # @@ -151,6 +156,7 @@ CONFIG_RT_DFS_ELM_DRIVES=2 CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 # CONFIG_RT_DFS_ELM_USE_ERASE is not set CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set @@ -165,6 +171,8 @@ CONFIG_RT_USING_SYSTEM_WORKQUEUE=y CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set @@ -179,7 +187,9 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_RTC is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set CONFIG_RT_USING_SPI=y # CONFIG_RT_USING_QSPI is not set @@ -244,8 +254,9 @@ CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_TERMIOS is not set # CONFIG_RT_USING_POSIX_GETLINE is not set # CONFIG_RT_USING_POSIX_AIO is not set +CONFIG_RT_LIBC_USING_TIME=y # CONFIG_RT_USING_MODULE is not set -CONFIG_RT_LIBC_FIXED_TIMEZONE=8 +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # Network @@ -261,8 +272,7 @@ CONFIG_RT_USING_SAL=y # protocol stack implement # CONFIG_SAL_USING_LWIP=y -# CONFIG_SAL_USING_POSIX is not set -CONFIG_SAL_SOCKETS_NUM=16 +CONFIG_SAL_USING_POSIX=y # # Network interface device @@ -283,6 +293,7 @@ CONFIG_NETDEV_IPV6=0 CONFIG_RT_USING_LWIP=y # CONFIG_RT_USING_LWIP141 is not set CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP203 is not set # CONFIG_RT_USING_LWIP212 is not set # CONFIG_RT_USING_LWIP_IPV6 is not set CONFIG_RT_LWIP_MEM_ALIGNMENT=8 @@ -352,6 +363,7 @@ CONFIG_RT_LWIP_USING_PING=y # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set # CONFIG_RT_USING_RT_LINK is not set # @@ -363,9 +375,15 @@ CONFIG_RT_LWIP_USING_PING=y # Board Drivers Config # CONFIG_BSP_USING_UART_HS=y + +# +# General Purpose UARTs +# CONFIG_BSP_USING_UART1=y CONFIG_BSP_UART1_TXD_PIN=20 CONFIG_BSP_UART1_RXD_PIN=21 +CONFIG_BSP_UART1_RTS_PIN=-1 +CONFIG_BSP_UART1_CTS_PIN=-1 # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_USING_I2C1 is not set @@ -385,6 +403,13 @@ CONFIG_BSP_LCD_CS_PIN=36 CONFIG_BSP_LCD_WR_PIN=39 CONFIG_BSP_LCD_DC_PIN=38 CONFIG_BSP_LCD_RST_PIN=37 +CONFIG_BSP_LCD_BACKLIGHT_PIN=-1 +CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_LOW=y +# CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_HIGH is not set +CONFIG_BSP_LCD_CLK_FREQ=20000000 +# CONFIG_BSP_BOARD_KD233 is not set +# CONFIG_BSP_BOARD_K210_OPENMV_TEST is not set +CONFIG_BSP_BOARD_USER=y CONFIG_BSP_LCD_X_MAX=240 CONFIG_BSP_LCD_Y_MAX=320 CONFIG_BSP_USING_SDCARD=y @@ -401,6 +426,9 @@ CONFIG_BSP_DVP_CMOS_PWDN_PIN=44 CONFIG_BSP_DVP_CMOS_XCLK_PIN=46 CONFIG_BSP_DVP_CMOS_PCLK_PIN=47 CONFIG_BSP_DVP_CMOS_HREF_PIN=45 +CONFIG_RW007_SPIDEV_NAME="spi11" +CONFIG_RW007_INT_BUSY_PIN=7 +CONFIG_RW007_RST_PIN=6 # # Kendryte SDK Config @@ -410,7 +438,10 @@ CONFIG_PKG_KENDRYTE_SDK_VERNUM=0x0055 # # More Drivers # -# CONFIG_PKG_USING_RW007 is not set +CONFIG_PKG_USING_RW007=y +CONFIG_RW007_NOT_USE_EXAMPLE_DRIVERS=y +# CONFIG_RW007_USING_STM32_DRIVERS is not set +CONFIG_RW007_SPI_MAX_HZ=20000000 CONFIG_DRV_USING_OV2640=y # @@ -443,12 +474,23 @@ CONFIG_MAIN_KTASK_STACK_SIZE=1024 # # knowing app # +CONFIG_APPLICATION_KNOWING=y +CONFIG_APP_MNIST=y CONFIG_FACE_DETECT=y +# CONFIG_INSTRUSION_DETECT is not set +# CONFIG_HELMET_DETECT is not set +# CONFIG_IRIS_ML_DEMO is not set # # sensor app # -# CONFIG_APPLICATION_SENSOR is not set +CONFIG_APPLICATION_SENSOR=y +# CONFIG_APPLICATION_SENSOR_CO2 is not set +# CONFIG_APPLICATION_SENSOR_PM1_0 is not set +CONFIG_APPLICATION_SENSOR_VOICE=y +CONFIG_APPLICATION_SENSOR_VOICE_D124=y +# CONFIG_APPLICATION_SENSOR_HUMIDITY is not set +# CONFIG_APPLICATION_SENSOR_TEMPERATURE is not set # # Framework @@ -460,19 +502,36 @@ CONFIG_ADD_XIUOS_FETURES=y CONFIG_SUPPORT_SENSOR_FRAMEWORK=y # CONFIG_SENSOR_CO2 is not set # CONFIG_SENSOR_PM is not set -# CONFIG_SENSOR_VOICE is not set +CONFIG_SENSOR_VOICE=y +CONFIG_SENSOR_D124=y +CONFIG_SENSOR_DEVICE_D124="d124_1" +CONFIG_SENSOR_QUANTITY_D124_VOICE="voice_1" +# CONFIG_SENSOR_D124_DRIVER_EXTUART is not set +CONFIG_SENSOR_DEVICE_D124_DEV="/dev/uar2" # CONFIG_SENSOR_TEMPERATURE is not set # CONFIG_SENSOR_HUMIDITY is not set # CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set CONFIG_SUPPORT_KNOWING_FRAMEWORK=y -# CONFIG_USING_TENSORFLOWLITEMICRO is not set +CONFIG_USING_TENSORFLOWLITEMICRO=y +CONFIG_USING_TENSORFLOWLITEMICRO_NORMAL=y +# CONFIG_USING_TENSORFLOWLITEMICRO_CMSISNN is not set +# CONFIG_USING_TENSORFLOWLITEMICRO_DEMOAPP is not set CONFIG_USING_KPU_POSTPROCESSING=y CONFIG_USING_YOLOV2=y +# CONFIG_USING_KNOWING_FILTER is not set +# CONFIG_USING_OTA_MODEL is not set # CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set # -# app lib +# Security +# +# CONFIG_CRYPTO is not set + +# +# lib # CONFIG_APP_SELECT_NEWLIB=y # CONFIG_APP_SELECT_OTHER_LIB is not set +CONFIG_LIB_USING_CJSON=y +# CONFIG_LIB_USING_QUEUE is not set CONFIG___STACKSIZE__=4096 diff --git a/Ubiquitous/RT_Thread/bsp/k210/applications/main.c b/Ubiquitous/RT_Thread/bsp/k210/applications/main.c index 45213d732..5b51e4275 100644 --- a/Ubiquitous/RT_Thread/bsp/k210/applications/main.c +++ b/Ubiquitous/RT_Thread/bsp/k210/applications/main.c @@ -1,3 +1,11 @@ +/* + * @Author: your name + * @Date: 2021-10-11 22:04:25 + * @LastEditTime: 2021-10-14 11:12:52 + * @LastEditors: Please set LastEditors + * @Description: In User Settings Edit + * @FilePath: \xiuos\Ubiquitous\RT_Thread\bsp\k210\applications\main.c + */ /* * Copyright (c) 2020 AIIT XUOS Lab * XiUOS is licensed under Mulan PSL v2. @@ -21,14 +29,13 @@ int main(void) rt_thread_mdelay(100); char info1[25] ={0}; char info2[25] ={0}; - sprintf(info1,"xuos-intelligence k210 build "); - sprintf(info2,"%s %s",__DATE__,__TIME__); + sprintf(info1,"xuos-intelligence k210 "); + sprintf(info2,"build %s %s",__DATE__,__TIME__); printf("%s %s \n",info1,info2); #ifdef BSP_USING_LCD #include - lcd_clear(PINK); - lcd_draw_string(70,100,info1,BLACK); - lcd_draw_string(70,120,info2,BLACK); + lcd_show_string(0,60,24,info1); + lcd_show_string(0,90,24,info2); #endif while(1) { diff --git a/Ubiquitous/RT_Thread/bsp/k210/applications/ov2640_test.c b/Ubiquitous/RT_Thread/bsp/k210/applications/ov2640_test.c index b9401ff08..b5027c7e4 100644 --- a/Ubiquitous/RT_Thread/bsp/k210/applications/ov2640_test.c +++ b/Ubiquitous/RT_Thread/bsp/k210/applications/ov2640_test.c @@ -21,10 +21,10 @@ static int g_fd = 0; static _ioctl_shoot_para shoot_para_t = {0}; - +extern void lcd_show_image(int x, int y, int wide, int height,const rt_uint8_t *buf); +extern void lcd_draw_picture(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height, uint32_t *ptr); void ov2640_test(int argc, char **argv) { - extern void lcd_draw_picture(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height, uint32_t *ptr); g_fd = open("/dev/ov2640",O_RDONLY); if(g_fd < 0) @@ -71,7 +71,7 @@ void ov2640_test(int argc, char **argv) close(g_fd); return; } - lcd_draw_picture(0, 0, 320, 240, rgbbuffer); + lcd_show_image(0, 0, 320, 240, rgbbuffer); rt_thread_mdelay(100); printf("the lcd has shown the image \n"); rt_free(rgbbuffer); @@ -82,7 +82,6 @@ MSH_CMD_EXPORT(ov2640_test,lcd show camera shot image); void lcd_show_ov2640_thread(uint32_t* rgbbuffer) { - extern void lcd_draw_picture(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height, uint32_t *ptr); rt_err_t ret = 0; while(1) { @@ -94,8 +93,9 @@ void lcd_show_ov2640_thread(uint32_t* rgbbuffer) rt_free(rgbbuffer); return; } + //lcd_show_image(0, 0, 320, 240, rgbbuffer); lcd_draw_picture(0, 0, 320, 240, rgbbuffer); - rt_thread_mdelay(2); + rt_thread_mdelay(1); } } diff --git a/Ubiquitous/RT_Thread/bsp/k210/base-drivers/Kconfig b/Ubiquitous/RT_Thread/bsp/k210/base-drivers/Kconfig index 060bd2064..57e84d54f 100644 --- a/Ubiquitous/RT_Thread/bsp/k210/base-drivers/Kconfig +++ b/Ubiquitous/RT_Thread/bsp/k210/base-drivers/Kconfig @@ -5,6 +5,7 @@ config BSP_USING_UART_HS default y +menu "General Purpose UARTs" menuconfig BSP_USING_UART1 bool "Enable UART1" default n @@ -15,6 +16,12 @@ menuconfig BSP_USING_UART1 config BSP_UART1_RXD_PIN int "uart1 RXD pin number" default 21 + config BSP_UART1_RTS_PIN + int "uart1 RTS pin number (-1 for not used)" + default -1 + config BSP_UART1_CTS_PIN + int "uart1 CTS pin number (-1 for not used)" + default -1 endif menuconfig BSP_USING_UART2 @@ -27,6 +34,12 @@ menuconfig BSP_USING_UART2 config BSP_UART2_RXD_PIN int "uart2 RXD pin number" default 27 + config BSP_UART2_RTS_PIN + int "uart2 RTS pin number (-1 for not used)" + default -1 + config BSP_UART2_CTS_PIN + int "uart2 CTS pin number (-1 for not used)" + default -1 endif menuconfig BSP_USING_UART3 @@ -39,7 +52,14 @@ menuconfig BSP_USING_UART3 config BSP_UART3_RXD_PIN int "uart3 RXD pin number" default 23 + config BSP_UART3_RTS_PIN + int "uart3 RTS pin number (-1 for not used)" + default -1 + config BSP_UART3_CTS_PIN + int "uart3 CTS pin number (-1 for not used)" + default -1 endif +endmenu config BSP_USING_I2C1 bool "Enable I2C1 (GPIO0/1)" @@ -119,9 +139,40 @@ if BSP_USING_LCD config BSP_LCD_DC_PIN int "DC pin number of 8080 interface" default 38 - config BSP_LCD_RST_PIN - int "RST pin number of 8080 interface" + config BSP_LCD_RST_PIN + int "RESET pin number of 8080 interface (-1 for not used)" default 37 + config BSP_LCD_BACKLIGHT_PIN + int "Backlight control pin number (-1 for not used)" + default -1 + choice + prompt "backlight active polarity" + default BSP_LCD_BACKLIGHT_ACTIVE_LOW + + config BSP_LCD_BACKLIGHT_ACTIVE_LOW + bool "lcd backlight on low level" + config BSP_LCD_BACKLIGHT_ACTIVE_HIGH + bool "lcd_backlight on high level" + endchoice + + config BSP_LCD_CLK_FREQ + int "Lcd max clk frequency" + default 15000000 + + choice + prompt "lcd scan direction" + default BSP_BOARD_KD233 + + config BSP_BOARD_KD233 + bool "board_kd233 lcd scan: DIR_YX_RLUD" + + config BSP_BOARD_K210_OPENMV_TEST + bool "board_k210_openmv lcd scan: DIR_YX_LRUD" + + config BSP_BOARD_USER + bool "board_user: user defined." + endchoice + config BSP_LCD_X_MAX int "LCD Height" default 240 diff --git a/Ubiquitous/RT_Thread/bsp/k210/base-drivers/SConscript b/Ubiquitous/RT_Thread/bsp/k210/base-drivers/SConscript index 233d649de..5523339bf 100644 --- a/Ubiquitous/RT_Thread/bsp/k210/base-drivers/SConscript +++ b/Ubiquitous/RT_Thread/bsp/k210/base-drivers/SConscript @@ -5,28 +5,26 @@ from building import * cwd = GetCurrentDir() drv_path = cwd+"/../../../rt-thread/bsp/k210/driver/" src = [ - drv_path + 'board.c', - drv_path + 'heap.c', + 'board.c', + 'heap.c', drv_path + 'drv_uart.c', - drv_path + 'drv_interrupt.c', - 'drv_io_config.c' + 'drv_interrupt.c', + 'drv_io_config.c', + 'dmalock.c' ] CPPPATH = [cwd,drv_path] if GetDepend('RT_USING_PIN'): - src += [drv_path + 'drv_gpio.c'] + src += ['drv_gpio.c'] if GetDepend('RT_USING_HWTIMER'): src += [drv_path + 'drv_hw_timer.c'] -if GetDepend('RT_USING_CPUTIME'): - src += [drv_path + 'drv_cputime.c'] - if GetDepend('RT_USING_I2C'): src += [drv_path + 'drv_i2c.c'] if GetDepend('RT_USING_SPI'): - src += [drv_path + 'drv_spi.c'] + src += ['drv_spi.c'] if GetDepend('RT_USING_PWM'): src += [drv_path + 'drv_pwm.c'] @@ -42,6 +40,7 @@ if GetDepend('BSP_USING_DVP'): if GetDepend('BSP_USING_LCD'): src += ['drv_lcd.c'] + src += ['drv_mpylcd.c'] if GetDepend('PKG_USING_RW007'): src += ['rw007_port.c'] diff --git a/Ubiquitous/RT_Thread/bsp/k210/base-drivers/drv_io_config.c b/Ubiquitous/RT_Thread/bsp/k210/base-drivers/drv_io_config.c index 56c1e07d9..b2a0a5a3d 100644 --- a/Ubiquitous/RT_Thread/bsp/k210/base-drivers/drv_io_config.c +++ b/Ubiquitous/RT_Thread/bsp/k210/base-drivers/drv_io_config.c @@ -6,7 +6,6 @@ * Change Logs: * Date Author Notes * 2019-03-19 ZYH first version - * 2021-01-28 tianchunyu Modify macro definitions */ #include @@ -24,7 +23,18 @@ static struct io_config fpioa_function_t func; const char * func_name; } io_config[] = -{ +{ +#ifdef BSP_USING_LCD + IOCONFIG(BSP_LCD_CS_PIN, FUNC_SPI0_SS0), /* LCD CS PIN */ + IOCONFIG(BSP_LCD_WR_PIN, FUNC_SPI0_SCLK), /* LCD WR PIN */ + IOCONFIG(BSP_LCD_DC_PIN, HS_GPIO(LCD_DC_PIN)), /* LCD DC PIN */ +#if BSP_LCD_RST_PIN >= 0 + IOCONFIG(BSP_LCD_RST_PIN, HS_GPIO(LCD_RST_PIN)), /* LCD RESET PIN */ +#endif +#if BSP_LCD_BACKLIGHT_PIN >= 0 + IOCONFIG(BSP_LCD_BACKLIGHT_PIN, HS_GPIO(LCD_BACKLIGHT_PIN)), /* LCD BACKLIGHT PIN */ +#endif +#endif #ifdef BSP_USING_DVP IOCONFIG(BSP_DVP_SCCB_SDA_PIN, FUNC_SCCB_SDA), @@ -37,13 +47,6 @@ static struct io_config IOCONFIG(BSP_DVP_CMOS_HREF_PIN, FUNC_CMOS_HREF), #endif -#if 0 //here is a drv lcd bug now don't know why - IOCONFIG(BSP_LCD_CS_PIN, FUNC_SPI0_SS3), /* LCD CS PIN */ - IOCONFIG(BSP_LCD_WR_PIN, FUNC_SPI0_SCLK), /* LCD WR PIN */ - IOCONFIG(BSP_LCD_DC_PIN, FUNC_GPIOHS2), /* LCD DC PIN */ - IOCONFIG(BSP_LCD_RST_PIN,FUNC_GPIOHS3), /* LCD DC PIN */ -#endif - #ifdef BSP_USING_SPI1 IOCONFIG(BSP_SPI1_CLK_PIN, FUNC_SPI1_SCLK), IOCONFIG(BSP_SPI1_D0_PIN, FUNC_SPI1_D0), @@ -69,14 +72,72 @@ static struct io_config #ifdef BSP_USING_UART1 IOCONFIG(BSP_UART1_TXD_PIN, FUNC_UART1_TX), IOCONFIG(BSP_UART1_RXD_PIN, FUNC_UART1_RX), + #if BSP_UART1_RTS_PIN >= 0 + IOCONFIG(BSP_UART1_RTS_PIN, FUNC_UART1_RTS), + #endif + #if BSP_UART1_CTS_PIN >= 0 + IOCONFIG(BSP_UART1_CTS_PIN, FUNC_UART1_CTS), + #endif #endif #ifdef BSP_USING_UART2 IOCONFIG(BSP_UART2_TXD_PIN, FUNC_UART2_TX), IOCONFIG(BSP_UART2_RXD_PIN, FUNC_UART2_RX), + #if BSP_UART2_RTS_PIN >= 0 + IOCONFIG(BSP_UART2_RTS_PIN, FUNC_UART2_RTS), + #endif + #if BSP_UART2_CTS_PIN >= 0 + IOCONFIG(BSP_UART2_CTS_PIN, FUNC_UART2_CTS), + #endif #endif #ifdef BSP_USING_UART3 IOCONFIG(BSP_UART3_TXD_PIN, FUNC_UART3_TX), IOCONFIG(BSP_UART3_RXD_PIN, FUNC_UART3_RX), + #if BSP_UART3_RTS_PIN >= 0 + IOCONFIG(BSP_UART3_RTS_PIN, FUNC_UART3_RTS), + #endif + #if BSP_UART3_CTS_PIN >= 0 + IOCONFIG(BSP_UART3_CTS_PIN, FUNC_UART3_CTS), + #endif +#endif +#ifdef BSP_USING_I2C0 + IOCONFIG(BSP_I2C0_SCL_PIN, FUNC_I2C0_SCLK), + IOCONFIG(BSP_I2C0_SDA_PIN, FUNC_I2C0_SDA), +#endif +#ifdef BSP_USING_I2C1 + IOCONFIG(BSP_I2C1_SCL_PIN, FUNC_I2C1_SCLK), + IOCONFIG(BSP_I2C1_SDA_PIN, FUNC_I2C1_SDA), +#endif +#ifdef BSP_USING_I2C2 + IOCONFIG(BSP_I2C2_SCL_PIN, FUNC_I2C2_SCLK), + IOCONFIG(BSP_I2C2_SDA_PIN, FUNC_I2C2_SDA), +#endif +#ifdef BSP_USING_I2S0 + IOCONFIG(BSP_I2S0_OUT_D1_PIN, FUNC_I2S0_OUT_D1), + IOCONFIG(BSP_I2S0_WS_PIN, FUNC_I2S0_WS), + IOCONFIG(BSP_I2S0_SCLK_PIN, FUNC_I2S0_SCLK), +#endif +#ifdef BSP_USING_I2S1 + IOCONFIG(BSP_I2S1_IN_D0_PIN, FUNC_I2S1_IN_D0), + IOCONFIG(BSP_I2S1_WS_PIN, FUNC_I2S1_WS), + IOCONFIG(BSP_I2S1_SCLK_PIN, FUNC_I2S1_SCLK), +#endif +#ifdef BSP_USING_I2S2 + IOCONFIG(BSP_I2S2_OUT_D1_PIN, FUNC_I2S2_OUT_D1), + IOCONFIG(BSP_I2S2_WS_PIN, FUNC_I2S2_WS), + IOCONFIG(BSP_I2S2_SCLK_PIN, FUNC_I2S2_SCLK), +#endif + +#ifdef BSP_PWM_CHN0_ENABLE + IOCONFIG(BSP_PWM_CHN0_PIN, FUNC_TIMER2_TOGGLE1), +#endif +#ifdef BSP_PWM_CHN1_ENABLE + IOCONFIG(BSP_PWM_CHN1_PIN, FUNC_TIMER2_TOGGLE2), +#endif +#ifdef BSP_PWM_CHN2_ENABLE + IOCONFIG(BSP_PWM_CHN2_PIN, FUNC_TIMER2_TOGGLE3), +#endif +#ifdef BSP_PWM_CHN3_ENABLE + IOCONFIG(BSP_PWM_CHN3_PIN, FUNC_TIMER2_TOGGLE4), #endif }; @@ -101,16 +162,35 @@ int io_config_init(void) int count = sizeof(io_config) / sizeof(io_config[0]); int i; +/* IO GroupA Power Supply Setting */ +#if defined(BSP_GROUPA_POWER_SUPPLY_3V3) + sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V33); + sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V33); + sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V33); +#else sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V18); sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V18); sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V18); -#ifdef BSP_USING_UART2 - // for IO-27/28 - sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V33); #endif -#if defined(BSP_USING_UART1) || defined(BSP_USING_UART3) - // for IO-20~23 + +/* IO GroupB Power Supply Setting */ +#if defined(BSP_GROUPB_POWER_SUPPLY_3V3) sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V33); + sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V33); + sysctl_set_power_mode(SYSCTL_POWER_BANK5, SYSCTL_POWER_V33); +#else + sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V18); + sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V18); + sysctl_set_power_mode(SYSCTL_POWER_BANK5, SYSCTL_POWER_V18); +#endif + +/* IO GroupC Power Supply Setting */ +#if defined(BSP_GROUPC_POWER_SUPPLY_3V3) + sysctl_set_power_mode(SYSCTL_POWER_BANK6, SYSCTL_POWER_V33); + sysctl_set_power_mode(SYSCTL_POWER_BANK7, SYSCTL_POWER_V33); +#else + sysctl_set_power_mode(SYSCTL_POWER_BANK6, SYSCTL_POWER_V18); + sysctl_set_power_mode(SYSCTL_POWER_BANK7, SYSCTL_POWER_V18); #endif for(i = 0; i < count; i++) @@ -120,12 +200,20 @@ int io_config_init(void) #if defined(BSP_USING_DVP) || defined(BSP_USING_LCD) sysctl_set_spi0_dvp_data(1); - sysctl_set_power_mode(SYSCTL_POWER_BANK6, SYSCTL_POWER_V18); - sysctl_set_power_mode(SYSCTL_POWER_BANK7, SYSCTL_POWER_V18); -#endif -#ifdef FACE_DETECT sysctl_clock_enable(SYSCTL_CLOCK_AI); #endif } -INIT_BOARD_EXPORT(io_config_init); +int io_config_used(int io_num) +{ + int count = sizeof(io_config) / sizeof(io_config[0]); + int i; + + for(i = 0; i < count; i++) + { + if (io_config[i].io_num == io_num) + break; + } + + return (i < count); +} diff --git a/Ubiquitous/RT_Thread/bsp/k210/base-drivers/drv_io_config.h b/Ubiquitous/RT_Thread/bsp/k210/base-drivers/drv_io_config.h index 78db1d8c6..1b725e9e8 100644 --- a/Ubiquitous/RT_Thread/bsp/k210/base-drivers/drv_io_config.h +++ b/Ubiquitous/RT_Thread/bsp/k210/base-drivers/drv_io_config.h @@ -11,10 +11,18 @@ #ifndef __DRV_IO_CONFIG_H__ #define __DRV_IO_CONFIG_H__ +#include + enum HS_GPIO_CONFIG { #ifdef BSP_USING_LCD LCD_DC_PIN = 0, /* LCD DC PIN */ +#if BSP_LCD_RST_PIN >= 0 + LCD_RST_PIN, +#endif +#if BSP_LCD_BACKLIGHT_PIN >= 0 + LCD_BACKLIGHT_PIN, +#endif #endif #ifdef BSP_SPI1_USING_SS0 SPI1_CS0_PIN, @@ -28,6 +36,11 @@ enum HS_GPIO_CONFIG #ifdef BSP_SPI1_USING_SS3 SPI1_CS3_PIN, #endif + +#ifdef BSP_USING_BRIDGE + SPI2_INT_PIN, + SPI2_READY_PIN, +#endif GPIO_ALLOC_START /* index of gpio driver start */ }; diff --git a/Ubiquitous/RT_Thread/bsp/k210/base-drivers/drv_lcd.c b/Ubiquitous/RT_Thread/bsp/k210/base-drivers/drv_lcd.c index 4b6146223..933bd7290 100644 --- a/Ubiquitous/RT_Thread/bsp/k210/base-drivers/drv_lcd.c +++ b/Ubiquitous/RT_Thread/bsp/k210/base-drivers/drv_lcd.c @@ -1,16 +1,11 @@ -/* Copyright 2018 Canaan Inc. +/* + * Copyright (c) 2006-2018, RT-Thread Development Team * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * SPDX-License-Identifier: Apache-2.0 * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * Change Logs: + * Date Author Notes + * 2019-03-12 ZYH first version */ @@ -18,314 +13,538 @@ #ifdef BSP_USING_LCD #include -#include -#include -#include -#include -#include #define DBG_TAG "LCD" -#define DBG_LVL DBG_LOG +#define DBG_LVL DBG_WARNING #include +#define NO_OPERATION 0x00 +#define SOFTWARE_RESET 0x01 +#define READ_ID 0x04 +#define READ_STATUS 0x09 +#define READ_POWER_MODE 0x0A +#define READ_MADCTL 0x0B +#define READ_PIXEL_FORMAT 0x0C +#define READ_IMAGE_FORMAT 0x0D +#define READ_SIGNAL_MODE 0x0E +#define READ_SELT_DIAG_RESULT 0x0F +#define SLEEP_ON 0x10 +#define SLEEP_OFF 0x11 +#define PARTIAL_DISPALY_ON 0x12 +#define NORMAL_DISPALY_ON 0x13 +#define INVERSION_DISPALY_OFF 0x20 +#define INVERSION_DISPALY_ON 0x21 +#define GAMMA_SET 0x26 +#define DISPALY_OFF 0x28 +#define DISPALY_ON 0x29 +#define HORIZONTAL_ADDRESS_SET 0x2A +#define VERTICAL_ADDRESS_SET 0x2B +#define MEMORY_WRITE 0x2C +#define COLOR_SET 0x2D +#define MEMORY_READ 0x2E +#define PARTIAL_AREA 0x30 +#define VERTICAL_SCROL_DEFINE 0x33 +#define TEAR_EFFECT_LINE_OFF 0x34 +#define TEAR_EFFECT_LINE_ON 0x35 +#define MEMORY_ACCESS_CTL 0x36 +#define VERTICAL_SCROL_S_ADD 0x37 +#define IDLE_MODE_OFF 0x38 +#define IDLE_MODE_ON 0x39 +#define PIXEL_FORMAT_SET 0x3A +#define WRITE_MEMORY_CONTINUE 0x3C +#define READ_MEMORY_CONTINUE 0x3E +#define SET_TEAR_SCANLINE 0x44 +#define GET_SCANLINE 0x45 +#define WRITE_BRIGHTNESS 0x51 +#define READ_BRIGHTNESS 0x52 +#define WRITE_CTRL_DISPALY 0x53 +#define READ_CTRL_DISPALY 0x54 +#define WRITE_BRIGHTNESS_CTL 0x55 +#define READ_BRIGHTNESS_CTL 0x56 +#define WRITE_MIN_BRIGHTNESS 0x5E +#define READ_MIN_BRIGHTNESS 0x5F +#define READ_ID1 0xDA +#define READ_ID2 0xDB +#define READ_ID3 0xDC +#define RGB_IF_SIGNAL_CTL 0xB0 +#define NORMAL_FRAME_CTL 0xB1 +#define IDLE_FRAME_CTL 0xB2 +#define PARTIAL_FRAME_CTL 0xB3 +#define INVERSION_CTL 0xB4 +#define BLANK_PORCH_CTL 0xB5 +#define DISPALY_FUNCTION_CTL 0xB6 +#define ENTRY_MODE_SET 0xB7 +#define BACKLIGHT_CTL1 0xB8 +#define BACKLIGHT_CTL2 0xB9 +#define BACKLIGHT_CTL3 0xBA +#define BACKLIGHT_CTL4 0xBB +#define BACKLIGHT_CTL5 0xBC +#define BACKLIGHT_CTL7 0xBE +#define BACKLIGHT_CTL8 0xBF +#define POWER_CTL1 0xC0 +#define POWER_CTL2 0xC1 +#define VCOM_CTL1 0xC5 +#define VCOM_CTL2 0xC7 +#define NV_MEMORY_WRITE 0xD0 +#define NV_MEMORY_PROTECT_KEY 0xD1 +#define NV_MEMORY_STATUS_READ 0xD2 +#define READ_ID4 0xD3 +#define POSITIVE_GAMMA_CORRECT 0xE0 +#define NEGATIVE_GAMMA_CORRECT 0xE1 +#define DIGITAL_GAMMA_CTL1 0xE2 +#define DIGITAL_GAMMA_CTL2 0xE3 +#define INTERFACE_CTL 0xF6 + +#define LCD_SPI_CHANNEL SPI_DEVICE_0 +#define LCD_SPI_CHIP_SELECT SPI_CHIP_SELECT_0 + +#if defined(BSP_BOARD_K210_OPENMV_TEST) +#define LCD_SCAN_DIR DIR_YX_LRUD +#elif defined(BSP_BOARD_KD233) +#define LCD_SCAN_DIR (DIR_YX_RLUD | 0x08) +#elif defined(BSP_BOARD_USER) +/*user define.*/ +#define LCD_SCAN_DIR DIR_YX_RLDU +#endif -static lcd_ctl_t lcd_ctl; -static void init_dcx(void) +static struct lcd_8080_device _lcddev; + +static void drv_lcd_cmd(lcd_8080_device_t lcd, rt_uint8_t cmd) { - gpiohs_set_drive_mode(DCX_GPIONUM, GPIO_DM_OUTPUT); - gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_HIGH); + gpiohs_set_pin(lcd->dc_pin, GPIO_PV_LOW); + spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0); + spi_init_non_standard(lcd->spi_channel, 8 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/, + SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/); + spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, &cmd, 1, SPI_TRANS_CHAR); } -static void set_dcx_control(void) +static void drv_lcd_data_byte(lcd_8080_device_t lcd, rt_uint8_t *data_buf, rt_uint32_t length) { - gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_LOW); + gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH); + spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0); + spi_init_non_standard(lcd->spi_channel, 8 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/, + SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/); + spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_CHAR); } -static void set_dcx_data(void) +void drv_lcd_data_half_word(lcd_8080_device_t lcd, rt_uint16_t *data_buf, rt_uint32_t length) { - gpiohs_set_pin(DCX_GPIONUM, GPIO_PV_HIGH); + gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH); + spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 16, 0); + spi_init_non_standard(lcd->spi_channel, 16 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/, + SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/); + spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_SHORT); } - -static void init_rst(void) +void drv_lcd_data_word(lcd_8080_device_t lcd, rt_uint32_t *data_buf, rt_uint32_t length) { - gpiohs_set_drive_mode(RST_GPIONUM, GPIO_DM_OUTPUT); - gpiohs_set_pin(RST_GPIONUM, GPIO_PV_LOW); - rt_thread_mdelay(10); - gpiohs_set_pin(RST_GPIONUM, GPIO_PV_HIGH); - rt_thread_mdelay(10); + gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH); + spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0); + spi_init_non_standard(lcd->spi_channel, 0 /*instrction length*/, 32 /*address length*/, 0 /*wait cycles*/, + SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/); + spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_INT); } - -void tft_hard_init(void) +static void drv_lcd_hw_init(lcd_8080_device_t lcd) { - init_dcx(); - spi_init(SPI_CHANNEL, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0); - init_rst(); - spi_set_clk_rate(SPI_CHANNEL, 20000000); +#if BSP_LCD_RST_PIN >= 0 + { + gpiohs_set_drive_mode(lcd->rst_pin, GPIO_DM_OUTPUT); + gpiohs_set_pin(lcd->rst_pin, GPIO_PV_LOW); + rt_thread_mdelay(20); + gpiohs_set_pin(lcd->rst_pin, GPIO_PV_HIGH); + rt_thread_mdelay(20); + } +#endif +#if BSP_LCD_BACKLIGHT_PIN >= 0 + { + gpiohs_set_drive_mode(lcd->backlight_pin, GPIO_DM_OUTPUT); +#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW) + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW); +#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH) + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH); +#else + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW); +#endif + } +#endif + + gpiohs_set_drive_mode(lcd->dc_pin, GPIO_DM_OUTPUT); + gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH); + spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0); + spi_set_clk_rate(lcd->spi_channel, BSP_LCD_CLK_FREQ); } -void tft_write_command(uint8_t cmd) +static void drv_lcd_set_direction(lcd_8080_device_t lcd, lcd_dir_t dir) { - set_dcx_control(); - spi_init(SPI_CHANNEL, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0); - spi_init_non_standard(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, - SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT, (uint8_t *)(&cmd), 1,SPI_TRANS_CHAR); -} - -void tft_write_byte(uint8_t *data_buf, uint32_t length) -{ - set_dcx_data(); - spi_init(SPI_CHANNEL, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0); - spi_init_non_standard(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, - SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT, data_buf, length, SPI_TRANS_CHAR); -} - -void tft_write_half(uint16_t *data_buf, uint32_t length) -{ - set_dcx_data(); - spi_init(SPI_CHANNEL, SPI_WORK_MODE_0, SPI_FF_OCTAL, 16, 0); - spi_init_non_standard(SPI_CHANNEL, 16/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, - SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_SHORT); -} - -void tft_write_word(uint32_t *data_buf, uint32_t length, uint32_t flag) -{ - set_dcx_data(); - spi_init(SPI_CHANNEL, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0); - - spi_init_non_standard(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, - SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_send_data_normal_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_INT); -} - -void tft_fill_data(uint32_t *data_buf, uint32_t length) -{ - set_dcx_data(); - spi_init(SPI_CHANNEL, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0); - spi_init_non_standard(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, - SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/); - spi_fill_data_dma(DMAC_CHANNEL0, SPI_CHANNEL, SPI_SLAVE_SELECT,data_buf, length); -} - -void lcd_polling_enable(void) -{ - lcd_ctl.mode = 0; -} - -void lcd_interrupt_enable(void) -{ - lcd_ctl.mode = 1; -} - -void lcd_pre() -{ - fpioa_set_function(37, FUNC_GPIOHS0 + RST_GPIONUM); - fpioa_set_function(38, FUNC_GPIOHS0 + DCX_GPIONUM); - fpioa_set_function(36, FUNC_SPI0_SS0 + LCD_SPI_SLAVE_SELECT); - fpioa_set_function(39, FUNC_SPI0_SCLK); -} - -int lcd_init(void) -{ - - uint8_t data = 0; - lcd_pre(); - tft_hard_init(); - /*soft reset*/ - tft_write_command(SOFTWARE_RESET); - rt_thread_mdelay(10); - /*exit sleep*/ - tft_write_command(SLEEP_OFF); - rt_thread_mdelay(10); - /*pixel format*/ - tft_write_command(PIXEL_FORMAT_SET); - data = 0x55; - tft_write_byte(&data, 1); - /*display on*/ - tft_write_command(DISPALY_ON); - lcd_polling_enable(); - lcd_clear(PINK); - lcd_set_direction(DIR_YX_RLDU); - LOG_I("LCD initialization successfully"); -} -INIT_APP_EXPORT(lcd_init); - - - -void lcd_set_direction(lcd_dir_t dir) -{ - lcd_ctl.dir = dir; if (dir & DIR_XY_MASK) { - lcd_ctl.width = LCD_Y_MAX - 1; - lcd_ctl.height = LCD_X_MAX - 1; + lcd->lcd_info.width = BSP_LCD_Y_MAX; + lcd->lcd_info.height = BSP_LCD_X_MAX; } else { - lcd_ctl.width = LCD_X_MAX - 1; - lcd_ctl.height = LCD_Y_MAX - 1; + lcd->lcd_info.width = BSP_LCD_X_MAX; + lcd->lcd_info.height = BSP_LCD_Y_MAX; } - - tft_write_command(MEMORY_ACCESS_CTL); - tft_write_byte((uint8_t *)&dir, 1); + rt_kprintf("lcd witdth %d,height %d \n",lcd->lcd_info.width,lcd->lcd_info.height); + drv_lcd_cmd(lcd, MEMORY_ACCESS_CTL); + drv_lcd_data_byte(lcd, (rt_uint8_t *)&dir, 1); } -void lcd_set_area(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2) + void drv_lcd_set_area(lcd_8080_device_t lcd, rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2) { - uint8_t data[4] = {0}; + rt_uint8_t data[4] = {0}; - data[0] = (uint8_t)(x1 >> 8); - data[1] = (uint8_t)(x1); - data[2] = (uint8_t)(x2 >> 8); - data[3] = (uint8_t)(x2); - tft_write_command(HORIZONTAL_ADDRESS_SET); - tft_write_byte(data, 4); + data[0] = (rt_uint8_t)(x1 >> 8); + data[1] = (rt_uint8_t)(x1); + data[2] = (rt_uint8_t)(x2 >> 8); + data[3] = (rt_uint8_t)(x2); + drv_lcd_cmd(lcd, HORIZONTAL_ADDRESS_SET); + drv_lcd_data_byte(lcd, data, 4); - data[0] = (uint8_t)(y1 >> 8); - data[1] = (uint8_t)(y1); - data[2] = (uint8_t)(y2 >> 8); - data[3] = (uint8_t)(y2); - tft_write_command(VERTICAL_ADDRESS_SET); - tft_write_byte(data, 4); + data[0] = (rt_uint8_t)(y1 >> 8); + data[1] = (rt_uint8_t)(y1); + data[2] = (rt_uint8_t)(y2 >> 8); + data[3] = (rt_uint8_t)(y2); + drv_lcd_cmd(lcd, VERTICAL_ADDRESS_SET); + drv_lcd_data_byte(lcd, data, 4); - tft_write_command(MEMORY_WRITE); + drv_lcd_cmd(lcd, MEMORY_WRITE); } -void lcd_draw_point(uint16_t x, uint16_t y, uint16_t color) +static void drv_lcd_set_pixel(lcd_8080_device_t lcd, uint16_t x, uint16_t y, uint16_t color) { - lcd_set_area(x, y, x, y); - tft_write_half(&color, 1); + drv_lcd_set_area(lcd, x, y, x, y); + drv_lcd_data_half_word(lcd, &color, 1); } -void lcd_draw_char(uint16_t x, uint16_t y, char c, uint16_t color) -{ - uint8_t i = 0; - uint8_t j = 0; - uint8_t data = 0; - - for (i = 0; i < 16; i++) - { - data = ascii0816[c * 16 + i]; - for (j = 0; j < 8; j++) - { - if (data & 0x80) - lcd_draw_point(x + j, y, color); - data <<= 1; - } - y++; - } -} - -void lcd_draw_string(uint16_t x, uint16_t y, char *str, uint16_t color) -{ - while (*str) - { - lcd_draw_char(x, y, *str, color); - str++; - x += 8; - } -} - -void lcd_ram_draw_string(char *str, uint32_t *ptr, uint16_t font_color, uint16_t bg_color) -{ - uint8_t i = 0; - uint8_t j = 0; - uint8_t data = 0; - uint8_t *pdata = NULL; - uint16_t width = 0; - uint32_t *pixel = NULL; - - width = 4 * strlen(str); - while (*str) - { - pdata = (uint8_t *)&ascii0816[(*str) * 16]; - for (i = 0; i < 16; i++) - { - data = *pdata++; - pixel = ptr + i * width; - for (j = 0; j < 4; j++) - { - switch (data >> 6) - { - case 0: - *pixel = ((uint32_t)bg_color << 16) | bg_color; - break; - case 1: - *pixel = ((uint32_t)bg_color << 16) | font_color; - break; - case 2: - *pixel = ((uint32_t)font_color << 16) | bg_color; - break; - case 3: - *pixel = ((uint32_t)font_color << 16) | font_color; - break; - default: - *pixel = 0; - break; - } - data <<= 2; - pixel++; - } - } - str++; - ptr += 4; - } -} - -void lcd_clear(uint16_t color) +static void drv_lcd_clear(lcd_8080_device_t lcd, uint16_t color) { uint32_t data = ((uint32_t)color << 16) | (uint32_t)color; - lcd_set_area(0, 0, lcd_ctl.width, lcd_ctl.height); - tft_fill_data(&data, LCD_X_MAX * LCD_Y_MAX / 2); + drv_lcd_set_area(lcd, 0, 0, lcd->lcd_info.width - 1, lcd->lcd_info.height - 1); + gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH); + spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0); + spi_init_non_standard(lcd->spi_channel, 0 /*instrction length*/, 32 /*address length*/, 0 /*wait cycles*/, + SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/); + spi_fill_data_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, (const uint32_t *)&data, lcd->lcd_info.width * lcd->lcd_info.height / 2); } -void lcd_draw_rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t width, uint16_t color) +static void rt_bitblt(rt_uint16_t * dest, int dest_segment, int dest_common, int dest_x, int dest_y, int width, int height, + rt_uint16_t *src, int src_segment, int src_common, int src_x, int src_y) { - uint32_t data_buf[640] = {0}; - uint32_t *p = data_buf; - uint32_t data = color; - uint32_t index = 0; + int sx0, sx1, sy0, sy1; + int dx0, dx1, dy0, dy1; + rt_uint16_t *buff_src; + rt_uint16_t *buff_dest; + int x, y; - data = (data << 16) | data; - for (index = 0; index < 160 * width; index++) - *p++ = data; + if (width <= 0) { + return; + } + if (height <= 0) { + return; + } - lcd_set_area(x1, y1, x2, y1 + width - 1); - tft_write_word(data_buf, ((x2 - x1 + 1) * width + 1) / 2, 0); - lcd_set_area(x1, y2 - width + 1, x2, y2); - tft_write_word(data_buf, ((x2 - x1 + 1) * width + 1) / 2, 0); - lcd_set_area(x1, y1, x1 + width - 1, y2); - tft_write_word(data_buf, ((y2 - y1 + 1) * width + 1) / 2, 0); - lcd_set_area(x2 - width + 1, y1, x2, y2); - tft_write_word(data_buf, ((y2 - y1 + 1) * width + 1) / 2, 0); + sx0 = src_x; + sy0 = src_y; + sx1 = sx0 + width - 1; + sy1 = sy0 + height - 1; + dx0 = dest_x; + dy0 = dest_y; + dx1 = dx0 + width - 1; + dy1 = dy0 + height - 1; + + if (sx0 < 0) { + dx0 -= sx0; + sx0 = 0; + } + if (sy0 < 0) { + dy0 -= sy0; + sy0 = 0; + } + if (sx1 >= src_segment) { + dx1 -= (sx1 - src_segment + 1); + sx1 = src_segment - 1; + } + if (sy1 >= src_common) { + dy1 -= (sy1 - src_common + 1); + sy1 = src_common - 1; + } + + if (dx0 < 0) { + sx0 -= dx0; + dx0 = 0; + } + if (dy0 < 0) { + sy0 -= dy0; + dy0 = 0; + } + if (dx1 >= dest_segment) { + sx1 -= (dx1 - dest_segment + 1); + dx1 = dest_segment - 1; + } + if (dy1 >= dest_common) { + sy1 -= (dy1 - dest_common + 1); + dy1 = dest_common - 1; + } + + if (sx1 < 0 || sx0 >= src_segment) { + return; + } + if (sy1 < 0 || sy0 >= src_common) { + return; + } + if (dx1 < 0 || dx0 >= dest_segment) { + return; + } + if (dy1 < 0 || dy0 >= dest_common) { + return; + } + + if ((rt_ubase_t)dest < (rt_ubase_t)src) { + buff_src = src + (sy0 * src_segment) + sx0; + buff_dest = dest + (dy0 * dest_segment) + dx0; + for (y = sy0; y <= sy1; y++) { + src = buff_src; + dest = buff_dest; + for (x = sx0; x <= sx1; x++) { + *dest++ = *src++; + } + buff_src += src_segment; + buff_dest += dest_segment; + } + } else { + buff_src = src + (sy1 * src_segment) + sx1; + buff_dest = dest + (dy1 * dest_segment) + dx1; + for (y = sy1; y >= sy0; y--) { + src = buff_src; + dest = buff_dest; + for (x = sx1; x >= sx0; x--) { + *dest-- = *src--; + } + buff_src -= src_segment; + buff_dest -= dest_segment; + } + } } -void lcd_draw_picture(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height, uint32_t *ptr) +static void drv_lcd_rect_update(lcd_8080_device_t lcd, uint16_t x1, uint16_t y1, uint16_t width, uint16_t height) { - lcd_set_area(x1, y1, x1 + width - 1, y1 + height - 1); - tft_write_word(ptr, width * height / 2, lcd_ctl.mode ? 2 : 0); + static rt_uint16_t * rect_buffer = RT_NULL; + if(!rect_buffer) + { + rect_buffer = rt_malloc_align(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8), 64); + if(!rect_buffer) + { + return; + } + } + if(x1 == 0 && y1 == 0 && width == lcd->lcd_info.width && height == lcd->lcd_info.height) + { + drv_lcd_set_area(lcd, x1, y1, x1 + width - 1, y1 + height - 1); + drv_lcd_data_half_word(lcd, (rt_uint32_t *)lcd->lcd_info.framebuffer, width * height); + } + else + { + rt_bitblt(rect_buffer, width, height, 0, 0, width, height,(rt_uint16_t *)lcd->lcd_info.framebuffer, lcd->lcd_info.width, lcd->lcd_info.height, x1, y1); + drv_lcd_set_area(lcd, x1, y1, x1 + width - 1, y1 + height - 1); + drv_lcd_data_half_word(lcd, (rt_uint16_t *)rect_buffer, width * height); + } } - -void lcd_test0() +static rt_err_t drv_lcd_init(rt_device_t dev) { - char test[]={"xuos-intelligence framwork"}; - lcd_draw_string(0,0,test,BLUE); + rt_err_t ret = RT_EOK; + lcd_8080_device_t lcd = (lcd_8080_device_t)dev; + rt_uint8_t data = 0; + if(!lcd) + { + return RT_ERROR; + } + drv_lcd_hw_init(lcd); + /* reset LCD */ + drv_lcd_cmd(lcd, SOFTWARE_RESET); + rt_thread_mdelay(100); + + /* Enter normal status */ + drv_lcd_cmd(lcd, SLEEP_OFF); + rt_thread_mdelay(100); + + /* pixel format rgb565 */ + drv_lcd_cmd(lcd, PIXEL_FORMAT_SET); + data = 0x55; + drv_lcd_data_byte(lcd, &data, 1); + + /* set direction */ + drv_lcd_set_direction(lcd, LCD_SCAN_DIR); + + lcd->lcd_info.framebuffer = rt_malloc_align(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8), 64); + RT_ASSERT(lcd->lcd_info.framebuffer); + + uint16_t *framebuffer = (uint16_t *)(lcd->lcd_info.framebuffer); + for(uint32_t i=0; i<(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8))/2; i++) { + framebuffer[i] = BLACK; + } + /*display on*/ + drv_lcd_cmd(lcd, DISPALY_ON); + + /* set to black */ + drv_lcd_clear(lcd, BLACK); + return ret; } -MSH_CMD_EXPORT(lcd_test0,lcd show string); -void lcd_test1() +static rt_err_t drv_lcd_open(rt_device_t dev, rt_uint16_t oflag) { - lcd_clear(YELLOW); + /* Not need */ + + return RT_EOK; } -MSH_CMD_EXPORT(lcd_test1,lcd show string); +static rt_err_t drv_lcd_close(rt_device_t dev) +{ + + /* Not need */ + + return RT_EOK; +} + +static rt_size_t drv_lcd_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + + /* Not need */ + + return 0; +} + +static rt_size_t drv_lcd_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + + /* Not need */ + + return 0; +} + +static rt_err_t drv_lcd_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t ret = RT_EOK; + lcd_8080_device_t lcd = (lcd_8080_device_t)dev; + rt_base_t level; + struct rt_device_rect_info* rect_info = (struct rt_device_rect_info*)args; + + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + if(!rect_info) + { + LOG_E("RTGRAPHIC_CTRL_RECT_UPDATE error args"); + return -RT_ERROR; + } + drv_lcd_rect_update(lcd, rect_info->x, rect_info->y, rect_info->width, rect_info->height); + break; + +#if BSP_LCD_BACKLIGHT_PIN >= 0 + case RTGRAPHIC_CTRL_POWERON: +#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW) + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW); +#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH) + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH); +#else + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW); +#endif + break; + + case RTGRAPHIC_CTRL_POWEROFF: +#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW) + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH); +#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH) + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW); +#else + gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH); +#endif + break; +#endif /* BSP_LCD_BACKLIGHT_PIN >= 0 */ + + case RTGRAPHIC_CTRL_GET_INFO: + *(struct rt_device_graphic_info *)args = lcd->lcd_info; + break; + + case RTGRAPHIC_CTRL_SET_MODE: + ret = -RT_ENOSYS; + break; + case RTGRAPHIC_CTRL_GET_EXT: + ret = -RT_ENOSYS; + break; + default: + LOG_E("drv_lcd_control cmd: %d", cmd); + break; + } + + return ret; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops drv_lcd_ops = +{ + drv_lcd_init, + drv_lcd_open, + drv_lcd_close, + drv_lcd_read, + drv_lcd_write, + drv_lcd_control +}; +#endif + + +int rt_hw_lcd_init(void) +{ + rt_err_t ret = RT_EOK; + lcd_8080_device_t lcd_dev = &_lcddev; + + lcd_dev->cs = SPI_CHIP_SELECT_0; + lcd_dev->dc_pin = LCD_DC_PIN; +#if BSP_LCD_RST_PIN >= 0 + lcd_dev->rst_pin = LCD_RST_PIN; +#endif +#if BSP_LCD_BACKLIGHT_PIN >= 0 + lcd_dev->backlight_pin = LCD_BACKLIGHT_PIN; +#endif + dmalock_sync_take(&lcd_dev->dma_channel, RT_WAITING_FOREVER); + lcd_dev->spi_channel = SPI_DEVICE_0; + lcd_dev->lcd_info.bits_per_pixel = 16; + lcd_dev->lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; + + lcd_dev->parent.type = RT_Device_Class_Graphic; + lcd_dev->parent.rx_indicate = RT_NULL; + lcd_dev->parent.tx_complete = RT_NULL; + +#ifdef RT_USING_DEVICE_OPS + lcd_dev->parent.ops = &drv_lcd_ops; +#else + lcd_dev->parent.init = drv_lcd_init; + lcd_dev->parent.open = drv_lcd_open; + lcd_dev->parent.close = drv_lcd_close; + lcd_dev->parent.read = drv_lcd_read; + lcd_dev->parent.write = drv_lcd_write; + lcd_dev->parent.control = drv_lcd_control; +#endif + + lcd_dev->parent.user_data = RT_NULL; + + ret = rt_device_register(&lcd_dev->parent, "lcd", RT_DEVICE_FLAG_RDWR); + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_lcd_init); + +void lcd_set_direction(lcd_dir_t dir) +{ + drv_lcd_set_direction(&_lcddev, dir); +} #endif diff --git a/Ubiquitous/RT_Thread/bsp/k210/base-drivers/drv_lcd.h b/Ubiquitous/RT_Thread/bsp/k210/base-drivers/drv_lcd.h index 925780367..868c528ff 100644 --- a/Ubiquitous/RT_Thread/bsp/k210/base-drivers/drv_lcd.h +++ b/Ubiquitous/RT_Thread/bsp/k210/base-drivers/drv_lcd.h @@ -1,480 +1,43 @@ -/* Copyright 2018 Canaan Inc. +/* + * Copyright (c) 2006-2018, RT-Thread Development Team * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * SPDX-License-Identifier: Apache-2.0 * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + * Change Logs: + * Date Author Notes + * 2019-03-07 ZYH first version */ +#ifndef DRV_LCD_H__ +#define DRV_LCD_H__ +#include +#include +#include +#include +#include +#include +#include "dmalock.h" -#ifndef _DRV_LCD_H__ -#define _DRV_LCD_H__ - -#include -/* clang-format off */ -#define NO_OPERATION 0x00 -#define SOFTWARE_RESET 0x01 -#define READ_ID 0x04 -#define READ_STATUS 0x09 -#define READ_POWER_MODE 0x0A -#define READ_MADCTL 0x0B -#define READ_PIXEL_FORMAT 0x0C -#define READ_IMAGE_FORMAT 0x0D -#define READ_SIGNAL_MODE 0x0E -#define READ_SELT_DIAG_RESULT 0x0F -#define SLEEP_ON 0x10 -#define SLEEP_OFF 0x11 -#define PARTIAL_DISPALY_ON 0x12 -#define NORMAL_DISPALY_ON 0x13 -#define INVERSION_DISPALY_OFF 0x20 -#define INVERSION_DISPALY_ON 0x21 -#define GAMMA_SET 0x26 -#define DISPALY_OFF 0x28 -#define DISPALY_ON 0x29 -#define HORIZONTAL_ADDRESS_SET 0x2A -#define VERTICAL_ADDRESS_SET 0x2B -#define MEMORY_WRITE 0x2C -#define COLOR_SET 0x2D -#define MEMORY_READ 0x2E -#define PARTIAL_AREA 0x30 -#define VERTICAL_SCROL_DEFINE 0x33 -#define TEAR_EFFECT_LINE_OFF 0x34 -#define TEAR_EFFECT_LINE_ON 0x35 -#define MEMORY_ACCESS_CTL 0x36 -#define VERTICAL_SCROL_S_ADD 0x37 -#define IDLE_MODE_OFF 0x38 -#define IDLE_MODE_ON 0x39 -#define PIXEL_FORMAT_SET 0x3A -#define WRITE_MEMORY_CONTINUE 0x3C -#define READ_MEMORY_CONTINUE 0x3E -#define SET_TEAR_SCANLINE 0x44 -#define GET_SCANLINE 0x45 -#define WRITE_BRIGHTNESS 0x51 -#define READ_BRIGHTNESS 0x52 -#define WRITE_CTRL_DISPALY 0x53 -#define READ_CTRL_DISPALY 0x54 -#define WRITE_BRIGHTNESS_CTL 0x55 -#define READ_BRIGHTNESS_CTL 0x56 -#define WRITE_MIN_BRIGHTNESS 0x5E -#define READ_MIN_BRIGHTNESS 0x5F -#define READ_ID1 0xDA -#define READ_ID2 0xDB -#define READ_ID3 0xDC -#define RGB_IF_SIGNAL_CTL 0xB0 -#define NORMAL_FRAME_CTL 0xB1 -#define IDLE_FRAME_CTL 0xB2 -#define PARTIAL_FRAME_CTL 0xB3 -#define INVERSION_CTL 0xB4 -#define BLANK_PORCH_CTL 0xB5 -#define DISPALY_FUNCTION_CTL 0xB6 -#define ENTRY_MODE_SET 0xB7 -#define BACKLIGHT_CTL1 0xB8 -#define BACKLIGHT_CTL2 0xB9 -#define BACKLIGHT_CTL3 0xBA -#define BACKLIGHT_CTL4 0xBB -#define BACKLIGHT_CTL5 0xBC -#define BACKLIGHT_CTL7 0xBE -#define BACKLIGHT_CTL8 0xBF -#define POWER_CTL1 0xC0 -#define POWER_CTL2 0xC1 -#define VCOM_CTL1 0xC5 -#define VCOM_CTL2 0xC7 -#define NV_MEMORY_WRITE 0xD0 -#define NV_MEMORY_PROTECT_KEY 0xD1 -#define NV_MEMORY_STATUS_READ 0xD2 -#define READ_ID4 0xD3 -#define POSITIVE_GAMMA_CORRECT 0xE0 -#define NEGATIVE_GAMMA_CORRECT 0xE1 -#define DIGITAL_GAMMA_CTL1 0xE2 -#define DIGITAL_GAMMA_CTL2 0xE3 -#define INTERFACE_CTL 0xF6 - -#define DCX_GPIONUM (5) -#define RST_GPIONUM (4) -#define LCD_SPI_SLAVE_SELECT 3 - -#define SPI_CHANNEL 0 -#define SPI_SLAVE_SELECT 3 - -/* clang-format off */ -#define LCD_X_MAX (240) -#define LCD_Y_MAX (320) - -#define BLACK 0x0000 -#define NAVY 0x000F -#define DARKGREEN 0x03E0 -#define DARKCYAN 0x03EF -#define MAROON 0x7800 -#define PURPLE 0x780F -#define OLIVE 0x7BE0 -#define LIGHTGREY 0xC618 -#define DARKGREY 0x7BEF -#define BLUE 0x001F -#define GREEN 0x07E0 -#define CYAN 0x07FF -#define RED 0xF800 -#define MAGENTA 0xF81F -#define YELLOW 0xFFE0 -#define WHITE 0xFFFF -#define ORANGE 0xFD20 -#define GREENYELLOW 0xAFE5 -#define PINK 0xF81F -#define USER_COLOR 0xAA55 -/* clang-format on */ - -uint8_t const ascii0816[] = -{ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x81, 0xA5, 0x81, 0x81, 0xBD, - 0x99, 0x81, 0x81, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0xFF, - 0xDB, 0xFF, 0xFF, 0xC3, 0xE7, 0xFF, 0xFF, 0x7E, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x6C, 0xFE, 0xFE, 0xFE, 0xFE, 0x7C, 0x38, 0x10, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x38, 0x7C, 0xFE, - 0x7C, 0x38, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, - 0x3C, 0x3C, 0xE7, 0xE7, 0xE7, 0x18, 0x18, 0x3C, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x18, 0x3C, 0x7E, 0xFF, 0xFF, 0x7E, 0x18, 0x18, 0x3C, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x3C, - 0x3C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xE7, 0xC3, 0xC3, 0xE7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x66, 0x42, 0x42, 0x66, 0x3C, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xC3, 0x99, 0xBD, - 0xBD, 0x99, 0xC3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x1E, 0x0E, - 0x1A, 0x32, 0x78, 0xCC, 0xCC, 0xCC, 0xCC, 0x78, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x3C, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x18, 0x7E, 0x18, 0x18, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x33, 0x3F, 0x30, 0x30, 0x30, - 0x30, 0x70, 0xF0, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x63, - 0x7F, 0x63, 0x63, 0x63, 0x63, 0x67, 0xE7, 0xE6, 0xC0, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x18, 0x18, 0xDB, 0x3C, 0xE7, 0x3C, 0xDB, 0x18, 0x18, - 0x00, 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0x00, 0x00, 0x1F, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF0, 0xF0, 0xF0, 0xF0, - 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, - 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, - 0x0F, 0x0F, 0x0F, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x76, 0xDC, 0xD8, 0xD8, 0xD8, 0xDC, 0x76, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x78, 0xCC, 0xCC, 0xCC, 0xD8, 0xCC, 0xC6, 0xC6, 0xC6, 0xCC, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xC6, 0xC6, 0xC0, 0xC0, 0xC0, - 0xC0, 0xC0, 0xC0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xFE, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0xFE, 0xC6, 0x60, 0x30, 0x18, 0x30, 0x60, 0xC6, 0xFE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0xD8, 0xD8, - 0xD8, 0xD8, 0xD8, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x66, 0x66, 0x66, 0x66, 0x66, 0x7C, 0x60, 0x60, 0xC0, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x76, 0xDC, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x18, 0x3C, 0x66, 0x66, - 0x66, 0x3C, 0x18, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, - 0x6C, 0xC6, 0xC6, 0xFE, 0xC6, 0xC6, 0x6C, 0x38, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x38, 0x6C, 0xC6, 0xC6, 0xC6, 0x6C, 0x6C, 0x6C, 0x6C, 0xEE, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x30, 0x18, 0x0C, 0x3E, 0x66, - 0x66, 0x66, 0x66, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x7E, 0xDB, 0xDB, 0xDB, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x03, 0x06, 0x7E, 0xDB, 0xDB, 0xF3, 0x7E, 0x60, 0xC0, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x30, 0x60, 0x60, 0x7C, 0x60, - 0x60, 0x60, 0x30, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, - 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xFE, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x7E, 0x18, - 0x18, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, - 0x18, 0x0C, 0x06, 0x0C, 0x18, 0x30, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x0C, 0x18, 0x30, 0x60, 0x30, 0x18, 0x0C, 0x00, 0x7E, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x1B, 0x1B, 0x18, 0x18, 0x18, - 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, - 0x18, 0x18, 0x18, 0x18, 0xD8, 0xD8, 0xD8, 0x70, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x7E, 0x00, 0x18, 0x18, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x76, 0xDC, 0x00, - 0x76, 0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x6C, 0x6C, - 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0C, 0x0C, - 0x0C, 0x0C, 0x0C, 0xEC, 0x6C, 0x6C, 0x3C, 0x1C, 0x00, 0x00, 0x00, 0x00, - 0x00, 0xD8, 0x6C, 0x6C, 0x6C, 0x6C, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0xD8, 0x30, 0x60, 0xC8, 0xF8, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; +//POINT_COLOR +#define WHITE 0xFFFF +#define BLACK 0x0000 +#define BLUE 0x001F +#define BRED 0XF81F +#define GRED 0XFFE0 +#define GBLUE 0X07FF +#define RED 0xF800 +#define MAGENTA 0xF81F +#define GREEN 0x07E0 +#define CYAN 0x7FFF +#define YELLOW 0xFFE0 +#define BROWN 0XBC40 +#define BRRED 0XFC07 +#define GRAY 0X8430 +#define GRAY175 0XAD75 +#define GRAY151 0X94B2 +#define GRAY187 0XBDD7 +#define GRAY240 0XF79E typedef enum _lcd_dir { @@ -490,31 +53,38 @@ typedef enum _lcd_dir DIR_MASK = 0xE0, } lcd_dir_t; -typedef struct _lcd_ctl +typedef struct lcd_8080_device { - uint8_t mode; - uint8_t dir; - uint16_t width; - uint16_t height; -} lcd_ctl_t; + struct rt_device parent; + struct rt_device_graphic_info lcd_info; + int spi_channel; + int cs; + int dc_pin; +#if BSP_LCD_RST_PIN >= 0 + int rst_pin; +#endif +#if BSP_LCD_BACKLIGHT_PIN >= 0 + int backlight_pin; +#endif + int dma_channel; +} * lcd_8080_device_t; -void tft_hard_init(void); -void tft_write_command(uint8_t cmd); -void tft_write_byte(uint8_t *data_buf, uint32_t length); -void tft_write_half(uint16_t *data_buf, uint32_t length); -void tft_write_word(uint32_t *data_buf, uint32_t length, uint32_t flag); -void tft_fill_data(uint32_t *data_buf, uint32_t length); +int rt_hw_lcd_init(void); +void drv_lcd_set_area(lcd_8080_device_t lcd, rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2); +void drv_lcd_data_word(lcd_8080_device_t lcd, rt_uint32_t *data_buf, rt_uint32_t length); +void drv_lcd_data_half_word(lcd_8080_device_t lcd, rt_uint16_t *data_buf, rt_uint32_t length); -void lcd_polling_enable(void); -void lcd_interrupt_enable(void); -int lcd_init(void); -void lcd_clear(uint16_t color); +/* for mpy machine.lcd */ +void lcd_display_on(void); +void lcd_display_off(void); +void lcd_clear(int color); +void lcd_draw_point_color(int x, int y, int color); +void lcd_show_string(int x, int y, int size, const char *data); +void lcd_draw_line(int x1, int y1, int x2, int y2); +void lcd_draw_rectangle(int x1, int y1, int x2, int y2); +void lcd_draw_circle(int x1, int y1, int r); +void lcd_set_color(int back, int fore); +void lcd_show_image(int x, int y, int length, int wide, const unsigned char *buf); void lcd_set_direction(lcd_dir_t dir); -void lcd_set_area(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2); -void lcd_draw_point(uint16_t x, uint16_t y, uint16_t color); -void lcd_draw_string(uint16_t x, uint16_t y, char *str, uint16_t color); -void lcd_draw_picture(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height, uint32_t *ptr); -void lcd_draw_rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t width, uint16_t color); -void lcd_ram_draw_string(char *str, uint32_t *ptr, uint16_t font_color, uint16_t bg_color); #endif diff --git a/Ubiquitous/RT_Thread/bsp/k210/rtconfig.h b/Ubiquitous/RT_Thread/bsp/k210/rtconfig.h index 4730b6183..dd0ddb421 100644 --- a/Ubiquitous/RT_Thread/bsp/k210/rtconfig.h +++ b/Ubiquitous/RT_Thread/bsp/k210/rtconfig.h @@ -18,12 +18,13 @@ #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 1000 +#define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 4096 +#define SYSTEM_THREAD_STACK_SIZE 4096 /* kservice optimization */ @@ -70,21 +71,22 @@ /* C++ features */ +#define RT_USING_CPLUSPLUS /* Command shell */ #define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH #define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 16384 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 16384 #define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT -#define FINSH_USING_MSH_ONLY +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION #define FINSH_ARG_MAX 10 /* Device virtual file system */ @@ -108,6 +110,7 @@ #define RT_DFS_ELM_DRIVES 2 #define RT_DFS_ELM_MAX_SECTOR_SIZE 4096 #define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS /* Device Drivers */ @@ -118,9 +121,11 @@ #define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 #define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN +#define RT_USING_RTC #define RT_USING_SPI #define RT_USING_SPI_MSD #define RT_USING_SFUD @@ -163,7 +168,8 @@ #define RT_USING_PTHREADS #define PTHREAD_NUM_MAX 8 #define RT_USING_POSIX -#define RT_LIBC_FIXED_TIMEZONE 8 +#define RT_LIBC_USING_TIME +#define RT_LIBC_DEFAULT_TIMEZONE 8 /* Network */ @@ -174,7 +180,7 @@ /* protocol stack implement */ #define SAL_USING_LWIP -#define SAL_SOCKETS_NUM 16 +#define SAL_USING_POSIX /* Network interface device */ @@ -245,9 +251,14 @@ /* Board Drivers Config */ #define BSP_USING_UART_HS + +/* General Purpose UARTs */ + #define BSP_USING_UART1 #define BSP_UART1_TXD_PIN 20 #define BSP_UART1_RXD_PIN 21 +#define BSP_UART1_RTS_PIN -1 +#define BSP_UART1_CTS_PIN -1 #define BSP_USING_SPI1 #define BSP_SPI1_CLK_PIN 27 #define BSP_SPI1_D0_PIN 28 @@ -261,6 +272,10 @@ #define BSP_LCD_WR_PIN 39 #define BSP_LCD_DC_PIN 38 #define BSP_LCD_RST_PIN 37 +#define BSP_LCD_BACKLIGHT_PIN -1 +#define BSP_LCD_BACKLIGHT_ACTIVE_LOW +#define BSP_LCD_CLK_FREQ 20000000 +#define BSP_BOARD_USER #define BSP_LCD_X_MAX 240 #define BSP_LCD_Y_MAX 320 #define BSP_USING_SDCARD @@ -276,6 +291,9 @@ #define BSP_DVP_CMOS_XCLK_PIN 46 #define BSP_DVP_CMOS_PCLK_PIN 47 #define BSP_DVP_CMOS_HREF_PIN 45 +#define RW007_SPIDEV_NAME "spi11" +#define RW007_INT_BUSY_PIN 7 +#define RW007_RST_PIN 6 /* Kendryte SDK Config */ @@ -283,6 +301,9 @@ /* More Drivers */ +#define PKG_USING_RW007 +#define RW007_NOT_USE_EXAMPLE_DRIVERS +#define RW007_SPI_MAX_HZ 20000000 #define DRV_USING_OV2640 /* APP_Framework */ @@ -303,23 +324,39 @@ /* knowing app */ +#define APPLICATION_KNOWING +#define APP_MNIST #define FACE_DETECT /* sensor app */ +#define APPLICATION_SENSOR +#define APPLICATION_SENSOR_VOICE +#define APPLICATION_SENSOR_VOICE_D124 /* Framework */ #define TRANSFORM_LAYER_ATTRIUBUTE #define ADD_XIUOS_FETURES #define SUPPORT_SENSOR_FRAMEWORK +#define SENSOR_VOICE +#define SENSOR_D124 +#define SENSOR_DEVICE_D124 "d124_1" +#define SENSOR_QUANTITY_D124_VOICE "voice_1" +#define SENSOR_DEVICE_D124_DEV "/dev/uar2" #define SUPPORT_KNOWING_FRAMEWORK +#define USING_TENSORFLOWLITEMICRO +#define USING_TENSORFLOWLITEMICRO_NORMAL #define USING_KPU_POSTPROCESSING #define USING_YOLOV2 -/* app lib */ +/* Security */ + + +/* lib */ #define APP_SELECT_NEWLIB +#define LIB_USING_CJSON #define __STACKSIZE__ 4096 #endif diff --git a/Ubiquitous/RT_Thread/bsp/stm32f407-atk-coreboard/.config b/Ubiquitous/RT_Thread/bsp/stm32f407-atk-coreboard/.config index f4caa0c56..681cee720 100644 --- a/Ubiquitous/RT_Thread/bsp/stm32f407-atk-coreboard/.config +++ b/Ubiquitous/RT_Thread/bsp/stm32f407-atk-coreboard/.config @@ -33,8 +33,9 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 # # CONFIG_RT_KSERVICE_USING_STDLIB is not set # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set CONFIG_RT_DEBUG=y -# CONFIG_RT_DEBUG_COLOR is not set +CONFIG_RT_DEBUG_COLOR=y # CONFIG_RT_DEBUG_INIT_CONFIG is not set # CONFIG_RT_DEBUG_THREAD_CONFIG is not set # CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set @@ -60,10 +61,12 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # Memory Management # CONFIG_RT_USING_MEMPOOL=y -# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y # CONFIG_RT_USING_NOHEAP is not set -CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SMALL_MEM is not set # CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y # CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y @@ -77,6 +80,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +# CONFIG_RT_PRINTF_LONGLONG is not set CONFIG_RT_VER_NUM=0x40004 CONFIG_ARCH_ARM=y CONFIG_RT_USING_CPU_FFS=y @@ -101,19 +105,19 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10 # Command shell # CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y CONFIG_FINSH_USING_DESCRIPTION=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_CMD_SIZE=80 # CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -# CONFIG_FINSH_USING_MSH_ONLY is not set CONFIG_FINSH_ARG_MAX=10 # @@ -147,17 +151,23 @@ CONFIG_RT_DFS_ELM_DRIVES=2 CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 # CONFIG_RT_DFS_ELM_USE_ERASE is not set CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_NFS is not set # # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set @@ -190,7 +200,33 @@ CONFIG_RT_USING_SPI_MSD=y # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_PULSE_ENCODER is not set # CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_WIFI is not set +CONFIG_RT_USING_WIFI=y +CONFIG_RT_WLAN_DEVICE_STA_NAME="wlan0" +CONFIG_RT_WLAN_DEVICE_AP_NAME="wlan1" +CONFIG_RT_WLAN_SSID_MAX_LENGTH=32 +CONFIG_RT_WLAN_PASSWORD_MAX_LENGTH=32 +CONFIG_RT_WLAN_DEV_EVENT_NUM=2 +CONFIG_RT_WLAN_MANAGE_ENABLE=y +CONFIG_RT_WLAN_SCAN_WAIT_MS=10000 +CONFIG_RT_WLAN_CONNECT_WAIT_MS=10000 +CONFIG_RT_WLAN_SCAN_SORT=y +CONFIG_RT_WLAN_MSH_CMD_ENABLE=y +CONFIG_RT_WLAN_AUTO_CONNECT_ENABLE=y +CONFIG_AUTO_CONNECTION_PERIOD_MS=2000 +CONFIG_RT_WLAN_CFG_ENABLE=y +CONFIG_RT_WLAN_CFG_INFO_MAX=3 +CONFIG_RT_WLAN_PROT_ENABLE=y +CONFIG_RT_WLAN_PROT_NAME_LEN=8 +CONFIG_RT_WLAN_PROT_MAX=2 +CONFIG_RT_WLAN_DEFAULT_PROT="lwip" +CONFIG_RT_WLAN_PROT_LWIP_ENABLE=y +CONFIG_RT_WLAN_PROT_LWIP_NAME="lwip" +# CONFIG_RT_WLAN_PROT_LWIP_PBUF_FORCE is not set +CONFIG_RT_WLAN_WORK_THREAD_ENABLE=y +CONFIG_RT_WLAN_WORKQUEUE_THREAD_NAME="wlan" +CONFIG_RT_WLAN_WORKQUEUE_THREAD_SIZE=2048 +CONFIG_RT_WLAN_WORKQUEUE_THREAD_PRIO=15 +# CONFIG_RT_WLAN_DEBUG is not set # # Using USB @@ -202,14 +238,16 @@ CONFIG_RT_USING_SPI_MSD=y # POSIX layer and C standard library # CONFIG_RT_USING_LIBC=y -# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_PTHREADS=y +CONFIG_PTHREAD_NUM_MAX=8 CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_MMAP is not set # CONFIG_RT_USING_POSIX_TERMIOS is not set # CONFIG_RT_USING_POSIX_GETLINE is not set # CONFIG_RT_USING_POSIX_AIO is not set +CONFIG_RT_LIBC_USING_TIME=y # CONFIG_RT_USING_MODULE is not set -CONFIG_RT_LIBC_FIXED_TIMEZONE=8 +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # Network @@ -218,22 +256,93 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8 # # Socket abstraction layer # -# CONFIG_RT_USING_SAL is not set +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# protocol stack implement +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_POSIX is not set +CONFIG_SAL_SOCKETS_NUM=16 # # Network interface device # -# CONFIG_RT_USING_NETDEV is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set # # light weight TCP/IP stack # -# CONFIG_RT_USING_LWIP is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP202 is not set +CONFIG_RT_USING_LWIP203=y +# CONFIG_RT_USING_LWIP212 is not set +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=4 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=16 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_RT_LWIP_DEBUG is not set # # AT commands # # CONFIG_RT_USING_AT is not set +# CONFIG_LWIP_USING_DHCPD is not set # # VBUS(Virtual Software BUS) @@ -246,6 +355,7 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8 # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_LWP is not set @@ -285,7 +395,9 @@ CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART1=y # CONFIG_BSP_UART1_RX_USING_DMA is not set # CONFIG_BSP_UART1_TX_USING_DMA is not set -# CONFIG_BSP_USING_UART2 is not set +CONFIG_BSP_USING_UART2=y +# CONFIG_BSP_UART2_RX_USING_DMA is not set +# CONFIG_BSP_UART2_TX_USING_DMA is not set # CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_USING_UART4 is not set # CONFIG_BSP_USING_UART5 is not set @@ -323,8 +435,17 @@ CONFIG_BSP_USING_FMC=y # # More Drivers # -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_DRV_USING_OV2640 is not set +CONFIG_PKG_USING_RW007=y +# CONFIG_RW007_NOT_USE_EXAMPLE_DRIVERS is not set +CONFIG_RW007_USING_STM32_DRIVERS=y +CONFIG_RW007_SPI_MAX_HZ=30000000 +CONFIG_RW007_SPI_BUS_NAME="spi1" +CONFIG_RW007_CS_PIN=86 +CONFIG_RW007_BOOT0_PIN=19 +CONFIG_RW007_BOOT1_PIN=86 +CONFIG_RW007_INT_BUSY_PIN=87 +CONFIG_RW007_RST_PIN=88 +CONFIG_DRV_USING_OV2640=y # # APP_Framework @@ -356,12 +477,18 @@ CONFIG_MAIN_KTASK_STACK_SIZE=1024 # # knowing app # -CONFIG_IRIS_ML_DEMO=y +# CONFIG_APPLICATION_KNOWING is not set # # sensor app # -# CONFIG_APPLICATION_SENSOR is not set +CONFIG_APPLICATION_SENSOR=y +# CONFIG_APPLICATION_SENSOR_CO2 is not set +# CONFIG_APPLICATION_SENSOR_PM1_0 is not set +CONFIG_APPLICATION_SENSOR_VOICE=y +CONFIG_APPLICATION_SENSOR_VOICE_D124=y +# CONFIG_APPLICATION_SENSOR_HUMIDITY is not set +# CONFIG_APPLICATION_SENSOR_TEMPERATURE is not set # # Framework @@ -373,7 +500,12 @@ CONFIG_ADD_XIUOS_FETURES=y CONFIG_SUPPORT_SENSOR_FRAMEWORK=y # CONFIG_SENSOR_CO2 is not set # CONFIG_SENSOR_PM is not set -# CONFIG_SENSOR_VOICE is not set +CONFIG_SENSOR_VOICE=y +CONFIG_SENSOR_D124=y +CONFIG_SENSOR_DEVICE_D124="d124_1" +CONFIG_SENSOR_QUANTITY_D124_VOICE="voice_1" +# CONFIG_SENSOR_D124_DRIVER_EXTUART is not set +CONFIG_SENSOR_DEVICE_D124_DEV="/dev/uart2" # CONFIG_SENSOR_TEMPERATURE is not set # CONFIG_SENSOR_HUMIDITY is not set # CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set @@ -381,11 +513,19 @@ CONFIG_SUPPORT_KNOWING_FRAMEWORK=y # CONFIG_USING_TENSORFLOWLITEMICRO is not set CONFIG_USING_KPU_POSTPROCESSING=y # CONFIG_USING_YOLOV2 is not set +# CONFIG_USING_KNOWING_FILTER is not set +# CONFIG_USING_OTA_MODEL is not set # CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set +# +# Security +# +# CONFIG_CRYPTO is not set + # # lib # CONFIG_APP_SELECT_NEWLIB=y # CONFIG_APP_SELECT_OTHER_LIB is not set # CONFIG_LIB_USING_CJSON is not set +# CONFIG_LIB_USING_QUEUE is not set diff --git a/Ubiquitous/RT_Thread/bsp/stm32f407-atk-coreboard/applications/main.c b/Ubiquitous/RT_Thread/bsp/stm32f407-atk-coreboard/applications/main.c index 09ee06729..7f11d6ed8 100644 --- a/Ubiquitous/RT_Thread/bsp/stm32f407-atk-coreboard/applications/main.c +++ b/Ubiquitous/RT_Thread/bsp/stm32f407-atk-coreboard/applications/main.c @@ -1,3 +1,12 @@ +/* + * @Author: chunyexixiaoyu + * @Date: 2021-09-24 16:33:15 + * @LastEditTime: 2021-09-24 15:48:30 + * @LastEditors: Please set LastEditors + * @Description: In User Settings Edit + * @FilePath: \xiuos\Ubiquitous\RT_Thread\bsp\stm32f407-atk-coreboard\applications\main.c + */ + /* * Copyright (c) 2006-2018, RT-Thread Development Team * @@ -10,14 +19,27 @@ #include #include #include +#include +#ifdef RT_USING_POSIX +#include +#include +#include +#include +#include +#include +#ifdef RT_USING_POSIX_TERMIOS +#include +#endif +#endif #define LED0_PIN GET_PIN(F, 9) - +extern int FrameworkInit(); int main(void) { int count = 1; rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); rt_thread_mdelay(100); + FrameworkInit(); printf("XIUOS stm32f4 build %s %s\n",__DATE__,__TIME__); while (count++) { diff --git a/Ubiquitous/RT_Thread/bsp/stm32f407-atk-coreboard/rtconfig.h b/Ubiquitous/RT_Thread/bsp/stm32f407-atk-coreboard/rtconfig.h index 4dfc486d7..a2c1cb8be 100644 --- a/Ubiquitous/RT_Thread/bsp/stm32f407-atk-coreboard/rtconfig.h +++ b/Ubiquitous/RT_Thread/bsp/stm32f407-atk-coreboard/rtconfig.h @@ -28,6 +28,7 @@ /* kservice optimization */ #define RT_DEBUG +#define RT_DEBUG_COLOR /* Inter-Thread communication */ @@ -40,7 +41,9 @@ /* Memory Management */ #define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM +#define RT_USING_MEMHEAP +#define RT_USING_MEMHEAP_AUTO_BINDING +#define RT_USING_MEMHEAP_AS_HEAP #define RT_USING_HEAP /* Kernel Device Object */ @@ -68,16 +71,17 @@ /* Command shell */ #define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH #define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION #define FINSH_ARG_MAX 10 /* Device virtual file system */ @@ -101,13 +105,18 @@ #define RT_DFS_ELM_DRIVES 2 #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 #define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS /* Device Drivers */ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_I2C @@ -115,6 +124,31 @@ #define RT_USING_PIN #define RT_USING_SPI #define RT_USING_SPI_MSD +#define RT_USING_WIFI +#define RT_WLAN_DEVICE_STA_NAME "wlan0" +#define RT_WLAN_DEVICE_AP_NAME "wlan1" +#define RT_WLAN_SSID_MAX_LENGTH 32 +#define RT_WLAN_PASSWORD_MAX_LENGTH 32 +#define RT_WLAN_DEV_EVENT_NUM 2 +#define RT_WLAN_MANAGE_ENABLE +#define RT_WLAN_SCAN_WAIT_MS 10000 +#define RT_WLAN_CONNECT_WAIT_MS 10000 +#define RT_WLAN_SCAN_SORT +#define RT_WLAN_MSH_CMD_ENABLE +#define RT_WLAN_AUTO_CONNECT_ENABLE +#define AUTO_CONNECTION_PERIOD_MS 2000 +#define RT_WLAN_CFG_ENABLE +#define RT_WLAN_CFG_INFO_MAX 3 +#define RT_WLAN_PROT_ENABLE +#define RT_WLAN_PROT_NAME_LEN 8 +#define RT_WLAN_PROT_MAX 2 +#define RT_WLAN_DEFAULT_PROT "lwip" +#define RT_WLAN_PROT_LWIP_ENABLE +#define RT_WLAN_PROT_LWIP_NAME "lwip" +#define RT_WLAN_WORK_THREAD_ENABLE +#define RT_WLAN_WORKQUEUE_THREAD_NAME "wlan" +#define RT_WLAN_WORKQUEUE_THREAD_SIZE 2048 +#define RT_WLAN_WORKQUEUE_THREAD_PRIO 15 /* Using USB */ @@ -122,19 +156,77 @@ /* POSIX layer and C standard library */ #define RT_USING_LIBC +#define RT_USING_PTHREADS +#define PTHREAD_NUM_MAX 8 #define RT_USING_POSIX -#define RT_LIBC_FIXED_TIMEZONE 8 +#define RT_LIBC_USING_TIME +#define RT_LIBC_DEFAULT_TIMEZONE 8 /* Network */ /* Socket abstraction layer */ +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* protocol stack implement */ + +#define SAL_USING_LWIP +#define SAL_SOCKETS_NUM 16 /* Network interface device */ +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 /* light weight TCP/IP stack */ +#define RT_USING_LWIP +#define RT_USING_LWIP203 +#define RT_LWIP_MEM_ALIGNMENT 4 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS +#define RT_LWIP_DHCP +#define IP_SOF_BROADCAST 1 +#define IP_SOF_BROADCAST_RECV 1 + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.1.30" +#define RT_LWIP_GWADDR "192.168.1.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 10 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING /* AT commands */ @@ -168,6 +260,7 @@ #define BSP_USING_GPIO #define BSP_USING_UART #define BSP_USING_UART1 +#define BSP_USING_UART2 #define BSP_USING_SPI #define BSP_USING_SPI1 #define BSP_USING_SPI2 @@ -182,6 +275,16 @@ /* More Drivers */ +#define PKG_USING_RW007 +#define RW007_USING_STM32_DRIVERS +#define RW007_SPI_MAX_HZ 30000000 +#define RW007_SPI_BUS_NAME "spi1" +#define RW007_CS_PIN 86 +#define RW007_BOOT0_PIN 19 +#define RW007_BOOT1_PIN 86 +#define RW007_INT_BUSY_PIN 87 +#define RW007_RST_PIN 88 +#define DRV_USING_OV2640 /* APP_Framework */ @@ -201,19 +304,29 @@ /* knowing app */ -#define IRIS_ML_DEMO /* sensor app */ +#define APPLICATION_SENSOR +#define APPLICATION_SENSOR_VOICE +#define APPLICATION_SENSOR_VOICE_D124 /* Framework */ #define TRANSFORM_LAYER_ATTRIUBUTE #define ADD_XIUOS_FETURES #define SUPPORT_SENSOR_FRAMEWORK +#define SENSOR_VOICE +#define SENSOR_D124 +#define SENSOR_DEVICE_D124 "d124_1" +#define SENSOR_QUANTITY_D124_VOICE "voice_1" +#define SENSOR_DEVICE_D124_DEV "/dev/uart2" #define SUPPORT_KNOWING_FRAMEWORK #define USING_KPU_POSTPROCESSING +/* Security */ + + /* lib */ #define APP_SELECT_NEWLIB diff --git a/Ubiquitous/RT_Thread/drivers/ov2640/ov2640_source/drv_ov2640.h b/Ubiquitous/RT_Thread/drivers/ov2640/ov2640_source/drv_ov2640.h index 573b1f4ab..6d0d01cb6 100644 --- a/Ubiquitous/RT_Thread/drivers/ov2640/ov2640_source/drv_ov2640.h +++ b/Ubiquitous/RT_Thread/drivers/ov2640/ov2640_source/drv_ov2640.h @@ -125,6 +125,8 @@ extern "C" { #ifdef BOARD_K210_EVB #define IOCTRL_CAMERA_SET_DVP_RESO (21) // set dev resolution +#else +#define IOCTRL_CAMERA_SET_DVP_RESO (22) // same as IOCTRL_CAMERA_START_SHOT #endif #define IOCTRL_CAMERA_START_SHOT (22) // start shoot diff --git a/Ubiquitous/XiUOS/Makefile b/Ubiquitous/XiUOS/Makefile index f6f8f64bf..619ae2769 100755 --- a/Ubiquitous/XiUOS/Makefile +++ b/Ubiquitous/XiUOS/Makefile @@ -5,7 +5,7 @@ MAKEFLAGS += --no-print-directory .PHONY:COMPILE_APP COMPILE_KERNEL -support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator ok1052-c gapuino +support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator ok1052-c gapuino cortex-m0-emulator SRC_DIR:= export BOARD ?=kd233 diff --git a/Ubiquitous/XiUOS/arch/arm/Makefile b/Ubiquitous/XiUOS/arch/arm/Makefile index 7697b0f46..d2bdd9b18 100644 --- a/Ubiquitous/XiUOS/arch/arm/Makefile +++ b/Ubiquitous/XiUOS/arch/arm/Makefile @@ -1,16 +1,28 @@ #公共部分 SRC_DIR := shared +# The following three platforms support compatiable instructions. + ifeq ($(CONFIG_BOARD_CORTEX_M3_EVB),y) -SRC_DIR +=cortex-m3 +SRC_DIR += armv7m +SRC_DIR += cortex-m3 endif ifeq ($(CONFIG_BOARD_STM32F407_EVB),y) -SRC_DIR +=cortex-m4 +SRC_DIR += armv7m +SRC_DIR += cortex-m4 endif ifeq ($(CONFIG_BOARD_CORTEX_M7_EVB),y) -SRC_DIR +=cortex-m7 +SRC_DIR += armv7m +SRC_DIR += cortex-m7 +endif + +# cortex-m0 is ARMv6-m + +ifeq ($(CONFIG_BOARD_CORTEX_M0_EVB),y) +SRC_DIR += armv6m +SRC_DIR += cortex-m0 endif include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiUOS/arch/arm/armv6m/Makefile b/Ubiquitous/XiUOS/arch/arm/armv6m/Makefile new file mode 100644 index 000000000..7524ef1ec --- /dev/null +++ b/Ubiquitous/XiUOS/arch/arm/armv6m/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := pendsv.S arm32_switch.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiUOS/arch/arm/armv6m/arm32_switch.c b/Ubiquitous/XiUOS/arch/arm/armv6m/arm32_switch.c new file mode 100644 index 000000000..a35ad27ea --- /dev/null +++ b/Ubiquitous/XiUOS/arch/arm/armv6m/arm32_switch.c @@ -0,0 +1,241 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +#include +#include + +#define SCB_VTOR "0xE000ED08" +#define NVIC_INT_CTRL "0xE000ED04" +#define NVIC_SYSPRI2 "0xE000ED20" +#define NVIC_PENDSV_PRI "0x00FF0000" +#define NVIC_PENDSVSET "0x10000000" + +/* We replaced instructions that were not supported in thumb mode. */ + +void __attribute__((naked)) HwInterruptcontextSwitch(x_ubase from, x_ubase to, struct TaskDescriptor *to_task, void *context) +{ + asm volatile ("PUSH {R4}"); + asm volatile ("PUSH {R5}"); + + asm volatile ("LDR r4, =KtaskSwitchInterruptFlag"); + asm volatile ("LDR r5, [r4]"); + asm volatile ("CMP r5, #1"); + + asm volatile ("POP {R5}"); + asm volatile ("POP {R4}"); + + asm volatile ("BEQ Arm32SwitchReswitch"); + + asm volatile ("PUSH {R4}"); + asm volatile ("PUSH {R5}"); + asm volatile ("LDR r4, =KtaskSwitchInterruptFlag"); + + asm volatile ("MOV r5, #1"); + asm volatile ("STR r5, [r4]"); + asm volatile ("LDR r4, =InterruptFromKtask"); + asm volatile ("STR r0, [r4]"); + + asm volatile ("POP {R5}"); + asm volatile ("POP {R4}"); + + asm volatile ("B Arm32SwitchReswitch"); +} + +void __attribute__((naked)) Arm32SwitchReswitch() +{ + asm volatile ("PUSH {R4}"); + asm volatile ("LDR r4, =InterruptToKtask"); + asm volatile ("STR r1, [r4]"); + asm volatile ("LDR r4, =InterruptToKtaskDescriptor"); + asm volatile ("STR r2, [r4]"); + asm volatile ("LDR r0, =" NVIC_INT_CTRL); + asm volatile ("LDR r1, =" NVIC_PENDSVSET); + asm volatile ("STR r1, [r0]"); + asm volatile ("POP {R4}"); + asm volatile ("BX LR"); +} + +void __attribute__((naked)) SwitchKtaskContext(x_ubase from, x_ubase to, struct TaskDescriptor *to_task) +{ + asm volatile("B HwInterruptcontextSwitch"); +} + +void SwitchKtaskContextTo(x_ubase to, struct TaskDescriptor *to_task) +{ + asm volatile ("LDR r2, =InterruptToKtask"); + asm volatile ("STR r0, [r2]"); + asm volatile ("LDR r2, =InterruptToKtaskDescriptor"); + asm volatile ("STR r1, [r2]"); +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + asm volatile ("MRS r2, CONTROL"); + asm volatile ("BIC r2, #0x04"); + asm volatile ("MSR CONTROL, r2"); +#endif + asm volatile ("LDR r1, =InterruptFromKtask"); + asm volatile ("MOV r0, #0x0"); + asm volatile ("STR r0, [r1]"); + asm volatile ("LDR r1, =KtaskSwitchInterruptFlag"); + asm volatile ("MOV r0, #1"); + asm volatile ("STR r0, [r1]"); + asm volatile ("LDR r0, =" NVIC_SYSPRI2); + asm volatile ("LDR r1, =" NVIC_PENDSV_PRI); + // asm volatile ("LDR.W r2, [r0,#0x00]"); + asm volatile ("LDR r2, [r0,#0x00]"); + asm volatile ("ORR r1,r1,r2"); + asm volatile ("STR r1, [r0]"); + asm volatile ("LDR r0, =" NVIC_INT_CTRL); + asm volatile ("LDR r1, =" NVIC_PENDSVSET); + asm volatile ("STR r1, [r0]"); + asm volatile ("LDR r0, =" SCB_VTOR); + asm volatile ("LDR r0, [r0]"); + asm volatile ("LDR r0, [r0]"); + asm volatile ("NOP"); + asm volatile ("MSR msp, r0"); + asm volatile ("CPSIE F"); + asm volatile ("CPSIE I"); + asm volatile ("BX lr"); +} + +void __attribute__((naked)) HardFaultHandler() +{ + asm volatile ("MRS r0, msp"); + + // asm volatile ("TST lr, #0x04"); + asm volatile ("MOV r1, lr"); + asm volatile ("MOV r2, #0x04"); + asm volatile ("TST r1, r2"); + + asm volatile ("BEQ Arm32SwitchGetSpDone"); + asm volatile ("MRS r0, psp"); + asm volatile ("B Arm32SwitchGetSpDone"); +} + +void __attribute__((naked)) Arm32SwitchGetSpDone() +{ + asm volatile ("MRS r3, primask"); + + // asm volatile ("STMFD r0!, {r3 - r11}"); + asm volatile ("SUB r0, r0, #0x24"); + asm volatile ("STMIA r0!, {r3 - r7}"); + asm volatile ("MOV r3, r8"); + asm volatile ("MOV r4, r9"); + asm volatile ("MOV r5, r10"); + asm volatile ("MOV r6, r11"); + asm volatile ("STMIA r0!, {r3 - r6}"); + asm volatile ("SUB r0, r0, #0x24"); + + // asm volatile ("STMFD r0!, {lr}"); + asm volatile ("SUB r0, r0, #0x4"); + asm volatile ("MOV r0, lr"); +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + asm volatile ("MOV r4, #0x00"); + // asm volatile ("TST lr, #0x10"); + asm volatile ("MOV r1, lr"); + asm volatile ("MOV r2, #0x10"); + asm volatile ("TST r1, r2"); + + asm volatile ("MOVEQ r4, #0x01"); + asm volatile ("STMFD r0!, {r4}"); +#endif + // asm volatile ("TST lr, #0x04"); + asm volatile ("MOV r1, lr"); + asm volatile ("MOV r2, #0x04"); + asm volatile ("TST r1, r2"); + + asm volatile ("BEQ Arm32SwitchUpdateMsp"); + asm volatile ("MSR psp, r0"); + asm volatile ("B Arm32SwitchUpdateDone"); + asm volatile ("B Arm32SwitchUpdateMsp"); +} + +void __attribute__((naked)) Arm32SwitchUpdateMsp() +{ + asm volatile ("MSR msp, r0"); + asm volatile ("B Arm32SwitchUpdateDone"); +} + +void __attribute__((naked)) Arm32SwitchUpdateDone() +{ + asm volatile ("PUSH {LR}"); + asm volatile ("BL HwHardFaultException"); + + // asm volatile ("POP {LR}"); + asm volatile ("POP {R1}"); + asm volatile ("MOV lr, r1"); + + // asm volatile ("ORR lr, lr, #0x04"); + asm volatile ("MOV r1, lr"); + asm volatile ("MOV r2, #0x04"); + asm volatile ("ORR r1, r2"); + asm volatile ("MOV lr, r1"); + + asm volatile ("BX lr"); +} + +void __attribute__((naked)) MemFaultHandler() +{ + asm volatile ("MRS r0, msp"); + + // asm volatile ("TST lr, #0x04"); + asm volatile ("MOV r1, lr"); + asm volatile ("MOV r2, #0x04"); + asm volatile ("TST r1, r2"); + + asm volatile ("BEQ Arm32Switch1"); + asm volatile ("MRS r0, psp"); + asm volatile ("B Arm32Switch1"); +} + +void __attribute__((naked)) Arm32Switch1() +{ + asm volatile ("MRS r3, primask"); + + // asm volatile ("STMFD r0!, {r3 - r11}"); + asm volatile ("SUB r0, r0, #0x24"); + asm volatile ("STMIA r0!, {r3 - r7}"); + asm volatile ("MOV r3, r8"); + asm volatile ("MOV r4, r9"); + asm volatile ("MOV r5, r10"); + asm volatile ("MOV r6, r11"); + asm volatile ("STMIA r0!, {r3 - r6}"); + asm volatile ("SUB r0, r0, #0x24"); + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + asm volatile ("MOV r4, #0x00"); + // asm volatile ("TST lr, #0x10"); + asm volatile ("MOV r1, lr"); + asm volatile ("MOV r2, #0x10"); + asm volatile ("TST r1, r2"); + asm volatile ("MOV lr, r1"); + + asm volatile ("MOVEQ r4, #0x01"); + asm volatile ("STMFD r0!, {r4}"); +#endif + // asm volatile ("STMFD r0!, {lr}"); + asm volatile ("SUB r0, r0, #0x4"); + asm volatile ("MOV r0, lr"); + + asm volatile ("PUSH {LR}"); + asm volatile ("BL MemFaultHandle"); + + // asm volatile ("POP {LR}"); + asm volatile ("POP {R5}"); + asm volatile ("MOV lr, r5"); + + // asm volatile ("ORR lr, lr, #0x04"); + asm volatile ("MOV r5, lr"); + asm volatile ("MOV r6, #0x04"); + asm volatile ("ORR r5, r6"); + asm volatile ("MOV lr, r5"); + + asm volatile ("BX lr"); +} diff --git a/Ubiquitous/XiUOS/arch/arm/armv6m/pendsv.S b/Ubiquitous/XiUOS/arch/arm/armv6m/pendsv.S new file mode 100644 index 000000000..477c5d2c1 --- /dev/null +++ b/Ubiquitous/XiUOS/arch/arm/armv6m/pendsv.S @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-10-11 Bernard first version + * 2012-01-01 aozima support context switch load/store FPU register. + * 2013-06-18 aozima add restore MSP feature. + * 2013-06-23 aozima support lazy stack optimized. + * 2018-07-24 aozima enhancement hard fault exception handler. + */ + +/************************************************* +File name: pendsv.S +Description: PendSV interrupt handler +Others: take RT-Thread v4.0.2/libcpu/arm/cortex-m4/context_gcc.S for references + https://github.com/RT-Thread/rt-thread/tree/v4.0.2 +History: +1. Date: 2021-04-25 +Author: AIIT XUOS Lab +*************************************************/ + +#include + +.cpu cortex-m0 +.syntax unified +.thumb +.text + +.equ SCB_VTOR, 0xE000ED08 +.equ NVIC_INT_CTRL, 0xE000ED04 +.equ NVIC_SYSPRI2, 0xE000ED20 +.equ NVIC_PENDSV_PRI, 0x00FF0000 +.equ NVIC_PENDSVSET, 0x10000000 + +.globl PendSV_Handler +.type PendSV_Handler, %function +PendSV_Handler: + MRS r3, PRIMASK + CPSID I + + LDR r0, =KtaskSwitchInterruptFlag + LDR r1, [r0] + /*CBZ r1, switch_to_task*/ + CMP r1, #0 + BEQ pendsv_exit + + MOVS r1, #0x00 + STR r1, [r0] + + LDR r0, =InterruptFromKtask + LDR r1, [r0] + /*CBZ r1, switch_to_task*/ + CMP r1, #0 + BEQ switch_to_task + + MRS r1, psp + + /*STMFD r1!, {r3 - r11}*/ + SUBS r1, #0x24 + STMIA r1!, {r3 - r7} + MOV r3, r8 + MOV r4, r9 + MOV r5, r10 + MOV r6, r11 + STMIA r1!, {r3 - r6} + SUBS r1, #0x24 + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + MOV r4, #0x00 + + TST lr, #0x10 + MOVEQ r4, #0x01 + + /*STMFD r1!, {r4}*/ + SUBS r1, #0x4 + STMIA r1!, {r4} + SUBS r1, #0x4 +#endif + + LDR r0, [r0] + STR r1, [r0] + +switch_to_task: + + PUSH {lr} + BL UpdateRunningTask + POP {r0} + MOV lr, r0 + +#ifdef TASK_ISOLATION + PUSH {lr} + BL GetTaskPrivilege + /*POP {lr}*/ + POP {r0} + MOV lr, r0 +#endif + + LDR r1, =InterruptToKtask + LDR r1, [r1] + LDR r1, [r1] + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + LDMFD r1!, {r2} +#endif + + /*LDMFD r1!, {r3 - r11}*/ + ADDS r1, #0x14 + LDMFD r1!, {r3 - r6} + MOV r8, r3 + MOV r9, r4 + MOV r10, r5 + MOV r11, r6 + SUBS r1, #0x24 + LDMFD r1!, {r3 - r7} + ADDS r1, #0x10 + + MSR psp, r1 +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + /*ORR lr, lr, #0x10*/ + MOV r2, lr + MOVS r3, #0x10 + ORRS r2, r3 + MOV lr, r2 + + CMP r2, #0 + BICNE lr, lr, #0x10 +#endif + MRS r2, control +#ifdef TASK_ISOLATION + CMP r0, #1 + BEQ unprivilege + +privilege: + BIC r2, r2, #0x01 + B exit +unprivilege: + /*ORR r2, r2, #0x01*/ + MOVS r1, #0x01 + ORRS r2, r1 +#else + /*BIC r2, r2, #0x01*/ + MOVS r0, #0x01 + BICS r2, r0 +#endif +exit: + MSR control, r2 + +pendsv_exit: + /*ORR lr, lr, #0x04*/ + MOV r0, lr + MOVS r1, #0x04 + ORRS r0, r1 + MOV lr, r0 + + MSR PRIMASK, r3 + BX lr diff --git a/Ubiquitous/XiUOS/arch/arm/armv7m/Makefile b/Ubiquitous/XiUOS/arch/arm/armv7m/Makefile new file mode 100644 index 000000000..7524ef1ec --- /dev/null +++ b/Ubiquitous/XiUOS/arch/arm/armv7m/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := pendsv.S arm32_switch.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiUOS/arch/arm/shared/arm32_switch.c b/Ubiquitous/XiUOS/arch/arm/armv7m/arm32_switch.c similarity index 93% rename from Ubiquitous/XiUOS/arch/arm/shared/arm32_switch.c rename to Ubiquitous/XiUOS/arch/arm/armv7m/arm32_switch.c index 5fd08dab0..09ee4bb1f 100644 --- a/Ubiquitous/XiUOS/arch/arm/shared/arm32_switch.c +++ b/Ubiquitous/XiUOS/arch/arm/armv7m/arm32_switch.c @@ -21,19 +21,37 @@ void __attribute__((naked)) HwInterruptcontextSwitch(x_ubase from, x_ubase to, struct TaskDescriptor *to_task, void *context) { + asm volatile ("PUSH {R4}"); + asm volatile ("PUSH {R5}"); + asm volatile ("LDR r4, =KtaskSwitchInterruptFlag"); asm volatile ("LDR r5, [r4]"); asm volatile ("CMP r5, #1"); + + asm volatile ("POP {R5}"); + asm volatile ("POP {R4}"); + asm volatile ("BEQ Arm32SwitchReswitch"); + + asm volatile ("PUSH {R4}"); + asm volatile ("PUSH {R5}"); + asm volatile ("LDR r4, =KtaskSwitchInterruptFlag"); + asm volatile ("MOV r5, #1"); asm volatile ("STR r5, [r4]"); asm volatile ("LDR r4, =InterruptFromKtask"); asm volatile ("STR r0, [r4]"); + + asm volatile ("POP {R5}"); + asm volatile ("POP {R4}"); + asm volatile ("B Arm32SwitchReswitch"); } void __attribute__((naked)) Arm32SwitchReswitch() { + asm volatile ("PUSH {R4}"); + asm volatile ("LDR r4, =InterruptToKtask"); asm volatile ("STR r1, [r4]"); asm volatile ("LDR r4, =InterruptToKtaskDescriptor"); @@ -41,6 +59,9 @@ void __attribute__((naked)) Arm32SwitchReswitch() asm volatile ("LDR r0, =" NVIC_INT_CTRL); asm volatile ("LDR r1, =" NVIC_PENDSVSET); asm volatile ("STR r1, [r0]"); + + asm volatile ("POP {R4}"); + asm volatile ("BX LR"); } diff --git a/Ubiquitous/XiUOS/arch/arm/shared/pendsv.S b/Ubiquitous/XiUOS/arch/arm/armv7m/pendsv.S similarity index 100% rename from Ubiquitous/XiUOS/arch/arm/shared/pendsv.S rename to Ubiquitous/XiUOS/arch/arm/armv7m/pendsv.S diff --git a/Ubiquitous/XiUOS/arch/arm/cortex-m0/Makefile b/Ubiquitous/XiUOS/arch/arm/cortex-m0/Makefile index e69de29bb..34ddb6c52 100644 --- a/Ubiquitous/XiUOS/arch/arm/cortex-m0/Makefile +++ b/Ubiquitous/XiUOS/arch/arm/cortex-m0/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := boot.c interrupt.c interrupt_vector.S + +include $(KERNEL_ROOT)/compiler.mk diff --git a/APP_Framework/Framework/connection/5G/adapter_5G.c b/Ubiquitous/XiUOS/arch/arm/cortex-m0/arch_interrupt.h similarity index 64% rename from APP_Framework/Framework/connection/5G/adapter_5G.c rename to Ubiquitous/XiUOS/arch/arm/cortex-m0/arch_interrupt.h index ff5ff1943..cfbb08253 100644 --- a/APP_Framework/Framework/connection/5G/adapter_5G.c +++ b/Ubiquitous/XiUOS/arch/arm/cortex-m0/arch_interrupt.h @@ -10,11 +10,19 @@ * See the Mulan PSL v2 for more details. */ -/** - * @file adapter_5G.c - * @brief Implement the connection 5G adapter function - * @version 1.1 - * @author AIIT XUOS Lab - * @date 2021.06.25 - */ +#ifndef ARCH_INTERRUPT_H__ +#define ARCH_INTERRUPT_H__ +#include + +#define ARCH_MAX_IRQ_NUM (48) + +#define ARCH_IRQ_NUM_OFFSET 0 + +#define SYSTICK_IRQN 15 +#define UART1_IRQn 18 + +int32 ArchEnableHwIrq(uint32 irq_num); +int32 ArchDisableHwIrq(uint32 irq_num); + +#endif diff --git a/Ubiquitous/XiUOS/arch/arm/cortex-m0/boot.c b/Ubiquitous/XiUOS/arch/arm/cortex-m0/boot.c new file mode 100644 index 000000000..7894eb6ff --- /dev/null +++ b/Ubiquitous/XiUOS/arch/arm/cortex-m0/boot.c @@ -0,0 +1,75 @@ +//***************************************************************************** +// +// startup_gcc.c - Startup code for use with GNU tools. +// +// Copyright (c) 2013 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 10636 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +/** +* @file boot.c +* @brief derived from Stellaris Firmware Development Package +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-13 +*/ + +/************************************************* +File name: boot.c +Description: Reset and init function +Others: +History: +1. Date: 2021-05-13 +Author: AIIT XUOS Lab +Modification: +1. take startup_gcc.c from revision 10636 of the Stellaris Firmware Development Package for XiUOS +*************************************************/ + +extern unsigned _sdata[], _edata[], + _sbss[], _ebss[], _etext[], _sidata[]; + +extern int entry(void); + +void +Reset_Handler(void) +{ + unsigned *p, *q; + + p = _sdata; q = _sidata; + while (p < _edata) *p++ = *q++; + p = _sbss; + while (p < _ebss) *p++ = 0; + + entry(); +} \ No newline at end of file diff --git a/Ubiquitous/XiUOS/arch/arm/cortex-m0/interrupt.c b/Ubiquitous/XiUOS/arch/arm/cortex-m0/interrupt.c new file mode 100644 index 000000000..a230745fe --- /dev/null +++ b/Ubiquitous/XiUOS/arch/arm/cortex-m0/interrupt.c @@ -0,0 +1,83 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file interrupt.c +* @brief support arm cortex-m4 interrupt function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-29 +*/ + +#include +#include + + +x_base __attribute__((naked)) DisableLocalInterrupt() +{ + asm volatile ("MRS r0, PRIMASK"); + asm volatile ("CPSID I"); + asm volatile ("BX LR "); +} + +void __attribute__((naked)) EnableLocalInterrupt(x_base level) +{ + asm volatile ("MSR PRIMASK, r0"); + asm volatile ("BX LR"); +} + +int32 ArchEnableHwIrq(uint32 irq_num) +{ + return EOK; +} + +int32 ArchDisableHwIrq(uint32 irq_num) +{ + return EOK; +} + +extern void KTaskOsAssignAfterIrq(void *context); + +void IsrEntry() +{ + uint32 ipsr; + + __asm__ volatile("MRS %0, IPSR" : "=r"(ipsr)); + + isrManager.done->incCounter(); + isrManager.done->handleIrq(ipsr); + KTaskOsAssignAfterIrq(NONE); + isrManager.done->decCounter(); +} + +void UsageFault_Handler(int irqn, void *arg) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +void BusFault_Handler(int irqn, void *arg) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +void NMI_Handler(int irqn, void *arg) +{ + while (1) + { + } +} diff --git a/Ubiquitous/XiUOS/arch/arm/cortex-m0/interrupt_vector.S b/Ubiquitous/XiUOS/arch/arm/cortex-m0/interrupt_vector.S new file mode 100644 index 000000000..95e482031 --- /dev/null +++ b/Ubiquitous/XiUOS/arch/arm/cortex-m0/interrupt_vector.S @@ -0,0 +1,122 @@ +//***************************************************************************** +// +// startup_gcc.c - Startup code for use with GNU tools. +// +// Copyright (c) 2013 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 10636 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +/** +* @file interrupt_vector.S +* @brief derived from Stellaris Firmware Development Package +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-13 +*/ + +/************************************************* +File name: interrupt_vector.S +Description: vector table for a Cortex M3 +Others: +History: +1. Date: 2021-05-13 +Author: AIIT XUOS Lab +Modification: +1. take startup_gcc.c from revision 10636 of the Stellaris Firmware Development Package for XiUOS +*************************************************/ + + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +//***************************************************************************** +.globl InterruptVectors + +/****************************************************************************** +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type InterruptVectors, %object + .size InterruptVectors, .-InterruptVectors + +InterruptVectors: + .word _sp + .word Reset_Handler + .word NMI_Handler // NMI_Handler + .word HardFaultHandler + .word MemFaultHandler // MemManage_Handler + .word BusFault_Handler // BusFault_Handler + .word UsageFault_Handler // UsageFault_Handler + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry // SVC_Handler + .word IsrEntry // DebugMon_Handler + .word IsrEntry + .word PendSV_Handler // PendSV_Handler + .word IsrEntry // systick + + .word IsrEntry + .word IsrEntry + .word IsrEntry // UART + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry + .word IsrEntry diff --git a/Ubiquitous/XiUOS/arch/arm/shared/Makefile b/Ubiquitous/XiUOS/arch/arm/shared/Makefile index 9edf7d314..9d183f38a 100644 --- a/Ubiquitous/XiUOS/arch/arm/shared/Makefile +++ b/Ubiquitous/XiUOS/arch/arm/shared/Makefile @@ -1,4 +1,4 @@ -SRC_FILES := pendsv.S prepare_ahwstack.c arm32_switch.c +SRC_FILES := prepare_ahwstack.c include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiUOS/board/aiit-arm32-board/third_party_driver/spi/connect_lora_spi.c b/Ubiquitous/XiUOS/board/aiit-arm32-board/third_party_driver/spi/connect_lora_spi.c index 3a879c694..7688b59e2 100644 --- a/Ubiquitous/XiUOS/board/aiit-arm32-board/third_party_driver/spi/connect_lora_spi.c +++ b/Ubiquitous/XiUOS/board/aiit-arm32-board/third_party_driver/spi/connect_lora_spi.c @@ -1,31 +1,22 @@ /* - * Original Copyright (c) 2006-2018, RT-Thread Development Team - * Modified Copyright (c) 2020 AIIT XUOS Lab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ - * http://www.apache.org/licenses/LICENSE-2.0 - - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Change Logs: - * Date Author Notes - * 2019-02-20 XiaojieFan the first version - */ - -/* - * Modified by: AIIT XUOS Lab - * Modified date: 2020-09-01 - * Description: replace original macro and basic date type with AIIT XUOS Lab's own defination - * start using AIIT XUOS Lab's own functional interfaces - * change some header files - */ +/** +* @file connect_lora_spi.c +* @brief support to register spi lora pointer and function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-17 +*/ #include @@ -319,6 +310,11 @@ static uint32 SpiLoraOpen(void *dev) KPrintf("SpiLoraOpen start\n"); x_err_t ret = EOK; + static x_bool lora_init_status = RET_FALSE; + + if (RET_TRUE == lora_init_status) { + return EOK; + } struct HardwareDev *haldev = (struct HardwareDev *)dev; @@ -360,14 +356,23 @@ static uint32 SpiLoraOpen(void *dev) Radio = RadioDriverInit(); KPrintf("LoRa check ok!\nNote: The length of the message that can be sent in a single time is 120 characters\n"); } + + lora_init_status = RET_TRUE; return ret; } +static uint32 SpiLoraClose(void *dev) +{ + NULL_PARAM_CHECK(dev); + + return EOK; +} + static const struct LoraDevDone lora_done = { .open = SpiLoraOpen, - .close = NONE, + .close = SpiLoraClose, .write = SpiLoraWrite, .read = SpiLoraRead, }; @@ -475,7 +480,7 @@ int LoraSx12xxSpiDeviceInit(void) return EOK; } - +#ifdef LORA_TEST /*Just for lora test*/ static struct Bus *bus; static struct HardwareDev *dev; @@ -540,4 +545,4 @@ static void LoraSend(int argc, char *argv[]) } SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), LoraSend, LoraSend, lora send message ); - +#endif diff --git a/Ubiquitous/XiUOS/board/aiit-arm32-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276.c b/Ubiquitous/XiUOS/board/aiit-arm32-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276.c index 98e09cb7b..4ba3a1cd4 100644 --- a/Ubiquitous/XiUOS/board/aiit-arm32-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276.c +++ b/Ubiquitous/XiUOS/board/aiit-arm32-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276.c @@ -61,8 +61,7 @@ void SX1276Init( void ) SX1276Reset( ); - SX1276Read(0x06, &TempReg); - KPrintf("SX1276 Read 0x%x\n", &TempReg); + SX1276Read(0x06, &TempReg); if(TempReg != 0x6C) { diff --git a/Ubiquitous/XiUOS/board/aiit-riscv64-board/third_party_driver/spi/connect_lora_spi.c b/Ubiquitous/XiUOS/board/aiit-riscv64-board/third_party_driver/spi/connect_lora_spi.c index 444c2d2e9..b27871d77 100644 --- a/Ubiquitous/XiUOS/board/aiit-riscv64-board/third_party_driver/spi/connect_lora_spi.c +++ b/Ubiquitous/XiUOS/board/aiit-riscv64-board/third_party_driver/spi/connect_lora_spi.c @@ -1,31 +1,22 @@ /* - * Original Copyright (c) 2006-2018, RT-Thread Development Team - * Modified Copyright (c) 2020 AIIT XUOS Lab - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ - * http://www.apache.org/licenses/LICENSE-2.0 - - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Change Logs: - * Date Author Notes - * 2019-02-20 XiaojieFan the first version - */ - -/* - * Modified by: AIIT XUOS Lab - * Modified date: 2020-09-01 - * Description: replace original macro and basic date type with AIIT XUOS Lab's own defination - * start using AIIT XUOS Lab's own functional interfaces - * change some header files - */ +/** +* @file connect_lora_spi.c +* @brief support to register spi lora pointer and function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-17 +*/ #include @@ -136,14 +127,7 @@ inline uint8_t SX1276ReadDio5(void) inline void SX1276WriteRxTx(uint8_t txEnable) { - if (txEnable != 0) - { - - } - else - { - - } + return; } void SX1276SetReset(uint8_t state) @@ -319,6 +303,11 @@ static uint32 SpiLoraOpen(void *dev) KPrintf("SpiLoraOpen start\n"); x_err_t ret = EOK; + static x_bool lora_init_status = RET_FALSE; + + if (RET_TRUE == lora_init_status) { + return EOK; + } struct HardwareDev *haldev = (struct HardwareDev *)dev; @@ -361,13 +350,22 @@ static uint32 SpiLoraOpen(void *dev) KPrintf("LoRa check ok!\nNote: The length of the message that can be sent in a single time is 120 characters\n"); } + lora_init_status = RET_TRUE; + return ret; } +static uint32 SpiLoraClose(void *dev) +{ + NULL_PARAM_CHECK(dev); + + return EOK; +} + static const struct LoraDevDone lora_done = { .open = SpiLoraOpen, - .close = NONE, + .close = SpiLoraClose, .write = SpiLoraWrite, .read = SpiLoraRead, }; @@ -467,7 +465,7 @@ int LoraSx12xxSpiDeviceInit(void) return EOK; } - +#ifdef LORA_TEST /*Just for lora test*/ static struct Bus *bus; static struct HardwareDev *dev; @@ -532,4 +530,4 @@ static void LoraSend(int argc, char *argv[]) } SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), LoraSend, LoraSend, lora send message ); - +#endif diff --git a/Ubiquitous/XiUOS/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276.c b/Ubiquitous/XiUOS/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276.c index 98e09cb7b..4ba3a1cd4 100644 --- a/Ubiquitous/XiUOS/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276.c +++ b/Ubiquitous/XiUOS/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276.c @@ -61,8 +61,7 @@ void SX1276Init( void ) SX1276Reset( ); - SX1276Read(0x06, &TempReg); - KPrintf("SX1276 Read 0x%x\n", &TempReg); + SX1276Read(0x06, &TempReg); if(TempReg != 0x6C) { diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/.defconfig b/Ubiquitous/XiUOS/board/cortex-m0-emulator/.defconfig new file mode 100644 index 000000000..edf437357 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/.defconfig @@ -0,0 +1,248 @@ +# +# Automatically generated file; DO NOT EDIT. +# XiUOS Project Configuration +# +CONFIG_BOARD_CORTEX_M3_EVB=y +CONFIG_KERNEL_CONSOLE_DEVICE_NAME="uart0" +#CONFIG_LED0=24 +#CONFIG_LED1=25 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y +CONFIG_ARCH_CPU_32BIT=y + +# +# cortex-m3-emulator feature +# +# CONFIG_BSP_USING_AUDIO is not set +# CONFIG_BSP_USING_CAMERA is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_DMA is not set +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_I2S is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SECURITY is not set +# CONFIG_BSP_USING_SPI is not set +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART_HS is not set +# CONFIG_BSP_USING_VIDEO is not set +# CONFIG_BSP_USING_WDT is not set + +# +# General Purpose UARTs +# + +CONFIG___STACKSIZE__=4096 + +# +# Hardware feature +# +CONFIG_RESOURCES_SERIAL=y +# CONFIG_SERIAL_USING_DMA=y +CONFIG_SERIAL_RB_BUFSZ=64 +CONFIG_FS_VFS=n +# CONFIG_RESOURCES_HWTIMER is not set +# CONFIG_RESOURCES_I2C is not set +# CONFIG_RESOURCES_LCD is not set +# CONFIG_RESOURCES_SDIO is not set +# CONFIG_RESOURCES_TOUCH is not set +# CONFIG_RESOURCES_PIN=y +# CONFIG_RESOURCES_RTC is not set +# CONFIG_RESOURCES_SPI is not set +#CONFIG_RESOURCES_SPI_SD is not set +#CONFIG_RESOURCES_SPI_SFUD is not set +# SFUD_USING_SFDP is not set +# SFUD_USING_FLASH_INFO_TABLE is not set +# SFUD_DEBUG_LOG is not set +# CONFIG_RESOURCES_WDT is not set +# CONFIG_RESOURCES_USB is not set +# CONFIG_RESOURCES_USB_HOST is not set +# CONFIG_UDISK_MOUNTPOINT is not set +# CONFIG_USBH_MSTORAGE is not set +# CONFIG_RESOURCES_USB_DEVICE is not set +# CONFIG_USBD_THREAD_STACK_SZ is not set + +# +# Kernel feature +# + +# +# Kernel Device Object +# +CONFIG_KERNEL_DEVICE=y +CONFIG_KERNEL_CONSOLE=y +CONFIG_KERNEL_CONSOLEBUF_SIZE=128 + +# +# Task feature +# +CONFIG_SCHED_POLICY_RR_REMAINSLICE=y +# CONFIG_SCHED_POLICY_RR is not set +# CONFIG_SCHED_POLICY_FIFO is not set + +# +# Memory Management +# +# CONFIG_KERNEL_MEMBLOCK is not set +CONFIG_MEM_ALIGN_SIZE=4 +CONFIG_MM_PAGE_SIZE=1024 + +# +# Using small memory allocator +# +CONFIG_KERNEL_SMALL_MEM_ALLOC=y +CONFIG_SMALL_NUMBER_32B=32 +CONFIG_SMALL_NUMBER_64B=16 + +# +# Inter-Task communication +# +# CONFIG_KERNEL_SEMAPHORE=y +# CONFIG_KERNEL_MUTEX=y +CONFIG_KERNEL_EVENT=n +CONFIG_KERNEL_MESSAGEQUEUE=n +CONFIG_KTASK_PRIORITY_8=y +CONFIG_KTASK_PRIORITY_MAX=8 +CONFIG_TICK_PER_SECOND=100 +# CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y +CONFIG_KERNEL_BANNER=y +# CONFIG_KERNEL_HOOK is not set +# CONFIG_KERNEL_SOFTTIMER=y +# CONFIG_KERNEL_IDLE_HOOK=y +# CONFIG_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_KTASK_STACKSIZE=512 +CONFIG_ZOMBIE_KTASK_STACKSIZE=512 +# CONFIG_KERNEL_TASK_ISOLATION is not set + +# +# Memory Management +# +# CONFIG_KERNEL_MEMBLOCK is not set + +# +# Command shell +# +CONFIG_TOOL_SHELL=y +CONFIG_SHELL_TASK_PRIORITY=4 +CONFIG_SHELL_TASK_STACK_SIZE=2048 + +# +# User Control +# +CONFIG_SHELL_DEFAULT_USER="letter" +CONFIG_SHELL_DEFAULT_USER_PASSWORD="" +CONFIG_SHELL_LOCK_TIMEOUT=10000 +CONFIG_SHELL_ENTER_CR_AND_LF=y +# CONFIG_SHELL_ENTER_CRLF is not set +CONFIG_SHELL_ENTER_CR=y +CONFIG_SHELL_ENTER_LF=y +CONFIG_SHELL_MAX_NUMBER=5 +CONFIG_SHELL_PARAMETER_MAX_NUMBER=8 +CONFIG_SHELL_HISTORY_MAX_NUMBER=5 +CONFIG_SHELL_PRINT_BUFFER=128 +CONFIG_SHELL_USING_CMD_EXPORT=y +# CONFIG_SHELL_HELP_LIST_USER is not set +CONFIG_SHELL_HELP_SHOW_PERMISSION=y +# CONFIG_SHELL_HELP_LIST_VAR is not set +# CONFIG_SHELL_HELP_LIST_KEY is not set +#CONFIG_KERNEL_QUEUEMANAGE=y +# CONFIG_KERNEL_WORKQUEUE is not set +CONFIG_WORKQUEUE_KTASK_STACKSIZE=256 +CONFIG_WORKQUEUE_KTASK_PRIORITY=2 +CONFIG_QUEUE_MAX=2 +CONFIG_KERNEL_WAITQUEUE=y +CONFIG_KERNEL_DATAQUEUE=y +# CONFIG_KERNEL_CIRCULAR_AREA is not set +# CONFIG_KERNEL_AVL_TREE is not set +CONFIG_NAME_MAX=32 +CONFIG_ALIGN_SIZE=8 +CONFIG_KERNEL_COMPONENTS_INIT=n +CONFIG_KERNEL_USER_MAIN=y +CONFIG_MAIN_KTASK_STACK_SIZE=2048 +CONFIG_ENV_INIT_KTASK_STACK_SIZE=2048 +CONFIG_MAIN_KTASK_PRIORITY=3 +# CONFIG_USER_TEST is not set +# CONFIG_TOOL_TEST_SEM is not set +# CONFIG_TOOL_TEST_MUTEX is not set +# CONFIG_TOOL_TEST_EVENT is not set +# CONFIG_TOOL_TEST_MSG is not set +# CONFIG_TOOL_TEST_AVLTREE is not set +# CONFIG_TEST_CRICULAR_AREA is not set +# CONFIG_TOOL_TEST_MEM is not set +# CONFIG_TOOL_TEST_TIMER is not set +# CONFIG_TOOL_TEST_IWG is not set +# CONFIG_TOOL_TEST_REALTIME is not set +# CONFIG_TOOL_TEST_DBG is not set +# CONFIG_TOOL_TEST_SCHED is not set +# CONFIG_KERNEL_DEBUG is not set +#CONFIG_DEBUG_INIT_CONFIG=y +#CONFIG_DBG_INIT=1 +#CONFIG_ARCH_SMP=y +#CONFIG_CPUS_NR=2 + +# +# hash table config +# +CONFIG_ID_HTABLE_SIZE=4 +CONFIG_ID_NUM_MAX=16 + +# +# File system +# +CONFIG_FS_DFS=n +#CONFIG_DFS_USING_WORKDIR=y +#CONFIG_FS_DFS_DEVFS=y + +# +# Fat filesystem +# + +# +# IOT-Device File system +# + +# +# Lwext4 filesystem +# + +# +# APP Framework +# + +# +# Perception +# +# CONFIG_PERCEPTION_SENSORDEVICE is not set + +# +# connection +# +# CONFIG_CONNECTION_AT is not set +# CONFIG_CONNECTION_MQTT is not set + +# +# medium communication +# + + +# +# Intelligence +# + +# +# Control +# + +# +# Lib +# +CONFIG_LIB=y +CONFIG_LIB_POSIX=y +CONFIG_LIB_NEWLIB=y + +# CONFIG_LITTLEVGL2RTT_USING_DEMO=y + +# +# Security +# diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/Kconfig b/Ubiquitous/XiUOS/board/cortex-m0-emulator/Kconfig new file mode 100644 index 000000000..14fad1f2a --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/Kconfig @@ -0,0 +1,56 @@ +mainmenu "XiUOS Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_CORTEX_M0_EVB + bool + select ARCH_ARM + default y + +config KERNEL_CONSOLE_DEVICE_NAME + string + default "uart0" + + +source "$KERNEL_DIR/arch/Kconfig" + +menu "cortex-m0 emulator feature" + source "$BSP_DIR/third_party_driver/Kconfig" + + menu "config default board resources" + menu "config board app name" + config BOARD_APP_NAME + string "config board app name" + default "/XiUOS_cortex-m0-emulator_app.bin" + endmenu + + menu "config board service table" + config SERVICE_TABLE_ADDRESS + hex "board service table address" + default 0x2007F0000 + endmenu + + endmenu + + config __STACKSIZE__ + int "stack size for interrupt" + default 4096 + +endmenu + + +menu "Hardware feature" +source "$KERNEL_DIR/resources/Kconfig" +endmenu + +source "$KERNEL_DIR/Kconfig" + + diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/Makefile b/Ubiquitous/XiUOS/board/cortex-m0-emulator/Makefile new file mode 100644 index 000000000..36f2e0089 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/Makefile @@ -0,0 +1,5 @@ +SRC_DIR := third_party_driver + +SRC_FILES := board.c connect_uart.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/README.md b/Ubiquitous/XiUOS/board/cortex-m0-emulator/README.md new file mode 100644 index 000000000..b8e80002f --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/README.md @@ -0,0 +1,187 @@ +# 从零开始构建矽璓工业物联操作系统：使用ARM架构的cortex-m0 emulator + +# cortex-m0 emulator + +[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓XiUOS是一款面向智慧车间的工业物联网操作系统，主要由一个极简的微型实时操作系统内核和其上的工业物联框架构成，通过高效管理工业物联网设备、支撑工业物联应用，在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”，促进以工业设备和工业控制系统为核心的人、机、物深度互联，帮助提升生产线的数字化和智能化水平。 + +## 1. 简介 + +Q‎EMU 是一个通用的开源模拟器和虚拟化工具。目前Q‎EMU已经可以较完整的支持ARM cortex-m0架构。XiUOS同样支持运行在Q‎EMU上 + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| microbit nRF51 | +|架构| cortex-m0 | +|主频| 50MHz | +|片内SRAM| 64KB | +| 外设支持 | UART | + +XiUOS板级当前支持使用UART。 + +## 2. 开发环境搭建 + +### 推荐使用： + +**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop) + +更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改） + +第一步:打开sources.list文件 + +```c +sudo vim /etc/apt/sources.list +``` + +第二步:将以下内容复制到sources.list文件 + +```c +deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +``` + +第三步:更新源和系统软件 + +```c +sudo apt-get update +sudo apt-get upgrade +``` + +**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb) + +### 依赖包安装： + +``` +$ sudo apt install build-essential pkg-config git +$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev +``` + +**XiUOS操作系统源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos) + +新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下： + +```c +mkdir test && cd test +git clone https://git.trustie.net/xuos/xiuos.git +``` + +打开源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| application | 应用代码 | +| board | 板级支持包 | +| framework | 应用框架 | +| fs | 文件系统 | +| kernel | 内核源码 | +| resources | 驱动文件 | +| tool | 系统工具 | + +使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示： + +
+ +
+ +### 裁减配置工具的下载 + +裁减配置工具： + +**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)，下载与安装的具体命令如下： + +```c +mkdir kfrontends && cd kfrontends +git clone https://git.trustie.net/xuos/kconfig-frontends.git +``` + +下载源码后按以下步骤执行软件安装： + +```c +cd kconfig-frontends + ./xs_build.sh +``` + +### 编译工具链： + +ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。 + +```shell +$ sudo apt install gcc-arm-none-eabi +``` + +## 编译说明 + +### 编辑环境：`Ubuntu18.04` + +### 编译工具链：`arm-none-eabi-gcc` +使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目 + + +编译步骤： + +1.在VScode命令终端中执行以下命令，生成配置文件 + +```c + make BOARD=cortex-m0-emulator menuconfig +``` + +2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置） + +![menuconfig](img/menuconfig.png) + +退出时选择`yes`保存上面所配置的内容，如下图所示： + +![menuconfig1](img/menuconfig1.png) + +3.继续执行以下命令，进行编译 + +``` +make BOARD=cortex-m0-emulator +``` + +4.如果编译正确无误，会产生XiUOS_cortex-m0-emulator.elf、XiUOS_cortex-m0-emulator.bin文件。 + +## 3. 运行 + +### 3.1 安装Q‎EMU + +``` +sudo apt install qemu-system-arm +``` + +### 3.2 运行结果 + +通过以下命令启动Q‎EMU并加载XiUOS ELF文件 + +``` +qemu-system-arm -machine microbit -nographic -kernel build/XiUOS_cortex-m0-emulator.elf +``` + +QEMU运行起来后将会在终端上看到信息打印输出 + +![terminal](img/terminal.png) + +### 3.3 调试 + +通过Q‎EMU可以方便的对XiUOS进行调试，首先安装gdb调试工具 +``` +sudo apt install gdb-multiarch +``` + +并通过以下命令启动Q‎EMU + +``` +qemu-system-arm -machine microbit -nographic -kernel build/XiUOS_cortex-m0-emulator.elf -s -S +``` + +然后要重新开启另一个linux系统终端一个终端，执行命令 + +``` +gdb-multiarch build/XiUOS_cortex-m0-emulator.elf -ex "target remote localhost:1234" +``` diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/board.c b/Ubiquitous/XiUOS/board/cortex-m0-emulator/board.c new file mode 100644 index 000000000..ec04ac244 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/board.c @@ -0,0 +1,39 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.c +* @brief support cortex-m3-emulator init configure and start-up +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-13 +*/ + + +#include +#include +#include +#include + +void SysTick_Handler(int irqn, void *arg) +{ + TickAndTaskTimesliceUpdate(); +} +DECLARE_HW_IRQ(SYSTICK_IRQN, SysTick_Handler, NONE); + +void InitBoardHardware() +{ + extern int InitHwUart(void); + InitHwUart(); + InstallConsole(SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1, SERIAL_DEVICE_NAME_1); + InitBoardMemory((void*)LM3S_SRAM_START, (void*)LM3S_SRAM_END); +} diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/board.h b/Ubiquitous/XiUOS/board/cortex-m0-emulator/board.h new file mode 100644 index 000000000..d07377c8b --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/board.h @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.h +* @brief define cortex-m3-emulator init configure and start-up function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-13 +*/ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + + +extern void *__bss_end; +extern void *_heap_end; +#define MEM_OFFSET 0x20001000 +#define LM3S_SRAM_START ( ( ((unsigned long)(&__bss_end)) > MEM_OFFSET)? (unsigned long)(&__bss_end):(MEM_OFFSET) ) +#define LM3S_SRAM_END ( &_heap_end ) + +#define BSP_USING_UART1 +#define SERIAL_BUS_NAME_1 "uart0" +#define SERIAL_DRV_NAME_1 "uart0_drv" +#define SERIAL_DEVICE_NAME_1 "uart0_dev0" + + + +#endif diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/config.mk b/Ubiquitous/XiUOS/board/cortex-m0-emulator/config.mk new file mode 100644 index 000000000..1ac914974 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/config.mk @@ -0,0 +1,14 @@ +export CROSS_COMPILE ?=/usr/bin/arm-none-eabi- + +export CFLAGS := -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb +export AFLAGS := -c -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2 +export LFLAGS := -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_cortex-m0-emulator.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds +export CXXFLAGS := -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g + +export APPLFLAGS := -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds + + +export DEFINES := -DHAVE_CCONFIG_H -g + +export ARCH = arm +export MCU = cortex-m0 diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/connect_uart.c b/Ubiquitous/XiUOS/board/cortex-m0-emulator/connect_uart.c new file mode 100644 index 000000000..bc3e068f1 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/connect_uart.c @@ -0,0 +1,331 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_uart.c +* @brief support cortex_m3_emulator board uart function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-10 +*/ + +#include +#include +#include +#include +#include +#include +#include + +#define NO_IMPL() KPrintf("%s is not implemented!\n", __func__) + +#ifdef BSP_USING_UART1 +static struct SerialBus serial_bus_1; +static struct SerialDriver serial_driver_1; +static struct SerialHardwareDevice serial_device_1; +#endif +#ifdef BSP_USING_UART2 +static struct SerialBus serial_bus_2; +static struct SerialDriver serial_driver_2; +static struct SerialHardwareDevice serial_device_2; +#endif + +static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new) +{ + struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg; + struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg; + + if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) { + data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate; + } + + if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) { + data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order; + } + + if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) { + data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size; + } + + if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) { + data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits; + } + + if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) { + data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode; + } + + if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) { + data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode; + } + + if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) { + data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits; + } +} + +static void UartHandler(struct SerialBus *serial_bus, struct SerialDriver *serial_drv) +{ + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_bus->bus.owner_haldev; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + + uint32 status; + + status = UARTIntStatus(serial_cfg->hw_cfg.serial_register_base, RET_TRUE); + + /* clear interrupt status */ + UARTIntClear(serial_cfg->hw_cfg.serial_register_base, status); + + while (UARTCharsAvail(serial_cfg->hw_cfg.serial_register_base)) { + SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND); + } + +} + +#ifdef BSP_USING_UART1 +void UartIsr1(int vector, void *param) +{ + /* get serial bus 1 */ + UartHandler(&serial_bus_1, &serial_driver_1); +} +DECLARE_HW_IRQ(UART1_IRQn, UartIsr1, NONE); +#endif + +#ifdef BSP_USING_UART2 +void UartIsr2(int irqno) +{ + /* get serial bus 2 */ + UartHandler(&serial_bus_2, &serial_driver_2); +} +#endif + +static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(serial_drv); + + return EOK; +} + +static uint32 SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd) +{ + NO_IMPL(); + return 0; +} + +static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + int serial_operation_cmd; + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = SerialInit(serial_drv, configure_info); + break; + case OPE_CFG: + serial_operation_cmd = *(int *)configure_info->private_data; + ret = SerialConfigure(serial_drv, serial_operation_cmd); + break; + default: + break; + } + + return ret; +} + +static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + while (UARTCharPutNonBlocking(serial_cfg->hw_cfg.serial_register_base, c) == RET_FALSE); + + return 0; +} + +static int SerialGetChar(struct SerialHardwareDevice *serial_dev) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + long val = UARTCharGetNonBlocking(serial_cfg->hw_cfg.serial_register_base); + if (val > 0) + return (int)val; + else + return -1; +} + +static const struct SerialDataCfg data_cfg_init = +{ + .serial_baud_rate = BAUD_RATE_115200, + .serial_data_bits = DATA_BITS_8, + .serial_stop_bits = STOP_BITS_1, + .serial_parity_mode = PARITY_NONE, + .serial_bit_order = BIT_ORDER_LSB, + .serial_invert_mode = NRZ_NORMAL, + .serial_buffer_size = SERIAL_RB_BUFSZ, +}; + +/*manage the serial device operations*/ +static const struct SerialDrvDone drv_done = +{ + .init = SerialInit, + .configure = SerialConfigure, +}; + +/*manage the serial device hal operations*/ +static struct SerialHwDevDone hwdev_done = +{ + .put_char = SerialPutChar, + .get_char = SerialGetChar, +}; + +static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name) +{ + + x_err_t ret = EOK; + + /*Init the serial bus */ + + ret = SerialBusInit(serial_bus, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialBusInit error %d\n", ret); + return ERROR; + } + + /*Init the serial driver*/ + ret = SerialDriverInit(serial_driver, drv_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the serial driver to the serial bus*/ + ret = SerialDriverAttachToBus(drv_name, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the serial device to the serial bus*/ +static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name) +{ + x_err_t ret = EOK; + + ret = SerialDeviceRegister(serial_device, serial_param, dev_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDeviceInit device %s error %d\n", dev_name, ret); + return ERROR; + } + + ret = SerialDeviceAttachToBus(dev_name, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDeviceAttachToBus device %s error %d\n", dev_name, ret); + return ERROR; + } + + return ret; +} + +int InitHwUart(void) +{ + x_err_t ret = EOK; + + UARTlInitialize(); +#ifdef BSP_USING_UART1 + memset(&serial_bus_1, 0, sizeof(struct SerialBus)); + memset(&serial_driver_1, 0, sizeof(struct SerialDriver)); + memset(&serial_device_1, 0, sizeof(struct SerialHardwareDevice)); + + static struct SerialCfgParam serial_cfg_1; + memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam)); + + static struct SerialDevParam serial_dev_param_1; + memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam)); + + serial_driver_1.drv_done = &drv_done; + serial_driver_1.configure = &SerialDrvConfigure; + serial_device_1.hwdev_done = &hwdev_done; + + serial_cfg_1.data_cfg = data_cfg_init; + + serial_cfg_1.hw_cfg.serial_register_base = UART0_BASE; + serial_driver_1.private_data = (void *)&serial_cfg_1; + + serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX; + serial_device_1.haldev.private_data = (void *)&serial_dev_param_1; + + /* enable UART0 clock */ + // SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + // SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + /* set UART0 pinmux */ + // GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); + + /* Configure the UART for 115,200, 8-N-1 operation. */ + // UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), serial_cfg_1.data_cfg.serial_baud_rate, + // (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | + // UART_CONFIG_PAR_NONE)); + + ret = BoardSerialBusInit(&serial_bus_1, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_DEVICE_NAME_1); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_UART2 + memset(&serial_bus_2, 0, sizeof(struct SerialBus)); + memset(&serial_driver_2, 0, sizeof(struct SerialDriver)); + memset(&serial_device_2, 0, sizeof(struct SerialHardwareDevice)); + + static struct SerialCfgParam serial_cfg_2; + memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam)); + + static struct SerialDevParam serial_dev_param_2; + memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam)); + + serial_driver_2.drv_done = &drv_done; + serial_driver_2.configure = &SerialDrvConfigure; + serial_device_2.hwdev_done = &hwdev_done; + + serial_cfg_2.data_cfg = data_cfg_init; + + serial_cfg_2.hw_cfg.serial_register_base = UART1_BASE; + serial_driver_2.private_data = (void *)&serial_cfg_2; + + serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX | SIGN_OPER_POLL_RX; + serial_device_2.haldev.private_data = (void *)&serial_dev_param_2; + + ret = BoardSerialBusInit(&serial_bus_2, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_DEVICE_NAME_2); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } +#endif + return ret; +} diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/link.lds b/Ubiquitous/XiUOS/board/cortex-m0-emulator/link.lds new file mode 100644 index 000000000..294200574 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/link.lds @@ -0,0 +1,72 @@ + +MEMORY { + flash (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 +} + +OUTPUT_FORMAT ("elf32-littlearm") +__SYSTEM_STACKSIZE__ = 0x400; + +ENTRY(Reset_Handler) +SECTIONS { + .text : { + . = ALIGN(4); + KEEP(*(.isr_vector)) + . = ALIGN(4); + *(.text*) + *(.rodata*) + + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(4); + + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(4); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + + PROVIDE(_etext = ABSOLUTE(.)); + _etext = .; + } > flash = 0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + _sidata = .; + } > flash + __exidx_end = .; + + .data : AT (_sidata) { + . = ALIGN(4); + _sdata = .; + *(.data*) + . = ALIGN(4); + _edata = .; + } > sram + + .bss : { + . = ALIGN(4); + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } > sram + __bss_end = .; + __end = .; + + .stack ORIGIN(sram) + LENGTH(sram) - __SYSTEM_STACKSIZE__ : + { + PROVIDE( _heap_end = . ); + . = __SYSTEM_STACKSIZE__; + PROVIDE( _sp = . ); + } >sram +} diff --git a/APP_Framework/Framework/connection/5G/Kconfig b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Kconfig similarity index 100% rename from APP_Framework/Framework/connection/5G/Kconfig rename to Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Kconfig diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/Makefile b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/Makefile new file mode 100644 index 000000000..78b02eb44 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/Makefile @@ -0,0 +1,3 @@ +SRC_DIR := driverlib + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/Makefile b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/Makefile new file mode 100644 index 000000000..b456f10ac --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := uart.c +# SRC_FILES := uart.c +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/gpio.h b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/gpio.h new file mode 100644 index 000000000..3631cd73f --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/gpio.h @@ -0,0 +1,13 @@ +#pragma once +/* GPIO */ +#define GPIO_DIRSET ADDR(0x50000518) +#define GPIO_DIRCLR ADDR(0x5000051c) +#define GPIO_PINCNF ARRAY(0x50000700) + +#define GPIO_PINCNF_PULL_Pos 2 +#define GPIO_PINCNF_PULL_Wid 2 +#define GPIO_Pullup 0x3 + +#define GPIO_PINCNF_DRIVE_Pos 8 +#define GPIO_PINCNF_DRIVE_Wid 3 +#define GPIO_S0D1 0x6 // Open drain \ No newline at end of file diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/opt.h b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/opt.h new file mode 100644 index 000000000..939a450c2 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/opt.h @@ -0,0 +1,23 @@ +#define BIT(i) (1 << (i)) + +#define SET_BIT(reg, n) reg |= BIT(n) +#define CLR_BIT(reg, n) reg &= ~BIT(n) + +#define SET_FIELD(reg, field, val) \ + reg = (reg & ~MASK(field)) | FIELD(field, val) + +#define GET_FIELD(reg, field) \ + ((reg >> field##_Pos) & MASK0(field)) + +#define FIELD(field, val) \ + (((val) & MASK0(field)) << field##_Pos) + +#define MASK(field) (MASK0(field) << field##_Pos) + +#define MASK0(field) (~((-2) << (field##_Wid-1))) + +#define SET_BYTE(reg, n, v) \ + reg = (reg & ~(0xff << 8*n)) | ((v & 0xff) << 8*n) + +#define ADDR(x) (* (unsigned volatile *) (x)) +#define ARRAY(x) ((unsigned volatile *) (x)) diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/uart.c b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/uart.c new file mode 100644 index 000000000..5e4f70e93 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/uart.c @@ -0,0 +1,156 @@ +//***************************************************************************** +// +// uart.c - Driver for the UART. +// +// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 10636 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup uart_api +//! @{ +// +//***************************************************************************** +#include + +#include "inc/hw_types.h" +#include "inc/hw_nvic.h" +#include "driverlib/uart.h" +#include "driverlib/gpio.h" +#include "driverlib/opt.h" + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt enable for that +// interrupt. +// +//***************************************************************************** +static const unsigned long g_pulEnRegs[] = +{ + NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4 +}; + +void UARTlInitialize(void) { + GPIO_DIRSET = BIT(USB_TX); + GPIO_DIRCLR = BIT(USB_RX); + SET_FIELD(GPIO_PINCNF[USB_TX], GPIO_PINCNF_PULL, GPIO_Pullup); + SET_FIELD(GPIO_PINCNF[USB_RX], GPIO_PINCNF_PULL, GPIO_Pullup); + + UART_BAUDRATE = UART_BAUD_9600; // 9600 baud + UART_CONFIG = 0; // format 8N1 + UART_PSELTXD = USB_TX; // choose pins + UART_PSELRXD = USB_RX; + /* Configure the uart device interrupt */ + UART_ENABLE = UART_Enabled; + UART_INTENSET = (1 << 17) | (1<<2); + UART_STARTTX = 1; + UART_STARTRX = 1; + UART_RXDRDY = 0; + UART_TXDRDY = 1; + /* Enable the uart interrupt in NVIC */ + HWREG(g_pulEnRegs[(18 - 16) / 32]) = 1 << ((18 - 16) & 31); +} + +void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig) +{ + NO_IMPL(); +} + +tBoolean UARTCharsAvail(unsigned long ulBase) +{ + return UART_RXDRDY; +} + +long UARTCharGetNonBlocking(unsigned long ulBase) +{ + char ch; + + if (UART_RXDRDY) { + UART_RXDRDY = 0; + ch = UART_RXD; + return ch; + } + return -1; +} + +long UARTCharGet(unsigned long ulBase) +{ + char ch; + + while (!UART_RXDRDY); + UART_RXDRDY = 0; + ch = UART_RXD; + return ch; +} + +tBoolean UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData) +{ + if (UART_TXDRDY) { + UART_TXDRDY = 0; + UART_TXD = ucData; + return true; + } + return false; +} + +void UARTCharPut(unsigned long ulBase, unsigned char ucData) +{ + while (!UART_TXDRDY); + UART_TXDRDY = 0; + UART_TXD = ucData; +} + +void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + NO_IMPL(); +} + +void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + NO_IMPL(); +} + +unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + return UART_INTENCLR; +} + +void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + UART_INTENCLR = ulIntFlags; + UART_INTENSET = ulIntFlags; +} diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/uart.h b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/uart.h new file mode 100644 index 000000000..c4516ee4a --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/uart.h @@ -0,0 +1,70 @@ +#ifndef __UART_H__ +#define __UART_H__ + +#include + +#define NO_IMPL() KPrintf("%s is not implemented!\n", __func__) + +/* Device pins */ +#define USB_TX 24 +#define USB_RX 25 + +/* UART */ +#define UART_STARTRX ADDR(0x40002000) +#define UART_STARTTX ADDR(0x40002008) +#define UART_RXDRDY ADDR(0x40002108) +#define UART_TXDRDY ADDR(0x4000211c) +#define UART_ENABLE ADDR(0x40002500) +#define UART_PSELTXD ADDR(0x4000250c) +#define UART_PSELRXD ADDR(0x40002514) +#define UART_RXD ADDR(0x40002518) +#define UART_TXD ADDR(0x4000251c) +#define UART_BAUDRATE ADDR(0x40002524) +#define UART_CONFIG ADDR(0x4000256c) +#define UART_INTEN ADDR(0x40002300) +#define UART_INTENSET ADDR(0x40002304) +#define UART_INTENCLR ADDR(0x40002308) + +#define UART_Enabled 0x4 +#define UART_INT_TXDRDY 7 +#define UART_INT_RXDRDY 2 + +#define UART_BAUD_9600 0x00275000 + +#ifdef __cplusplus +extern "C" +{ +#endif + +extern void UARTlInitialize(void); +extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern long UARTCharGetNonBlocking(unsigned long ulBase); +long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifndef DEPRECATED + +#define UARTCharNonBlockingGet(a) \ + UARTCharGetNonBlocking(a) +#define UARTCharNonBlockingPut(a, b) \ + UARTCharPutNonBlocking(a, b) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ \ No newline at end of file diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_memmap.h b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_memmap.h new file mode 100644 index 000000000..64a036663 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_memmap.h @@ -0,0 +1,44 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 10636 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +#define UART0_BASE 0x40002000 // UART0 +#endif \ No newline at end of file diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_nvic.h b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_nvic.h new file mode 100644 index 000000000..20c68e9e8 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_nvic.h @@ -0,0 +1,1717 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 10636 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following are defines for the NVIC register addresses. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status + // Register +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable +#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable +#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable +#define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable +#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable +#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable +#define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending +#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending +#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending +#define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending +#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending +#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending +#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit +#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit +#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit +#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority +#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority +#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority +#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority +#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority +#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority +#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority +#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority +#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority +#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority +#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority +#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority +#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority +#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority +#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority +#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority +#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority +#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority +#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority +#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority +#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority +#define NVIC_PRI34 0xE000E488 // Interrupt 136-138 Priority +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset + // Control +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_CPAC 0xE000ED88 // Coprocessor Access Control +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size + // Alias 1 +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size + // Alias 2 +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size + // Alias 3 +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt +#define NVIC_FPCC 0xE000EF34 // Floating-Point Context Control +#define NVIC_FPCA 0xE000EF38 // Floating-Point Context Address +#define NVIC_FPDSC 0xE000EF3C // Floating-Point Default Status + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating + // Point +#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN2 register. +// +//***************************************************************************** +#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN3 register. +// +//***************************************************************************** +#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN4 register. +// +//***************************************************************************** +#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable +#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS2 register. +// +//***************************************************************************** +#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS3 register. +// +//***************************************************************************** +#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS4 register. +// +//***************************************************************************** +#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend +#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND2 register. +// +//***************************************************************************** +#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND3 register. +// +//***************************************************************************** +#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND4 register. +// +//***************************************************************************** +#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend +#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND2 register. +// +//***************************************************************************** +#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND3 register. +// +//***************************************************************************** +#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND4 register. +// +//***************************************************************************** +#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active +#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE2 register. +// +//***************************************************************************** +#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE3 register. +// +//***************************************************************************** +#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE4 register. +// +//***************************************************************************** +#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI14 register. +// +//***************************************************************************** +#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask +#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask +#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask +#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask +#define NVIC_PRI14_INTD_S 29 +#define NVIC_PRI14_INTC_S 21 +#define NVIC_PRI14_INTB_S 13 +#define NVIC_PRI14_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI15 register. +// +//***************************************************************************** +#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask +#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask +#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask +#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask +#define NVIC_PRI15_INTD_S 29 +#define NVIC_PRI15_INTC_S 21 +#define NVIC_PRI15_INTB_S 13 +#define NVIC_PRI15_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI16 register. +// +//***************************************************************************** +#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask +#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask +#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask +#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask +#define NVIC_PRI16_INTD_S 29 +#define NVIC_PRI16_INTC_S 21 +#define NVIC_PRI16_INTB_S 13 +#define NVIC_PRI16_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI17 register. +// +//***************************************************************************** +#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask +#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask +#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask +#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask +#define NVIC_PRI17_INTD_S 29 +#define NVIC_PRI17_INTC_S 21 +#define NVIC_PRI17_INTB_S 13 +#define NVIC_PRI17_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI18 register. +// +//***************************************************************************** +#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask +#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask +#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask +#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask +#define NVIC_PRI18_INTD_S 29 +#define NVIC_PRI18_INTC_S 21 +#define NVIC_PRI18_INTB_S 13 +#define NVIC_PRI18_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI19 register. +// +//***************************************************************************** +#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask +#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask +#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask +#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask +#define NVIC_PRI19_INTD_S 29 +#define NVIC_PRI19_INTC_S 21 +#define NVIC_PRI19_INTB_S 13 +#define NVIC_PRI19_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI20 register. +// +//***************************************************************************** +#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask +#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask +#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask +#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask +#define NVIC_PRI20_INTD_S 29 +#define NVIC_PRI20_INTC_S 21 +#define NVIC_PRI20_INTB_S 13 +#define NVIC_PRI20_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI21 register. +// +//***************************************************************************** +#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask +#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask +#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask +#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask +#define NVIC_PRI21_INTD_S 29 +#define NVIC_PRI21_INTC_S 21 +#define NVIC_PRI21_INTB_S 13 +#define NVIC_PRI21_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI22 register. +// +//***************************************************************************** +#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask +#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask +#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask +#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask +#define NVIC_PRI22_INTD_S 29 +#define NVIC_PRI22_INTC_S 21 +#define NVIC_PRI22_INTB_S 13 +#define NVIC_PRI22_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI23 register. +// +//***************************************************************************** +#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask +#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask +#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask +#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask +#define NVIC_PRI23_INTD_S 29 +#define NVIC_PRI23_INTC_S 21 +#define NVIC_PRI23_INTB_S 13 +#define NVIC_PRI23_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI24 register. +// +//***************************************************************************** +#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask +#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask +#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask +#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask +#define NVIC_PRI24_INTD_S 29 +#define NVIC_PRI24_INTC_S 21 +#define NVIC_PRI24_INTB_S 13 +#define NVIC_PRI24_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI25 register. +// +//***************************************************************************** +#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask +#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask +#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask +#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask +#define NVIC_PRI25_INTD_S 29 +#define NVIC_PRI25_INTC_S 21 +#define NVIC_PRI25_INTB_S 13 +#define NVIC_PRI25_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI26 register. +// +//***************************************************************************** +#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask +#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask +#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask +#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask +#define NVIC_PRI26_INTD_S 29 +#define NVIC_PRI26_INTC_S 21 +#define NVIC_PRI26_INTB_S 13 +#define NVIC_PRI26_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI27 register. +// +//***************************************************************************** +#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask +#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask +#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask +#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask +#define NVIC_PRI27_INTD_S 29 +#define NVIC_PRI27_INTC_S 21 +#define NVIC_PRI27_INTB_S 13 +#define NVIC_PRI27_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI28 register. +// +//***************************************************************************** +#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask +#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask +#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask +#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask +#define NVIC_PRI28_INTD_S 29 +#define NVIC_PRI28_INTC_S 21 +#define NVIC_PRI28_INTB_S 13 +#define NVIC_PRI28_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI29 register. +// +//***************************************************************************** +#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask +#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask +#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask +#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask +#define NVIC_PRI29_INTD_S 29 +#define NVIC_PRI29_INTC_S 21 +#define NVIC_PRI29_INTB_S 13 +#define NVIC_PRI29_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI30 register. +// +//***************************************************************************** +#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask +#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask +#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask +#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask +#define NVIC_PRI30_INTD_S 29 +#define NVIC_PRI30_INTC_S 21 +#define NVIC_PRI30_INTB_S 13 +#define NVIC_PRI30_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI31 register. +// +//***************************************************************************** +#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask +#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask +#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask +#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask +#define NVIC_PRI31_INTD_S 29 +#define NVIC_PRI31_INTC_S 21 +#define NVIC_PRI31_INTB_S 13 +#define NVIC_PRI31_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI32 register. +// +//***************************************************************************** +#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask +#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask +#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask +#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask +#define NVIC_PRI32_INTD_S 29 +#define NVIC_PRI32_INTC_S 21 +#define NVIC_PRI32_INTB_S 13 +#define NVIC_PRI32_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI33 register. +// +//***************************************************************************** +#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI33_INTD_S 29 +#define NVIC_PRI33_INTC_S 21 +#define NVIC_PRI33_INTB_S 13 +#define NVIC_PRI33_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI34 register. +// +//***************************************************************************** +#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI34_INTD_S 29 +#define NVIC_PRI34_INTC_S 21 +#define NVIC_PRI34_INTB_S 13 +#define NVIC_PRI34_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPAC register. +// +//***************************************************************************** +#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only +#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access +#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only +#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_NUMBER +// register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE_ADDR_S 5 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access +#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none +#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only +#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw +#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none +#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro +#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable +#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable +#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable +#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable +#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable +#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable +#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable +#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable +#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable +#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable +#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable +#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes +#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes +#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes +#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes +#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes +#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes +#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes +#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes +#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes +#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes +#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes +#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes +#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes +#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes +#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes +#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes +#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes +#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes +#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes +#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes +#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes +#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes +#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes +#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes +#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes +#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes +#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes +#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes +#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE1_ADDR_S 5 +#define NVIC_MPU_BASE1_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR1_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR1_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR1_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE2_ADDR_S 5 +#define NVIC_MPU_BASE2_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR2_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR2_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR2_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE3_ADDR_S 5 +#define NVIC_MPU_BASE3_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR3_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR3_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR3_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID +#define NVIC_SW_TRIG_INTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCC register. +// +//***************************************************************************** +#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation + // Enable +#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable +#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready +#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready +#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready +#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready +#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode +#define NVIC_FPCC_USER 0x00000002 // User Privilege Level +#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCA register. +// +//***************************************************************************** +#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address +#define NVIC_FPCA_ADDRESS_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPDSC register. +// +//***************************************************************************** +#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default +#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default +#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default +#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default +#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode +#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) + // mode +#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity + // (RM) mode +#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode + +#endif // __HW_NVIC_H__ diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_types.h b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_types.h new file mode 100644 index 000000000..8339305e7 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_types.h @@ -0,0 +1,212 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 10636 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +//***************************************************************************** +// +// Helper Macros for determining silicon revisions, etc. +// +// These macros will be used by Driverlib at "run-time" to create necessary +// conditional code blocks that will allow a single version of the Driverlib +// "binary" code to support multiple(all) Stellaris silicon revisions. +// +// It is expected that these macros will be used inside of a standard 'C' +// conditional block of code, e.g. +// +// if(CLASS_IS_SANDSTORM) +// { +// do some Sandstorm-class specific code here. +// } +// +// By default, these macros will be defined as run-time checks of the +// appropriate register(s) to allow creation of run-time conditional code +// blocks for a common DriverLib across the entire Stellaris family. +// +// However, if code-space optimization is required, these macros can be "hard- +// coded" for a specific version of Stellaris silicon. Many compilers will +// then detect the "hard-coded" conditionals, and appropriately optimize the +// code blocks, eliminating any "unreachable" code. This would result in +// a smaller Driverlib, thus producing a smaller final application size, but +// at the cost of limiting the Driverlib binary to a specific Stellaris +// silicon revision. +// +//***************************************************************************** +#ifndef CLASS_IS_SANDSTORM +#define CLASS_IS_SANDSTORM \ + (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) || \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM))) +#endif + +#ifndef CLASS_IS_FURY +#define CLASS_IS_FURY \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY)) +#endif + +#ifndef CLASS_IS_DUSTDEVIL +#define CLASS_IS_DUSTDEVIL \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL)) +#endif + +#ifndef CLASS_IS_TEMPEST +#define CLASS_IS_TEMPEST \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TEMPEST)) +#endif + +#ifndef CLASS_IS_FIRESTORM +#define CLASS_IS_FIRESTORM \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FIRESTORM)) +#endif + +#ifndef REVISION_IS_A0 +#define REVISION_IS_A0 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_A1 +#define REVISION_IS_A1 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_A2 +#define REVISION_IS_A2 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2)) +#endif + +#ifndef REVISION_IS_B0 +#define REVISION_IS_B0 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_B1 +#define REVISION_IS_B1 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1)) +#endif + +#ifndef REVISION_IS_C0 +#define REVISION_IS_C0 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_C1 +#define REVISION_IS_C1 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1)) +#endif + +#ifndef REVISION_IS_C2 +#define REVISION_IS_C2 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2)) +#endif + +#ifndef REVISION_IS_C3 +#define REVISION_IS_C3 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_3)) +#endif + +#ifndef REVISION_IS_C5 +#define REVISION_IS_C5 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_5)) +#endif + +//***************************************************************************** +// +// Deprecated silicon class and revision detection macros. +// +//***************************************************************************** +#ifndef DEPRECATED +#define DEVICE_IS_SANDSTORM CLASS_IS_SANDSTORM +#define DEVICE_IS_FURY CLASS_IS_FURY +#define DEVICE_IS_REVA2 REVISION_IS_A2 +#define DEVICE_IS_REVC1 REVISION_IS_C1 +#define DEVICE_IS_REVC2 REVISION_IS_C2 +#endif + +#endif // __HW_TYPES_H__ diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Makefile b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Makefile new file mode 100644 index 000000000..15ac75206 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Makefile @@ -0,0 +1,3 @@ +SRC_DIR := Libraries + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiUOS/board/cortex-m3-emulator/.defconfig b/Ubiquitous/XiUOS/board/cortex-m3-emulator/.defconfig index bff68ddf8..1b0f2cf08 100644 --- a/Ubiquitous/XiUOS/board/cortex-m3-emulator/.defconfig +++ b/Ubiquitous/XiUOS/board/cortex-m3-emulator/.defconfig @@ -4,11 +4,6 @@ # CONFIG_BOARD_CORTEX_M3_EVB=y CONFIG_KERNEL_CONSOLE_DEVICE_NAME="uart0" -#CONFIG_LED0=24 -#CONFIG_LED1=25 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_RISCV32=y -CONFIG_ARCH_CPU_32BIT=y # # cortex-m3-emulator feature @@ -41,7 +36,7 @@ CONFIG___STACKSIZE__=4096 CONFIG_RESOURCES_SERIAL=y # CONFIG_SERIAL_USING_DMA=y CONFIG_SERIAL_RB_BUFSZ=64 -CONFIG_FS_VFS=n +CONFIG_FS_VFS=y # CONFIG_RESOURCES_HWTIMER is not set # CONFIG_RESOURCES_I2C is not set # CONFIG_RESOURCES_LCD is not set @@ -100,8 +95,8 @@ CONFIG_SMALL_NUMBER_64B=16 # # CONFIG_KERNEL_SEMAPHORE=y # CONFIG_KERNEL_MUTEX=y -CONFIG_KERNEL_EVENT=n -CONFIG_KERNEL_MESSAGEQUEUE=n +CONFIG_KERNEL_EVENT=y +CONFIG_KERNEL_MESSAGEQUEUE=y CONFIG_KTASK_PRIORITY_8=y CONFIG_KTASK_PRIORITY_MAX=8 CONFIG_TICK_PER_SECOND=100 @@ -115,11 +110,6 @@ CONFIG_IDLE_KTASK_STACKSIZE=512 CONFIG_ZOMBIE_KTASK_STACKSIZE=512 # CONFIG_KERNEL_TASK_ISOLATION is not set -# -# Memory Management -# -# CONFIG_KERNEL_MEMBLOCK is not set - # # Command shell # diff --git a/Ubiquitous/XiUOS/board/hifive1-emulator/.defconfig b/Ubiquitous/XiUOS/board/hifive1-emulator/.defconfig index c6451fff5..1502a964d 100644 --- a/Ubiquitous/XiUOS/board/hifive1-emulator/.defconfig +++ b/Ubiquitous/XiUOS/board/hifive1-emulator/.defconfig @@ -41,7 +41,7 @@ CONFIG___STACKSIZE__=1024 CONFIG_RESOURCES_SERIAL=y # CONFIG_SERIAL_USING_DMA=y CONFIG_SERIAL_RB_BUFSZ=64 -CONFIG_FS_VFS=n +CONFIG_FS_VFS=y # CONFIG_RESOURCES_HWTIMER is not set # CONFIG_RESOURCES_I2C is not set # CONFIG_RESOURCES_LCD is not set @@ -98,8 +98,8 @@ CONFIG_MM_PAGE_SIZE=1024 # # CONFIG_KERNEL_SEMAPHORE=y # CONFIG_KERNEL_MUTEX=y -CONFIG_KERNEL_EVENT=n -CONFIG_KERNEL_MESSAGEQUEUE=n +CONFIG_KERNEL_EVENT=y +CONFIG_KERNEL_MESSAGEQUEUE=y CONFIG_KTASK_PRIORITY_8=y CONFIG_KTASK_PRIORITY_MAX=8 CONFIG_TICK_PER_SECOND=100 @@ -113,11 +113,6 @@ CONFIG_IDLE_KTASK_STACKSIZE=512 CONFIG_ZOMBIE_KTASK_STACKSIZE=512 # CONFIG_KERNEL_TASK_ISOLATION is not set -# -# Memory Management -# -# CONFIG_KERNEL_MEMBLOCK is not set - # # Command shell # diff --git a/Ubiquitous/XiUOS/board/hifive1-rev-B/.defconfig b/Ubiquitous/XiUOS/board/hifive1-rev-B/.defconfig index 26e9621e7..3c68a127e 100644 --- a/Ubiquitous/XiUOS/board/hifive1-rev-B/.defconfig +++ b/Ubiquitous/XiUOS/board/hifive1-rev-B/.defconfig @@ -41,7 +41,7 @@ CONFIG___STACKSIZE__=1024 CONFIG_RESOURCES_SERIAL=y # CONFIG_SERIAL_USING_DMA=y CONFIG_SERIAL_RB_BUFSZ=64 -CONFIG_FS_VFS=n +CONFIG_FS_VFS=y # CONFIG_RESOURCES_HWTIMER is not set # CONFIG_RESOURCES_I2C is not set # CONFIG_RESOURCES_LCD is not set @@ -98,8 +98,8 @@ CONFIG_MM_PAGE_SIZE=1024 # # CONFIG_KERNEL_SEMAPHORE=y # CONFIG_KERNEL_MUTEX=y -CONFIG_KERNEL_EVENT=n -CONFIG_KERNEL_MESSAGEQUEUE=n +CONFIG_KERNEL_EVENT=y +CONFIG_KERNEL_MESSAGEQUEUE=y CONFIG_KTASK_PRIORITY_8=y CONFIG_KTASK_PRIORITY_MAX=8 CONFIG_TICK_PER_SECOND=100 @@ -113,11 +113,6 @@ CONFIG_IDLE_KTASK_STACKSIZE=512 CONFIG_ZOMBIE_KTASK_STACKSIZE=512 # CONFIG_KERNEL_TASK_ISOLATION is not set -# -# Memory Management -# -# CONFIG_KERNEL_MEMBLOCK is not set - # # Command shell # diff --git a/Ubiquitous/XiUOS/board/stm32f407-st-discovery/third_party_driver/uart/Kconfig b/Ubiquitous/XiUOS/board/stm32f407-st-discovery/third_party_driver/uart/Kconfig index 9ad064d63..79ce0890c 100644 --- a/Ubiquitous/XiUOS/board/stm32f407-st-discovery/third_party_driver/uart/Kconfig +++ b/Ubiquitous/XiUOS/board/stm32f407-st-discovery/third_party_driver/uart/Kconfig @@ -52,7 +52,7 @@ menuconfig BSP_USING_UART4 default "uart4" config SERIAL_DRV_NAME_4 string "serial bus 4 driver name" - default "uart4drv" + default "uart4_drv" config SERIAL_4_DEVICE_NAME_0 string "serial bus 4 device 0 name" default "uart4_dev4" diff --git a/Ubiquitous/XiUOS/path_kernel.mk b/Ubiquitous/XiUOS/path_kernel.mk index 438881908..cc90ee59e 100755 --- a/Ubiquitous/XiUOS/path_kernel.mk +++ b/Ubiquitous/XiUOS/path_kernel.mk @@ -128,6 +128,17 @@ KERNELPATHS :=-I$(BSP_ROOT) \ -I$(KERNEL_ROOT)/include # endif +ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/cortex-m0-emulator) +KERNELPATHS :=-I$(BSP_ROOT) \ + -I$(KERNEL_ROOT)/arch/arm/cortex-m0 \ + -I$(BSP_ROOT)/third_party_driver \ + -I$(BSP_ROOT)/third_party_driver/Libraries/driverlib \ + -I$(BSP_ROOT)/third_party_driver/Libraries/ \ + -I$(BSP_ROOT)/third_party_driver/Libraries/inc \ + -I$(KERNEL_ROOT)/include \ + -I$(BSP_ROOT)/include # +endif + ifeq ($(BSP_ROOT),$(KERNEL_ROOT)/board/cortex-m3-emulator) KERNELPATHS :=-I$(BSP_ROOT) \ -I$(KERNEL_ROOT)/arch/arm/cortex-m3 \ @@ -188,6 +199,7 @@ endif ifeq ($(CONFIG_SUPPORT_CONNECTION_FRAMEWORK), y) KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/connection # +KERNELPATHS += -I$(KERNEL_ROOT)/../../APP_Framework/Framework/connection/zigbee # endif ifeq ($(CONFIG_SUPPORT_KNOWING_FRAMEWORK), y) diff --git a/Ubiquitous/XiUOS/resources/include/dev_serial.h b/Ubiquitous/XiUOS/resources/include/dev_serial.h index 8672e3c4e..146202f8a 100644 --- a/Ubiquitous/XiUOS/resources/include/dev_serial.h +++ b/Ubiquitous/XiUOS/resources/include/dev_serial.h @@ -73,6 +73,7 @@ extern "C" { #define SERIAL_DMA_RX 0x01 #define SERIAL_DMA_TX 0x02 +#define KEY_LENGTH 8 struct SerialTx { diff --git a/Ubiquitous/XiUOS/resources/serial/dev_serial.c b/Ubiquitous/XiUOS/resources/serial/dev_serial.c index 46a042dfb..f12cb1d0b 100644 --- a/Ubiquitous/XiUOS/resources/serial/dev_serial.c +++ b/Ubiquitous/XiUOS/resources/serial/dev_serial.c @@ -122,30 +122,41 @@ static inline int SerialDevIntRead(struct SerialHardwareDevice *serial_dev, stru NULL_PARAM_CHECK(serial_dev); NULL_PARAM_CHECK(read_param); + int char_num = 0; struct SerialHwDevDone *hwdev_done = serial_dev->hwdev_done; struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; uint8 *read_data = (uint8 *)read_param->buffer; x_size_t read_length = read_param->size; + int start_pointer, end_pointer; + int i; + while (read_length) { - uint8 get_char; x_base lock; + start_pointer = serial_dev->serial_fifo.serial_rx->serial_recv_num; + end_pointer = serial_dev->serial_fifo.serial_rx->serial_send_num; lock = CriticalAreaLock(); - if (serial_dev->serial_fifo.serial_rx->serial_recv_num == serial_dev->serial_fifo.serial_rx->serial_send_num) { + if (start_pointer == end_pointer) { if (RET_FALSE == serial_dev->serial_fifo.serial_rx->serial_rx_full) { CriticalAreaUnLock(lock); break; } } - - get_char = serial_dev->serial_fifo.serial_rx->serial_rx_buffer[serial_dev->serial_fifo.serial_rx->serial_recv_num]; - serial_dev->serial_fifo.serial_rx->serial_recv_num += 1; - if (serial_dev->serial_fifo.serial_rx->serial_recv_num >= serial_cfg->data_cfg.serial_buffer_size) { - serial_dev->serial_fifo.serial_rx->serial_recv_num = 0; + + /* Read all the chars from the serial_rx_buffer */ + while (start_pointer != end_pointer) + { + read_data[char_num] = serial_dev->serial_fifo.serial_rx->serial_rx_buffer[start_pointer]; + start_pointer += 1; + if (start_pointer >= serial_cfg->data_cfg.serial_buffer_size) { + start_pointer = 0; + } + char_num = char_num + 1; } + read_data[char_num]='\0'; if (RET_TRUE == serial_dev->serial_fifo.serial_rx->serial_rx_full) { serial_dev->serial_fifo.serial_rx->serial_rx_full = RET_FALSE; @@ -153,10 +164,9 @@ static inline int SerialDevIntRead(struct SerialHardwareDevice *serial_dev, stru CriticalAreaUnLock(lock); - *read_data = get_char; - read_data++; read_length--; - read_param->read_length++; + read_param->read_length += char_num; + serial_dev->serial_fifo.serial_rx->serial_recv_num = start_pointer; } return EOK; diff --git a/Ubiquitous/XiUOS/tool/shell/letter-shell/shell.c b/Ubiquitous/XiUOS/tool/shell/letter-shell/shell.c index 2cd6e577b..a0e3f46db 100644 --- a/Ubiquitous/XiUOS/tool/shell/letter-shell/shell.c +++ b/Ubiquitous/XiUOS/tool/shell/letter-shell/shell.c @@ -1645,14 +1645,21 @@ void shellTask(void *param) { // KPrintf("this is in 1733"); Shell *shell = (Shell *)param; - char data; + + /* One input key from the the keyboard/uart may consist of mutliple characters (e.g., arrow keys). */ + char data[KEY_LENGTH]; + int i; + int data_len; + while(RET_TRUE) { - if (shell->read && shell->read(&data) == 0) - { + if (shell->read && shell->read(data) == 0) { // KPrintf("in 1741 the char is: '%c' and ascii code is %d.\n\n",data,data); // KPrintf("the buffer is:'%s'\n\n",shell->parser.); - shellHandler(shell, data); + data_len = strlen(data); + for (i = 0; i < data_len; i++) { + shellHandler(shell, data[i]); + } } } } diff --git a/Ubiquitous/XiUOS/tool/shell/letter-shell/shell.h b/Ubiquitous/XiUOS/tool/shell/letter-shell/shell.h index 61cb78d3f..75084d63c 100644 --- a/Ubiquitous/XiUOS/tool/shell/letter-shell/shell.h +++ b/Ubiquitous/XiUOS/tool/shell/letter-shell/shell.h @@ -256,6 +256,7 @@ typedef struct #define shellSetPath(_shell, _path) (_shell)->info.path = _path #define shellGetPath(_shell) ((_shell)->info.path) +#define KEY_LENGTH 8 void shellInit(Shell *shell, char *buffer, unsigned short size); unsigned short shellWriteString(Shell *shell, const char *string);