kernel: add the boot and interrupt code for cortex-m0

Ubiquitous/XiUOS/arch/arm/cortex-m0/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := boot.c interrupt.c interrupt_vector.S
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiUOS/arch/arm/cortex-m0/arch_interrupt.h

@@ -0,0 +1,28 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+#ifndef ARCH_INTERRUPT_H__
+#define ARCH_INTERRUPT_H__
+
+#include <xs_base.h>
+
+#define ARCH_MAX_IRQ_NUM (48)
+
+#define ARCH_IRQ_NUM_OFFSET 0
+
+#define SYSTICK_IRQN       15
+#define UART1_IRQn         18
+
+int32 ArchEnableHwIrq(uint32 irq_num);
+int32 ArchDisableHwIrq(uint32 irq_num);
+
+#endif

Ubiquitous/XiUOS/arch/arm/cortex-m0/boot.c

@@ -0,0 +1,75 @@
+//*****************************************************************************
+//
+// startup_gcc.c - Startup code for use with GNU tools.
+//
+// Copyright (c) 2013 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 10636 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+/**
+* @file boot.c
+* @brief derived from Stellaris Firmware Development Package
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-05-13
+*/
+
+/*************************************************
+File name: boot.c
+Description: Reset and init function
+Others: 
+History: 
+1. Date: 2021-05-13
+Author: AIIT XUOS Lab
+Modification: 
+1. take startup_gcc.c from revision 10636 of the Stellaris Firmware Development Package   for XiUOS
+*************************************************/
+
+extern unsigned _sdata[], _edata[],
+     _sbss[], _ebss[], _etext[], _sidata[];
+
+extern int entry(void);
+
+void
+Reset_Handler(void)
+{
+     unsigned *p, *q;
+
+     p = _sdata; q = _sidata;
+     while (p < _edata) *p++ = *q++;
+     p = _sbss;
+     while (p < _ebss) *p++ = 0;
+
+    entry();
+}

Ubiquitous/XiUOS/arch/arm/cortex-m0/interrupt.c

@@ -0,0 +1,83 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file interrupt.c
+* @brief support arm cortex-m4 interrupt function
+* @version 1.0
+* @author AIIT XUOS Lab
+* @date 2021-04-29
+*/
+
+#include <xs_base.h>
+#include <xs_isr.h>
+
+
+x_base __attribute__((naked)) DisableLocalInterrupt()
+{
+    asm volatile ("MRS     r0, PRIMASK");
+    asm volatile ("CPSID   I");
+    asm volatile ("BX      LR ");
+}
+
+void __attribute__((naked)) EnableLocalInterrupt(x_base level)
+{
+    asm volatile ("MSR     PRIMASK, r0");
+    asm volatile ("BX      LR");
+}
+
+int32 ArchEnableHwIrq(uint32 irq_num)
+{
+    return EOK;
+}
+
+int32 ArchDisableHwIrq(uint32 irq_num)
+{
+    return EOK;
+}
+
+extern  void KTaskOsAssignAfterIrq(void *context);
+
+void IsrEntry()
+{
+    uint32 ipsr;
+
+    __asm__ volatile("MRS %0, IPSR" : "=r"(ipsr));
+
+    isrManager.done->incCounter();
+    isrManager.done->handleIrq(ipsr);
+    KTaskOsAssignAfterIrq(NONE);
+    isrManager.done->decCounter();
+}
+
+void UsageFault_Handler(int irqn, void *arg)
+{
+    /* Go to infinite loop when Usage Fault exception occurs */
+    while (1)
+    {
+    }
+}
+
+void BusFault_Handler(int irqn, void *arg)
+{
+    /* Go to infinite loop when Bus Fault exception occurs */
+    while (1)
+    {
+    }
+}
+
+void NMI_Handler(int irqn, void *arg)
+{
+    while (1)
+    {
+    }
+}

Ubiquitous/XiUOS/arch/arm/cortex-m0/interrupt_vector.S

@@ -0,0 +1,122 @@
+//*****************************************************************************
+//
+// startup_gcc.c - Startup code for use with GNU tools.
+//
+// Copyright (c) 2013 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 10636 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+/**
+* @file interrupt_vector.S
+* @brief derived from Stellaris Firmware Development Package
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-05-13
+*/
+
+/*************************************************
+File name: interrupt_vector.S
+Description: vector table for a Cortex M3
+Others: 
+History: 
+1. Date: 2021-05-13
+Author: AIIT XUOS Lab
+Modification: 
+1. take startup_gcc.c from revision 10636 of the Stellaris Firmware Development Package   for XiUOS
+*************************************************/
+
+
+//*****************************************************************************
+//
+// The vector table.  Note that the proper constructs must be placed on this to
+// ensure that it ends up at physical address 0x0000.0000.
+//
+//*****************************************************************************
+.globl  InterruptVectors
+
+/******************************************************************************
+*******************************************************************************/
+  .section  .isr_vector,"a",%progbits
+  .type  InterruptVectors, %object
+  .size  InterruptVectors, .-InterruptVectors
+
+InterruptVectors:
+  .word  _sp
+  .word  Reset_Handler
+  .word  NMI_Handler                  // NMI_Handler
+  .word  HardFaultHandler
+  .word  MemFaultHandler              // MemManage_Handler
+  .word  BusFault_Handler             // BusFault_Handler
+  .word  UsageFault_Handler           // UsageFault_Handler
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry                     // SVC_Handler
+  .word  IsrEntry                     // DebugMon_Handler
+  .word  IsrEntry
+  .word  PendSV_Handler               // PendSV_Handler
+  .word  IsrEntry                     // systick 
+
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry                     // UART
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry