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sync the upstream

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This commit is contained in:
Wang_Weigen
2022-05-07 10:47:23 +08:00
parent 0189de57e7 909f3cc635
commit 709fbc5a4b
109 changed files with 5542 additions and 520 deletions
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Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/uart/connect_usart.c
+11
View File
@@ -255,6 +255,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
@@ -269,6 +273,12 @@ static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigu
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
USART_InitTypeDef USART_InitStructure;
USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate;
@@ -584,6 +594,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
/*manage the serial device operations*/
Ubiquitous/XiZi/board/aiit-arm32-board/third_party_driver/watchdog/connect_wdg.c
+1 -1
View File
@@ -11,7 +11,7 @@
*/
/**
* @file connect_wdt.c
* @file connect_wdg.c
* @brief support aiit-arm32-board watchdog function and register to bus framework
* @version 1.0
* @author AIIT XUOS Lab
Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/uart/connect_uart.c
+17
View File
@@ -101,6 +101,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
/* UARTHS ISR */
@@ -144,6 +148,12 @@ static uint32 SerialHsInit(struct SerialDriver *serial_drv, struct BusConfigureI
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
uint32 freq_hs = SysctlClockGetFreq(SYSCTL_CLOCK_CPU);
uint16 div_hs = freq_hs / serial_cfg->data_cfg.serial_baud_rate - 1;
@@ -221,6 +231,12 @@ static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInf
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
UartBitwidthPointer DataWidth = (UartBitwidthPointer)serial_cfg->data_cfg.serial_data_bits;
UartStopbitT stopbit = (UartStopbitT)(serial_cfg->data_cfg.serial_stop_bits - 1);
UartParityT parity = (UartParityT)(serial_cfg->data_cfg.serial_parity_mode - 1);
@@ -390,6 +406,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
/*manage the serial high speed device operations*/
Ubiquitous/XiZi/board/cortex-m0-emulator/connect_uart.c
+11
View File
@@ -71,6 +71,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
static void UartHandler(struct SerialBus *serial_bus, struct SerialDriver *serial_drv)
@@ -112,6 +116,12 @@ static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInf
{
NULL_PARAM_CHECK(serial_drv);
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
return EOK;
}
@@ -173,6 +183,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
/*manage the serial device operations*/
Ubiquitous/XiZi/board/cortex-m3-emulator/connect_uart.c
+11
View File
@@ -73,6 +73,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
static void UartHandler(struct SerialBus *serial_bus, struct SerialDriver *serial_drv)
@@ -113,6 +117,12 @@ static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInf
{
NULL_PARAM_CHECK(serial_drv);
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
return EOK;
}
@@ -195,6 +205,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
/*manage the serial device operations*/
Ubiquitous/XiZi/board/cortex-m4-emulator/third_party_driver/uart/connect_usart.c
+11
View File
@@ -256,6 +256,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
@@ -270,6 +274,12 @@ static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigu
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
USART_InitTypeDef USART_InitStructure;
USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate;
@@ -578,6 +588,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
/*manage the serial device operations*/
Ubiquitous/XiZi/board/gapuino/third_party_driver/uart/connect_uart.c
+11
View File
@@ -58,6 +58,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
static void UartRxIsr(void *arg)
@@ -79,6 +83,12 @@ static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInf
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
struct gap8_udma_peripheral *uart_udma = (struct gap8_udma_peripheral *)serial_cfg->hw_cfg.private_data;
uart_reg_t *uart_reg = (uart_reg_t *)uart_udma->regs;
uint32_t cfg_reg = 0;
@@ -202,6 +212,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
static struct gap8_udma_peripheral gap8_udma =
Ubiquitous/XiZi/board/gd32vf103_rvstar/third_party_driver/uart/connect_uart.c
+15
View File
@@ -58,6 +58,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
static void UartIsr(struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
@@ -99,6 +103,16 @@ static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInf
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
// struct UsartHwCfg *serial_hw_cfg = (struct UsartHwCfg *)serial_cfg->hw_cfg.private_data;
if (configure_info->private_data) {
struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
usart_deinit(serial_cfg->hw_cfg.serial_register_base);
usart_baudrate_set(serial_cfg->hw_cfg.serial_register_base, serial_cfg->data_cfg.serial_baud_rate);
@@ -235,6 +249,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
Ubiquitous/XiZi/board/hifive1-emulator/third_party_driver/connect_usart.c
+11
View File
@@ -59,6 +59,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
static void usart_handler(int vector, void *param)
@@ -78,6 +82,12 @@ static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInf
struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
@@ -148,6 +158,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
/*manage the serial device operations*/
Ubiquitous/XiZi/board/hifive1-rev-B/third_party_driver/connect_usart.c
+11
View File
@@ -59,6 +59,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
static void usart_handler(int vector, void *param)
@@ -78,6 +82,12 @@ static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInf
struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
@@ -148,6 +158,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
/*manage the serial device operations*/
Ubiquitous/XiZi/board/k210-emulator/third_party_driver/uart/connect_uart.c
+11
View File
@@ -103,6 +103,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
/* UARTHS ISR */
@@ -146,6 +150,12 @@ static uint32 SerialHsInit(struct SerialDriver *serial_drv, struct BusConfigureI
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
//uint32 freq_hs = SysctlClockGetFreq(SYSCTL_CLOCK_CPU);
uint32 freq_hs = 26000000;
uint16 div_hs = freq_hs / serial_cfg->data_cfg.serial_baud_rate - 1;
@@ -393,6 +403,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
/*manage the serial high speed device operations*/
Ubiquitous/XiZi/board/kd233/third_party_driver/uart/connect_uart.c
+17
View File
@@ -103,6 +103,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
/* UARTHS ISR */
@@ -146,6 +150,12 @@ static uint32 SerialHsInit(struct SerialDriver *serial_drv, struct BusConfigureI
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
uint32 freq_hs = SysctlClockGetFreq(SYSCTL_CLOCK_CPU);
uint16 div_hs = freq_hs / serial_cfg->data_cfg.serial_baud_rate - 1;
@@ -223,6 +233,12 @@ static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInf
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
UartBitwidthPointer DataWidth = (UartBitwidthPointer)serial_cfg->data_cfg.serial_data_bits;
UartStopbitT stopbit = (UartStopbitT)(serial_cfg->data_cfg.serial_stop_bits - 1);
UartParityT parity = (UartParityT)(serial_cfg->data_cfg.serial_parity_mode - 1);
@@ -392,6 +408,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
/*manage the serial high speed device operations*/
Ubiquitous/XiZi/board/maix-go/third_party_driver/uart/connect_uart.c
+17
View File
@@ -103,6 +103,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
/* UARTHS ISR */
@@ -146,6 +150,12 @@ static uint32 SerialHsInit(struct SerialDriver *serial_drv, struct BusConfigureI
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
uint32 freq_hs = SysctlClockGetFreq(SYSCTL_CLOCK_CPU);
uint16 div_hs = freq_hs / serial_cfg->data_cfg.serial_baud_rate - 1;
@@ -223,6 +233,12 @@ static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInf
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
UartBitwidthPointer DataWidth = (UartBitwidthPointer)serial_cfg->data_cfg.serial_data_bits;
UartStopbitT stopbit = (UartStopbitT)(serial_cfg->data_cfg.serial_stop_bits - 1);
UartParityT parity = (UartParityT)(serial_cfg->data_cfg.serial_parity_mode - 1);
@@ -392,6 +408,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
/*manage the serial high speed device operations*/
Ubiquitous/XiZi/board/nuvoton-m2354/third_party_driver/uart/connect_uart.c
+11
View File
@@ -66,6 +66,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
static void UartHandler(struct SerialBus *serial_bus, struct SerialDriver *serial_drv)
@@ -116,6 +120,12 @@ static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInf
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
switch (serial_cfg->data_cfg.serial_data_bits)
{
case DATA_BITS_5:
@@ -261,6 +271,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
/*manage the serial device operations*/
Ubiquitous/XiZi/board/ok1052-c/third_party_driver/uart/connect_uart.c
+11
View File
@@ -97,6 +97,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
static void UartIsr(struct SerialBus *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
@@ -142,6 +146,12 @@ static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInf
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
lpuart_config_t config;
LPUART_GetDefaultConfig(&config);
config.baudRate_Bps = serial_cfg->data_cfg.serial_baud_rate;
@@ -269,6 +279,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
/*manage the serial device operations*/
Ubiquitous/XiZi/board/rv32m1_vega/third_party_driver/uart/connect_uart.c
+16
View File
@@ -57,6 +57,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
static void UartIsr(struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
@@ -86,6 +90,17 @@ static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInf
NULL_PARAM_CHECK(serial_drv);
struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data;
if (configure_info->private_data) {
struct SerialCfgParam *serial_cfg_new = (struct SerialCfgParam *)configure_info->private_data;
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
LPUART_GetDefaultConfig(&config);
config.baudRate_Bps = serial_cfg->data_cfg.serial_baud_rate;
@@ -218,6 +233,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
Ubiquitous/XiZi/board/stm32f103-nano/third_party_driver/uart/connect_uart.c
+11
View File
@@ -64,6 +64,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
static void UartHandler(struct SerialBus *serial_bus, struct SerialDriver *serial_drv)
@@ -127,6 +131,12 @@ static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInf
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
serial_hw_cfg->uart_handle.Instance = serial_hw_cfg->uart_device;
serial_hw_cfg->uart_handle.Init.BaudRate = serial_cfg->data_cfg.serial_baud_rate;
serial_hw_cfg->uart_handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
@@ -273,6 +283,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
/*manage the serial device operations*/
Ubiquitous/XiZi/board/stm32f407-st-discovery/third_party_driver/uart/connect_usart.c
+11
View File
@@ -256,6 +256,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
@@ -270,6 +274,12 @@ static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigu
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
USART_InitTypeDef USART_InitStructure;
USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate;
@@ -585,6 +595,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
/*manage the serial device operations*/
Ubiquitous/XiZi/board/stm32f407zgt6/third_party_driver/uart/connect_usart.c
+11
View File
@@ -204,6 +204,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
@@ -218,6 +222,12 @@ static uint32 Stm32SerialInit(struct SerialDriver *serial_drv, struct BusConfigu
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
USART_InitTypeDef USART_InitStructure;
USART_InitStructure.USART_BaudRate = serial_cfg->data_cfg.serial_baud_rate;
@@ -390,6 +400,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
/*manage the serial device operations*/
Ubiquitous/XiZi/board/xidatong/board.c
+7
View File
@@ -52,6 +52,10 @@ Modification:
#include <connect_sdio.h>
#endif
#ifdef BSP_USING_WDT
#include <connect_wdt.h>
#endif
#ifdef BSP_USING_SEMC
extern status_t BOARD_InitSEMC(void);
#ifdef BSP_USING_EXTSRAM
@@ -340,5 +344,8 @@ void InitBoardHardware()
#ifdef BSP_USING_LCD
Imxrt1052HwLcdInit();
#endif
#ifdef BSP_USING_WDT
Imxrt1052HwWdgInit();
#endif
}
Ubiquitous/XiZi/board/xidatong/third_party_driver/Kconfig
+8
View File
@@ -54,3 +54,11 @@ menuconfig BSP_USING_USB
if BSP_USING_USB
source "$BSP_DIR/third_party_driver/usb/Kconfig"
endif
menuconfig BSP_USING_WDT
bool "Using WATCHDOG TIMER device"
default n
select RESOURCES_WDT
if BSP_USING_WDT
source "$BSP_DIR/third_party_driver/wdt/Kconfig"
endif
Ubiquitous/XiZi/board/xidatong/third_party_driver/Makefile
+4
View File
@@ -27,4 +27,8 @@ endif
ifeq ($(CONFIG_BSP_USING_LCD),y)
SRC_DIR += lcd
endif
ifeq ($(CONFIG_BSP_USING_WDT),y)
SRC_DIR += wdt
endif
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi/board/xidatong/third_party_driver/ch438/connect_ch438.c
+77 -47
View File
@@ -629,7 +629,7 @@ void WriteCH438Block(uint8 maddr, uint8 mlen, uint8 *mbuf)
** date:
**-------------------------------------------------------------------------------------------------------
********************************************************************************************************/
void Ch438UartSend( uint8 ext_uart_no,uint8 *data, uint8 Num )
void Ch438UartSend(uint8 ext_uart_no, uint8 *data, uint16 Num)
{
uint8 REG_LSR_ADDR,REG_THR_ADDR;
@@ -939,7 +939,12 @@ static uint32 Ch438DrvConfigure(void *drv, struct BusConfigureInfo *configure_in
x_err_t ret = EOK;
struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialCfgParam *ext_serial_cfg = (struct SerialCfgParam *)configure_info->private_data;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
//config serial receive sem timeout
dev_param->serial_timeout = ext_serial_cfg->data_cfg.serial_timeout;
switch (configure_info->configure_cmd)
{
@@ -958,10 +963,35 @@ static uint32 ImxrtCh438WriteData(void *dev, struct BusBlockWriteParam *write_pa
NULL_PARAM_CHECK(dev);
NULL_PARAM_CHECK(write_param);
int write_len, write_len_continue;
int i, write_index;
uint8 *write_buffer;
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
Ch438UartSend(dev_param->ext_uart_no, (uint8 *)write_param->buffer, write_param->size);
write_len = write_param->size;
write_len_continue = write_param->size;
write_buffer = (uint8 *)write_param->buffer;
if (write_len > 256) {
if (0 == write_len % 256) {
write_index = write_len / 256;
for (i = 0; i < write_index; i ++) {
Ch438UartSend(dev_param->ext_uart_no, write_buffer + i * 256, 256);
}
} else {
write_index = 0;
while (write_len_continue > 256) {
Ch438UartSend(dev_param->ext_uart_no, write_buffer + write_index * 256, 256);
write_index++;
write_len_continue = write_len - write_index * 256;
}
Ch438UartSend(dev_param->ext_uart_no, write_buffer + write_index * 256, write_len_continue);
}
} else {
Ch438UartSend(dev_param->ext_uart_no, write_buffer, write_len);
}
return EOK;
}
@@ -974,6 +1004,7 @@ static uint32 ImxrtCh438ReadData(void *dev, struct BusBlockReadParam *read_param
x_err_t result;
uint8 rcv_num = 0;
uint8 gInterruptStatus;
uint8 interrupt_done = 0;
uint8 InterruptStatus;
static uint8 dat;
uint8 REG_LCR_ADDR;
@@ -991,56 +1022,55 @@ static uint32 ImxrtCh438ReadData(void *dev, struct BusBlockReadParam *read_param
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
result = KSemaphoreObtain(ch438_sem, WAITING_FOREVER);
if (EOK == result) {
gInterruptStatus = ReadCH438Data(REG_SSR_ADDR);
if (!gInterruptStatus) {
dat = ReadCH438Data(REG_LCR0_ADDR);
dat = ReadCH438Data(REG_IER0_ADDR);
dat = ReadCH438Data(REG_MCR0_ADDR);
dat = ReadCH438Data(REG_LSR0_ADDR);
dat = ReadCH438Data(REG_MSR0_ADDR);
dat = ReadCH438Data(REG_RBR0_ADDR);
dat = ReadCH438Data(REG_THR0_ADDR);
dat = ReadCH438Data(REG_IIR0_ADDR);
dat = dat ;
} else {
if (gInterruptStatus & interrupt_num[dev_param->ext_uart_no]) { /* check which uart port triggers interrupt*/
REG_LCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IIR0_ADDR;
REG_LSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LSR0_ADDR;
REG_MSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MSR0_ADDR;
InterruptStatus = ReadCH438Data( REG_IIR_ADDR ) & 0x0f; /* read the status of the uart port*/
while (!interrupt_done) {
result = KSemaphoreObtain(ch438_sem, dev_param->serial_timeout);
if (EOK == result) {
gInterruptStatus = ReadCH438Data(REG_SSR_ADDR);
if (!gInterruptStatus) {
// dat = ReadCH438Data(REG_LCR0_ADDR);
// dat = ReadCH438Data(REG_IER0_ADDR);
// dat = ReadCH438Data(REG_MCR0_ADDR);
// dat = ReadCH438Data(REG_LSR0_ADDR);
// dat = ReadCH438Data(REG_MSR0_ADDR);
// dat = ReadCH438Data(REG_RBR0_ADDR);
// dat = ReadCH438Data(REG_THR0_ADDR);
// dat = ReadCH438Data(REG_IIR0_ADDR);
// dat = dat;
interrupt_done = 0;
} else {
if (gInterruptStatus & interrupt_num[dev_param->ext_uart_no]) { /* check which uart port triggers interrupt*/
REG_LCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IIR0_ADDR;
REG_LSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LSR0_ADDR;
REG_MSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MSR0_ADDR;
InterruptStatus = ReadCH438Data( REG_IIR_ADDR ) & 0x0f; /* read the status of the uart port*/
switch( InterruptStatus )
{
case INT_NOINT: /* NO INTERRUPT */
break;
case INT_THR_EMPTY: /* THR EMPTY INTERRUPT*/
break;
case INT_RCV_OVERTIME: /* RECV OVERTIME INTERRUPT*/
case INT_RCV_SUCCESS: /* RECV INTERRUPT SUCCESSFULLY*/
if ((INT_RCV_OVERTIME == InterruptStatus) || (INT_RCV_SUCCESS == InterruptStatus)) {
rcv_num = Ch438UartRcv(dev_param->ext_uart_no, (uint8 *)read_param->buffer, read_param->size);
read_param->read_length = rcv_num;
break;
case INT_RCV_LINES: /* RECV LINES INTERRUPT */
ReadCH438Data( REG_LSR_ADDR );
break;
case INT_MODEM_CHANGE: /* MODEM CHANGE INTERRUPT */
ReadCH438Data( REG_MSR_ADDR );
break;
default:
break;
interrupt_done = 1;
// int i;
// uint8 *buffer = (uint8 *)read_param->buffer;
// for (i = 0; i < rcv_num; i ++) {
// KPrintf("Ch438UartRcv i %u data 0x%x\n", i, buffer[i]);
// }
}
}
}
} else {
//Wait serial sem timeout, break and return 0
rcv_num = 0;
break;
}
}
return rcv_num;
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/connect_wdt.h
+38
View File
@@ -0,0 +1,38 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_wdt.h
* @brief define imxrt1052-board watchdog function and struct
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-05-06
*/
#ifndef CONNECT_WDT_H
#define CONNECT_WDT_H
#include <device.h>
#ifdef __cplusplus
extern "C" {
#endif
int Imxrt1052HwWdgInit(void);
int StartWatchdog(void);
#ifdef __cplusplus
}
#endif
#endif
Ubiquitous/XiZi/board/xidatong/third_party_driver/include/fsl_wdog.h
+312
View File
@@ -0,0 +1,312 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_WDOG_H_
#define _FSL_WDOG_H_
#include "fsl_common.h"
/*!
* @addtogroup wdog
* @{
*/
/*******************************************************************************
* Definitions
*******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief Defines WDOG driver version */
#define FSL_WDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
/*@}*/
/*! @name Refresh sequence */
/*@{*/
#define WDOG_REFRESH_KEY (0xAAAA5555U)
/*@}*/
/*! @brief Defines WDOG work mode. */
typedef struct _wdog_work_mode
{
bool enableWait; /*!< continue or suspend WDOG in wait mode */
bool enableStop; /*!< continue or suspend WDOG in stop mode */
bool enableDebug; /*!< continue or suspend WDOG in debug mode */
} wdog_work_mode_t;
/*! @brief Describes WDOG configuration structure. */
typedef struct _wdog_config
{
bool enableWdog; /*!< Enables or disables WDOG */
wdog_work_mode_t workMode; /*!< Configures WDOG work mode in debug stop and wait mode */
bool enableInterrupt; /*!< Enables or disables WDOG interrupt */
uint16_t timeoutValue; /*!< Timeout value */
uint16_t interruptTimeValue; /*!< Interrupt count timeout value */
bool softwareResetExtension; /*!< software reset extension */
bool enablePowerDown; /*!< power down enable bit */
bool enableTimeOutAssert; /*!< Enable WDOG_B timeout assertion. */
} wdog_config_t;
/*!
* @brief WDOG interrupt configuration structure, default settings all disabled.
*
* This structure contains the settings for all of the WDOG interrupt configurations.
*/
enum _wdog_interrupt_enable
{
kWDOG_InterruptEnable = WDOG_WICR_WIE_MASK /*!< WDOG timeout generates an interrupt before reset*/
};
/*!
* @brief WDOG status flags.
*
* This structure contains the WDOG status flags for use in the WDOG functions.
*/
enum _wdog_status_flags
{
kWDOG_RunningFlag = WDOG_WCR_WDE_MASK, /*!< Running flag, set when WDOG is enabled*/
kWDOG_PowerOnResetFlag = WDOG_WRSR_POR_MASK, /*!< Power On flag, set when reset is the result of a powerOnReset*/
kWDOG_TimeoutResetFlag = WDOG_WRSR_TOUT_MASK, /*!< Timeout flag, set when reset is the result of a timeout*/
kWDOG_SoftwareResetFlag = WDOG_WRSR_SFTW_MASK, /*!< Software flag, set when reset is the result of a software*/
kWDOG_InterruptFlag = WDOG_WICR_WTIS_MASK /*!< interrupt flag,whether interrupt has occurred or not*/
};
/*******************************************************************************
* API
*******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*!
* @name WDOG Initialization and De-initialization.
* @{
*/
/*!
* @brief Initializes the WDOG configuration structure.
*
* This function initializes the WDOG configuration structure to default values. The default
* values are as follows.
* @code
* wdogConfig->enableWdog = true;
* wdogConfig->workMode.enableWait = true;
* wdogConfig->workMode.enableStop = false;
* wdogConfig->workMode.enableDebug = false;
* wdogConfig->enableInterrupt = false;
* wdogConfig->enablePowerdown = false;
* wdogConfig->resetExtension = flase;
* wdogConfig->timeoutValue = 0xFFU;
* wdogConfig->interruptTimeValue = 0x04u;
* @endcode
*
* @param config Pointer to the WDOG configuration structure.
* @see wdog_config_t
*/
void WDOG_GetDefaultConfig(wdog_config_t *config);
/*!
* @brief Initializes the WDOG.
*
* This function initializes the WDOG. When called, the WDOG runs according to the configuration.
*
* This is an example.
* @code
* wdog_config_t config;
* WDOG_GetDefaultConfig(&config);
* config.timeoutValue = 0xffU;
* config->interruptTimeValue = 0x04u;
* WDOG_Init(wdog_base,&config);
* @endcode
*
* @param base WDOG peripheral base address
* @param config The configuration of WDOG
*/
void WDOG_Init(WDOG_Type *base, const wdog_config_t *config);
/*!
* @brief Shuts down the WDOG.
*
* This function shuts down the WDOG.
* Watchdog Enable bit is a write one once only bit. It is not
* possible to clear this bit by a software write, once the bit is set.
* This bit(WDE) can be set/reset only in debug mode(exception).
*/
void WDOG_Deinit(WDOG_Type *base);
/*!
* @brief Enables the WDOG module.
*
* This function writes a value into the WDOG_WCR register to enable the WDOG.
* This is a write one once only bit. It is not possible to clear this bit by a software write,
* once the bit is set. only debug mode exception.
* @param base WDOG peripheral base address
*/
static inline void WDOG_Enable(WDOG_Type *base)
{
base->WCR |= WDOG_WCR_WDE_MASK;
}
static inline void SET_WDOG_WDT(WDOG_Type *base)
{
base->WCR |= WDOG_WCR_WDT_MASK;
}
/*!
* @brief Disables the WDOG module.
*
* This function writes a value into the WDOG_WCR register to disable the WDOG.
* This is a write one once only bit. It is not possible to clear this bit by a software write,once the bit is set.
* only debug mode exception
* @param base WDOG peripheral base address
*/
static inline void WDOG_Disable(WDOG_Type *base)
{
base->WCR &= ~WDOG_WCR_WDE_MASK;
}
/*!
* @brief Trigger the system software reset.
*
* This function will write to the WCR[SRS] bit to trigger a software system reset.
* This bit will automatically resets to "1" after it has been asserted to "0".
* Note: Calling this API will reset the system right now, please using it with more attention.
*
* @param base WDOG peripheral base address
*/
static inline void WDOG_TriggerSystemSoftwareReset(WDOG_Type *base)
{
base->WCR &= ~WDOG_WCR_SRS_MASK;
}
/*!
* @brief Trigger an output assertion.
*
* This function will write to the WCR[WDA] bit to trigger WDOG_B signal assertion.
* The WDOG_B signal can be routed to external pin of the chip, the output pin will turn to
* assertion along with WDOG_B signal.
* Note: The WDOG_B signal will remain assert until a power on reset occurred, so, please
* take more attention while calling it.
*
* @param base WDOG peripheral base address
*/
static inline void WDOG_TriggerSoftwareSignal(WDOG_Type *base)
{
base->WCR &= ~WDOG_WCR_WDA_MASK;
}
/*!
* @brief Enables the WDOG interrupt.
*
*This bit is a write once only bit. Once the software does a write access to this bit, it will get
*locked and cannot be reprogrammed until the next system reset assertion
*
* @param base WDOG peripheral base address
* @param mask The interrupts to enable
* The parameter can be combination of the following source if defined.
* @arg kWDOG_InterruptEnable
*/
static inline void WDOG_EnableInterrupts(WDOG_Type *base, uint16_t mask)
{
base->WICR |= mask;
}
/*!
* @brief Gets the WDOG all reset status flags.
*
* This function gets all reset status flags.
*
* @code
* uint16_t status;
* status = WDOG_GetStatusFlags (wdog_base);
* @endcode
* @param base WDOG peripheral base address
* @return State of the status flag: asserted (true) or not-asserted (false).@see _wdog_status_flags
* - true: a related status flag has been set.
* - false: a related status flag is not set.
*/
uint16_t WDOG_GetStatusFlags(WDOG_Type *base);
/*!
* @brief Clears the WDOG flag.
*
* This function clears the WDOG status flag.
*
* This is an example for clearing the interrupt flag.
* @code
* WDOG_ClearStatusFlags(wdog_base,KWDOG_InterruptFlag);
* @endcode
* @param base WDOG peripheral base address
* @param mask The status flags to clear.
* The parameter could be any combination of the following values.
* kWDOG_TimeoutFlag
*/
void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask);
/*!
* @brief Sets the WDOG timeout value.
*
* This function sets the timeout value.
* This function writes a value into WCR registers.
* The time-out value can be written at any point of time but it is loaded to the counter at the time
* when WDOG is enabled or after the service routine has been performed.
*
* @param base WDOG peripheral base address
* @param timeoutCount WDOG timeout value; count of WDOG clock tick.
*/
static inline void WDOG_SetTimeoutValue(WDOG_Type *base, uint16_t timeoutCount)
{
base->WCR = (base->WCR & ~WDOG_WCR_WT_MASK) | WDOG_WCR_WT(timeoutCount);
}
/*!
* @brief Sets the WDOG interrupt count timeout value.
*
* This function sets the interrupt count timeout value.
* This function writes a value into WIC registers which are wirte-once.
* This field is write once only. Once the software does a write access to this field, it will get locked
* and cannot be reprogrammed until the next system reset assertion.
* @param base WDOG peripheral base address
* @param timeoutCount WDOG timeout value; count of WDOG clock tick.
*/
static inline void WDOG_SetInterrputTimeoutValue(WDOG_Type *base, uint16_t timeoutCount)
{
base->WICR = (base->WICR & ~WDOG_WICR_WICT_MASK) | WDOG_WICR_WICT(timeoutCount);
}
/*!
* @brief Disable the WDOG power down enable bit.
*
* This function disable the WDOG power down enable(PDE).
* This function writes a value into WMCR registers which are wirte-once.
* This field is write once only. Once software sets this bit it cannot be reset until the next system reset.
* @param base WDOG peripheral base address
*/
static inline void WDOG_DisablePowerDownEnable(WDOG_Type *base)
{
base->WMCR &= ~WDOG_WMCR_PDE_MASK;
}
/*!
* @brief Refreshes the WDOG timer.
*
* This function feeds the WDOG.
* This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted.
*
* @param base WDOG peripheral base address
*/
void WDOG_Refresh(WDOG_Type *base);
/*@}*/
#if defined(__cplusplus)
}
#endif /* __cplusplus */
/*! @}*/
#endif /* _FSL_WDOG_H_ */
Ubiquitous/XiZi/board/xidatong/third_party_driver/uart/connect_uart.c
+11
View File
@@ -98,6 +98,10 @@ static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struc
if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
}
if ((data_cfg_default->serial_timeout != data_cfg_new->serial_timeout) && (data_cfg_new->serial_timeout)) {
data_cfg_default->serial_timeout = data_cfg_new->serial_timeout;
}
}
static void UartIsr(struct SerialBus *serial, struct SerialDriver *serial_drv, struct SerialHardwareDevice *serial_dev)
@@ -143,6 +147,12 @@ static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInf
SerialCfgParamCheck(serial_cfg, serial_cfg_new);
}
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_drv->driver.owner_bus->owner_haldev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
// config serial receive sem timeout
dev_param->serial_timeout = serial_cfg->data_cfg.serial_timeout;
lpuart_config_t config;
LPUART_GetDefaultConfig(&config);
config.baudRate_Bps = serial_cfg->data_cfg.serial_baud_rate;
@@ -281,6 +291,7 @@ static const struct SerialDataCfg data_cfg_init =
.serial_bit_order = BIT_ORDER_LSB,
.serial_invert_mode = NRZ_NORMAL,
.serial_buffer_size = SERIAL_RB_BUFSZ,
.serial_timeout = WAITING_FOREVER,
};
/*manage the serial device operations*/
Ubiquitous/XiZi/board/xidatong/third_party_driver/wdt/Kconfig
+13
View File
@@ -0,0 +1,13 @@
if BSP_USING_WDT
config WDT_BUS_NAME
string "watchdog bus name"
default "wdt"
config WDT_DRIVER_NAME
string "watchdog driver name"
default "wdt_drv"
config WDT_DEVICE_NAME
string "watchdog device name"
default "wdt_dev"
endif
Ubiquitous/XiZi/board/xidatong/third_party_driver/wdt/Makefile
+3
View File
@@ -0,0 +1,3 @@
SRC_FILES := connect_wdt.c fsl_wdog.c
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi/board/xidatong/third_party_driver/wdt/connect_wdt.c
+182
View File
@@ -0,0 +1,182 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_wdt.c
* @brief support imxrt1052-board watchdog(WDG1) function and register to bus framework
* @version 2.0
* @author AIIT XUOS Lab
* @date 2022-05-06
*/
#include <connect_wdt.h>
#include <fsl_wdog.h>
static BusType wdt;
static wdog_config_t wdog_config_t_param;
void WDOG1_IRQHandler(void)
{
WDOG_ClearInterruptStatus(WDOG1, kWDOG_InterruptFlag);
/* User code. User can do urgent case before timeout reset.
* IE. user can backup the ram data or ram log to flash.
* the period is set by config.interruptTimeValue, user need to
* check the period between interrupt and timeout.
*/
}
static uint32 Imxrt1052WdgOpen(void *dev)
{
return EOK;
}
static uint32 Imxrt1052WdgClose(void *dev)
{
WDOG_Deinit(WDOG1);
return EOK;
}
static int Imxrt1052WdgInit(struct WdtHardwareDevice *dev, uint16_t timeout)
{
/*
* wdogConfig->enableWdog = true;
* wdogConfig->workMode.enableWait = true;
* wdogConfig->workMode.enableStop = false;
* wdogConfig->workMode.enableDebug = false;
* wdogConfig->enableInterrupt = false;
* wdogConfig->enablePowerdown = false;
* wdogConfig->resetExtension = flase;
* wdogConfig->timeoutValue = 0xFFU;
* wdogConfig->interruptTimeValue = 0x04u;
*/
WDOG_GetDefaultConfig(&wdog_config_t_param);
wdog_config_t_param.timeoutValue = timeout; /* Timeout value is 1 sec / 6.4 num, 5s means 32. */
WDOG_Init(WDOG1, &wdog_config_t_param);
return EOK;
}
static uint32 Imxrt1052WdgConfigure(void *drv, struct BusConfigureInfo *args)
{
struct WdtDriver *wdt_drv = (struct WdtDriver *)drv;
struct WdtHardwareDevice *wdt_dev = (struct WdtHardwareDevice *)wdt_drv->driver.owner_bus->owner_haldev;
uint16_t timeout;
switch(args->configure_cmd)
{
case OPER_WDT_SET_TIMEOUT:
timeout = *(uint16_t *)(args->private_data);
if (timeout) {
Imxrt1052WdgInit(wdt_dev, timeout);
}
break;
case OPER_WDT_KEEPALIVE:
WDOG_Refresh(WDOG1);
break;
default:
return ERROR;
}
return EOK;
}
static const struct WdtDevDone dev_done =
{
Imxrt1052WdgOpen,
Imxrt1052WdgClose,
NONE,
NONE,
};
/**
* @description: Feed watchdog task function
*/
static void FeedWatchdogTask(void)
{
while (1)
{
/* keep watchdog alive in idle task */
struct BusConfigureInfo cfg;
cfg.configure_cmd = OPER_WDT_KEEPALIVE;
cfg.private_data = NONE;
BusDrvConfigure(wdt->owner_driver, &cfg);
MdelayKTask(500);
}
}
/**
* @description: Watchdog function
* @return success: EOK, failure: other
*/
int StartWatchdog(void)
{
int ret = EOK;
uint16_t timeout = 32; /* timeout time 5s*/
wdt = BusFind(WDT_BUS_NAME);
wdt->owner_driver = BusFindDriver(wdt, WDT_DRIVER_NAME);
/* set watchdog timeout time */
struct BusConfigureInfo cfg;
cfg.configure_cmd = OPER_WDT_SET_TIMEOUT;
cfg.private_data = &timeout;
ret = BusDrvConfigure(wdt->owner_driver, &cfg);
int32 WdtTask = KTaskCreate("WdtTask", (void *)FeedWatchdogTask, NONE, 1024, 20);
StartupKTask(WdtTask);
return EOK;
}
int Imxrt1052HwWdgInit(void)
{
x_err_t ret = EOK;
static struct WdtBus watch_dog_timer_bus;
static struct WdtDriver watch_dog_timer_drv;
static struct WdtHardwareDevice watch_dog_timer_dev;
ret = WdtBusInit(&watch_dog_timer_bus, WDT_BUS_NAME);
if (ret != EOK) {
KPrintf("Watchdog bus init error %d\n", ret);
return ERROR;
}
watch_dog_timer_drv.configure = Imxrt1052WdgConfigure;
ret = WdtDriverInit(&watch_dog_timer_drv, WDT_DRIVER_NAME);
if (ret != EOK) {
KPrintf("Watchdog driver init error %d\n", ret);
return ERROR;
}
ret = WdtDriverAttachToBus(WDT_DRIVER_NAME, WDT_BUS_NAME);
if (ret != EOK) {
KPrintf("Watchdog driver attach error %d\n", ret);
return ERROR;
}
watch_dog_timer_dev.dev_done = &dev_done;
ret = WdtDeviceRegister(&watch_dog_timer_dev, WDT_DEVICE_NAME);
if (ret != EOK) {
KPrintf("Watchdog device register error %d\n", ret);
return ERROR;
}
ret = WdtDeviceAttachToBus(WDT_DEVICE_NAME, WDT_BUS_NAME);
if (ret != EOK) {
KPrintf("Watchdog device register error %d\n", ret);
return ERROR;
}
return ret;
}
Ubiquitous/XiZi/board/xidatong/third_party_driver/wdt/fsl_wdog.c
+206
View File
@@ -0,0 +1,206 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_wdog.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.wdog01"
#endif
/*******************************************************************************
* Variables
******************************************************************************/
static WDOG_Type *const s_wdogBases[] = WDOG_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Array of WDOG clock name. */
static const clock_ip_name_t s_wdogClock[] = WDOG_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
static const IRQn_Type s_wdogIRQ[] = WDOG_IRQS;
/*******************************************************************************
* Code
******************************************************************************/
static uint32_t WDOG_GetInstance(WDOG_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_wdogBases); instance++)
{
if (s_wdogBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_wdogBases));
return instance;
}
/*!
* brief Initializes the WDOG configuration structure.
*
* This function initializes the WDOG configuration structure to default values. The default
* values are as follows.
* code
* wdogConfig->enableWdog = true;
* wdogConfig->workMode.enableWait = true;
* wdogConfig->workMode.enableStop = false;
* wdogConfig->workMode.enableDebug = false;
* wdogConfig->enableInterrupt = false;
* wdogConfig->enablePowerdown = false;
* wdogConfig->resetExtension = flase;
* wdogConfig->timeoutValue = 0xFFU;
* wdogConfig->interruptTimeValue = 0x04u;
* endcode
*
* param config Pointer to the WDOG configuration structure.
* see wdog_config_t
*/
void WDOG_GetDefaultConfig(wdog_config_t *config)
{
assert(config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableWdog = true;
config->workMode.enableWait = false;
config->workMode.enableStop = false;
config->workMode.enableDebug = false;
config->enableInterrupt = false;
config->softwareResetExtension = false;
config->enablePowerDown = false;
config->timeoutValue = 0xffu;
config->interruptTimeValue = 0x04u;
config->enableTimeOutAssert = false;
}
/*!
* brief Initializes the WDOG.
*
* This function initializes the WDOG. When called, the WDOG runs according to the configuration.
*
* This is an example.
* code
* wdog_config_t config;
* WDOG_GetDefaultConfig(&config);
* config.timeoutValue = 0xffU;
* config->interruptTimeValue = 0x04u;
* WDOG_Init(wdog_base,&config);
* endcode
*
* param base WDOG peripheral base address
* param config The configuration of WDOG
*/
void WDOG_Init(WDOG_Type *base, const wdog_config_t *config)
{
assert(config);
uint16_t value = 0u;
value = WDOG_WCR_WDE(config->enableWdog) | WDOG_WCR_WDW(config->workMode.enableWait) |
WDOG_WCR_WDZST(config->workMode.enableStop) | WDOG_WCR_WDBG(config->workMode.enableDebug) |
WDOG_WCR_SRE(config->softwareResetExtension) | WDOG_WCR_WT(config->timeoutValue) |
WDOG_WCR_WDT(config->enableTimeOutAssert) | WDOG_WCR_SRS_MASK | WDOG_WCR_WDA_MASK;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Set configuration */
CLOCK_EnableClock(s_wdogClock[WDOG_GetInstance(base)]);
#endif
base->WICR = WDOG_WICR_WICT(config->interruptTimeValue) | WDOG_WICR_WIE(config->enableInterrupt);
base->WMCR = WDOG_WMCR_PDE(config->enablePowerDown);
base->WCR = value;
if (config->enableInterrupt)
{
EnableIRQ(s_wdogIRQ[WDOG_GetInstance(base)]);
}
}
/*!
* brief Shuts down the WDOG.
*
* This function shuts down the WDOG.
* Watchdog Enable bit is a write one once only bit. It is not
* possible to clear this bit by a software write, once the bit is set.
* This bit(WDE) can be set/reset only in debug mode(exception).
*/
void WDOG_Deinit(WDOG_Type *base)
{
if (base->WCR & WDOG_WCR_WDBG_MASK)
{
WDOG_Disable(base);
}
}
/*!
* brief Gets the WDOG all reset status flags.
*
* This function gets all reset status flags.
*
* code
* uint16_t status;
* status = WDOG_GetStatusFlags (wdog_base);
* endcode
* param base WDOG peripheral base address
* return State of the status flag: asserted (true) or not-asserted (false).see _wdog_status_flags
* - true: a related status flag has been set.
* - false: a related status flag is not set.
*/
uint16_t WDOG_GetStatusFlags(WDOG_Type *base)
{
uint16_t status_flag = 0U;
status_flag |= (base->WCR & WDOG_WCR_WDE_MASK);
status_flag |= (base->WRSR & WDOG_WRSR_POR_MASK);
status_flag |= (base->WRSR & WDOG_WRSR_TOUT_MASK);
status_flag |= (base->WRSR & WDOG_WRSR_SFTW_MASK);
status_flag |= (base->WICR & WDOG_WICR_WTIS_MASK);
return status_flag;
}
/*!
* brief Clears the WDOG flag.
*
* This function clears the WDOG status flag.
*
* This is an example for clearing the interrupt flag.
* code
* WDOG_ClearStatusFlags(wdog_base,KWDOG_InterruptFlag);
* endcode
* param base WDOG peripheral base address
* param mask The status flags to clear.
* The parameter could be any combination of the following values.
* kWDOG_TimeoutFlag
*/
void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask)
{
if (mask & kWDOG_InterruptFlag)
{
base->WICR |= WDOG_WICR_WTIS_MASK;
}
}
/*!
* brief Refreshes the WDOG timer.
*
* This function feeds the WDOG.
* This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted.
*
* param base WDOG peripheral base address
*/
void WDOG_Refresh(WDOG_Type *base)
{
base->WSR = WDOG_REFRESH_KEY & 0xFFFFU;
base->WSR = (WDOG_REFRESH_KEY >> 16U) & 0xFFFFU;
}
Ubiquitous/XiZi/kernel/kernel_test/test_iwg.c
+9 -7
View File
@@ -28,14 +28,17 @@ static BusType wdt;
*/
static void FeedWatchdog(void)
{
while (1)
int cnt = 0;
while (cnt < 20)
{
/* keep watchdog alive in idle task */
struct BusConfigureInfo cfg;
cfg.configure_cmd = OPER_WDT_KEEPALIVE;
cfg.private_data = NONE;
BusDrvConfigure(wdt->owner_driver, &cfg);
KPrintf("feed the dog!\n ");
KPrintf("feed the dog! cnt %u\n", cnt);
cnt++;
MdelayKTask(1000);
}
}
@@ -46,18 +49,17 @@ static void FeedWatchdog(void)
int TestIwg(void)
{
x_err_t res = EOK;
uint32 timeout = 1000; /* timeout time */
uint16 timeout = 1000; /* timeout time */
wdt = BusFind(WDT_BUS_NAME_0);
wdt->owner_driver = BusFindDriver(wdt, WDT_DRIVER_NAME_0);
wdt->owner_haldev = BusFindDevice(wdt, WDT_0_DEVICE_NAME_0);
wdt = BusFind(WDT_BUS_NAME);
wdt->owner_driver = BusFindDriver(wdt, WDT_DRIVER_NAME);
wdt->owner_haldev = BusFindDevice(wdt, WDT_DEVICE_NAME);
/* set watchdog timeout time */
struct BusConfigureInfo cfg;
cfg.configure_cmd = OPER_WDT_SET_TIMEOUT;
cfg.private_data = &timeout;
res = BusDrvConfigure(wdt->owner_driver, &cfg);
KPrintf("feed the dog!\n");
int32 WdtTask = KTaskCreate("WdtTask", (void *)FeedWatchdog, NONE, 2048, 20);
res = StartupKTask(WdtTask);
Ubiquitous/XiZi/kernel/thread/console.c
+2 -1
View File
@@ -68,11 +68,12 @@ void InstallConsole(const char *bus_name, const char *drv_name, const char *dev_
BusDevClose(_console);
}
console_bus->match(console_drv, console);
configure_info.configure_cmd = OPE_INT;
memset(&serial_cfg, 0, sizeof(struct SerialCfgParam));
configure_info.private_data = &serial_cfg;
BusDrvConfigure(console_drv, &configure_info);
console_bus->match(console_drv, console);
serial_dev_param = (struct SerialDevParam *)console->private_data;
serial_dev_param->serial_set_mode = 0;
Ubiquitous/XiZi/kernel/thread/init.c
+8
View File
@@ -31,6 +31,10 @@
#include "connect_usb.h"
#endif
#ifdef BSP_USING_WDT
#include "connect_wdt.h"
#endif
#ifdef KERNEL_USER_MAIN
#ifndef MAIN_KTASK_STACK_SIZE
#define MAIN_KTASK_STACK_SIZE 2048
@@ -242,6 +246,10 @@ extern int InitUserspace(void);
HwLockSpinlock(&AssignSpinLock);
#endif
#ifdef BSP_USING_WDT
StartWatchdog();
#endif
StartupOsAssign();
return 0;
Ubiquitous/XiZi/kernel/thread/msgqueue.c
-1
View File
@@ -96,7 +96,6 @@ static x_err_t _MsgQueueSend(struct MsgQueue *mq,
tick_delta = 0;
task = GetKTaskDescriptor();
if(WAITING_FOREVER == msec)
timeout = WAITING_FOREVER;
else
Ubiquitous/XiZi/kernel/thread/semaphore.c
-2
View File
@@ -94,12 +94,10 @@ static int32 _SemaphoreObtain(struct Semaphore *sem, int32 msec)
struct TaskDescriptor *task = NONE;
NULL_PARAM_CHECK(sem);
if(WAITING_FOREVER == msec)
wait_time = WAITING_FOREVER;
else
wait_time = CalculteTickFromTimeMs(msec);
lock = CriticalAreaLock();
SYS_KDEBUG_LOG(KDBG_IPC, ("obtain semaphore: id %d, value %d, by task %s\n",
Ubiquitous/XiZi/resources/bus.c
+1 -1
View File
@@ -52,7 +52,7 @@ static int BusMatchDrvDev(struct Driver *driver, struct HardwareDev *device)
NULL_PARAM_CHECK(device);
if(!strncmp(driver->owner_bus->bus_name, device->owner_bus->bus_name, NAME_NUM_MAX)) {
KPrintf("BusMatchDrvDev match successfully, bus name %s\n", driver->owner_bus->bus_name);
//KPrintf("BusMatchDrvDev match successfully, bus name %s\n", driver->owner_bus->bus_name);
driver->private_data = device->private_data;//driver get the device param
device->owner_bus->owner_driver = driver;
Ubiquitous/XiZi/resources/ethernet/LwIP/arch/lwipopts.h
+22 -1
View File
@@ -204,7 +204,28 @@ The STM32F4x7 allows computing and verifying the IP, UDP, TCP and ICMP checksums
/**
* LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing.
*/
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_RCVBUF 1
/**
* LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and
* SO_SNDTIMEO processing.
*/
#ifndef LWIP_SO_SNDTIMEO
#define LWIP_SO_SNDTIMEO 1
#endif
/**
* LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and
* SO_RCVTIMEO processing.
*/
#ifndef LWIP_SO_RCVTIMEO
#define LWIP_SO_RCVTIMEO 1
#endif
/**
* LWIP_SO_LINGER==1: Enable SO_LINGER processing.
*/
#define LWIP_SO_LINGER 1
/*
---------------------------------
Ubiquitous/XiZi/resources/include/bus.h
+2 -2
View File
@@ -27,11 +27,11 @@
extern "C" {
#endif
#define OPE_INT 0x0000
#define OPE_INT 0x0000
#define OPE_CFG 0x0001
#define OPER_WDT_SET_TIMEOUT 0x0002
#define OPER_WDT_KEEPALIVE 0x0003
#define OPER_WDT_KEEPALIVE 0x0003
typedef struct Bus *BusType;
typedef struct HardwareDev *HardwareDevType;
Ubiquitous/XiZi/resources/include/bus_serial.h
+1
View File
@@ -44,6 +44,7 @@ struct SerialDataCfg
uint8 serial_bit_order;
uint8 serial_invert_mode;
uint16 serial_buffer_size;
int32 serial_timeout;
uint8 ext_uart_no;
enum ExtSerialPortConfigure port_configure;
Ubiquitous/XiZi/resources/include/dev_serial.h
+2
View File
@@ -107,6 +107,8 @@ struct SerialDevParam
uint16 serial_work_mode;
uint16 serial_set_mode;
uint16 serial_stream_mode;
int32 serial_timeout;
};
struct SerialHardwareDevice;
Ubiquitous/XiZi/resources/serial/dev_serial.c
+3 -1
View File
@@ -630,7 +630,7 @@ static uint32 SerialDevRead(void *dev, struct BusBlockReadParam *read_param)
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev;
struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
if (EOK == KSemaphoreObtain(serial_dev->haldev.dev_sem, WAITING_FOREVER)) {
if (EOK == KSemaphoreObtain(serial_dev->haldev.dev_sem, serial_dev_param->serial_timeout)) {
if (serial_dev_param->serial_work_mode & SIGN_OPER_INT_RX) {
ret = SerialDevIntRead(serial_dev, read_param);
if (EOK != ret) {
@@ -654,6 +654,8 @@ static uint32 SerialDevRead(void *dev, struct BusBlockReadParam *read_param)
return ERROR;
}
}
} else {
return ERROR;
}
return EOK;
}