From 6fe9a4f5a89e3790e94d32223abd56f19f51f6f1 Mon Sep 17 00:00:00 2001 From: Gujinyu Date: Mon, 30 Aug 2021 21:03:02 +0800 Subject: [PATCH] kernel: add the board director for cortex-m0-emulator (qemu emulates microbit which uses nRF51) --- .../XiUOS/board/cortex-m0-emulator/.defconfig | 248 +++ .../XiUOS/board/cortex-m0-emulator/Kconfig | 56 + .../XiUOS/board/cortex-m0-emulator/Makefile | 5 + .../XiUOS/board/cortex-m0-emulator/README.md | 187 ++ .../XiUOS/board/cortex-m0-emulator/board.c | 39 + .../XiUOS/board/cortex-m0-emulator/board.h | 38 + .../XiUOS/board/cortex-m0-emulator/config.mk | 14 + .../board/cortex-m0-emulator/connect_uart.c | 331 ++++ .../XiUOS/board/cortex-m0-emulator/link.lds | 73 + .../third_party_driver/Kconfig | 0 .../third_party_driver/Libraries/Makefile | 3 + .../Libraries/driverlib/Makefile | 3 + .../Libraries/driverlib/gpio.h | 13 + .../Libraries/driverlib/opt.h | 23 + .../Libraries/driverlib/uart.c | 153 ++ .../Libraries/driverlib/uart.h | 70 + .../Libraries/inc/hw_memmap.h | 44 + .../Libraries/inc/hw_nvic.h | 1717 +++++++++++++++++ .../Libraries/inc/hw_types.h | 212 ++ .../third_party_driver/Makefile | 3 + 20 files changed, 3232 insertions(+) create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/.defconfig create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/Kconfig create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/Makefile create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/README.md create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/board.c create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/board.h create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/config.mk create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/connect_uart.c create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/link.lds create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Kconfig create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/Makefile create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/Makefile create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/gpio.h create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/opt.h create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/uart.c create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/uart.h create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_memmap.h create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_nvic.h create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_types.h create mode 100644 Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Makefile diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/.defconfig b/Ubiquitous/XiUOS/board/cortex-m0-emulator/.defconfig new file mode 100644 index 000000000..edf437357 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/.defconfig @@ -0,0 +1,248 @@ +# +# Automatically generated file; DO NOT EDIT. +# XiUOS Project Configuration +# +CONFIG_BOARD_CORTEX_M3_EVB=y +CONFIG_KERNEL_CONSOLE_DEVICE_NAME="uart0" +#CONFIG_LED0=24 +#CONFIG_LED1=25 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y +CONFIG_ARCH_CPU_32BIT=y + +# +# cortex-m3-emulator feature +# +# CONFIG_BSP_USING_AUDIO is not set +# CONFIG_BSP_USING_CAMERA is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_DMA is not set +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_I2S is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SECURITY is not set +# CONFIG_BSP_USING_SPI is not set +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART_HS is not set +# CONFIG_BSP_USING_VIDEO is not set +# CONFIG_BSP_USING_WDT is not set + +# +# General Purpose UARTs +# + +CONFIG___STACKSIZE__=4096 + +# +# Hardware feature +# +CONFIG_RESOURCES_SERIAL=y +# CONFIG_SERIAL_USING_DMA=y +CONFIG_SERIAL_RB_BUFSZ=64 +CONFIG_FS_VFS=n +# CONFIG_RESOURCES_HWTIMER is not set +# CONFIG_RESOURCES_I2C is not set +# CONFIG_RESOURCES_LCD is not set +# CONFIG_RESOURCES_SDIO is not set +# CONFIG_RESOURCES_TOUCH is not set +# CONFIG_RESOURCES_PIN=y +# CONFIG_RESOURCES_RTC is not set +# CONFIG_RESOURCES_SPI is not set +#CONFIG_RESOURCES_SPI_SD is not set +#CONFIG_RESOURCES_SPI_SFUD is not set +# SFUD_USING_SFDP is not set +# SFUD_USING_FLASH_INFO_TABLE is not set +# SFUD_DEBUG_LOG is not set +# CONFIG_RESOURCES_WDT is not set +# CONFIG_RESOURCES_USB is not set +# CONFIG_RESOURCES_USB_HOST is not set +# CONFIG_UDISK_MOUNTPOINT is not set +# CONFIG_USBH_MSTORAGE is not set +# CONFIG_RESOURCES_USB_DEVICE is not set +# CONFIG_USBD_THREAD_STACK_SZ is not set + +# +# Kernel feature +# + +# +# Kernel Device Object +# +CONFIG_KERNEL_DEVICE=y +CONFIG_KERNEL_CONSOLE=y +CONFIG_KERNEL_CONSOLEBUF_SIZE=128 + +# +# Task feature +# +CONFIG_SCHED_POLICY_RR_REMAINSLICE=y +# CONFIG_SCHED_POLICY_RR is not set +# CONFIG_SCHED_POLICY_FIFO is not set + +# +# Memory Management +# +# CONFIG_KERNEL_MEMBLOCK is not set +CONFIG_MEM_ALIGN_SIZE=4 +CONFIG_MM_PAGE_SIZE=1024 + +# +# Using small memory allocator +# +CONFIG_KERNEL_SMALL_MEM_ALLOC=y +CONFIG_SMALL_NUMBER_32B=32 +CONFIG_SMALL_NUMBER_64B=16 + +# +# Inter-Task communication +# +# CONFIG_KERNEL_SEMAPHORE=y +# CONFIG_KERNEL_MUTEX=y +CONFIG_KERNEL_EVENT=n +CONFIG_KERNEL_MESSAGEQUEUE=n +CONFIG_KTASK_PRIORITY_8=y +CONFIG_KTASK_PRIORITY_MAX=8 +CONFIG_TICK_PER_SECOND=100 +# CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y +CONFIG_KERNEL_BANNER=y +# CONFIG_KERNEL_HOOK is not set +# CONFIG_KERNEL_SOFTTIMER=y +# CONFIG_KERNEL_IDLE_HOOK=y +# CONFIG_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_KTASK_STACKSIZE=512 +CONFIG_ZOMBIE_KTASK_STACKSIZE=512 +# CONFIG_KERNEL_TASK_ISOLATION is not set + +# +# Memory Management +# +# CONFIG_KERNEL_MEMBLOCK is not set + +# +# Command shell +# +CONFIG_TOOL_SHELL=y +CONFIG_SHELL_TASK_PRIORITY=4 +CONFIG_SHELL_TASK_STACK_SIZE=2048 + +# +# User Control +# +CONFIG_SHELL_DEFAULT_USER="letter" +CONFIG_SHELL_DEFAULT_USER_PASSWORD="" +CONFIG_SHELL_LOCK_TIMEOUT=10000 +CONFIG_SHELL_ENTER_CR_AND_LF=y +# CONFIG_SHELL_ENTER_CRLF is not set +CONFIG_SHELL_ENTER_CR=y +CONFIG_SHELL_ENTER_LF=y +CONFIG_SHELL_MAX_NUMBER=5 +CONFIG_SHELL_PARAMETER_MAX_NUMBER=8 +CONFIG_SHELL_HISTORY_MAX_NUMBER=5 +CONFIG_SHELL_PRINT_BUFFER=128 +CONFIG_SHELL_USING_CMD_EXPORT=y +# CONFIG_SHELL_HELP_LIST_USER is not set +CONFIG_SHELL_HELP_SHOW_PERMISSION=y +# CONFIG_SHELL_HELP_LIST_VAR is not set +# CONFIG_SHELL_HELP_LIST_KEY is not set +#CONFIG_KERNEL_QUEUEMANAGE=y +# CONFIG_KERNEL_WORKQUEUE is not set +CONFIG_WORKQUEUE_KTASK_STACKSIZE=256 +CONFIG_WORKQUEUE_KTASK_PRIORITY=2 +CONFIG_QUEUE_MAX=2 +CONFIG_KERNEL_WAITQUEUE=y +CONFIG_KERNEL_DATAQUEUE=y +# CONFIG_KERNEL_CIRCULAR_AREA is not set +# CONFIG_KERNEL_AVL_TREE is not set +CONFIG_NAME_MAX=32 +CONFIG_ALIGN_SIZE=8 +CONFIG_KERNEL_COMPONENTS_INIT=n +CONFIG_KERNEL_USER_MAIN=y +CONFIG_MAIN_KTASK_STACK_SIZE=2048 +CONFIG_ENV_INIT_KTASK_STACK_SIZE=2048 +CONFIG_MAIN_KTASK_PRIORITY=3 +# CONFIG_USER_TEST is not set +# CONFIG_TOOL_TEST_SEM is not set +# CONFIG_TOOL_TEST_MUTEX is not set +# CONFIG_TOOL_TEST_EVENT is not set +# CONFIG_TOOL_TEST_MSG is not set +# CONFIG_TOOL_TEST_AVLTREE is not set +# CONFIG_TEST_CRICULAR_AREA is not set +# CONFIG_TOOL_TEST_MEM is not set +# CONFIG_TOOL_TEST_TIMER is not set +# CONFIG_TOOL_TEST_IWG is not set +# CONFIG_TOOL_TEST_REALTIME is not set +# CONFIG_TOOL_TEST_DBG is not set +# CONFIG_TOOL_TEST_SCHED is not set +# CONFIG_KERNEL_DEBUG is not set +#CONFIG_DEBUG_INIT_CONFIG=y +#CONFIG_DBG_INIT=1 +#CONFIG_ARCH_SMP=y +#CONFIG_CPUS_NR=2 + +# +# hash table config +# +CONFIG_ID_HTABLE_SIZE=4 +CONFIG_ID_NUM_MAX=16 + +# +# File system +# +CONFIG_FS_DFS=n +#CONFIG_DFS_USING_WORKDIR=y +#CONFIG_FS_DFS_DEVFS=y + +# +# Fat filesystem +# + +# +# IOT-Device File system +# + +# +# Lwext4 filesystem +# + +# +# APP Framework +# + +# +# Perception +# +# CONFIG_PERCEPTION_SENSORDEVICE is not set + +# +# connection +# +# CONFIG_CONNECTION_AT is not set +# CONFIG_CONNECTION_MQTT is not set + +# +# medium communication +# + + +# +# Intelligence +# + +# +# Control +# + +# +# Lib +# +CONFIG_LIB=y +CONFIG_LIB_POSIX=y +CONFIG_LIB_NEWLIB=y + +# CONFIG_LITTLEVGL2RTT_USING_DEMO=y + +# +# Security +# diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/Kconfig b/Ubiquitous/XiUOS/board/cortex-m0-emulator/Kconfig new file mode 100644 index 000000000..14fad1f2a --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/Kconfig @@ -0,0 +1,56 @@ +mainmenu "XiUOS Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config KERNEL_DIR + string + option env="KERNEL_ROOT" + default "../.." + +config BOARD_CORTEX_M0_EVB + bool + select ARCH_ARM + default y + +config KERNEL_CONSOLE_DEVICE_NAME + string + default "uart0" + + +source "$KERNEL_DIR/arch/Kconfig" + +menu "cortex-m0 emulator feature" + source "$BSP_DIR/third_party_driver/Kconfig" + + menu "config default board resources" + menu "config board app name" + config BOARD_APP_NAME + string "config board app name" + default "/XiUOS_cortex-m0-emulator_app.bin" + endmenu + + menu "config board service table" + config SERVICE_TABLE_ADDRESS + hex "board service table address" + default 0x2007F0000 + endmenu + + endmenu + + config __STACKSIZE__ + int "stack size for interrupt" + default 4096 + +endmenu + + +menu "Hardware feature" +source "$KERNEL_DIR/resources/Kconfig" +endmenu + +source "$KERNEL_DIR/Kconfig" + + diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/Makefile b/Ubiquitous/XiUOS/board/cortex-m0-emulator/Makefile new file mode 100644 index 000000000..36f2e0089 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/Makefile @@ -0,0 +1,5 @@ +SRC_DIR := third_party_driver + +SRC_FILES := board.c connect_uart.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/README.md b/Ubiquitous/XiUOS/board/cortex-m0-emulator/README.md new file mode 100644 index 000000000..25d61cc64 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/README.md @@ -0,0 +1,187 @@ +# 从零开始构建矽璓工业物联操作系统：使用ARM架构的cortex-m0 emulator + +# cortex-m0 emulator + +[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓XiUOS是一款面向智慧车间的工业物联网操作系统，主要由一个极简的微型实时操作系统内核和其上的工业物联框架构成，通过高效管理工业物联网设备、支撑工业物联应用，在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”，促进以工业设备和工业控制系统为核心的人、机、物深度互联，帮助提升生产线的数字化和智能化水平。 + +## 1. 简介 + +Q‎EMU 是一个通用的开源模拟器和虚拟化工具。目前Q‎EMU已经可以较完整的支持ARM cortex-m3架构。XiUOS同样支持运行在Q‎EMU上 + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| lm3s6965evb | +|架构| cortex-m0 | +|主频| 50MHz | +|片内SRAM| 64KB | +| 外设支持 | UART | + +XiUOS板级当前支持使用UART。 + +## 2. 开发环境搭建 + +### 推荐使用： + +**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop) + +更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改） + +第一步:打开sources.list文件 + +```c +sudo vim /etc/apt/sources.list +``` + +第二步:将以下内容复制到sources.list文件 + +```c +deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse +deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse +``` + +第三步:更新源和系统软件 + +```c +sudo apt-get update +sudo apt-get upgrade +``` + +**开发工具推荐使用 VSCode ，VScode下载地址为：** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb) + +### 依赖包安装： + +``` +$ sudo apt install build-essential pkg-config git +$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev +``` + +**XiUOS操作系统源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos) + +新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下： + +```c +mkdir test && cd test +git clone https://git.trustie.net/xuos/xiuos.git +``` + +打开源码文件包可以看到以下目录： +| 名称 | 说明 | +| -- | -- | +| application | 应用代码 | +| board | 板级支持包 | +| framework | 应用框架 | +| fs | 文件系统 | +| kernel | 内核源码 | +| resources | 驱动文件 | +| tool | 系统工具 | + +使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示： + +
+ +
+ +### 裁减配置工具的下载 + +裁减配置工具： + +**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)，下载与安装的具体命令如下： + +```c +mkdir kfrontends && cd kfrontends +git clone https://git.trustie.net/xuos/kconfig-frontends.git +``` + +下载源码后按以下步骤执行软件安装： + +```c +cd kconfig-frontends + ./xs_build.sh +``` + +### 编译工具链： + +ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。 + +```shell +$ sudo apt install gcc-arm-none-eabi +``` + +## 编译说明 + +### 编辑环境：`Ubuntu18.04` + +### 编译工具链：`arm-none-eabi-gcc` +使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目 + + +编译步骤： + +1.在VScode命令终端中执行以下命令，生成配置文件 + +```c + make BOARD=cortex-m3-emulator menuconfig +``` + +2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置） + +![menuconfig](img/menuconfig.png) + +退出时选择`yes`保存上面所配置的内容，如下图所示： + +![menuconfig1](img/menuconfig1.png) + +3.继续执行以下命令，进行编译 + +``` +make BOARD=cortex-m3-emulator +``` + +4.如果编译正确无误，会产生XiUOS_cortex-m0-emulator.elf、XiUOS_cortex-m0-emulator.bin文件。 + +## 3. 运行 + +### 3.1 安装Q‎EMU + +``` +sudo apt install qemu-system-arm +``` + +### 3.2 运行结果 + +通过以下命令启动Q‎EMU并加载XiUOS ELF文件 + +``` +qemu-system-arm -machine lm3s6965evb -nographic -kernel build/XiUOS_cortex-m3-emulator.elf +``` + +QEMU运行起来后将会在终端上看到信息打印输出 + +![terminal](img/terminal.png) + +### 3.3 调试 + +通过Q‎EMU可以方便的对XiUOS进行调试，首先安装gdb调试工具 +``` +sudo apt install gdb-multiarch +``` + +并通过以下命令启动Q‎EMU + +``` +qemu-system-arm -machine lm3s6965evb -nographic -kernel build/XiUOS_cortex-m3-emulator.elf -s -S +``` + +然后要重新开启另一个linux系统终端一个终端，执行`riscv-none-embed-gdb`命令 + +``` +gdb-multiarch build/XiUOS_cortex-m3-emulator.elf -ex "target remote localhost:1234" +``` diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/board.c b/Ubiquitous/XiUOS/board/cortex-m0-emulator/board.c new file mode 100644 index 000000000..ec04ac244 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/board.c @@ -0,0 +1,39 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.c +* @brief support cortex-m3-emulator init configure and start-up +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-13 +*/ + + +#include +#include +#include +#include + +void SysTick_Handler(int irqn, void *arg) +{ + TickAndTaskTimesliceUpdate(); +} +DECLARE_HW_IRQ(SYSTICK_IRQN, SysTick_Handler, NONE); + +void InitBoardHardware() +{ + extern int InitHwUart(void); + InitHwUart(); + InstallConsole(SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1, SERIAL_DEVICE_NAME_1); + InitBoardMemory((void*)LM3S_SRAM_START, (void*)LM3S_SRAM_END); +} diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/board.h b/Ubiquitous/XiUOS/board/cortex-m0-emulator/board.h new file mode 100644 index 000000000..d07377c8b --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/board.h @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file board.h +* @brief define cortex-m3-emulator init configure and start-up function +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-13 +*/ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + + +extern void *__bss_end; +extern void *_heap_end; +#define MEM_OFFSET 0x20001000 +#define LM3S_SRAM_START ( ( ((unsigned long)(&__bss_end)) > MEM_OFFSET)? (unsigned long)(&__bss_end):(MEM_OFFSET) ) +#define LM3S_SRAM_END ( &_heap_end ) + +#define BSP_USING_UART1 +#define SERIAL_BUS_NAME_1 "uart0" +#define SERIAL_DRV_NAME_1 "uart0_drv" +#define SERIAL_DEVICE_NAME_1 "uart0_dev0" + + + +#endif diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/config.mk b/Ubiquitous/XiUOS/board/cortex-m0-emulator/config.mk new file mode 100644 index 000000000..1ac914974 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/config.mk @@ -0,0 +1,14 @@ +export CROSS_COMPILE ?=/usr/bin/arm-none-eabi- + +export CFLAGS := -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb +export AFLAGS := -c -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2 +export LFLAGS := -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_cortex-m0-emulator.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds +export CXXFLAGS := -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g + +export APPLFLAGS := -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds + + +export DEFINES := -DHAVE_CCONFIG_H -g + +export ARCH = arm +export MCU = cortex-m0 diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/connect_uart.c b/Ubiquitous/XiUOS/board/cortex-m0-emulator/connect_uart.c new file mode 100644 index 000000000..bc3e068f1 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/connect_uart.c @@ -0,0 +1,331 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_uart.c +* @brief support cortex_m3_emulator board uart function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-05-10 +*/ + +#include +#include +#include +#include +#include +#include +#include + +#define NO_IMPL() KPrintf("%s is not implemented!\n", __func__) + +#ifdef BSP_USING_UART1 +static struct SerialBus serial_bus_1; +static struct SerialDriver serial_driver_1; +static struct SerialHardwareDevice serial_device_1; +#endif +#ifdef BSP_USING_UART2 +static struct SerialBus serial_bus_2; +static struct SerialDriver serial_driver_2; +static struct SerialHardwareDevice serial_device_2; +#endif + +static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new) +{ + struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg; + struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg; + + if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) { + data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate; + } + + if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) { + data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order; + } + + if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) { + data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size; + } + + if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) { + data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits; + } + + if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) { + data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode; + } + + if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) { + data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode; + } + + if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) { + data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits; + } +} + +static void UartHandler(struct SerialBus *serial_bus, struct SerialDriver *serial_drv) +{ + struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_bus->bus.owner_haldev; + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; + + uint32 status; + + status = UARTIntStatus(serial_cfg->hw_cfg.serial_register_base, RET_TRUE); + + /* clear interrupt status */ + UARTIntClear(serial_cfg->hw_cfg.serial_register_base, status); + + while (UARTCharsAvail(serial_cfg->hw_cfg.serial_register_base)) { + SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND); + } + +} + +#ifdef BSP_USING_UART1 +void UartIsr1(int vector, void *param) +{ + /* get serial bus 1 */ + UartHandler(&serial_bus_1, &serial_driver_1); +} +DECLARE_HW_IRQ(UART1_IRQn, UartIsr1, NONE); +#endif + +#ifdef BSP_USING_UART2 +void UartIsr2(int irqno) +{ + /* get serial bus 2 */ + UartHandler(&serial_bus_2, &serial_driver_2); +} +#endif + +static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(serial_drv); + + return EOK; +} + +static uint32 SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd) +{ + NO_IMPL(); + return 0; +} + +static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info) +{ + NULL_PARAM_CHECK(drv); + NULL_PARAM_CHECK(configure_info); + + x_err_t ret = EOK; + int serial_operation_cmd; + struct SerialDriver *serial_drv = (struct SerialDriver *)drv; + + switch (configure_info->configure_cmd) + { + case OPE_INT: + ret = SerialInit(serial_drv, configure_info); + break; + case OPE_CFG: + serial_operation_cmd = *(int *)configure_info->private_data; + ret = SerialConfigure(serial_drv, serial_operation_cmd); + break; + default: + break; + } + + return ret; +} + +static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + while (UARTCharPutNonBlocking(serial_cfg->hw_cfg.serial_register_base, c) == RET_FALSE); + + return 0; +} + +static int SerialGetChar(struct SerialHardwareDevice *serial_dev) +{ + struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; + long val = UARTCharGetNonBlocking(serial_cfg->hw_cfg.serial_register_base); + if (val > 0) + return (int)val; + else + return -1; +} + +static const struct SerialDataCfg data_cfg_init = +{ + .serial_baud_rate = BAUD_RATE_115200, + .serial_data_bits = DATA_BITS_8, + .serial_stop_bits = STOP_BITS_1, + .serial_parity_mode = PARITY_NONE, + .serial_bit_order = BIT_ORDER_LSB, + .serial_invert_mode = NRZ_NORMAL, + .serial_buffer_size = SERIAL_RB_BUFSZ, +}; + +/*manage the serial device operations*/ +static const struct SerialDrvDone drv_done = +{ + .init = SerialInit, + .configure = SerialConfigure, +}; + +/*manage the serial device hal operations*/ +static struct SerialHwDevDone hwdev_done = +{ + .put_char = SerialPutChar, + .get_char = SerialGetChar, +}; + +static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name) +{ + + x_err_t ret = EOK; + + /*Init the serial bus */ + + ret = SerialBusInit(serial_bus, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialBusInit error %d\n", ret); + return ERROR; + } + + /*Init the serial driver*/ + ret = SerialDriverInit(serial_driver, drv_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDriverInit error %d\n", ret); + return ERROR; + } + + /*Attach the serial driver to the serial bus*/ + ret = SerialDriverAttachToBus(drv_name, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDriverAttachToBus error %d\n", ret); + return ERROR; + } + + return ret; +} + +/*Attach the serial device to the serial bus*/ +static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name) +{ + x_err_t ret = EOK; + + ret = SerialDeviceRegister(serial_device, serial_param, dev_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDeviceInit device %s error %d\n", dev_name, ret); + return ERROR; + } + + ret = SerialDeviceAttachToBus(dev_name, bus_name); + if (EOK != ret) { + KPrintf("InitHwUart SerialDeviceAttachToBus device %s error %d\n", dev_name, ret); + return ERROR; + } + + return ret; +} + +int InitHwUart(void) +{ + x_err_t ret = EOK; + + UARTlInitialize(); +#ifdef BSP_USING_UART1 + memset(&serial_bus_1, 0, sizeof(struct SerialBus)); + memset(&serial_driver_1, 0, sizeof(struct SerialDriver)); + memset(&serial_device_1, 0, sizeof(struct SerialHardwareDevice)); + + static struct SerialCfgParam serial_cfg_1; + memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam)); + + static struct SerialDevParam serial_dev_param_1; + memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam)); + + serial_driver_1.drv_done = &drv_done; + serial_driver_1.configure = &SerialDrvConfigure; + serial_device_1.hwdev_done = &hwdev_done; + + serial_cfg_1.data_cfg = data_cfg_init; + + serial_cfg_1.hw_cfg.serial_register_base = UART0_BASE; + serial_driver_1.private_data = (void *)&serial_cfg_1; + + serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX; + serial_device_1.haldev.private_data = (void *)&serial_dev_param_1; + + /* enable UART0 clock */ + // SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + // SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + + /* set UART0 pinmux */ + // GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); + + /* Configure the UART for 115,200, 8-N-1 operation. */ + // UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), serial_cfg_1.data_cfg.serial_baud_rate, + // (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | + // UART_CONFIG_PAR_NONE)); + + ret = BoardSerialBusInit(&serial_bus_1, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_DEVICE_NAME_1); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } +#endif + +#ifdef BSP_USING_UART2 + memset(&serial_bus_2, 0, sizeof(struct SerialBus)); + memset(&serial_driver_2, 0, sizeof(struct SerialDriver)); + memset(&serial_device_2, 0, sizeof(struct SerialHardwareDevice)); + + static struct SerialCfgParam serial_cfg_2; + memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam)); + + static struct SerialDevParam serial_dev_param_2; + memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam)); + + serial_driver_2.drv_done = &drv_done; + serial_driver_2.configure = &SerialDrvConfigure; + serial_device_2.hwdev_done = &hwdev_done; + + serial_cfg_2.data_cfg = data_cfg_init; + + serial_cfg_2.hw_cfg.serial_register_base = UART1_BASE; + serial_driver_2.private_data = (void *)&serial_cfg_2; + + serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX | SIGN_OPER_POLL_RX; + serial_device_2.haldev.private_data = (void *)&serial_dev_param_2; + + ret = BoardSerialBusInit(&serial_bus_2, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } + + ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_DEVICE_NAME_2); + if (EOK != ret) { + KPrintf("InitHwUart uarths error ret %u\n", ret); + return ERROR; + } +#endif + return ret; +} diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/link.lds b/Ubiquitous/XiUOS/board/cortex-m0-emulator/link.lds new file mode 100644 index 000000000..27ce795bf --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/link.lds @@ -0,0 +1,73 @@ +/* NRF51822.ld -- Copyright (c) 2018 J. M. Spivey */ + +MEMORY { + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 +} + +OUTPUT_FORMAT ("elf32-littlearm") +__SYSTEM_STACKSIZE__ = 0x400; + +ENTRY(Reset_Handler) +SECTIONS { + .text : { + . = ALIGN(4); + KEEP(*(.isr_vector)) + . = ALIGN(4); + *(.text*) + *(.rodata*) + + _shell_command_start = .; + KEEP (*(shellCommand)) + _shell_command_end = .; + . = ALIGN(4); + + __isrtbl_idx_start = .; + KEEP(*(.isrtbl.idx)) + __isrtbl_start = .; + KEEP(*(.isrtbl)) + __isrtbl_end = .; + . = ALIGN(4); + + PROVIDE(g_service_table_start = ABSOLUTE(.)); + KEEP(*(.g_service_table)) + PROVIDE(g_service_table_end = ABSOLUTE(.)); + + PROVIDE(_etext = ABSOLUTE(.)); + _etext = .; + } > FLASH = 0 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + _sidata = .; + } > FLASH + __exidx_end = .; + + .data : AT (_sidata) { + . = ALIGN(4); + _sdata = .; + *(.data*) + . = ALIGN(4); + _edata = .; + } > RAM + + .bss : { + . = ALIGN(4); + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } > RAM + __bss_end = .; + __end = .; + + .stack ORIGIN(RAM) + LENGTH(RAM) - __SYSTEM_STACKSIZE__ : + { + PROVIDE( _heap_end = . ); + . = __SYSTEM_STACKSIZE__; + PROVIDE( _sp = . ); + } >RAM +} diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Kconfig b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Kconfig new file mode 100644 index 000000000..e69de29bb diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/Makefile b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/Makefile new file mode 100644 index 000000000..78b02eb44 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/Makefile @@ -0,0 +1,3 @@ +SRC_DIR := driverlib + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/Makefile b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/Makefile new file mode 100644 index 000000000..b456f10ac --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := uart.c +# SRC_FILES := uart.c +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/gpio.h b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/gpio.h new file mode 100644 index 000000000..3631cd73f --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/gpio.h @@ -0,0 +1,13 @@ +#pragma once +/* GPIO */ +#define GPIO_DIRSET ADDR(0x50000518) +#define GPIO_DIRCLR ADDR(0x5000051c) +#define GPIO_PINCNF ARRAY(0x50000700) + +#define GPIO_PINCNF_PULL_Pos 2 +#define GPIO_PINCNF_PULL_Wid 2 +#define GPIO_Pullup 0x3 + +#define GPIO_PINCNF_DRIVE_Pos 8 +#define GPIO_PINCNF_DRIVE_Wid 3 +#define GPIO_S0D1 0x6 // Open drain \ No newline at end of file diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/opt.h b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/opt.h new file mode 100644 index 000000000..939a450c2 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/opt.h @@ -0,0 +1,23 @@ +#define BIT(i) (1 << (i)) + +#define SET_BIT(reg, n) reg |= BIT(n) +#define CLR_BIT(reg, n) reg &= ~BIT(n) + +#define SET_FIELD(reg, field, val) \ + reg = (reg & ~MASK(field)) | FIELD(field, val) + +#define GET_FIELD(reg, field) \ + ((reg >> field##_Pos) & MASK0(field)) + +#define FIELD(field, val) \ + (((val) & MASK0(field)) << field##_Pos) + +#define MASK(field) (MASK0(field) << field##_Pos) + +#define MASK0(field) (~((-2) << (field##_Wid-1))) + +#define SET_BYTE(reg, n, v) \ + reg = (reg & ~(0xff << 8*n)) | ((v & 0xff) << 8*n) + +#define ADDR(x) (* (unsigned volatile *) (x)) +#define ARRAY(x) ((unsigned volatile *) (x)) diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/uart.c b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/uart.c new file mode 100644 index 000000000..757d3d36d --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/uart.c @@ -0,0 +1,153 @@ +//***************************************************************************** +// +// uart.c - Driver for the UART. +// +// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 10636 of the Stellaris Peripheral Driver Library. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup uart_api +//! @{ +// +//***************************************************************************** +#include + +#include "inc/hw_types.h" +#include "inc/hw_nvic.h" +#include "driverlib/uart.h" +#include "driverlib/gpio.h" +#include "driverlib/opt.h" + +//***************************************************************************** +// +// This is a mapping between interrupt number (for the peripheral interrupts +// only) and the register that contains the interrupt enable for that +// interrupt. +// +//***************************************************************************** +static const unsigned long g_pulEnRegs[] = +{ + NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4 +}; + +void UARTlInitialize(void) { + GPIO_DIRSET = BIT(USB_TX); + GPIO_DIRCLR = BIT(USB_RX); + SET_FIELD(GPIO_PINCNF[USB_TX], GPIO_PINCNF_PULL, GPIO_Pullup); + SET_FIELD(GPIO_PINCNF[USB_RX], GPIO_PINCNF_PULL, GPIO_Pullup); + + UART_BAUDRATE = UART_BAUD_9600; // 9600 baud + UART_CONFIG = 0; // format 8N1 + UART_PSELTXD = USB_TX; // choose pins + UART_PSELRXD = USB_RX; + /* Configure the uart device interrupt */ + UART_ENABLE = UART_Enabled; + UART_INTENSET = (1 << 17) | (1<<2); + UART_STARTTX = 1; + UART_STARTRX = 1; + UART_RXDRDY = 0; + /* Enable the uart interrupt in NVIC */ + HWREG(g_pulEnRegs[(18 - 16) / 32]) = 1 << ((18 - 16) & 31); +} + +int SerialGetcNoBlock(void) { + char ch; + if (UART_RXDRDY) { + ch = UART_RXD; + UART_RXDRDY = 0; + return ch; + } + return -1; +} + +void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig) +{ + NO_IMPL(); +} + +tBoolean UARTCharsAvail(unsigned long ulBase) +{ + return UART_RXDRDY; +} + +long UARTCharGetNonBlocking(unsigned long ulBase) +{ + return SerialGetcNoBlock(); +} + +long UARTCharGet(unsigned long ulBase) +{ + while (!UART_RXDRDY); + char ch = UART_RXD; + UART_RXDRDY = 0; + return ch; +} + +tBoolean UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData) +{ + UART_TXDRDY = 0; + UART_TXD = ucData; + return 1; +} + +void UARTCharPut(unsigned long ulBase, unsigned char ucData) +{ + while (!UART_TXDRDY); + UART_TXDRDY = 0; + UART_TXD = ucData; +} + +void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags) +{ + NO_IMPL(); +} + +void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags) +{ + NO_IMPL(); +} + +unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked) +{ + return UART_INTENCLR; +} + +void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags) +{ + ulIntFlags &= 0xFFFFFFFB; + UART_INTENCLR = ulIntFlags; +} diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/uart.h b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/uart.h new file mode 100644 index 000000000..c4516ee4a --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/driverlib/uart.h @@ -0,0 +1,70 @@ +#ifndef __UART_H__ +#define __UART_H__ + +#include + +#define NO_IMPL() KPrintf("%s is not implemented!\n", __func__) + +/* Device pins */ +#define USB_TX 24 +#define USB_RX 25 + +/* UART */ +#define UART_STARTRX ADDR(0x40002000) +#define UART_STARTTX ADDR(0x40002008) +#define UART_RXDRDY ADDR(0x40002108) +#define UART_TXDRDY ADDR(0x4000211c) +#define UART_ENABLE ADDR(0x40002500) +#define UART_PSELTXD ADDR(0x4000250c) +#define UART_PSELRXD ADDR(0x40002514) +#define UART_RXD ADDR(0x40002518) +#define UART_TXD ADDR(0x4000251c) +#define UART_BAUDRATE ADDR(0x40002524) +#define UART_CONFIG ADDR(0x4000256c) +#define UART_INTEN ADDR(0x40002300) +#define UART_INTENSET ADDR(0x40002304) +#define UART_INTENCLR ADDR(0x40002308) + +#define UART_Enabled 0x4 +#define UART_INT_TXDRDY 7 +#define UART_INT_RXDRDY 2 + +#define UART_BAUD_9600 0x00275000 + +#ifdef __cplusplus +extern "C" +{ +#endif + +extern void UARTlInitialize(void); +extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig); +extern tBoolean UARTCharsAvail(unsigned long ulBase); +extern long UARTCharGetNonBlocking(unsigned long ulBase); +long UARTCharGet(unsigned long ulBase); +extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase, + unsigned char ucData); +extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); +extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); +extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); +extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); + +#ifndef DEPRECATED + +#define UARTCharNonBlockingGet(a) \ + UARTCharGetNonBlocking(a) +#define UARTCharNonBlockingPut(a, b) \ + UARTCharPutNonBlocking(a, b) +#endif + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __UART_H__ \ No newline at end of file diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_memmap.h b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_memmap.h new file mode 100644 index 000000000..64a036663 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_memmap.h @@ -0,0 +1,44 @@ +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of Stellaris. +// +// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 10636 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +#define UART0_BASE 0x40002000 // UART0 +#endif \ No newline at end of file diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_nvic.h b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_nvic.h new file mode 100644 index 000000000..20c68e9e8 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_nvic.h @@ -0,0 +1,1717 @@ +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 10636 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following are defines for the NVIC register addresses. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status + // Register +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable +#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable +#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable +#define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable +#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable +#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable +#define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending +#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending +#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending +#define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending +#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending +#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending +#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit +#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit +#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit +#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority +#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority +#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority +#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority +#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority +#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority +#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority +#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority +#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority +#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority +#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority +#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority +#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority +#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority +#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority +#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority +#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority +#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority +#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority +#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority +#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority +#define NVIC_PRI34 0xE000E488 // Interrupt 136-138 Priority +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset + // Control +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_CPAC 0xE000ED88 // Coprocessor Access Control +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size + // Alias 1 +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size + // Alias 2 +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size + // Alias 3 +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt +#define NVIC_FPCC 0xE000EF34 // Floating-Point Context Control +#define NVIC_FPCA 0xE000EF38 // Floating-Point Context Address +#define NVIC_FPDSC 0xE000EF3C // Floating-Point Default Status + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating + // Point +#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN2 register. +// +//***************************************************************************** +#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN3 register. +// +//***************************************************************************** +#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN4 register. +// +//***************************************************************************** +#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable +#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS2 register. +// +//***************************************************************************** +#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS3 register. +// +//***************************************************************************** +#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS4 register. +// +//***************************************************************************** +#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend +#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND2 register. +// +//***************************************************************************** +#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND3 register. +// +//***************************************************************************** +#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND4 register. +// +//***************************************************************************** +#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend +#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND2 register. +// +//***************************************************************************** +#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND3 register. +// +//***************************************************************************** +#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND4 register. +// +//***************************************************************************** +#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active +#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE2 register. +// +//***************************************************************************** +#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE3 register. +// +//***************************************************************************** +#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE4 register. +// +//***************************************************************************** +#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI14 register. +// +//***************************************************************************** +#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask +#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask +#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask +#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask +#define NVIC_PRI14_INTD_S 29 +#define NVIC_PRI14_INTC_S 21 +#define NVIC_PRI14_INTB_S 13 +#define NVIC_PRI14_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI15 register. +// +//***************************************************************************** +#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask +#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask +#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask +#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask +#define NVIC_PRI15_INTD_S 29 +#define NVIC_PRI15_INTC_S 21 +#define NVIC_PRI15_INTB_S 13 +#define NVIC_PRI15_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI16 register. +// +//***************************************************************************** +#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask +#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask +#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask +#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask +#define NVIC_PRI16_INTD_S 29 +#define NVIC_PRI16_INTC_S 21 +#define NVIC_PRI16_INTB_S 13 +#define NVIC_PRI16_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI17 register. +// +//***************************************************************************** +#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask +#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask +#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask +#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask +#define NVIC_PRI17_INTD_S 29 +#define NVIC_PRI17_INTC_S 21 +#define NVIC_PRI17_INTB_S 13 +#define NVIC_PRI17_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI18 register. +// +//***************************************************************************** +#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask +#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask +#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask +#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask +#define NVIC_PRI18_INTD_S 29 +#define NVIC_PRI18_INTC_S 21 +#define NVIC_PRI18_INTB_S 13 +#define NVIC_PRI18_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI19 register. +// +//***************************************************************************** +#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask +#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask +#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask +#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask +#define NVIC_PRI19_INTD_S 29 +#define NVIC_PRI19_INTC_S 21 +#define NVIC_PRI19_INTB_S 13 +#define NVIC_PRI19_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI20 register. +// +//***************************************************************************** +#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask +#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask +#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask +#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask +#define NVIC_PRI20_INTD_S 29 +#define NVIC_PRI20_INTC_S 21 +#define NVIC_PRI20_INTB_S 13 +#define NVIC_PRI20_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI21 register. +// +//***************************************************************************** +#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask +#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask +#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask +#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask +#define NVIC_PRI21_INTD_S 29 +#define NVIC_PRI21_INTC_S 21 +#define NVIC_PRI21_INTB_S 13 +#define NVIC_PRI21_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI22 register. +// +//***************************************************************************** +#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask +#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask +#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask +#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask +#define NVIC_PRI22_INTD_S 29 +#define NVIC_PRI22_INTC_S 21 +#define NVIC_PRI22_INTB_S 13 +#define NVIC_PRI22_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI23 register. +// +//***************************************************************************** +#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask +#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask +#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask +#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask +#define NVIC_PRI23_INTD_S 29 +#define NVIC_PRI23_INTC_S 21 +#define NVIC_PRI23_INTB_S 13 +#define NVIC_PRI23_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI24 register. +// +//***************************************************************************** +#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask +#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask +#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask +#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask +#define NVIC_PRI24_INTD_S 29 +#define NVIC_PRI24_INTC_S 21 +#define NVIC_PRI24_INTB_S 13 +#define NVIC_PRI24_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI25 register. +// +//***************************************************************************** +#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask +#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask +#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask +#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask +#define NVIC_PRI25_INTD_S 29 +#define NVIC_PRI25_INTC_S 21 +#define NVIC_PRI25_INTB_S 13 +#define NVIC_PRI25_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI26 register. +// +//***************************************************************************** +#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask +#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask +#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask +#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask +#define NVIC_PRI26_INTD_S 29 +#define NVIC_PRI26_INTC_S 21 +#define NVIC_PRI26_INTB_S 13 +#define NVIC_PRI26_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI27 register. +// +//***************************************************************************** +#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask +#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask +#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask +#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask +#define NVIC_PRI27_INTD_S 29 +#define NVIC_PRI27_INTC_S 21 +#define NVIC_PRI27_INTB_S 13 +#define NVIC_PRI27_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI28 register. +// +//***************************************************************************** +#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask +#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask +#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask +#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask +#define NVIC_PRI28_INTD_S 29 +#define NVIC_PRI28_INTC_S 21 +#define NVIC_PRI28_INTB_S 13 +#define NVIC_PRI28_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI29 register. +// +//***************************************************************************** +#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask +#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask +#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask +#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask +#define NVIC_PRI29_INTD_S 29 +#define NVIC_PRI29_INTC_S 21 +#define NVIC_PRI29_INTB_S 13 +#define NVIC_PRI29_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI30 register. +// +//***************************************************************************** +#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask +#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask +#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask +#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask +#define NVIC_PRI30_INTD_S 29 +#define NVIC_PRI30_INTC_S 21 +#define NVIC_PRI30_INTB_S 13 +#define NVIC_PRI30_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI31 register. +// +//***************************************************************************** +#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask +#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask +#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask +#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask +#define NVIC_PRI31_INTD_S 29 +#define NVIC_PRI31_INTC_S 21 +#define NVIC_PRI31_INTB_S 13 +#define NVIC_PRI31_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI32 register. +// +//***************************************************************************** +#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask +#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask +#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask +#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask +#define NVIC_PRI32_INTD_S 29 +#define NVIC_PRI32_INTC_S 21 +#define NVIC_PRI32_INTB_S 13 +#define NVIC_PRI32_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI33 register. +// +//***************************************************************************** +#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI33_INTD_S 29 +#define NVIC_PRI33_INTC_S 21 +#define NVIC_PRI33_INTB_S 13 +#define NVIC_PRI33_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI34 register. +// +//***************************************************************************** +#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI34_INTD_S 29 +#define NVIC_PRI34_INTC_S 21 +#define NVIC_PRI34_INTB_S 13 +#define NVIC_PRI34_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPAC register. +// +//***************************************************************************** +#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only +#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access +#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only +#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_NUMBER +// register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE_ADDR_S 5 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access +#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none +#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only +#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw +#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none +#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro +#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable +#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable +#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable +#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable +#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable +#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable +#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable +#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable +#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable +#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable +#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable +#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes +#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes +#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes +#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes +#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes +#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes +#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes +#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes +#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes +#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes +#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes +#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes +#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes +#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes +#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes +#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes +#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes +#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes +#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes +#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes +#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes +#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes +#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes +#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes +#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes +#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes +#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes +#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes +#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE1_ADDR_S 5 +#define NVIC_MPU_BASE1_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR1_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR1_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR1_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE2_ADDR_S 5 +#define NVIC_MPU_BASE2_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR2_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR2_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR2_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE3_ADDR_S 5 +#define NVIC_MPU_BASE3_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR3_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR3_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR3_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID +#define NVIC_SW_TRIG_INTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCC register. +// +//***************************************************************************** +#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation + // Enable +#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable +#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready +#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready +#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready +#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready +#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode +#define NVIC_FPCC_USER 0x00000002 // User Privilege Level +#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCA register. +// +//***************************************************************************** +#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address +#define NVIC_FPCA_ADDRESS_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPDSC register. +// +//***************************************************************************** +#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default +#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default +#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default +#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default +#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode +#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) + // mode +#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity + // (RM) mode +#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode + +#endif // __HW_NVIC_H__ diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_types.h b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_types.h new file mode 100644 index 000000000..8339305e7 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Libraries/inc/hw_types.h @@ -0,0 +1,212 @@ +//***************************************************************************** +// +// hw_types.h - Common types and macros. +// +// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 10636 of the Stellaris Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +//***************************************************************************** +// +// Helper Macros for determining silicon revisions, etc. +// +// These macros will be used by Driverlib at "run-time" to create necessary +// conditional code blocks that will allow a single version of the Driverlib +// "binary" code to support multiple(all) Stellaris silicon revisions. +// +// It is expected that these macros will be used inside of a standard 'C' +// conditional block of code, e.g. +// +// if(CLASS_IS_SANDSTORM) +// { +// do some Sandstorm-class specific code here. +// } +// +// By default, these macros will be defined as run-time checks of the +// appropriate register(s) to allow creation of run-time conditional code +// blocks for a common DriverLib across the entire Stellaris family. +// +// However, if code-space optimization is required, these macros can be "hard- +// coded" for a specific version of Stellaris silicon. Many compilers will +// then detect the "hard-coded" conditionals, and appropriately optimize the +// code blocks, eliminating any "unreachable" code. This would result in +// a smaller Driverlib, thus producing a smaller final application size, but +// at the cost of limiting the Driverlib binary to a specific Stellaris +// silicon revision. +// +//***************************************************************************** +#ifndef CLASS_IS_SANDSTORM +#define CLASS_IS_SANDSTORM \ + (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) || \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM))) +#endif + +#ifndef CLASS_IS_FURY +#define CLASS_IS_FURY \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY)) +#endif + +#ifndef CLASS_IS_DUSTDEVIL +#define CLASS_IS_DUSTDEVIL \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL)) +#endif + +#ifndef CLASS_IS_TEMPEST +#define CLASS_IS_TEMPEST \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TEMPEST)) +#endif + +#ifndef CLASS_IS_FIRESTORM +#define CLASS_IS_FIRESTORM \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ + (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FIRESTORM)) +#endif + +#ifndef REVISION_IS_A0 +#define REVISION_IS_A0 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_A1 +#define REVISION_IS_A1 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_A2 +#define REVISION_IS_A2 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2)) +#endif + +#ifndef REVISION_IS_B0 +#define REVISION_IS_B0 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_B1 +#define REVISION_IS_B1 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1)) +#endif + +#ifndef REVISION_IS_C0 +#define REVISION_IS_C0 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_0)) +#endif + +#ifndef REVISION_IS_C1 +#define REVISION_IS_C1 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1)) +#endif + +#ifndef REVISION_IS_C2 +#define REVISION_IS_C2 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2)) +#endif + +#ifndef REVISION_IS_C3 +#define REVISION_IS_C3 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_3)) +#endif + +#ifndef REVISION_IS_C5 +#define REVISION_IS_C5 \ + ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ + (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_5)) +#endif + +//***************************************************************************** +// +// Deprecated silicon class and revision detection macros. +// +//***************************************************************************** +#ifndef DEPRECATED +#define DEVICE_IS_SANDSTORM CLASS_IS_SANDSTORM +#define DEVICE_IS_FURY CLASS_IS_FURY +#define DEVICE_IS_REVA2 REVISION_IS_A2 +#define DEVICE_IS_REVC1 REVISION_IS_C1 +#define DEVICE_IS_REVC2 REVISION_IS_C2 +#endif + +#endif // __HW_TYPES_H__ diff --git a/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Makefile b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Makefile new file mode 100644 index 000000000..15ac75206 --- /dev/null +++ b/Ubiquitous/XiUOS/board/cortex-m0-emulator/third_party_driver/Makefile @@ -0,0 +1,3 @@ +SRC_DIR := Libraries + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file