Ubiquitous/RT-Thread_Fusion_XiUOS:change name from RT_Thread to RT-Thread_Fusion_XiUOS

This commit is contained in:
chunyexixiaoyu
2022-03-30 18:18:18 +08:00
parent 658feff666
commit 5a0ffaf193
624 changed files with 13 additions and 13 deletions
@@ -0,0 +1,554 @@
#
# Automatically generated file; DO NOT EDIT.
# XIUOS Rt-thread Configuration
#
CONFIG_ROOT_DIR="../../../.."
CONFIG_BSP_DIR="."
CONFIG_RT_Thread_DIR="../.."
CONFIG_RTT_DIR="../../rt-thread"
CONFIG_BOARD_K210_EVB=y
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_BIG_ENDIAN is not set
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=2
CONFIG_RT_ALIGN_SIZE=8
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=4096
CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
# CONFIG_RT_USING_TIMER_SOFT is not set
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_ASM_MEMCPY is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
CONFIG_RT_DEBUG_INIT_CONFIG=y
CONFIG_RT_DEBUG_INIT=1
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
CONFIG_RT_USING_SIGNALS=y
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_MEMHEAP=y
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_SMALL_MEM is not set
CONFIG_RT_USING_SLAB=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uarths"
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_VER_NUM=0x40004
CONFIG_ARCH_CPU_64BIT=y
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_RISCV_FPU=y
CONFIG_ARCH_RISCV_FPU_S=y
CONFIG_ARCH_RISCV64=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
CONFIG_RT_USING_CPLUSPLUS=y
# CONFIG_RT_USING_CPLUSPLUS11 is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_RT_USING_MSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=16384
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=16
CONFIG_DFS_FILESYSTEM_TYPES_MAX=16
CONFIG_DFS_FD_MAX=64
# CONFIG_RT_USING_DFS_MNTTABLE is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_NFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_QSPI is not set
CONFIG_RT_USING_SPI_MSD=y
CONFIG_RT_USING_SFUD=y
CONFIG_RT_SFUD_USING_SFDP=y
CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
# CONFIG_RT_SFUD_USING_QSPI is not set
CONFIG_RT_SFUD_SPI_MAX_HZ=50000000
CONFIG_RT_DEBUG_SFUD=y
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
CONFIG_RT_USING_WIFI=y
CONFIG_RT_WLAN_DEVICE_STA_NAME="wlan0"
CONFIG_RT_WLAN_DEVICE_AP_NAME="wlan1"
CONFIG_RT_WLAN_SSID_MAX_LENGTH=32
CONFIG_RT_WLAN_PASSWORD_MAX_LENGTH=32
CONFIG_RT_WLAN_DEV_EVENT_NUM=2
CONFIG_RT_WLAN_MANAGE_ENABLE=y
CONFIG_RT_WLAN_SCAN_WAIT_MS=10000
CONFIG_RT_WLAN_CONNECT_WAIT_MS=10000
CONFIG_RT_WLAN_SCAN_SORT=y
CONFIG_RT_WLAN_MSH_CMD_ENABLE=y
CONFIG_RT_WLAN_AUTO_CONNECT_ENABLE=y
CONFIG_AUTO_CONNECTION_PERIOD_MS=2000
CONFIG_RT_WLAN_CFG_ENABLE=y
CONFIG_RT_WLAN_CFG_INFO_MAX=3
CONFIG_RT_WLAN_PROT_ENABLE=y
CONFIG_RT_WLAN_PROT_NAME_LEN=8
CONFIG_RT_WLAN_PROT_MAX=2
CONFIG_RT_WLAN_DEFAULT_PROT="lwip"
CONFIG_RT_WLAN_PROT_LWIP_ENABLE=y
CONFIG_RT_WLAN_PROT_LWIP_NAME="lwip"
# CONFIG_RT_WLAN_PROT_LWIP_PBUF_FORCE is not set
CONFIG_RT_WLAN_WORK_THREAD_ENABLE=y
CONFIG_RT_WLAN_WORKQUEUE_THREAD_NAME="wlan"
CONFIG_RT_WLAN_WORKQUEUE_THREAD_SIZE=2048
CONFIG_RT_WLAN_WORKQUEUE_THREAD_PRIO=15
# CONFIG_RT_WLAN_DEBUG is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
CONFIG_RT_USING_PTHREADS=y
CONFIG_PTHREAD_NUM_MAX=8
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_GETLINE is not set
# CONFIG_RT_USING_POSIX_AIO is not set
CONFIG_RT_LIBC_USING_TIME=y
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# Network
#
#
# Socket abstraction layer
#
CONFIG_RT_USING_SAL=y
# CONFIG_SAL_INTERNET_CHECK is not set
#
# protocol stack implement
#
CONFIG_SAL_USING_LWIP=y
CONFIG_SAL_USING_POSIX=y
#
# Network interface device
#
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
#
# light weight TCP/IP stack
#
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
CONFIG_RT_USING_LWIP202=y
# CONFIG_RT_USING_LWIP203 is not set
# CONFIG_RT_USING_LWIP212 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=8
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
CONFIG_RT_LWIP_DHCP=y
CONFIG_IP_SOF_BROADCAST=1
CONFIG_IP_SOF_BROADCAST_RECV=1
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.1.30"
CONFIG_RT_LWIP_GWADDR="192.168.1.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=16
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=10240
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=10240
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
CONFIG_LWIP_SO_LINGER=0
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_RT_LWIP_DEBUG is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
# CONFIG_LWIP_USING_DHCPD is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# Board Drivers Config
#
CONFIG_BSP_USING_UART_HS=y
#
# General Purpose UARTs
#
CONFIG_BSP_USING_UART1=y
CONFIG_BSP_UART1_TXD_PIN=20
CONFIG_BSP_UART1_RXD_PIN=21
CONFIG_BSP_UART1_RTS_PIN=-1
CONFIG_BSP_UART1_CTS_PIN=-1
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_I2C1 is not set
CONFIG_BSP_USING_SPI1=y
# CONFIG_BSP_USING_SPI1_AS_QSPI is not set
CONFIG_BSP_SPI1_CLK_PIN=27
CONFIG_BSP_SPI1_D0_PIN=28
CONFIG_BSP_SPI1_D1_PIN=26
CONFIG_BSP_SPI1_USING_SS0=y
CONFIG_BSP_SPI1_SS0_PIN=29
CONFIG_BSP_SPI1_USING_SS1=y
CONFIG_BSP_SPI1_SS1_PIN=8
# CONFIG_BSP_SPI1_USING_SS2 is not set
# CONFIG_BSP_SPI1_USING_SS3 is not set
CONFIG_BSP_USING_LCD=y
CONFIG_BSP_LCD_CS_PIN=36
CONFIG_BSP_LCD_WR_PIN=39
CONFIG_BSP_LCD_DC_PIN=38
CONFIG_BSP_LCD_RST_PIN=37
CONFIG_BSP_LCD_BACKLIGHT_PIN=-1
CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_LOW=y
# CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_HIGH is not set
CONFIG_BSP_LCD_CLK_FREQ=20000000
# CONFIG_BSP_BOARD_KD233 is not set
# CONFIG_BSP_BOARD_K210_OPENMV_TEST is not set
CONFIG_BSP_BOARD_USER=y
CONFIG_BSP_LCD_X_MAX=240
CONFIG_BSP_LCD_Y_MAX=320
CONFIG_BSP_USING_SDCARD=y
CONFIG_BSP_USING_DVP=y
#
# The default pin assignment is based on the Maix Duino K210 development board
#
CONFIG_BSP_DVP_SCCB_SDA_PIN=40
CONFIG_BSP_DVP_SCCB_SCLK_PIN=41
CONFIG_BSP_DVP_CMOS_RST_PIN=42
CONFIG_BSP_DVP_CMOS_VSYNC_PIN=43
CONFIG_BSP_DVP_CMOS_PWDN_PIN=44
CONFIG_BSP_DVP_CMOS_XCLK_PIN=46
CONFIG_BSP_DVP_CMOS_PCLK_PIN=47
CONFIG_BSP_DVP_CMOS_HREF_PIN=45
#
# Kendryte SDK Config
#
CONFIG_PKG_KENDRYTE_SDK_VERNUM=0x0055
#
# MicroPython
#
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# More Drivers
#
# CONFIG_PKG_USING_RW007 is not set
CONFIG_DRV_USING_OV2640=y
CONFIG_OV2640_JPEG_MODE=y
# CONFIG_OV2640_RGB565_MODE is not set
CONFIG_OV2640_X_RESOLUTION_IMAGE_OUTSIZE=240
CONFIG_OV2640_Y_RESOLUTION_IMAGE_OUTSIZE=240
CONFIG_OV2640_X_IMAGE_WINDOWS_SIZE=400
#
# the value must be greater than OV2640_X_RESOLUTION_IMAGE_OUTSIZE
#
CONFIG_OV2640_Y_IMAGE_WINDOWS_SIZE=400
#
# the value must be greater than OV2640_Y_RESOLUTION_IMAGE_OUTSIZE
#
#
# APP_Framework
#
#
# Framework
#
CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y
CONFIG_ADD_XIZI_FETURES=y
# CONFIG_ADD_NUTTX_FETURES is not set
# CONFIG_ADD_RTTHREAD_FETURES is not set
# CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set
# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set
CONFIG_SUPPORT_KNOWING_FRAMEWORK=y
# CONFIG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_USING_KNOWING_FILTER is not set
# CONFIG_USING_OTA_MODEL is not set
# CONFIG_USING_IMAGE_PROCESSING is not set
# CONFIG_USING_CMSIS_5 is not set
CONFIG_USING_KPU_PROCESSING=y
CONFIG_USING_YOLOV2=y
CONFIG_USING_YOLOV2_JSONPARSER=y
CONFIG_USING_K210_YOLOV2_DETECT=y
# CONFIG_USING_NNOM is not set
# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set
#
# Security
#
# CONFIG_CRYPTO is not set
#
# Applications
#
#
# config stack size and priority of main task
#
CONFIG_MAIN_KTASK_STACK_SIZE=1024
#
# ota app
#
# CONFIG_APPLICATION_OTA is not set
#
# test app
#
# CONFIG_USER_TEST is not set
#
# connection app
#
# CONFIG_APPLICATION_CONNECTION is not set
#
# control app
#
#
# knowing app
#
CONFIG_APPLICATION_KNOWING=y
CONFIG_K210_DETECT_ENTRY=y
# CONFIG_IRIS_ML_DEMO is not set
# CONFIG_K210_FFT_TEST is not set
# CONFIG_USING_IMAGE_PROCESSING_APP is not set
#
# sensor app
#
CONFIG_APPLICATION_SENSOR=y
# CONFIG_APPLICATION_SENSOR_HCHO is not set
# CONFIG_APPLICATION_SENSOR_TVOC is not set
# CONFIG_APPLICATION_SENSOR_IAQ is not set
# CONFIG_APPLICATION_SENSOR_CH4 is not set
# CONFIG_APPLICATION_SENSOR_CO2 is not set
# CONFIG_APPLICATION_SENSOR_PM1_0 is not set
# CONFIG_APPLICATION_SENSOR_PM2_5 is not set
# CONFIG_APPLICATION_SENSOR_PM10 is not set
# CONFIG_APPLICATION_SENSOR_VOICE is not set
# CONFIG_APPLICATION_SENSOR_TEMPERATURE is not set
# CONFIG_APPLICATION_SENSOR_HUMIDITY is not set
# CONFIG_USING_EMBEDDED_DATABASE_APP is not set
#
# lib
#
CONFIG_APP_SELECT_NEWLIB=y
# CONFIG_APP_SELECT_OTHER_LIB is not set
CONFIG_LIB_USING_CJSON=y
# CONFIG_LIB_USING_QUEUE is not set
# CONFIG_LIB_LV is not set
# CONFIG_USING_EMBEDDED_DATABASE is not set
CONFIG___STACKSIZE__=4096
@@ -0,0 +1,228 @@
# this
*.old
*.dblite
cconfig.h
*.bin
*.map
# rtconfig.h
# .config
# General
.DS_Store
.AppleDouble
.LSOverride
# Icon must end with two \r
Icon
# Thumbnails
._*
# Files that might appear in the root of a volume
.DocumentRevisions-V100
.fseventsd
.Spotlight-V100
.TemporaryItems
.Trashes
.VolumeIcon.icns
.com.apple.timemachine.donotpresent
# Directories potentially created on remote AFP share
.AppleDB
.AppleDesktop
Network Trash Folder
Temporary Items
.apdisk
# Byte-compiled / optimized / DLL files
__pycache__/
*.py[cod]
*$py.class
# C extensions
*.so
# Distribution / packaging
.Python
build/
develop-eggs/
dist/
downloads/
eggs/
.eggs/
lib/
lib64/
parts/
sdist/
var/
wheels/
share/python-wheels/
*.egg-info/
.installed.cfg
*.egg
MANIFEST
# PyInstaller
# Usually these files are written by a python script from a template
# before PyInstaller builds the exe, so as to inject date/other infos into it.
*.manifest
*.spec
# Installer logs
pip-log.txt
pip-delete-this-directory.txt
# Unit test / coverage reports
htmlcov/
.tox/
.nox/
.coverage
.coverage.*
.cache
nosetests.xml
coverage.xml
*.cover
*.py,cover
.hypothesis/
.pytest_cache/
cover/
# Translations
*.mo
*.pot
# Django stuff:
*.log
local_settings.py
db.sqlite3
db.sqlite3-journal
# Flask stuff:
instance/
.webassets-cache
# Scrapy stuff:
.scrapy
# Sphinx documentation
docs/_build/
# PyBuilder
.pybuilder/
target/
# Jupyter Notebook
.ipynb_checkpoints
# IPython
profile_default/
ipython_config.py
# pyenv
# For a library or package, you might want to ignore these files since the code is
# intended to run in multiple environments; otherwise, check them in:
# .python-version
# pipenv
# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control.
# However, in case of collaboration, if having platform-specific dependencies or dependencies
# having no cross-platform support, pipenv may install dependencies that don't work, or not
# install all needed dependencies.
#Pipfile.lock
# PEP 582; used by e.g. github.com/David-OConnor/pyflow
__pypackages__/
# Celery stuff
celerybeat-schedule
celerybeat.pid
# SageMath parsed files
*.sage.py
# Environments
.env
.venv
env/
venv/
ENV/
env.bak/
venv.bak/
# Spyder project settings
.spyderproject
.spyproject
# Rope project settings
.ropeproject
# mkdocs documentation
/site
# mypy
.mypy_cache/
.dmypy.json
dmypy.json
# Pyre type checker
.pyre/
# pytype static type analyzer
.pytype/
# Cython debug symbols
cython_debug/
# Prerequisites
*.d
# Object files
*.o
*.ko
*.obj
*.elf
# Linker output
*.ilk
*.map
*.exp
# Precompiled Headers
*.gch
*.pch
# Libraries
*.lib
*.a
*.la
*.lo
# Shared objects (inc. Windows DLLs)
*.dll
*.so
*.so.*
*.dylib
# Executables
*.exe
*.out
*.app
*.i*86
*.x86_64
*.hex
# Debug files
*.dSYM/
*.su
*.idb
*.pdb
# Kernel Module Compile Results
*.mod*
*.cmd
.tmp_versions/
modules.order
Module.symvers
Mkfile.old
dkms.con
@@ -0,0 +1,40 @@
mainmenu "XIUOS Rt-thread Configuration"
config ROOT_DIR
string
default "../../../.."
config BSP_DIR
string
default "."
config RT_Thread_DIR
string
default "../.."
config RTT_DIR
string
default "../../rt-thread"
config BOARD_K210_EVB
bool
select ARCH_RISCV64
select ARCH_RISCV_FPU_S
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
config APP_DIR
string
default "../../../../APP_Framework"
source "$RTT_DIR/Kconfig"
source "base-drivers/Kconfig"
source "kendryte-sdk/Kconfig"
source "$RT_Thread_DIR/micropython/Kconfig"
source "$RT_Thread_DIR/app_match_rt-thread/Kconfig"
source "$ROOT_DIR/APP_Framework/Kconfig"
config __STACKSIZE__
int "stack size for interrupt"
default 4096
@@ -0,0 +1,117 @@
# K210最小系统板(Max bit)说明
## OV2640 menuconfig 配置:
More Driver-------->ov2640 driver (勾选) 保存即可
## RW007 menuconfig 配置:
More Driver-------->rw007:SPI WIFI rw007 driver
example driver port (not use example driver, porting by myself)
(20000000) SPI MAX Hz
Board Drivers Config
Enable SPI1
(27) spi1 clk pin number
(28) spi1 d0 pin number
(26) spi1 d1 pin number
SPI1 Enable SS1spi11 dev-------->(8) spi1 ss1 pin number
(spi11) the SPIDEV rw007 driver on
(7) rw007 int pin for rw007
(6) rw007 rst pin for rw007
**SPI1 Enable SS1spi11 dev)表示SPI1总线片选编号1 ,此时挂载在总线上设备名是spi11,所以 the SPIDEV rw007 driver on参数也要填写(spi11**
## SD卡配置:
Board Drivers Config-------->Enable SDCARD (spi1(ss0)) (勾选)保存即可 SPI1 Enable SS0spi10 dev-------->(29) spi1 ss1 pin number 会默认配置
**SD卡和RW007共用一条spi硬件总线 ,其中片选设备sd卡为SPI1 Enable SS0spi10 dev),RW007片选设备为SPI1 Enable SS1spi11 dev**
**上述引脚根据电路实际而定,另外涉及到相关的Lwip wifi framwork等已经默认配置并匹配**
## 以下为引脚硬件的连接表
## RW007(SPI1 ) Kendryte Sipeed MAX bit io
| 引脚 | 作用 | 引脚序号 | RW007板子 |
| ------------------ | --------- | -------- | --------- |
| io 27(印丝标注SCK) | SPI1_SCK | | SCK |
| io 26(印丝标注SO) | SPI1_MISO | | MISO |
| io 28(印丝标注SI) | SPI1_MOSI | | MOSI |
| io 8 | CS/BOOT1 | | CS |
| io 7 | INT/BUSY | | D9 |
| io 6 | RESET | | D8 |
## SD卡Kendryte Sipeed MAX bit io
| 引脚 | 作用 | 引脚序号 | RW007板子 |
| ------------------ | --------- | -------- | --------- |
| io 27(印丝标注SCK) | SPI1_SCK | | SCK |
| io 26(印丝标注SO) | SPI1_MISO | | MISO |
| io 28(印丝标注SI) | SPI1_MOSI | | MOSI |
| io 29 | CS/BOOT1 | | CS |
**注意:BSP_SPI1_D0_PIN 10 d0也就是MOSI sd卡可直接利用Max bit板载,无需重新接线。SD卡和Rw007设备共用一条SPI1总线**
## 编译说明
编译K210,需要有RT-Thread的代码,因为K210的sdk是以软件包方式,所以需要在bsp/k210下做软件包更新。Windows下推进使用[env工具][1],然后在console下进入bsp/k210目录中,运行:
cd bsp/k210
pkgs --update
如果在Linux平台下,可以先执行
scons --menuconfig
它会自动下载env相关脚本到~/.env目录,然后执行
source ~/.env/env.sh
cd bsp/k210
pkgs --update
下载risc-v的工具链,[下载地址](https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases)
更新完软件包后,在`rtconfig.py`中将risc-v工具链的本地路径加入文档。
注:
1. 工具链建议使用上方提供的,`kendryte的官方工具链`会报浮点类型不兼容的错误,`risc-v工具链8.2.0之前的版本`会出现头文件不兼容的问题。
2. 网上传需要开启C++ 17,认为k210的神经网络编译器nncase多数语法由C++ 17,故需要开启C++ 17。个人认为没有必要,nncase是在PC端独立使用的,
作用是将神经网络模型转为kmodel格式,此格式文件为已经编译的二进制文件.
然后执行scons编译:
set RTT_EXEC_PATH=your_toolchains
scons
来编译这个板级支持包。如果编译正确无误,会产生rtthread.elf、rtthread.bin文件。其中rtthread.bin需要烧写到设备中进行运行。
注:如果初次使用编译报错,可能是使用的SDK过老,使用`menuconfig`命令,在→ RT-Thread online packages → peripheral libraries
and drivers → the kendryte-sdk package for rt-thread中将SDK改为latest版本即可。
@@ -0,0 +1,13 @@
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
@@ -0,0 +1,69 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../rt-thread')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
# use ASPPCOM to replace ASCOM, ASPPCOM will use CFLAGS/CPPFLAGS with AS
env['ASCOM'] = env['ASPPCOM']
AddOption('--compiledb',
dest = 'compiledb',
action = 'store_true',
default = False,
help = 'generate compile_commands.json')
if GetOption('compiledb'):
if int(SCons.__version__.split('.')[0]) >= 4:
env['COMPILATIONDB_USE_ABSPATH'] = True
env.Tool('compilation_db')
env.CompilationDatabase('compile_commands.json')
else:
print('Warning: --compiledb only support on SCons 4.0+')
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
stack_size = 4096
stack_lds = open('link_stacksize.lds', 'w')
if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__')
stack_lds.write('__STACKSIZE__ = %d;' % stack_size)
stack_lds.close()
# include more drivers
objs.extend(SConscript(os.getcwd() + '/../../app_match_rt-thread/SConscript'))
# include APP_Framework/Framework
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Framework/SConscript'))
# include APP_Framework/Applications
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Applications/SConscript'))
# include APP_Framework/lib
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/lib/SConscript'))
# include Ubiquitous/RT-Thread/micropython
objs.extend(SConscript(os.getcwd() + '/../../micropython/SConscript'))
# make a building
DoBuilding(TARGET, objs)
@@ -0,0 +1,9 @@
from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
@@ -0,0 +1,100 @@
#include <rtthread.h>
#include <rtdevice.h>
#include <stdint.h>
#include <stdlib.h>
#include "drv_lcd.h"
static void drawarea(rt_device_t dev, struct rt_device_graphic_info *info,
int x, int y, int w, int h, uint16_t c)
{
struct rt_device_rect_info rect;
uint16_t *fb;
int i, j;
fb = (uint16_t *)info->framebuffer;
fb += (info->width * y);
fb += x;
for (j = 0; j < h; j++)
{
for (i = 0; i < w; i++)
{
fb[i] = c;
}
fb += info->width;
}
rect.x = x;
rect.y = y;
rect.width = w;
rect.height = h;
rt_device_control(dev, RTGRAPHIC_CTRL_RECT_UPDATE, &rect);
}
#define RGB_BUF_SIZE (320*240*2)
static int showcolor(int argc, char **argv)
{
unsigned char r = 0, g = 0, b = 0;
char *devname = "lcd";
rt_device_t dev;
struct rt_device_graphic_info info;
int result;
int x = 0, y = 0;
int i;
uint16_t c;
for (i = 1; i < argc; i++)
{
switch (i)
{
case 1:
r = atoi(argv[i]);
break;
case 2:
g = atoi(argv[i]);
break;
case 3:
b = atoi(argv[i]);
break;
}
}
dev = rt_device_find(devname);
if (!dev)
{
rt_kprintf("lcd: %s not found\n", devname);
return -1;
}
if (rt_device_open(dev, 0) != 0)
{
rt_kprintf("lcd open fail\n");
return -1;
}
result = rt_device_control(dev, RTGRAPHIC_CTRL_GET_INFO, &info);
if (result != RT_EOK)
{
rt_kprintf("get device information failed\n");
return result;
}
c = (uint16_t)(((r >> 3) << 11) | ((g >> 2) << 6) | ((b >> 3)));
drawarea(dev, &info, x, y, 24, 24, c);
lcd_set_color(BLACK, BLUE);
lcd_show_string(0, 40, 16, "hello world");
lcd_show_string(0, 60, 24, "hello world");
lcd_show_string(0, 90, 32, "hello world");
lcd_draw_line(0, 200, 319, 200);
lcd_draw_circle(270, 120, 30);
lcd_set_color(BLACK, RED);
lcd_show_string(0, 130, 32, "after set color");
lcd_draw_line(0, 0, 319, 239);
lcd_draw_rectangle(50, 10, 170, 145);
lcd_draw_circle(160, 120, 50);
rt_device_close(dev);
return 0;
}
MSH_CMD_EXPORT(showcolor, showcolor R G B-- R / G / B : 0 ~255);
@@ -0,0 +1,48 @@
/*
* @Author: your name
* @Date: 2021-10-11 22:04:25
* @LastEditTime: 2021-10-14 11:12:52
* @LastEditors: Please set LastEditors
* @Description: In User Settings Edit
* @FilePath: \xiuos\Ubiquitous\RT_Thread\bsp\k210\applications\main.c
*/
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <stdio.h>
#define LED_G 12
int main(void)
{
rt_pin_mode(LED_G, PIN_MODE_OUTPUT);
rt_thread_mdelay(100);
char info1[25] ={0};
char info2[25] ={0};
sprintf(info1,"xuos-intelligence k210 ");
sprintf(info2,"build %s %s",__DATE__,__TIME__);
printf("%s %s \n",info1,info2);
#ifdef BSP_USING_LCD
#include<drv_lcd.h>
lcd_show_string(0,60,24,info1);
lcd_show_string(0,90,24,info2);
#endif
while(1)
{
rt_pin_write(LED_G, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED_G, PIN_LOW);
rt_thread_mdelay(500);
}
return 0;
}
@@ -0,0 +1,106 @@
#include <rtthread.h>
#include <rtdevice.h>
#include "stdio.h"
#include "string.h"
#include "dvp.h"
#include "fpioa.h"
#include "plic.h"
#include "sysctl.h"
#if(defined DRV_USING_OV2640 && defined BSP_USING_LCD)
#include<drv_ov2640.h>
#define RGB_BUF_SIZE (320*240*2)
#ifdef RT_USING_POSIX
#include <pthread.h>
#include <unistd.h>
#include <stdio.h>
#include <dfs_poll.h>
#ifdef RT_USING_POSIX_TERMIOS
#include <posix_termios.h>
#endif
#endif
static int g_fd = 0;
static _ioctl_shoot_para shoot_para_t = {0};
extern void lcd_show_image(int x, int y, int wide, int height,const rt_uint8_t *buf);
extern void lcd_draw_picture(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height, uint32_t *ptr);
void ov2640_test(int argc, char **argv)
{
g_fd = open("/dev/ov2640",O_RDONLY);
if(g_fd < 0)
{
printf("open ov2640 fail !!");
return;
}
if (argc < 2)
{
printf("Usage:ov2640 display images in real time or take photos \n");
printf("Like: ov2640_test 1(take photos )\n");
printf("Like: ov2640_test 0(display images in real time )\n");
close(g_fd);
return ;
}
uint32_t* rgbbuffer = rt_malloc(RGB_BUF_SIZE);
rt_thread_t tid;
rt_err_t ret = 0;
int temf = 0;
if(NULL == rgbbuffer)
{
printf("malloc rgbbuffer failed ! \n");
close(g_fd);
return;
}
temf = strtoul(argv[1],0, 10);
printf("ov2640_test choose %d mode \n",temf);
shoot_para_t.pdata = (uint32_t)(rgbbuffer);
shoot_para_t.length = RGB_BUF_SIZE;
if(temf == 0)
{
void lcd_show_ov2640_thread(uint32_t* rgbbuffer);
tid = rt_thread_create("lcdshow", lcd_show_ov2640_thread, rgbbuffer,3000, 9, 20);
rt_thread_startup(tid);
}
else
{
memset(rgbbuffer,0,320*240*2);
ret = ioctl(g_fd,IOCTRL_CAMERA_START_SHOT,&shoot_para_t);
// ret = rt_ov2640_start_shoot((uint32_t)(rgbbuffer), RGB_BUF_SIZE);
if(RT_ERROR == ret)
{
printf("ov2640 can't wait event flag");
close(g_fd);
return;
}
lcd_show_image(0, 0, 320, 240, rgbbuffer);
rt_thread_mdelay(100);
printf("the lcd has shown the image \n");
rt_free(rgbbuffer);
close(g_fd);
}
}
MSH_CMD_EXPORT(ov2640_test,lcd show camera shot image);
void lcd_show_ov2640_thread(uint32_t* rgbbuffer)
{
rt_err_t ret = 0;
while(1)
{
ret = ioctl(g_fd,IOCTRL_CAMERA_START_SHOT,&shoot_para_t);
if(RT_ERROR == ret)
{
printf("ov2640 can't wait event flag");
rt_free(rgbbuffer);
return;
}
//lcd_show_image(0, 0, 320, 240, rgbbuffer);
lcd_draw_picture(0, 0, 320, 240, rgbbuffer);
rt_thread_mdelay(1);
}
}
#endif
@@ -0,0 +1,105 @@
#include <rtthread.h>
#ifdef PKG_USING_RW007
#include <netdb.h>
#include <string.h>
#include <finsh.h>
#include <sys/socket.h>
static const char send_data[] = "This is TCP Client from AIIT";
void rw007_test(int argc, char **argv)
{
int ret;
char *recv_data;
struct hostent *host;
int sock, bytes_received;
struct sockaddr_in server_addr;
const char *url;
int port;
extern rt_bool_t rt_wlan_is_connected(void);
if (rt_wlan_is_connected() != 1)
{
printf("Please connect a wifi firstly\n");
return;
}
if (argc < 3)
{
printf("Usage: rw007 URL PORT\n");
printf("Like: rw007 192.168.12.44 5000\n");
return ;
}
url = argv[1];
port = strtoul(argv[2], 0, 10);
host = gethostbyname(url);
recv_data = rt_malloc(1024);
if (recv_data == RT_NULL)
{
printf("No memory\n");
return;
}
if ((sock = socket(AF_INET, SOCK_STREAM, 0)) == -1)
{
printf("Socket error\n");
rt_free(recv_data);
return;
}
server_addr.sin_family = AF_INET;
server_addr.sin_port = htons(port);
server_addr.sin_addr = *((struct in_addr *)host->h_addr);
rt_memset(&(server_addr.sin_zero), 0, sizeof(server_addr.sin_zero));
if (connect(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)) == -1)
{
printf("Connect fail!\n");
closesocket(sock);
rt_free(recv_data);
return;
}
else
{
printf("Connect successful\n");
}
while (1)
{
bytes_received = recv(sock, recv_data, 1024 - 1, 0);
if (bytes_received < 0)
{
closesocket(sock);
printf("\nreceived error,close the socket.\r\n");
rt_free(recv_data);
break;
}
else if (bytes_received == 0)
{
closesocket(sock);
printf("\nreceived error,close the socket.\r\n");
rt_free(recv_data);
break;
}
recv_data[bytes_received] = '\0';
if (strncmp(recv_data, "q", 1) == 0 || strncmp(recv_data, "Q", 1) == 0)
{
closesocket(sock);
printf("\n got a 'q' or 'Q',close the socket.\r\n");
rt_free(recv_data);
break;
}
else
{
printf("\nReceived data = %s ", recv_data);
}
ret = send(sock, send_data, strlen(send_data), 0);
if (ret < 0)
{
closesocket(sock);
printf("\nsend error,close the socket.\r\n");
rt_free(recv_data);
break;
}
else if (ret == 0)
{
printf("\n Send warning,send function return 0.\r\n");
}
}
return;
}
MSH_CMD_EXPORT(rw007_test, a tcp client sample);
#endif
@@ -0,0 +1,239 @@
menu "Board Drivers Config"
config BSP_USING_UART_HS
bool "Enable High Speed UART"
default y
menu "General Purpose UARTs"
menuconfig BSP_USING_UART1
bool "Enable UART1"
default n
if BSP_USING_UART1
config BSP_UART1_TXD_PIN
int "uart1 TXD pin number"
default 20
config BSP_UART1_RXD_PIN
int "uart1 RXD pin number"
default 21
config BSP_UART1_RTS_PIN
int "uart1 RTS pin number (-1 for not used)"
default -1
config BSP_UART1_CTS_PIN
int "uart1 CTS pin number (-1 for not used)"
default -1
endif
menuconfig BSP_USING_UART2
bool "Enable UART2"
default n
if BSP_USING_UART2
config BSP_UART2_TXD_PIN
int "uart2 TXD pin number"
default 28
config BSP_UART2_RXD_PIN
int "uart2 RXD pin number"
default 27
config BSP_UART2_RTS_PIN
int "uart2 RTS pin number (-1 for not used)"
default -1
config BSP_UART2_CTS_PIN
int "uart2 CTS pin number (-1 for not used)"
default -1
endif
menuconfig BSP_USING_UART3
bool "Enable UART3"
default n
if BSP_USING_UART3
config BSP_UART3_TXD_PIN
int "uart3 TXD pin number"
default 22
config BSP_UART3_RXD_PIN
int "uart3 RXD pin number"
default 23
config BSP_UART3_RTS_PIN
int "uart3 RTS pin number (-1 for not used)"
default -1
config BSP_UART3_CTS_PIN
int "uart3 CTS pin number (-1 for not used)"
default -1
endif
endmenu
config BSP_USING_I2C1
bool "Enable I2C1 (GPIO0/1)"
select RT_USING_I2C
default n
menuconfig BSP_USING_SPI1
bool "Enable SPI1"
select RT_USING_SPI
default n
if BSP_USING_SPI1
config BSP_USING_SPI1_AS_QSPI
bool
default n
config BSP_SPI1_CLK_PIN
int "spi1 clk pin number"
default 27
config BSP_SPI1_D0_PIN
int "spi1 d0 pin number"
default 28
config BSP_SPI1_D1_PIN
int "spi1 d1 pin number"
default 26
if BSP_USING_SPI1_AS_QSPI
config BSP_SPI1_D2_PIN
int "spi1 d2 pin number"
default 32
config BSP_SPI1_D3_PIN
int "spi1 d3 pin number"
default 33
endif
menuconfig BSP_SPI1_USING_SS0
bool "SPI1 Enable SS0(spi10 dev)"
default n
if BSP_SPI1_USING_SS0
config BSP_SPI1_SS0_PIN
int "spi1 ss0 pin number"
default 29
endif
menuconfig BSP_SPI1_USING_SS1
bool "SPI1 Enable SS1(spi11 dev)"
default n
if BSP_SPI1_USING_SS1
config BSP_SPI1_SS1_PIN
int "spi1 ss1 pin number"
default 8
endif
menuconfig BSP_SPI1_USING_SS2
bool "SPI1 Enable SS2(spi12 dev)"
default n
if BSP_SPI1_USING_SS2
config BSP_SPI1_SS2_PIN
int "spi1 ss2 pin number"
default 26
endif
menuconfig BSP_SPI1_USING_SS3
bool "SPI1 Enable SS3(spi13 dev)"
default n
if BSP_SPI1_USING_SS3
config BSP_SPI1_SS3_PIN
int "spi1 ss3 pin number"
default 27
endif
endif
menuconfig BSP_USING_LCD
bool "Enable LCD on SPI0"
default n
if BSP_USING_LCD
config BSP_LCD_CS_PIN
int "CS pin number of 8080 interface"
default 36
config BSP_LCD_WR_PIN
int "WR pin number of 8080 interface"
default 39
config BSP_LCD_DC_PIN
int "DC pin number of 8080 interface"
default 38
config BSP_LCD_RST_PIN
int "RESET pin number of 8080 interface (-1 for not used)"
default 37
config BSP_LCD_BACKLIGHT_PIN
int "Backlight control pin number (-1 for not used)"
default -1
choice
prompt "backlight active polarity"
default BSP_LCD_BACKLIGHT_ACTIVE_LOW
config BSP_LCD_BACKLIGHT_ACTIVE_LOW
bool "lcd backlight on low level"
config BSP_LCD_BACKLIGHT_ACTIVE_HIGH
bool "lcd_backlight on high level"
endchoice
config BSP_LCD_CLK_FREQ
int "Lcd max clk frequency"
default 15000000
choice
prompt "lcd scan direction"
default BSP_BOARD_KD233
config BSP_BOARD_KD233
bool "board_kd233 lcd scan: DIR_YX_RLUD"
config BSP_BOARD_K210_OPENMV_TEST
bool "board_k210_openmv lcd scan: DIR_YX_LRUD"
config BSP_BOARD_USER
bool "board_user: user defined."
endchoice
config BSP_LCD_X_MAX
int "LCD Height"
default 240
config BSP_LCD_Y_MAX
int "LCD Width"
default 320
endif
menuconfig BSP_USING_SDCARD
bool "Enable SDCARD (spi1(ss0))"
select BSP_USING_SPI1
select BSP_SPI1_USING_SS0
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
select RT_USING_SPI_MSD
default n
menuconfig BSP_USING_DVP
bool "Enable DVP(camera)"
default n
if BSP_USING_DVP
comment "The default pin assignment is based on the Maix Duino K210 development board"
config BSP_DVP_SCCB_SDA_PIN
int "SCCB SDA pin number for camera"
default 40
config BSP_DVP_SCCB_SCLK_PIN
int "SCCB SCLK pin number for camera"
default 41
config BSP_DVP_CMOS_RST_PIN
int "CMOS RST pin number for camera"
default 42
config BSP_DVP_CMOS_VSYNC_PIN
int "CMOS VSYNC pin number for camera"
default 43
config BSP_DVP_CMOS_PWDN_PIN
int "CMOS PWDN pin number for camera"
default 44
config BSP_DVP_CMOS_XCLK_PIN
int "CMOS XCLK pin number for camera"
default 46
config BSP_DVP_CMOS_PCLK_PIN
int "CMOS PCLK pin number for camera"
default 47
config BSP_DVP_CMOS_HREF_PIN
int "CMOS HREF pin number for camera"
default 45
endif
if PKG_USING_RW007
config RW007_SPIDEV_NAME
string "the SPIDEV rw007 driver on"
default "spi11"
config RW007_INT_BUSY_PIN
int "rw007 int pin for rw007"
default 7
config RW007_RST_PIN
int "rw007 rst pin for rw007"
default 6
endif
endmenu
@@ -0,0 +1,50 @@
import os
import rtconfig
from building import *
cwd = GetCurrentDir()
drv_path = cwd+"/../../../rt-thread/bsp/k210/driver/"
src = [
'board.c',
'heap.c',
drv_path + 'drv_uart.c',
'drv_interrupt.c',
'drv_io_config.c',
'dmalock.c'
]
CPPPATH = [cwd,drv_path]
if GetDepend('RT_USING_PIN'):
src += ['drv_gpio.c']
if GetDepend('RT_USING_HWTIMER'):
src += [drv_path + 'drv_hw_timer.c']
if GetDepend('RT_USING_I2C'):
src += [drv_path + 'drv_i2c.c']
if GetDepend('RT_USING_SPI'):
src += ['drv_spi.c']
if GetDepend('RT_USING_PWM'):
src += [drv_path + 'drv_pwm.c']
if GetDepend('RT_USING_WDT'):
src += [drv_path + 'drv_wdt.c']
if GetDepend('BSP_USING_SDCARD'):
src += ['sdcard_port.c']
if GetDepend('BSP_USING_DVP'):
src += ['drv_dvp.c']
if GetDepend('BSP_USING_LCD'):
src += ['drv_lcd.c']
src += ['drv_mpylcd.c']
if GetDepend('PKG_USING_RW007'):
src += ['rw007_port.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
@@ -0,0 +1,144 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "tick.h"
#include "drv_uart.h"
#include "encoding.h"
#include "fpioa.h"
#include "dmac.h"
#include "dmalock.h"
void init_bss(void)
{
unsigned int *dst;
dst = &__bss_start;
while (dst < &__bss_end)
{
*dst++ = 0;
}
}
void primary_cpu_entry(void)
{
extern void entry(void);
/* disable global interrupt */
init_bss();
rt_hw_interrupt_disable();
entry();
}
#include <clint.h>
#include <sysctl.h>
int freq(void)
{
rt_uint64_t value = 0;
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL0);
rt_kprintf("PLL0: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL1);
rt_kprintf("PLL1: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL2);
rt_kprintf("PLL2: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU);
rt_kprintf("CPU : %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB0);
rt_kprintf("APB0: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB1);
rt_kprintf("APB1: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB2);
rt_kprintf("APB2: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_HCLK);
rt_kprintf("HCLK: %d\n", value);
value = clint_get_time();
rt_kprintf("mtime: %d\n", value);
return 0;
}
MSH_CMD_EXPORT(freq, show freq info);
#ifdef RT_USING_SMP
extern int rt_hw_clint_ipi_enable(void);
#endif
extern int io_config_init(void);
void rt_hw_board_init(void)
{
sysctl_pll_set_freq(SYSCTL_PLL0, 800000000UL);
sysctl_pll_set_freq(SYSCTL_PLL1, 400000000UL);
sysctl_pll_set_freq(SYSCTL_PLL2, 45158400UL);
sysctl_clock_set_threshold(SYSCTL_THRESHOLD_APB1, 2);
/* Init FPIOA */
fpioa_init();
io_config_init();
/* Dmac init */
dmac_init();
dmalock_init();
/* initalize interrupt */
rt_hw_interrupt_init();
/* initialize hardware interrupt */
rt_hw_uart_init();
rt_hw_tick_init();
#ifdef RT_USING_SMP
rt_hw_clint_ipi_enable();
#endif
#ifdef RT_USING_CONSOLE
/* set console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif /* RT_USING_CONSOLE */
#ifdef RT_USING_HEAP
rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t) RT_HW_HEAP_BEGIN, (rt_ubase_t) RT_HW_HEAP_END);
/* initialize memory system */
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}
void rt_hw_cpu_reset(void)
{
sysctl->soft_reset.soft_reset = 1;
while(1);
}
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
/**
* This function will delay for some us.
*
* @param us the delay time of us
*/
void rt_hw_us_delay(rt_uint32_t usec)
{
rt_uint32_t cycle = read_cycle();
rt_uint32_t nop_all = usec * sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / 1000000UL;
while (1)
{
if(read_cycle() - cycle >= nop_all)
break;
}
}
@@ -0,0 +1,26 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
*/
#ifndef BOARD_H__
#define BOARD_H__
#include "fpioa.h"
#include "platform.h"
#include <rtconfig.h>
extern unsigned int __bss_start;
extern unsigned int __bss_end;
#define RT_HW_HEAP_BEGIN (void*)&__bss_end
#define RT_HW_HEAP_END (void*)(0x80000000 + 6 * 1024 * 1024)
void rt_hw_board_init(void);
#endif
@@ -0,0 +1,90 @@
/* Copyright Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <rtthread.h>
#include "dmalock.h"
struct dmac_host
{
struct rt_semaphore sem;
struct rt_mutex mutex;
uint8_t channel_used[DMAC_CHANNEL_COUNT];
char *channel_name[DMAC_CHANNEL_COUNT];
};
static struct dmac_host _dmac_host;
void dmalock_init(void)
{
rt_sem_init(&_dmac_host.sem, "dma_sem", DMAC_CHANNEL_COUNT, RT_IPC_FLAG_FIFO);
rt_mutex_init(&_dmac_host.mutex, "dma_mutex", RT_IPC_FLAG_FIFO);
for (int i = 0; i < DMAC_CHANNEL_COUNT; i++)
{
_dmac_host.channel_used[i] = 0;
_dmac_host.channel_name[i] = NULL;
}
}
int _dmalock_sync_take(dmac_channel_number_t *chn, int timeout_ms, const char *name)
{
rt_err_t result;
*chn = DMAC_CHANNEL_MAX;
result = rt_sem_take(&_dmac_host.sem, timeout_ms);
if (result == RT_EOK)
{
rt_mutex_take(&_dmac_host.mutex, RT_WAITING_FOREVER);
for (int i = 0; i < DMAC_CHANNEL_COUNT; i++)
{
if (_dmac_host.channel_used[i] == 0)
{
_dmac_host.channel_used[i] = 1;
_dmac_host.channel_name[i] = name;
*chn = i;
break;
}
}
rt_mutex_release(&_dmac_host.mutex);
}
return result;
}
void dmalock_release(dmac_channel_number_t chn)
{
if (chn >= DMAC_CHANNEL_MAX)
return;
_dmac_host.channel_name[chn] = NULL;
_dmac_host.channel_used[chn] = 0;
rt_sem_release(&_dmac_host.sem);
}
static void dma_ch_info(int argc, char **argv)
{
uint32_t cnt = 0;
for (int i = 0; i < DMAC_CHANNEL_COUNT; i++)
{
if (_dmac_host.channel_used[i] != 0)
{
rt_kprintf("dma_ch%d is using by func [%s]\n", i, _dmac_host.channel_name[i]);
cnt++;
}
}
if(cnt == 0)
rt_kprintf(" no dma_ch is using.\n");
}
MSH_CMD_EXPORT(dma_ch_info, list dma channel informationn.);
@@ -0,0 +1,14 @@
#ifndef __DMALOCK_H
#define __DMALOCK_H
#include <stdint.h>
#include <rtdef.h>
#include <dmac.h>
#define dmalock_sync_take(x,y) _dmalock_sync_take(x, y, __func__)
void dmalock_init(void);
int _dmalock_sync_take(dmac_channel_number_t *chn, int timeout_ms, const char *name);
void dmalock_release(dmac_channel_number_t chn);
#endif
@@ -0,0 +1,167 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-27 tianchunyu the first version
*/
#include <rtthread.h>
#include <stdio.h>
#ifdef BSP_USING_DVP
#include <drv_dvp.h>
#define DRV_DEBUG
#define LOG_TAG "drv.dvp"
#define DBG_LVL DBG_LOG
#include <rtdbg.h>
static struct kendryte_dvp rt_dvp = {0};
static void (*dvp_irq_callback)(void) = NULL;
/*
the camera starts transfering photos
*/
static int on_irq_dvp(void* ctx)
{
if (dvp_get_interrupt(DVP_STS_FRAME_FINISH))
{
rt_dvp_stop();
dvp_clear_interrupt(DVP_STS_FRAME_FINISH);
(*dvp_irq_callback)();
}
return 0;
}
void rt_dvp_start(uint32_t pData, uint32_t Length)
{
dvp_set_display_addr(pData);
dvp_config_interrupt(DVP_CFG_FINISH_INT_ENABLE, 1);
dvp_start_convert();
}
/*
the camera stops transfering photos
*/
void rt_dvp_stop(void)
{
dvp_config_interrupt(DVP_CFG_FINISH_INT_ENABLE, 0);
}
static rt_err_t rt_dvp_init(rt_device_t dev)
{
//sysctl_pll_set_freq(SYSCTL_PLL2, 45158400UL);
RT_ASSERT(dev != RT_NULL);
rt_err_t result = RT_EOK;
/* Init DVP IO map and function settings io pin serial number depends on schematic diagram
initialize io in io_config_init function*/
/*ov2640 dvp interface initialize*/
dvp_init(8);
dvp_set_xclk_rate(24000000);
dvp_enable_burst();
dvp_set_output_enable(0, 1);
dvp_set_output_enable(1, 1);
dvp_set_image_format(DVP_CFG_RGB_FORMAT);////////////////
dvp_set_image_size(320, 240); // default
dvp_config_interrupt(DVP_CFG_FINISH_INT_ENABLE, 0);
dvp_disable_auto();
plic_set_priority(IRQN_DVP_INTERRUPT, 1);
plic_irq_register(IRQN_DVP_INTERRUPT, on_irq_dvp, NULL);
plic_irq_enable(IRQN_DVP_INTERRUPT);
dvp_clear_interrupt(DVP_STS_FRAME_FINISH);
LOG_I("dvp initialize success");
return result;
}
static rt_err_t rt_dvp_open(rt_device_t dev, rt_uint16_t oflag)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_err_t rt_dvp_close(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_err_t rt_dvp_control(rt_device_t dev, int cmd, void *args)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_size_t rt_dvp_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_size_t rt_dvp_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
rt_err_t rt_set_irq_dvp_callback_hander(void (*p)(void))
{
if(NULL == p)
{
LOG_E("set irq dcmi callback hander is NULL");
return RT_ERROR;
}
dvp_irq_callback = p;
return RT_EOK;
}
int kendryte_dvp_init(void)
{
int ret = 0;
rt_device_t dvp_dev = RT_NULL;
rt_dvp.dev.parent.type = RT_Device_Class_Miscellaneous;
rt_dvp.dev.parent.init = rt_dvp_init;
rt_dvp.dev.parent.open = rt_dvp_open;
rt_dvp.dev.parent.close = rt_dvp_close;
rt_dvp.dev.parent.read = rt_dvp_read;
rt_dvp.dev.parent.write = rt_dvp_write;
rt_dvp.dev.parent.control = rt_dvp_control;
rt_dvp.dev.parent.user_data = RT_NULL;
ret = rt_device_register(&rt_dvp.dev.parent, "dvp", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
if(ret != RT_EOK)
{
LOG_E("dvp register fail!!\n\r");
return -RT_ERROR;
}
LOG_I("dvp register successfully");
dvp_dev = rt_device_find("dvp");
if (dvp_dev == RT_NULL)
{
LOG_E("can't find dvp device!");
return RT_ERROR;
}
ret = rt_device_open(dvp_dev, RT_DEVICE_FLAG_RDWR);
if(ret != RT_EOK)
{
LOG_E("can't open dvp device!");
return RT_ERROR;
}
LOG_I("dvp open successfully");
return RT_EOK;
}
INIT_BOARD_EXPORT(kendryte_dvp_init);
#endif
@@ -0,0 +1,46 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-27 tianchunyu the first version
*/
#ifndef __DRV_DVP_H__
#define __DRV_DVP_H__
#include <dvp.h>
#include <fpioa.h>
#include <sysctl.h>
#include <plic.h>
#include <sysctl.h>
#ifdef __cplusplus
extern "C" {
#endif
struct rt_dvp_device
{
struct rt_device parent;
};
struct kendryte_dvp
{
struct rt_dvp_device dev;
};
extern void rt_dvp_start(uint32_t pData, uint32_t Length);
extern void rt_dvp_stop(void);
extern rt_err_t rt_set_irq_dvp_callback_hander(void (*p)(void));
#ifdef __cplusplus
}
#endif
#endif
@@ -0,0 +1,267 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <fpioa.h>
#include <gpiohs.h>
#include "drv_gpio.h"
#include "drv_io_config.h"
#include <plic.h>
#include <rthw.h>
#include <utils.h>
#include <string.h>
#define DBG_ENABLE
#define DBG_TAG "PIN"
#define DBG_LVL DBG_WARNING
#define DBG_COLOR
#include <rtdbg.h>
#define FUNC_GPIOHS(n) (FUNC_GPIOHS0 + n)
static short pin_alloc_table[FPIOA_NUM_IO];
static uint32_t free_pin = 0;
static int alloc_pin_channel(rt_base_t pin_index)
{
if(free_pin == 32)
{
LOG_E("no free gpiohs channel to alloc");
return -1;
}
if(pin_alloc_table[pin_index] != -1)
{
LOG_W("already alloc gpiohs channel for pin %d", pin_index);
return pin_alloc_table[pin_index];
}
pin_alloc_table[pin_index] = free_pin;
free_pin++;
fpioa_set_function(pin_index, FUNC_GPIOHS(pin_alloc_table[pin_index]));
return pin_alloc_table[pin_index];
}
int get_pin_channel(rt_base_t pin_index)
{
return pin_alloc_table[pin_index];
}
static void free_pin_channel(rt_base_t pin_index)
{
if(pin_alloc_table[pin_index] == -1)
{
LOG_W("free error:not alloc gpiohs channel for pin %d", pin_index);
return;
}
pin_alloc_table[pin_index] = -1;
free_pin--;
}
static void drv_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
{
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
pin_channel = alloc_pin_channel(pin);
if(pin_channel == -1)
{
return;
}
}
switch (mode)
{
case PIN_MODE_OUTPUT:
gpiohs_set_drive_mode(pin_channel, GPIO_DM_OUTPUT);
break;
case PIN_MODE_INPUT:
gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT);
break;
case PIN_MODE_INPUT_PULLUP:
gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT_PULL_UP);
break;
case PIN_MODE_INPUT_PULLDOWN:
gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT_PULL_DOWN);
break;
default:
LOG_E("Not support mode %d", mode);
break;
}
}
static void drv_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
{
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return;
}
gpiohs_set_pin(pin_channel, value == PIN_HIGH ? GPIO_PV_HIGH : GPIO_PV_LOW);
}
static int drv_pin_read(struct rt_device *device, rt_base_t pin)
{
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return -1;
}
return gpiohs_get_pin(pin_channel) == GPIO_PV_HIGH ? PIN_HIGH : PIN_LOW;
}
static struct
{
void (*hdr)(void *args);
void* args;
gpio_pin_edge_t edge;
} irq_table[32];
static void pin_irq(int vector, void *param)
{
int pin_channel = vector - IRQN_GPIOHS0_INTERRUPT;
if(irq_table[pin_channel].edge & GPIO_PE_FALLING)
{
set_gpio_bit(gpiohs->fall_ie.u32, pin_channel, 0);
set_gpio_bit(gpiohs->fall_ip.u32, pin_channel, 1);
set_gpio_bit(gpiohs->fall_ie.u32, pin_channel, 1);
}
if(irq_table[pin_channel].edge & GPIO_PE_RISING)
{
set_gpio_bit(gpiohs->rise_ie.u32, pin_channel, 0);
set_gpio_bit(gpiohs->rise_ip.u32, pin_channel, 1);
set_gpio_bit(gpiohs->rise_ie.u32, pin_channel, 1);
}
if(irq_table[pin_channel].edge & GPIO_PE_LOW)
{
set_gpio_bit(gpiohs->low_ie.u32, pin_channel, 0);
set_gpio_bit(gpiohs->low_ip.u32, pin_channel, 1);
set_gpio_bit(gpiohs->low_ie.u32, pin_channel, 1);
}
if(irq_table[pin_channel].edge & GPIO_PE_HIGH)
{
set_gpio_bit(gpiohs->high_ie.u32, pin_channel, 0);
set_gpio_bit(gpiohs->high_ip.u32, pin_channel, 1);
set_gpio_bit(gpiohs->high_ie.u32, pin_channel, 1);
}
if(irq_table[pin_channel].hdr)
{
irq_table[pin_channel].hdr(irq_table[pin_channel].args);
}
}
static rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
int pin_channel = get_pin_channel(pin);
char irq_name[10];
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return -RT_ERROR;
}
irq_table[pin_channel].hdr = hdr;
irq_table[pin_channel].args = args;
switch (mode)
{
case PIN_IRQ_MODE_RISING:
irq_table[pin_channel].edge = GPIO_PE_RISING;
break;
case PIN_IRQ_MODE_FALLING:
irq_table[pin_channel].edge = GPIO_PE_FALLING;
break;
case PIN_IRQ_MODE_RISING_FALLING:
irq_table[pin_channel].edge = GPIO_PE_BOTH;
break;
case PIN_IRQ_MODE_HIGH_LEVEL:
irq_table[pin_channel].edge = GPIO_PE_LOW;
break;
case PIN_IRQ_MODE_LOW_LEVEL:
irq_table[pin_channel].edge = GPIO_PE_HIGH;
break;
default:
break;
}
gpiohs_set_pin_edge(pin_channel, irq_table[pin_channel].edge);
rt_snprintf(irq_name, sizeof irq_name, "pin%d", pin);
rt_hw_interrupt_install(IRQN_GPIOHS0_INTERRUPT + pin_channel, pin_irq, RT_NULL, irq_name);
return RT_EOK;
}
static rt_err_t drv_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{
rt_err_t ret = RT_EOK;
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return -RT_ERROR;
}
irq_table[pin_channel].hdr = RT_NULL;
irq_table[pin_channel].args = RT_NULL;
return ret;
}
static rt_err_t drv_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
{
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return -RT_ERROR;
}
if(enabled)
{
rt_hw_interrupt_umask(IRQN_GPIOHS0_INTERRUPT + pin_channel);
}
else
{
rt_hw_interrupt_mask(IRQN_GPIOHS0_INTERRUPT + pin_channel);
}
return RT_EOK;
}
const static struct rt_pin_ops drv_pin_ops =
{
drv_pin_mode,
drv_pin_write,
drv_pin_read,
drv_pin_attach_irq,
drv_pin_detach_irq,
drv_pin_irq_enable
};
int rt_hw_pin_init(void)
{
rt_err_t ret = RT_EOK;
memset(pin_alloc_table, 0xff, sizeof pin_alloc_table);
free_pin = GPIO_ALLOC_START;
ret = rt_device_pin_register("pin", &drv_pin_ops, RT_NULL);
return ret;
}
INIT_BOARD_EXPORT(rt_hw_pin_init);
@@ -0,0 +1,16 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#ifndef DRV_GPIO_H__
#define DRV_GPIO_H__
int rt_hw_pin_init(void);
#endif
@@ -0,0 +1,27 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#include <plic.h>
void plic_irq_handle(plic_irq_t irq)
{
plic_instance_t (*plic_instance)[IRQN_MAX] = plic_get_instance();
if (plic_instance[0][irq].callback)
{
plic_instance[0][irq].callback(
plic_instance[0][irq].ctx);
}
else if (plic_instance[1][irq].callback)
{
plic_instance[1][irq].callback(
plic_instance[1][irq].ctx);
}
}
@@ -0,0 +1,219 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#include <rtthread.h>
#include <fpioa.h>
#include <drv_io_config.h>
#include <sysctl.h>
#define HS_GPIO(n) (FUNC_GPIOHS0 + n)
#define IOCONFIG(pin,func) {pin, func, #func}
static struct io_config
{
int io_num;
fpioa_function_t func;
const char * func_name;
} io_config[] =
{
#ifdef BSP_USING_LCD
IOCONFIG(BSP_LCD_CS_PIN, FUNC_SPI0_SS0), /* LCD CS PIN */
IOCONFIG(BSP_LCD_WR_PIN, FUNC_SPI0_SCLK), /* LCD WR PIN */
IOCONFIG(BSP_LCD_DC_PIN, HS_GPIO(LCD_DC_PIN)), /* LCD DC PIN */
#if BSP_LCD_RST_PIN >= 0
IOCONFIG(BSP_LCD_RST_PIN, HS_GPIO(LCD_RST_PIN)), /* LCD RESET PIN */
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
IOCONFIG(BSP_LCD_BACKLIGHT_PIN, HS_GPIO(LCD_BACKLIGHT_PIN)), /* LCD BACKLIGHT PIN */
#endif
#endif
#ifdef BSP_USING_DVP
IOCONFIG(BSP_DVP_SCCB_SDA_PIN, FUNC_SCCB_SDA),
IOCONFIG(BSP_DVP_SCCB_SCLK_PIN, FUNC_SCCB_SCLK),
IOCONFIG(BSP_DVP_CMOS_RST_PIN, FUNC_CMOS_RST),
IOCONFIG(BSP_DVP_CMOS_VSYNC_PIN, FUNC_CMOS_VSYNC),
IOCONFIG(BSP_DVP_CMOS_PWDN_PIN, FUNC_CMOS_PWDN),
IOCONFIG(BSP_DVP_CMOS_XCLK_PIN, FUNC_CMOS_XCLK),
IOCONFIG(BSP_DVP_CMOS_PCLK_PIN, FUNC_CMOS_PCLK),
IOCONFIG(BSP_DVP_CMOS_HREF_PIN, FUNC_CMOS_HREF),
#endif
#ifdef BSP_USING_SPI1
IOCONFIG(BSP_SPI1_CLK_PIN, FUNC_SPI1_SCLK),
IOCONFIG(BSP_SPI1_D0_PIN, FUNC_SPI1_D0),
IOCONFIG(BSP_SPI1_D1_PIN, FUNC_SPI1_D1),
#ifdef BSP_USING_SPI1_AS_QSPI
IOCONFIG(BSP_SPI1_D2_PIN, FUNC_SPI1_D2),
IOCONFIG(BSP_SPI1_D3_PIN, FUNC_SPI1_D3),
#endif
#ifdef BSP_SPI1_USING_SS0
IOCONFIG(BSP_SPI1_SS0_PIN, HS_GPIO(SPI1_CS0_PIN)),
#endif
#ifdef BSP_SPI1_USING_SS1
IOCONFIG(BSP_SPI1_SS1_PIN, HS_GPIO(SPI1_CS1_PIN)),
#endif
#ifdef BSP_SPI1_USING_SS2
IOCONFIG(BSP_SPI1_SS2_PIN, HS_GPIO(SPI1_CS2_PIN)),
#endif
#ifdef BSP_SPI1_USING_SS3
IOCONFIG(BSP_SPI1_SS3_PIN, HS_GPIO(SPI1_CS3_PIN)),
#endif
#endif
#ifdef BSP_USING_UART1
IOCONFIG(BSP_UART1_TXD_PIN, FUNC_UART1_TX),
IOCONFIG(BSP_UART1_RXD_PIN, FUNC_UART1_RX),
#if BSP_UART1_RTS_PIN >= 0
IOCONFIG(BSP_UART1_RTS_PIN, FUNC_UART1_RTS),
#endif
#if BSP_UART1_CTS_PIN >= 0
IOCONFIG(BSP_UART1_CTS_PIN, FUNC_UART1_CTS),
#endif
#endif
#ifdef BSP_USING_UART2
IOCONFIG(BSP_UART2_TXD_PIN, FUNC_UART2_TX),
IOCONFIG(BSP_UART2_RXD_PIN, FUNC_UART2_RX),
#if BSP_UART2_RTS_PIN >= 0
IOCONFIG(BSP_UART2_RTS_PIN, FUNC_UART2_RTS),
#endif
#if BSP_UART2_CTS_PIN >= 0
IOCONFIG(BSP_UART2_CTS_PIN, FUNC_UART2_CTS),
#endif
#endif
#ifdef BSP_USING_UART3
IOCONFIG(BSP_UART3_TXD_PIN, FUNC_UART3_TX),
IOCONFIG(BSP_UART3_RXD_PIN, FUNC_UART3_RX),
#if BSP_UART3_RTS_PIN >= 0
IOCONFIG(BSP_UART3_RTS_PIN, FUNC_UART3_RTS),
#endif
#if BSP_UART3_CTS_PIN >= 0
IOCONFIG(BSP_UART3_CTS_PIN, FUNC_UART3_CTS),
#endif
#endif
#ifdef BSP_USING_I2C0
IOCONFIG(BSP_I2C0_SCL_PIN, FUNC_I2C0_SCLK),
IOCONFIG(BSP_I2C0_SDA_PIN, FUNC_I2C0_SDA),
#endif
#ifdef BSP_USING_I2C1
IOCONFIG(BSP_I2C1_SCL_PIN, FUNC_I2C1_SCLK),
IOCONFIG(BSP_I2C1_SDA_PIN, FUNC_I2C1_SDA),
#endif
#ifdef BSP_USING_I2C2
IOCONFIG(BSP_I2C2_SCL_PIN, FUNC_I2C2_SCLK),
IOCONFIG(BSP_I2C2_SDA_PIN, FUNC_I2C2_SDA),
#endif
#ifdef BSP_USING_I2S0
IOCONFIG(BSP_I2S0_OUT_D1_PIN, FUNC_I2S0_OUT_D1),
IOCONFIG(BSP_I2S0_WS_PIN, FUNC_I2S0_WS),
IOCONFIG(BSP_I2S0_SCLK_PIN, FUNC_I2S0_SCLK),
#endif
#ifdef BSP_USING_I2S1
IOCONFIG(BSP_I2S1_IN_D0_PIN, FUNC_I2S1_IN_D0),
IOCONFIG(BSP_I2S1_WS_PIN, FUNC_I2S1_WS),
IOCONFIG(BSP_I2S1_SCLK_PIN, FUNC_I2S1_SCLK),
#endif
#ifdef BSP_USING_I2S2
IOCONFIG(BSP_I2S2_OUT_D1_PIN, FUNC_I2S2_OUT_D1),
IOCONFIG(BSP_I2S2_WS_PIN, FUNC_I2S2_WS),
IOCONFIG(BSP_I2S2_SCLK_PIN, FUNC_I2S2_SCLK),
#endif
#ifdef BSP_PWM_CHN0_ENABLE
IOCONFIG(BSP_PWM_CHN0_PIN, FUNC_TIMER2_TOGGLE1),
#endif
#ifdef BSP_PWM_CHN1_ENABLE
IOCONFIG(BSP_PWM_CHN1_PIN, FUNC_TIMER2_TOGGLE2),
#endif
#ifdef BSP_PWM_CHN2_ENABLE
IOCONFIG(BSP_PWM_CHN2_PIN, FUNC_TIMER2_TOGGLE3),
#endif
#ifdef BSP_PWM_CHN3_ENABLE
IOCONFIG(BSP_PWM_CHN3_PIN, FUNC_TIMER2_TOGGLE4),
#endif
};
static int print_io_config()
{
int i;
rt_kprintf("IO Configuration Table\n");
rt_kprintf("┌───────┬────────────────────────┐\n");
rt_kprintf("│Pin │Function │\n");
rt_kprintf("├───────┼────────────────────────┤\n");
for(i = 0; i < sizeof io_config / sizeof io_config[0]; i++)
{
rt_kprintf("│%-2d │%-24.24s│\n", io_config[i].io_num, io_config[i].func_name);
}
rt_kprintf("└───────┴────────────────────────┘\n");
return 0;
}
MSH_CMD_EXPORT_ALIAS(print_io_config, io, print io config);
int io_config_init(void)
{
int count = sizeof(io_config) / sizeof(io_config[0]);
int i;
/* IO GroupA Power Supply Setting */
#if defined(BSP_GROUPA_POWER_SUPPLY_3V3)
sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V33);
#else
sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V18);
#endif
/* IO GroupB Power Supply Setting */
#if defined(BSP_GROUPB_POWER_SUPPLY_3V3)
sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK5, SYSCTL_POWER_V33);
#else
sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK5, SYSCTL_POWER_V18);
#endif
/* IO GroupC Power Supply Setting */
#if defined(BSP_GROUPC_POWER_SUPPLY_3V3)
sysctl_set_power_mode(SYSCTL_POWER_BANK6, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK7, SYSCTL_POWER_V33);
#else
sysctl_set_power_mode(SYSCTL_POWER_BANK6, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK7, SYSCTL_POWER_V18);
#endif
for(i = 0; i < count; i++)
{
fpioa_set_function(io_config[i].io_num, io_config[i].func);
}
#if defined(BSP_USING_DVP) || defined(BSP_USING_LCD)
sysctl_set_spi0_dvp_data(1);
sysctl_clock_enable(SYSCTL_CLOCK_AI);
#endif
}
int io_config_used(int io_num)
{
int count = sizeof(io_config) / sizeof(io_config[0]);
int i;
for(i = 0; i < count; i++)
{
if (io_config[i].io_num == io_num)
break;
}
return (i < count);
}
@@ -0,0 +1,49 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#ifndef __DRV_IO_CONFIG_H__
#define __DRV_IO_CONFIG_H__
#include <rtconfig.h>
enum HS_GPIO_CONFIG
{
#ifdef BSP_USING_LCD
LCD_DC_PIN = 0, /* LCD DC PIN */
#if BSP_LCD_RST_PIN >= 0
LCD_RST_PIN,
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
LCD_BACKLIGHT_PIN,
#endif
#endif
#ifdef BSP_SPI1_USING_SS0
SPI1_CS0_PIN,
#endif
#ifdef BSP_SPI1_USING_SS1
SPI1_CS1_PIN,
#endif
#ifdef BSP_SPI1_USING_SS2
SPI1_CS2_PIN,
#endif
#ifdef BSP_SPI1_USING_SS3
SPI1_CS3_PIN,
#endif
#ifdef BSP_USING_BRIDGE
SPI2_INT_PIN,
SPI2_READY_PIN,
#endif
GPIO_ALLOC_START /* index of gpio driver start */
};
extern int io_config_init(void);
#endif
@@ -0,0 +1,550 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-12 ZYH first version
*/
#include <rtthread.h>
#ifdef BSP_USING_LCD
#include <drv_lcd.h>
#define DBG_TAG "LCD"
#define DBG_LVL DBG_WARNING
#include <rtdbg.h>
#define NO_OPERATION 0x00
#define SOFTWARE_RESET 0x01
#define READ_ID 0x04
#define READ_STATUS 0x09
#define READ_POWER_MODE 0x0A
#define READ_MADCTL 0x0B
#define READ_PIXEL_FORMAT 0x0C
#define READ_IMAGE_FORMAT 0x0D
#define READ_SIGNAL_MODE 0x0E
#define READ_SELT_DIAG_RESULT 0x0F
#define SLEEP_ON 0x10
#define SLEEP_OFF 0x11
#define PARTIAL_DISPALY_ON 0x12
#define NORMAL_DISPALY_ON 0x13
#define INVERSION_DISPALY_OFF 0x20
#define INVERSION_DISPALY_ON 0x21
#define GAMMA_SET 0x26
#define DISPALY_OFF 0x28
#define DISPALY_ON 0x29
#define HORIZONTAL_ADDRESS_SET 0x2A
#define VERTICAL_ADDRESS_SET 0x2B
#define MEMORY_WRITE 0x2C
#define COLOR_SET 0x2D
#define MEMORY_READ 0x2E
#define PARTIAL_AREA 0x30
#define VERTICAL_SCROL_DEFINE 0x33
#define TEAR_EFFECT_LINE_OFF 0x34
#define TEAR_EFFECT_LINE_ON 0x35
#define MEMORY_ACCESS_CTL 0x36
#define VERTICAL_SCROL_S_ADD 0x37
#define IDLE_MODE_OFF 0x38
#define IDLE_MODE_ON 0x39
#define PIXEL_FORMAT_SET 0x3A
#define WRITE_MEMORY_CONTINUE 0x3C
#define READ_MEMORY_CONTINUE 0x3E
#define SET_TEAR_SCANLINE 0x44
#define GET_SCANLINE 0x45
#define WRITE_BRIGHTNESS 0x51
#define READ_BRIGHTNESS 0x52
#define WRITE_CTRL_DISPALY 0x53
#define READ_CTRL_DISPALY 0x54
#define WRITE_BRIGHTNESS_CTL 0x55
#define READ_BRIGHTNESS_CTL 0x56
#define WRITE_MIN_BRIGHTNESS 0x5E
#define READ_MIN_BRIGHTNESS 0x5F
#define READ_ID1 0xDA
#define READ_ID2 0xDB
#define READ_ID3 0xDC
#define RGB_IF_SIGNAL_CTL 0xB0
#define NORMAL_FRAME_CTL 0xB1
#define IDLE_FRAME_CTL 0xB2
#define PARTIAL_FRAME_CTL 0xB3
#define INVERSION_CTL 0xB4
#define BLANK_PORCH_CTL 0xB5
#define DISPALY_FUNCTION_CTL 0xB6
#define ENTRY_MODE_SET 0xB7
#define BACKLIGHT_CTL1 0xB8
#define BACKLIGHT_CTL2 0xB9
#define BACKLIGHT_CTL3 0xBA
#define BACKLIGHT_CTL4 0xBB
#define BACKLIGHT_CTL5 0xBC
#define BACKLIGHT_CTL7 0xBE
#define BACKLIGHT_CTL8 0xBF
#define POWER_CTL1 0xC0
#define POWER_CTL2 0xC1
#define VCOM_CTL1 0xC5
#define VCOM_CTL2 0xC7
#define NV_MEMORY_WRITE 0xD0
#define NV_MEMORY_PROTECT_KEY 0xD1
#define NV_MEMORY_STATUS_READ 0xD2
#define READ_ID4 0xD3
#define POSITIVE_GAMMA_CORRECT 0xE0
#define NEGATIVE_GAMMA_CORRECT 0xE1
#define DIGITAL_GAMMA_CTL1 0xE2
#define DIGITAL_GAMMA_CTL2 0xE3
#define INTERFACE_CTL 0xF6
#define LCD_SPI_CHANNEL SPI_DEVICE_0
#define LCD_SPI_CHIP_SELECT SPI_CHIP_SELECT_0
#if defined(BSP_BOARD_K210_OPENMV_TEST)
#define LCD_SCAN_DIR DIR_YX_LRUD
#elif defined(BSP_BOARD_KD233)
#define LCD_SCAN_DIR (DIR_YX_RLUD | 0x08)
#elif defined(BSP_BOARD_USER)
/*user define.*/
#define LCD_SCAN_DIR DIR_YX_RLDU
#endif
static struct lcd_8080_device _lcddev;
static void drv_lcd_cmd(lcd_8080_device_t lcd, rt_uint8_t cmd)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_LOW);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
spi_init_non_standard(lcd->spi_channel, 8 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, &cmd, 1, SPI_TRANS_CHAR);
}
static void drv_lcd_data_byte(lcd_8080_device_t lcd, rt_uint8_t *data_buf, rt_uint32_t length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
spi_init_non_standard(lcd->spi_channel, 8 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_CHAR);
}
void drv_lcd_data_half_word(lcd_8080_device_t lcd, rt_uint16_t *data_buf, rt_uint32_t length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 16, 0);
spi_init_non_standard(lcd->spi_channel, 16 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_SHORT);
}
void drv_lcd_data_word(lcd_8080_device_t lcd, rt_uint32_t *data_buf, rt_uint32_t length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0);
spi_init_non_standard(lcd->spi_channel, 0 /*instrction length*/, 32 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_INT);
}
static void drv_lcd_hw_init(lcd_8080_device_t lcd)
{
#if BSP_LCD_RST_PIN >= 0
{
gpiohs_set_drive_mode(lcd->rst_pin, GPIO_DM_OUTPUT);
gpiohs_set_pin(lcd->rst_pin, GPIO_PV_LOW);
rt_thread_mdelay(20);
gpiohs_set_pin(lcd->rst_pin, GPIO_PV_HIGH);
rt_thread_mdelay(20);
}
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
{
gpiohs_set_drive_mode(lcd->backlight_pin, GPIO_DM_OUTPUT);
#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH);
#else
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#endif
}
#endif
gpiohs_set_drive_mode(lcd->dc_pin, GPIO_DM_OUTPUT);
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
spi_set_clk_rate(lcd->spi_channel, BSP_LCD_CLK_FREQ);
}
static void drv_lcd_set_direction(lcd_8080_device_t lcd, lcd_dir_t dir)
{
if (dir & DIR_XY_MASK)
{
lcd->lcd_info.width = BSP_LCD_Y_MAX;
lcd->lcd_info.height = BSP_LCD_X_MAX;
}
else
{
lcd->lcd_info.width = BSP_LCD_X_MAX;
lcd->lcd_info.height = BSP_LCD_Y_MAX;
}
rt_kprintf("lcd witdth %d,height %d \n",lcd->lcd_info.width,lcd->lcd_info.height);
drv_lcd_cmd(lcd, MEMORY_ACCESS_CTL);
drv_lcd_data_byte(lcd, (rt_uint8_t *)&dir, 1);
}
void drv_lcd_set_area(lcd_8080_device_t lcd, rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2)
{
rt_uint8_t data[4] = {0};
data[0] = (rt_uint8_t)(x1 >> 8);
data[1] = (rt_uint8_t)(x1);
data[2] = (rt_uint8_t)(x2 >> 8);
data[3] = (rt_uint8_t)(x2);
drv_lcd_cmd(lcd, HORIZONTAL_ADDRESS_SET);
drv_lcd_data_byte(lcd, data, 4);
data[0] = (rt_uint8_t)(y1 >> 8);
data[1] = (rt_uint8_t)(y1);
data[2] = (rt_uint8_t)(y2 >> 8);
data[3] = (rt_uint8_t)(y2);
drv_lcd_cmd(lcd, VERTICAL_ADDRESS_SET);
drv_lcd_data_byte(lcd, data, 4);
drv_lcd_cmd(lcd, MEMORY_WRITE);
}
static void drv_lcd_set_pixel(lcd_8080_device_t lcd, uint16_t x, uint16_t y, uint16_t color)
{
drv_lcd_set_area(lcd, x, y, x, y);
drv_lcd_data_half_word(lcd, &color, 1);
}
static void drv_lcd_clear(lcd_8080_device_t lcd, uint16_t color)
{
uint32_t data = ((uint32_t)color << 16) | (uint32_t)color;
drv_lcd_set_area(lcd, 0, 0, lcd->lcd_info.width - 1, lcd->lcd_info.height - 1);
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0);
spi_init_non_standard(lcd->spi_channel, 0 /*instrction length*/, 32 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_fill_data_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, (const uint32_t *)&data, lcd->lcd_info.width * lcd->lcd_info.height / 2);
}
static void rt_bitblt(rt_uint16_t * dest, int dest_segment, int dest_common, int dest_x, int dest_y, int width, int height,
rt_uint16_t *src, int src_segment, int src_common, int src_x, int src_y)
{
int sx0, sx1, sy0, sy1;
int dx0, dx1, dy0, dy1;
rt_uint16_t *buff_src;
rt_uint16_t *buff_dest;
int x, y;
if (width <= 0) {
return;
}
if (height <= 0) {
return;
}
sx0 = src_x;
sy0 = src_y;
sx1 = sx0 + width - 1;
sy1 = sy0 + height - 1;
dx0 = dest_x;
dy0 = dest_y;
dx1 = dx0 + width - 1;
dy1 = dy0 + height - 1;
if (sx0 < 0) {
dx0 -= sx0;
sx0 = 0;
}
if (sy0 < 0) {
dy0 -= sy0;
sy0 = 0;
}
if (sx1 >= src_segment) {
dx1 -= (sx1 - src_segment + 1);
sx1 = src_segment - 1;
}
if (sy1 >= src_common) {
dy1 -= (sy1 - src_common + 1);
sy1 = src_common - 1;
}
if (dx0 < 0) {
sx0 -= dx0;
dx0 = 0;
}
if (dy0 < 0) {
sy0 -= dy0;
dy0 = 0;
}
if (dx1 >= dest_segment) {
sx1 -= (dx1 - dest_segment + 1);
dx1 = dest_segment - 1;
}
if (dy1 >= dest_common) {
sy1 -= (dy1 - dest_common + 1);
dy1 = dest_common - 1;
}
if (sx1 < 0 || sx0 >= src_segment) {
return;
}
if (sy1 < 0 || sy0 >= src_common) {
return;
}
if (dx1 < 0 || dx0 >= dest_segment) {
return;
}
if (dy1 < 0 || dy0 >= dest_common) {
return;
}
if ((rt_ubase_t)dest < (rt_ubase_t)src) {
buff_src = src + (sy0 * src_segment) + sx0;
buff_dest = dest + (dy0 * dest_segment) + dx0;
for (y = sy0; y <= sy1; y++) {
src = buff_src;
dest = buff_dest;
for (x = sx0; x <= sx1; x++) {
*dest++ = *src++;
}
buff_src += src_segment;
buff_dest += dest_segment;
}
} else {
buff_src = src + (sy1 * src_segment) + sx1;
buff_dest = dest + (dy1 * dest_segment) + dx1;
for (y = sy1; y >= sy0; y--) {
src = buff_src;
dest = buff_dest;
for (x = sx1; x >= sx0; x--) {
*dest-- = *src--;
}
buff_src -= src_segment;
buff_dest -= dest_segment;
}
}
}
static void drv_lcd_rect_update(lcd_8080_device_t lcd, uint16_t x1, uint16_t y1, uint16_t width, uint16_t height)
{
static rt_uint16_t * rect_buffer = RT_NULL;
if(!rect_buffer)
{
rect_buffer = rt_malloc_align(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8), 64);
if(!rect_buffer)
{
return;
}
}
if(x1 == 0 && y1 == 0 && width == lcd->lcd_info.width && height == lcd->lcd_info.height)
{
drv_lcd_set_area(lcd, x1, y1, x1 + width - 1, y1 + height - 1);
drv_lcd_data_half_word(lcd, (rt_uint32_t *)lcd->lcd_info.framebuffer, width * height);
}
else
{
rt_bitblt(rect_buffer, width, height, 0, 0, width, height,(rt_uint16_t *)lcd->lcd_info.framebuffer, lcd->lcd_info.width, lcd->lcd_info.height, x1, y1);
drv_lcd_set_area(lcd, x1, y1, x1 + width - 1, y1 + height - 1);
drv_lcd_data_half_word(lcd, (rt_uint16_t *)rect_buffer, width * height);
}
}
static rt_err_t drv_lcd_init(rt_device_t dev)
{
rt_err_t ret = RT_EOK;
lcd_8080_device_t lcd = (lcd_8080_device_t)dev;
rt_uint8_t data = 0;
if(!lcd)
{
return RT_ERROR;
}
drv_lcd_hw_init(lcd);
/* reset LCD */
drv_lcd_cmd(lcd, SOFTWARE_RESET);
rt_thread_mdelay(100);
/* Enter normal status */
drv_lcd_cmd(lcd, SLEEP_OFF);
rt_thread_mdelay(100);
/* pixel format rgb565 */
drv_lcd_cmd(lcd, PIXEL_FORMAT_SET);
data = 0x55;
drv_lcd_data_byte(lcd, &data, 1);
/* set direction */
drv_lcd_set_direction(lcd, LCD_SCAN_DIR);
lcd->lcd_info.framebuffer = rt_malloc_align(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8), 64);
RT_ASSERT(lcd->lcd_info.framebuffer);
uint16_t *framebuffer = (uint16_t *)(lcd->lcd_info.framebuffer);
for(uint32_t i=0; i<(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8))/2; i++) {
framebuffer[i] = BLACK;
}
/*display on*/
drv_lcd_cmd(lcd, DISPALY_ON);
/* set to black */
drv_lcd_clear(lcd, BLACK);
return ret;
}
static rt_err_t drv_lcd_open(rt_device_t dev, rt_uint16_t oflag)
{
/* Not need */
return RT_EOK;
}
static rt_err_t drv_lcd_close(rt_device_t dev)
{
/* Not need */
return RT_EOK;
}
static rt_size_t drv_lcd_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
/* Not need */
return 0;
}
static rt_size_t drv_lcd_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
/* Not need */
return 0;
}
static rt_err_t drv_lcd_control(rt_device_t dev, int cmd, void *args)
{
rt_err_t ret = RT_EOK;
lcd_8080_device_t lcd = (lcd_8080_device_t)dev;
rt_base_t level;
struct rt_device_rect_info* rect_info = (struct rt_device_rect_info*)args;
RT_ASSERT(dev != RT_NULL);
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
if(!rect_info)
{
LOG_E("RTGRAPHIC_CTRL_RECT_UPDATE error args");
return -RT_ERROR;
}
drv_lcd_rect_update(lcd, rect_info->x, rect_info->y, rect_info->width, rect_info->height);
break;
#if BSP_LCD_BACKLIGHT_PIN >= 0
case RTGRAPHIC_CTRL_POWERON:
#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH);
#else
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#endif
break;
case RTGRAPHIC_CTRL_POWEROFF:
#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH);
#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#else
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH);
#endif
break;
#endif /* BSP_LCD_BACKLIGHT_PIN >= 0 */
case RTGRAPHIC_CTRL_GET_INFO:
*(struct rt_device_graphic_info *)args = lcd->lcd_info;
break;
case RTGRAPHIC_CTRL_SET_MODE:
ret = -RT_ENOSYS;
break;
case RTGRAPHIC_CTRL_GET_EXT:
ret = -RT_ENOSYS;
break;
default:
LOG_E("drv_lcd_control cmd: %d", cmd);
break;
}
return ret;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops drv_lcd_ops =
{
drv_lcd_init,
drv_lcd_open,
drv_lcd_close,
drv_lcd_read,
drv_lcd_write,
drv_lcd_control
};
#endif
int rt_hw_lcd_init(void)
{
rt_err_t ret = RT_EOK;
lcd_8080_device_t lcd_dev = &_lcddev;
lcd_dev->cs = SPI_CHIP_SELECT_0;
lcd_dev->dc_pin = LCD_DC_PIN;
#if BSP_LCD_RST_PIN >= 0
lcd_dev->rst_pin = LCD_RST_PIN;
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
lcd_dev->backlight_pin = LCD_BACKLIGHT_PIN;
#endif
dmalock_sync_take(&lcd_dev->dma_channel, RT_WAITING_FOREVER);
lcd_dev->spi_channel = SPI_DEVICE_0;
lcd_dev->lcd_info.bits_per_pixel = 16;
lcd_dev->lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
lcd_dev->parent.type = RT_Device_Class_Graphic;
lcd_dev->parent.rx_indicate = RT_NULL;
lcd_dev->parent.tx_complete = RT_NULL;
#ifdef RT_USING_DEVICE_OPS
lcd_dev->parent.ops = &drv_lcd_ops;
#else
lcd_dev->parent.init = drv_lcd_init;
lcd_dev->parent.open = drv_lcd_open;
lcd_dev->parent.close = drv_lcd_close;
lcd_dev->parent.read = drv_lcd_read;
lcd_dev->parent.write = drv_lcd_write;
lcd_dev->parent.control = drv_lcd_control;
#endif
lcd_dev->parent.user_data = RT_NULL;
ret = rt_device_register(&lcd_dev->parent, "lcd", RT_DEVICE_FLAG_RDWR);
return ret;
}
INIT_DEVICE_EXPORT(rt_hw_lcd_init);
void lcd_set_direction(lcd_dir_t dir)
{
drv_lcd_set_direction(&_lcddev, dir);
}
#endif
@@ -0,0 +1,90 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-07 ZYH first version
*/
#ifndef DRV_LCD_H__
#define DRV_LCD_H__
#include <rtdevice.h>
#include <board.h>
#include <gpiohs.h>
#include <spi.h>
#include <drv_io_config.h>
#include <rthw.h>
#include "dmalock.h"
//POINT_COLOR
#define WHITE 0xFFFF
#define BLACK 0x0000
#define BLUE 0x001F
#define BRED 0XF81F
#define GRED 0XFFE0
#define GBLUE 0X07FF
#define RED 0xF800
#define MAGENTA 0xF81F
#define GREEN 0x07E0
#define CYAN 0x7FFF
#define YELLOW 0xFFE0
#define BROWN 0XBC40
#define BRRED 0XFC07
#define GRAY 0X8430
#define GRAY175 0XAD75
#define GRAY151 0X94B2
#define GRAY187 0XBDD7
#define GRAY240 0XF79E
typedef enum _lcd_dir
{
DIR_XY_RLUD = 0x00,
DIR_YX_RLUD = 0x20,
DIR_XY_LRUD = 0x40,
DIR_YX_LRUD = 0x60,
DIR_XY_RLDU = 0x80,
DIR_YX_RLDU = 0xA0,
DIR_XY_LRDU = 0xC0,
DIR_YX_LRDU = 0xE0,
DIR_XY_MASK = 0x20,
DIR_MASK = 0xE0,
} lcd_dir_t;
typedef struct lcd_8080_device
{
struct rt_device parent;
struct rt_device_graphic_info lcd_info;
int spi_channel;
int cs;
int dc_pin;
#if BSP_LCD_RST_PIN >= 0
int rst_pin;
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
int backlight_pin;
#endif
int dma_channel;
} * lcd_8080_device_t;
int rt_hw_lcd_init(void);
void drv_lcd_set_area(lcd_8080_device_t lcd, rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2);
void drv_lcd_data_word(lcd_8080_device_t lcd, rt_uint32_t *data_buf, rt_uint32_t length);
void drv_lcd_data_half_word(lcd_8080_device_t lcd, rt_uint16_t *data_buf, rt_uint32_t length);
/* for mpy machine.lcd */
void lcd_display_on(void);
void lcd_display_off(void);
void lcd_clear(int color);
void lcd_draw_point_color(int x, int y, int color);
void lcd_show_string(int x, int y, int size, const char *data);
void lcd_draw_line(int x1, int y1, int x2, int y2);
void lcd_draw_rectangle(int x1, int y1, int x2, int y2);
void lcd_draw_circle(int x1, int y1, int r);
void lcd_set_color(int back, int fore);
void lcd_show_image(int x, int y, int length, int wide, const unsigned char *buf);
void lcd_set_direction(lcd_dir_t dir);
#endif
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,27 @@
#include <sysctl.h>
int mp_port_get_freq(int clkid, int *freq)
{
int ret = 0;
uint32_t value;
switch (clkid)
{
case 0:
value = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU);
break;
case 1:
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL1);
break;
case 2:
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL2);
break;
default:
ret = -1;
break;
}
*freq = (int)value;
return ret;
}
@@ -0,0 +1,301 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-18 ZYH first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#ifdef RT_USING_SPI
#include "drv_spi.h"
#include <drv_io_config.h>
#include <spi.h>
#include "dmalock.h"
#include <sysctl.h>
#include <gpiohs.h>
#include <string.h>
#include "utils.h"
#define DRV_SPI_DEVICE(spi_bus) (struct drv_spi_bus *)(spi_bus)
#define MAX_CLOCK (40000000UL)
struct drv_spi_bus
{
struct rt_spi_bus parent;
spi_device_num_t spi_instance;
dmac_channel_number_t dma_send_channel;
dmac_channel_number_t dma_recv_channel;
struct rt_completion dma_completion;
};
struct drv_cs
{
int cs_index;
int cs_pin;
};
static volatile spi_t *const spi_instance[4] =
{
(volatile spi_t *)SPI0_BASE_ADDR,
(volatile spi_t *)SPI1_BASE_ADDR,
(volatile spi_t *)SPI_SLAVE_BASE_ADDR,
(volatile spi_t *)SPI3_BASE_ADDR
};
static rt_err_t drv_spi_configure(struct rt_spi_device *device,
struct rt_spi_configuration *configuration)
{
rt_err_t ret = RT_EOK;
int freq = 0;
struct drv_spi_bus *bus = DRV_SPI_DEVICE(device->bus);
struct drv_cs * cs = (struct drv_cs *)device->parent.user_data;
RT_ASSERT(bus != RT_NULL);
gpiohs_set_drive_mode(cs->cs_pin, GPIO_DM_OUTPUT);
gpiohs_set_pin(cs->cs_pin, GPIO_PV_HIGH);
#ifdef BSP_USING_SPI1_AS_QSPI
/* Todo:QSPI*/
#else
spi_init(bus->spi_instance, configuration->mode & RT_SPI_MODE_3, SPI_FF_STANDARD, configuration->data_width, 0);
#endif
freq = spi_set_clk_rate(bus->spi_instance, configuration->max_hz > MAX_CLOCK ? MAX_CLOCK : configuration->max_hz);
rt_kprintf("set spi freq %d\n", freq);
return ret;
}
void __spi_set_tmod(uint8_t spi_num, uint32_t tmod)
{
RT_ASSERT(spi_num < SPI_DEVICE_MAX);
volatile spi_t *spi_handle = spi[spi_num];
uint8_t tmod_offset = 0;
switch(spi_num)
{
case 0:
case 1:
case 2:
tmod_offset = 8;
break;
case 3:
default:
tmod_offset = 10;
break;
}
set_bit(&spi_handle->ctrlr0, 3 << tmod_offset, tmod << tmod_offset);
}
int dma_irq_callback(void *ctx)
{
struct rt_completion * cmp = ctx;
if(cmp)
{
rt_completion_done(cmp);
}
}
static rt_uint32_t drv_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
struct drv_spi_bus *bus = DRV_SPI_DEVICE(device->bus);
struct drv_cs * cs = (struct drv_cs *)device->parent.user_data;
struct rt_spi_configuration *cfg = &device->config;
uint32_t * tx_buff = RT_NULL;
uint32_t * rx_buff = RT_NULL;
int i;
rt_ubase_t dummy = 0xFFFFFFFFU;
if(cfg->data_width != 8)
{
return 0;
}
RT_ASSERT(bus != RT_NULL);
if(message->cs_take)
{
gpiohs_set_pin(cs->cs_pin, GPIO_PV_LOW);
}
if(message->length)
{
bus->dma_send_channel = DMAC_CHANNEL_MAX;
bus->dma_recv_channel = DMAC_CHANNEL_MAX;
rt_completion_init(&bus->dma_completion);
if(message->recv_buf)
{
dmalock_sync_take(&bus->dma_recv_channel, RT_WAITING_FOREVER);
sysctl_dma_select(bus->dma_recv_channel, SYSCTL_DMA_SELECT_SSI0_RX_REQ + bus->spi_instance * 2);
rx_buff = rt_calloc(message->length * 4, 1);
if(!rx_buff)
{
goto transfer_done;
}
}
if(message->send_buf)
{
dmalock_sync_take(&bus->dma_send_channel, RT_WAITING_FOREVER);
sysctl_dma_select(bus->dma_send_channel, SYSCTL_DMA_SELECT_SSI0_TX_REQ + bus->spi_instance * 2);
tx_buff = rt_malloc(message->length * 4);
if(!tx_buff)
{
goto transfer_done;
}
for(i = 0; i < message->length; i++)
{
tx_buff[i] = ((uint8_t *)message->send_buf)[i];
}
}
if(message->send_buf && message->recv_buf)
{
dmac_irq_register(bus->dma_recv_channel, dma_irq_callback, &bus->dma_completion, 1);
__spi_set_tmod(bus->spi_instance, SPI_TMOD_TRANS_RECV);
spi_instance[bus->spi_instance]->dmacr = 0x3;
spi_instance[bus->spi_instance]->ssienr = 0x01;
dmac_set_single_mode(bus->dma_recv_channel, (void *)(&spi_instance[bus->spi_instance]->dr[0]), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, message->length);
dmac_set_single_mode(bus->dma_send_channel, tx_buff, (void *)(&spi_instance[bus->spi_instance]->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, message->length);
}
else if(message->send_buf)
{
dmac_irq_register(bus->dma_send_channel, dma_irq_callback, &bus->dma_completion, 1);
__spi_set_tmod(bus->spi_instance, SPI_TMOD_TRANS);
spi_instance[bus->spi_instance]->dmacr = 0x2;
spi_instance[bus->spi_instance]->ssienr = 0x01;
dmac_set_single_mode(bus->dma_send_channel, tx_buff, (void *)(&spi_instance[bus->spi_instance]->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, message->length);
}
else if(message->recv_buf)
{
dmac_irq_register(bus->dma_recv_channel, dma_irq_callback, &bus->dma_completion, 1);
__spi_set_tmod(bus->spi_instance, SPI_TMOD_RECV);
spi_instance[bus->spi_instance]->ctrlr1 = message->length - 1;
spi_instance[bus->spi_instance]->dmacr = 0x1;
spi_instance[bus->spi_instance]->ssienr = 0x01;
spi_instance[bus->spi_instance]->dr[0] = 0xFF;
dmac_set_single_mode(bus->dma_recv_channel, (void *)(&spi_instance[bus->spi_instance]->dr[0]), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, message->length);
}
else
{
goto transfer_done;
}
spi_instance[bus->spi_instance]->ser = 1U << cs->cs_index;
rt_completion_wait(&bus->dma_completion, RT_WAITING_FOREVER);
if(message->recv_buf)
dmac_irq_unregister(bus->dma_recv_channel);
else
dmac_irq_unregister(bus->dma_send_channel);
// wait until all data has been transmitted
while ((spi_instance[bus->spi_instance]->sr & 0x05) != 0x04)
;
spi_instance[bus->spi_instance]->ser = 0x00;
spi_instance[bus->spi_instance]->ssienr = 0x00;
if(message->recv_buf)
{
for(i = 0; i < message->length; i++)
{
((uint8_t *)message->recv_buf)[i] = (uint8_t)rx_buff[i];
}
}
transfer_done:
dmalock_release(bus->dma_send_channel);
dmalock_release(bus->dma_recv_channel);
if(tx_buff)
{
rt_free(tx_buff);
}
if(rx_buff)
{
rt_free(rx_buff);
}
}
if(message->cs_release)
{
gpiohs_set_pin(cs->cs_pin, GPIO_PV_HIGH);
}
return message->length;
}
const static struct rt_spi_ops drv_spi_ops =
{
drv_spi_configure,
drv_spi_xfer
};
int rt_hw_spi_init(void)
{
rt_err_t ret = RT_EOK;
#ifdef BSP_USING_SPI1
{
static struct drv_spi_bus spi_bus1;
spi_bus1.spi_instance = SPI_DEVICE_1;
ret = rt_spi_bus_register(&spi_bus1.parent, "spi1", &drv_spi_ops);
#ifdef BSP_SPI1_USING_SS0
{
static struct rt_spi_device spi_device10;
static struct drv_cs cs10 =
{
.cs_index = SPI_CHIP_SELECT_0,
.cs_pin = SPI1_CS0_PIN
};
rt_spi_bus_attach_device(&spi_device10, "spi10", "spi1", (void *)&cs10);
}
#endif
#ifdef BSP_SPI1_USING_SS1
{
static struct rt_spi_device spi_device11;
static struct drv_cs cs11 =
{
.cs_index = SPI_CHIP_SELECT_1,
.cs_pin = SPI1_CS1_PIN
};
rt_spi_bus_attach_device(&spi_device11, "spi11", "spi1", (void *)&cs11);
}
#endif
#ifdef BSP_SPI1_USING_SS2
{
static struct rt_spi_device spi_device12;
static struct drv_cs cs12 =
{
.cs_index = SPI_CHIP_SELECT_2,
.cs_pin = SPI1_CS2_PIN
};
rt_spi_bus_attach_device(&spi_device12, "spi12", "spi1", (void *)&cs12);
}
#endif
#ifdef BSP_SPI1_USING_SS3
{
static struct rt_spi_device spi_device13;
static struct drv_cs cs13 =
{
.cs_index = SPI_CHIP_SELECT_2,
.cs_pin = SPI1_CS2_PIN
};
rt_spi_bus_attach_device(&spi_device13, "spi13", "spi1", (void *)&cs13);
}
#endif
}
#endif
return ret;
}
INIT_DEVICE_EXPORT(rt_hw_spi_init);
#endif
@@ -0,0 +1,16 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-18 ZYH first version
*/
#ifndef DRV_SPI_H__
#define DRV_SPI_H__
int rt_hw_spi_init(void);
#endif
@@ -0,0 +1,11 @@
#include <rtthread.h>
#include <stdlib.h>
size_t get_free_heap_size(void)
{
rt_uint32_t total, used, max;
rt_memory_info(&total, &used, &max);
return total - used;
}
@@ -0,0 +1,96 @@
#include <rtthread.h>
/*
RW007(SPI1 ) Kendryte Sipeed MAX bit io
pin numbers function pin number on rw007 board
io 15 SPI1_SCK SCK
io 8 SPI1_MISO MISO
io 10 SPI1_MOSI MOSI
io 9 CS/BOOT1 CS
io 6 INT/BUSY D9
io 7 RESET D8
set in mencuconfig after suring hardware well
board driver config-> enble spi1
(15) spi1 clk pin number
(10) spi1 d0 pin number
(8) spi1 d1 pin number
(*) spi1 enble ss1 --->
(9) spi1 ss1 pin number
verified
*/
#ifdef PKG_USING_RW007
#include <rtdevice.h>
#include <drv_spi.h>
#include <board.h>
#include <spi_wifi_rw007.h>
extern void spi_wifi_isr(int vector);
static int rw007_gpio_init(void)
{
int cnt = 15;
/* Configure IO */
rt_pin_mode(RW007_RST_PIN, PIN_MODE_OUTPUT);
rt_pin_mode(RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLDOWN);
/* Reset rw007 and config mode */
rt_pin_write(RW007_RST_PIN, PIN_LOW);
rt_thread_mdelay(100);
rt_pin_write(RW007_RST_PIN, PIN_HIGH);
/* Wait rw007 ready(exit busy stat) */
while(!rt_pin_read(RW007_INT_BUSY_PIN))
{
rt_thread_mdelay(100);
if (--cnt < 0)
return -1;
}
rt_thread_mdelay(200);
rt_pin_mode(RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLUP);
return 0;
}
int wifi_spi_device_init(void)
{
char sn_version[32] = {0};
if (rw007_gpio_init() != 0)
{
rt_kprintf("rw007 wait busy timeout\n");
return -1;
}
rt_hw_wifi_init(RW007_SPIDEV_NAME);
rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION);
rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP);
rw007_sn_get(sn_version);
rt_kprintf("\nrw007 sn: [%s]\n", sn_version);
rw007_version_get(sn_version);
rt_kprintf("rw007 ver: [%s]\n\n", sn_version);
return 0;
}
INIT_APP_EXPORT(wifi_spi_device_init);
static void int_wifi_irq(void * p)
{
((void)p);
spi_wifi_isr(0);
}
void spi_wifi_hw_init(void)
{
rt_pin_attach_irq(RW007_INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0);
rt_pin_irq_enable(RW007_INT_BUSY_PIN, RT_TRUE);
}
#endif /* RW007_USING_STM32_DRIVERS */
@@ -0,0 +1,42 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rtthread.h>
#ifdef BSP_USING_SDCARD
#if defined(RT_USING_SPI_MSD) && defined(RT_USING_DFS_ELMFAT)
#include <spi_msd.h>
#include <dfs_fs.h>
#define DBG_TAG "sdcard"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
int sd_mount(void)
{
int ret = 0;
ret = msd_init("sd0", "spi10");
if(RT_EOK == ret)
{
if(dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{
LOG_I("Mount /sd0 successfully");
return RT_EOK;
}
else
{
LOG_E("Mount fail !!1");
return -1;
}
}
LOG_E("msd_init fail !!!");
return -2;
}
INIT_ENV_EXPORT(sd_mount);
#endif
#endif
@@ -0,0 +1,7 @@
menu "Kendryte SDK Config"
config PKG_KENDRYTE_SDK_VERNUM
hex "Kendryte SDK Version"
default 0x0055
endmenu
@@ -0,0 +1,37 @@
from building import *
cwd = GetCurrentDir()
src = Split('''
kendryte-sdk-source/lib/bsp/entry.c
kendryte-sdk-source/lib/bsp/entry_user.c
kendryte-sdk-source/lib/drivers/aes.c
kendryte-sdk-source/lib/drivers/clint.c
kendryte-sdk-source/lib/drivers/dmac.c
kendryte-sdk-source/lib/drivers/dvp.c
kendryte-sdk-source/lib/drivers/fft.c
kendryte-sdk-source/lib/drivers/fpioa.c
kendryte-sdk-source/lib/drivers/gpio.c
kendryte-sdk-source/lib/drivers/gpiohs.c
kendryte-sdk-source/lib/drivers/i2c.c
kendryte-sdk-source/lib/drivers/i2s.c
kendryte-sdk-source/lib/drivers/kpu.c
kendryte-sdk-source/lib/drivers/plic.c
kendryte-sdk-source/lib/drivers/pwm.c
kendryte-sdk-source/lib/drivers/rtc.c
kendryte-sdk-source/lib/drivers/sha256.c
kendryte-sdk-source/lib/drivers/spi.c
kendryte-sdk-source/lib/drivers/sysctl.c
kendryte-sdk-source/lib/drivers/timer.c
kendryte-sdk-source/lib/drivers/uart.c
kendryte-sdk-source/lib/drivers/uarths.c
kendryte-sdk-source/lib/drivers/utils.c
kendryte-sdk-source/lib/drivers/wdt.c
''')
CPPPATH = [cwd + '/kendryte-sdk-source/lib/drivers/include',
cwd + '/kendryte-sdk-source/lib/bsp/include',
cwd + '/kendryte-sdk-source/lib/utils/include']
CPPDEFINES = ['CONFIG_LOG_COLORS', 'CONFIG_LOG_ENABLE', 'CONFIG_LOG_LEVEL=LOG_VERBOSE', 'FPGA_PLL', 'LOG_KERNEL', '__riscv64']
group = DefineGroup('SDK', src, depend = [''], CPPPATH = CPPPATH, LOCAL_CPPDEFINES = CPPDEFINES)
Return('group')
@@ -0,0 +1,170 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
INCLUDE "link_stacksize.lds"
/*
* The OUTPUT_ARCH command specifies the machine architecture where the
* argument is one of the names used in the Kendryte library.
*/
OUTPUT_ARCH( "riscv" )
MEMORY
{
/* 6M SRAM */
SRAM : ORIGIN = 0x80000000, LENGTH = 0x600000
}
ENTRY(_start)
SECTIONS
{
. = 0x80000000 ;
/* __STACKSIZE__ = 4096; */
.start :
{
*(.start);
} > SRAM
. = ALIGN(8);
.text :
{
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(8);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(8);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(8);
/* section information for initial. */
. = ALIGN(8);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(8);
PROVIDE(__ctors_start__ = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
. = ALIGN(8);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
. = ALIGN(8);
_etext = .;
} > SRAM
.eh_frame_hdr :
{
*(.eh_frame_hdr)
*(.eh_frame_entry)
} > SRAM
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
. = ALIGN(8);
.data :
{
*(.data)
*(.data.*)
*(.data1)
*(.data1.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata)
*(.sdata.*)
} > SRAM
/* stack for dual core */
.stack :
{
. = ALIGN(64);
__stack_start__ = .;
. += __STACKSIZE__;
__stack_cpu0 = .;
. += __STACKSIZE__;
__stack_cpu1 = .;
} > SRAM
.sbss :
{
__bss_start = .;
*(.sbss)
*(.sbss.*)
*(.dynsbss)
*(.scommon)
} > SRAM
.bss :
{
*(.bss)
*(.bss.*)
*(.dynbss)
*(COMMON)
__bss_end = .;
} > SRAM
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
@@ -0,0 +1 @@
__STACKSIZE__ = 4096;
@@ -0,0 +1,363 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* XIUOS Rt-thread Configuration */
#define ROOT_DIR "../../../.."
#define BSP_DIR "."
#define RT_Thread_DIR "../.."
#define RTT_DIR "../../rt-thread"
#define BOARD_K210_EVB
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_DEBUG
#define RT_DEBUG_COLOR
#define RT_DEBUG_INIT_CONFIG
#define RT_DEBUG_INIT 1
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_SIGNALS
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_MEMHEAP
#define RT_USING_SLAB
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uarths"
#define RT_VER_NUM 0x40004
#define ARCH_CPU_64BIT
#define ARCH_RISCV
#define ARCH_RISCV_FPU
#define ARCH_RISCV_FPU_S
#define ARCH_RISCV64
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
#define RT_USING_CPLUSPLUS
/* Command shell */
#define RT_USING_FINSH
#define RT_USING_MSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 16384
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 16
#define DFS_FILESYSTEM_TYPES_MAX 16
#define DFS_FD_MAX 64
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_RTC
#define RT_USING_SPI
#define RT_USING_SPI_MSD
#define RT_USING_SFUD
#define RT_SFUD_USING_SFDP
#define RT_SFUD_USING_FLASH_INFO_TABLE
#define RT_SFUD_SPI_MAX_HZ 50000000
#define RT_DEBUG_SFUD
#define RT_USING_WIFI
#define RT_WLAN_DEVICE_STA_NAME "wlan0"
#define RT_WLAN_DEVICE_AP_NAME "wlan1"
#define RT_WLAN_SSID_MAX_LENGTH 32
#define RT_WLAN_PASSWORD_MAX_LENGTH 32
#define RT_WLAN_DEV_EVENT_NUM 2
#define RT_WLAN_MANAGE_ENABLE
#define RT_WLAN_SCAN_WAIT_MS 10000
#define RT_WLAN_CONNECT_WAIT_MS 10000
#define RT_WLAN_SCAN_SORT
#define RT_WLAN_MSH_CMD_ENABLE
#define RT_WLAN_AUTO_CONNECT_ENABLE
#define AUTO_CONNECTION_PERIOD_MS 2000
#define RT_WLAN_CFG_ENABLE
#define RT_WLAN_CFG_INFO_MAX 3
#define RT_WLAN_PROT_ENABLE
#define RT_WLAN_PROT_NAME_LEN 8
#define RT_WLAN_PROT_MAX 2
#define RT_WLAN_DEFAULT_PROT "lwip"
#define RT_WLAN_PROT_LWIP_ENABLE
#define RT_WLAN_PROT_LWIP_NAME "lwip"
#define RT_WLAN_WORK_THREAD_ENABLE
#define RT_WLAN_WORKQUEUE_THREAD_NAME "wlan"
#define RT_WLAN_WORKQUEUE_THREAD_SIZE 2048
#define RT_WLAN_WORKQUEUE_THREAD_PRIO 15
/* Using USB */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_USING_PTHREADS
#define PTHREAD_NUM_MAX 8
#define RT_USING_POSIX
#define RT_LIBC_USING_TIME
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* Network */
/* Socket abstraction layer */
#define RT_USING_SAL
/* protocol stack implement */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
/* Network interface device */
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
/* light weight TCP/IP stack */
#define RT_USING_LWIP
#define RT_USING_LWIP202
#define RT_LWIP_MEM_ALIGNMENT 8
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
#define RT_LWIP_DHCP
#define IP_SOF_BROADCAST 1
#define IP_SOF_BROADCAST_RECV 1
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.1.30"
#define RT_LWIP_GWADDR "192.168.1.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 16
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 10
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 10240
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 10240
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread Utestcases */
/* Board Drivers Config */
#define BSP_USING_UART_HS
/* General Purpose UARTs */
#define BSP_USING_UART1
#define BSP_UART1_TXD_PIN 20
#define BSP_UART1_RXD_PIN 21
#define BSP_UART1_RTS_PIN -1
#define BSP_UART1_CTS_PIN -1
#define BSP_USING_SPI1
#define BSP_SPI1_CLK_PIN 27
#define BSP_SPI1_D0_PIN 28
#define BSP_SPI1_D1_PIN 26
#define BSP_SPI1_USING_SS0
#define BSP_SPI1_SS0_PIN 29
#define BSP_SPI1_USING_SS1
#define BSP_SPI1_SS1_PIN 8
#define BSP_USING_LCD
#define BSP_LCD_CS_PIN 36
#define BSP_LCD_WR_PIN 39
#define BSP_LCD_DC_PIN 38
#define BSP_LCD_RST_PIN 37
#define BSP_LCD_BACKLIGHT_PIN -1
#define BSP_LCD_BACKLIGHT_ACTIVE_LOW
#define BSP_LCD_CLK_FREQ 20000000
#define BSP_BOARD_USER
#define BSP_LCD_X_MAX 240
#define BSP_LCD_Y_MAX 320
#define BSP_USING_SDCARD
#define BSP_USING_DVP
/* The default pin assignment is based on the Maix Duino K210 development board */
#define BSP_DVP_SCCB_SDA_PIN 40
#define BSP_DVP_SCCB_SCLK_PIN 41
#define BSP_DVP_CMOS_RST_PIN 42
#define BSP_DVP_CMOS_VSYNC_PIN 43
#define BSP_DVP_CMOS_PWDN_PIN 44
#define BSP_DVP_CMOS_XCLK_PIN 46
#define BSP_DVP_CMOS_PCLK_PIN 47
#define BSP_DVP_CMOS_HREF_PIN 45
/* Kendryte SDK Config */
#define PKG_KENDRYTE_SDK_VERNUM 0x0055
/* MicroPython */
/* More Drivers */
#define DRV_USING_OV2640
#define OV2640_JPEG_MODE
#define OV2640_X_RESOLUTION_IMAGE_OUTSIZE 240
#define OV2640_Y_RESOLUTION_IMAGE_OUTSIZE 240
#define OV2640_X_IMAGE_WINDOWS_SIZE 400
/* the value must be greater than OV2640_X_RESOLUTION_IMAGE_OUTSIZE */
#define OV2640_Y_IMAGE_WINDOWS_SIZE 400
/* the value must be greater than OV2640_Y_RESOLUTION_IMAGE_OUTSIZE */
/* APP_Framework */
/* Framework */
#define TRANSFORM_LAYER_ATTRIUBUTE
#define ADD_XIZI_FETURES
#define SUPPORT_KNOWING_FRAMEWORK
#define USING_KPU_PROCESSING
#define USING_YOLOV2
#define USING_YOLOV2_JSONPARSER
#define USING_K210_YOLOV2_DETECT
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 1024
/* ota app */
/* test app */
/* connection app */
/* control app */
/* knowing app */
#define APPLICATION_KNOWING
#define K210_DETECT_ENTRY
/* sensor app */
#define APPLICATION_SENSOR
/* lib */
#define APP_SELECT_NEWLIB
#define LIB_USING_CJSON
#define __STACKSIZE__ 4096
#endif
@@ -0,0 +1,49 @@
import os
# toolchains options
ARCH ='risc-v'
CPU ='k210'
CROSS_TOOL ='gcc'
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'/opt/xpack-riscv-none-gcc/bin'
else:
print('Please make sure your toolchains is GNU GCC!')
exit(0)
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
PREFIX = 'riscv-none-embed-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcmodel=medany -march=rv64imafc -mabi=lp64f -fsingle-precision-constant'
CFLAGS = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -ggdb'
AFLAGS += ' -ggdb'
else:
CFLAGS += ' -O2 -Os'
CXXFLAGS = CFLAGS
# we use c++ 11, but -std=c++11 don't have 'struct siginfo', need gnu++11
CXXFLAGS += ' -std=gnu++11'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'