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Ubiquitous/RT-Thread_Fusion_XiUOS:change name from RT_Thread to RT-Thread_Fusion_XiUOS

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chunyexixiaoyu
2022-03-30 18:18:18 +08:00
parent 658feff666
commit 5a0ffaf193
624 changed files with 13 additions and 13 deletions
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46
Ubiquitous/RT-Thread_Fusion_XiUOS/README.md Normal file
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# 基于rt-thread的矽璓工业物联操作系统XiUOS
矽璓工业物联操作系统XiUOS主要分为系统层 、框架层、和应用层。其中系统层支持XIUOS、Nuttx、rt-thread三个操作系统，该目录主要内容是基于**rt-thread的系统层。**
## 目录内容
```
xiuos/Ubiquitous/Rt-thread
├── README.md
├── aiit_board 板级支持包
|──stm32f407_core
|──k210
├── app_match_rt-thread WiFi、Camera 等适配rt-thread的用户驱动
└── rt-thread RT-Thread 代码
```
## 支持平台
RT-Thread_Fusion_XiUOS/aiit_board 目前主要支持两个平台：STM32F4 和 Kendryte K210。如果后续用户想自己添加相关的板级支持包在此目录添加即可。
RT-Thread_Fusion_XiUOS/app_match_rt-thread 目前主要支持 WiFi 和 Camera，其他驱动复用 RT-Thread 的内容。如果rt-thread官方仓库驱动不满足用户使用要求，如果用户增加相关驱动可在此目录。
RT-Thread_Fusion_XiUOS/rt-thread 使用 RT-Thread 作为系统基础设施，提供底层支持。
## 使用
运行以下指令下载代码、编译运行：
```
# 下载代码
# 进入xiuos目录下载更新子模块(包括RT-thread 和 K210 SDK（如果用到K210 需更新kendryte-sdk）)执行以下三条命令或者直接执行当前目录下的download.sh脚本命令
git submodule init
git submodule update Ubiquitous/RT-Thread_Fusion_XiUOS/rt-thread
git submodule update Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/kendryte-sdk/kendryte-sdk-source
# 进入 xiuos/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core 配置 Kconfig
scons --menuconfig
# 编译
scons
# 烧录镜像
st-flash write rtthread.bin 0x8000000
```
同时也可以支持windows开发环境进行上述命令进行编译，需安装env插件，详细介绍可以参照[rt-thread官方资料](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/application-note/setup/standard-project/an0017-standard-project?id=%e4%bd%bf%e7%94%a8-env-%e5%88%9b%e5%bb%ba-rt-thread-%e9%a1%b9%e7%9b%ae%e5%b7%a5%e7%a8%8b
)。

431
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/.config Normal file
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#
# Automatically generated file; DO NOT EDIT.
# XIUOS Rt-thread Configuration
#
CONFIG_ROOT_DIR="../../../.."
CONFIG_BSP_DIR="."
CONFIG_RT_Thread_DIR="../.."
CONFIG_RTT_DIR="../../rt-thread"
CONFIG_BOARD_K210_EVB=y
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=24
# CONFIG_RT_USING_BIG_ENDIAN is not set
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=2
CONFIG_RT_ALIGN_SIZE=8
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=4096
CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
# CONFIG_RT_USING_TIMER_SOFT is not set
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_ASM_MEMCPY is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
CONFIG_RT_DEBUG_INIT_CONFIG=y
CONFIG_RT_DEBUG_INIT=1
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
CONFIG_RT_USING_SIGNALS=y
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_MEMHEAP=y
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_SMALL_MEM is not set
CONFIG_RT_USING_SLAB=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uarths"
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_VER_NUM=0x40004
CONFIG_ARCH_CPU_64BIT=y
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_RISCV_FPU=y
CONFIG_ARCH_RISCV_FPU_S=y
CONFIG_ARCH_RISCV64=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
CONFIG_RT_USING_CPLUSPLUS=y
# CONFIG_RT_USING_CPLUSPLUS11 is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_RT_USING_MSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=16384
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=16
CONFIG_DFS_FILESYSTEM_TYPES_MAX=16
CONFIG_DFS_FD_MAX=64
# CONFIG_RT_USING_DFS_MNTTABLE is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_QSPI is not set
CONFIG_RT_USING_SPI_MSD=y
CONFIG_RT_USING_SFUD=y
CONFIG_RT_SFUD_USING_SFDP=y
CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
# CONFIG_RT_SFUD_USING_QSPI is not set
CONFIG_RT_SFUD_SPI_MAX_HZ=50000000
CONFIG_RT_DEBUG_SFUD=y
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
CONFIG_RT_USING_PTHREADS=y
CONFIG_PTHREAD_NUM_MAX=8
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_GETLINE is not set
# CONFIG_RT_USING_POSIX_AIO is not set
CONFIG_RT_LIBC_USING_TIME=y
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# Board Drivers Config
#
CONFIG_BSP_USING_UART_HS=y
#
# General Purpose UARTs
#
CONFIG_BSP_USING_UART1=y
CONFIG_BSP_UART1_TXD_PIN=20
CONFIG_BSP_UART1_RXD_PIN=21
CONFIG_BSP_UART1_RTS_PIN=-1
CONFIG_BSP_UART1_CTS_PIN=-1
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_SPI1 is not set
# CONFIG_BSP_USING_LCD is not set
# CONFIG_BSP_USING_SDCARD is not set
# CONFIG_BSP_USING_DVP is not set
CONFIG_BSP_USING_CH438=y
CONFIG_BSP_CH438_ALE_PIN=23
CONFIG_BSP_CH438_NWR_PIN=24
CONFIG_BSP_CH438_NRD_PIN=25
CONFIG_BSP_CH438_D0_PIN=27
CONFIG_BSP_CH438_D1_PIN=28
CONFIG_BSP_CH438_D2_PIN=29
CONFIG_BSP_CH438_D3_PIN=30
CONFIG_BSP_CH438_D4_PIN=31
CONFIG_BSP_CH438_D5_PIN=32
CONFIG_BSP_CH438_D6_PIN=33
CONFIG_BSP_CH438_D7_PIN=34
CONFIG_BSP_CH438_INT_PIN=35
#
# Kendryte SDK Config
#
CONFIG_PKG_KENDRYTE_SDK_VERNUM=0x0055
#
# More Drivers
#
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_DRV_USING_OV2640 is not set
#
# APP_Framework
#
#
# Framework
#
CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y
# CONFIG_ADD_XIZI_FETURES is not set
# CONFIG_ADD_NUTTX_FETURES is not set
CONFIG_ADD_RTTHREAD_FETURES=y
CONFIG_SUPPORT_SENSOR_FRAMEWORK=y
CONFIG_SENSOR_HCHO=y
CONFIG_SENSOR_TB600B_WQ_HCHO1OS=y
CONFIG_SENSOR_DEVICE_TB600B_WQ_HCHO1OS="tb600b_wq_hcho1os_1"
CONFIG_SENSOR_QUANTITY_TB600B_HCHO="hcho_1"
CONFIG_SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART=y
CONFIG_SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV="/dev/extuart_dev1"
CONFIG_SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV_EXT_PORT=1
# CONFIG_SENSOR_TVOC is not set
# CONFIG_SENSOR_IAQ is not set
CONFIG_SENSOR_CH4=y
CONFIG_SENSOR_AS830=y
CONFIG_SENSOR_DEVICE_AS830="as830_1"
CONFIG_SENSOR_QUANTITY_AS830_CH4="ch4_1"
CONFIG_SENSOR_AS830_DRIVER_EXTUART=y
CONFIG_SENSOR_DEVICE_AS830_DEV="/dev/extuart_dev4"
CONFIG_SENSOR_DEVICE_AS830_DEV_EXT_PORT=4
# CONFIG_SENSOR_CO2 is not set
# CONFIG_SENSOR_PM is not set
# CONFIG_SENSOR_VOICE is not set
# CONFIG_SENSOR_TEMPERATURE is not set
# CONFIG_SENSOR_HUMIDITY is not set
# CONFIG_SENSOR_WINDSPEED is not set
# CONFIG_SENSOR_WINDDIRECTION is not set
# CONFIG_SENSOR_ALTITUDE is not set
# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set
# CONFIG_SUPPORT_KNOWING_FRAMEWORK is not set
# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set
#
# Security
#
# CONFIG_CRYPTO is not set
#
# Applications
#
#
# config stack size and priority of main task
#
CONFIG_MAIN_KTASK_STACK_SIZE=1024
#
# ota app
#
# CONFIG_APPLICATION_OTA is not set
#
# test app
#
# CONFIG_USER_TEST is not set
#
# connection app
#
# CONFIG_APPLICATION_CONNECTION is not set
#
# control app
#
#
# knowing app
#
# CONFIG_APPLICATION_KNOWING is not set
#
# sensor app
#
CONFIG_APPLICATION_SENSOR=y
CONFIG_APPLICATION_SENSOR_HCHO=y
CONFIG_APPLICATION_SENSOR_HCHO_TB600B_WQ_HCHO1OS=y
# CONFIG_APPLICATION_SENSOR_TVOC is not set
# CONFIG_APPLICATION_SENSOR_IAQ is not set
CONFIG_APPLICATION_SENSOR_CH4=y
CONFIG_APPLICATION_SENSOR_CH4_AS830=y
# CONFIG_APPLICATION_SENSOR_CO2 is not set
# CONFIG_APPLICATION_SENSOR_PM1_0 is not set
# CONFIG_APPLICATION_SENSOR_PM2_5 is not set
# CONFIG_APPLICATION_SENSOR_PM10 is not set
# CONFIG_APPLICATION_SENSOR_VOICE is not set
# CONFIG_APPLICATION_SENSOR_TEMPERATURE is not set
# CONFIG_APPLICATION_SENSOR_HUMIDITY is not set
# CONFIG_APPLICATION_SENSOR_WINDDIRECTION is not set
# CONFIG_APPLICATION_SENSOR_WINDSPEED is not set
# CONFIG_APPLICATION_SENSOR_ALTITUDE is not set
# CONFIG_USING_EMBEDDED_DATABASE_APP is not set
#
# lib
#
CONFIG_APP_SELECT_NEWLIB=y
# CONFIG_APP_SELECT_OTHER_LIB is not set
# CONFIG_LIB_USING_CJSON is not set
# CONFIG_LIB_USING_QUEUE is not set
# CONFIG_LIB_LV is not set
# CONFIG_USING_EMBEDDED_DATABASE is not set
CONFIG___STACKSIZE__=4096

228
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/.gitignore vendored Normal file
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# this
*.old
*.dblite
cconfig.h
*.bin
*.map
# rtconfig.h
# .config
# General
.DS_Store
.AppleDouble
.LSOverride
# Icon must end with two \r
Icon
# Thumbnails
._*
# Files that might appear in the root of a volume
.DocumentRevisions-V100
.fseventsd
.Spotlight-V100
.TemporaryItems
.Trashes
.VolumeIcon.icns
.com.apple.timemachine.donotpresent
# Directories potentially created on remote AFP share
.AppleDB
.AppleDesktop
Network Trash Folder
Temporary Items
.apdisk
# Byte-compiled / optimized / DLL files
__pycache__/
*.py[cod]
*$py.class
# C extensions
*.so
# Distribution / packaging
.Python
build/
develop-eggs/
dist/
downloads/
eggs/
.eggs/
lib/
lib64/
parts/
sdist/
var/
wheels/
share/python-wheels/
*.egg-info/
.installed.cfg
*.egg
MANIFEST
# PyInstaller
# Usually these files are written by a python script from a template
# before PyInstaller builds the exe, so as to inject date/other infos into it.
*.manifest
*.spec
# Installer logs
pip-log.txt
pip-delete-this-directory.txt
# Unit test / coverage reports
htmlcov/
.tox/
.nox/
.coverage
.coverage.*
.cache
nosetests.xml
coverage.xml
*.cover
*.py,cover
.hypothesis/
.pytest_cache/
cover/
# Translations
*.mo
*.pot
# Django stuff:
*.log
local_settings.py
db.sqlite3
db.sqlite3-journal
# Flask stuff:
instance/
.webassets-cache
# Scrapy stuff:
.scrapy
# Sphinx documentation
docs/_build/
# PyBuilder
.pybuilder/
target/
# Jupyter Notebook
.ipynb_checkpoints
# IPython
profile_default/
ipython_config.py
# pyenv
# For a library or package, you might want to ignore these files since the code is
# intended to run in multiple environments; otherwise, check them in:
# .python-version
# pipenv
# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control.
# However, in case of collaboration, if having platform-specific dependencies or dependencies
# having no cross-platform support, pipenv may install dependencies that don't work, or not
# install all needed dependencies.
#Pipfile.lock
# PEP 582; used by e.g. github.com/David-OConnor/pyflow
__pypackages__/
# Celery stuff
celerybeat-schedule
celerybeat.pid
# SageMath parsed files
*.sage.py
# Environments
.env
.venv
env/
venv/
ENV/
env.bak/
venv.bak/
# Spyder project settings
.spyderproject
.spyproject
# Rope project settings
.ropeproject
# mkdocs documentation
/site
# mypy
.mypy_cache/
.dmypy.json
dmypy.json
# Pyre type checker
.pyre/
# pytype static type analyzer
.pytype/
# Cython debug symbols
cython_debug/
# Prerequisites
*.d
# Object files
*.o
*.ko
*.obj
*.elf
# Linker output
*.ilk
*.map
*.exp
# Precompiled Headers
*.gch
*.pch
# Libraries
*.lib
*.a
*.la
*.lo
# Shared objects (inc. Windows DLLs)
*.dll
*.so
*.so.*
*.dylib
# Executables
*.exe
*.out
*.app
*.i*86
*.x86_64
*.hex
# Debug files
*.dSYM/
*.su
*.idb
*.pdb
# Kernel Module Compile Results
*.mod*
*.cmd
.tmp_versions/
modules.order
Module.symvers
Mkfile.old
dkms.con

39
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/Kconfig Normal file
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mainmenu "XIUOS Rt-thread Configuration"
config ROOT_DIR
string
default "../../../.."
config BSP_DIR
string
default "."
config RT_Thread_DIR
string
default "../.."
config RTT_DIR
string
default "../../rt-thread"
config BOARD_K210_EVB
bool
select ARCH_RISCV64
select ARCH_RISCV_FPU_S
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
config APP_DIR
string
default "../../../../APP_Framework"
source "$RTT_DIR/Kconfig"
source "base-drivers/Kconfig"
source "kendryte-sdk/Kconfig"
source "$RT_Thread_DIR/app_match_rt-thread/Kconfig"
source "$ROOT_DIR/APP_Framework/Kconfig"
config __STACKSIZE__
int "stack size for interrupt"
default 4096

17
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/README.md Normal file
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## aiit-riscv64-board编译说明
编译aiit-riscv64-board，需要有RT-Thread的代码，因为aiit-riscv64-boar的sdk是以软件包方式，更新软件包在~/yourdir/xiuos/目录执行以下语句：
git submodule init
git submodule update Ubiquitous/RT_Thread/rt-thread
git submodule update Ubiquitous/RT_Thread/aiit_board/aiit-riscv64-board/kendryte-sdk/kendryte-sdk-source
如果在Linux平台下，可以先执行
scons --menuconfig
退出后执行编译：
scons
编译工具链安装参考：xiuos/Ubiquitous/XiZi/board/aiit-riscv64-board/README.md

13
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/SConscript Normal file
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import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../rt-thread')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
# use ASPPCOM to replace ASCOM, ASPPCOM will use CFLAGS/CPPFLAGS with AS
env['ASCOM'] = env['ASPPCOM']
AddOption('--compiledb',
dest = 'compiledb',
action = 'store_true',
default = False,
help = 'generate compile_commands.json')
if GetOption('compiledb'):
if int(SCons.__version__.split('.')[0]) >= 4:
env['COMPILATIONDB_USE_ABSPATH'] = True
env.Tool('compilation_db')
env.CompilationDatabase('compile_commands.json')
else:
print('Warning: --compiledb only support on SCons 4.0+')
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
stack_size = 4096
stack_lds = open('link_stacksize.lds', 'w')
if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__')
stack_lds.write('__STACKSIZE__ = %d;' % stack_size)
stack_lds.close()
# include more drivers
objs.extend(SConscript(os.getcwd() + '/../../app_match_rt-thread/SConscript'))
# include APP_Framework/Framework
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Framework/SConscript'))
# include APP_Framework/Applications
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Applications/SConscript'))
# include APP_Framework/lib
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/lib/SConscript'))
# make a building
DoBuilding(TARGET, objs)

9
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/applications/SConscript Normal file
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from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

29
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/applications/main.c Normal file
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/*
* @Author: your name
* @Date: 2021-10-11 22:04:25
* @LastEditTime: 2021-10-14 11:12:52
* @LastEditors: Please set LastEditors
* @Description: In User Settings Edit
* @FilePath: \xiuos\Ubiquitous\RT_Thread\bsp\k210\applications\main.c
*/
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include <rtthread.h>
#include <stdio.h>
extern int FrameworkInit();
int main(void)
{
printf("Hello World\n");
FrameworkInit();
return 0;
}

284
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/Kconfig Normal file
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menu "Board Drivers Config"
config BSP_USING_UART_HS
bool "Enable High Speed UART"
default y
menu "General Purpose UARTs"
menuconfig BSP_USING_UART1
bool "Enable UART1"
default n
if BSP_USING_UART1
config BSP_UART1_TXD_PIN
int "uart1 TXD pin number"
default 20
config BSP_UART1_RXD_PIN
int "uart1 RXD pin number"
default 21
config BSP_UART1_RTS_PIN
int "uart1 RTS pin number (-1 for not used)"
default -1
config BSP_UART1_CTS_PIN
int "uart1 CTS pin number (-1 for not used)"
default -1
endif
menuconfig BSP_USING_UART2
bool "Enable UART2"
default n
if BSP_USING_UART2
config BSP_UART2_TXD_PIN
int "uart2 TXD pin number"
default 28
config BSP_UART2_RXD_PIN
int "uart2 RXD pin number"
default 27
config BSP_UART2_RTS_PIN
int "uart2 RTS pin number (-1 for not used)"
default -1
config BSP_UART2_CTS_PIN
int "uart2 CTS pin number (-1 for not used)"
default -1
endif
menuconfig BSP_USING_UART3
bool "Enable UART3"
default n
if BSP_USING_UART3
config BSP_UART3_TXD_PIN
int "uart3 TXD pin number"
default 22
config BSP_UART3_RXD_PIN
int "uart3 RXD pin number"
default 23
config BSP_UART3_RTS_PIN
int "uart3 RTS pin number (-1 for not used)"
default -1
config BSP_UART3_CTS_PIN
int "uart3 CTS pin number (-1 for not used)"
default -1
endif
endmenu
config BSP_USING_I2C1
bool "Enable I2C1 (GPIO0/1)"
select RT_USING_I2C
default n
menuconfig BSP_USING_SPI1
bool "Enable SPI1"
select RT_USING_SPI
default n
if BSP_USING_SPI1
config BSP_USING_SPI1_AS_QSPI
bool
default n
config BSP_SPI1_CLK_PIN
int "spi1 clk pin number"
default 27
config BSP_SPI1_D0_PIN
int "spi1 d0 pin number"
default 28
config BSP_SPI1_D1_PIN
int "spi1 d1 pin number"
default 26
if BSP_USING_SPI1_AS_QSPI
config BSP_SPI1_D2_PIN
int "spi1 d2 pin number"
default 32
config BSP_SPI1_D3_PIN
int "spi1 d3 pin number"
default 33
endif
menuconfig BSP_SPI1_USING_SS0
bool "SPI1 Enable SS0(spi10 dev)"
default n
if BSP_SPI1_USING_SS0
config BSP_SPI1_SS0_PIN
int "spi1 ss0 pin number"
default 29
endif
menuconfig BSP_SPI1_USING_SS1
bool "SPI1 Enable SS1(spi11 dev)"
default n
if BSP_SPI1_USING_SS1
config BSP_SPI1_SS1_PIN
int "spi1 ss1 pin number"
default 8
endif
menuconfig BSP_SPI1_USING_SS2
bool "SPI1 Enable SS2(spi12 dev)"
default n
if BSP_SPI1_USING_SS2
config BSP_SPI1_SS2_PIN
int "spi1 ss2 pin number"
default 26
endif
menuconfig BSP_SPI1_USING_SS3
bool "SPI1 Enable SS3(spi13 dev)"
default n
if BSP_SPI1_USING_SS3
config BSP_SPI1_SS3_PIN
int "spi1 ss3 pin number"
default 27
endif
endif
menuconfig BSP_USING_LCD
bool "Enable LCD on SPI0"
default n
if BSP_USING_LCD
config BSP_LCD_CS_PIN
int "CS pin number of 8080 interface"
default 36
config BSP_LCD_WR_PIN
int "WR pin number of 8080 interface"
default 39
config BSP_LCD_DC_PIN
int "DC pin number of 8080 interface"
default 38
config BSP_LCD_RST_PIN
int "RESET pin number of 8080 interface (-1 for not used)"
default 37
config BSP_LCD_BACKLIGHT_PIN
int "Backlight control pin number (-1 for not used)"
default -1
choice
prompt "backlight active polarity"
default BSP_LCD_BACKLIGHT_ACTIVE_LOW
config BSP_LCD_BACKLIGHT_ACTIVE_LOW
bool "lcd backlight on low level"
config BSP_LCD_BACKLIGHT_ACTIVE_HIGH
bool "lcd_backlight on high level"
endchoice
config BSP_LCD_CLK_FREQ
int "Lcd max clk frequency"
default 15000000
choice
prompt "lcd scan direction"
default BSP_BOARD_KD233
config BSP_BOARD_KD233
bool "board_kd233 lcd scan: DIR_YX_RLUD"
config BSP_BOARD_K210_OPENMV_TEST
bool "board_k210_openmv lcd scan: DIR_YX_LRUD"
config BSP_BOARD_USER
bool "board_user: user defined."
endchoice
config BSP_LCD_X_MAX
int "LCD Height"
default 240
config BSP_LCD_Y_MAX
int "LCD Width"
default 320
endif
menuconfig BSP_USING_SDCARD
bool "Enable SDCARD (spi1(ss0))"
select BSP_USING_SPI1
select BSP_SPI1_USING_SS0
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
select RT_USING_SPI_MSD
default n
menuconfig BSP_USING_DVP
bool "Enable DVP(camera)"
default n
if BSP_USING_DVP
comment "The default pin assignment is based on the Maix Duino K210 development board"
config BSP_DVP_SCCB_SDA_PIN
int "SCCB SDA pin number for camera"
default 40
config BSP_DVP_SCCB_SCLK_PIN
int "SCCB SCLK pin number for camera"
default 41
config BSP_DVP_CMOS_RST_PIN
int "CMOS RST pin number for camera"
default 42
config BSP_DVP_CMOS_VSYNC_PIN
int "CMOS VSYNC pin number for camera"
default 43
config BSP_DVP_CMOS_PWDN_PIN
int "CMOS PWDN pin number for camera"
default 44
config BSP_DVP_CMOS_XCLK_PIN
int "CMOS XCLK pin number for camera"
default 46
config BSP_DVP_CMOS_PCLK_PIN
int "CMOS PCLK pin number for camera"
default 47
config BSP_DVP_CMOS_HREF_PIN
int "CMOS HREF pin number for camera"
default 45
endif
if PKG_USING_RW007
config RW007_SPIDEV_NAME
string "the SPIDEV rw007 driver on"
default "spi11"
config RW007_INT_BUSY_PIN
int "rw007 int pin for rw007"
default 7
config RW007_RST_PIN
int "rw007 rst pin for rw007"
default 6
endif
endmenu
menuconfig BSP_USING_CH438
bool "Enable CH438"
default y
if BSP_USING_CH438
config BSP_CH438_ALE_PIN
int "ale pin number for ch438"
default 23
config BSP_CH438_NWR_PIN
int "nwr pin number for ch438"
default 24
config BSP_CH438_NRD_PIN
int "nrd pin number for ch438"
default 25
config BSP_CH438_D0_PIN
int "d0 pin number for ch438"
default 27
config BSP_CH438_D1_PIN
int "d1 pin number for ch438"
default 28
config BSP_CH438_D2_PIN
int "d2 pin number for ch438"
default 29
config BSP_CH438_D3_PIN
int "d3 pin number for ch438"
default 30
config BSP_CH438_D4_PIN
int "d4 pin number for ch438"
default 31
config BSP_CH438_D5_PIN
int "d5 pin number for ch438"
default 32
config BSP_CH438_D6_PIN
int "d6 pin number for ch438"
default 33
config BSP_CH438_D7_PIN
int "d7 pin number for ch438"
default 34
config BSP_CH438_INT_PIN
int "int pin number for ch438"
default 35
endif

51
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/SConscript Normal file
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import os
import rtconfig
from building import *
cwd = GetCurrentDir()
drv_path = cwd+"/../../../rt-thread/bsp/k210/driver/"
src = [
'board.c',
'heap.c',
drv_path + 'drv_uart.c',
'drv_interrupt.c',
'drv_io_config.c',
'dmalock.c'
]
CPPPATH = [cwd,drv_path]
if GetDepend('RT_USING_PIN'):
src += ['drv_gpio.c']
if GetDepend('RT_USING_HWTIMER'):
src += [drv_path + 'drv_hw_timer.c']
if GetDepend('RT_USING_I2C'):
src += [drv_path + 'drv_i2c.c']
if GetDepend('RT_USING_SPI'):
src += ['drv_spi.c']
if GetDepend('RT_USING_PWM'):
src += [drv_path + 'drv_pwm.c']
if GetDepend('RT_USING_WDT'):
src += [drv_path + 'drv_wdt.c']
# if GetDepend('BSP_USING_SDCARD'):
# src += ['sdcard_port.c']
# if GetDepend('BSP_USING_DVP'):
# src += ['drv_dvp.c']
# if GetDepend('BSP_USING_LCD'):
# src += ['drv_lcd.c']
# src += ['drv_mpylcd.c']
if GetDepend('BSP_USING_CH438'):
src += ['ch438.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

144
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/board.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "tick.h"
#include "drv_uart.h"
#include "encoding.h"
#include "fpioa.h"
#include "dmac.h"
#include "dmalock.h"
void init_bss(void)
{
unsigned int *dst;
dst = &__bss_start;
while (dst < &__bss_end)
{
*dst++ = 0;
}
}
void primary_cpu_entry(void)
{
extern void entry(void);
/* disable global interrupt */
init_bss();
rt_hw_interrupt_disable();
entry();
}
#include <clint.h>
#include <sysctl.h>
int freq(void)
{
rt_uint64_t value = 0;
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL0);
rt_kprintf("PLL0: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL1);
rt_kprintf("PLL1: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL2);
rt_kprintf("PLL2: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU);
rt_kprintf("CPU : %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB0);
rt_kprintf("APB0: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB1);
rt_kprintf("APB1: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB2);
rt_kprintf("APB2: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_HCLK);
rt_kprintf("HCLK: %d\n", value);
value = clint_get_time();
rt_kprintf("mtime: %d\n", value);
return 0;
}
MSH_CMD_EXPORT(freq, show freq info);
#ifdef RT_USING_SMP
extern int rt_hw_clint_ipi_enable(void);
#endif
extern int io_config_init(void);
void rt_hw_board_init(void)
{
sysctl_pll_set_freq(SYSCTL_PLL0, 800000000UL);
sysctl_pll_set_freq(SYSCTL_PLL1, 400000000UL);
sysctl_pll_set_freq(SYSCTL_PLL2, 45158400UL);
sysctl_clock_set_threshold(SYSCTL_THRESHOLD_APB1, 2);
/* Init FPIOA */
fpioa_init();
io_config_init();
/* Dmac init */
dmac_init();
dmalock_init();
/* initalize interrupt */
rt_hw_interrupt_init();
/* initialize hardware interrupt */
rt_hw_uart_init();
rt_hw_tick_init();
#ifdef RT_USING_SMP
rt_hw_clint_ipi_enable();
#endif
#ifdef RT_USING_CONSOLE
/* set console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif /* RT_USING_CONSOLE */
#ifdef RT_USING_HEAP
rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t) RT_HW_HEAP_BEGIN, (rt_ubase_t) RT_HW_HEAP_END);
/* initialize memory system */
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}
void rt_hw_cpu_reset(void)
{
sysctl->soft_reset.soft_reset = 1;
while(1);
}
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
/**
* This function will delay for some us.
*
* @param us the delay time of us
*/
void rt_hw_us_delay(rt_uint32_t usec)
{
rt_uint32_t cycle = read_cycle();
rt_uint32_t nop_all = usec * sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / 1000000UL;
while (1)
{
if(read_cycle() - cycle >= nop_all)
break;
}
}

26
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/board.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
*/
#ifndef BOARD_H__
#define BOARD_H__
#include "fpioa.h"
#include "platform.h"
#include <rtconfig.h>
extern unsigned int __bss_start;
extern unsigned int __bss_end;
#define RT_HW_HEAP_BEGIN (void*)&__bss_end
#define RT_HW_HEAP_END (void*)(0x80000000 + 6 * 1024 * 1024)
void rt_hw_board_init(void);
#endif

484
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/ch438.c Normal file
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#include <rtthread.h>
#include <rtdevice.h>
#include <drv_io_config.h>
#include <gpiohs.h>
#include "board.h"
#include "ch438.h"
#include "sleep.h"
#include <math.h>
static rt_uint8_t offsetadd[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* Offset address of serial port number */
struct rt_serial_device *extuart_serial_parm[8];
void CH438_INIT(void)
{
CH438_set_output();
gpiohs_set_drive_mode(FPIOA_CH438_NWR, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_NRD, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_ALE, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_drive_mode(FPIOA_485_DIR, GPIO_DM_OUTPUT);
gpiohs_set_pin(FPIOA_CH438_NWR, GPIO_PV_HIGH);
gpiohs_set_pin(FPIOA_CH438_NRD, GPIO_PV_HIGH);
gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH);
}
void CH438_PORT_INIT( rt_uint8_t ext_uart_no,rt_uint32_t BaudRate )
{
rt_uint32_t div;
rt_uint8_t DLL,DLM,dlab;
rt_uint8_t REG_LCR_ADDR;
rt_uint8_t REG_DLL_ADDR;
rt_uint8_t REG_DLM_ADDR;
rt_uint8_t REG_IER_ADDR;
rt_uint8_t REG_MCR_ADDR;
rt_uint8_t REG_FCR_ADDR;
rt_uint8_t REG_RBR_ADDR;
rt_uint8_t REG_THR_ADDR;
rt_uint8_t REG_IIR_ADDR;
REG_LCR_ADDR = offsetadd[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offsetadd[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offsetadd[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offsetadd[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offsetadd[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offsetadd[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offsetadd[ext_uart_no] | REG_IIR0_ADDR;
WriteCH438Data( REG_IER_ADDR, BIT_IER_RESET ); /* Reset the serial port */
rt_thread_delay(50);
dlab = ReadCH438Data(REG_IER_ADDR);
dlab &= 0xDF;
WriteCH438Data(REG_IER_ADDR, dlab);
dlab = ReadCH438Data(REG_LCR_ADDR);
dlab |= 0x80;
WriteCH438Data(REG_LCR_ADDR, dlab);
div = ( Fpclk >> 4 ) / BaudRate;
DLM = div >> 8;
DLL = div & 0xff;
WriteCH438Data( REG_DLL_ADDR, DLL ); /* Set baud rate */
WriteCH438Data( REG_DLM_ADDR, DLM );
WriteCH438Data( REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN ); /* Set FIFO mode */
WriteCH438Data( REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0 );
WriteCH438Data( REG_IER_ADDR, /*BIT_IER_IEMODEM | BIT_IER_IETHRE | BIT_IER_IELINES | */BIT_IER_IERECV );
WriteCH438Data( REG_MCR_ADDR, BIT_MCR_OUT2 );
WriteCH438Data(REG_FCR_ADDR,ReadCH438Data(REG_FCR_ADDR)| BIT_FCR_RFIFORST | BIT_FCR_TFIFORST);
}
static void CH438_set_output(void)
{
gpiohs_set_drive_mode(FPIOA_CH438_D0, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_D1, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_D2, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_D3, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_D4, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_D5, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_D6, GPIO_DM_OUTPUT);
gpiohs_set_drive_mode(FPIOA_CH438_D7, GPIO_DM_OUTPUT);
}
static void CH438_set_input(void)
{
gpiohs_set_drive_mode(FPIOA_CH438_D0, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_drive_mode(FPIOA_CH438_D1, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_drive_mode(FPIOA_CH438_D2, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_drive_mode(FPIOA_CH438_D3, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_drive_mode(FPIOA_CH438_D4, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_drive_mode(FPIOA_CH438_D5, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_drive_mode(FPIOA_CH438_D6, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_drive_mode(FPIOA_CH438_D7, GPIO_DM_INPUT_PULL_UP);
}
void set_485_input(rt_uint8_t ch_no)
{
if(ch_no == 1)
gpiohs_set_pin(FPIOA_485_DIR, GPIO_PV_LOW);
}
void set_485_output(rt_uint8_t ch_no)
{
if(ch_no == 1)
gpiohs_set_pin(FPIOA_485_DIR, GPIO_PV_HIGH);
}
rt_uint8_t ReadCH438Data( rt_uint8_t addr )
{
rt_uint8_t dat = 0;
gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_HIGH);
gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_HIGH);
gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_HIGH);
CH438_set_output();
usleep(1);
if(addr &0x80) gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_LOW);
if(addr &0x40) gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_LOW);
if(addr &0x20) gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_LOW);
if(addr &0x10) gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_LOW);
if(addr &0x08) gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_LOW);
if(addr &0x04) gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_LOW);
if(addr &0x02) gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_LOW);
if(addr &0x01) gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_LOW);
usleep(1);
gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_LOW);
usleep(1);
CH438_set_input();
usleep(1);
gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_LOW);
usleep(1);
dat = 0;
if (gpiohs_get_pin(FPIOA_CH438_D7)) dat |= 0x80;
if (gpiohs_get_pin(FPIOA_CH438_D6)) dat |= 0x40;
if (gpiohs_get_pin(FPIOA_CH438_D5)) dat |= 0x20;
if (gpiohs_get_pin(FPIOA_CH438_D4)) dat |= 0x10;
if (gpiohs_get_pin(FPIOA_CH438_D3)) dat |= 0x08;
if (gpiohs_get_pin(FPIOA_CH438_D2)) dat |= 0x04;
if (gpiohs_get_pin(FPIOA_CH438_D1)) dat |= 0x02;
if (gpiohs_get_pin(FPIOA_CH438_D0)) dat |= 0x01;
gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_HIGH);
gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_HIGH);
usleep(1);
return dat;
}
static void WriteCH438Data( rt_uint8_t addr, rt_uint8_t dat)
{
gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_HIGH);
gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_HIGH);
gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_HIGH);
CH438_set_output();
usleep(1);
if(addr &0x80) gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_LOW);
if(addr &0x40) gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_LOW);
if(addr &0x20) gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_LOW);
if(addr &0x10) gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_LOW);
if(addr &0x08) gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_LOW);
if(addr &0x04) gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_LOW);
if(addr &0x02) gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_LOW);
if(addr &0x01) gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_LOW);
usleep(1);
gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_LOW);
usleep(1);
if(dat &0x80) gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_LOW);
if(dat &0x40) gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_LOW);
if(dat &0x20) gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_LOW);
if(dat &0x10) gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_LOW);
if(dat &0x08) gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_LOW);
if(dat &0x04) gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_LOW);
if(dat &0x02) gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_LOW);
if(dat &0x01) gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_LOW);
usleep(1);
gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_LOW);
usleep(1);
gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_HIGH);
gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_HIGH);
usleep(1);
CH438_set_input();
return;
}
static void WriteCH438Block( rt_uint8_t mAddr, rt_uint8_t mLen, rt_uint8_t *mBuf )
{
while ( mLen -- )
WriteCH438Data( mAddr, *mBuf++ );
}
static int Ch438Irq(void *parameter)
{
rt_uint8_t gInterruptStatus;
rt_uint8_t port = 0;
struct rt_serial_device *serial = (struct rt_serial_device *)parameter;
/* multi irq may happen*/
gInterruptStatus = ReadCH438Data(REG_SSR_ADDR);
port = log(gInterruptStatus & 0xFF)/log(2);
rt_hw_serial_isr(extuart_serial_parm[port], RT_SERIAL_EVENT_RX_IND);
}
static rt_err_t rt_extuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
rt_uint32_t baud_rate = cfg->baud_rate;
rt_uint16_t port = cfg->reserved;
CH438_PORT_INIT(port, baud_rate);
return RT_EOK;
}
static rt_err_t extuart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
rt_uint16_t ext_uart_no = serial->config.reserved;
static rt_uint16_t register_flag = 0;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
if(1 == register_flag)
{
gpiohs_irq_unregister(FPIOA_CH438_INT);
register_flag = 0;
}
break;
case RT_DEVICE_CTRL_SET_INT:
if(0 == register_flag)
{
gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP);
gpiohs_set_pin_edge(FPIOA_CH438_INT,GPIO_PE_FALLING);
gpiohs_irq_register(FPIOA_CH438_INT, 1, Ch438Irq, (void*)serial);
register_flag = 1;
}
break;
}
return (RT_EOK);
}
static int drv_extuart_putc(struct rt_serial_device *serial, char c)
{
uint16_t ext_uart_no = serial->config.reserved;
rt_uint8_t REG_LSR_ADDR,REG_THR_ADDR;
REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
if((ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_TEMT) != 0)
{
WriteCH438Block( REG_THR_ADDR, 1, &c );
return 1;
} else {
return 0;
}
}
static int drv_extuart_getc(struct rt_serial_device *serial)
{
rt_uint8_t dat = 0;
rt_uint8_t REG_LSR_ADDR,REG_RBR_ADDR;
uint16_t ext_uart_no = serial->config.reserved;///< get extern uart port
REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
if((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0x01)
{
dat = ReadCH438Data( REG_RBR_ADDR );
if(dat >= 0)
return dat;
} else {
return -1;
}
}
const struct rt_uart_ops extuart_ops =
{
rt_extuart_configure,
extuart_control,
drv_extuart_putc,
drv_extuart_getc,
RT_NULL
};
int rt_hw_ch438_init(void)
{
struct rt_serial_device *extserial;
struct device_uart *extuart;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
rt_err_t ret;
{
static struct rt_serial_device extserial0;
extserial = &extserial0;
extserial->ops = &extuart_ops;
extserial->config = config;
extserial->config.baud_rate = 115200;
extserial->config.reserved = 0; ///< extern uart port
extuart_serial_parm[0] = &extserial0;
ret = rt_hw_serial_register(extserial,
"extuart_dev0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
extuart);
if(ret < 0){
rt_kprintf("extuart_dev0 register failed.\n");
}
}
{
static struct rt_serial_device extserial1;
extserial = &extserial1;
extserial->ops = &extuart_ops;
extserial->config = config;
extserial->config.baud_rate = 9600;
extserial->config.reserved = 1; ///< extern uart port
extuart_serial_parm[1] = &extserial1;
ret = rt_hw_serial_register(extserial,
"extuart_dev1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
extuart);
if(ret < 0){
rt_kprintf("extuart_dev1 register failed.\n");
}
}
{
static struct rt_serial_device extserial2;
extserial = &extserial2;
extserial->ops = &extuart_ops;
extserial->config = config;
extserial->config.baud_rate = 9600;
extserial->config.reserved = 2; ///< extern uart port
extuart_serial_parm[2] = &extserial2;
ret = rt_hw_serial_register(extserial,
"extuart_dev2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
extuart);
if(ret < 0){
rt_kprintf("extuart_dev2 register failed.\n");
}
}
{
static struct rt_serial_device extserial3;
extserial = &extserial3;
extserial->ops = &extuart_ops;
extserial->config = config;
extserial->config.baud_rate = 9600;
extserial->config.reserved = 3; ///< extern uart port
ret = rt_hw_serial_register(extserial,
"extuart_dev3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
extuart);
if(ret < 0){
rt_kprintf("extuart_dev3 register failed.\n");
}
extuart_serial_parm[3] = &extserial3;
}
{
static struct rt_serial_device extserial4;
extserial = &extserial4;
extserial->ops = &extuart_ops;
extserial->config = config;
extserial->config.baud_rate = 9600;
extserial->config.reserved = 4; ///< extern uart port
ret = rt_hw_serial_register(extserial,
"extuart_dev4",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
extuart);
if(ret < 0){
rt_kprintf("extuart_dev4 register failed.\n");
}
extuart_serial_parm[4] = &extserial4;
}
{
static struct rt_serial_device extserial5;
extserial = &extserial5;
extserial->ops = &extuart_ops;
extserial->config = config;
extserial->config.baud_rate = 115200;
extserial->config.reserved = 5; ///< extern uart port
ret = rt_hw_serial_register(extserial,
"extuart_dev5",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
extuart);
if(ret < 0){
rt_kprintf("extuart_dev5 register failed.\n");
}
extuart_serial_parm[5] = &extserial5;
}
{
static struct rt_serial_device extserial6;
extserial = &extserial6;
extserial->ops = &extuart_ops;
extserial->config = config;
extserial->config.baud_rate = 57600;
extserial->config.reserved = 6; ///< extern uart port
ret = rt_hw_serial_register(extserial,
"extuart_dev6",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
extuart);
if(ret < 0){
rt_kprintf("extuart_dev6 register failed.\n");
}
extuart_serial_parm[6] = &extserial6;
}
{
static struct rt_serial_device extserial7;
extserial = &extserial7;
extserial->ops = &extuart_ops;
extserial->config = config;
extserial->config.baud_rate = 9600;
extserial->config.reserved = 7; ///< extern uart port
ret = rt_hw_serial_register(extserial,
"extuart_dev7",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
extuart);
if(ret < 0){
rt_kprintf("extuart_dev7 register failed.\n");
}
extuart_serial_parm[7] = &extserial7;
}
CH438_INIT();
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_ch438_init);

251
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/ch438.h Executable file
View File

@@ -0,0 +1,251 @@
#ifndef __CH438_H_
#define __CH438_H_
#include "board.h"
#define BUFFSIZE 255
/******************************************************************************************/
/* CH438serial port0 register address */
#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */
#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */
#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */
#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */
#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */
#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */
#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */
#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */
#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */
#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */
#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port1 register address */
#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */
#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */
#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */
#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */
#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */
#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */
#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */
#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */
#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */
#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */
#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port2 register address */
#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */
#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */
#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */
#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */
#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */
#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */
#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */
#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */
#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */
#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */
#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port3 register address */
#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */
#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */
#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */
#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */
#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */
#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */
#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */
#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */
#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */
#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */
#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port4 register address */
#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */
#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */
#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */
#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */
#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */
#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */
#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */
#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */
#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */
#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */
#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port5 register address */
#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */
#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */
#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */
#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */
#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */
#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */
#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */
#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */
#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */
#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */
#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port6 register address */
#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */
#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */
#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */
#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */
#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */
#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */
#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */
#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */
#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */
#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */
#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port7 register address */
#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */
#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */
#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */
#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */
#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */
#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */
#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */
#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */
#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */
#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */
#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */
#define REG_SSR_ADDR 0x4F /* pecial status register address */
/* IER register bit */
#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */
#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */
#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */
#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */
#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */
#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */
#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */
#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */
/* IIR register bit */
#define BIT_IIR_FIFOENS1 0x80
#define BIT_IIR_FIFOENS0 0x40 /* The two is 1 said use FIFO */
/* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted,
1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */
#define BIT_IIR_IID3 0x08
#define BIT_IIR_IID2 0x04
#define BIT_IIR_IID1 0x02
#define BIT_IIR_NOINT 0x01
/* FCR register bit */
/* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */
#define BIT_FCR_RECVTG1 0x80 /* Set the trigger point for FIFO interruption and automatic hardware flow control */
#define BIT_FCR_RECVTG0 0x40 /* Set the trigger point for FIFO interruption and automatic hardware flow control */
#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */
#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */
#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */
/* LCR register bit */
#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */
#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/
/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */
#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */
#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */
#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */
#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */
/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */
#define BIT_LCR_WORDSZ1 0x02 /* Set the word length length */
#define BIT_LCR_WORDSZ0 0x01
/* MCR register bit */
#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */
#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */
#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */
#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */
#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */
#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */
/* LSR register bit */
#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */
#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */
#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/
#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/
#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */
#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */
#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */
#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */
/* MSR register bit */
#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */
#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */
#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */
#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */
#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */
#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */
#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */
#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */
/* Interrupt status code */
#define INT_NOINT 0x01 /* There is no interruption */
#define INT_THR_EMPTY 0x02 /* THR empty interruption */
#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */
#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */
#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */
#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */
#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */
#define Fpclk 1843200 /* Define the internal clock frequency */
void CH438_INIT(void);
void CH438_PORT_INIT( rt_uint8_t ext_uart_no,rt_uint32_t BaudRate );
rt_uint8_t ReadCH438Data( rt_uint8_t addr );
void CH438UARTSend( rt_uint8_t ext_uart_no,rt_uint8_t *Data, rt_uint8_t Num );
rt_uint8_t CH438UARTRcv( rt_uint8_t ext_uart_no, rt_uint8_t* buf );
void set_485_input(rt_uint8_t ch_no);
void set_485_output(rt_uint8_t ch_no);
static void CH438_set_output(void);
static void CH438_set_input(void);
static void WriteCH438Data( rt_uint8_t addr, rt_uint8_t dat);
static void WriteCH438Block( rt_uint8_t mAddr, rt_uint8_t mLen, rt_uint8_t *mBuf );
#endif

90
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/dmalock.c Normal file
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/* Copyright Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <rtthread.h>
#include "dmalock.h"
struct dmac_host
{
struct rt_semaphore sem;
struct rt_mutex mutex;
uint8_t channel_used[DMAC_CHANNEL_COUNT];
char *channel_name[DMAC_CHANNEL_COUNT];
};
static struct dmac_host _dmac_host;
void dmalock_init(void)
{
rt_sem_init(&_dmac_host.sem, "dma_sem", DMAC_CHANNEL_COUNT, RT_IPC_FLAG_FIFO);
rt_mutex_init(&_dmac_host.mutex, "dma_mutex", RT_IPC_FLAG_FIFO);
for (int i = 0; i < DMAC_CHANNEL_COUNT; i++)
{
_dmac_host.channel_used[i] = 0;
_dmac_host.channel_name[i] = NULL;
}
}
int _dmalock_sync_take(dmac_channel_number_t *chn, int timeout_ms, const char *name)
{
rt_err_t result;
*chn = DMAC_CHANNEL_MAX;
result = rt_sem_take(&_dmac_host.sem, timeout_ms);
if (result == RT_EOK)
{
rt_mutex_take(&_dmac_host.mutex, RT_WAITING_FOREVER);
for (int i = 0; i < DMAC_CHANNEL_COUNT; i++)
{
if (_dmac_host.channel_used[i] == 0)
{
_dmac_host.channel_used[i] = 1;
_dmac_host.channel_name[i] = name;
*chn = i;
break;
}
}
rt_mutex_release(&_dmac_host.mutex);
}
return result;
}
void dmalock_release(dmac_channel_number_t chn)
{
if (chn >= DMAC_CHANNEL_MAX)
return;
_dmac_host.channel_name[chn] = NULL;
_dmac_host.channel_used[chn] = 0;
rt_sem_release(&_dmac_host.sem);
}
static void dma_ch_info(int argc, char **argv)
{
uint32_t cnt = 0;
for (int i = 0; i < DMAC_CHANNEL_COUNT; i++)
{
if (_dmac_host.channel_used[i] != 0)
{
rt_kprintf("dma_ch%d is using by func [%s]\n", i, _dmac_host.channel_name[i]);
cnt++;
}
}
if(cnt == 0)
rt_kprintf(" no dma_ch is using.\n");
}
MSH_CMD_EXPORT(dma_ch_info, list dma channel informationn.);

14
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/dmalock.h Normal file
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#ifndef __DMALOCK_H
#define __DMALOCK_H
#include <stdint.h>
#include <rtdef.h>
#include <dmac.h>
#define dmalock_sync_take(x,y) _dmalock_sync_take(x, y, __func__)
void dmalock_init(void);
int _dmalock_sync_take(dmac_channel_number_t *chn, int timeout_ms, const char *name);
void dmalock_release(dmac_channel_number_t chn);
#endif

167
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/drv_dvp.c Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-27 tianchunyu the first version
*/
#include <rtthread.h>
#include <stdio.h>
#ifdef BSP_USING_DVP
#include <drv_dvp.h>
#define DRV_DEBUG
#define LOG_TAG "drv.dvp"
#define DBG_LVL DBG_LOG
#include <rtdbg.h>
static struct kendryte_dvp rt_dvp = {0};
static void (*dvp_irq_callback)(void) = NULL;
/*
the camera starts transfering photos
*/
static int on_irq_dvp(void* ctx)
{
if (dvp_get_interrupt(DVP_STS_FRAME_FINISH))
{
rt_dvp_stop();
dvp_clear_interrupt(DVP_STS_FRAME_FINISH);
(*dvp_irq_callback)();
}
return 0;
}
void rt_dvp_start(uint32_t pData, uint32_t Length)
{
dvp_set_display_addr(pData);
dvp_config_interrupt(DVP_CFG_FINISH_INT_ENABLE, 1);
dvp_start_convert();
}
/*
the camera stops transfering photos
*/
void rt_dvp_stop(void)
{
dvp_config_interrupt(DVP_CFG_FINISH_INT_ENABLE, 0);
}
static rt_err_t rt_dvp_init(rt_device_t dev)
{
//sysctl_pll_set_freq(SYSCTL_PLL2, 45158400UL);
RT_ASSERT(dev != RT_NULL);
rt_err_t result = RT_EOK;
/* Init DVP IO map and function settings io pin serial number depends on schematic diagram
initialize io in io_config_init function*/
/*ov2640 dvp interface initialize*/
dvp_init(8);
dvp_set_xclk_rate(24000000);
dvp_enable_burst();
dvp_set_output_enable(0, 1);
dvp_set_output_enable(1, 1);
dvp_set_image_format(DVP_CFG_RGB_FORMAT);////////////////
dvp_set_image_size(320, 240); // default
dvp_config_interrupt(DVP_CFG_FINISH_INT_ENABLE, 0);
dvp_disable_auto();
plic_set_priority(IRQN_DVP_INTERRUPT, 1);
plic_irq_register(IRQN_DVP_INTERRUPT, on_irq_dvp, NULL);
plic_irq_enable(IRQN_DVP_INTERRUPT);
dvp_clear_interrupt(DVP_STS_FRAME_FINISH);
LOG_I("dvp initialize success");
return result;
}
static rt_err_t rt_dvp_open(rt_device_t dev, rt_uint16_t oflag)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_err_t rt_dvp_close(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_err_t rt_dvp_control(rt_device_t dev, int cmd, void *args)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_size_t rt_dvp_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_size_t rt_dvp_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
rt_err_t rt_set_irq_dvp_callback_hander(void (*p)(void))
{
if(NULL == p)
{
LOG_E("set irq dcmi callback hander is NULL");
return RT_ERROR;
}
dvp_irq_callback = p;
return RT_EOK;
}
int kendryte_dvp_init(void)
{
int ret = 0;
rt_device_t dvp_dev = RT_NULL;
rt_dvp.dev.parent.type = RT_Device_Class_Miscellaneous;
rt_dvp.dev.parent.init = rt_dvp_init;
rt_dvp.dev.parent.open = rt_dvp_open;
rt_dvp.dev.parent.close = rt_dvp_close;
rt_dvp.dev.parent.read = rt_dvp_read;
rt_dvp.dev.parent.write = rt_dvp_write;
rt_dvp.dev.parent.control = rt_dvp_control;
rt_dvp.dev.parent.user_data = RT_NULL;
ret = rt_device_register(&rt_dvp.dev.parent, "dvp", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
if(ret != RT_EOK)
{
LOG_E("dvp register fail!!\n\r");
return -RT_ERROR;
}
LOG_I("dvp register successfully");
dvp_dev = rt_device_find("dvp");
if (dvp_dev == RT_NULL)
{
LOG_E("can't find dvp device!");
return RT_ERROR;
}
ret = rt_device_open(dvp_dev, RT_DEVICE_FLAG_RDWR);
if(ret != RT_EOK)
{
LOG_E("can't open dvp device!");
return RT_ERROR;
}
LOG_I("dvp open successfully");
return RT_EOK;
}
INIT_BOARD_EXPORT(kendryte_dvp_init);
#endif

46
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/drv_dvp.h Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-27 tianchunyu the first version
*/
#ifndef __DRV_DVP_H__
#define __DRV_DVP_H__
#include <dvp.h>
#include <fpioa.h>
#include <sysctl.h>
#include <plic.h>
#include <sysctl.h>
#ifdef __cplusplus
extern "C" {
#endif
struct rt_dvp_device
{
struct rt_device parent;
};
struct kendryte_dvp
{
struct rt_dvp_device dev;
};
extern void rt_dvp_start(uint32_t pData, uint32_t Length);
extern void rt_dvp_stop(void);
extern rt_err_t rt_set_irq_dvp_callback_hander(void (*p)(void));
#ifdef __cplusplus
}
#endif
#endif

267
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/drv_gpio.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <fpioa.h>
#include <gpiohs.h>
#include "drv_gpio.h"
#include "drv_io_config.h"
#include <plic.h>
#include <rthw.h>
#include <utils.h>
#include <string.h>
#define DBG_ENABLE
#define DBG_TAG "PIN"
#define DBG_LVL DBG_WARNING
#define DBG_COLOR
#include <rtdbg.h>
#define FUNC_GPIOHS(n) (FUNC_GPIOHS0 + n)
static short pin_alloc_table[FPIOA_NUM_IO];
static uint32_t free_pin = 0;
static int alloc_pin_channel(rt_base_t pin_index)
{
if(free_pin == 32)
{
LOG_E("no free gpiohs channel to alloc");
return -1;
}
if(pin_alloc_table[pin_index] != -1)
{
LOG_W("already alloc gpiohs channel for pin %d", pin_index);
return pin_alloc_table[pin_index];
}
pin_alloc_table[pin_index] = free_pin;
free_pin++;
fpioa_set_function(pin_index, FUNC_GPIOHS(pin_alloc_table[pin_index]));
return pin_alloc_table[pin_index];
}
int get_pin_channel(rt_base_t pin_index)
{
return pin_alloc_table[pin_index];
}
static void free_pin_channel(rt_base_t pin_index)
{
if(pin_alloc_table[pin_index] == -1)
{
LOG_W("free error:not alloc gpiohs channel for pin %d", pin_index);
return;
}
pin_alloc_table[pin_index] = -1;
free_pin--;
}
static void drv_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
{
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
pin_channel = alloc_pin_channel(pin);
if(pin_channel == -1)
{
return;
}
}
switch (mode)
{
case PIN_MODE_OUTPUT:
gpiohs_set_drive_mode(pin_channel, GPIO_DM_OUTPUT);
break;
case PIN_MODE_INPUT:
gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT);
break;
case PIN_MODE_INPUT_PULLUP:
gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT_PULL_UP);
break;
case PIN_MODE_INPUT_PULLDOWN:
gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT_PULL_DOWN);
break;
default:
LOG_E("Not support mode %d", mode);
break;
}
}
static void drv_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
{
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return;
}
gpiohs_set_pin(pin_channel, value == PIN_HIGH ? GPIO_PV_HIGH : GPIO_PV_LOW);
}
static int drv_pin_read(struct rt_device *device, rt_base_t pin)
{
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return -1;
}
return gpiohs_get_pin(pin_channel) == GPIO_PV_HIGH ? PIN_HIGH : PIN_LOW;
}
static struct
{
void (*hdr)(void *args);
void* args;
gpio_pin_edge_t edge;
} irq_table[32];
static void pin_irq(int vector, void *param)
{
int pin_channel = vector - IRQN_GPIOHS0_INTERRUPT;
if(irq_table[pin_channel].edge & GPIO_PE_FALLING)
{
set_gpio_bit(gpiohs->fall_ie.u32, pin_channel, 0);
set_gpio_bit(gpiohs->fall_ip.u32, pin_channel, 1);
set_gpio_bit(gpiohs->fall_ie.u32, pin_channel, 1);
}
if(irq_table[pin_channel].edge & GPIO_PE_RISING)
{
set_gpio_bit(gpiohs->rise_ie.u32, pin_channel, 0);
set_gpio_bit(gpiohs->rise_ip.u32, pin_channel, 1);
set_gpio_bit(gpiohs->rise_ie.u32, pin_channel, 1);
}
if(irq_table[pin_channel].edge & GPIO_PE_LOW)
{
set_gpio_bit(gpiohs->low_ie.u32, pin_channel, 0);
set_gpio_bit(gpiohs->low_ip.u32, pin_channel, 1);
set_gpio_bit(gpiohs->low_ie.u32, pin_channel, 1);
}
if(irq_table[pin_channel].edge & GPIO_PE_HIGH)
{
set_gpio_bit(gpiohs->high_ie.u32, pin_channel, 0);
set_gpio_bit(gpiohs->high_ip.u32, pin_channel, 1);
set_gpio_bit(gpiohs->high_ie.u32, pin_channel, 1);
}
if(irq_table[pin_channel].hdr)
{
irq_table[pin_channel].hdr(irq_table[pin_channel].args);
}
}
static rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
int pin_channel = get_pin_channel(pin);
char irq_name[10];
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return -RT_ERROR;
}
irq_table[pin_channel].hdr = hdr;
irq_table[pin_channel].args = args;
switch (mode)
{
case PIN_IRQ_MODE_RISING:
irq_table[pin_channel].edge = GPIO_PE_RISING;
break;
case PIN_IRQ_MODE_FALLING:
irq_table[pin_channel].edge = GPIO_PE_FALLING;
break;
case PIN_IRQ_MODE_RISING_FALLING:
irq_table[pin_channel].edge = GPIO_PE_BOTH;
break;
case PIN_IRQ_MODE_HIGH_LEVEL:
irq_table[pin_channel].edge = GPIO_PE_LOW;
break;
case PIN_IRQ_MODE_LOW_LEVEL:
irq_table[pin_channel].edge = GPIO_PE_HIGH;
break;
default:
break;
}
gpiohs_set_pin_edge(pin_channel, irq_table[pin_channel].edge);
rt_snprintf(irq_name, sizeof irq_name, "pin%d", pin);
rt_hw_interrupt_install(IRQN_GPIOHS0_INTERRUPT + pin_channel, pin_irq, RT_NULL, irq_name);
return RT_EOK;
}
static rt_err_t drv_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{
rt_err_t ret = RT_EOK;
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return -RT_ERROR;
}
irq_table[pin_channel].hdr = RT_NULL;
irq_table[pin_channel].args = RT_NULL;
return ret;
}
static rt_err_t drv_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
{
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return -RT_ERROR;
}
if(enabled)
{
rt_hw_interrupt_umask(IRQN_GPIOHS0_INTERRUPT + pin_channel);
}
else
{
rt_hw_interrupt_mask(IRQN_GPIOHS0_INTERRUPT + pin_channel);
}
return RT_EOK;
}
const static struct rt_pin_ops drv_pin_ops =
{
drv_pin_mode,
drv_pin_write,
drv_pin_read,
drv_pin_attach_irq,
drv_pin_detach_irq,
drv_pin_irq_enable
};
int rt_hw_pin_init(void)
{
rt_err_t ret = RT_EOK;
memset(pin_alloc_table, 0xff, sizeof pin_alloc_table);
free_pin = GPIO_ALLOC_START;
ret = rt_device_pin_register("pin", &drv_pin_ops, RT_NULL);
return ret;
}
INIT_BOARD_EXPORT(rt_hw_pin_init);

16
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/drv_gpio.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#ifndef DRV_GPIO_H__
#define DRV_GPIO_H__
int rt_hw_pin_init(void);
#endif

27
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/drv_interrupt.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#include <plic.h>
void plic_irq_handle(plic_irq_t irq)
{
plic_instance_t (*plic_instance)[IRQN_MAX] = plic_get_instance();
if (plic_instance[0][irq].callback)
{
plic_instance[0][irq].callback(
plic_instance[0][irq].ctx);
}
else if (plic_instance[1][irq].callback)
{
plic_instance[1][irq].callback(
plic_instance[1][irq].ctx);
}
}

233
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/drv_io_config.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#include <rtthread.h>
#include <fpioa.h>
#include <drv_io_config.h>
#include <sysctl.h>
#define HS_GPIO(n) (FUNC_GPIOHS0 + n)
#define IOCONFIG(pin,func) {pin, func, #func}
static struct io_config
{
int io_num;
fpioa_function_t func;
const char * func_name;
} io_config[] =
{
#ifdef BSP_USING_LCD
IOCONFIG(BSP_LCD_CS_PIN, FUNC_SPI0_SS0), /* LCD CS PIN */
IOCONFIG(BSP_LCD_WR_PIN, FUNC_SPI0_SCLK), /* LCD WR PIN */
IOCONFIG(BSP_LCD_DC_PIN, HS_GPIO(LCD_DC_PIN)), /* LCD DC PIN */
#if BSP_LCD_RST_PIN >= 0
IOCONFIG(BSP_LCD_RST_PIN, HS_GPIO(LCD_RST_PIN)), /* LCD RESET PIN */
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
IOCONFIG(BSP_LCD_BACKLIGHT_PIN, HS_GPIO(LCD_BACKLIGHT_PIN)), /* LCD BACKLIGHT PIN */
#endif
#endif
#ifdef BSP_USING_DVP
IOCONFIG(BSP_DVP_SCCB_SDA_PIN, FUNC_SCCB_SDA),
IOCONFIG(BSP_DVP_SCCB_SCLK_PIN, FUNC_SCCB_SCLK),
IOCONFIG(BSP_DVP_CMOS_RST_PIN, FUNC_CMOS_RST),
IOCONFIG(BSP_DVP_CMOS_VSYNC_PIN, FUNC_CMOS_VSYNC),
IOCONFIG(BSP_DVP_CMOS_PWDN_PIN, FUNC_CMOS_PWDN),
IOCONFIG(BSP_DVP_CMOS_XCLK_PIN, FUNC_CMOS_XCLK),
IOCONFIG(BSP_DVP_CMOS_PCLK_PIN, FUNC_CMOS_PCLK),
IOCONFIG(BSP_DVP_CMOS_HREF_PIN, FUNC_CMOS_HREF),
#endif
#ifdef BSP_USING_SPI1
IOCONFIG(BSP_SPI1_CLK_PIN, FUNC_SPI1_SCLK),
IOCONFIG(BSP_SPI1_D0_PIN, FUNC_SPI1_D0),
IOCONFIG(BSP_SPI1_D1_PIN, FUNC_SPI1_D1),
#ifdef BSP_USING_SPI1_AS_QSPI
IOCONFIG(BSP_SPI1_D2_PIN, FUNC_SPI1_D2),
IOCONFIG(BSP_SPI1_D3_PIN, FUNC_SPI1_D3),
#endif
#ifdef BSP_SPI1_USING_SS0
IOCONFIG(BSP_SPI1_SS0_PIN, HS_GPIO(SPI1_CS0_PIN)),
#endif
#ifdef BSP_SPI1_USING_SS1
IOCONFIG(BSP_SPI1_SS1_PIN, HS_GPIO(SPI1_CS1_PIN)),
#endif
#ifdef BSP_SPI1_USING_SS2
IOCONFIG(BSP_SPI1_SS2_PIN, HS_GPIO(SPI1_CS2_PIN)),
#endif
#ifdef BSP_SPI1_USING_SS3
IOCONFIG(BSP_SPI1_SS3_PIN, HS_GPIO(SPI1_CS3_PIN)),
#endif
#endif
#ifdef BSP_USING_UART1
IOCONFIG(BSP_UART1_TXD_PIN, FUNC_UART1_TX),
IOCONFIG(BSP_UART1_RXD_PIN, FUNC_UART1_RX),
#if BSP_UART1_RTS_PIN >= 0
IOCONFIG(BSP_UART1_RTS_PIN, FUNC_UART1_RTS),
#endif
#if BSP_UART1_CTS_PIN >= 0
IOCONFIG(BSP_UART1_CTS_PIN, FUNC_UART1_CTS),
#endif
#endif
#ifdef BSP_USING_UART2
IOCONFIG(BSP_UART2_TXD_PIN, FUNC_UART2_TX),
IOCONFIG(BSP_UART2_RXD_PIN, FUNC_UART2_RX),
#if BSP_UART2_RTS_PIN >= 0
IOCONFIG(BSP_UART2_RTS_PIN, FUNC_UART2_RTS),
#endif
#if BSP_UART2_CTS_PIN >= 0
IOCONFIG(BSP_UART2_CTS_PIN, FUNC_UART2_CTS),
#endif
#endif
#ifdef BSP_USING_UART3
IOCONFIG(BSP_UART3_TXD_PIN, FUNC_UART3_TX),
IOCONFIG(BSP_UART3_RXD_PIN, FUNC_UART3_RX),
#if BSP_UART3_RTS_PIN >= 0
IOCONFIG(BSP_UART3_RTS_PIN, FUNC_UART3_RTS),
#endif
#if BSP_UART3_CTS_PIN >= 0
IOCONFIG(BSP_UART3_CTS_PIN, FUNC_UART3_CTS),
#endif
#endif
#ifdef BSP_USING_I2C0
IOCONFIG(BSP_I2C0_SCL_PIN, FUNC_I2C0_SCLK),
IOCONFIG(BSP_I2C0_SDA_PIN, FUNC_I2C0_SDA),
#endif
#ifdef BSP_USING_I2C1
IOCONFIG(BSP_I2C1_SCL_PIN, FUNC_I2C1_SCLK),
IOCONFIG(BSP_I2C1_SDA_PIN, FUNC_I2C1_SDA),
#endif
#ifdef BSP_USING_I2C2
IOCONFIG(BSP_I2C2_SCL_PIN, FUNC_I2C2_SCLK),
IOCONFIG(BSP_I2C2_SDA_PIN, FUNC_I2C2_SDA),
#endif
#ifdef BSP_USING_I2S0
IOCONFIG(BSP_I2S0_OUT_D1_PIN, FUNC_I2S0_OUT_D1),
IOCONFIG(BSP_I2S0_WS_PIN, FUNC_I2S0_WS),
IOCONFIG(BSP_I2S0_SCLK_PIN, FUNC_I2S0_SCLK),
#endif
#ifdef BSP_USING_I2S1
IOCONFIG(BSP_I2S1_IN_D0_PIN, FUNC_I2S1_IN_D0),
IOCONFIG(BSP_I2S1_WS_PIN, FUNC_I2S1_WS),
IOCONFIG(BSP_I2S1_SCLK_PIN, FUNC_I2S1_SCLK),
#endif
#ifdef BSP_USING_I2S2
IOCONFIG(BSP_I2S2_OUT_D1_PIN, FUNC_I2S2_OUT_D1),
IOCONFIG(BSP_I2S2_WS_PIN, FUNC_I2S2_WS),
IOCONFIG(BSP_I2S2_SCLK_PIN, FUNC_I2S2_SCLK),
#endif
#ifdef BSP_PWM_CHN0_ENABLE
IOCONFIG(BSP_PWM_CHN0_PIN, FUNC_TIMER2_TOGGLE1),
#endif
#ifdef BSP_PWM_CHN1_ENABLE
IOCONFIG(BSP_PWM_CHN1_PIN, FUNC_TIMER2_TOGGLE2),
#endif
#ifdef BSP_PWM_CHN2_ENABLE
IOCONFIG(BSP_PWM_CHN2_PIN, FUNC_TIMER2_TOGGLE3),
#endif
#ifdef BSP_PWM_CHN3_ENABLE
IOCONFIG(BSP_PWM_CHN3_PIN, FUNC_TIMER2_TOGGLE4),
#endif
IOCONFIG(BSP_CH438_ALE_PIN, HS_GPIO(FPIOA_CH438_ALE)),
IOCONFIG(BSP_CH438_NWR_PIN, HS_GPIO(FPIOA_CH438_NWR)),
IOCONFIG(BSP_CH438_NRD_PIN, HS_GPIO(FPIOA_CH438_NRD)),
IOCONFIG(BSP_CH438_INT_PIN, HS_GPIO(FPIOA_CH438_INT)),
IOCONFIG(BSP_CH438_D0_PIN, HS_GPIO(FPIOA_CH438_D0)),
IOCONFIG(BSP_CH438_D1_PIN, HS_GPIO(FPIOA_CH438_D1)),
IOCONFIG(BSP_CH438_D2_PIN, HS_GPIO(FPIOA_CH438_D2)),
IOCONFIG(BSP_CH438_D3_PIN, HS_GPIO(FPIOA_CH438_D3)),
IOCONFIG(BSP_CH438_D4_PIN, HS_GPIO(FPIOA_CH438_D4)),
IOCONFIG(BSP_CH438_D5_PIN, HS_GPIO(FPIOA_CH438_D5)),
IOCONFIG(BSP_CH438_D6_PIN, HS_GPIO(FPIOA_CH438_D6)),
IOCONFIG(BSP_CH438_D7_PIN, HS_GPIO(FPIOA_CH438_D7)),
};
static int print_io_config()
{
int i;
rt_kprintf("IO Configuration Table\n");
rt_kprintf("┌───────┬────────────────────────┐\n");
rt_kprintf("│Pin │Function │\n");
rt_kprintf("├───────┼────────────────────────┤\n");
for(i = 0; i < sizeof io_config / sizeof io_config[0]; i++)
{
rt_kprintf("│%-2d │%-24.24s│\n", io_config[i].io_num, io_config[i].func_name);
}
rt_kprintf("└───────┴────────────────────────┘\n");
return 0;
}
MSH_CMD_EXPORT_ALIAS(print_io_config, io, print io config);
int io_config_init(void)
{
int count = sizeof(io_config) / sizeof(io_config[0]);
int i;
/* IO GroupA Power Supply Setting */
#if defined(BSP_GROUPA_POWER_SUPPLY_3V3)
sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V33);
#else
sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V18);
#endif
/* IO GroupB Power Supply Setting */
#if defined(BSP_GROUPB_POWER_SUPPLY_3V3)
sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK5, SYSCTL_POWER_V33);
#else
sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK5, SYSCTL_POWER_V18);
#endif
/* IO GroupC Power Supply Setting */
#if defined(BSP_GROUPC_POWER_SUPPLY_3V3)
sysctl_set_power_mode(SYSCTL_POWER_BANK6, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK7, SYSCTL_POWER_V33);
#else
sysctl_set_power_mode(SYSCTL_POWER_BANK6, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK7, SYSCTL_POWER_V18);
#endif
for(i = 0; i < count; i++)
{
fpioa_set_function(io_config[i].io_num, io_config[i].func);
}
#if defined(BSP_USING_DVP) || defined(BSP_USING_LCD)
sysctl_set_spi0_dvp_data(1);
sysctl_clock_enable(SYSCTL_CLOCK_AI);
#endif
}
int io_config_used(int io_num)
{
int count = sizeof(io_config) / sizeof(io_config[0]);
int i;
for(i = 0; i < count; i++)
{
if (io_config[i].io_num == io_num)
break;
}
return (i < count);
}

78
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/drv_io_config.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#ifndef __DRV_IO_CONFIG_H__
#define __DRV_IO_CONFIG_H__
#include <rtconfig.h>
enum HS_GPIO_CONFIG
{
#ifdef BSP_USING_LCD
LCD_DC_PIN = 0, /* LCD DC PIN */
#if BSP_LCD_RST_PIN >= 0
LCD_RST_PIN,
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
LCD_BACKLIGHT_PIN,
#endif
#endif
#ifdef BSP_SPI1_USING_SS0
SPI1_CS0_PIN,
#endif
#ifdef BSP_SPI1_USING_SS1
SPI1_CS1_PIN,
#endif
#ifdef BSP_SPI1_USING_SS2
SPI1_CS2_PIN,
#endif
#ifdef BSP_SPI1_USING_SS3
SPI1_CS3_PIN,
#endif
#ifdef BSP_USING_BRIDGE
SPI2_INT_PIN,
SPI2_READY_PIN,
#endif
GPIO_ALLOC_START /* index of gpio driver start */
};
#define FPIOA_CH438_ALE 11
#define FPIOA_CH438_NWR 12
#define FPIOA_CH438_NRD 13
#define FPIOA_CH438_D0 14
#define FPIOA_CH438_D1 15
#define FPIOA_CH438_D2 16
#define FPIOA_CH438_D3 17
#define FPIOA_CH438_D4 18
#define FPIOA_CH438_D5 19
#define FPIOA_CH438_D6 20
#define FPIOA_CH438_D7 21
#define FPIOA_CH438_INT 22
#define FPIOA_485_DIR 23
//PIN.define
#define BSP_CH438_ALE_PIN 23
#define BSP_CH438_NWR_PIN 24
#define BSP_CH438_NRD_PIN 25
#define BSP_CH438_D0_PIN 27
#define BSP_CH438_D1_PIN 28
#define BSP_CH438_D2_PIN 29
#define BSP_CH438_D3_PIN 30
#define BSP_CH438_D4_PIN 31
#define BSP_CH438_D5_PIN 32
#define BSP_CH438_D6_PIN 33
#define BSP_CH438_D7_PIN 34
#define BSP_CH438_INT_PIN 35
extern int io_config_init(void);
#endif

550
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/drv_lcd.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-12 ZYH first version
*/
#include <rtthread.h>
#ifdef BSP_USING_LCD
#include <drv_lcd.h>
#define DBG_TAG "LCD"
#define DBG_LVL DBG_WARNING
#include <rtdbg.h>
#define NO_OPERATION 0x00
#define SOFTWARE_RESET 0x01
#define READ_ID 0x04
#define READ_STATUS 0x09
#define READ_POWER_MODE 0x0A
#define READ_MADCTL 0x0B
#define READ_PIXEL_FORMAT 0x0C
#define READ_IMAGE_FORMAT 0x0D
#define READ_SIGNAL_MODE 0x0E
#define READ_SELT_DIAG_RESULT 0x0F
#define SLEEP_ON 0x10
#define SLEEP_OFF 0x11
#define PARTIAL_DISPALY_ON 0x12
#define NORMAL_DISPALY_ON 0x13
#define INVERSION_DISPALY_OFF 0x20
#define INVERSION_DISPALY_ON 0x21
#define GAMMA_SET 0x26
#define DISPALY_OFF 0x28
#define DISPALY_ON 0x29
#define HORIZONTAL_ADDRESS_SET 0x2A
#define VERTICAL_ADDRESS_SET 0x2B
#define MEMORY_WRITE 0x2C
#define COLOR_SET 0x2D
#define MEMORY_READ 0x2E
#define PARTIAL_AREA 0x30
#define VERTICAL_SCROL_DEFINE 0x33
#define TEAR_EFFECT_LINE_OFF 0x34
#define TEAR_EFFECT_LINE_ON 0x35
#define MEMORY_ACCESS_CTL 0x36
#define VERTICAL_SCROL_S_ADD 0x37
#define IDLE_MODE_OFF 0x38
#define IDLE_MODE_ON 0x39
#define PIXEL_FORMAT_SET 0x3A
#define WRITE_MEMORY_CONTINUE 0x3C
#define READ_MEMORY_CONTINUE 0x3E
#define SET_TEAR_SCANLINE 0x44
#define GET_SCANLINE 0x45
#define WRITE_BRIGHTNESS 0x51
#define READ_BRIGHTNESS 0x52
#define WRITE_CTRL_DISPALY 0x53
#define READ_CTRL_DISPALY 0x54
#define WRITE_BRIGHTNESS_CTL 0x55
#define READ_BRIGHTNESS_CTL 0x56
#define WRITE_MIN_BRIGHTNESS 0x5E
#define READ_MIN_BRIGHTNESS 0x5F
#define READ_ID1 0xDA
#define READ_ID2 0xDB
#define READ_ID3 0xDC
#define RGB_IF_SIGNAL_CTL 0xB0
#define NORMAL_FRAME_CTL 0xB1
#define IDLE_FRAME_CTL 0xB2
#define PARTIAL_FRAME_CTL 0xB3
#define INVERSION_CTL 0xB4
#define BLANK_PORCH_CTL 0xB5
#define DISPALY_FUNCTION_CTL 0xB6
#define ENTRY_MODE_SET 0xB7
#define BACKLIGHT_CTL1 0xB8
#define BACKLIGHT_CTL2 0xB9
#define BACKLIGHT_CTL3 0xBA
#define BACKLIGHT_CTL4 0xBB
#define BACKLIGHT_CTL5 0xBC
#define BACKLIGHT_CTL7 0xBE
#define BACKLIGHT_CTL8 0xBF
#define POWER_CTL1 0xC0
#define POWER_CTL2 0xC1
#define VCOM_CTL1 0xC5
#define VCOM_CTL2 0xC7
#define NV_MEMORY_WRITE 0xD0
#define NV_MEMORY_PROTECT_KEY 0xD1
#define NV_MEMORY_STATUS_READ 0xD2
#define READ_ID4 0xD3
#define POSITIVE_GAMMA_CORRECT 0xE0
#define NEGATIVE_GAMMA_CORRECT 0xE1
#define DIGITAL_GAMMA_CTL1 0xE2
#define DIGITAL_GAMMA_CTL2 0xE3
#define INTERFACE_CTL 0xF6
#define LCD_SPI_CHANNEL SPI_DEVICE_0
#define LCD_SPI_CHIP_SELECT SPI_CHIP_SELECT_0
#if defined(BSP_BOARD_K210_OPENMV_TEST)
#define LCD_SCAN_DIR DIR_YX_LRUD
#elif defined(BSP_BOARD_KD233)
#define LCD_SCAN_DIR (DIR_YX_RLUD | 0x08)
#elif defined(BSP_BOARD_USER)
/*user define.*/
#define LCD_SCAN_DIR DIR_YX_RLDU
#endif
static struct lcd_8080_device _lcddev;
static void drv_lcd_cmd(lcd_8080_device_t lcd, rt_uint8_t cmd)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_LOW);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
spi_init_non_standard(lcd->spi_channel, 8 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, &cmd, 1, SPI_TRANS_CHAR);
}
static void drv_lcd_data_byte(lcd_8080_device_t lcd, rt_uint8_t *data_buf, rt_uint32_t length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
spi_init_non_standard(lcd->spi_channel, 8 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_CHAR);
}
void drv_lcd_data_half_word(lcd_8080_device_t lcd, rt_uint16_t *data_buf, rt_uint32_t length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 16, 0);
spi_init_non_standard(lcd->spi_channel, 16 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_SHORT);
}
void drv_lcd_data_word(lcd_8080_device_t lcd, rt_uint32_t *data_buf, rt_uint32_t length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0);
spi_init_non_standard(lcd->spi_channel, 0 /*instrction length*/, 32 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_INT);
}
static void drv_lcd_hw_init(lcd_8080_device_t lcd)
{
#if BSP_LCD_RST_PIN >= 0
{
gpiohs_set_drive_mode(lcd->rst_pin, GPIO_DM_OUTPUT);
gpiohs_set_pin(lcd->rst_pin, GPIO_PV_LOW);
rt_thread_mdelay(20);
gpiohs_set_pin(lcd->rst_pin, GPIO_PV_HIGH);
rt_thread_mdelay(20);
}
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
{
gpiohs_set_drive_mode(lcd->backlight_pin, GPIO_DM_OUTPUT);
#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH);
#else
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#endif
}
#endif
gpiohs_set_drive_mode(lcd->dc_pin, GPIO_DM_OUTPUT);
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
spi_set_clk_rate(lcd->spi_channel, BSP_LCD_CLK_FREQ);
}
static void drv_lcd_set_direction(lcd_8080_device_t lcd, lcd_dir_t dir)
{
if (dir & DIR_XY_MASK)
{
lcd->lcd_info.width = BSP_LCD_Y_MAX;
lcd->lcd_info.height = BSP_LCD_X_MAX;
}
else
{
lcd->lcd_info.width = BSP_LCD_X_MAX;
lcd->lcd_info.height = BSP_LCD_Y_MAX;
}
rt_kprintf("lcd witdth %d,height %d \n",lcd->lcd_info.width,lcd->lcd_info.height);
drv_lcd_cmd(lcd, MEMORY_ACCESS_CTL);
drv_lcd_data_byte(lcd, (rt_uint8_t *)&dir, 1);
}
void drv_lcd_set_area(lcd_8080_device_t lcd, rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2)
{
rt_uint8_t data[4] = {0};
data[0] = (rt_uint8_t)(x1 >> 8);
data[1] = (rt_uint8_t)(x1);
data[2] = (rt_uint8_t)(x2 >> 8);
data[3] = (rt_uint8_t)(x2);
drv_lcd_cmd(lcd, HORIZONTAL_ADDRESS_SET);
drv_lcd_data_byte(lcd, data, 4);
data[0] = (rt_uint8_t)(y1 >> 8);
data[1] = (rt_uint8_t)(y1);
data[2] = (rt_uint8_t)(y2 >> 8);
data[3] = (rt_uint8_t)(y2);
drv_lcd_cmd(lcd, VERTICAL_ADDRESS_SET);
drv_lcd_data_byte(lcd, data, 4);
drv_lcd_cmd(lcd, MEMORY_WRITE);
}
static void drv_lcd_set_pixel(lcd_8080_device_t lcd, uint16_t x, uint16_t y, uint16_t color)
{
drv_lcd_set_area(lcd, x, y, x, y);
drv_lcd_data_half_word(lcd, &color, 1);
}
static void drv_lcd_clear(lcd_8080_device_t lcd, uint16_t color)
{
uint32_t data = ((uint32_t)color << 16) | (uint32_t)color;
drv_lcd_set_area(lcd, 0, 0, lcd->lcd_info.width - 1, lcd->lcd_info.height - 1);
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0);
spi_init_non_standard(lcd->spi_channel, 0 /*instrction length*/, 32 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_fill_data_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, (const uint32_t *)&data, lcd->lcd_info.width * lcd->lcd_info.height / 2);
}
static void rt_bitblt(rt_uint16_t * dest, int dest_segment, int dest_common, int dest_x, int dest_y, int width, int height,
rt_uint16_t *src, int src_segment, int src_common, int src_x, int src_y)
{
int sx0, sx1, sy0, sy1;
int dx0, dx1, dy0, dy1;
rt_uint16_t *buff_src;
rt_uint16_t *buff_dest;
int x, y;
if (width <= 0) {
return;
}
if (height <= 0) {
return;
}
sx0 = src_x;
sy0 = src_y;
sx1 = sx0 + width - 1;
sy1 = sy0 + height - 1;
dx0 = dest_x;
dy0 = dest_y;
dx1 = dx0 + width - 1;
dy1 = dy0 + height - 1;
if (sx0 < 0) {
dx0 -= sx0;
sx0 = 0;
}
if (sy0 < 0) {
dy0 -= sy0;
sy0 = 0;
}
if (sx1 >= src_segment) {
dx1 -= (sx1 - src_segment + 1);
sx1 = src_segment - 1;
}
if (sy1 >= src_common) {
dy1 -= (sy1 - src_common + 1);
sy1 = src_common - 1;
}
if (dx0 < 0) {
sx0 -= dx0;
dx0 = 0;
}
if (dy0 < 0) {
sy0 -= dy0;
dy0 = 0;
}
if (dx1 >= dest_segment) {
sx1 -= (dx1 - dest_segment + 1);
dx1 = dest_segment - 1;
}
if (dy1 >= dest_common) {
sy1 -= (dy1 - dest_common + 1);
dy1 = dest_common - 1;
}
if (sx1 < 0 || sx0 >= src_segment) {
return;
}
if (sy1 < 0 || sy0 >= src_common) {
return;
}
if (dx1 < 0 || dx0 >= dest_segment) {
return;
}
if (dy1 < 0 || dy0 >= dest_common) {
return;
}
if ((rt_ubase_t)dest < (rt_ubase_t)src) {
buff_src = src + (sy0 * src_segment) + sx0;
buff_dest = dest + (dy0 * dest_segment) + dx0;
for (y = sy0; y <= sy1; y++) {
src = buff_src;
dest = buff_dest;
for (x = sx0; x <= sx1; x++) {
*dest++ = *src++;
}
buff_src += src_segment;
buff_dest += dest_segment;
}
} else {
buff_src = src + (sy1 * src_segment) + sx1;
buff_dest = dest + (dy1 * dest_segment) + dx1;
for (y = sy1; y >= sy0; y--) {
src = buff_src;
dest = buff_dest;
for (x = sx1; x >= sx0; x--) {
*dest-- = *src--;
}
buff_src -= src_segment;
buff_dest -= dest_segment;
}
}
}
static void drv_lcd_rect_update(lcd_8080_device_t lcd, uint16_t x1, uint16_t y1, uint16_t width, uint16_t height)
{
static rt_uint16_t * rect_buffer = RT_NULL;
if(!rect_buffer)
{
rect_buffer = rt_malloc_align(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8), 64);
if(!rect_buffer)
{
return;
}
}
if(x1 == 0 && y1 == 0 && width == lcd->lcd_info.width && height == lcd->lcd_info.height)
{
drv_lcd_set_area(lcd, x1, y1, x1 + width - 1, y1 + height - 1);
drv_lcd_data_half_word(lcd, (rt_uint32_t *)lcd->lcd_info.framebuffer, width * height);
}
else
{
rt_bitblt(rect_buffer, width, height, 0, 0, width, height,(rt_uint16_t *)lcd->lcd_info.framebuffer, lcd->lcd_info.width, lcd->lcd_info.height, x1, y1);
drv_lcd_set_area(lcd, x1, y1, x1 + width - 1, y1 + height - 1);
drv_lcd_data_half_word(lcd, (rt_uint16_t *)rect_buffer, width * height);
}
}
static rt_err_t drv_lcd_init(rt_device_t dev)
{
rt_err_t ret = RT_EOK;
lcd_8080_device_t lcd = (lcd_8080_device_t)dev;
rt_uint8_t data = 0;
if(!lcd)
{
return RT_ERROR;
}
drv_lcd_hw_init(lcd);
/* reset LCD */
drv_lcd_cmd(lcd, SOFTWARE_RESET);
rt_thread_mdelay(100);
/* Enter normal status */
drv_lcd_cmd(lcd, SLEEP_OFF);
rt_thread_mdelay(100);
/* pixel format rgb565 */
drv_lcd_cmd(lcd, PIXEL_FORMAT_SET);
data = 0x55;
drv_lcd_data_byte(lcd, &data, 1);
/* set direction */
drv_lcd_set_direction(lcd, LCD_SCAN_DIR);
lcd->lcd_info.framebuffer = rt_malloc_align(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8), 64);
RT_ASSERT(lcd->lcd_info.framebuffer);
uint16_t *framebuffer = (uint16_t *)(lcd->lcd_info.framebuffer);
for(uint32_t i=0; i<(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8))/2; i++) {
framebuffer[i] = BLACK;
}
/*display on*/
drv_lcd_cmd(lcd, DISPALY_ON);
/* set to black */
drv_lcd_clear(lcd, BLACK);
return ret;
}
static rt_err_t drv_lcd_open(rt_device_t dev, rt_uint16_t oflag)
{
/* Not need */
return RT_EOK;
}
static rt_err_t drv_lcd_close(rt_device_t dev)
{
/* Not need */
return RT_EOK;
}
static rt_size_t drv_lcd_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
/* Not need */
return 0;
}
static rt_size_t drv_lcd_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
/* Not need */
return 0;
}
static rt_err_t drv_lcd_control(rt_device_t dev, int cmd, void *args)
{
rt_err_t ret = RT_EOK;
lcd_8080_device_t lcd = (lcd_8080_device_t)dev;
rt_base_t level;
struct rt_device_rect_info* rect_info = (struct rt_device_rect_info*)args;
RT_ASSERT(dev != RT_NULL);
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
if(!rect_info)
{
LOG_E("RTGRAPHIC_CTRL_RECT_UPDATE error args");
return -RT_ERROR;
}
drv_lcd_rect_update(lcd, rect_info->x, rect_info->y, rect_info->width, rect_info->height);
break;
#if BSP_LCD_BACKLIGHT_PIN >= 0
case RTGRAPHIC_CTRL_POWERON:
#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH);
#else
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#endif
break;
case RTGRAPHIC_CTRL_POWEROFF:
#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH);
#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#else
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH);
#endif
break;
#endif /* BSP_LCD_BACKLIGHT_PIN >= 0 */
case RTGRAPHIC_CTRL_GET_INFO:
*(struct rt_device_graphic_info *)args = lcd->lcd_info;
break;
case RTGRAPHIC_CTRL_SET_MODE:
ret = -RT_ENOSYS;
break;
case RTGRAPHIC_CTRL_GET_EXT:
ret = -RT_ENOSYS;
break;
default:
LOG_E("drv_lcd_control cmd: %d", cmd);
break;
}
return ret;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops drv_lcd_ops =
{
drv_lcd_init,
drv_lcd_open,
drv_lcd_close,
drv_lcd_read,
drv_lcd_write,
drv_lcd_control
};
#endif
int rt_hw_lcd_init(void)
{
rt_err_t ret = RT_EOK;
lcd_8080_device_t lcd_dev = &_lcddev;
lcd_dev->cs = SPI_CHIP_SELECT_0;
lcd_dev->dc_pin = LCD_DC_PIN;
#if BSP_LCD_RST_PIN >= 0
lcd_dev->rst_pin = LCD_RST_PIN;
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
lcd_dev->backlight_pin = LCD_BACKLIGHT_PIN;
#endif
dmalock_sync_take(&lcd_dev->dma_channel, RT_WAITING_FOREVER);
lcd_dev->spi_channel = SPI_DEVICE_0;
lcd_dev->lcd_info.bits_per_pixel = 16;
lcd_dev->lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
lcd_dev->parent.type = RT_Device_Class_Graphic;
lcd_dev->parent.rx_indicate = RT_NULL;
lcd_dev->parent.tx_complete = RT_NULL;
#ifdef RT_USING_DEVICE_OPS
lcd_dev->parent.ops = &drv_lcd_ops;
#else
lcd_dev->parent.init = drv_lcd_init;
lcd_dev->parent.open = drv_lcd_open;
lcd_dev->parent.close = drv_lcd_close;
lcd_dev->parent.read = drv_lcd_read;
lcd_dev->parent.write = drv_lcd_write;
lcd_dev->parent.control = drv_lcd_control;
#endif
lcd_dev->parent.user_data = RT_NULL;
ret = rt_device_register(&lcd_dev->parent, "lcd", RT_DEVICE_FLAG_RDWR);
return ret;
}
INIT_DEVICE_EXPORT(rt_hw_lcd_init);
void lcd_set_direction(lcd_dir_t dir)
{
drv_lcd_set_direction(&_lcddev, dir);
}
#endif

90
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/drv_lcd.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-07 ZYH first version
*/
#ifndef DRV_LCD_H__
#define DRV_LCD_H__
#include <rtdevice.h>
#include <board.h>
#include <gpiohs.h>
#include <spi.h>
#include <drv_io_config.h>
#include <rthw.h>
#include "dmalock.h"
//POINT_COLOR
#define WHITE 0xFFFF
#define BLACK 0x0000
#define BLUE 0x001F
#define BRED 0XF81F
#define GRED 0XFFE0
#define GBLUE 0X07FF
#define RED 0xF800
#define MAGENTA 0xF81F
#define GREEN 0x07E0
#define CYAN 0x7FFF
#define YELLOW 0xFFE0
#define BROWN 0XBC40
#define BRRED 0XFC07
#define GRAY 0X8430
#define GRAY175 0XAD75
#define GRAY151 0X94B2
#define GRAY187 0XBDD7
#define GRAY240 0XF79E
typedef enum _lcd_dir
{
DIR_XY_RLUD = 0x00,
DIR_YX_RLUD = 0x20,
DIR_XY_LRUD = 0x40,
DIR_YX_LRUD = 0x60,
DIR_XY_RLDU = 0x80,
DIR_YX_RLDU = 0xA0,
DIR_XY_LRDU = 0xC0,
DIR_YX_LRDU = 0xE0,
DIR_XY_MASK = 0x20,
DIR_MASK = 0xE0,
} lcd_dir_t;
typedef struct lcd_8080_device
{
struct rt_device parent;
struct rt_device_graphic_info lcd_info;
int spi_channel;
int cs;
int dc_pin;
#if BSP_LCD_RST_PIN >= 0
int rst_pin;
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
int backlight_pin;
#endif
int dma_channel;
} * lcd_8080_device_t;
int rt_hw_lcd_init(void);
void drv_lcd_set_area(lcd_8080_device_t lcd, rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2);
void drv_lcd_data_word(lcd_8080_device_t lcd, rt_uint32_t *data_buf, rt_uint32_t length);
void drv_lcd_data_half_word(lcd_8080_device_t lcd, rt_uint16_t *data_buf, rt_uint32_t length);
/* for mpy machine.lcd */
void lcd_display_on(void);
void lcd_display_off(void);
void lcd_clear(int color);
void lcd_draw_point_color(int x, int y, int color);
void lcd_show_string(int x, int y, int size, const char *data);
void lcd_draw_line(int x1, int y1, int x2, int y2);
void lcd_draw_rectangle(int x1, int y1, int x2, int y2);
void lcd_draw_circle(int x1, int y1, int r);
void lcd_set_color(int back, int fore);
void lcd_show_image(int x, int y, int length, int wide, const unsigned char *buf);
void lcd_set_direction(lcd_dir_t dir);
#endif

1297
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/drv_mpylcd.c Normal file
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27
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/drv_mpymachine.c Normal file
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#include <sysctl.h>
int mp_port_get_freq(int clkid, int *freq)
{
int ret = 0;
uint32_t value;
switch (clkid)
{
case 0:
value = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU);
break;
case 1:
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL1);
break;
case 2:
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL2);
break;
default:
ret = -1;
break;
}
*freq = (int)value;
return ret;
}

301
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/drv_spi.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-18 ZYH first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#ifdef RT_USING_SPI
#include "drv_spi.h"
#include <drv_io_config.h>
#include <spi.h>
#include "dmalock.h"
#include <sysctl.h>
#include <gpiohs.h>
#include <string.h>
#include "utils.h"
#define DRV_SPI_DEVICE(spi_bus) (struct drv_spi_bus *)(spi_bus)
#define MAX_CLOCK (40000000UL)
struct drv_spi_bus
{
struct rt_spi_bus parent;
spi_device_num_t spi_instance;
dmac_channel_number_t dma_send_channel;
dmac_channel_number_t dma_recv_channel;
struct rt_completion dma_completion;
};
struct drv_cs
{
int cs_index;
int cs_pin;
};
static volatile spi_t *const spi_instance[4] =
{
(volatile spi_t *)SPI0_BASE_ADDR,
(volatile spi_t *)SPI1_BASE_ADDR,
(volatile spi_t *)SPI_SLAVE_BASE_ADDR,
(volatile spi_t *)SPI3_BASE_ADDR
};
static rt_err_t drv_spi_configure(struct rt_spi_device *device,
struct rt_spi_configuration *configuration)
{
rt_err_t ret = RT_EOK;
int freq = 0;
struct drv_spi_bus *bus = DRV_SPI_DEVICE(device->bus);
struct drv_cs * cs = (struct drv_cs *)device->parent.user_data;
RT_ASSERT(bus != RT_NULL);
gpiohs_set_drive_mode(cs->cs_pin, GPIO_DM_OUTPUT);
gpiohs_set_pin(cs->cs_pin, GPIO_PV_HIGH);
#ifdef BSP_USING_SPI1_AS_QSPI
/* Todo:QSPI*/
#else
spi_init(bus->spi_instance, configuration->mode & RT_SPI_MODE_3, SPI_FF_STANDARD, configuration->data_width, 0);
#endif
freq = spi_set_clk_rate(bus->spi_instance, configuration->max_hz > MAX_CLOCK ? MAX_CLOCK : configuration->max_hz);
rt_kprintf("set spi freq %d\n", freq);
return ret;
}
void __spi_set_tmod(uint8_t spi_num, uint32_t tmod)
{
RT_ASSERT(spi_num < SPI_DEVICE_MAX);
volatile spi_t *spi_handle = spi[spi_num];
uint8_t tmod_offset = 0;
switch(spi_num)
{
case 0:
case 1:
case 2:
tmod_offset = 8;
break;
case 3:
default:
tmod_offset = 10;
break;
}
set_bit(&spi_handle->ctrlr0, 3 << tmod_offset, tmod << tmod_offset);
}
int dma_irq_callback(void *ctx)
{
struct rt_completion * cmp = ctx;
if(cmp)
{
rt_completion_done(cmp);
}
}
static rt_uint32_t drv_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
struct drv_spi_bus *bus = DRV_SPI_DEVICE(device->bus);
struct drv_cs * cs = (struct drv_cs *)device->parent.user_data;
struct rt_spi_configuration *cfg = &device->config;
uint32_t * tx_buff = RT_NULL;
uint32_t * rx_buff = RT_NULL;
int i;
rt_ubase_t dummy = 0xFFFFFFFFU;
if(cfg->data_width != 8)
{
return 0;
}
RT_ASSERT(bus != RT_NULL);
if(message->cs_take)
{
gpiohs_set_pin(cs->cs_pin, GPIO_PV_LOW);
}
if(message->length)
{
bus->dma_send_channel = DMAC_CHANNEL_MAX;
bus->dma_recv_channel = DMAC_CHANNEL_MAX;
rt_completion_init(&bus->dma_completion);
if(message->recv_buf)
{
dmalock_sync_take(&bus->dma_recv_channel, RT_WAITING_FOREVER);
sysctl_dma_select(bus->dma_recv_channel, SYSCTL_DMA_SELECT_SSI0_RX_REQ + bus->spi_instance * 2);
rx_buff = rt_calloc(message->length * 4, 1);
if(!rx_buff)
{
goto transfer_done;
}
}
if(message->send_buf)
{
dmalock_sync_take(&bus->dma_send_channel, RT_WAITING_FOREVER);
sysctl_dma_select(bus->dma_send_channel, SYSCTL_DMA_SELECT_SSI0_TX_REQ + bus->spi_instance * 2);
tx_buff = rt_malloc(message->length * 4);
if(!tx_buff)
{
goto transfer_done;
}
for(i = 0; i < message->length; i++)
{
tx_buff[i] = ((uint8_t *)message->send_buf)[i];
}
}
if(message->send_buf && message->recv_buf)
{
dmac_irq_register(bus->dma_recv_channel, dma_irq_callback, &bus->dma_completion, 1);
__spi_set_tmod(bus->spi_instance, SPI_TMOD_TRANS_RECV);
spi_instance[bus->spi_instance]->dmacr = 0x3;
spi_instance[bus->spi_instance]->ssienr = 0x01;
dmac_set_single_mode(bus->dma_recv_channel, (void *)(&spi_instance[bus->spi_instance]->dr[0]), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, message->length);
dmac_set_single_mode(bus->dma_send_channel, tx_buff, (void *)(&spi_instance[bus->spi_instance]->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, message->length);
}
else if(message->send_buf)
{
dmac_irq_register(bus->dma_send_channel, dma_irq_callback, &bus->dma_completion, 1);
__spi_set_tmod(bus->spi_instance, SPI_TMOD_TRANS);
spi_instance[bus->spi_instance]->dmacr = 0x2;
spi_instance[bus->spi_instance]->ssienr = 0x01;
dmac_set_single_mode(bus->dma_send_channel, tx_buff, (void *)(&spi_instance[bus->spi_instance]->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, message->length);
}
else if(message->recv_buf)
{
dmac_irq_register(bus->dma_recv_channel, dma_irq_callback, &bus->dma_completion, 1);
__spi_set_tmod(bus->spi_instance, SPI_TMOD_RECV);
spi_instance[bus->spi_instance]->ctrlr1 = message->length - 1;
spi_instance[bus->spi_instance]->dmacr = 0x1;
spi_instance[bus->spi_instance]->ssienr = 0x01;
spi_instance[bus->spi_instance]->dr[0] = 0xFF;
dmac_set_single_mode(bus->dma_recv_channel, (void *)(&spi_instance[bus->spi_instance]->dr[0]), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, message->length);
}
else
{
goto transfer_done;
}
spi_instance[bus->spi_instance]->ser = 1U << cs->cs_index;
rt_completion_wait(&bus->dma_completion, RT_WAITING_FOREVER);
if(message->recv_buf)
dmac_irq_unregister(bus->dma_recv_channel);
else
dmac_irq_unregister(bus->dma_send_channel);
// wait until all data has been transmitted
while ((spi_instance[bus->spi_instance]->sr & 0x05) != 0x04)
;
spi_instance[bus->spi_instance]->ser = 0x00;
spi_instance[bus->spi_instance]->ssienr = 0x00;
if(message->recv_buf)
{
for(i = 0; i < message->length; i++)
{
((uint8_t *)message->recv_buf)[i] = (uint8_t)rx_buff[i];
}
}
transfer_done:
dmalock_release(bus->dma_send_channel);
dmalock_release(bus->dma_recv_channel);
if(tx_buff)
{
rt_free(tx_buff);
}
if(rx_buff)
{
rt_free(rx_buff);
}
}
if(message->cs_release)
{
gpiohs_set_pin(cs->cs_pin, GPIO_PV_HIGH);
}
return message->length;
}
const static struct rt_spi_ops drv_spi_ops =
{
drv_spi_configure,
drv_spi_xfer
};
int rt_hw_spi_init(void)
{
rt_err_t ret = RT_EOK;
#ifdef BSP_USING_SPI1
{
static struct drv_spi_bus spi_bus1;
spi_bus1.spi_instance = SPI_DEVICE_1;
ret = rt_spi_bus_register(&spi_bus1.parent, "spi1", &drv_spi_ops);
#ifdef BSP_SPI1_USING_SS0
{
static struct rt_spi_device spi_device10;
static struct drv_cs cs10 =
{
.cs_index = SPI_CHIP_SELECT_0,
.cs_pin = SPI1_CS0_PIN
};
rt_spi_bus_attach_device(&spi_device10, "spi10", "spi1", (void *)&cs10);
}
#endif
#ifdef BSP_SPI1_USING_SS1
{
static struct rt_spi_device spi_device11;
static struct drv_cs cs11 =
{
.cs_index = SPI_CHIP_SELECT_1,
.cs_pin = SPI1_CS1_PIN
};
rt_spi_bus_attach_device(&spi_device11, "spi11", "spi1", (void *)&cs11);
}
#endif
#ifdef BSP_SPI1_USING_SS2
{
static struct rt_spi_device spi_device12;
static struct drv_cs cs12 =
{
.cs_index = SPI_CHIP_SELECT_2,
.cs_pin = SPI1_CS2_PIN
};
rt_spi_bus_attach_device(&spi_device12, "spi12", "spi1", (void *)&cs12);
}
#endif
#ifdef BSP_SPI1_USING_SS3
{
static struct rt_spi_device spi_device13;
static struct drv_cs cs13 =
{
.cs_index = SPI_CHIP_SELECT_2,
.cs_pin = SPI1_CS2_PIN
};
rt_spi_bus_attach_device(&spi_device13, "spi13", "spi1", (void *)&cs13);
}
#endif
}
#endif
return ret;
}
INIT_DEVICE_EXPORT(rt_hw_spi_init);
#endif

16
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/drv_spi.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-18 ZYH first version
*/
#ifndef DRV_SPI_H__
#define DRV_SPI_H__
int rt_hw_spi_init(void);
#endif

11
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/heap.c Normal file
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#include <rtthread.h>
#include <stdlib.h>
size_t get_free_heap_size(void)
{
rt_uint32_t total, used, max;
rt_memory_info(&total, &used, &max);
return total - used;
}

42
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/base-drivers/sdcard_port.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rtthread.h>
#ifdef BSP_USING_SDCARD
#if defined(RT_USING_SPI_MSD) && defined(RT_USING_DFS_ELMFAT)
#include <spi_msd.h>
#include <dfs_fs.h>
#define DBG_TAG "sdcard"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
int sd_mount(void)
{
int ret = 0;
ret = msd_init("sd0", "spi10");
if(RT_EOK == ret)
{
if(dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{
LOG_I("Mount /sd0 successfully");
return RT_EOK;
}
else
{
LOG_E("Mount fail !!1");
return -1;
}
}
LOG_E("msd_init fail !!!");
return -2;
}
INIT_ENV_EXPORT(sd_mount);
#endif
#endif

7
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/kendryte-sdk/Kconfig Normal file
View File

@@ -0,0 +1,7 @@
menu "Kendryte SDK Config"
config PKG_KENDRYTE_SDK_VERNUM
hex "Kendryte SDK Version"
default 0x0055
endmenu

38
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/kendryte-sdk/SConscript Normal file
View File

@@ -0,0 +1,38 @@
from building import *
cwd = GetCurrentDir()
src = Split('''
kendryte-sdk-source/lib/bsp/entry.c
kendryte-sdk-source/lib/bsp/entry_user.c
kendryte-sdk-source/lib/drivers/aes.c
kendryte-sdk-source/lib/drivers/clint.c
kendryte-sdk-source/lib/drivers/dmac.c
kendryte-sdk-source/lib/drivers/dvp.c
kendryte-sdk-source/lib/drivers/fft.c
kendryte-sdk-source/lib/drivers/fpioa.c
kendryte-sdk-source/lib/drivers/gpio.c
kendryte-sdk-source/lib/drivers/gpiohs.c
kendryte-sdk-source/lib/drivers/i2c.c
kendryte-sdk-source/lib/drivers/i2s.c
kendryte-sdk-source/lib/drivers/kpu.c
kendryte-sdk-source/lib/drivers/plic.c
kendryte-sdk-source/lib/drivers/pwm.c
kendryte-sdk-source/lib/drivers/rtc.c
kendryte-sdk-source/lib/drivers/sha256.c
kendryte-sdk-source/lib/drivers/spi.c
kendryte-sdk-source/lib/drivers/sysctl.c
kendryte-sdk-source/lib/drivers/timer.c
kendryte-sdk-source/lib/drivers/uart.c
kendryte-sdk-source/lib/drivers/uarths.c
kendryte-sdk-source/lib/drivers/utils.c
kendryte-sdk-source/lib/drivers/wdt.c
''')
CPPPATH = [cwd + '/kendryte-sdk-source/lib/drivers/include',
cwd + '/kendryte-sdk-source/lib/nncase/include',
cwd + '/kendryte-sdk-source/lib/bsp/include',
cwd + '/kendryte-sdk-source/lib/utils/include']
CPPDEFINES = ['CONFIG_LOG_COLORS', 'CONFIG_LOG_ENABLE', 'CONFIG_LOG_LEVEL=LOG_VERBOSE', 'FPGA_PLL', 'LOG_KERNEL', '__riscv64']
group = DefineGroup('SDK', src, depend = [''], CPPPATH = CPPPATH, LOCAL_CPPDEFINES = CPPDEFINES)
Return('group')

1
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/kendryte-sdk/kendryte-sdk-source Submodule

Submodule Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/kendryte-sdk/kendryte-sdk-source added at 77d9df93ba

170
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/link.lds Normal file
View File

@@ -0,0 +1,170 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
INCLUDE "link_stacksize.lds"
/*
* The OUTPUT_ARCH command specifies the machine architecture where the
* argument is one of the names used in the Kendryte library.
*/
OUTPUT_ARCH( "riscv" )
MEMORY
{
/* 6M SRAM */
SRAM : ORIGIN = 0x80000000, LENGTH = 0x600000
}
ENTRY(_start)
SECTIONS
{
. = 0x80000000 ;
/* __STACKSIZE__ = 4096; */
.start :
{
*(.start);
} > SRAM
. = ALIGN(8);
.text :
{
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(8);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(8);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(8);
/* section information for initial. */
. = ALIGN(8);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(8);
PROVIDE(__ctors_start__ = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
. = ALIGN(8);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
. = ALIGN(8);
_etext = .;
} > SRAM
.eh_frame_hdr :
{
*(.eh_frame_hdr)
*(.eh_frame_entry)
} > SRAM
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
. = ALIGN(8);
.data :
{
*(.data)
*(.data.*)
*(.data1)
*(.data1.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata)
*(.sdata.*)
} > SRAM
/* stack for dual core */
.stack :
{
. = ALIGN(64);
__stack_start__ = .;
. += __STACKSIZE__;
__stack_cpu0 = .;
. += __STACKSIZE__;
__stack_cpu1 = .;
} > SRAM
.sbss :
{
__bss_start = .;
*(.sbss)
*(.sbss.*)
*(.dynsbss)
*(.scommon)
} > SRAM
.bss :
{
*(.bss)
*(.bss.*)
*(.dynbss)
*(COMMON)
__bss_end = .;
} > SRAM
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

1
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/link_stacksize.lds Normal file
View File

@@ -0,0 +1 @@
__STACKSIZE__ = 4096;

262
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/rtconfig.h Normal file
View File

@@ -0,0 +1,262 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* XIUOS Rt-thread Configuration */
#define ROOT_DIR "../../../.."
#define BSP_DIR "."
#define RT_Thread_DIR "../.."
#define RTT_DIR "../../rt-thread"
#define BOARD_K210_EVB
/* RT-Thread Kernel */
#define RT_NAME_MAX 24
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_DEBUG
#define RT_DEBUG_COLOR
#define RT_DEBUG_INIT_CONFIG
#define RT_DEBUG_INIT 1
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_SIGNALS
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_MEMHEAP
#define RT_USING_SLAB
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uarths"
#define RT_VER_NUM 0x40004
#define ARCH_CPU_64BIT
#define ARCH_RISCV
#define ARCH_RISCV_FPU
#define ARCH_RISCV_FPU_S
#define ARCH_RISCV64
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
#define RT_USING_CPLUSPLUS
/* Command shell */
#define RT_USING_FINSH
#define RT_USING_MSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 16384
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 16
#define DFS_FILESYSTEM_TYPES_MAX 16
#define DFS_FD_MAX 64
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_RTC
#define RT_USING_SPI
#define RT_USING_SPI_MSD
#define RT_USING_SFUD
#define RT_SFUD_USING_SFDP
#define RT_SFUD_USING_FLASH_INFO_TABLE
#define RT_SFUD_SPI_MAX_HZ 50000000
#define RT_DEBUG_SFUD
/* Using USB */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_USING_PTHREADS
#define PTHREAD_NUM_MAX 8
#define RT_USING_POSIX
#define RT_LIBC_USING_TIME
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* Network */
/* Socket abstraction layer */
/* Network interface device */
/* light weight TCP/IP stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread Utestcases */
/* Board Drivers Config */
#define BSP_USING_UART_HS
/* General Purpose UARTs */
#define BSP_USING_UART1
#define BSP_UART1_TXD_PIN 20
#define BSP_UART1_RXD_PIN 21
#define BSP_UART1_RTS_PIN -1
#define BSP_UART1_CTS_PIN -1
#define BSP_USING_CH438
#define BSP_CH438_ALE_PIN 23
#define BSP_CH438_NWR_PIN 24
#define BSP_CH438_NRD_PIN 25
#define BSP_CH438_D0_PIN 27
#define BSP_CH438_D1_PIN 28
#define BSP_CH438_D2_PIN 29
#define BSP_CH438_D3_PIN 30
#define BSP_CH438_D4_PIN 31
#define BSP_CH438_D5_PIN 32
#define BSP_CH438_D6_PIN 33
#define BSP_CH438_D7_PIN 34
#define BSP_CH438_INT_PIN 35
/* Kendryte SDK Config */
#define PKG_KENDRYTE_SDK_VERNUM 0x0055
/* More Drivers */
/* APP_Framework */
/* Framework */
#define TRANSFORM_LAYER_ATTRIUBUTE
#define ADD_RTTHREAD_FETURES
#define SUPPORT_SENSOR_FRAMEWORK
#define SENSOR_HCHO
#define SENSOR_TB600B_WQ_HCHO1OS
#define SENSOR_DEVICE_TB600B_WQ_HCHO1OS "tb600b_wq_hcho1os_1"
#define SENSOR_QUANTITY_TB600B_HCHO "hcho_1"
#define SENSOR_TB600B_WQ_HCHO1OS_DRIVER_EXTUART
#define SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV "/dev/extuart_dev1"
#define SENSOR_DEVICE_TB600B_WQ_HCHO1OS_DEV_EXT_PORT 1
#define SENSOR_CH4
#define SENSOR_AS830
#define SENSOR_DEVICE_AS830 "as830_1"
#define SENSOR_QUANTITY_AS830_CH4 "ch4_1"
#define SENSOR_AS830_DRIVER_EXTUART
#define SENSOR_DEVICE_AS830_DEV "/dev/extuart_dev4"
#define SENSOR_DEVICE_AS830_DEV_EXT_PORT 4
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 1024
/* ota app */
/* test app */
/* connection app */
/* control app */
/* knowing app */
/* sensor app */
#define APPLICATION_SENSOR
#define APPLICATION_SENSOR_HCHO
#define APPLICATION_SENSOR_HCHO_TB600B_WQ_HCHO1OS
#define APPLICATION_SENSOR_CH4
#define APPLICATION_SENSOR_CH4_AS830
/* lib */
#define APP_SELECT_NEWLIB
#define __STACKSIZE__ 4096
#endif

49
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/aiit-riscv64-board/rtconfig.py Normal file
View File

@@ -0,0 +1,49 @@
import os
# toolchains options
ARCH ='risc-v'
CPU ='k210'
CROSS_TOOL ='gcc'
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin'
else:
print('Please make sure your toolchains is GNU GCC!')
exit(0)
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
PREFIX = 'riscv-none-embed-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcmodel=medany -march=rv64imafc -mabi=lp64f -fsingle-precision-constant'
CFLAGS = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -ggdb'
AFLAGS += ' -ggdb'
else:
CFLAGS += ' -O2 -Os'
CXXFLAGS = CFLAGS
# we use c++ 11, but -std=c++11 don't have 'struct siginfo', need gnu++11
CXXFLAGS += ' -std=gnu++11'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

554
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/.config Normal file
View File

@@ -0,0 +1,554 @@
#
# Automatically generated file; DO NOT EDIT.
# XIUOS Rt-thread Configuration
#
CONFIG_ROOT_DIR="../../../.."
CONFIG_BSP_DIR="."
CONFIG_RT_Thread_DIR="../.."
CONFIG_RTT_DIR="../../rt-thread"
CONFIG_BOARD_K210_EVB=y
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_BIG_ENDIAN is not set
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=2
CONFIG_RT_ALIGN_SIZE=8
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=4096
CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
# CONFIG_RT_USING_TIMER_SOFT is not set
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_ASM_MEMCPY is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
CONFIG_RT_DEBUG_INIT_CONFIG=y
CONFIG_RT_DEBUG_INIT=1
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
CONFIG_RT_USING_SIGNALS=y
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_MEMHEAP=y
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_SMALL_MEM is not set
CONFIG_RT_USING_SLAB=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uarths"
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_VER_NUM=0x40004
CONFIG_ARCH_CPU_64BIT=y
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_RISCV_FPU=y
CONFIG_ARCH_RISCV_FPU_S=y
CONFIG_ARCH_RISCV64=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
CONFIG_RT_USING_CPLUSPLUS=y
# CONFIG_RT_USING_CPLUSPLUS11 is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_RT_USING_MSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=16384
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=16
CONFIG_DFS_FILESYSTEM_TYPES_MAX=16
CONFIG_DFS_FD_MAX=64
# CONFIG_RT_USING_DFS_MNTTABLE is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_NFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_QSPI is not set
CONFIG_RT_USING_SPI_MSD=y
CONFIG_RT_USING_SFUD=y
CONFIG_RT_SFUD_USING_SFDP=y
CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
# CONFIG_RT_SFUD_USING_QSPI is not set
CONFIG_RT_SFUD_SPI_MAX_HZ=50000000
CONFIG_RT_DEBUG_SFUD=y
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
CONFIG_RT_USING_WIFI=y
CONFIG_RT_WLAN_DEVICE_STA_NAME="wlan0"
CONFIG_RT_WLAN_DEVICE_AP_NAME="wlan1"
CONFIG_RT_WLAN_SSID_MAX_LENGTH=32
CONFIG_RT_WLAN_PASSWORD_MAX_LENGTH=32
CONFIG_RT_WLAN_DEV_EVENT_NUM=2
CONFIG_RT_WLAN_MANAGE_ENABLE=y
CONFIG_RT_WLAN_SCAN_WAIT_MS=10000
CONFIG_RT_WLAN_CONNECT_WAIT_MS=10000
CONFIG_RT_WLAN_SCAN_SORT=y
CONFIG_RT_WLAN_MSH_CMD_ENABLE=y
CONFIG_RT_WLAN_AUTO_CONNECT_ENABLE=y
CONFIG_AUTO_CONNECTION_PERIOD_MS=2000
CONFIG_RT_WLAN_CFG_ENABLE=y
CONFIG_RT_WLAN_CFG_INFO_MAX=3
CONFIG_RT_WLAN_PROT_ENABLE=y
CONFIG_RT_WLAN_PROT_NAME_LEN=8
CONFIG_RT_WLAN_PROT_MAX=2
CONFIG_RT_WLAN_DEFAULT_PROT="lwip"
CONFIG_RT_WLAN_PROT_LWIP_ENABLE=y
CONFIG_RT_WLAN_PROT_LWIP_NAME="lwip"
# CONFIG_RT_WLAN_PROT_LWIP_PBUF_FORCE is not set
CONFIG_RT_WLAN_WORK_THREAD_ENABLE=y
CONFIG_RT_WLAN_WORKQUEUE_THREAD_NAME="wlan"
CONFIG_RT_WLAN_WORKQUEUE_THREAD_SIZE=2048
CONFIG_RT_WLAN_WORKQUEUE_THREAD_PRIO=15
# CONFIG_RT_WLAN_DEBUG is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
CONFIG_RT_USING_PTHREADS=y
CONFIG_PTHREAD_NUM_MAX=8
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_GETLINE is not set
# CONFIG_RT_USING_POSIX_AIO is not set
CONFIG_RT_LIBC_USING_TIME=y
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# Network
#
#
# Socket abstraction layer
#
CONFIG_RT_USING_SAL=y
# CONFIG_SAL_INTERNET_CHECK is not set
#
# protocol stack implement
#
CONFIG_SAL_USING_LWIP=y
CONFIG_SAL_USING_POSIX=y
#
# Network interface device
#
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
#
# light weight TCP/IP stack
#
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
CONFIG_RT_USING_LWIP202=y
# CONFIG_RT_USING_LWIP203 is not set
# CONFIG_RT_USING_LWIP212 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=8
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
CONFIG_RT_LWIP_DHCP=y
CONFIG_IP_SOF_BROADCAST=1
CONFIG_IP_SOF_BROADCAST_RECV=1
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.1.30"
CONFIG_RT_LWIP_GWADDR="192.168.1.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=16
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=10240
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=10240
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
CONFIG_LWIP_SO_LINGER=0
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_RT_LWIP_DEBUG is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
# CONFIG_LWIP_USING_DHCPD is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# Board Drivers Config
#
CONFIG_BSP_USING_UART_HS=y
#
# General Purpose UARTs
#
CONFIG_BSP_USING_UART1=y
CONFIG_BSP_UART1_TXD_PIN=20
CONFIG_BSP_UART1_RXD_PIN=21
CONFIG_BSP_UART1_RTS_PIN=-1
CONFIG_BSP_UART1_CTS_PIN=-1
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_I2C1 is not set
CONFIG_BSP_USING_SPI1=y
# CONFIG_BSP_USING_SPI1_AS_QSPI is not set
CONFIG_BSP_SPI1_CLK_PIN=27
CONFIG_BSP_SPI1_D0_PIN=28
CONFIG_BSP_SPI1_D1_PIN=26
CONFIG_BSP_SPI1_USING_SS0=y
CONFIG_BSP_SPI1_SS0_PIN=29
CONFIG_BSP_SPI1_USING_SS1=y
CONFIG_BSP_SPI1_SS1_PIN=8
# CONFIG_BSP_SPI1_USING_SS2 is not set
# CONFIG_BSP_SPI1_USING_SS3 is not set
CONFIG_BSP_USING_LCD=y
CONFIG_BSP_LCD_CS_PIN=36
CONFIG_BSP_LCD_WR_PIN=39
CONFIG_BSP_LCD_DC_PIN=38
CONFIG_BSP_LCD_RST_PIN=37
CONFIG_BSP_LCD_BACKLIGHT_PIN=-1
CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_LOW=y
# CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_HIGH is not set
CONFIG_BSP_LCD_CLK_FREQ=20000000
# CONFIG_BSP_BOARD_KD233 is not set
# CONFIG_BSP_BOARD_K210_OPENMV_TEST is not set
CONFIG_BSP_BOARD_USER=y
CONFIG_BSP_LCD_X_MAX=240
CONFIG_BSP_LCD_Y_MAX=320
CONFIG_BSP_USING_SDCARD=y
CONFIG_BSP_USING_DVP=y
#
# The default pin assignment is based on the Maix Duino K210 development board
#
CONFIG_BSP_DVP_SCCB_SDA_PIN=40
CONFIG_BSP_DVP_SCCB_SCLK_PIN=41
CONFIG_BSP_DVP_CMOS_RST_PIN=42
CONFIG_BSP_DVP_CMOS_VSYNC_PIN=43
CONFIG_BSP_DVP_CMOS_PWDN_PIN=44
CONFIG_BSP_DVP_CMOS_XCLK_PIN=46
CONFIG_BSP_DVP_CMOS_PCLK_PIN=47
CONFIG_BSP_DVP_CMOS_HREF_PIN=45
#
# Kendryte SDK Config
#
CONFIG_PKG_KENDRYTE_SDK_VERNUM=0x0055
#
# MicroPython
#
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# More Drivers
#
# CONFIG_PKG_USING_RW007 is not set
CONFIG_DRV_USING_OV2640=y
CONFIG_OV2640_JPEG_MODE=y
# CONFIG_OV2640_RGB565_MODE is not set
CONFIG_OV2640_X_RESOLUTION_IMAGE_OUTSIZE=240
CONFIG_OV2640_Y_RESOLUTION_IMAGE_OUTSIZE=240
CONFIG_OV2640_X_IMAGE_WINDOWS_SIZE=400
#
# the value must be greater than OV2640_X_RESOLUTION_IMAGE_OUTSIZE
#
CONFIG_OV2640_Y_IMAGE_WINDOWS_SIZE=400
#
# the value must be greater than OV2640_Y_RESOLUTION_IMAGE_OUTSIZE
#
#
# APP_Framework
#
#
# Framework
#
CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y
CONFIG_ADD_XIZI_FETURES=y
# CONFIG_ADD_NUTTX_FETURES is not set
# CONFIG_ADD_RTTHREAD_FETURES is not set
# CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set
# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set
CONFIG_SUPPORT_KNOWING_FRAMEWORK=y
# CONFIG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_USING_KNOWING_FILTER is not set
# CONFIG_USING_OTA_MODEL is not set
# CONFIG_USING_IMAGE_PROCESSING is not set
# CONFIG_USING_CMSIS_5 is not set
CONFIG_USING_KPU_PROCESSING=y
CONFIG_USING_YOLOV2=y
CONFIG_USING_YOLOV2_JSONPARSER=y
CONFIG_USING_K210_YOLOV2_DETECT=y
# CONFIG_USING_NNOM is not set
# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set
#
# Security
#
# CONFIG_CRYPTO is not set
#
# Applications
#
#
# config stack size and priority of main task
#
CONFIG_MAIN_KTASK_STACK_SIZE=1024
#
# ota app
#
# CONFIG_APPLICATION_OTA is not set
#
# test app
#
# CONFIG_USER_TEST is not set
#
# connection app
#
# CONFIG_APPLICATION_CONNECTION is not set
#
# control app
#
#
# knowing app
#
CONFIG_APPLICATION_KNOWING=y
CONFIG_K210_DETECT_ENTRY=y
# CONFIG_IRIS_ML_DEMO is not set
# CONFIG_K210_FFT_TEST is not set
# CONFIG_USING_IMAGE_PROCESSING_APP is not set
#
# sensor app
#
CONFIG_APPLICATION_SENSOR=y
# CONFIG_APPLICATION_SENSOR_HCHO is not set
# CONFIG_APPLICATION_SENSOR_TVOC is not set
# CONFIG_APPLICATION_SENSOR_IAQ is not set
# CONFIG_APPLICATION_SENSOR_CH4 is not set
# CONFIG_APPLICATION_SENSOR_CO2 is not set
# CONFIG_APPLICATION_SENSOR_PM1_0 is not set
# CONFIG_APPLICATION_SENSOR_PM2_5 is not set
# CONFIG_APPLICATION_SENSOR_PM10 is not set
# CONFIG_APPLICATION_SENSOR_VOICE is not set
# CONFIG_APPLICATION_SENSOR_TEMPERATURE is not set
# CONFIG_APPLICATION_SENSOR_HUMIDITY is not set
# CONFIG_USING_EMBEDDED_DATABASE_APP is not set
#
# lib
#
CONFIG_APP_SELECT_NEWLIB=y
# CONFIG_APP_SELECT_OTHER_LIB is not set
CONFIG_LIB_USING_CJSON=y
# CONFIG_LIB_USING_QUEUE is not set
# CONFIG_LIB_LV is not set
# CONFIG_USING_EMBEDDED_DATABASE is not set
CONFIG___STACKSIZE__=4096

228
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/.gitignore vendored Normal file
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# this
*.old
*.dblite
cconfig.h
*.bin
*.map
# rtconfig.h
# .config
# General
.DS_Store
.AppleDouble
.LSOverride
# Icon must end with two \r
Icon
# Thumbnails
._*
# Files that might appear in the root of a volume
.DocumentRevisions-V100
.fseventsd
.Spotlight-V100
.TemporaryItems
.Trashes
.VolumeIcon.icns
.com.apple.timemachine.donotpresent
# Directories potentially created on remote AFP share
.AppleDB
.AppleDesktop
Network Trash Folder
Temporary Items
.apdisk
# Byte-compiled / optimized / DLL files
__pycache__/
*.py[cod]
*$py.class
# C extensions
*.so
# Distribution / packaging
.Python
build/
develop-eggs/
dist/
downloads/
eggs/
.eggs/
lib/
lib64/
parts/
sdist/
var/
wheels/
share/python-wheels/
*.egg-info/
.installed.cfg
*.egg
MANIFEST
# PyInstaller
# Usually these files are written by a python script from a template
# before PyInstaller builds the exe, so as to inject date/other infos into it.
*.manifest
*.spec
# Installer logs
pip-log.txt
pip-delete-this-directory.txt
# Unit test / coverage reports
htmlcov/
.tox/
.nox/
.coverage
.coverage.*
.cache
nosetests.xml
coverage.xml
*.cover
*.py,cover
.hypothesis/
.pytest_cache/
cover/
# Translations
*.mo
*.pot
# Django stuff:
*.log
local_settings.py
db.sqlite3
db.sqlite3-journal
# Flask stuff:
instance/
.webassets-cache
# Scrapy stuff:
.scrapy
# Sphinx documentation
docs/_build/
# PyBuilder
.pybuilder/
target/
# Jupyter Notebook
.ipynb_checkpoints
# IPython
profile_default/
ipython_config.py
# pyenv
# For a library or package, you might want to ignore these files since the code is
# intended to run in multiple environments; otherwise, check them in:
# .python-version
# pipenv
# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control.
# However, in case of collaboration, if having platform-specific dependencies or dependencies
# having no cross-platform support, pipenv may install dependencies that don't work, or not
# install all needed dependencies.
#Pipfile.lock
# PEP 582; used by e.g. github.com/David-OConnor/pyflow
__pypackages__/
# Celery stuff
celerybeat-schedule
celerybeat.pid
# SageMath parsed files
*.sage.py
# Environments
.env
.venv
env/
venv/
ENV/
env.bak/
venv.bak/
# Spyder project settings
.spyderproject
.spyproject
# Rope project settings
.ropeproject
# mkdocs documentation
/site
# mypy
.mypy_cache/
.dmypy.json
dmypy.json
# Pyre type checker
.pyre/
# pytype static type analyzer
.pytype/
# Cython debug symbols
cython_debug/
# Prerequisites
*.d
# Object files
*.o
*.ko
*.obj
*.elf
# Linker output
*.ilk
*.map
*.exp
# Precompiled Headers
*.gch
*.pch
# Libraries
*.lib
*.a
*.la
*.lo
# Shared objects (inc. Windows DLLs)
*.dll
*.so
*.so.*
*.dylib
# Executables
*.exe
*.out
*.app
*.i*86
*.x86_64
*.hex
# Debug files
*.dSYM/
*.su
*.idb
*.pdb
# Kernel Module Compile Results
*.mod*
*.cmd
.tmp_versions/
modules.order
Module.symvers
Mkfile.old
dkms.con

40
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/Kconfig Normal file
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mainmenu "XIUOS Rt-thread Configuration"
config ROOT_DIR
string
default "../../../.."
config BSP_DIR
string
default "."
config RT_Thread_DIR
string
default "../.."
config RTT_DIR
string
default "../../rt-thread"
config BOARD_K210_EVB
bool
select ARCH_RISCV64
select ARCH_RISCV_FPU_S
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
config APP_DIR
string
default "../../../../APP_Framework"
source "$RTT_DIR/Kconfig"
source "base-drivers/Kconfig"
source "kendryte-sdk/Kconfig"
source "$RT_Thread_DIR/micropython/Kconfig"
source "$RT_Thread_DIR/app_match_rt-thread/Kconfig"
source "$ROOT_DIR/APP_Framework/Kconfig"
config __STACKSIZE__
int "stack size for interrupt"
default 4096

117
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/README.md Normal file
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# K210最小系统板（Max bit）说明
## OV2640 menuconfig 配置：
​ More Driver-------->ov2640 driver （勾选） 保存即可
## RW007 menuconfig 配置：
​ More Driver-------->rw007:SPI WIFI rw007 driver
​ example driver port (not use example driver, porting by myself)
​ (20000000) SPI MAX Hz
​ Board Drivers Config
​ Enable SPI1
​ (27) spi1 clk pin number
​ (28) spi1 d0 pin number
​ (26) spi1 d1 pin number
​ SPI1 Enable SS1（spi11 dev）-------->(8) spi1 ss1 pin number
​ (spi11) the SPIDEV rw007 driver on
​ (7) rw007 int pin for rw007
​ (6) rw007 rst pin for rw007
**SPI1 Enable SS1（spi11 dev）表示SPI1总线片选编号1 ，此时挂载在总线上设备名是spi11，所以 the SPIDEV rw007 driver on参数也要填写（spi11）**
## SD卡配置：
​ Board Drivers Config-------->Enable SDCARD (spi1(ss0)) （勾选）保存即可 SPI1 Enable SS0（spi10 dev）-------->(29) spi1 ss1 pin number 会默认配置
**SD卡和RW007共用一条spi硬件总线 ，其中片选设备sd卡为SPI1 Enable SS0（spi10 dev），RW007片选设备为SPI1 Enable SS1（spi11 dev）**
​
**上述引脚根据电路实际而定,另外涉及到相关的Lwip wifi framwork等已经默认配置并匹配**
## 以下为引脚硬件的连接表
## RW007(SPI1 ) Kendryte Sipeed MAX bit io
| 引脚 | 作用 | 引脚序号 | RW007板子 |
| ------------------ | --------- | -------- | --------- |
| io 27(印丝标注SCK) | SPI1_SCK | | SCK |
| io 26(印丝标注SO) | SPI1_MISO | | MISO |
| io 28(印丝标注SI) | SPI1_MOSI | | MOSI |
| io 8 | CS/BOOT1 | | CS |
| io 7 | INT/BUSY | | D9 |
| io 6 | RESET | | D8 |
## SD卡Kendryte Sipeed MAX bit io
| 引脚 | 作用 | 引脚序号 | RW007板子 |
| ------------------ | --------- | -------- | --------- |
| io 27(印丝标注SCK) | SPI1_SCK | | SCK |
| io 26(印丝标注SO) | SPI1_MISO | | MISO |
| io 28(印丝标注SI) | SPI1_MOSI | | MOSI |
| io 29 | CS/BOOT1 | | CS |
**注意：BSP_SPI1_D0_PIN 10 d0也就是MOSI ，sd卡可直接利用Max bit板载，无需重新接线。SD卡和Rw007设备共用一条SPI1总线**
## 编译说明
编译K210，需要有RT-Thread的代码，因为K210的sdk是以软件包方式，所以需要在bsp/k210下做软件包更新。Windows下推进使用[env工具][1]，然后在console下进入bsp/k210目录中，运行：
cd bsp/k210
pkgs --update
如果在Linux平台下，可以先执行
scons --menuconfig
它会自动下载env相关脚本到~/.env目录，然后执行
source ~/.env/env.sh
cd bsp/k210
pkgs --update
下载risc-v的工具链，[下载地址](https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases)
更新完软件包后，在`rtconfig.py`中将risc-v工具链的本地路径加入文档。
注：
1. 工具链建议使用上方提供的，`kendryte的官方工具链`会报浮点类型不兼容的错误，`risc-v工具链8.2.0之前的版本`会出现头文件不兼容的问题。
2. 网上传需要开启C++ 17,认为k210的神经网络编译器nncase多数语法由C++ 17,故需要开启C++ 17。个人认为没有必要，nncase是在PC端独立使用的，
作用是将神经网络模型转为kmodel格式，此格式文件为已经编译的二进制文件.
然后执行scons编译：
set RTT_EXEC_PATH=your_toolchains
scons
来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中rtthread.bin需要烧写到设备中进行运行。
注：如果初次使用编译报错，可能是使用的SDK过老，使用`menuconfig`命令，在→ RT-Thread online packages → peripheral libraries
and drivers → the kendryte-sdk package for rt-thread中将SDK改为latest版本即可。

13
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/SConscript Normal file
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import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

69
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/SConstruct Normal file
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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../rt-thread')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
# use ASPPCOM to replace ASCOM, ASPPCOM will use CFLAGS/CPPFLAGS with AS
env['ASCOM'] = env['ASPPCOM']
AddOption('--compiledb',
dest = 'compiledb',
action = 'store_true',
default = False,
help = 'generate compile_commands.json')
if GetOption('compiledb'):
if int(SCons.__version__.split('.')[0]) >= 4:
env['COMPILATIONDB_USE_ABSPATH'] = True
env.Tool('compilation_db')
env.CompilationDatabase('compile_commands.json')
else:
print('Warning: --compiledb only support on SCons 4.0+')
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
stack_size = 4096
stack_lds = open('link_stacksize.lds', 'w')
if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__')
stack_lds.write('__STACKSIZE__ = %d;' % stack_size)
stack_lds.close()
# include more drivers
objs.extend(SConscript(os.getcwd() + '/../../app_match_rt-thread/SConscript'))
# include APP_Framework/Framework
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Framework/SConscript'))
# include APP_Framework/Applications
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Applications/SConscript'))
# include APP_Framework/lib
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/lib/SConscript'))
# include Ubiquitous/RT-Thread/micropython
objs.extend(SConscript(os.getcwd() + '/../../micropython/SConscript'))
# make a building
DoBuilding(TARGET, objs)

9
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from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

100
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/applications/lcd_test.c Normal file
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#include <rtthread.h>
#include <rtdevice.h>
#include <stdint.h>
#include <stdlib.h>
#include "drv_lcd.h"
static void drawarea(rt_device_t dev, struct rt_device_graphic_info *info,
int x, int y, int w, int h, uint16_t c)
{
struct rt_device_rect_info rect;
uint16_t *fb;
int i, j;
fb = (uint16_t *)info->framebuffer;
fb += (info->width * y);
fb += x;
for (j = 0; j < h; j++)
{
for (i = 0; i < w; i++)
{
fb[i] = c;
}
fb += info->width;
}
rect.x = x;
rect.y = y;
rect.width = w;
rect.height = h;
rt_device_control(dev, RTGRAPHIC_CTRL_RECT_UPDATE, &rect);
}
#define RGB_BUF_SIZE (320*240*2)
static int showcolor(int argc, char **argv)
{
unsigned char r = 0, g = 0, b = 0;
char *devname = "lcd";
rt_device_t dev;
struct rt_device_graphic_info info;
int result;
int x = 0, y = 0;
int i;
uint16_t c;
for (i = 1; i < argc; i++)
{
switch (i)
{
case 1:
r = atoi(argv[i]);
break;
case 2:
g = atoi(argv[i]);
break;
case 3:
b = atoi(argv[i]);
break;
}
}
dev = rt_device_find(devname);
if (!dev)
{
rt_kprintf("lcd: %s not found\n", devname);
return -1;
}
if (rt_device_open(dev, 0) != 0)
{
rt_kprintf("lcd open fail\n");
return -1;
}
result = rt_device_control(dev, RTGRAPHIC_CTRL_GET_INFO, &info);
if (result != RT_EOK)
{
rt_kprintf("get device information failed\n");
return result;
}
c = (uint16_t)(((r >> 3) << 11) | ((g >> 2) << 6) | ((b >> 3)));
drawarea(dev, &info, x, y, 24, 24, c);
lcd_set_color(BLACK, BLUE);
lcd_show_string(0, 40, 16, "hello world");
lcd_show_string(0, 60, 24, "hello world");
lcd_show_string(0, 90, 32, "hello world");
lcd_draw_line(0, 200, 319, 200);
lcd_draw_circle(270, 120, 30);
lcd_set_color(BLACK, RED);
lcd_show_string(0, 130, 32, "after set color");
lcd_draw_line(0, 0, 319, 239);
lcd_draw_rectangle(50, 10, 170, 145);
lcd_draw_circle(160, 120, 50);
rt_device_close(dev);
return 0;
}
MSH_CMD_EXPORT(showcolor, showcolor R G B-- R / G / B : 0 ~255);

48
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/applications/main.c Normal file
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/*
* @Author: your name
* @Date: 2021-10-11 22:04:25
* @LastEditTime: 2021-10-14 11:12:52
* @LastEditors: Please set LastEditors
* @Description: In User Settings Edit
* @FilePath: \xiuos\Ubiquitous\RT_Thread\bsp\k210\applications\main.c
*/
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <stdio.h>
#define LED_G 12
int main(void)
{
rt_pin_mode(LED_G, PIN_MODE_OUTPUT);
rt_thread_mdelay(100);
char info1[25] ={0};
char info2[25] ={0};
sprintf(info1,"xuos-intelligence k210 ");
sprintf(info2,"build %s %s",__DATE__,__TIME__);
printf("%s %s \n",info1,info2);
#ifdef BSP_USING_LCD
#include<drv_lcd.h>
lcd_show_string(0,60,24,info1);
lcd_show_string(0,90,24,info2);
#endif
while(1)
{
rt_pin_write(LED_G, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED_G, PIN_LOW);
rt_thread_mdelay(500);
}
return 0;
}

106
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#include <rtthread.h>
#include <rtdevice.h>
#include "stdio.h"
#include "string.h"
#include "dvp.h"
#include "fpioa.h"
#include "plic.h"
#include "sysctl.h"
#if(defined DRV_USING_OV2640 && defined BSP_USING_LCD)
#include<drv_ov2640.h>
#define RGB_BUF_SIZE (320*240*2)
#ifdef RT_USING_POSIX
#include <pthread.h>
#include <unistd.h>
#include <stdio.h>
#include <dfs_poll.h>
#ifdef RT_USING_POSIX_TERMIOS
#include <posix_termios.h>
#endif
#endif
static int g_fd = 0;
static _ioctl_shoot_para shoot_para_t = {0};
extern void lcd_show_image(int x, int y, int wide, int height,const rt_uint8_t *buf);
extern void lcd_draw_picture(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height, uint32_t *ptr);
void ov2640_test(int argc, char **argv)
{
g_fd = open("/dev/ov2640",O_RDONLY);
if(g_fd < 0)
{
printf("open ov2640 fail !!");
return;
}
if (argc < 2)
{
printf("Usage:ov2640 display images in real time or take photos \n");
printf("Like: ov2640_test 1(take photos )\n");
printf("Like: ov2640_test 0(display images in real time )\n");
close(g_fd);
return ;
}
uint32_t* rgbbuffer = rt_malloc(RGB_BUF_SIZE);
rt_thread_t tid;
rt_err_t ret = 0;
int temf = 0;
if(NULL == rgbbuffer)
{
printf("malloc rgbbuffer failed ! \n");
close(g_fd);
return;
}
temf = strtoul(argv[1],0, 10);
printf("ov2640_test choose %d mode \n",temf);
shoot_para_t.pdata = (uint32_t)(rgbbuffer);
shoot_para_t.length = RGB_BUF_SIZE;
if(temf == 0)
{
void lcd_show_ov2640_thread(uint32_t* rgbbuffer);
tid = rt_thread_create("lcdshow", lcd_show_ov2640_thread, rgbbuffer,3000, 9, 20);
rt_thread_startup(tid);
}
else
{
memset(rgbbuffer,0,320*240*2);
ret = ioctl(g_fd,IOCTRL_CAMERA_START_SHOT,&shoot_para_t);
// ret = rt_ov2640_start_shoot((uint32_t)(rgbbuffer), RGB_BUF_SIZE);
if(RT_ERROR == ret)
{
printf("ov2640 can't wait event flag");
close(g_fd);
return;
}
lcd_show_image(0, 0, 320, 240, rgbbuffer);
rt_thread_mdelay(100);
printf("the lcd has shown the image \n");
rt_free(rgbbuffer);
close(g_fd);
}
}
MSH_CMD_EXPORT(ov2640_test,lcd show camera shot image);
void lcd_show_ov2640_thread(uint32_t* rgbbuffer)
{
rt_err_t ret = 0;
while(1)
{
ret = ioctl(g_fd,IOCTRL_CAMERA_START_SHOT,&shoot_para_t);
if(RT_ERROR == ret)
{
printf("ov2640 can't wait event flag");
rt_free(rgbbuffer);
return;
}
//lcd_show_image(0, 0, 320, 240, rgbbuffer);
lcd_draw_picture(0, 0, 320, 240, rgbbuffer);
rt_thread_mdelay(1);
}
}
#endif

105
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#include <rtthread.h>
#ifdef PKG_USING_RW007
#include <netdb.h>
#include <string.h>
#include <finsh.h>
#include <sys/socket.h>
static const char send_data[] = "This is TCP Client from AIIT";
void rw007_test(int argc, char **argv)
{
int ret;
char *recv_data;
struct hostent *host;
int sock, bytes_received;
struct sockaddr_in server_addr;
const char *url;
int port;
extern rt_bool_t rt_wlan_is_connected(void);
if (rt_wlan_is_connected() != 1)
{
printf("Please connect a wifi firstly\n");
return;
}
if (argc < 3)
{
printf("Usage: rw007 URL PORT\n");
printf("Like: rw007 192.168.12.44 5000\n");
return ;
}
url = argv[1];
port = strtoul(argv[2], 0, 10);
host = gethostbyname(url);
recv_data = rt_malloc(1024);
if (recv_data == RT_NULL)
{
printf("No memory\n");
return;
}
if ((sock = socket(AF_INET, SOCK_STREAM, 0)) == -1)
{
printf("Socket error\n");
rt_free(recv_data);
return;
}
server_addr.sin_family = AF_INET;
server_addr.sin_port = htons(port);
server_addr.sin_addr = *((struct in_addr *)host->h_addr);
rt_memset(&(server_addr.sin_zero), 0, sizeof(server_addr.sin_zero));
if (connect(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)) == -1)
{
printf("Connect fail!\n");
closesocket(sock);
rt_free(recv_data);
return;
}
else
{
printf("Connect successful\n");
}
while (1)
{
bytes_received = recv(sock, recv_data, 1024 - 1, 0);
if (bytes_received < 0)
{
closesocket(sock);
printf("\nreceived error,close the socket.\r\n");
rt_free(recv_data);
break;
}
else if (bytes_received == 0)
{
closesocket(sock);
printf("\nreceived error,close the socket.\r\n");
rt_free(recv_data);
break;
}
recv_data[bytes_received] = '\0';
if (strncmp(recv_data, "q", 1) == 0 || strncmp(recv_data, "Q", 1) == 0)
{
closesocket(sock);
printf("\n got a 'q' or 'Q',close the socket.\r\n");
rt_free(recv_data);
break;
}
else
{
printf("\nReceived data = %s ", recv_data);
}
ret = send(sock, send_data, strlen(send_data), 0);
if (ret < 0)
{
closesocket(sock);
printf("\nsend error,close the socket.\r\n");
rt_free(recv_data);
break;
}
else if (ret == 0)
{
printf("\n Send warning,send function return 0.\r\n");
}
}
return;
}
MSH_CMD_EXPORT(rw007_test, a tcp client sample);
#endif

239
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/Kconfig Normal file
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menu "Board Drivers Config"
config BSP_USING_UART_HS
bool "Enable High Speed UART"
default y
menu "General Purpose UARTs"
menuconfig BSP_USING_UART1
bool "Enable UART1"
default n
if BSP_USING_UART1
config BSP_UART1_TXD_PIN
int "uart1 TXD pin number"
default 20
config BSP_UART1_RXD_PIN
int "uart1 RXD pin number"
default 21
config BSP_UART1_RTS_PIN
int "uart1 RTS pin number (-1 for not used)"
default -1
config BSP_UART1_CTS_PIN
int "uart1 CTS pin number (-1 for not used)"
default -1
endif
menuconfig BSP_USING_UART2
bool "Enable UART2"
default n
if BSP_USING_UART2
config BSP_UART2_TXD_PIN
int "uart2 TXD pin number"
default 28
config BSP_UART2_RXD_PIN
int "uart2 RXD pin number"
default 27
config BSP_UART2_RTS_PIN
int "uart2 RTS pin number (-1 for not used)"
default -1
config BSP_UART2_CTS_PIN
int "uart2 CTS pin number (-1 for not used)"
default -1
endif
menuconfig BSP_USING_UART3
bool "Enable UART3"
default n
if BSP_USING_UART3
config BSP_UART3_TXD_PIN
int "uart3 TXD pin number"
default 22
config BSP_UART3_RXD_PIN
int "uart3 RXD pin number"
default 23
config BSP_UART3_RTS_PIN
int "uart3 RTS pin number (-1 for not used)"
default -1
config BSP_UART3_CTS_PIN
int "uart3 CTS pin number (-1 for not used)"
default -1
endif
endmenu
config BSP_USING_I2C1
bool "Enable I2C1 (GPIO0/1)"
select RT_USING_I2C
default n
menuconfig BSP_USING_SPI1
bool "Enable SPI1"
select RT_USING_SPI
default n
if BSP_USING_SPI1
config BSP_USING_SPI1_AS_QSPI
bool
default n
config BSP_SPI1_CLK_PIN
int "spi1 clk pin number"
default 27
config BSP_SPI1_D0_PIN
int "spi1 d0 pin number"
default 28
config BSP_SPI1_D1_PIN
int "spi1 d1 pin number"
default 26
if BSP_USING_SPI1_AS_QSPI
config BSP_SPI1_D2_PIN
int "spi1 d2 pin number"
default 32
config BSP_SPI1_D3_PIN
int "spi1 d3 pin number"
default 33
endif
menuconfig BSP_SPI1_USING_SS0
bool "SPI1 Enable SS0(spi10 dev)"
default n
if BSP_SPI1_USING_SS0
config BSP_SPI1_SS0_PIN
int "spi1 ss0 pin number"
default 29
endif
menuconfig BSP_SPI1_USING_SS1
bool "SPI1 Enable SS1(spi11 dev)"
default n
if BSP_SPI1_USING_SS1
config BSP_SPI1_SS1_PIN
int "spi1 ss1 pin number"
default 8
endif
menuconfig BSP_SPI1_USING_SS2
bool "SPI1 Enable SS2(spi12 dev)"
default n
if BSP_SPI1_USING_SS2
config BSP_SPI1_SS2_PIN
int "spi1 ss2 pin number"
default 26
endif
menuconfig BSP_SPI1_USING_SS3
bool "SPI1 Enable SS3(spi13 dev)"
default n
if BSP_SPI1_USING_SS3
config BSP_SPI1_SS3_PIN
int "spi1 ss3 pin number"
default 27
endif
endif
menuconfig BSP_USING_LCD
bool "Enable LCD on SPI0"
default n
if BSP_USING_LCD
config BSP_LCD_CS_PIN
int "CS pin number of 8080 interface"
default 36
config BSP_LCD_WR_PIN
int "WR pin number of 8080 interface"
default 39
config BSP_LCD_DC_PIN
int "DC pin number of 8080 interface"
default 38
config BSP_LCD_RST_PIN
int "RESET pin number of 8080 interface (-1 for not used)"
default 37
config BSP_LCD_BACKLIGHT_PIN
int "Backlight control pin number (-1 for not used)"
default -1
choice
prompt "backlight active polarity"
default BSP_LCD_BACKLIGHT_ACTIVE_LOW
config BSP_LCD_BACKLIGHT_ACTIVE_LOW
bool "lcd backlight on low level"
config BSP_LCD_BACKLIGHT_ACTIVE_HIGH
bool "lcd_backlight on high level"
endchoice
config BSP_LCD_CLK_FREQ
int "Lcd max clk frequency"
default 15000000
choice
prompt "lcd scan direction"
default BSP_BOARD_KD233
config BSP_BOARD_KD233
bool "board_kd233 lcd scan: DIR_YX_RLUD"
config BSP_BOARD_K210_OPENMV_TEST
bool "board_k210_openmv lcd scan: DIR_YX_LRUD"
config BSP_BOARD_USER
bool "board_user: user defined."
endchoice
config BSP_LCD_X_MAX
int "LCD Height"
default 240
config BSP_LCD_Y_MAX
int "LCD Width"
default 320
endif
menuconfig BSP_USING_SDCARD
bool "Enable SDCARD (spi1(ss0))"
select BSP_USING_SPI1
select BSP_SPI1_USING_SS0
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
select RT_USING_SPI_MSD
default n
menuconfig BSP_USING_DVP
bool "Enable DVP(camera)"
default n
if BSP_USING_DVP
comment "The default pin assignment is based on the Maix Duino K210 development board"
config BSP_DVP_SCCB_SDA_PIN
int "SCCB SDA pin number for camera"
default 40
config BSP_DVP_SCCB_SCLK_PIN
int "SCCB SCLK pin number for camera"
default 41
config BSP_DVP_CMOS_RST_PIN
int "CMOS RST pin number for camera"
default 42
config BSP_DVP_CMOS_VSYNC_PIN
int "CMOS VSYNC pin number for camera"
default 43
config BSP_DVP_CMOS_PWDN_PIN
int "CMOS PWDN pin number for camera"
default 44
config BSP_DVP_CMOS_XCLK_PIN
int "CMOS XCLK pin number for camera"
default 46
config BSP_DVP_CMOS_PCLK_PIN
int "CMOS PCLK pin number for camera"
default 47
config BSP_DVP_CMOS_HREF_PIN
int "CMOS HREF pin number for camera"
default 45
endif
if PKG_USING_RW007
config RW007_SPIDEV_NAME
string "the SPIDEV rw007 driver on"
default "spi11"
config RW007_INT_BUSY_PIN
int "rw007 int pin for rw007"
default 7
config RW007_RST_PIN
int "rw007 rst pin for rw007"
default 6
endif
endmenu

50
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/SConscript Normal file
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import os
import rtconfig
from building import *
cwd = GetCurrentDir()
drv_path = cwd+"/../../../rt-thread/bsp/k210/driver/"
src = [
'board.c',
'heap.c',
drv_path + 'drv_uart.c',
'drv_interrupt.c',
'drv_io_config.c',
'dmalock.c'
]
CPPPATH = [cwd,drv_path]
if GetDepend('RT_USING_PIN'):
src += ['drv_gpio.c']
if GetDepend('RT_USING_HWTIMER'):
src += [drv_path + 'drv_hw_timer.c']
if GetDepend('RT_USING_I2C'):
src += [drv_path + 'drv_i2c.c']
if GetDepend('RT_USING_SPI'):
src += ['drv_spi.c']
if GetDepend('RT_USING_PWM'):
src += [drv_path + 'drv_pwm.c']
if GetDepend('RT_USING_WDT'):
src += [drv_path + 'drv_wdt.c']
if GetDepend('BSP_USING_SDCARD'):
src += ['sdcard_port.c']
if GetDepend('BSP_USING_DVP'):
src += ['drv_dvp.c']
if GetDepend('BSP_USING_LCD'):
src += ['drv_lcd.c']
src += ['drv_mpylcd.c']
if GetDepend('PKG_USING_RW007'):
src += ['rw007_port.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

144
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/board.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "tick.h"
#include "drv_uart.h"
#include "encoding.h"
#include "fpioa.h"
#include "dmac.h"
#include "dmalock.h"
void init_bss(void)
{
unsigned int *dst;
dst = &__bss_start;
while (dst < &__bss_end)
{
*dst++ = 0;
}
}
void primary_cpu_entry(void)
{
extern void entry(void);
/* disable global interrupt */
init_bss();
rt_hw_interrupt_disable();
entry();
}
#include <clint.h>
#include <sysctl.h>
int freq(void)
{
rt_uint64_t value = 0;
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL0);
rt_kprintf("PLL0: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL1);
rt_kprintf("PLL1: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL2);
rt_kprintf("PLL2: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU);
rt_kprintf("CPU : %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB0);
rt_kprintf("APB0: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB1);
rt_kprintf("APB1: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB2);
rt_kprintf("APB2: %d\n", value);
value = sysctl_clock_get_freq(SYSCTL_CLOCK_HCLK);
rt_kprintf("HCLK: %d\n", value);
value = clint_get_time();
rt_kprintf("mtime: %d\n", value);
return 0;
}
MSH_CMD_EXPORT(freq, show freq info);
#ifdef RT_USING_SMP
extern int rt_hw_clint_ipi_enable(void);
#endif
extern int io_config_init(void);
void rt_hw_board_init(void)
{
sysctl_pll_set_freq(SYSCTL_PLL0, 800000000UL);
sysctl_pll_set_freq(SYSCTL_PLL1, 400000000UL);
sysctl_pll_set_freq(SYSCTL_PLL2, 45158400UL);
sysctl_clock_set_threshold(SYSCTL_THRESHOLD_APB1, 2);
/* Init FPIOA */
fpioa_init();
io_config_init();
/* Dmac init */
dmac_init();
dmalock_init();
/* initalize interrupt */
rt_hw_interrupt_init();
/* initialize hardware interrupt */
rt_hw_uart_init();
rt_hw_tick_init();
#ifdef RT_USING_SMP
rt_hw_clint_ipi_enable();
#endif
#ifdef RT_USING_CONSOLE
/* set console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif /* RT_USING_CONSOLE */
#ifdef RT_USING_HEAP
rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t) RT_HW_HEAP_BEGIN, (rt_ubase_t) RT_HW_HEAP_END);
/* initialize memory system */
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}
void rt_hw_cpu_reset(void)
{
sysctl->soft_reset.soft_reset = 1;
while(1);
}
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
/**
* This function will delay for some us.
*
* @param us the delay time of us
*/
void rt_hw_us_delay(rt_uint32_t usec)
{
rt_uint32_t cycle = read_cycle();
rt_uint32_t nop_all = usec * sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / 1000000UL;
while (1)
{
if(read_cycle() - cycle >= nop_all)
break;
}
}

26
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/board.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
*/
#ifndef BOARD_H__
#define BOARD_H__
#include "fpioa.h"
#include "platform.h"
#include <rtconfig.h>
extern unsigned int __bss_start;
extern unsigned int __bss_end;
#define RT_HW_HEAP_BEGIN (void*)&__bss_end
#define RT_HW_HEAP_END (void*)(0x80000000 + 6 * 1024 * 1024)
void rt_hw_board_init(void);
#endif

90
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/dmalock.c Normal file
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/* Copyright Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <rtthread.h>
#include "dmalock.h"
struct dmac_host
{
struct rt_semaphore sem;
struct rt_mutex mutex;
uint8_t channel_used[DMAC_CHANNEL_COUNT];
char *channel_name[DMAC_CHANNEL_COUNT];
};
static struct dmac_host _dmac_host;
void dmalock_init(void)
{
rt_sem_init(&_dmac_host.sem, "dma_sem", DMAC_CHANNEL_COUNT, RT_IPC_FLAG_FIFO);
rt_mutex_init(&_dmac_host.mutex, "dma_mutex", RT_IPC_FLAG_FIFO);
for (int i = 0; i < DMAC_CHANNEL_COUNT; i++)
{
_dmac_host.channel_used[i] = 0;
_dmac_host.channel_name[i] = NULL;
}
}
int _dmalock_sync_take(dmac_channel_number_t *chn, int timeout_ms, const char *name)
{
rt_err_t result;
*chn = DMAC_CHANNEL_MAX;
result = rt_sem_take(&_dmac_host.sem, timeout_ms);
if (result == RT_EOK)
{
rt_mutex_take(&_dmac_host.mutex, RT_WAITING_FOREVER);
for (int i = 0; i < DMAC_CHANNEL_COUNT; i++)
{
if (_dmac_host.channel_used[i] == 0)
{
_dmac_host.channel_used[i] = 1;
_dmac_host.channel_name[i] = name;
*chn = i;
break;
}
}
rt_mutex_release(&_dmac_host.mutex);
}
return result;
}
void dmalock_release(dmac_channel_number_t chn)
{
if (chn >= DMAC_CHANNEL_MAX)
return;
_dmac_host.channel_name[chn] = NULL;
_dmac_host.channel_used[chn] = 0;
rt_sem_release(&_dmac_host.sem);
}
static void dma_ch_info(int argc, char **argv)
{
uint32_t cnt = 0;
for (int i = 0; i < DMAC_CHANNEL_COUNT; i++)
{
if (_dmac_host.channel_used[i] != 0)
{
rt_kprintf("dma_ch%d is using by func [%s]\n", i, _dmac_host.channel_name[i]);
cnt++;
}
}
if(cnt == 0)
rt_kprintf(" no dma_ch is using.\n");
}
MSH_CMD_EXPORT(dma_ch_info, list dma channel informationn.);

14
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/dmalock.h Normal file
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#ifndef __DMALOCK_H
#define __DMALOCK_H
#include <stdint.h>
#include <rtdef.h>
#include <dmac.h>
#define dmalock_sync_take(x,y) _dmalock_sync_take(x, y, __func__)
void dmalock_init(void);
int _dmalock_sync_take(dmac_channel_number_t *chn, int timeout_ms, const char *name);
void dmalock_release(dmac_channel_number_t chn);
#endif

167
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/drv_dvp.c Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-27 tianchunyu the first version
*/
#include <rtthread.h>
#include <stdio.h>
#ifdef BSP_USING_DVP
#include <drv_dvp.h>
#define DRV_DEBUG
#define LOG_TAG "drv.dvp"
#define DBG_LVL DBG_LOG
#include <rtdbg.h>
static struct kendryte_dvp rt_dvp = {0};
static void (*dvp_irq_callback)(void) = NULL;
/*
the camera starts transfering photos
*/
static int on_irq_dvp(void* ctx)
{
if (dvp_get_interrupt(DVP_STS_FRAME_FINISH))
{
rt_dvp_stop();
dvp_clear_interrupt(DVP_STS_FRAME_FINISH);
(*dvp_irq_callback)();
}
return 0;
}
void rt_dvp_start(uint32_t pData, uint32_t Length)
{
dvp_set_display_addr(pData);
dvp_config_interrupt(DVP_CFG_FINISH_INT_ENABLE, 1);
dvp_start_convert();
}
/*
the camera stops transfering photos
*/
void rt_dvp_stop(void)
{
dvp_config_interrupt(DVP_CFG_FINISH_INT_ENABLE, 0);
}
static rt_err_t rt_dvp_init(rt_device_t dev)
{
//sysctl_pll_set_freq(SYSCTL_PLL2, 45158400UL);
RT_ASSERT(dev != RT_NULL);
rt_err_t result = RT_EOK;
/* Init DVP IO map and function settings io pin serial number depends on schematic diagram
initialize io in io_config_init function*/
/*ov2640 dvp interface initialize*/
dvp_init(8);
dvp_set_xclk_rate(24000000);
dvp_enable_burst();
dvp_set_output_enable(0, 1);
dvp_set_output_enable(1, 1);
dvp_set_image_format(DVP_CFG_RGB_FORMAT);////////////////
dvp_set_image_size(320, 240); // default
dvp_config_interrupt(DVP_CFG_FINISH_INT_ENABLE, 0);
dvp_disable_auto();
plic_set_priority(IRQN_DVP_INTERRUPT, 1);
plic_irq_register(IRQN_DVP_INTERRUPT, on_irq_dvp, NULL);
plic_irq_enable(IRQN_DVP_INTERRUPT);
dvp_clear_interrupt(DVP_STS_FRAME_FINISH);
LOG_I("dvp initialize success");
return result;
}
static rt_err_t rt_dvp_open(rt_device_t dev, rt_uint16_t oflag)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_err_t rt_dvp_close(rt_device_t dev)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_err_t rt_dvp_control(rt_device_t dev, int cmd, void *args)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_size_t rt_dvp_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
static rt_size_t rt_dvp_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
RT_ASSERT(dev != RT_NULL);
return RT_EOK;
}
rt_err_t rt_set_irq_dvp_callback_hander(void (*p)(void))
{
if(NULL == p)
{
LOG_E("set irq dcmi callback hander is NULL");
return RT_ERROR;
}
dvp_irq_callback = p;
return RT_EOK;
}
int kendryte_dvp_init(void)
{
int ret = 0;
rt_device_t dvp_dev = RT_NULL;
rt_dvp.dev.parent.type = RT_Device_Class_Miscellaneous;
rt_dvp.dev.parent.init = rt_dvp_init;
rt_dvp.dev.parent.open = rt_dvp_open;
rt_dvp.dev.parent.close = rt_dvp_close;
rt_dvp.dev.parent.read = rt_dvp_read;
rt_dvp.dev.parent.write = rt_dvp_write;
rt_dvp.dev.parent.control = rt_dvp_control;
rt_dvp.dev.parent.user_data = RT_NULL;
ret = rt_device_register(&rt_dvp.dev.parent, "dvp", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
if(ret != RT_EOK)
{
LOG_E("dvp register fail!!\n\r");
return -RT_ERROR;
}
LOG_I("dvp register successfully");
dvp_dev = rt_device_find("dvp");
if (dvp_dev == RT_NULL)
{
LOG_E("can't find dvp device!");
return RT_ERROR;
}
ret = rt_device_open(dvp_dev, RT_DEVICE_FLAG_RDWR);
if(ret != RT_EOK)
{
LOG_E("can't open dvp device!");
return RT_ERROR;
}
LOG_I("dvp open successfully");
return RT_EOK;
}
INIT_BOARD_EXPORT(kendryte_dvp_init);
#endif

46
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/drv_dvp.h Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-27 tianchunyu the first version
*/
#ifndef __DRV_DVP_H__
#define __DRV_DVP_H__
#include <dvp.h>
#include <fpioa.h>
#include <sysctl.h>
#include <plic.h>
#include <sysctl.h>
#ifdef __cplusplus
extern "C" {
#endif
struct rt_dvp_device
{
struct rt_device parent;
};
struct kendryte_dvp
{
struct rt_dvp_device dev;
};
extern void rt_dvp_start(uint32_t pData, uint32_t Length);
extern void rt_dvp_stop(void);
extern rt_err_t rt_set_irq_dvp_callback_hander(void (*p)(void));
#ifdef __cplusplus
}
#endif
#endif

267
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/drv_gpio.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <fpioa.h>
#include <gpiohs.h>
#include "drv_gpio.h"
#include "drv_io_config.h"
#include <plic.h>
#include <rthw.h>
#include <utils.h>
#include <string.h>
#define DBG_ENABLE
#define DBG_TAG "PIN"
#define DBG_LVL DBG_WARNING
#define DBG_COLOR
#include <rtdbg.h>
#define FUNC_GPIOHS(n) (FUNC_GPIOHS0 + n)
static short pin_alloc_table[FPIOA_NUM_IO];
static uint32_t free_pin = 0;
static int alloc_pin_channel(rt_base_t pin_index)
{
if(free_pin == 32)
{
LOG_E("no free gpiohs channel to alloc");
return -1;
}
if(pin_alloc_table[pin_index] != -1)
{
LOG_W("already alloc gpiohs channel for pin %d", pin_index);
return pin_alloc_table[pin_index];
}
pin_alloc_table[pin_index] = free_pin;
free_pin++;
fpioa_set_function(pin_index, FUNC_GPIOHS(pin_alloc_table[pin_index]));
return pin_alloc_table[pin_index];
}
int get_pin_channel(rt_base_t pin_index)
{
return pin_alloc_table[pin_index];
}
static void free_pin_channel(rt_base_t pin_index)
{
if(pin_alloc_table[pin_index] == -1)
{
LOG_W("free error:not alloc gpiohs channel for pin %d", pin_index);
return;
}
pin_alloc_table[pin_index] = -1;
free_pin--;
}
static void drv_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
{
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
pin_channel = alloc_pin_channel(pin);
if(pin_channel == -1)
{
return;
}
}
switch (mode)
{
case PIN_MODE_OUTPUT:
gpiohs_set_drive_mode(pin_channel, GPIO_DM_OUTPUT);
break;
case PIN_MODE_INPUT:
gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT);
break;
case PIN_MODE_INPUT_PULLUP:
gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT_PULL_UP);
break;
case PIN_MODE_INPUT_PULLDOWN:
gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT_PULL_DOWN);
break;
default:
LOG_E("Not support mode %d", mode);
break;
}
}
static void drv_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
{
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return;
}
gpiohs_set_pin(pin_channel, value == PIN_HIGH ? GPIO_PV_HIGH : GPIO_PV_LOW);
}
static int drv_pin_read(struct rt_device *device, rt_base_t pin)
{
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return -1;
}
return gpiohs_get_pin(pin_channel) == GPIO_PV_HIGH ? PIN_HIGH : PIN_LOW;
}
static struct
{
void (*hdr)(void *args);
void* args;
gpio_pin_edge_t edge;
} irq_table[32];
static void pin_irq(int vector, void *param)
{
int pin_channel = vector - IRQN_GPIOHS0_INTERRUPT;
if(irq_table[pin_channel].edge & GPIO_PE_FALLING)
{
set_gpio_bit(gpiohs->fall_ie.u32, pin_channel, 0);
set_gpio_bit(gpiohs->fall_ip.u32, pin_channel, 1);
set_gpio_bit(gpiohs->fall_ie.u32, pin_channel, 1);
}
if(irq_table[pin_channel].edge & GPIO_PE_RISING)
{
set_gpio_bit(gpiohs->rise_ie.u32, pin_channel, 0);
set_gpio_bit(gpiohs->rise_ip.u32, pin_channel, 1);
set_gpio_bit(gpiohs->rise_ie.u32, pin_channel, 1);
}
if(irq_table[pin_channel].edge & GPIO_PE_LOW)
{
set_gpio_bit(gpiohs->low_ie.u32, pin_channel, 0);
set_gpio_bit(gpiohs->low_ip.u32, pin_channel, 1);
set_gpio_bit(gpiohs->low_ie.u32, pin_channel, 1);
}
if(irq_table[pin_channel].edge & GPIO_PE_HIGH)
{
set_gpio_bit(gpiohs->high_ie.u32, pin_channel, 0);
set_gpio_bit(gpiohs->high_ip.u32, pin_channel, 1);
set_gpio_bit(gpiohs->high_ie.u32, pin_channel, 1);
}
if(irq_table[pin_channel].hdr)
{
irq_table[pin_channel].hdr(irq_table[pin_channel].args);
}
}
static rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
int pin_channel = get_pin_channel(pin);
char irq_name[10];
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return -RT_ERROR;
}
irq_table[pin_channel].hdr = hdr;
irq_table[pin_channel].args = args;
switch (mode)
{
case PIN_IRQ_MODE_RISING:
irq_table[pin_channel].edge = GPIO_PE_RISING;
break;
case PIN_IRQ_MODE_FALLING:
irq_table[pin_channel].edge = GPIO_PE_FALLING;
break;
case PIN_IRQ_MODE_RISING_FALLING:
irq_table[pin_channel].edge = GPIO_PE_BOTH;
break;
case PIN_IRQ_MODE_HIGH_LEVEL:
irq_table[pin_channel].edge = GPIO_PE_LOW;
break;
case PIN_IRQ_MODE_LOW_LEVEL:
irq_table[pin_channel].edge = GPIO_PE_HIGH;
break;
default:
break;
}
gpiohs_set_pin_edge(pin_channel, irq_table[pin_channel].edge);
rt_snprintf(irq_name, sizeof irq_name, "pin%d", pin);
rt_hw_interrupt_install(IRQN_GPIOHS0_INTERRUPT + pin_channel, pin_irq, RT_NULL, irq_name);
return RT_EOK;
}
static rt_err_t drv_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{
rt_err_t ret = RT_EOK;
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return -RT_ERROR;
}
irq_table[pin_channel].hdr = RT_NULL;
irq_table[pin_channel].args = RT_NULL;
return ret;
}
static rt_err_t drv_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
{
int pin_channel = get_pin_channel(pin);
if(pin_channel == -1)
{
LOG_E("pin %d not set mode", pin);
return -RT_ERROR;
}
if(enabled)
{
rt_hw_interrupt_umask(IRQN_GPIOHS0_INTERRUPT + pin_channel);
}
else
{
rt_hw_interrupt_mask(IRQN_GPIOHS0_INTERRUPT + pin_channel);
}
return RT_EOK;
}
const static struct rt_pin_ops drv_pin_ops =
{
drv_pin_mode,
drv_pin_write,
drv_pin_read,
drv_pin_attach_irq,
drv_pin_detach_irq,
drv_pin_irq_enable
};
int rt_hw_pin_init(void)
{
rt_err_t ret = RT_EOK;
memset(pin_alloc_table, 0xff, sizeof pin_alloc_table);
free_pin = GPIO_ALLOC_START;
ret = rt_device_pin_register("pin", &drv_pin_ops, RT_NULL);
return ret;
}
INIT_BOARD_EXPORT(rt_hw_pin_init);

16
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/drv_gpio.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#ifndef DRV_GPIO_H__
#define DRV_GPIO_H__
int rt_hw_pin_init(void);
#endif

27
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/drv_interrupt.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#include <plic.h>
void plic_irq_handle(plic_irq_t irq)
{
plic_instance_t (*plic_instance)[IRQN_MAX] = plic_get_instance();
if (plic_instance[0][irq].callback)
{
plic_instance[0][irq].callback(
plic_instance[0][irq].ctx);
}
else if (plic_instance[1][irq].callback)
{
plic_instance[1][irq].callback(
plic_instance[1][irq].ctx);
}
}

219
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/drv_io_config.c Normal file
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@@ -0,0 +1,219 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#include <rtthread.h>
#include <fpioa.h>
#include <drv_io_config.h>
#include <sysctl.h>
#define HS_GPIO(n) (FUNC_GPIOHS0 + n)
#define IOCONFIG(pin,func) {pin, func, #func}
static struct io_config
{
int io_num;
fpioa_function_t func;
const char * func_name;
} io_config[] =
{
#ifdef BSP_USING_LCD
IOCONFIG(BSP_LCD_CS_PIN, FUNC_SPI0_SS0), /* LCD CS PIN */
IOCONFIG(BSP_LCD_WR_PIN, FUNC_SPI0_SCLK), /* LCD WR PIN */
IOCONFIG(BSP_LCD_DC_PIN, HS_GPIO(LCD_DC_PIN)), /* LCD DC PIN */
#if BSP_LCD_RST_PIN >= 0
IOCONFIG(BSP_LCD_RST_PIN, HS_GPIO(LCD_RST_PIN)), /* LCD RESET PIN */
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
IOCONFIG(BSP_LCD_BACKLIGHT_PIN, HS_GPIO(LCD_BACKLIGHT_PIN)), /* LCD BACKLIGHT PIN */
#endif
#endif
#ifdef BSP_USING_DVP
IOCONFIG(BSP_DVP_SCCB_SDA_PIN, FUNC_SCCB_SDA),
IOCONFIG(BSP_DVP_SCCB_SCLK_PIN, FUNC_SCCB_SCLK),
IOCONFIG(BSP_DVP_CMOS_RST_PIN, FUNC_CMOS_RST),
IOCONFIG(BSP_DVP_CMOS_VSYNC_PIN, FUNC_CMOS_VSYNC),
IOCONFIG(BSP_DVP_CMOS_PWDN_PIN, FUNC_CMOS_PWDN),
IOCONFIG(BSP_DVP_CMOS_XCLK_PIN, FUNC_CMOS_XCLK),
IOCONFIG(BSP_DVP_CMOS_PCLK_PIN, FUNC_CMOS_PCLK),
IOCONFIG(BSP_DVP_CMOS_HREF_PIN, FUNC_CMOS_HREF),
#endif
#ifdef BSP_USING_SPI1
IOCONFIG(BSP_SPI1_CLK_PIN, FUNC_SPI1_SCLK),
IOCONFIG(BSP_SPI1_D0_PIN, FUNC_SPI1_D0),
IOCONFIG(BSP_SPI1_D1_PIN, FUNC_SPI1_D1),
#ifdef BSP_USING_SPI1_AS_QSPI
IOCONFIG(BSP_SPI1_D2_PIN, FUNC_SPI1_D2),
IOCONFIG(BSP_SPI1_D3_PIN, FUNC_SPI1_D3),
#endif
#ifdef BSP_SPI1_USING_SS0
IOCONFIG(BSP_SPI1_SS0_PIN, HS_GPIO(SPI1_CS0_PIN)),
#endif
#ifdef BSP_SPI1_USING_SS1
IOCONFIG(BSP_SPI1_SS1_PIN, HS_GPIO(SPI1_CS1_PIN)),
#endif
#ifdef BSP_SPI1_USING_SS2
IOCONFIG(BSP_SPI1_SS2_PIN, HS_GPIO(SPI1_CS2_PIN)),
#endif
#ifdef BSP_SPI1_USING_SS3
IOCONFIG(BSP_SPI1_SS3_PIN, HS_GPIO(SPI1_CS3_PIN)),
#endif
#endif
#ifdef BSP_USING_UART1
IOCONFIG(BSP_UART1_TXD_PIN, FUNC_UART1_TX),
IOCONFIG(BSP_UART1_RXD_PIN, FUNC_UART1_RX),
#if BSP_UART1_RTS_PIN >= 0
IOCONFIG(BSP_UART1_RTS_PIN, FUNC_UART1_RTS),
#endif
#if BSP_UART1_CTS_PIN >= 0
IOCONFIG(BSP_UART1_CTS_PIN, FUNC_UART1_CTS),
#endif
#endif
#ifdef BSP_USING_UART2
IOCONFIG(BSP_UART2_TXD_PIN, FUNC_UART2_TX),
IOCONFIG(BSP_UART2_RXD_PIN, FUNC_UART2_RX),
#if BSP_UART2_RTS_PIN >= 0
IOCONFIG(BSP_UART2_RTS_PIN, FUNC_UART2_RTS),
#endif
#if BSP_UART2_CTS_PIN >= 0
IOCONFIG(BSP_UART2_CTS_PIN, FUNC_UART2_CTS),
#endif
#endif
#ifdef BSP_USING_UART3
IOCONFIG(BSP_UART3_TXD_PIN, FUNC_UART3_TX),
IOCONFIG(BSP_UART3_RXD_PIN, FUNC_UART3_RX),
#if BSP_UART3_RTS_PIN >= 0
IOCONFIG(BSP_UART3_RTS_PIN, FUNC_UART3_RTS),
#endif
#if BSP_UART3_CTS_PIN >= 0
IOCONFIG(BSP_UART3_CTS_PIN, FUNC_UART3_CTS),
#endif
#endif
#ifdef BSP_USING_I2C0
IOCONFIG(BSP_I2C0_SCL_PIN, FUNC_I2C0_SCLK),
IOCONFIG(BSP_I2C0_SDA_PIN, FUNC_I2C0_SDA),
#endif
#ifdef BSP_USING_I2C1
IOCONFIG(BSP_I2C1_SCL_PIN, FUNC_I2C1_SCLK),
IOCONFIG(BSP_I2C1_SDA_PIN, FUNC_I2C1_SDA),
#endif
#ifdef BSP_USING_I2C2
IOCONFIG(BSP_I2C2_SCL_PIN, FUNC_I2C2_SCLK),
IOCONFIG(BSP_I2C2_SDA_PIN, FUNC_I2C2_SDA),
#endif
#ifdef BSP_USING_I2S0
IOCONFIG(BSP_I2S0_OUT_D1_PIN, FUNC_I2S0_OUT_D1),
IOCONFIG(BSP_I2S0_WS_PIN, FUNC_I2S0_WS),
IOCONFIG(BSP_I2S0_SCLK_PIN, FUNC_I2S0_SCLK),
#endif
#ifdef BSP_USING_I2S1
IOCONFIG(BSP_I2S1_IN_D0_PIN, FUNC_I2S1_IN_D0),
IOCONFIG(BSP_I2S1_WS_PIN, FUNC_I2S1_WS),
IOCONFIG(BSP_I2S1_SCLK_PIN, FUNC_I2S1_SCLK),
#endif
#ifdef BSP_USING_I2S2
IOCONFIG(BSP_I2S2_OUT_D1_PIN, FUNC_I2S2_OUT_D1),
IOCONFIG(BSP_I2S2_WS_PIN, FUNC_I2S2_WS),
IOCONFIG(BSP_I2S2_SCLK_PIN, FUNC_I2S2_SCLK),
#endif
#ifdef BSP_PWM_CHN0_ENABLE
IOCONFIG(BSP_PWM_CHN0_PIN, FUNC_TIMER2_TOGGLE1),
#endif
#ifdef BSP_PWM_CHN1_ENABLE
IOCONFIG(BSP_PWM_CHN1_PIN, FUNC_TIMER2_TOGGLE2),
#endif
#ifdef BSP_PWM_CHN2_ENABLE
IOCONFIG(BSP_PWM_CHN2_PIN, FUNC_TIMER2_TOGGLE3),
#endif
#ifdef BSP_PWM_CHN3_ENABLE
IOCONFIG(BSP_PWM_CHN3_PIN, FUNC_TIMER2_TOGGLE4),
#endif
};
static int print_io_config()
{
int i;
rt_kprintf("IO Configuration Table\n");
rt_kprintf("┌───────┬────────────────────────┐\n");
rt_kprintf("│Pin │Function │\n");
rt_kprintf("├───────┼────────────────────────┤\n");
for(i = 0; i < sizeof io_config / sizeof io_config[0]; i++)
{
rt_kprintf("│%-2d │%-24.24s│\n", io_config[i].io_num, io_config[i].func_name);
}
rt_kprintf("└───────┴────────────────────────┘\n");
return 0;
}
MSH_CMD_EXPORT_ALIAS(print_io_config, io, print io config);
int io_config_init(void)
{
int count = sizeof(io_config) / sizeof(io_config[0]);
int i;
/* IO GroupA Power Supply Setting */
#if defined(BSP_GROUPA_POWER_SUPPLY_3V3)
sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V33);
#else
sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V18);
#endif
/* IO GroupB Power Supply Setting */
#if defined(BSP_GROUPB_POWER_SUPPLY_3V3)
sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK5, SYSCTL_POWER_V33);
#else
sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK5, SYSCTL_POWER_V18);
#endif
/* IO GroupC Power Supply Setting */
#if defined(BSP_GROUPC_POWER_SUPPLY_3V3)
sysctl_set_power_mode(SYSCTL_POWER_BANK6, SYSCTL_POWER_V33);
sysctl_set_power_mode(SYSCTL_POWER_BANK7, SYSCTL_POWER_V33);
#else
sysctl_set_power_mode(SYSCTL_POWER_BANK6, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK7, SYSCTL_POWER_V18);
#endif
for(i = 0; i < count; i++)
{
fpioa_set_function(io_config[i].io_num, io_config[i].func);
}
#if defined(BSP_USING_DVP) || defined(BSP_USING_LCD)
sysctl_set_spi0_dvp_data(1);
sysctl_clock_enable(SYSCTL_CLOCK_AI);
#endif
}
int io_config_used(int io_num)
{
int count = sizeof(io_config) / sizeof(io_config[0]);
int i;
for(i = 0; i < count; i++)
{
if (io_config[i].io_num == io_num)
break;
}
return (i < count);
}

49
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/drv_io_config.h Normal file
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@@ -0,0 +1,49 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-19 ZYH first version
*/
#ifndef __DRV_IO_CONFIG_H__
#define __DRV_IO_CONFIG_H__
#include <rtconfig.h>
enum HS_GPIO_CONFIG
{
#ifdef BSP_USING_LCD
LCD_DC_PIN = 0, /* LCD DC PIN */
#if BSP_LCD_RST_PIN >= 0
LCD_RST_PIN,
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
LCD_BACKLIGHT_PIN,
#endif
#endif
#ifdef BSP_SPI1_USING_SS0
SPI1_CS0_PIN,
#endif
#ifdef BSP_SPI1_USING_SS1
SPI1_CS1_PIN,
#endif
#ifdef BSP_SPI1_USING_SS2
SPI1_CS2_PIN,
#endif
#ifdef BSP_SPI1_USING_SS3
SPI1_CS3_PIN,
#endif
#ifdef BSP_USING_BRIDGE
SPI2_INT_PIN,
SPI2_READY_PIN,
#endif
GPIO_ALLOC_START /* index of gpio driver start */
};
extern int io_config_init(void);
#endif

550
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/drv_lcd.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-12 ZYH first version
*/
#include <rtthread.h>
#ifdef BSP_USING_LCD
#include <drv_lcd.h>
#define DBG_TAG "LCD"
#define DBG_LVL DBG_WARNING
#include <rtdbg.h>
#define NO_OPERATION 0x00
#define SOFTWARE_RESET 0x01
#define READ_ID 0x04
#define READ_STATUS 0x09
#define READ_POWER_MODE 0x0A
#define READ_MADCTL 0x0B
#define READ_PIXEL_FORMAT 0x0C
#define READ_IMAGE_FORMAT 0x0D
#define READ_SIGNAL_MODE 0x0E
#define READ_SELT_DIAG_RESULT 0x0F
#define SLEEP_ON 0x10
#define SLEEP_OFF 0x11
#define PARTIAL_DISPALY_ON 0x12
#define NORMAL_DISPALY_ON 0x13
#define INVERSION_DISPALY_OFF 0x20
#define INVERSION_DISPALY_ON 0x21
#define GAMMA_SET 0x26
#define DISPALY_OFF 0x28
#define DISPALY_ON 0x29
#define HORIZONTAL_ADDRESS_SET 0x2A
#define VERTICAL_ADDRESS_SET 0x2B
#define MEMORY_WRITE 0x2C
#define COLOR_SET 0x2D
#define MEMORY_READ 0x2E
#define PARTIAL_AREA 0x30
#define VERTICAL_SCROL_DEFINE 0x33
#define TEAR_EFFECT_LINE_OFF 0x34
#define TEAR_EFFECT_LINE_ON 0x35
#define MEMORY_ACCESS_CTL 0x36
#define VERTICAL_SCROL_S_ADD 0x37
#define IDLE_MODE_OFF 0x38
#define IDLE_MODE_ON 0x39
#define PIXEL_FORMAT_SET 0x3A
#define WRITE_MEMORY_CONTINUE 0x3C
#define READ_MEMORY_CONTINUE 0x3E
#define SET_TEAR_SCANLINE 0x44
#define GET_SCANLINE 0x45
#define WRITE_BRIGHTNESS 0x51
#define READ_BRIGHTNESS 0x52
#define WRITE_CTRL_DISPALY 0x53
#define READ_CTRL_DISPALY 0x54
#define WRITE_BRIGHTNESS_CTL 0x55
#define READ_BRIGHTNESS_CTL 0x56
#define WRITE_MIN_BRIGHTNESS 0x5E
#define READ_MIN_BRIGHTNESS 0x5F
#define READ_ID1 0xDA
#define READ_ID2 0xDB
#define READ_ID3 0xDC
#define RGB_IF_SIGNAL_CTL 0xB0
#define NORMAL_FRAME_CTL 0xB1
#define IDLE_FRAME_CTL 0xB2
#define PARTIAL_FRAME_CTL 0xB3
#define INVERSION_CTL 0xB4
#define BLANK_PORCH_CTL 0xB5
#define DISPALY_FUNCTION_CTL 0xB6
#define ENTRY_MODE_SET 0xB7
#define BACKLIGHT_CTL1 0xB8
#define BACKLIGHT_CTL2 0xB9
#define BACKLIGHT_CTL3 0xBA
#define BACKLIGHT_CTL4 0xBB
#define BACKLIGHT_CTL5 0xBC
#define BACKLIGHT_CTL7 0xBE
#define BACKLIGHT_CTL8 0xBF
#define POWER_CTL1 0xC0
#define POWER_CTL2 0xC1
#define VCOM_CTL1 0xC5
#define VCOM_CTL2 0xC7
#define NV_MEMORY_WRITE 0xD0
#define NV_MEMORY_PROTECT_KEY 0xD1
#define NV_MEMORY_STATUS_READ 0xD2
#define READ_ID4 0xD3
#define POSITIVE_GAMMA_CORRECT 0xE0
#define NEGATIVE_GAMMA_CORRECT 0xE1
#define DIGITAL_GAMMA_CTL1 0xE2
#define DIGITAL_GAMMA_CTL2 0xE3
#define INTERFACE_CTL 0xF6
#define LCD_SPI_CHANNEL SPI_DEVICE_0
#define LCD_SPI_CHIP_SELECT SPI_CHIP_SELECT_0
#if defined(BSP_BOARD_K210_OPENMV_TEST)
#define LCD_SCAN_DIR DIR_YX_LRUD
#elif defined(BSP_BOARD_KD233)
#define LCD_SCAN_DIR (DIR_YX_RLUD | 0x08)
#elif defined(BSP_BOARD_USER)
/*user define.*/
#define LCD_SCAN_DIR DIR_YX_RLDU
#endif
static struct lcd_8080_device _lcddev;
static void drv_lcd_cmd(lcd_8080_device_t lcd, rt_uint8_t cmd)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_LOW);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
spi_init_non_standard(lcd->spi_channel, 8 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, &cmd, 1, SPI_TRANS_CHAR);
}
static void drv_lcd_data_byte(lcd_8080_device_t lcd, rt_uint8_t *data_buf, rt_uint32_t length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
spi_init_non_standard(lcd->spi_channel, 8 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_CHAR);
}
void drv_lcd_data_half_word(lcd_8080_device_t lcd, rt_uint16_t *data_buf, rt_uint32_t length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 16, 0);
spi_init_non_standard(lcd->spi_channel, 16 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_SHORT);
}
void drv_lcd_data_word(lcd_8080_device_t lcd, rt_uint32_t *data_buf, rt_uint32_t length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0);
spi_init_non_standard(lcd->spi_channel, 0 /*instrction length*/, 32 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_INT);
}
static void drv_lcd_hw_init(lcd_8080_device_t lcd)
{
#if BSP_LCD_RST_PIN >= 0
{
gpiohs_set_drive_mode(lcd->rst_pin, GPIO_DM_OUTPUT);
gpiohs_set_pin(lcd->rst_pin, GPIO_PV_LOW);
rt_thread_mdelay(20);
gpiohs_set_pin(lcd->rst_pin, GPIO_PV_HIGH);
rt_thread_mdelay(20);
}
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
{
gpiohs_set_drive_mode(lcd->backlight_pin, GPIO_DM_OUTPUT);
#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH);
#else
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#endif
}
#endif
gpiohs_set_drive_mode(lcd->dc_pin, GPIO_DM_OUTPUT);
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
spi_set_clk_rate(lcd->spi_channel, BSP_LCD_CLK_FREQ);
}
static void drv_lcd_set_direction(lcd_8080_device_t lcd, lcd_dir_t dir)
{
if (dir & DIR_XY_MASK)
{
lcd->lcd_info.width = BSP_LCD_Y_MAX;
lcd->lcd_info.height = BSP_LCD_X_MAX;
}
else
{
lcd->lcd_info.width = BSP_LCD_X_MAX;
lcd->lcd_info.height = BSP_LCD_Y_MAX;
}
rt_kprintf("lcd witdth %d,height %d \n",lcd->lcd_info.width,lcd->lcd_info.height);
drv_lcd_cmd(lcd, MEMORY_ACCESS_CTL);
drv_lcd_data_byte(lcd, (rt_uint8_t *)&dir, 1);
}
void drv_lcd_set_area(lcd_8080_device_t lcd, rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2)
{
rt_uint8_t data[4] = {0};
data[0] = (rt_uint8_t)(x1 >> 8);
data[1] = (rt_uint8_t)(x1);
data[2] = (rt_uint8_t)(x2 >> 8);
data[3] = (rt_uint8_t)(x2);
drv_lcd_cmd(lcd, HORIZONTAL_ADDRESS_SET);
drv_lcd_data_byte(lcd, data, 4);
data[0] = (rt_uint8_t)(y1 >> 8);
data[1] = (rt_uint8_t)(y1);
data[2] = (rt_uint8_t)(y2 >> 8);
data[3] = (rt_uint8_t)(y2);
drv_lcd_cmd(lcd, VERTICAL_ADDRESS_SET);
drv_lcd_data_byte(lcd, data, 4);
drv_lcd_cmd(lcd, MEMORY_WRITE);
}
static void drv_lcd_set_pixel(lcd_8080_device_t lcd, uint16_t x, uint16_t y, uint16_t color)
{
drv_lcd_set_area(lcd, x, y, x, y);
drv_lcd_data_half_word(lcd, &color, 1);
}
static void drv_lcd_clear(lcd_8080_device_t lcd, uint16_t color)
{
uint32_t data = ((uint32_t)color << 16) | (uint32_t)color;
drv_lcd_set_area(lcd, 0, 0, lcd->lcd_info.width - 1, lcd->lcd_info.height - 1);
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0);
spi_init_non_standard(lcd->spi_channel, 0 /*instrction length*/, 32 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_fill_data_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, (const uint32_t *)&data, lcd->lcd_info.width * lcd->lcd_info.height / 2);
}
static void rt_bitblt(rt_uint16_t * dest, int dest_segment, int dest_common, int dest_x, int dest_y, int width, int height,
rt_uint16_t *src, int src_segment, int src_common, int src_x, int src_y)
{
int sx0, sx1, sy0, sy1;
int dx0, dx1, dy0, dy1;
rt_uint16_t *buff_src;
rt_uint16_t *buff_dest;
int x, y;
if (width <= 0) {
return;
}
if (height <= 0) {
return;
}
sx0 = src_x;
sy0 = src_y;
sx1 = sx0 + width - 1;
sy1 = sy0 + height - 1;
dx0 = dest_x;
dy0 = dest_y;
dx1 = dx0 + width - 1;
dy1 = dy0 + height - 1;
if (sx0 < 0) {
dx0 -= sx0;
sx0 = 0;
}
if (sy0 < 0) {
dy0 -= sy0;
sy0 = 0;
}
if (sx1 >= src_segment) {
dx1 -= (sx1 - src_segment + 1);
sx1 = src_segment - 1;
}
if (sy1 >= src_common) {
dy1 -= (sy1 - src_common + 1);
sy1 = src_common - 1;
}
if (dx0 < 0) {
sx0 -= dx0;
dx0 = 0;
}
if (dy0 < 0) {
sy0 -= dy0;
dy0 = 0;
}
if (dx1 >= dest_segment) {
sx1 -= (dx1 - dest_segment + 1);
dx1 = dest_segment - 1;
}
if (dy1 >= dest_common) {
sy1 -= (dy1 - dest_common + 1);
dy1 = dest_common - 1;
}
if (sx1 < 0 || sx0 >= src_segment) {
return;
}
if (sy1 < 0 || sy0 >= src_common) {
return;
}
if (dx1 < 0 || dx0 >= dest_segment) {
return;
}
if (dy1 < 0 || dy0 >= dest_common) {
return;
}
if ((rt_ubase_t)dest < (rt_ubase_t)src) {
buff_src = src + (sy0 * src_segment) + sx0;
buff_dest = dest + (dy0 * dest_segment) + dx0;
for (y = sy0; y <= sy1; y++) {
src = buff_src;
dest = buff_dest;
for (x = sx0; x <= sx1; x++) {
*dest++ = *src++;
}
buff_src += src_segment;
buff_dest += dest_segment;
}
} else {
buff_src = src + (sy1 * src_segment) + sx1;
buff_dest = dest + (dy1 * dest_segment) + dx1;
for (y = sy1; y >= sy0; y--) {
src = buff_src;
dest = buff_dest;
for (x = sx1; x >= sx0; x--) {
*dest-- = *src--;
}
buff_src -= src_segment;
buff_dest -= dest_segment;
}
}
}
static void drv_lcd_rect_update(lcd_8080_device_t lcd, uint16_t x1, uint16_t y1, uint16_t width, uint16_t height)
{
static rt_uint16_t * rect_buffer = RT_NULL;
if(!rect_buffer)
{
rect_buffer = rt_malloc_align(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8), 64);
if(!rect_buffer)
{
return;
}
}
if(x1 == 0 && y1 == 0 && width == lcd->lcd_info.width && height == lcd->lcd_info.height)
{
drv_lcd_set_area(lcd, x1, y1, x1 + width - 1, y1 + height - 1);
drv_lcd_data_half_word(lcd, (rt_uint32_t *)lcd->lcd_info.framebuffer, width * height);
}
else
{
rt_bitblt(rect_buffer, width, height, 0, 0, width, height,(rt_uint16_t *)lcd->lcd_info.framebuffer, lcd->lcd_info.width, lcd->lcd_info.height, x1, y1);
drv_lcd_set_area(lcd, x1, y1, x1 + width - 1, y1 + height - 1);
drv_lcd_data_half_word(lcd, (rt_uint16_t *)rect_buffer, width * height);
}
}
static rt_err_t drv_lcd_init(rt_device_t dev)
{
rt_err_t ret = RT_EOK;
lcd_8080_device_t lcd = (lcd_8080_device_t)dev;
rt_uint8_t data = 0;
if(!lcd)
{
return RT_ERROR;
}
drv_lcd_hw_init(lcd);
/* reset LCD */
drv_lcd_cmd(lcd, SOFTWARE_RESET);
rt_thread_mdelay(100);
/* Enter normal status */
drv_lcd_cmd(lcd, SLEEP_OFF);
rt_thread_mdelay(100);
/* pixel format rgb565 */
drv_lcd_cmd(lcd, PIXEL_FORMAT_SET);
data = 0x55;
drv_lcd_data_byte(lcd, &data, 1);
/* set direction */
drv_lcd_set_direction(lcd, LCD_SCAN_DIR);
lcd->lcd_info.framebuffer = rt_malloc_align(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8), 64);
RT_ASSERT(lcd->lcd_info.framebuffer);
uint16_t *framebuffer = (uint16_t *)(lcd->lcd_info.framebuffer);
for(uint32_t i=0; i<(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8))/2; i++) {
framebuffer[i] = BLACK;
}
/*display on*/
drv_lcd_cmd(lcd, DISPALY_ON);
/* set to black */
drv_lcd_clear(lcd, BLACK);
return ret;
}
static rt_err_t drv_lcd_open(rt_device_t dev, rt_uint16_t oflag)
{
/* Not need */
return RT_EOK;
}
static rt_err_t drv_lcd_close(rt_device_t dev)
{
/* Not need */
return RT_EOK;
}
static rt_size_t drv_lcd_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
/* Not need */
return 0;
}
static rt_size_t drv_lcd_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
/* Not need */
return 0;
}
static rt_err_t drv_lcd_control(rt_device_t dev, int cmd, void *args)
{
rt_err_t ret = RT_EOK;
lcd_8080_device_t lcd = (lcd_8080_device_t)dev;
rt_base_t level;
struct rt_device_rect_info* rect_info = (struct rt_device_rect_info*)args;
RT_ASSERT(dev != RT_NULL);
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
if(!rect_info)
{
LOG_E("RTGRAPHIC_CTRL_RECT_UPDATE error args");
return -RT_ERROR;
}
drv_lcd_rect_update(lcd, rect_info->x, rect_info->y, rect_info->width, rect_info->height);
break;
#if BSP_LCD_BACKLIGHT_PIN >= 0
case RTGRAPHIC_CTRL_POWERON:
#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH);
#else
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#endif
break;
case RTGRAPHIC_CTRL_POWEROFF:
#if defined(BSP_LCD_BACKLIGHT_ACTIVE_LOW)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH);
#elif defined(BSP_LCD_BACKLIGHT_ACTIVE_HIGH)
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_LOW);
#else
gpiohs_set_pin(lcd->backlight_pin, GPIO_PV_HIGH);
#endif
break;
#endif /* BSP_LCD_BACKLIGHT_PIN >= 0 */
case RTGRAPHIC_CTRL_GET_INFO:
*(struct rt_device_graphic_info *)args = lcd->lcd_info;
break;
case RTGRAPHIC_CTRL_SET_MODE:
ret = -RT_ENOSYS;
break;
case RTGRAPHIC_CTRL_GET_EXT:
ret = -RT_ENOSYS;
break;
default:
LOG_E("drv_lcd_control cmd: %d", cmd);
break;
}
return ret;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops drv_lcd_ops =
{
drv_lcd_init,
drv_lcd_open,
drv_lcd_close,
drv_lcd_read,
drv_lcd_write,
drv_lcd_control
};
#endif
int rt_hw_lcd_init(void)
{
rt_err_t ret = RT_EOK;
lcd_8080_device_t lcd_dev = &_lcddev;
lcd_dev->cs = SPI_CHIP_SELECT_0;
lcd_dev->dc_pin = LCD_DC_PIN;
#if BSP_LCD_RST_PIN >= 0
lcd_dev->rst_pin = LCD_RST_PIN;
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
lcd_dev->backlight_pin = LCD_BACKLIGHT_PIN;
#endif
dmalock_sync_take(&lcd_dev->dma_channel, RT_WAITING_FOREVER);
lcd_dev->spi_channel = SPI_DEVICE_0;
lcd_dev->lcd_info.bits_per_pixel = 16;
lcd_dev->lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
lcd_dev->parent.type = RT_Device_Class_Graphic;
lcd_dev->parent.rx_indicate = RT_NULL;
lcd_dev->parent.tx_complete = RT_NULL;
#ifdef RT_USING_DEVICE_OPS
lcd_dev->parent.ops = &drv_lcd_ops;
#else
lcd_dev->parent.init = drv_lcd_init;
lcd_dev->parent.open = drv_lcd_open;
lcd_dev->parent.close = drv_lcd_close;
lcd_dev->parent.read = drv_lcd_read;
lcd_dev->parent.write = drv_lcd_write;
lcd_dev->parent.control = drv_lcd_control;
#endif
lcd_dev->parent.user_data = RT_NULL;
ret = rt_device_register(&lcd_dev->parent, "lcd", RT_DEVICE_FLAG_RDWR);
return ret;
}
INIT_DEVICE_EXPORT(rt_hw_lcd_init);
void lcd_set_direction(lcd_dir_t dir)
{
drv_lcd_set_direction(&_lcddev, dir);
}
#endif

90
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/drv_lcd.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-07 ZYH first version
*/
#ifndef DRV_LCD_H__
#define DRV_LCD_H__
#include <rtdevice.h>
#include <board.h>
#include <gpiohs.h>
#include <spi.h>
#include <drv_io_config.h>
#include <rthw.h>
#include "dmalock.h"
//POINT_COLOR
#define WHITE 0xFFFF
#define BLACK 0x0000
#define BLUE 0x001F
#define BRED 0XF81F
#define GRED 0XFFE0
#define GBLUE 0X07FF
#define RED 0xF800
#define MAGENTA 0xF81F
#define GREEN 0x07E0
#define CYAN 0x7FFF
#define YELLOW 0xFFE0
#define BROWN 0XBC40
#define BRRED 0XFC07
#define GRAY 0X8430
#define GRAY175 0XAD75
#define GRAY151 0X94B2
#define GRAY187 0XBDD7
#define GRAY240 0XF79E
typedef enum _lcd_dir
{
DIR_XY_RLUD = 0x00,
DIR_YX_RLUD = 0x20,
DIR_XY_LRUD = 0x40,
DIR_YX_LRUD = 0x60,
DIR_XY_RLDU = 0x80,
DIR_YX_RLDU = 0xA0,
DIR_XY_LRDU = 0xC0,
DIR_YX_LRDU = 0xE0,
DIR_XY_MASK = 0x20,
DIR_MASK = 0xE0,
} lcd_dir_t;
typedef struct lcd_8080_device
{
struct rt_device parent;
struct rt_device_graphic_info lcd_info;
int spi_channel;
int cs;
int dc_pin;
#if BSP_LCD_RST_PIN >= 0
int rst_pin;
#endif
#if BSP_LCD_BACKLIGHT_PIN >= 0
int backlight_pin;
#endif
int dma_channel;
} * lcd_8080_device_t;
int rt_hw_lcd_init(void);
void drv_lcd_set_area(lcd_8080_device_t lcd, rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2);
void drv_lcd_data_word(lcd_8080_device_t lcd, rt_uint32_t *data_buf, rt_uint32_t length);
void drv_lcd_data_half_word(lcd_8080_device_t lcd, rt_uint16_t *data_buf, rt_uint32_t length);
/* for mpy machine.lcd */
void lcd_display_on(void);
void lcd_display_off(void);
void lcd_clear(int color);
void lcd_draw_point_color(int x, int y, int color);
void lcd_show_string(int x, int y, int size, const char *data);
void lcd_draw_line(int x1, int y1, int x2, int y2);
void lcd_draw_rectangle(int x1, int y1, int x2, int y2);
void lcd_draw_circle(int x1, int y1, int r);
void lcd_set_color(int back, int fore);
void lcd_show_image(int x, int y, int length, int wide, const unsigned char *buf);
void lcd_set_direction(lcd_dir_t dir);
#endif

1297
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/drv_mpylcd.c Normal file
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File diff suppressed because it is too large Load Diff

27
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/drv_mpymachine.c Normal file
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#include <sysctl.h>
int mp_port_get_freq(int clkid, int *freq)
{
int ret = 0;
uint32_t value;
switch (clkid)
{
case 0:
value = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU);
break;
case 1:
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL1);
break;
case 2:
value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL2);
break;
default:
ret = -1;
break;
}
*freq = (int)value;
return ret;
}

301
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/drv_spi.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-18 ZYH first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#ifdef RT_USING_SPI
#include "drv_spi.h"
#include <drv_io_config.h>
#include <spi.h>
#include "dmalock.h"
#include <sysctl.h>
#include <gpiohs.h>
#include <string.h>
#include "utils.h"
#define DRV_SPI_DEVICE(spi_bus) (struct drv_spi_bus *)(spi_bus)
#define MAX_CLOCK (40000000UL)
struct drv_spi_bus
{
struct rt_spi_bus parent;
spi_device_num_t spi_instance;
dmac_channel_number_t dma_send_channel;
dmac_channel_number_t dma_recv_channel;
struct rt_completion dma_completion;
};
struct drv_cs
{
int cs_index;
int cs_pin;
};
static volatile spi_t *const spi_instance[4] =
{
(volatile spi_t *)SPI0_BASE_ADDR,
(volatile spi_t *)SPI1_BASE_ADDR,
(volatile spi_t *)SPI_SLAVE_BASE_ADDR,
(volatile spi_t *)SPI3_BASE_ADDR
};
static rt_err_t drv_spi_configure(struct rt_spi_device *device,
struct rt_spi_configuration *configuration)
{
rt_err_t ret = RT_EOK;
int freq = 0;
struct drv_spi_bus *bus = DRV_SPI_DEVICE(device->bus);
struct drv_cs * cs = (struct drv_cs *)device->parent.user_data;
RT_ASSERT(bus != RT_NULL);
gpiohs_set_drive_mode(cs->cs_pin, GPIO_DM_OUTPUT);
gpiohs_set_pin(cs->cs_pin, GPIO_PV_HIGH);
#ifdef BSP_USING_SPI1_AS_QSPI
/* Todo:QSPI*/
#else
spi_init(bus->spi_instance, configuration->mode & RT_SPI_MODE_3, SPI_FF_STANDARD, configuration->data_width, 0);
#endif
freq = spi_set_clk_rate(bus->spi_instance, configuration->max_hz > MAX_CLOCK ? MAX_CLOCK : configuration->max_hz);
rt_kprintf("set spi freq %d\n", freq);
return ret;
}
void __spi_set_tmod(uint8_t spi_num, uint32_t tmod)
{
RT_ASSERT(spi_num < SPI_DEVICE_MAX);
volatile spi_t *spi_handle = spi[spi_num];
uint8_t tmod_offset = 0;
switch(spi_num)
{
case 0:
case 1:
case 2:
tmod_offset = 8;
break;
case 3:
default:
tmod_offset = 10;
break;
}
set_bit(&spi_handle->ctrlr0, 3 << tmod_offset, tmod << tmod_offset);
}
int dma_irq_callback(void *ctx)
{
struct rt_completion * cmp = ctx;
if(cmp)
{
rt_completion_done(cmp);
}
}
static rt_uint32_t drv_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
struct drv_spi_bus *bus = DRV_SPI_DEVICE(device->bus);
struct drv_cs * cs = (struct drv_cs *)device->parent.user_data;
struct rt_spi_configuration *cfg = &device->config;
uint32_t * tx_buff = RT_NULL;
uint32_t * rx_buff = RT_NULL;
int i;
rt_ubase_t dummy = 0xFFFFFFFFU;
if(cfg->data_width != 8)
{
return 0;
}
RT_ASSERT(bus != RT_NULL);
if(message->cs_take)
{
gpiohs_set_pin(cs->cs_pin, GPIO_PV_LOW);
}
if(message->length)
{
bus->dma_send_channel = DMAC_CHANNEL_MAX;
bus->dma_recv_channel = DMAC_CHANNEL_MAX;
rt_completion_init(&bus->dma_completion);
if(message->recv_buf)
{
dmalock_sync_take(&bus->dma_recv_channel, RT_WAITING_FOREVER);
sysctl_dma_select(bus->dma_recv_channel, SYSCTL_DMA_SELECT_SSI0_RX_REQ + bus->spi_instance * 2);
rx_buff = rt_calloc(message->length * 4, 1);
if(!rx_buff)
{
goto transfer_done;
}
}
if(message->send_buf)
{
dmalock_sync_take(&bus->dma_send_channel, RT_WAITING_FOREVER);
sysctl_dma_select(bus->dma_send_channel, SYSCTL_DMA_SELECT_SSI0_TX_REQ + bus->spi_instance * 2);
tx_buff = rt_malloc(message->length * 4);
if(!tx_buff)
{
goto transfer_done;
}
for(i = 0; i < message->length; i++)
{
tx_buff[i] = ((uint8_t *)message->send_buf)[i];
}
}
if(message->send_buf && message->recv_buf)
{
dmac_irq_register(bus->dma_recv_channel, dma_irq_callback, &bus->dma_completion, 1);
__spi_set_tmod(bus->spi_instance, SPI_TMOD_TRANS_RECV);
spi_instance[bus->spi_instance]->dmacr = 0x3;
spi_instance[bus->spi_instance]->ssienr = 0x01;
dmac_set_single_mode(bus->dma_recv_channel, (void *)(&spi_instance[bus->spi_instance]->dr[0]), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, message->length);
dmac_set_single_mode(bus->dma_send_channel, tx_buff, (void *)(&spi_instance[bus->spi_instance]->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, message->length);
}
else if(message->send_buf)
{
dmac_irq_register(bus->dma_send_channel, dma_irq_callback, &bus->dma_completion, 1);
__spi_set_tmod(bus->spi_instance, SPI_TMOD_TRANS);
spi_instance[bus->spi_instance]->dmacr = 0x2;
spi_instance[bus->spi_instance]->ssienr = 0x01;
dmac_set_single_mode(bus->dma_send_channel, tx_buff, (void *)(&spi_instance[bus->spi_instance]->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, message->length);
}
else if(message->recv_buf)
{
dmac_irq_register(bus->dma_recv_channel, dma_irq_callback, &bus->dma_completion, 1);
__spi_set_tmod(bus->spi_instance, SPI_TMOD_RECV);
spi_instance[bus->spi_instance]->ctrlr1 = message->length - 1;
spi_instance[bus->spi_instance]->dmacr = 0x1;
spi_instance[bus->spi_instance]->ssienr = 0x01;
spi_instance[bus->spi_instance]->dr[0] = 0xFF;
dmac_set_single_mode(bus->dma_recv_channel, (void *)(&spi_instance[bus->spi_instance]->dr[0]), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, message->length);
}
else
{
goto transfer_done;
}
spi_instance[bus->spi_instance]->ser = 1U << cs->cs_index;
rt_completion_wait(&bus->dma_completion, RT_WAITING_FOREVER);
if(message->recv_buf)
dmac_irq_unregister(bus->dma_recv_channel);
else
dmac_irq_unregister(bus->dma_send_channel);
// wait until all data has been transmitted
while ((spi_instance[bus->spi_instance]->sr & 0x05) != 0x04)
;
spi_instance[bus->spi_instance]->ser = 0x00;
spi_instance[bus->spi_instance]->ssienr = 0x00;
if(message->recv_buf)
{
for(i = 0; i < message->length; i++)
{
((uint8_t *)message->recv_buf)[i] = (uint8_t)rx_buff[i];
}
}
transfer_done:
dmalock_release(bus->dma_send_channel);
dmalock_release(bus->dma_recv_channel);
if(tx_buff)
{
rt_free(tx_buff);
}
if(rx_buff)
{
rt_free(rx_buff);
}
}
if(message->cs_release)
{
gpiohs_set_pin(cs->cs_pin, GPIO_PV_HIGH);
}
return message->length;
}
const static struct rt_spi_ops drv_spi_ops =
{
drv_spi_configure,
drv_spi_xfer
};
int rt_hw_spi_init(void)
{
rt_err_t ret = RT_EOK;
#ifdef BSP_USING_SPI1
{
static struct drv_spi_bus spi_bus1;
spi_bus1.spi_instance = SPI_DEVICE_1;
ret = rt_spi_bus_register(&spi_bus1.parent, "spi1", &drv_spi_ops);
#ifdef BSP_SPI1_USING_SS0
{
static struct rt_spi_device spi_device10;
static struct drv_cs cs10 =
{
.cs_index = SPI_CHIP_SELECT_0,
.cs_pin = SPI1_CS0_PIN
};
rt_spi_bus_attach_device(&spi_device10, "spi10", "spi1", (void *)&cs10);
}
#endif
#ifdef BSP_SPI1_USING_SS1
{
static struct rt_spi_device spi_device11;
static struct drv_cs cs11 =
{
.cs_index = SPI_CHIP_SELECT_1,
.cs_pin = SPI1_CS1_PIN
};
rt_spi_bus_attach_device(&spi_device11, "spi11", "spi1", (void *)&cs11);
}
#endif
#ifdef BSP_SPI1_USING_SS2
{
static struct rt_spi_device spi_device12;
static struct drv_cs cs12 =
{
.cs_index = SPI_CHIP_SELECT_2,
.cs_pin = SPI1_CS2_PIN
};
rt_spi_bus_attach_device(&spi_device12, "spi12", "spi1", (void *)&cs12);
}
#endif
#ifdef BSP_SPI1_USING_SS3
{
static struct rt_spi_device spi_device13;
static struct drv_cs cs13 =
{
.cs_index = SPI_CHIP_SELECT_2,
.cs_pin = SPI1_CS2_PIN
};
rt_spi_bus_attach_device(&spi_device13, "spi13", "spi1", (void *)&cs13);
}
#endif
}
#endif
return ret;
}
INIT_DEVICE_EXPORT(rt_hw_spi_init);
#endif

16
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/drv_spi.h Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-18 ZYH first version
*/
#ifndef DRV_SPI_H__
#define DRV_SPI_H__
int rt_hw_spi_init(void);
#endif

11
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/heap.c Normal file
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@@ -0,0 +1,11 @@
#include <rtthread.h>
#include <stdlib.h>
size_t get_free_heap_size(void)
{
rt_uint32_t total, used, max;
rt_memory_info(&total, &used, &max);
return total - used;
}

96
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/rw007_port.c Normal file
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@@ -0,0 +1,96 @@
#include <rtthread.h>
/*
RW007(SPI1 ) Kendryte Sipeed MAX bit io
pin numbers function pin number on rw007 board
io 15 SPI1_SCK SCK
io 8 SPI1_MISO MISO
io 10 SPI1_MOSI MOSI
io 9 CS/BOOT1 CS
io 6 INT/BUSY D9
io 7 RESET D8
set in mencuconfig after suring hardware well
board driver config-> enble spi1
(15) spi1 clk pin number
(10) spi1 d0 pin number
(8) spi1 d1 pin number
(*) spi1 enble ss1 --->
(9) spi1 ss1 pin number
verified
*/
#ifdef PKG_USING_RW007
#include <rtdevice.h>
#include <drv_spi.h>
#include <board.h>
#include <spi_wifi_rw007.h>
extern void spi_wifi_isr(int vector);
static int rw007_gpio_init(void)
{
int cnt = 15;
/* Configure IO */
rt_pin_mode(RW007_RST_PIN, PIN_MODE_OUTPUT);
rt_pin_mode(RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLDOWN);
/* Reset rw007 and config mode */
rt_pin_write(RW007_RST_PIN, PIN_LOW);
rt_thread_mdelay(100);
rt_pin_write(RW007_RST_PIN, PIN_HIGH);
/* Wait rw007 ready(exit busy stat) */
while(!rt_pin_read(RW007_INT_BUSY_PIN))
{
rt_thread_mdelay(100);
if (--cnt < 0)
return -1;
}
rt_thread_mdelay(200);
rt_pin_mode(RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLUP);
return 0;
}
int wifi_spi_device_init(void)
{
char sn_version[32] = {0};
if (rw007_gpio_init() != 0)
{
rt_kprintf("rw007 wait busy timeout\n");
return -1;
}
rt_hw_wifi_init(RW007_SPIDEV_NAME);
rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION);
rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP);
rw007_sn_get(sn_version);
rt_kprintf("\nrw007 sn: [%s]\n", sn_version);
rw007_version_get(sn_version);
rt_kprintf("rw007 ver: [%s]\n\n", sn_version);
return 0;
}
INIT_APP_EXPORT(wifi_spi_device_init);
static void int_wifi_irq(void * p)
{
((void)p);
spi_wifi_isr(0);
}
void spi_wifi_hw_init(void)
{
rt_pin_attach_irq(RW007_INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0);
rt_pin_irq_enable(RW007_INT_BUSY_PIN, RT_TRUE);
}
#endif /* RW007_USING_STM32_DRIVERS */

42
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/base-drivers/sdcard_port.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rtthread.h>
#ifdef BSP_USING_SDCARD
#if defined(RT_USING_SPI_MSD) && defined(RT_USING_DFS_ELMFAT)
#include <spi_msd.h>
#include <dfs_fs.h>
#define DBG_TAG "sdcard"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
int sd_mount(void)
{
int ret = 0;
ret = msd_init("sd0", "spi10");
if(RT_EOK == ret)
{
if(dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{
LOG_I("Mount /sd0 successfully");
return RT_EOK;
}
else
{
LOG_E("Mount fail !!1");
return -1;
}
}
LOG_E("msd_init fail !!!");
return -2;
}
INIT_ENV_EXPORT(sd_mount);
#endif
#endif

7
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/kendryte-sdk/Kconfig Normal file
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@@ -0,0 +1,7 @@
menu "Kendryte SDK Config"
config PKG_KENDRYTE_SDK_VERNUM
hex "Kendryte SDK Version"
default 0x0055
endmenu

37
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/kendryte-sdk/SConscript Normal file
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@@ -0,0 +1,37 @@
from building import *
cwd = GetCurrentDir()
src = Split('''
kendryte-sdk-source/lib/bsp/entry.c
kendryte-sdk-source/lib/bsp/entry_user.c
kendryte-sdk-source/lib/drivers/aes.c
kendryte-sdk-source/lib/drivers/clint.c
kendryte-sdk-source/lib/drivers/dmac.c
kendryte-sdk-source/lib/drivers/dvp.c
kendryte-sdk-source/lib/drivers/fft.c
kendryte-sdk-source/lib/drivers/fpioa.c
kendryte-sdk-source/lib/drivers/gpio.c
kendryte-sdk-source/lib/drivers/gpiohs.c
kendryte-sdk-source/lib/drivers/i2c.c
kendryte-sdk-source/lib/drivers/i2s.c
kendryte-sdk-source/lib/drivers/kpu.c
kendryte-sdk-source/lib/drivers/plic.c
kendryte-sdk-source/lib/drivers/pwm.c
kendryte-sdk-source/lib/drivers/rtc.c
kendryte-sdk-source/lib/drivers/sha256.c
kendryte-sdk-source/lib/drivers/spi.c
kendryte-sdk-source/lib/drivers/sysctl.c
kendryte-sdk-source/lib/drivers/timer.c
kendryte-sdk-source/lib/drivers/uart.c
kendryte-sdk-source/lib/drivers/uarths.c
kendryte-sdk-source/lib/drivers/utils.c
kendryte-sdk-source/lib/drivers/wdt.c
''')
CPPPATH = [cwd + '/kendryte-sdk-source/lib/drivers/include',
cwd + '/kendryte-sdk-source/lib/bsp/include',
cwd + '/kendryte-sdk-source/lib/utils/include']
CPPDEFINES = ['CONFIG_LOG_COLORS', 'CONFIG_LOG_ENABLE', 'CONFIG_LOG_LEVEL=LOG_VERBOSE', 'FPGA_PLL', 'LOG_KERNEL', '__riscv64']
group = DefineGroup('SDK', src, depend = [''], CPPPATH = CPPPATH, LOCAL_CPPDEFINES = CPPDEFINES)
Return('group')

1
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/kendryte-sdk/kendryte-sdk-source Submodule

Submodule Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/kendryte-sdk/kendryte-sdk-source added at 77d9df93ba

170
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/link.lds Normal file
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@@ -0,0 +1,170 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
INCLUDE "link_stacksize.lds"
/*
* The OUTPUT_ARCH command specifies the machine architecture where the
* argument is one of the names used in the Kendryte library.
*/
OUTPUT_ARCH( "riscv" )
MEMORY
{
/* 6M SRAM */
SRAM : ORIGIN = 0x80000000, LENGTH = 0x600000
}
ENTRY(_start)
SECTIONS
{
. = 0x80000000 ;
/* __STACKSIZE__ = 4096; */
.start :
{
*(.start);
} > SRAM
. = ALIGN(8);
.text :
{
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(8);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(8);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(8);
/* section information for initial. */
. = ALIGN(8);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(8);
PROVIDE(__ctors_start__ = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
. = ALIGN(8);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
. = ALIGN(8);
_etext = .;
} > SRAM
.eh_frame_hdr :
{
*(.eh_frame_hdr)
*(.eh_frame_entry)
} > SRAM
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
. = ALIGN(8);
.data :
{
*(.data)
*(.data.*)
*(.data1)
*(.data1.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata)
*(.sdata.*)
} > SRAM
/* stack for dual core */
.stack :
{
. = ALIGN(64);
__stack_start__ = .;
. += __STACKSIZE__;
__stack_cpu0 = .;
. += __STACKSIZE__;
__stack_cpu1 = .;
} > SRAM
.sbss :
{
__bss_start = .;
*(.sbss)
*(.sbss.*)
*(.dynsbss)
*(.scommon)
} > SRAM
.bss :
{
*(.bss)
*(.bss.*)
*(.dynbss)
*(COMMON)
__bss_end = .;
} > SRAM
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

1
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/link_stacksize.lds Normal file
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@@ -0,0 +1 @@
__STACKSIZE__ = 4096;

363
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/rtconfig.h Normal file
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@@ -0,0 +1,363 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* XIUOS Rt-thread Configuration */
#define ROOT_DIR "../../../.."
#define BSP_DIR "."
#define RT_Thread_DIR "../.."
#define RTT_DIR "../../rt-thread"
#define BOARD_K210_EVB
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_DEBUG
#define RT_DEBUG_COLOR
#define RT_DEBUG_INIT_CONFIG
#define RT_DEBUG_INIT 1
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_SIGNALS
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_MEMHEAP
#define RT_USING_SLAB
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uarths"
#define RT_VER_NUM 0x40004
#define ARCH_CPU_64BIT
#define ARCH_RISCV
#define ARCH_RISCV_FPU
#define ARCH_RISCV_FPU_S
#define ARCH_RISCV64
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
#define RT_USING_CPLUSPLUS
/* Command shell */
#define RT_USING_FINSH
#define RT_USING_MSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 16384
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 16
#define DFS_FILESYSTEM_TYPES_MAX 16
#define DFS_FD_MAX 64
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_RTC
#define RT_USING_SPI
#define RT_USING_SPI_MSD
#define RT_USING_SFUD
#define RT_SFUD_USING_SFDP
#define RT_SFUD_USING_FLASH_INFO_TABLE
#define RT_SFUD_SPI_MAX_HZ 50000000
#define RT_DEBUG_SFUD
#define RT_USING_WIFI
#define RT_WLAN_DEVICE_STA_NAME "wlan0"
#define RT_WLAN_DEVICE_AP_NAME "wlan1"
#define RT_WLAN_SSID_MAX_LENGTH 32
#define RT_WLAN_PASSWORD_MAX_LENGTH 32
#define RT_WLAN_DEV_EVENT_NUM 2
#define RT_WLAN_MANAGE_ENABLE
#define RT_WLAN_SCAN_WAIT_MS 10000
#define RT_WLAN_CONNECT_WAIT_MS 10000
#define RT_WLAN_SCAN_SORT
#define RT_WLAN_MSH_CMD_ENABLE
#define RT_WLAN_AUTO_CONNECT_ENABLE
#define AUTO_CONNECTION_PERIOD_MS 2000
#define RT_WLAN_CFG_ENABLE
#define RT_WLAN_CFG_INFO_MAX 3
#define RT_WLAN_PROT_ENABLE
#define RT_WLAN_PROT_NAME_LEN 8
#define RT_WLAN_PROT_MAX 2
#define RT_WLAN_DEFAULT_PROT "lwip"
#define RT_WLAN_PROT_LWIP_ENABLE
#define RT_WLAN_PROT_LWIP_NAME "lwip"
#define RT_WLAN_WORK_THREAD_ENABLE
#define RT_WLAN_WORKQUEUE_THREAD_NAME "wlan"
#define RT_WLAN_WORKQUEUE_THREAD_SIZE 2048
#define RT_WLAN_WORKQUEUE_THREAD_PRIO 15
/* Using USB */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_USING_PTHREADS
#define PTHREAD_NUM_MAX 8
#define RT_USING_POSIX
#define RT_LIBC_USING_TIME
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* Network */
/* Socket abstraction layer */
#define RT_USING_SAL
/* protocol stack implement */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
/* Network interface device */
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
/* light weight TCP/IP stack */
#define RT_USING_LWIP
#define RT_USING_LWIP202
#define RT_LWIP_MEM_ALIGNMENT 8
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
#define RT_LWIP_DHCP
#define IP_SOF_BROADCAST 1
#define IP_SOF_BROADCAST_RECV 1
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.1.30"
#define RT_LWIP_GWADDR "192.168.1.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 16
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 10
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 10240
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 10240
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread Utestcases */
/* Board Drivers Config */
#define BSP_USING_UART_HS
/* General Purpose UARTs */
#define BSP_USING_UART1
#define BSP_UART1_TXD_PIN 20
#define BSP_UART1_RXD_PIN 21
#define BSP_UART1_RTS_PIN -1
#define BSP_UART1_CTS_PIN -1
#define BSP_USING_SPI1
#define BSP_SPI1_CLK_PIN 27
#define BSP_SPI1_D0_PIN 28
#define BSP_SPI1_D1_PIN 26
#define BSP_SPI1_USING_SS0
#define BSP_SPI1_SS0_PIN 29
#define BSP_SPI1_USING_SS1
#define BSP_SPI1_SS1_PIN 8
#define BSP_USING_LCD
#define BSP_LCD_CS_PIN 36
#define BSP_LCD_WR_PIN 39
#define BSP_LCD_DC_PIN 38
#define BSP_LCD_RST_PIN 37
#define BSP_LCD_BACKLIGHT_PIN -1
#define BSP_LCD_BACKLIGHT_ACTIVE_LOW
#define BSP_LCD_CLK_FREQ 20000000
#define BSP_BOARD_USER
#define BSP_LCD_X_MAX 240
#define BSP_LCD_Y_MAX 320
#define BSP_USING_SDCARD
#define BSP_USING_DVP
/* The default pin assignment is based on the Maix Duino K210 development board */
#define BSP_DVP_SCCB_SDA_PIN 40
#define BSP_DVP_SCCB_SCLK_PIN 41
#define BSP_DVP_CMOS_RST_PIN 42
#define BSP_DVP_CMOS_VSYNC_PIN 43
#define BSP_DVP_CMOS_PWDN_PIN 44
#define BSP_DVP_CMOS_XCLK_PIN 46
#define BSP_DVP_CMOS_PCLK_PIN 47
#define BSP_DVP_CMOS_HREF_PIN 45
/* Kendryte SDK Config */
#define PKG_KENDRYTE_SDK_VERNUM 0x0055
/* MicroPython */
/* More Drivers */
#define DRV_USING_OV2640
#define OV2640_JPEG_MODE
#define OV2640_X_RESOLUTION_IMAGE_OUTSIZE 240
#define OV2640_Y_RESOLUTION_IMAGE_OUTSIZE 240
#define OV2640_X_IMAGE_WINDOWS_SIZE 400
/* the value must be greater than OV2640_X_RESOLUTION_IMAGE_OUTSIZE */
#define OV2640_Y_IMAGE_WINDOWS_SIZE 400
/* the value must be greater than OV2640_Y_RESOLUTION_IMAGE_OUTSIZE */
/* APP_Framework */
/* Framework */
#define TRANSFORM_LAYER_ATTRIUBUTE
#define ADD_XIZI_FETURES
#define SUPPORT_KNOWING_FRAMEWORK
#define USING_KPU_PROCESSING
#define USING_YOLOV2
#define USING_YOLOV2_JSONPARSER
#define USING_K210_YOLOV2_DETECT
/* Security */
/* Applications */
/* config stack size and priority of main task */
#define MAIN_KTASK_STACK_SIZE 1024
/* ota app */
/* test app */
/* connection app */
/* control app */
/* knowing app */
#define APPLICATION_KNOWING
#define K210_DETECT_ENTRY
/* sensor app */
#define APPLICATION_SENSOR
/* lib */
#define APP_SELECT_NEWLIB
#define LIB_USING_CJSON
#define __STACKSIZE__ 4096
#endif

49
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210/rtconfig.py Normal file
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@@ -0,0 +1,49 @@
import os
# toolchains options
ARCH ='risc-v'
CPU ='k210'
CROSS_TOOL ='gcc'
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'/opt/xpack-riscv-none-gcc/bin'
else:
print('Please make sure your toolchains is GNU GCC!')
exit(0)
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
PREFIX = 'riscv-none-embed-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcmodel=medany -march=rv64imafc -mabi=lp64f -fsingle-precision-constant'
CFLAGS = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -ggdb'
AFLAGS += ' -ggdb'
else:
CFLAGS += ' -O2 -Os'
CXXFLAGS = CFLAGS
# we use c++ 11, but -std=c++11 don't have 'struct siginfo', need gnu++11
CXXFLAGS += ' -std=gnu++11'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

581
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core/.config Normal file
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@@ -0,0 +1,581 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
CONFIG_ROOT_DIR="../../../.."
CONFIG_BSP_DIR="."
CONFIG_RT_Thread_DIR="../.."
CONFIG_RTT_DIR="../../rt-thread"
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_BIG_ENDIAN is not set
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_ASM_MEMCPY is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_SMALL_MEM is not set
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_VER_NUM=0x40004
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M4=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_RT_USING_MSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
CONFIG_RT_USING_DFS_ROMFS=y
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_NFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
CONFIG_RT_USING_I2C=y
# CONFIG_RT_I2C_DEBUG is not set
CONFIG_RT_USING_I2C_BITOPS=y
# CONFIG_RT_I2C_BITOPS_DEBUG is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_QSPI is not set
CONFIG_RT_USING_SPI_MSD=y
CONFIG_RT_USING_SFUD=y
CONFIG_RT_SFUD_USING_SFDP=y
CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
# CONFIG_RT_SFUD_USING_QSPI is not set
CONFIG_RT_SFUD_SPI_MAX_HZ=50000000
# CONFIG_RT_DEBUG_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
CONFIG_RT_USING_WIFI=y
CONFIG_RT_WLAN_DEVICE_STA_NAME="wlan0"
CONFIG_RT_WLAN_DEVICE_AP_NAME="wlan1"
CONFIG_RT_WLAN_SSID_MAX_LENGTH=32
CONFIG_RT_WLAN_PASSWORD_MAX_LENGTH=32
CONFIG_RT_WLAN_DEV_EVENT_NUM=2
CONFIG_RT_WLAN_MANAGE_ENABLE=y
CONFIG_RT_WLAN_SCAN_WAIT_MS=10000
CONFIG_RT_WLAN_CONNECT_WAIT_MS=10000
CONFIG_RT_WLAN_SCAN_SORT=y
CONFIG_RT_WLAN_MSH_CMD_ENABLE=y
CONFIG_RT_WLAN_AUTO_CONNECT_ENABLE=y
CONFIG_AUTO_CONNECTION_PERIOD_MS=2000
CONFIG_RT_WLAN_CFG_ENABLE=y
CONFIG_RT_WLAN_CFG_INFO_MAX=3
CONFIG_RT_WLAN_PROT_ENABLE=y
CONFIG_RT_WLAN_PROT_NAME_LEN=8
CONFIG_RT_WLAN_PROT_MAX=2
CONFIG_RT_WLAN_DEFAULT_PROT="lwip"
CONFIG_RT_WLAN_PROT_LWIP_ENABLE=y
CONFIG_RT_WLAN_PROT_LWIP_NAME="lwip"
# CONFIG_RT_WLAN_PROT_LWIP_PBUF_FORCE is not set
CONFIG_RT_WLAN_WORK_THREAD_ENABLE=y
CONFIG_RT_WLAN_WORKQUEUE_THREAD_NAME="wlan"
CONFIG_RT_WLAN_WORKQUEUE_THREAD_SIZE=2048
CONFIG_RT_WLAN_WORKQUEUE_THREAD_PRIO=15
# CONFIG_RT_WLAN_DEBUG is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
CONFIG_RT_USING_PTHREADS=y
CONFIG_PTHREAD_NUM_MAX=8
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_GETLINE is not set
# CONFIG_RT_USING_POSIX_AIO is not set
CONFIG_RT_LIBC_USING_TIME=y
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# Network
#
#
# Socket abstraction layer
#
CONFIG_RT_USING_SAL=y
CONFIG_SAL_INTERNET_CHECK=y
#
# protocol stack implement
#
CONFIG_SAL_USING_LWIP=y
CONFIG_SAL_USING_POSIX=y
#
# Network interface device
#
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
#
# light weight TCP/IP stack
#
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
# CONFIG_RT_USING_LWIP202 is not set
CONFIG_RT_USING_LWIP203=y
# CONFIG_RT_USING_LWIP212 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=4
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
CONFIG_RT_LWIP_DHCP=y
CONFIG_IP_SOF_BROADCAST=1
CONFIG_IP_SOF_BROADCAST_RECV=1
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.1.30"
CONFIG_RT_LWIP_GWADDR="192.168.1.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=16
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
CONFIG_LWIP_SO_LINGER=0
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_RT_LWIP_DEBUG is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
# CONFIG_LWIP_USING_DHCPD is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_LWP is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_SERIES_STM32F4=y
#
# Hardware Drivers Config
#
CONFIG_SOC_STM32F407ZG=y
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_USB_TO_USART=y
# CONFIG_BSP_USING_COM2 is not set
# CONFIG_BSP_USING_COM3 is not set
CONFIG_BSP_USING_SRAM=y
# CONFIG_BSP_USING_MCU_LCD is not set
CONFIG_BSP_USING_SPI_FLASH=y
# CONFIG_BSP_USING_EEPROM is not set
CONFIG_BSP_USING_OV2640=y
# CONFIG_BSP_USING_ETH is not set
# CONFIG_BSP_USING_MPU6050 is not set
CONFIG_BSP_USING_SDCARD=y
CONFIG_SDCARD_SPI2_CS_PIN=28
CONFIG_SDCARD_SPI_BUS_NAME="spi2"
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_UART1_RX_USING_DMA is not set
# CONFIG_BSP_UART1_TX_USING_DMA is not set
CONFIG_BSP_USING_UART2=y
# CONFIG_BSP_UART2_RX_USING_DMA is not set
# CONFIG_BSP_UART2_TX_USING_DMA is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_UART5 is not set
# CONFIG_BSP_USING_UART6 is not set
# CONFIG_BSP_USING_TIM is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
CONFIG_BSP_USING_SPI=y
CONFIG_BSP_USING_SPI1=y
# CONFIG_BSP_SPI1_TX_USING_DMA is not set
# CONFIG_BSP_SPI1_RX_USING_DMA is not set
CONFIG_BSP_USING_SPI2=y
# CONFIG_BSP_SPI2_TX_USING_DMA is not set
# CONFIG_BSP_SPI2_RX_USING_DMA is not set
# CONFIG_BSP_USING_ADC is not set
CONFIG_BSP_USING_I2C1=y
CONFIG_BSP_I2C1_SCL_PIN=55
CONFIG_BSP_I2C1_SDA_PIN=54
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_SDIO is not set
CONFIG_BSP_USING_DCMI=y
# CONFIG_BSP_USING_USBD is not set
# CONFIG_BSP_USING_USBH is not set
# CONFIG_BSP_USING_PULSE_ENCODER is not set
CONFIG_BSP_USING_EXT_FMC_IO=y
CONFIG_BSP_USING_FMC=y
# CONFIG_BSP_USING_RNG is not set
# CONFIG_BSP_USING_UDID is not set
#
# Board extended module Drivers
#
#
# MicroPython
#
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# More Drivers
#
CONFIG_PKG_USING_RW007=y
# CONFIG_RW007_NOT_USE_EXAMPLE_DRIVERS is not set
CONFIG_RW007_USING_STM32_DRIVERS=y
CONFIG_RW007_SPI_MAX_HZ=30000000
CONFIG_RW007_SPI_BUS_NAME="spi1"
CONFIG_RW007_CS_PIN=86
CONFIG_RW007_BOOT0_PIN=19
CONFIG_RW007_BOOT1_PIN=86
CONFIG_RW007_INT_BUSY_PIN=87
CONFIG_RW007_RST_PIN=88
CONFIG_DRV_USING_OV2640=y
CONFIG_OV2640_JPEG_MODE=y
# CONFIG_OV2640_RGB565_MODE is not set
CONFIG_OV2640_X_RESOLUTION_IMAGE_OUTSIZE=240
CONFIG_OV2640_Y_RESOLUTION_IMAGE_OUTSIZE=240
CONFIG_OV2640_X_IMAGE_WINDOWS_SIZE=400
#
# the value must be greater than OV2640_X_RESOLUTION_IMAGE_OUTSIZE
#
CONFIG_OV2640_Y_IMAGE_WINDOWS_SIZE=400
#
# the value must be greater than OV2640_Y_RESOLUTION_IMAGE_OUTSIZE
#
#
# APP_Framework
#
#
# Framework
#
CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y
CONFIG_ADD_XIZI_FETURES=y
# CONFIG_ADD_NUTTX_FETURES is not set
# CONFIG_ADD_RTTHREAD_FETURES is not set
CONFIG_SUPPORT_SENSOR_FRAMEWORK=y
# CONFIG_SENSOR_HCHO is not set
# CONFIG_SENSOR_TVOC is not set
# CONFIG_SENSOR_IAQ is not set
# CONFIG_SENSOR_CH4 is not set
# CONFIG_SENSOR_CO2 is not set
# CONFIG_SENSOR_PM is not set
CONFIG_SENSOR_VOICE=y
CONFIG_SENSOR_D124=y
CONFIG_SENSOR_DEVICE_D124="d124_1"
CONFIG_SENSOR_QUANTITY_D124_VOICE="voice_1"
# CONFIG_SENSOR_D124_DRIVER_EXTUART is not set
CONFIG_SENSOR_DEVICE_D124_DEV="/dev/uart2"
# CONFIG_SENSOR_TEMPERATURE is not set
# CONFIG_SENSOR_HUMIDITY is not set
# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set
CONFIG_SUPPORT_KNOWING_FRAMEWORK=y
# CONFIG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_USING_KNOWING_FILTER is not set
# CONFIG_USING_OTA_MODEL is not set
# CONFIG_USING_IMAGE_PROCESSING is not set
# CONFIG_USING_CMSIS_5 is not set
CONFIG_USING_KPU_PROCESSING=y
# CONFIG_USING_YOLOV2 is not set
# CONFIG_USING_YOLOV2_JSONPARSER is not set
# CONFIG_USING_K210_YOLOV2_DETECT is not set
# CONFIG_USING_NNOM is not set
# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set
#
# Security
#
# CONFIG_CRYPTO is not set
#
# Applications
#
#
# config stack size and priority of main task
#
CONFIG_MAIN_KTASK_STACK_SIZE=1024
#
# ota app
#
# CONFIG_APPLICATION_OTA is not set
#
# test app
#
# CONFIG_USER_TEST is not set
#
# connection app
#
# CONFIG_APPLICATION_CONNECTION is not set
#
# control app
#
#
# knowing app
#
# CONFIG_APPLICATION_KNOWING is not set
#
# sensor app
#
CONFIG_APPLICATION_SENSOR=y
# CONFIG_APPLICATION_SENSOR_HCHO is not set
# CONFIG_APPLICATION_SENSOR_TVOC is not set
# CONFIG_APPLICATION_SENSOR_IAQ is not set
# CONFIG_APPLICATION_SENSOR_CH4 is not set
# CONFIG_APPLICATION_SENSOR_CO2 is not set
# CONFIG_APPLICATION_SENSOR_PM1_0 is not set
# CONFIG_APPLICATION_SENSOR_PM2_5 is not set
# CONFIG_APPLICATION_SENSOR_PM10 is not set
CONFIG_APPLICATION_SENSOR_VOICE=y
CONFIG_APPLICATION_SENSOR_VOICE_D124=y
# CONFIG_APPLICATION_SENSOR_TEMPERATURE is not set
# CONFIG_APPLICATION_SENSOR_HUMIDITY is not set
# CONFIG_USING_EMBEDDED_DATABASE_APP is not set
#
# lib
#
CONFIG_APP_SELECT_NEWLIB=y
# CONFIG_APP_SELECT_OTHER_LIB is not set
# CONFIG_LIB_USING_CJSON is not set
# CONFIG_LIB_USING_QUEUE is not set
# CONFIG_LIB_LV is not set
# CONFIG_USING_EMBEDDED_DATABASE is not set

243
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core/.gitignore vendored Normal file
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@@ -0,0 +1,243 @@
# this
*.map
*.dblite
*.bin
*.axf
*.old
*~
*.o
*.bak
*.dep
*.i
*.d
*.uimg
GPATH
GRTAGS
GTAGS
JLinkLog.txt
JLinkSettings.ini
DebugConfig/
RTE/
settings/
*.uvguix*
cconfig.h
# General
.DS_Store
.AppleDouble
.LSOverride
# Icon must end with two \r
Icon
# Thumbnails
._*
# Files that might appear in the root of a volume
.DocumentRevisions-V100
.fseventsd
.Spotlight-V100
.TemporaryItems
.Trashes
.VolumeIcon.icns
.com.apple.timemachine.donotpresent
# Directories potentially created on remote AFP share
.AppleDB
.AppleDesktop
Network Trash Folder
Temporary Items
.apdisk
# Byte-compiled / optimized / DLL files
__pycache__/
*.py[cod]
*$py.class
# C extensions
*.so
# Distribution / packaging
.Python
build/
develop-eggs/
dist/
downloads/
eggs/
.eggs/
lib/
lib64/
parts/
sdist/
var/
wheels/
share/python-wheels/
*.egg-info/
.installed.cfg
*.egg
MANIFEST
# PyInstaller
# Usually these files are written by a python script from a template
# before PyInstaller builds the exe, so as to inject date/other infos into it.
*.manifest
*.spec
# Installer logs
pip-log.txt
pip-delete-this-directory.txt
# Unit test / coverage reports
htmlcov/
.tox/
.nox/
.coverage
.coverage.*
.cache
nosetests.xml
coverage.xml
*.cover
*.py,cover
.hypothesis/
.pytest_cache/
cover/
# Translations
*.mo
*.pot
# Django stuff:
*.log
local_settings.py
db.sqlite3
db.sqlite3-journal
# Flask stuff:
instance/
.webassets-cache
# Scrapy stuff:
.scrapy
# Sphinx documentation
docs/_build/
# PyBuilder
.pybuilder/
target/
# Jupyter Notebook
.ipynb_checkpoints
# IPython
profile_default/
ipython_config.py
# pyenv
# For a library or package, you might want to ignore these files since the code is
# intended to run in multiple environments; otherwise, check them in:
# .python-version
# pipenv
# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control.
# However, in case of collaboration, if having platform-specific dependencies or dependencies
# having no cross-platform support, pipenv may install dependencies that don't work, or not
# install all needed dependencies.
#Pipfile.lock
# PEP 582; used by e.g. github.com/David-OConnor/pyflow
__pypackages__/
# Celery stuff
celerybeat-schedule
celerybeat.pid
# SageMath parsed files
*.sage.py
# Environments
.env
.venv
env/
venv/
ENV/
env.bak/
venv.bak/
# Spyder project settings
.spyderproject
.spyproject
# Rope project settings
.ropeproject
# mkdocs documentation
/site
# mypy
.mypy_cache/
.dmypy.json
dmypy.json
# Pyre type checker
.pyre/
# pytype static type analyzer
.pytype/
# Cython debug symbols
cython_debug/
# Prerequisites
*.d
# Object files
*.o
*.ko
*.obj
*.elf
# Linker output
*.ilk
*.map
*.exp
# Precompiled Headers
*.gch
*.pch
# Libraries
*.lib
*.a
*.la
*.lo
# Shared objects (inc. Windows DLLs)
*.dll
*.so
*.so.*
*.dylib
# Executables
*.exe
*.out
*.app
*.i*86
*.x86_64
*.hex
# Debug files
*.dSYM/
*.su
*.idb
*.pdb
# Kernel Module Compile Results
*.mod*
*.cmd
.tmp_versions/
modules.order
Module.symvers
Mkfile.old
dkms.con

29
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core/Kconfig Normal file
View File

@@ -0,0 +1,29 @@
mainmenu "RT-Thread Configuration"
config ROOT_DIR
string
default "../../../.."
config BSP_DIR
string
default "."
config RT_Thread_DIR
string
default "../.."
config RTT_DIR
string
default "../../rt-thread"
config APP_DIR
string
default "../../../../APP_Framework"
source "$RTT_DIR/Kconfig"
source "$RTT_DIR/bsp/stm32/libraries/Kconfig"
source "board/Kconfig"
source "$RT_Thread_DIR/micropython/Kconfig"
source "$RT_Thread_DIR/app_match_rt-thread/Kconfig"
source "$ROOT_DIR/APP_Framework/Kconfig"

124
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core/README.md Normal file
View File

@@ -0,0 +1,124 @@
# STM32F407最小系统板说明
## OV2640 menuconfig 配置：
​ More Driver-------->ov2640 driver （勾选） 保存即可
## RW007 menuconfig 配置：
​ More Driver-------->rw007:SPI WIFI rw007 driver
​ example driver port (rw007 for stm32)---->rw007 for stm32
​ (30000000) SPI MAX Hz
​ (spi1) RW007 BUS NAME
​ (7) CS pin index
​ (19) BOOT0 pin insex (same as spi clk pin)
​ (7) BOOT1 pin index (same as spi cs pin)
​ (87) INT/BUSY pin index
​ (88) RESET pin index
**上述引脚根据电路实际而定,另外涉及到相关的Lwip wifi framwork已经默认配置并匹配**
## 以下为引脚硬件的连接表
## **RW007(SPI1 )**
| 引脚 | 作用 | 引脚序号 | RW007板子 |
| ---- | --------- | -------- | --------- |
| PB3 | SPI1_SCK | 19 | SCK |
| PB4 | SPI1_MISO | 20 | MISO |
| PB5 | SPI1_MOSI | 21 | MOSI |
| PF6 | CS/BOOT1 | 86 | CS |
| PF7 | INT/BUSY | 87 | D9 |
| PF8 | RESET | 88 | D8 |
PF6 (PA7)
## uart2 串口2PC2
| PA2 | UART2 TX |
| ---- | -------- |
| PA3 | UART2 RX |
## SPI2 SD卡文件系统
| PC2 | SPI2_MISO |
| ---- | --------- |
| PC3 | SPI2_MOSI |
| PB13 | SPI2_SCK |
| PB12 | SPI2_CS |
## OV2460（DCMI接口）
| PD6 | SCCB_SCL |
| ---- | ---------- |
| PD7 | SCCB_SDA |
| PB7 | DCMI_VSYNC |
| PA4 | DCMI_HREF |
| PA6 | DCMI_PCLK |
| PG15 | DCMI_RESET |
| PG9 | DCMI_PWDN |
| PA8 | DCMI_XCLK |
| PE6 | DCMI_D7 |
| PE5 | DCMI_D6 |
| PB6 | DCMI_D5 |
| PC11 | DCMI_D4 |
| PC9 | DCMI_D3 |
| PC8 | DCMI_D2 |
| PC7 | DCMI_D1 |
| PC6 | DCMI_D0 |
## SRAM（FSMC接口）Pin
| PF0 | FSMC_A0 |
| ---- | --------- |
| PF1 | FSMC_A1 |
| PF2 | FSMC_A2 |
| PF3 | FSMC_A3 |
| PF4 | FSMC_A4 |
| PF5 | FSMC_A5 |
| PF12 | FSMC_A6 |
| PF13 | FSMC_A7 |
| PF14 | FSMC_A8 |
| PF15 | FSMC_A9 |
| PG0 | FSMC_A10 |
| PG1 | FSMC_A11 |
| PE7 | FSMC_D4 |
| PE8 | FSMC_D5 |
| PE9 | FSMC_D6 |
| PE10 | FSMC_D7 |
| PE11 | FSMC_D8 |
| PE12 | FSMC_D9 |
| PE13 | FSMC_D10 |
| PE14 | FSMC_D11 |
| PE15 | FSMC_D12 |
| PD8 | FSMC_D13 |
| PD9 | FSMC_D14 |
| PD10 | FSMC_D15 |
| PD11 | FSMC_A16 |
| PD12 | FSMC_A17 |
| PD13 | FSMC_A18 |
| PD14 | FSMC_D0 |
| PD15 | FSMC_D1 |
| PG2 | FSMC_A12 |
| PG3 | FSMC_A13 |
| PG4 | FSMC_A14 |
| PG5 | FSMC_A15 |
| PD0 | FSMC_D2 |
| PD1 | FSMC_D3 |
| PD4 | FSMC_NOE |
| PD5 | FSMC_NWE |
| PG10 | FSMC_NE3 |
| PE0 | FSMC_NBL0 |
| PE1 | FSMC_NBL1 |

15
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core/SConscript Normal file
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# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

92
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core/SConstruct Normal file
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import os
import sys
import rtconfig
import SCons
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../rt-thread')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
AddOption('--compiledb',
dest = 'compiledb',
action = 'store_true',
default = False,
help = 'generate compile_commands.json')
if GetOption('compiledb'):
if int(SCons.__version__.split('.')[0]) >= 4:
env['COMPILATIONDB_USE_ABSPATH'] = True
env.Tool('compilation_db')
env.CompilationDatabase('compile_commands.json')
else:
print('Warning: --compiledb only support on SCons 4.0+')
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
#if os.path.exists(SDK_ROOT + '/libraries'):
# libraries_path_prefix = SDK_ROOT + '/libraries'
#else:
# libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
libraries_path_prefix = RTT_ROOT + '/bsp/stm32/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
stm32_library = 'STM32F4xx_HAL'
rtconfig.BSP_LIBRARY_TYPE = stm32_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript')))
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
# include more drivers
objs.extend(SConscript(os.getcwd() + '/../../app_match_rt-thread/SConscript'))
# include APP_Framework/Framework
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Framework/SConscript'))
# include APP_Framework/Applications
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Applications/SConscript'))
# include APP_Framework/lib
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/lib/SConscript'))
# include Ubiquitous/RT-Thread/micropython
objs.extend(SConscript(os.getcwd() + '/../../micropython/SConscript'))
# make a building
DoBuilding(TARGET, objs)

16
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core/applications/SConscript Normal file
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import rtconfig
from building import *
cwd = GetCurrentDir()
CPPPATH = [cwd]
src = Split("""
main.c
""")
if GetDepend(['PKG_USING_RW007']):
src+=['rw007_test.c']
if GetDepend(['DRV_USING_OV2640']):
src+=['ov2640_test.c']
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

51
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core/applications/main.c Normal file
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/*
* @Author: chunyexixiaoyu
* @Date: 2021-09-24 16:33:15
* @LastEditTime: 2021-09-24 15:48:30
* @LastEditors: Please set LastEditors
* @Description: In User Settings Edit
* @FilePath: \xiuos\Ubiquitous\RT_Thread\bsp\stm32f407-atk-coreboard\applications\main.c
*/
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rtthread.h>
#include <board.h>
#include <stdio.h>
#include <string.h>
#ifdef RT_USING_POSIX
#include <pthread.h>
#include <unistd.h>
#include <stdio.h>
#include <dfs_poll.h>
#include <dfs_posix.h>
#include <dfs.h>
#ifdef RT_USING_POSIX_TERMIOS
#include <posix_termios.h>
#endif
#endif
#define LED0_PIN GET_PIN(F, 9)
extern int FrameworkInit();
int main(void)
{
int count = 1;
rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
rt_thread_mdelay(100);
FrameworkInit();
printf("XIUOS stm32f4 build %s %s\n",__DATE__,__TIME__);
while (count++)
{
rt_pin_write(LED0_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED0_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}

130
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core/applications/ov2640_test.c Normal file
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#include <rtthread.h>
#include <rtdevice.h>
#include "stdio.h"
#include "string.h"
#ifdef DRV_USING_OV2640
#ifdef RT_USING_POSIX
#include <dfs_posix.h>
#include <dfs_poll.h>
#ifdef RT_USING_POSIX_TERMIOS
#include <posix_termios.h>
#endif
#endif
#include<drv_ov2640.h>
#ifdef OV2640_JPEG_MODE
#define JPEG_BUF_SIZE (1024*200)
#else
#define JPEG_BUF_SIZE (2*OV2640_X_RESOLUTION_IMAGE_OUTSIZE*OV2640_Y_RESOLUTION_IMAGE_OUTSIZE)
#endif
#define UART_NUMBER2 "uart2"
void lcd_show_ov2640_thread(uint16_t* rgbbuffer);
static int fd = 0;
static _ioctl_shoot_para shoot_para_t = {0};
void ov2640_test(int argc, char **argv)
{
rt_thread_t tid;
rt_err_t ret = 0;
fd = open("/dev/ov2640",O_RDONLY);
if(fd < 0)
{
printf("open ov2640 fail !!");
return;
}
rt_uint8_t* JpegBuffer = rt_malloc(JPEG_BUF_SIZE);
if (RT_NULL == JpegBuffer)
{
printf("JpegBuffer senddata buf malloc error!\n");
return;
}
printf("ov2640 test by printing the image value in memory \r\n");
shoot_para_t.pdata = (uint32_t)JpegBuffer;
#ifdef OV2640_RGB565_MODE
shoot_para_t.length = JPEG_BUF_SIZE/2;
#elif defined OV2640_JPEG_MODE
shoot_para_t.length = JPEG_BUF_SIZE;
#endif
ret = ioctl(fd,IOCTRL_CAMERA_START_SHOT,&shoot_para_t);
if(RT_ERROR == ret)
{
printf("ov2640 can't wait event flag");
return;
}
#ifdef OV2640_JPEG_MODE
printf("print the vaule:\r\n\r\n");
ret = rt_ov2640_calculate_jpeg_len(JpegBuffer,JPEG_BUF_SIZE);
printf("photo leghth is %d :\r\n\r\n",ret);
#ifdef BSP_USING_UART2
void img_output_uart2(rt_uint8_t* jpegbuf,rt_uint16_t len);
img_output_uart2(JpegBuffer,ret);
#endif
for(int i =0;i<ret;i++)
{
printf("%x",*(JpegBuffer+i));
}
printf("\r\n\r\n above :\r\n\r\n");
rt_free(JpegBuffer);
close(fd);
#elif defined OV2640_RGB565_MODE
tid = rt_thread_create("lcdshow", lcd_show_ov2640_thread, JpegBuffer,3000, 9, 20);
rt_thread_startup(tid);
#endif
return;
}
MSH_CMD_EXPORT(ov2640_test,printing the image value in memory);
#ifdef BSP_USING_UART2
void img_output_uart2(rt_uint8_t* jpegbuf,rt_uint16_t len)
{
static rt_uint8_t i =0;
static rt_device_t serial = NULL;
int ret = RT_EOK;
if(i == 0)
{
i = 1;
serial = rt_device_find(UART_NUMBER2);
if (!serial)
{
printf("find uart2 failed!\n");
i = 2;
return;
}
ret = rt_device_open(serial, RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
if(ret != RT_EOK)
{
printf("open uart2 failed!\n");
i = 2;
return ;
}
}
if(i == 1)
{
rt_device_write(serial, 0, jpegbuf, len);
}
}
#endif
#ifdef OV2640_RGB565_MODE
extern void lcd_fill_array(rt_uint16_t x_start, rt_uint16_t y_start, rt_uint16_t x_end, rt_uint16_t y_end, void *pcolor);
void lcd_show_ov2640_thread(uint16_t* rgbbuffer)
{
rt_err_t ret = 0;
while(1)
{
ret = ioctl(fd,IOCTRL_CAMERA_START_SHOT,&shoot_para_t);
if(RT_ERROR == ret)
{
printf("ov2640 can't wait event flag");
rt_free(rgbbuffer);
return;
}
//lcd_show_image(0, 0, 320, 240, rgbbuffer);
lcd_fill_array(0,0,OV2640_X_RESOLUTION_IMAGE_OUTSIZE,OV2640_Y_RESOLUTION_IMAGE_OUTSIZE,rgbbuffer);
rt_thread_mdelay(1);
}
}
#endif
#endif

106
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core/applications/rw007_test.c Normal file
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#include <rtthread.h>
#ifdef PKG_USING_RW007
#include <netdb.h>
#include <string.h>
#include <finsh.h>
#include <sys/socket.h>
static const char send_data[] = "This is TCP Client from AIIT";
void rw007_test(int argc, char **argv)
{
int ret;
char *recv_data;
struct hostent *host;
int sock, bytes_received;
struct sockaddr_in server_addr;
const char *url;
int port;
extern rt_bool_t rt_wlan_is_connected(void);
if (rt_wlan_is_connected() != 1)
{
printf("Please connect a wifi firstly\n");
return;
}
if (argc < 3)
{
printf("Usage: tcpclient URL PORT\n");
printf("Like: tcpclient 192.168.12.44 5000\n");
return ;
}
url = argv[1];
port = strtoul(argv[2], 0, 10);
host = gethostbyname(url);
recv_data = rt_malloc(1024);
if (recv_data == RT_NULL)
{
printf("No memory\n");
return;
}
if ((sock = socket(AF_INET, SOCK_STREAM, 0)) == -1)
{
printf("Socket error\n");
rt_free(recv_data);
return;
}
server_addr.sin_family = AF_INET;
server_addr.sin_port = htons(port);
server_addr.sin_addr = *((struct in_addr *)host->h_addr);
rt_memset(&(server_addr.sin_zero), 0, sizeof(server_addr.sin_zero));
if (connect(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)) == -1)
{
printf("Connect fail!\n");
closesocket(sock);
rt_free(recv_data);
return;
}
else
{
printf("Connect successful\n");
}
while (1)
{
bytes_received = recv(sock, recv_data, 1024 - 1, 0);
if (bytes_received < 0)
{
closesocket(sock);
printf("\nreceived error,close the socket.\r\n");
rt_free(recv_data);
break;
}
else if (bytes_received == 0)
{
closesocket(sock);
printf("\nreceived error,close the socket.\r\n");
rt_free(recv_data);
break;
}
recv_data[bytes_received] = '\0';
if (strncmp(recv_data, "q", 1) == 0 || strncmp(recv_data, "Q", 1) == 0)
{
closesocket(sock);
printf("\n got a 'q' or 'Q',close the socket.\r\n");
rt_free(recv_data);
break;
}
else
{
printf("\nReceived data = %s ", recv_data);
}
ret = send(sock, send_data, strlen(send_data), 0);
if (ret < 0)
{
closesocket(sock);
printf("\nsend error,close the socket.\r\n");
rt_free(recv_data);
break;
}
else if (ret == 0)
{
printf("\n Send warning,send function return 0.\r\n");
}
}
return;
}
MSH_CMD_EXPORT(rw007_test, a tcp client sample);
#endif

17
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core/board/CubeMX_Config/.mxproject Normal file
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File diff suppressed because one or more lines are too long

443
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core/board/CubeMX_Config/CubeMX_Config.ioc Normal file
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#MicroXplorer Configuration settings - do not modify
ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_5
ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,master
ADC1.NbrOfConversionFlag=1
ADC1.Rank-0\#ChannelRegularConversion=1
ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES
ADC1.master=1
ETH.IPParameters=MediaInterface
ETH.MediaInterface=ETH_MEDIA_INTERFACE_RMII
FSMC.IPParameters=WriteOperation1
FSMC.WriteOperation1=FSMC_WRITE_OPERATION_ENABLE
File.Version=6
GPIO.groupedBy=Group By Peripherals
KeepUserPlacement=false
Mcu.Family=STM32F4
Mcu.IP0=ADC1
Mcu.IP1=ETH
Mcu.IP10=SYS
Mcu.IP11=TIM2
Mcu.IP12=TIM4
Mcu.IP13=TIM11
Mcu.IP14=TIM13
Mcu.IP15=TIM14
Mcu.IP16=USART1
Mcu.IP17=USART3
Mcu.IP18=USB_OTG_FS
Mcu.IP2=FSMC
Mcu.IP3=IWDG
Mcu.IP4=NVIC
Mcu.IP5=RCC
Mcu.IP6=RTC
Mcu.IP7=SDIO
Mcu.IP8=SPI1
Mcu.IP9=SPI2
Mcu.IPNb=19
Mcu.Name=STM32F407Z(E-G)Tx
Mcu.Package=LQFP144
Mcu.Pin0=PC14-OSC32_IN
Mcu.Pin1=PC15-OSC32_OUT
Mcu.Pin10=PC1
Mcu.Pin11=PC2
Mcu.Pin12=PC3
Mcu.Pin13=PA1
Mcu.Pin14=PA2
Mcu.Pin15=PA3
Mcu.Pin16=PA5
Mcu.Pin17=PA7
Mcu.Pin18=PC4
Mcu.Pin19=PC5
Mcu.Pin2=PF0
Mcu.Pin20=PF12
Mcu.Pin21=PF13
Mcu.Pin22=PF14
Mcu.Pin23=PF15
Mcu.Pin24=PG0
Mcu.Pin25=PG1
Mcu.Pin26=PE7
Mcu.Pin27=PE8
Mcu.Pin28=PE9
Mcu.Pin29=PE10
Mcu.Pin3=PF1
Mcu.Pin30=PE11
Mcu.Pin31=PE12
Mcu.Pin32=PE13
Mcu.Pin33=PE14
Mcu.Pin34=PE15
Mcu.Pin35=PB10
Mcu.Pin36=PB11
Mcu.Pin37=PB13
Mcu.Pin38=PD8
Mcu.Pin39=PD9
Mcu.Pin4=PF2
Mcu.Pin40=PD10
Mcu.Pin41=PD11
Mcu.Pin42=PD12
Mcu.Pin43=PD13
Mcu.Pin44=PD14
Mcu.Pin45=PD15
Mcu.Pin46=PG2
Mcu.Pin47=PG3
Mcu.Pin48=PG4
Mcu.Pin49=PG5
Mcu.Pin5=PF3
Mcu.Pin50=PC8
Mcu.Pin51=PC9
Mcu.Pin52=PA9
Mcu.Pin53=PA10
Mcu.Pin54=PA11
Mcu.Pin55=PA12
Mcu.Pin56=PA13
Mcu.Pin57=PA14
Mcu.Pin58=PC10
Mcu.Pin59=PC11
Mcu.Pin6=PF4
Mcu.Pin60=PC12
Mcu.Pin61=PD0
Mcu.Pin62=PD1
Mcu.Pin63=PD2
Mcu.Pin64=PD4
Mcu.Pin65=PD5
Mcu.Pin66=PG10
Mcu.Pin67=PG11
Mcu.Pin68=PG13
Mcu.Pin69=PG14
Mcu.Pin7=PF5
Mcu.Pin70=PB3
Mcu.Pin71=PB4
Mcu.Pin72=PB5
Mcu.Pin73=PB6
Mcu.Pin74=PB7
Mcu.Pin75=PE0
Mcu.Pin76=PE1
Mcu.Pin77=VP_IWDG_VS_IWDG
Mcu.Pin78=VP_RTC_VS_RTC_Activate
Mcu.Pin79=VP_SYS_VS_Systick
Mcu.Pin8=PH0-OSC_IN
Mcu.Pin80=VP_TIM2_VS_ClockSourceINT
Mcu.Pin81=VP_TIM11_VS_ClockSourceINT
Mcu.Pin82=VP_TIM13_VS_ClockSourceINT
Mcu.Pin83=VP_TIM14_VS_ClockSourceINT
Mcu.Pin9=PH1-OSC_OUT
Mcu.PinsNb=84
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F407ZGTx
MxCube.Version=5.6.0
MxDb.Version=DB.5.0.60
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SPI1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
PA1.Mode=RMII
PA1.Signal=ETH_REF_CLK
PA10.Mode=Asynchronous
PA10.Signal=USART1_RX
PA11.Mode=Device_Only
PA11.Signal=USB_OTG_FS_DM
PA12.Mode=Device_Only
PA12.Signal=USB_OTG_FS_DP
PA13.Mode=Serial_Wire
PA13.Signal=SYS_JTMS-SWDIO
PA14.Mode=Serial_Wire
PA14.Signal=SYS_JTCK-SWCLK
PA2.Mode=RMII
PA2.Signal=ETH_MDIO
PA3.Signal=S_TIM2_CH4
PA5.Locked=true
PA5.Signal=ADCx_IN5
PA7.Mode=RMII
PA7.Signal=ETH_CRS_DV
PA9.Mode=Asynchronous
PA9.Signal=USART1_TX
PB10.Mode=Asynchronous
PB10.Signal=USART3_TX
PB11.Mode=Asynchronous
PB11.Signal=USART3_RX
PB13.Mode=Full_Duplex_Master
PB13.Signal=SPI2_SCK
PB3.Locked=true
PB3.Mode=Full_Duplex_Master
PB3.Signal=SPI1_SCK
PB4.Locked=true
PB4.Mode=Full_Duplex_Master
PB4.Signal=SPI1_MISO
PB5.Locked=true
PB5.Mode=Full_Duplex_Master
PB5.Signal=SPI1_MOSI
PB6.Locked=true
PB6.Signal=S_TIM4_CH1
PB7.Locked=true
PB7.Signal=S_TIM4_CH2
PC1.Mode=RMII
PC1.Signal=ETH_MDC
PC10.Mode=SD_4_bits_Wide_bus
PC10.Signal=SDIO_D2
PC11.Mode=SD_4_bits_Wide_bus
PC11.Signal=SDIO_D3
PC12.Mode=SD_4_bits_Wide_bus
PC12.Signal=SDIO_CK
PC14-OSC32_IN.Mode=LSE-External-Oscillator
PC14-OSC32_IN.Signal=RCC_OSC32_IN
PC15-OSC32_OUT.Mode=LSE-External-Oscillator
PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
PC2.Mode=Full_Duplex_Master
PC2.Signal=SPI2_MISO
PC3.Mode=Full_Duplex_Master
PC3.Signal=SPI2_MOSI
PC4.Mode=RMII
PC4.Signal=ETH_RXD0
PC5.Mode=RMII
PC5.Signal=ETH_RXD1
PC8.Mode=SD_4_bits_Wide_bus
PC8.Signal=SDIO_D0
PC9.Mode=SD_4_bits_Wide_bus
PC9.Signal=SDIO_D1
PD0.Signal=FSMC_D2_DA2
PD1.Signal=FSMC_D3_DA3
PD10.Signal=FSMC_D15_DA15
PD11.Signal=FSMC_A16_CLE
PD12.Signal=FSMC_A17_ALE
PD13.Signal=FSMC_A18
PD14.Signal=FSMC_D0_DA0
PD15.Signal=FSMC_D1_DA1
PD2.Mode=SD_4_bits_Wide_bus
PD2.Signal=SDIO_CMD
PD4.Signal=FSMC_NOE
PD5.Signal=FSMC_NWE
PD8.Signal=FSMC_D13_DA13
PD9.Signal=FSMC_D14_DA14
PE0.Signal=FSMC_NBL0
PE1.Signal=FSMC_NBL1
PE10.Signal=FSMC_D7_DA7
PE11.Signal=FSMC_D8_DA8
PE12.Signal=FSMC_D9_DA9
PE13.Signal=FSMC_D10_DA10
PE14.Signal=FSMC_D11_DA11
PE15.Signal=FSMC_D12_DA12
PE7.Signal=FSMC_D4_DA4
PE8.Signal=FSMC_D5_DA5
PE9.Signal=FSMC_D6_DA6
PF0.Signal=FSMC_A0
PF1.Signal=FSMC_A1
PF12.Signal=FSMC_A6
PF13.Signal=FSMC_A7
PF14.Signal=FSMC_A8
PF15.Signal=FSMC_A9
PF2.Signal=FSMC_A2
PF3.Signal=FSMC_A3
PF4.Signal=FSMC_A4
PF5.Signal=FSMC_A5
PG0.Signal=FSMC_A10
PG1.Signal=FSMC_A11
PG10.Mode=NorPsramChipSelect3_1
PG10.Signal=FSMC_NE3
PG11.Locked=true
PG11.Mode=RMII
PG11.Signal=ETH_TX_EN
PG13.Locked=true
PG13.Mode=RMII
PG13.Signal=ETH_TXD0
PG14.Locked=true
PG14.Mode=RMII
PG14.Signal=ETH_TXD1
PG2.Signal=FSMC_A12
PG3.Signal=FSMC_A13
PG4.Signal=FSMC_A14
PG5.Signal=FSMC_A15
PH0-OSC_IN.Mode=HSE-External-Oscillator
PH0-OSC_IN.Signal=RCC_OSC_IN
PH1-OSC_OUT.Mode=HSE-External-Oscillator
PH1-OSC_OUT.Signal=RCC_OSC_OUT
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=false
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32F407ZGTx
ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.25.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=0
ProjectManager.MainLocation=Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=CubeMX_Config.ioc
ProjectManager.ProjectName=CubeMX_Config
ProjectManager.RegisterCallBack=
ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=MDK-ARM V5
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI1_Init-SPI1-false-HAL-true,5-MX_ETH_Init-ETH-false-HAL-true,6-MX_USART3_UART_Init-USART3-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_IWDG_Init-IWDG-false-HAL-true,10-MX_TIM14_Init-TIM14-false-HAL-true,11-MX_TIM13_Init-TIM13-false-HAL-true,12-MX_TIM11_Init-TIM11-false-HAL-true,13-MX_SDIO_SD_Init-SDIO-false-HAL-true,14-MX_TIM2_Init-TIM2-false-HAL-true,15-MX_SPI2_Init-SPI2-false-HAL-true,16-MX_TIM4_Init-TIM4-false-HAL-true,17-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,18-MX_FSMC_Init-FSMC-false-HAL-true
RCC.48MHZClocksFreq_Value=48000000
RCC.AHBFreq_Value=168000000
RCC.APB1CLKDivider=RCC_HCLK_DIV4
RCC.APB1Freq_Value=42000000
RCC.APB1TimFreq_Value=84000000
RCC.APB2CLKDivider=RCC_HCLK_DIV2
RCC.APB2Freq_Value=84000000
RCC.APB2TimFreq_Value=168000000
RCC.CortexFreq_Value=168000000
RCC.EthernetFreq_Value=168000000
RCC.FCLKCortexFreq_Value=168000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=168000000
RCC.HSE_VALUE=8000000
RCC.HSI_VALUE=16000000
RCC.I2SClocksFreq_Value=192000000
RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S
RCC.LSI_VALUE=32000
RCC.MCO2PinFreq_Value=168000000
RCC.PLLCLKFreq_Value=168000000
RCC.PLLM=4
RCC.PLLN=168
RCC.PLLQ=7
RCC.PLLQCLKFreq_Value=48000000
RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE
RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE
RCC.RTCFreq_Value=32768
RCC.RTCHSEDivFreq_Value=4000000
RCC.SYSCLKFreq_VALUE=168000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.VCOI2SOutputFreq_Value=384000000
RCC.VCOInputFreq_Value=2000000
RCC.VCOOutputFreq_Value=336000000
RCC.VcooutputI2S=192000000
SH.ADCx_IN5.0=ADC1_IN5,IN5
SH.ADCx_IN5.ConfNb=1
SH.FSMC_A0.0=FSMC_A0,19b-a1
SH.FSMC_A0.ConfNb=1
SH.FSMC_A1.0=FSMC_A1,19b-a1
SH.FSMC_A1.ConfNb=1
SH.FSMC_A10.0=FSMC_A10,19b-a1
SH.FSMC_A10.ConfNb=1
SH.FSMC_A11.0=FSMC_A11,19b-a1
SH.FSMC_A11.ConfNb=1
SH.FSMC_A12.0=FSMC_A12,19b-a1
SH.FSMC_A12.ConfNb=1
SH.FSMC_A13.0=FSMC_A13,19b-a1
SH.FSMC_A13.ConfNb=1
SH.FSMC_A14.0=FSMC_A14,19b-a1
SH.FSMC_A14.ConfNb=1
SH.FSMC_A15.0=FSMC_A15,19b-a1
SH.FSMC_A15.ConfNb=1
SH.FSMC_A16_CLE.0=FSMC_A16,19b-a1
SH.FSMC_A16_CLE.ConfNb=1
SH.FSMC_A17_ALE.0=FSMC_A17,19b-a1
SH.FSMC_A17_ALE.ConfNb=1
SH.FSMC_A18.0=FSMC_A18,19b-a1
SH.FSMC_A18.ConfNb=1
SH.FSMC_A2.0=FSMC_A2,19b-a1
SH.FSMC_A2.ConfNb=1
SH.FSMC_A3.0=FSMC_A3,19b-a1
SH.FSMC_A3.ConfNb=1
SH.FSMC_A4.0=FSMC_A4,19b-a1
SH.FSMC_A4.ConfNb=1
SH.FSMC_A5.0=FSMC_A5,19b-a1
SH.FSMC_A5.ConfNb=1
SH.FSMC_A6.0=FSMC_A6,19b-a1
SH.FSMC_A6.ConfNb=1
SH.FSMC_A7.0=FSMC_A7,19b-a1
SH.FSMC_A7.ConfNb=1
SH.FSMC_A8.0=FSMC_A8,19b-a1
SH.FSMC_A8.ConfNb=1
SH.FSMC_A9.0=FSMC_A9,19b-a1
SH.FSMC_A9.ConfNb=1
SH.FSMC_D0_DA0.0=FSMC_D0,16b-d1
SH.FSMC_D0_DA0.ConfNb=1
SH.FSMC_D10_DA10.0=FSMC_D10,16b-d1
SH.FSMC_D10_DA10.ConfNb=1
SH.FSMC_D11_DA11.0=FSMC_D11,16b-d1
SH.FSMC_D11_DA11.ConfNb=1
SH.FSMC_D12_DA12.0=FSMC_D12,16b-d1
SH.FSMC_D12_DA12.ConfNb=1
SH.FSMC_D13_DA13.0=FSMC_D13,16b-d1
SH.FSMC_D13_DA13.ConfNb=1
SH.FSMC_D14_DA14.0=FSMC_D14,16b-d1
SH.FSMC_D14_DA14.ConfNb=1
SH.FSMC_D15_DA15.0=FSMC_D15,16b-d1
SH.FSMC_D15_DA15.ConfNb=1
SH.FSMC_D1_DA1.0=FSMC_D1,16b-d1
SH.FSMC_D1_DA1.ConfNb=1
SH.FSMC_D2_DA2.0=FSMC_D2,16b-d1
SH.FSMC_D2_DA2.ConfNb=1
SH.FSMC_D3_DA3.0=FSMC_D3,16b-d1
SH.FSMC_D3_DA3.ConfNb=1
SH.FSMC_D4_DA4.0=FSMC_D4,16b-d1
SH.FSMC_D4_DA4.ConfNb=1
SH.FSMC_D5_DA5.0=FSMC_D5,16b-d1
SH.FSMC_D5_DA5.ConfNb=1
SH.FSMC_D6_DA6.0=FSMC_D6,16b-d1
SH.FSMC_D6_DA6.ConfNb=1
SH.FSMC_D7_DA7.0=FSMC_D7,16b-d1
SH.FSMC_D7_DA7.ConfNb=1
SH.FSMC_D8_DA8.0=FSMC_D8,16b-d1
SH.FSMC_D8_DA8.ConfNb=1
SH.FSMC_D9_DA9.0=FSMC_D9,16b-d1
SH.FSMC_D9_DA9.ConfNb=1
SH.FSMC_NBL0.0=FSMC_NBL0,2ByteEnable1
SH.FSMC_NBL0.ConfNb=1
SH.FSMC_NBL1.0=FSMC_NBL1,2ByteEnable1
SH.FSMC_NBL1.ConfNb=1
SH.FSMC_NOE.0=FSMC_NOE,Sram1
SH.FSMC_NOE.ConfNb=1
SH.FSMC_NWE.0=FSMC_NWE,Sram1
SH.FSMC_NWE.ConfNb=1
SH.S_TIM2_CH4.0=TIM2_CH4,PWM Generation4 CH4
SH.S_TIM2_CH4.ConfNb=1
SH.S_TIM4_CH1.0=TIM4_CH1,Encoder_Interface
SH.S_TIM4_CH1.ConfNb=1
SH.S_TIM4_CH2.0=TIM4_CH2,Encoder_Interface
SH.S_TIM4_CH2.ConfNb=1
SPI1.CalculateBaudRate=42.0 MBits/s
SPI1.Direction=SPI_DIRECTION_2LINES
SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
SPI1.Mode=SPI_MODE_MASTER
SPI1.VirtualType=VM_MASTER
SPI2.CalculateBaudRate=21.0 MBits/s
SPI2.Direction=SPI_DIRECTION_2LINES
SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
SPI2.Mode=SPI_MODE_MASTER
SPI2.VirtualType=VM_MASTER
TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
TIM2.IPParameters=Channel-PWM Generation4 CH4
USART1.IPParameters=VirtualMode
USART1.VirtualMode=VM_ASYNC
USART3.IPParameters=VirtualMode
USART3.VirtualMode=VM_ASYNC
USB_OTG_FS.IPParameters=VirtualMode
USB_OTG_FS.VirtualMode=Device_Only
VP_IWDG_VS_IWDG.Mode=IWDG_Activate
VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
VP_TIM11_VS_ClockSourceINT.Mode=Enable_Timer
VP_TIM11_VS_ClockSourceINT.Signal=TIM11_VS_ClockSourceINT
VP_TIM13_VS_ClockSourceINT.Mode=Enable_Timer
VP_TIM13_VS_ClockSourceINT.Signal=TIM13_VS_ClockSourceINT
VP_TIM14_VS_ClockSourceINT.Mode=Enable_Timer
VP_TIM14_VS_ClockSourceINT.Signal=TIM14_VS_ClockSourceINT
VP_TIM2_VS_ClockSourceINT.Mode=Internal
VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT
board=custom

93
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core/board/CubeMX_Config/Inc/main.h Normal file
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.h
* @brief : Header for main.c file.
* This file contains the common defines of the application.
******************************************************************************
** This notice applies to any and all portions of this file
* that are not between comment pairs USER CODE BEGIN and
* USER CODE END. Other portions of this file, whether
* inserted by the user or by software development tools
* are owned by their respective copyright owners.
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H
#define __MAIN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include <rtthread.h>
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

446
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h Normal file
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/**
******************************************************************************
* @file stm32f4xx_hal_conf_template.h
* @author MCD Application Team
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32f4xx_hal_conf.h.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CONF_H
#define __STM32F4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_CAN_MODULE_ENABLED */
/* #define HAL_CRC_MODULE_ENABLED */
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_DAC_MODULE_ENABLED */
#define HAL_DCMI_MODULE_ENABLED
/* #define HAL_DMA2D_MODULE_ENABLED */
#define HAL_ETH_MODULE_ENABLED
/* #define HAL_NAND_MODULE_ENABLED */
/* #define HAL_NOR_MODULE_ENABLED */
/* #define HAL_PCCARD_MODULE_ENABLED */
#define HAL_SRAM_MODULE_ENABLED
/* #define HAL_SDRAM_MODULE_ENABLED */
/* #define HAL_HASH_MODULE_ENABLED */
/* #define HAL_I2C_MODULE_ENABLED */
/* #define HAL_I2S_MODULE_ENABLED */
#define HAL_IWDG_MODULE_ENABLED
/* #define HAL_LTDC_MODULE_ENABLED */
/* #define HAL_RNG_MODULE_ENABLED */
#define HAL_RTC_MODULE_ENABLED
/* #define HAL_SAI_MODULE_ENABLED */
#define HAL_SD_MODULE_ENABLED
/* #define HAL_MMC_MODULE_ENABLED */
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
/* #define HAL_USART_MODULE_ENABLED */
/* #define HAL_IRDA_MODULE_ENABLED */
/* #define HAL_SMARTCARD_MODULE_ENABLED */
/* #define HAL_SMBUS_MODULE_ENABLED */
/* #define HAL_WWDG_MODULE_ENABLED */
#define HAL_PCD_MODULE_ENABLED
/* #define HAL_HCD_MODULE_ENABLED */
/* #define HAL_DSI_MODULE_ENABLED */
/* #define HAL_QSPI_MODULE_ENABLED */
/* #define HAL_QSPI_MODULE_ENABLED */
/* #define HAL_CEC_MODULE_ENABLED */
/* #define HAL_FMPI2C_MODULE_ENABLED */
/* #define HAL_SPDIFRX_MODULE_ENABLED */
/* #define HAL_DFSDM_MODULE_ENABLED */
/* #define HAL_LPTIM_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 1U
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2U
#define MAC_ADDR1 0U
#define MAC_ADDR2 0U
#define MAC_ADDR3 0U
#define MAC_ADDR4 0U
#define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* LAN8742A_PHY_ADDRESS Address*/
#define LAN8742A_PHY_ADDRESS 1U
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FFU)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)
#define PHY_READ_TO ((uint32_t)0x0000FFFFU)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x1FU) /*!< PHY status register Offset */
#define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< PHY Duplex mask */
#define PHY_ISFR ((uint16_t)0x001DU) /*!< PHY Interrupt Source Flag register Offset */
#define PHY_ISFR_INT4 ((uint16_t)0x000BU) /*!< PHY Link down inturrupt */
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 0U
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f4xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32f4xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32f4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32f4xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32f4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32f4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f4xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f4xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32f4xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32f4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f4xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32f4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32f4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32f4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32f4xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_DSI_MODULE_ENABLED
#include "stm32f4xx_hal_dsi.h"
#endif /* HAL_DSI_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
#include "stm32f4xx_hal_qspi.h"
#endif /* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32f4xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_FMPI2C_MODULE_ENABLED
#include "stm32f4xx_hal_fmpi2c.h"
#endif /* HAL_FMPI2C_MODULE_ENABLED */
#ifdef HAL_SPDIFRX_MODULE_ENABLED
#include "stm32f4xx_hal_spdifrx.h"
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED
#include "stm32f4xx_hal_dfsdm.h"
#endif /* HAL_DFSDM_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32f4xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f4xx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_IT_H
#define __STM32F4xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
void SPI1_IRQHandler(void);
void USART1_IRQHandler(void);
void OTG_FS_IRQHandler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_IT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
** This notice applies to any and all portions of this file
* that are not between comment pairs USER CODE BEGIN and
* USER CODE END. Other portions of this file, whether
* inserted by the user or by software development tools
* are owned by their respective copyright owners.
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
ADC_HandleTypeDef hadc1;
ETH_HandleTypeDef heth;
IWDG_HandleTypeDef hiwdg;
RTC_HandleTypeDef hrtc;
SD_HandleTypeDef hsd;
SPI_HandleTypeDef hspi1;
SPI_HandleTypeDef hspi2;
TIM_HandleTypeDef htim2;
TIM_HandleTypeDef htim4;
TIM_HandleTypeDef htim11;
TIM_HandleTypeDef htim13;
TIM_HandleTypeDef htim14;
UART_HandleTypeDef huart1;
UART_HandleTypeDef huart3;
PCD_HandleTypeDef hpcd_USB_OTG_FS;
/* USER CODE BEGIN PV */
/* Private variables ---------------------------------------------------------*/
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
static void MX_GPIO_Init(void);
static void MX_USART1_UART_Init(void);
static void MX_SPI1_Init(void);
static void MX_ETH_Init(void);
static void MX_USART3_UART_Init(void);
static void MX_ADC1_Init(void);
static void MX_RTC_Init(void);
static void MX_IWDG_Init(void);
static void MX_TIM14_Init(void);
static void MX_TIM13_Init(void);
static void MX_TIM11_Init(void);
static void MX_SDIO_SD_Init(void);
static void MX_TIM2_Init(void);
static void MX_SPI2_Init(void);
static void MX_TIM4_Init(void);
static void MX_USB_OTG_FS_PCD_Init(void);
/* USER CODE BEGIN PFP */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_USART1_UART_Init();
MX_SPI1_Init();
MX_ETH_Init();
MX_USART3_UART_Init();
MX_ADC1_Init();
MX_RTC_Init();
MX_IWDG_Init();
MX_TIM14_Init();
MX_TIM13_Init();
MX_TIM11_Init();
MX_SDIO_SD_Init();
MX_TIM2_Init();
MX_SPI2_Init();
MX_TIM4_Init();
MX_USB_OTG_FS_PCD_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
|RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 4;
RCC_OscInitStruct.PLL.PLLN = 168;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 7;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
{
Error_Handler();
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
}
/**
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
/* USER CODE BEGIN ADC1_Init 1 */
/* USER CODE END ADC1_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc1.Instance = ADC1;
hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
hadc1.Init.ScanConvMode = DISABLE;
hadc1.Init.ContinuousConvMode = DISABLE;
hadc1.Init.DiscontinuousConvMode = DISABLE;
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc1.Init.NbrOfConversion = 1;
hadc1.Init.DMAContinuousRequests = DISABLE;
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
if (HAL_ADC_Init(&hadc1) != HAL_OK)
{
Error_Handler();
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_5;
sConfig.Rank = 1;
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
/**
* @brief ETH Initialization Function
* @param None
* @retval None
*/
static void MX_ETH_Init(void)
{
/* USER CODE BEGIN ETH_Init 0 */
/* USER CODE END ETH_Init 0 */
/* USER CODE BEGIN ETH_Init 1 */
/* USER CODE END ETH_Init 1 */
heth.Instance = ETH;
heth.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
heth.Init.PhyAddress = LAN8742A_PHY_ADDRESS;
heth.Init.MACAddr[0] = 0x00;
heth.Init.MACAddr[1] = 0x80;
heth.Init.MACAddr[2] = 0xE1;
heth.Init.MACAddr[3] = 0x00;
heth.Init.MACAddr[4] = 0x00;
heth.Init.MACAddr[5] = 0x00;
heth.Init.RxMode = ETH_RXPOLLING_MODE;
heth.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
heth.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
/* USER CODE BEGIN MACADDRESS */
/* USER CODE END MACADDRESS */
if (HAL_ETH_Init(&heth) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN ETH_Init 2 */
/* USER CODE END ETH_Init 2 */
}
/**
* @brief IWDG Initialization Function
* @param None
* @retval None
*/
static void MX_IWDG_Init(void)
{
/* USER CODE BEGIN IWDG_Init 0 */
/* USER CODE END IWDG_Init 0 */
/* USER CODE BEGIN IWDG_Init 1 */
/* USER CODE END IWDG_Init 1 */
hiwdg.Instance = IWDG;
hiwdg.Init.Prescaler = IWDG_PRESCALER_4;
hiwdg.Init.Reload = 4095;
if (HAL_IWDG_Init(&hiwdg) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN IWDG_Init 2 */
/* USER CODE END IWDG_Init 2 */
}
/**
* @brief RTC Initialization Function
* @param None
* @retval None
*/
static void MX_RTC_Init(void)
{
/* USER CODE BEGIN RTC_Init 0 */
/* USER CODE END RTC_Init 0 */
/* USER CODE BEGIN RTC_Init 1 */
/* USER CODE END RTC_Init 1 */
/** Initialize RTC Only
*/
hrtc.Instance = RTC;
hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
hrtc.Init.AsynchPrediv = 127;
hrtc.Init.SynchPrediv = 255;
hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
if (HAL_RTC_Init(&hrtc) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN RTC_Init 2 */
/* USER CODE END RTC_Init 2 */
}
/**
* @brief SDIO Initialization Function
* @param None
* @retval None
*/
static void MX_SDIO_SD_Init(void)
{
/* USER CODE BEGIN SDIO_Init 0 */
/* USER CODE END SDIO_Init 0 */
/* USER CODE BEGIN SDIO_Init 1 */
/* USER CODE END SDIO_Init 1 */
hsd.Instance = SDIO;
hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
hsd.Init.BusWide = SDIO_BUS_WIDE_1B;
hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
hsd.Init.ClockDiv = 0;
if (HAL_SD_Init(&hsd) != HAL_OK)
{
Error_Handler();
}
if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN SDIO_Init 2 */
/* USER CODE END SDIO_Init 2 */
}
/**
* @brief SPI1 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI1_Init(void)
{
/* USER CODE BEGIN SPI1_Init 0 */
/* USER CODE END SPI1_Init 0 */
/* USER CODE BEGIN SPI1_Init 1 */
/* USER CODE END SPI1_Init 1 */
/* SPI1 parameter configuration*/
hspi1.Instance = SPI1;
hspi1.Init.Mode = SPI_MODE_MASTER;
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
hspi1.Init.NSS = SPI_NSS_SOFT;
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
hspi1.Init.CRCPolynomial = 10;
if (HAL_SPI_Init(&hspi1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN SPI1_Init 2 */
/* USER CODE END SPI1_Init 2 */
}
/**
* @brief SPI2 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI2_Init(void)
{
/* USER CODE BEGIN SPI2_Init 0 */
/* USER CODE END SPI2_Init 0 */
/* USER CODE BEGIN SPI2_Init 1 */
/* USER CODE END SPI2_Init 1 */
/* SPI2 parameter configuration*/
hspi2.Instance = SPI2;
hspi2.Init.Mode = SPI_MODE_MASTER;
hspi2.Init.Direction = SPI_DIRECTION_2LINES;
hspi2.Init.DataSize = SPI_DATASIZE_8BIT;
hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
hspi2.Init.NSS = SPI_NSS_SOFT;
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
hspi2.Init.CRCPolynomial = 10;
if (HAL_SPI_Init(&hspi2) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN SPI2_Init 2 */
/* USER CODE END SPI2_Init 2 */
}
/**
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
TIM_MasterConfigTypeDef sMasterConfig = {0};
TIM_OC_InitTypeDef sConfigOC = {0};
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
htim2.Init.Prescaler = 0;
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
htim2.Init.Period = 0;
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
{
Error_Handler();
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
{
Error_Handler();
}
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
{
Error_Handler();
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
{
Error_Handler();
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
sConfigOC.Pulse = 0;
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
HAL_TIM_MspPostInit(&htim2);
}
/**
* @brief TIM4 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM4_Init(void)
{
/* USER CODE BEGIN TIM4_Init 0 */
/* USER CODE END TIM4_Init 0 */
TIM_Encoder_InitTypeDef sConfig = {0};
TIM_MasterConfigTypeDef sMasterConfig = {0};
/* USER CODE BEGIN TIM4_Init 1 */
/* USER CODE END TIM4_Init 1 */
htim4.Instance = TIM4;
htim4.Init.Prescaler = 0;
htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
htim4.Init.Period = 0;
htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
sConfig.EncoderMode = TIM_ENCODERMODE_TI1;
sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
sConfig.IC1Filter = 0;
sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
sConfig.IC2Filter = 0;
if (HAL_TIM_Encoder_Init(&htim4, &sConfig) != HAL_OK)
{
Error_Handler();
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM4_Init 2 */
/* USER CODE END TIM4_Init 2 */
}
/**
* @brief TIM11 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM11_Init(void)
{
/* USER CODE BEGIN TIM11_Init 0 */
/* USER CODE END TIM11_Init 0 */
/* USER CODE BEGIN TIM11_Init 1 */
/* USER CODE END TIM11_Init 1 */
htim11.Instance = TIM11;
htim11.Init.Prescaler = 0;
htim11.Init.CounterMode = TIM_COUNTERMODE_UP;
htim11.Init.Period = 0;
htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim11) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM11_Init 2 */
/* USER CODE END TIM11_Init 2 */
}
/**
* @brief TIM13 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM13_Init(void)
{
/* USER CODE BEGIN TIM13_Init 0 */
/* USER CODE END TIM13_Init 0 */
/* USER CODE BEGIN TIM13_Init 1 */
/* USER CODE END TIM13_Init 1 */
htim13.Instance = TIM13;
htim13.Init.Prescaler = 0;
htim13.Init.CounterMode = TIM_COUNTERMODE_UP;
htim13.Init.Period = 0;
htim13.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim13.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim13) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM13_Init 2 */
/* USER CODE END TIM13_Init 2 */
}
/**
* @brief TIM14 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM14_Init(void)
{
/* USER CODE BEGIN TIM14_Init 0 */
/* USER CODE END TIM14_Init 0 */
/* USER CODE BEGIN TIM14_Init 1 */
/* USER CODE END TIM14_Init 1 */
htim14.Instance = TIM14;
htim14.Init.Prescaler = 0;
htim14.Init.CounterMode = TIM_COUNTERMODE_UP;
htim14.Init.Period = 0;
htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim14) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM14_Init 2 */
/* USER CODE END TIM14_Init 2 */
}
/**
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
/* USER CODE BEGIN USART1_Init 0 */
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
huart1.Init.BaudRate = 115200;
huart1.Init.WordLength = UART_WORDLENGTH_8B;
huart1.Init.StopBits = UART_STOPBITS_1;
huart1.Init.Parity = UART_PARITY_NONE;
huart1.Init.Mode = UART_MODE_TX_RX;
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
if (HAL_UART_Init(&huart1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
/**
* @brief USART3 Initialization Function
* @param None
* @retval None
*/
static void MX_USART3_UART_Init(void)
{
/* USER CODE BEGIN USART3_Init 0 */
/* USER CODE END USART3_Init 0 */
/* USER CODE BEGIN USART3_Init 1 */
/* USER CODE END USART3_Init 1 */
huart3.Instance = USART3;
huart3.Init.BaudRate = 115200;
huart3.Init.WordLength = UART_WORDLENGTH_8B;
huart3.Init.StopBits = UART_STOPBITS_1;
huart3.Init.Parity = UART_PARITY_NONE;
huart3.Init.Mode = UART_MODE_TX_RX;
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
if (HAL_UART_Init(&huart3) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN USART3_Init 2 */
/* USER CODE END USART3_Init 2 */
}
/**
* @brief USB_OTG_FS Initialization Function
* @param None
* @retval None
*/
static void MX_USB_OTG_FS_PCD_Init(void)
{
/* USER CODE BEGIN USB_OTG_FS_Init 0 */
/* USER CODE END USB_OTG_FS_Init 0 */
/* USER CODE BEGIN USB_OTG_FS_Init 1 */
/* USER CODE END USB_OTG_FS_Init 1 */
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
hpcd_USB_OTG_FS.Init.dev_endpoints = 4;
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
hpcd_USB_OTG_FS.Init.dma_enable = DISABLE;
hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN USB_OTG_FS_Init 2 */
/* USER CODE END USB_OTG_FS_Init 2 */
}
/**
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
}
/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
while(1)
{
}
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f4xx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
*
* COPYRIGHT(c) 2018 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32f4xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
extern SPI_HandleTypeDef hspi1;
extern UART_HandleTypeDef huart1;
extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
/* USER CODE BEGIN EV */
/* USER CODE END EV */
/******************************************************************************/
/* Cortex-M4 Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
}
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
}
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVCall_IRQn 0 */
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn 0 */
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
/******************************************************************************/
/* STM32F4xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32f4xx.s). */
/******************************************************************************/
/**
* @brief This function handles SPI1 global interrupt.
*/
void SPI1_IRQHandler(void)
{
/* USER CODE BEGIN SPI1_IRQn 0 */
/* USER CODE END SPI1_IRQn 0 */
HAL_SPI_IRQHandler(&hspi1);
/* USER CODE BEGIN SPI1_IRQn 1 */
/* USER CODE END SPI1_IRQn 1 */
}
/**
* @brief This function handles USART1 global interrupt.
*/
void USART1_IRQHandler(void)
{
/* USER CODE BEGIN USART1_IRQn 0 */
/* USER CODE END USART1_IRQn 0 */
HAL_UART_IRQHandler(&huart1);
/* USER CODE BEGIN USART1_IRQn 1 */
/* USER CODE END USART1_IRQn 1 */
}
/**
* @brief This function handles USB On The Go FS global interrupt.
*/
void OTG_FS_IRQHandler(void)
{
/* USER CODE BEGIN OTG_FS_IRQn 0 */
//You can open usb device or usb host, but open both of them is fatal error.
/* USER CODE END OTG_FS_IRQn 0 */
HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);
/* USER CODE BEGIN OTG_FS_IRQn 1 */
/* USER CODE END OTG_FS_IRQn 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

761
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/**
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx_system
* @{
*/
/** @addtogroup STM32F4xx_System_Private_Includes
* @{
*/
#include "stm32f4xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
STM32F412Zx || STM32F412Vx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/* #define DATA_IN_ExtSDRAM */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
STM32F479xx */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
* @{
*/
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
* depends on the application requirements), user has to ensure that HSE_VALUE
* is same as the real frequency of the crystal used. Otherwise, this function
* may have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
* This function configures the external memories (SRAM/SDRAM)
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
__IO uint32_t tmp = 0x00;
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register __IO uint32_t index;
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
RCC->AHB1ENR |= 0x000001F8;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xAA800AAA;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0xAAAAAAAA;
/* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0xAAAAAAAA;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x00000000;
/* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000;
/*-- FMC Configuration -------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
FMC_Bank5_6->SDCR[0] = 0x000019E4;
FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Delay */
for (index = 0; index<1000; index++);
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Auto refresh command */
FMC_Bank5_6->SDCMR = 0x00000073;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* MRD register program */
FMC_Bank5_6->SDCMR = 0x00046014;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR;
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
/* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F469xx) || defined(STM32F479xx)
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001091;
FMC_Bank1->BTCR[3] = 0x00110212;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F469xx || STM32F479xx */
(void)(tmp);
}
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
* This function configures the external memories (SRAM/SDRAM)
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
__IO uint32_t tmp = 0x00;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#if defined (DATA_IN_ExtSDRAM)
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register __IO uint32_t index;
#if defined(STM32F446xx)
/* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
clock */
RCC->AHB1ENR |= 0x0000007D;
#else
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
clock */
RCC->AHB1ENR |= 0x000001F8;
#endif /* STM32F446xx */
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
#if defined(STM32F446xx)
/* Connect PAx pins to FMC Alternate function */
GPIOA->AFR[0] |= 0xC0000000;
GPIOA->AFR[1] |= 0x00000000;
/* Configure PDx pins in Alternate function mode */
GPIOA->MODER |= 0x00008000;
/* Configure PDx pins speed to 50 MHz */
GPIOA->OSPEEDR |= 0x00008000;
/* Configure PDx pins Output type to push-pull */
GPIOA->OTYPER |= 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOA->PUPDR |= 0x00000000;
/* Connect PCx pins to FMC Alternate function */
GPIOC->AFR[0] |= 0x00CC0000;
GPIOC->AFR[1] |= 0x00000000;
/* Configure PDx pins in Alternate function mode */
GPIOC->MODER |= 0x00000A00;
/* Configure PDx pins speed to 50 MHz */
GPIOC->OSPEEDR |= 0x00000A00;
/* Configure PDx pins Output type to push-pull */
GPIOC->OTYPER |= 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOC->PUPDR |= 0x00000000;
#endif /* STM32F446xx */
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x000000CC;
GPIOD->AFR[1] = 0xCC000CCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xA02A000A;
/* Configure PDx pins speed to 50 MHz */
GPIOD->OSPEEDR = 0xA02A000A;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00000CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA800A;
/* Configure PEx pins speed to 50 MHz */
GPIOE->OSPEEDR = 0xAAAA800A;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 50 MHz */
GPIOF->OSPEEDR = 0xAA800AAA;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0xAAAAAAAA;
/* Configure PGx pins speed to 50 MHz */
GPIOG->OSPEEDR = 0xAAAAAAAA;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
/* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA08A0;
/* Configure PHx pins speed to 50 MHz */
GPIOH->OSPEEDR = 0xAAAA08A0;
/* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x00000000;
/* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 50 MHz */
GPIOI->OSPEEDR = 0x0028AAAA;
/* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
/*-- FMC Configuration -------------------------------------------------------*/
/* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
/* Configure and enable SDRAM bank1 */
#if defined(STM32F446xx)
FMC_Bank5_6->SDCR[0] = 0x00001954;
#else
FMC_Bank5_6->SDCR[0] = 0x000019E4;
#endif /* STM32F446xx */
FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Delay */
for (index = 0; index<1000; index++);
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Auto refresh command */
#if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x000000F3;
#else
FMC_Bank5_6->SDCMR = 0x00000073;
#endif /* STM32F446xx */
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* MRD register program */
#if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x00044014;
#else
FMC_Bank5_6->SDCMR = 0x00046014;
#endif /* STM32F446xx */
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR;
#if defined(STM32F446xx)
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
#else
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
#endif /* STM32F446xx */
/* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#endif /* DATA_IN_ExtSDRAM */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
#if defined(DATA_IN_ExtSRAM)
/*-- GPIOs Configuration -----------------------------------------------------*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR |= 0x00000078;
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCC0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA000AAA;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xFF000FFF;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0x00CCCCCC;
GPIOG->AFR[1] = 0x000000C0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00085AAA;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000CAFFF;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FMC/FSMC Configuration --------------------------------------------------*/
/* Enable the FMC/FSMC interface clock */
RCC->AHB3ENR |= 0x00000001;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#if defined(STM32F469xx) || defined(STM32F479xx)
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001091;
FMC_Bank1->BTCR[3] = 0x00110212;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif /* STM32F469xx || STM32F479xx */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
|| defined(STM32F412Zx) || defined(STM32F412Vx)
/* Delay after an RCC peripheral clock enabling */
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001011;
FSMC_Bank1->BTCR[3] = 0x00000201;
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
#endif /* DATA_IN_ExtSRAM */
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
(void)(tmp);
}
#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

375
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core/board/Kconfig Normal file
View File

@@ -0,0 +1,375 @@
menu "Hardware Drivers Config"
config SOC_STM32F407ZG
bool
select SOC_SERIES_STM32F4
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_USB_TO_USART
bool "Enable USB TO USART (uart1)"
select BSP_USING_UART
select BSP_USING_UART1
default y
config BSP_USING_COM2
bool "Enable COM2 (uart2 pin conflict with Ethernet and PWM)"
select BSP_USING_UART
select BSP_USING_UART2
default n
config BSP_USING_COM3
bool "Enable COM3 (uart3)"
select BSP_USING_UART
select BSP_USING_UART3
default n
config BSP_USING_SRAM
bool "Enable SRAM"
select BSP_USING_EXT_FMC_IO
select BSP_USING_FMC
default n
config BSP_USING_MCU_LCD
bool "Enable ATK LCD"
select BSP_USING_SRAM
default n
if BSP_USING_MCU_LCD
config BSP_USING_MCU_LCD_TEST
bool "Enable lcd fill test"
default y
endif
config BSP_USING_SPI_FLASH
bool "Enable SPI FLASH (W25Q128 spi2)"
select BSP_USING_SPI
select BSP_USING_SPI1
select RT_USING_SFUD
select RT_SFUD_USING_SFDP
default n
config BSP_USING_EEPROM
bool "Enable I2C EEPROM (i2c1)"
select BSP_USING_I2C1
default n
config PHY_USING_LAN8720A
bool
config BSP_USING_OV2640
bool "Enable camera (ov2640)"
select BSP_USING_DCMI
default n
config BSP_USING_ETH
bool "Enable Ethernet"
default n
select RT_USING_LWIP
select PHY_USING_LAN8720A
config BSP_USING_MPU6050
bool "Enable MPU6050 (i2c1)"
default n
select BSP_USING_I2C1
select PKG_USING_MPU6XXX
config BSP_USING_SDCARD
bool "Enable SDCARD (spi2)"
select BSP_USING_SPI
select BSP_USING_SPI2
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
select RT_USING_SPI_MSD
default n
if BSP_USING_SDCARD
config SDCARD_SPI2_CS_PIN
int "spi2 cs pin"
default 28
config SDCARD_SPI_BUS_NAME
string "SD CARD BUS NAME"
default "spi2"
endif
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_UART1_TX_USING_DMA
bool "Enable UART1 TX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART2
bool "Enable UART2"
default n
config BSP_UART2_RX_USING_DMA
bool "Enable UART2 RX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_UART2_TX_USING_DMA
bool "Enable UART2 TX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART3
bool "Enable UART3"
default n
config BSP_UART3_RX_USING_DMA
bool "Enable UART3 RX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
config BSP_UART3_TX_USING_DMA
bool "Enable UART3 TX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART4
bool "Enable UART4"
default n
config BSP_UART4_RX_USING_DMA
bool "Enable UART4 RX DMA"
depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
default n
config BSP_UART4_TX_USING_DMA
bool "Enable UART4 TX DMA"
depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART5
bool "Enable UART5"
default n
config BSP_UART5_RX_USING_DMA
bool "Enable UART5 RX DMA"
depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
default n
config BSP_UART5_TX_USING_DMA
bool "Enable UART5 TX DMA"
depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART6
bool "Enable UART6"
default n
config BSP_UART6_RX_USING_DMA
bool "Enable UART6 RX DMA"
depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
default n
config BSP_UART6_TX_USING_DMA
bool "Enable UART6 TX DMA"
depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
default n
endif
menuconfig BSP_USING_TIM
bool "Enable timer"
default n
select RT_USING_HWTIMER
if BSP_USING_TIM
config BSP_USING_TIM11
bool "Enable TIM11"
default n
config BSP_USING_TIM13
bool "Enable TIM13"
default n
config BSP_USING_TIM14
bool "Enable TIM14"
default n
endif
menuconfig BSP_USING_PWM
bool "Enable pwm"
default n
select RT_USING_PWM
if BSP_USING_PWM
menuconfig BSP_USING_PWM2
bool "Enable timer2 output pwm"
default n
if BSP_USING_PWM2
config BSP_USING_PWM2_CH4
bool "Enable PWM2 channel4"
default n
endif
endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_SPI1_TX_USING_DMA
bool "Enable SPI1 TX DMA"
depends on BSP_USING_SPI1
default n
config BSP_SPI1_RX_USING_DMA
bool "Enable SPI1 RX DMA"
depends on BSP_USING_SPI1
select BSP_SPI1_TX_USING_DMA
default n
config BSP_USING_SPI2
bool "Enable SPI2 BUS"
default n
config BSP_SPI2_TX_USING_DMA
bool "Enable SPI2 TX DMA"
depends on BSP_USING_SPI2
default n
config BSP_SPI2_RX_USING_DMA
bool "Enable SPI2 RX DMA"
depends on BSP_USING_SPI2
select BSP_SPI2_TX_USING_DMA
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC1
bool "Enable ADC1"
default n
endif
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default y
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C1
config BSP_I2C1_SCL_PIN
int "i2c1 scl pin number"
range 0 143
default 24
config BSP_I2C1_SDA_PIN
int "I2C1 sda pin number"
range 0 143
default 25
endif
menuconfig BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
select RT_USING_LIBC
default n
if BSP_USING_ONCHIP_RTC
choice
prompt "Select clock source"
default BSP_RTC_USING_LSE
config BSP_RTC_USING_LSE
bool "RTC USING LSE"
config BSP_RTC_USING_LSI
bool "RTC USING LSI"
endchoice
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_SDIO
bool "Enable SDIO"
select RT_USING_SDIO
select RT_USING_DFS
default n
config BSP_USING_DCMI
bool "Enable DCMI(camera)"
default n
config BSP_USING_USBD
bool "Enable USB Device"
select RT_USING_USB_DEVICE
default n
menuconfig BSP_USING_USBH
bool "Enable USB Host"
select RT_USING_USB_HOST
default n
if BSP_USING_USBH
menuconfig RT_USBH_MSTORAGE
bool "Enable Udisk Drivers"
default n
if RT_USBH_MSTORAGE
config UDISK_MOUNTPOINT
string "Udisk mount dir"
default "/"
endif
endif
menuconfig BSP_USING_PULSE_ENCODER
bool "Enable Pulse Encoder"
default n
select RT_USING_PULSE_ENCODER
if BSP_USING_PULSE_ENCODER
config BSP_USING_PULSE_ENCODER4
bool "Enable Pulse Encoder4"
default n
endif
config BSP_USING_EXT_FMC_IO
bool
default n
config BSP_USING_FMC
bool
default n
source "$RTT_DIR/bsp/stm32/libraries/HAL_Drivers/Kconfig"
endmenu
menu "Board extended module Drivers"
endmenu
endmenu

53
Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/stm32f407_core/board/SConscript Normal file
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@@ -0,0 +1,53 @@
import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
src = Split('''
board.c
CubeMX_Config/Src/stm32f4xx_hal_msp.c
''')
if GetDepend(['BSP_USING_ETH']):
src += Glob('ports/phy_reset.c')
if GetDepend(['BSP_USING_SPI_FLASH']):
src += Glob('ports/flash_port.c')
if GetDepend(['BSP_USING_SDCARD']):
src += Glob('ports/sdcard_port.c')
if GetDepend(['BSP_USING_SRAM']):
src += Glob('ports/drv_sram.c')
if GetDepend(['BSP_USING_MCU_LCD']):
src += Glob('ports/drv_lcd.c')
if GetDepend(['BSP_USING_DCMI']):
src += ['drv_dcmi.c']
src += ['../../../../rt-thread/bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi.c']
if GetDepend(['RT_USING_DFS_ROMFS']):
src += ['ports/romfs.c']
src += ['ports/mnt_romfs.c']
path = [cwd]
path += [cwd + '/CubeMX_Config/Inc']
path += [cwd + '/ports']
startup_path_prefix = SDK_LIB
if rtconfig.CROSS_TOOL == 'gcc':
src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s']
elif rtconfig.CROSS_TOOL == 'keil':
src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f407xx.s']
elif rtconfig.CROSS_TOOL == 'iar':
src += [startup_path_prefix + '/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f407xx.s']
CPPDEFINES = ['STM32F407xx']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

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