feat modify XiUOS_Kernel dir from Ubiquitous/XiUOS to Ubiquitous/XiZi

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/Kconfig

@@ -0,0 +1,110 @@
+menuconfig BSP_USING_CH376
+bool "Using CH376 device"
+default n
+select FS_VFS
+select FS_CH376
+if BSP_USING_CH376
+source "$BSP_DIR/third_party_driver/ch376/Kconfig"
+endif
+
+menuconfig BSP_USING_CH438
+bool "Using CH438 device"
+default y
+if BSP_USING_CH438
+source "$BSP_DIR/third_party_driver/ch438/Kconfig"
+endif
+
+menuconfig BSP_USING_DMA
+bool "Using DMA device"
+default y
+if BSP_USING_DMA
+source "$BSP_DIR/third_party_driver/dma/Kconfig"
+endif
+
+menuconfig BSP_USING_GPIO
+bool "Using GPIO device"
+default y
+select RESOURCES_PIN
+if BSP_USING_GPIO
+source "$BSP_DIR/third_party_driver/gpio/Kconfig"
+endif
+
+menuconfig BSP_USING_I2C
+bool "Using I2C device"
+default n
+select RESOURCES_I2C
+if BSP_USING_I2C
+source "$BSP_DIR/third_party_driver/i2c/Kconfig"
+endif
+
+menuconfig BSP_USING_LCD
+bool "Using LCD device"
+default n
+select RESOURCES_LCD
+select BSP_USING_SPI1
+if BSP_USING_LCD
+source "$BSP_DIR/third_party_driver/lcd/Kconfig"
+endif
+
+menuconfig BSP_USING_PLIC
+bool "Using PLIC device"
+default y
+if BSP_USING_PLIC
+source "$BSP_DIR/third_party_driver/plic/Kconfig"
+endif
+
+menuconfig BSP_USING_RTC
+bool "Using RTC device"
+default n
+select RESOURCES_RTC
+if BSP_USING_RTC
+source "$BSP_DIR/third_party_driver/rtc/Kconfig"
+endif
+
+menuconfig BSP_USING_SPI
+bool "Using SPI device"
+default n
+select RESOURCES_SPI
+select  BSP_USING_DMA
+if BSP_USING_SPI
+source "$BSP_DIR/third_party_driver/spi/Kconfig"
+endif
+
+menuconfig BSP_USING_SYSCLOCK
+bool "Using SYSCLOCK device"
+default y
+if BSP_USING_SYSCLOCK
+source "$BSP_DIR/third_party_driver/sys_clock/Kconfig"
+endif
+
+menuconfig BSP_USING_HWTIMER
+bool "Using HWTIMER device"
+default n
+select RESOURCES_HWTIMER
+if BSP_USING_HWTIMER
+source "$BSP_DIR/third_party_driver/timer/Kconfig"
+endif
+
+menuconfig BSP_USING_TOUCH
+bool "Using TOUCH device"
+default n
+select RESOURCES_TOUCH
+if BSP_USING_TOUCH
+source "$BSP_DIR/third_party_driver/touch/Kconfig"
+endif
+
+menuconfig BSP_USING_UART
+bool "Using UART device"
+default y
+select RESOURCES_SERIAL
+if BSP_USING_UART
+source "$BSP_DIR/third_party_driver/uart/Kconfig"
+endif
+
+menuconfig BSP_USING_WDT
+bool "Using WATCHDOG device"
+default y
+select RESOURCES_WDT
+if BSP_USING_WDT
+source "$BSP_DIR/third_party_driver/watchdog/Kconfig"
+endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/Makefile

@@ -0,0 +1,91 @@
+SRC_FILES := sleep.c  
+
+ifeq ($(CONFIG_BSP_USING_AUDIO),y)
+  SRC_DIR += audio
+endif
+
+ifeq ($(CONFIG_BSP_USING_CAMERA),y)
+  SRC_DIR += camera
+endif
+
+ifeq ($(CONFIG_BSP_USING_CH376),y)
+  SRC_DIR += ch376
+endif
+
+ifeq ($(CONFIG_BSP_USING_CH438),y)
+  SRC_DIR += ch438
+endif
+
+ifeq ($(CONFIG_BSP_USING_DMA),y)
+  SRC_DIR += dma
+endif
+
+ifeq ($(CONFIG_ BSP_USING_FFT),y)
+  SRC_DIR += fft
+endif
+
+ifeq ($(CONFIG_BSP_USING_GPIO),y)
+  SRC_DIR += gpio
+endif
+
+ifeq ($(CONFIG_BSP_USING_I2C),y)
+  SRC_DIR += i2c
+endif
+
+ifeq ($(CONFIG_BSP_USING_I2S),y)
+  SRC_DIR += i2s
+endif
+
+ifeq ($(CONFIG_BSP_USING_KPU),y)
+  SRC_DIR += kpu
+endif
+
+ifeq ($(CONFIG_BSP_USING_LCD),y)
+  SRC_DIR += lcd
+endif
+
+ifeq ($(CONFIG_BSP_USING_PLIC),y)
+  SRC_DIR += plic
+endif
+
+ifeq ($(CONFIG_BSP_USING_PWM),y)
+  SRC_DIR += pwm
+endif
+
+ifeq ($(CONFIG_BSP_USING_RTC),y)
+  SRC_DIR += rtc
+endif
+
+ifeq ($(CONFIG_BSP_USING_SECURITY),y)
+  SRC_DIR += security
+endif
+
+ifeq ($(CONFIG_BSP_USING_SPI),y)
+  SRC_DIR += spi
+endif
+
+ifeq ($(CONFIG_BSP_USING_SYSCLOCK),y)
+  SRC_DIR += sys_clock
+endif
+
+ifeq ($(CONFIG_BSP_USING_HWTIMER),y)
+  SRC_DIR += timer
+endif
+
+ifeq ($(CONFIG_BSP_USING_TOUCH),y)
+  SRC_DIR += touch
+endif
+
+ifeq ($(CONFIG_BSP_USING_UART),y)
+  SRC_DIR += uart
+endif
+
+ifeq ($(CONFIG_BSP_USING_VIDEO),y)
+  SRC_DIR += video
+endif
+
+ifeq ($(CONFIG_BSP_USING_WDT),y)
+  SRC_DIR += watchdog
+endif
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch376/Kconfig

@@ -0,0 +1,35 @@
+menuconfig BSP_USING_SDIO
+bool "Using CH376 SD card"
+default n
+select RESOURCES_SDIO
+if BSP_USING_SDIO
+config SDIO_BUS_NAME
+    string "sdio bus name"
+    default "sdio"
+
+config SDIO_DRIVER_NAME
+    string "sdio driver name"
+    default "sdio_drv"
+
+config SDIO_DEVICE_NAME
+    string "sdio device name"
+    default "sdio_dev"
+endif
+
+menuconfig BSP_USING_USB
+bool "Using CH376 USB"
+default n
+select RESOURCES_USB
+if BSP_USING_USB
+config USB_BUS_NAME
+    string "USB bus name"
+    default "usb"
+
+config USB_DRIVER_NAME
+    string "USB driver name"
+    default "usb_drv"
+
+config USB_DEVICE_NAME
+    string "USB device name"
+    default "usb_dev"
+endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch376/Makefile

@@ -0,0 +1,4 @@
+SRC_FILES := connect_ch376.c
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch376/connect_ch376.c

@@ -0,0 +1,224 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_ch436.c
+* @brief support to register ch436 pointer and function
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-24
+*/
+
+#include <ch376fs.h>
+#include <connect_ch376.h>
+
+static struct HwCh376 sdio;
+
+static uint32 Ch376Configure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    uint8 temp[2];
+    temp[0] = 0x57;
+    temp[1] = 0xab;
+    MdelayKTask(100);
+
+    struct BusBlockWriteParam write_param;
+    write_param.pos = 0;
+    write_param.buffer = (void *)temp;
+    write_param.size = 2;
+    BusDevWriteData(sdio.dev, &write_param);
+
+    write_param.pos = 0;
+    write_param.buffer = &configure_info->configure_cmd;
+    write_param.size = 1;
+    BusDevWriteData(sdio.dev, &write_param);
+
+    return EOK;
+}
+
+static int HwCh376RxInd(void *dev, x_size_t length)
+{
+    sdio.msg_len += length;
+    KSemaphoreAbandon(sdio.sem);
+
+    return EOK;
+}
+
+static uint32 Ch376Open(void *dev)
+{
+    NULL_PARAM_CHECK(dev);
+
+    sdio.sem = KSemaphoreCreate(0);
+    if (sdio.sem < 0) {
+        KPrintf("CH376 open fail\n");
+        return -ERROR;
+    }
+
+    struct Bus *bus = BusFind(SERIAL_BUS_NAME_2);
+    struct Driver *bus_driver = BusFindDriver(bus, SERIAL_DRV_NAME_2);
+    sdio.dev = BusFindDevice(bus, SERIAL_2_DEVICE_NAME_0);
+    if (!sdio.dev) {
+        KPrintf("CH376 open fail\n");
+        return -ERROR;
+    }
+
+    struct SerialCfgParam serial_cfg;
+    memset(&serial_cfg, 0, sizeof(struct SerialCfgParam));
+    serial_cfg.data_cfg.serial_buffer_size = 512;
+    struct BusConfigureInfo cfg;
+    cfg.configure_cmd = OPE_INT;
+    cfg.private_data = &serial_cfg;
+
+    BusDrvConfigure(bus_driver, &cfg);
+
+    bus->match(bus_driver, sdio.dev);
+
+    struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)sdio.dev->private_data;
+    serial_dev_param->serial_set_mode = SIGN_OPER_INT_RX;
+    BusDevOpen(sdio.dev);
+
+    BusDevRecvCallback(sdio.dev, HwCh376RxInd);
+
+    KPrintf("CH376 open done\n");
+
+    return EOK;
+}
+
+static uint32 Ch376Close(void *dev)
+{
+    BusDevClose(sdio.dev);
+    KSemaphoreDelete(sdio.sem);
+
+    return EOK;
+}
+
+static uint32 Ch376Write(void *dev, struct BusBlockWriteParam *write_param)
+{
+    if (EOK == BusDevWriteData(sdio.dev, write_param))
+        return EOK;
+
+    return -ERROR;
+}
+
+static uint32 Ch376Read(void *dev, struct BusBlockReadParam *read_param)
+{
+    if (KSemaphoreObtain(sdio.sem, WAITING_FOREVER) == EOK) {
+        while(KSemaphoreObtain(sdio.sem, TICK_PER_SECOND) != -ETIMEOUT);
+        read_param->size = sdio.msg_len;
+        BusDevReadData(sdio.dev, read_param);
+        sdio.msg_len = 0;
+    }
+    
+    return read_param->read_length;
+}
+
+#ifdef BSP_USING_SDIO
+static struct SdioDevDone sdio_done = 
+{
+    Ch376Open,
+    Ch376Close,
+    Ch376Write,
+    Ch376Read,
+};
+#endif
+
+#ifdef BSP_USING_USB
+static struct UsbDevDone usb_done = 
+{
+    Ch376Open,
+    Ch376Close,
+    Ch376Write,
+    Ch376Read,
+};
+#endif
+
+int HwCh376Init(void)
+{
+    x_err_t ret = EOK;
+
+#ifdef BSP_USING_SDIO
+    static struct SdioBus sdio_bus;
+    static struct SdioDriver sdio_drv;
+    static struct SdioHardwareDevice sdio_dev;
+    
+    ret = SdioBusInit(&sdio_bus, SDIO_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("Sdio bus init error %d\n", ret);
+        return -ERROR;
+    }
+
+    sdio_drv.configure = &Ch376Configure;
+    ret = SdioDriverInit(&sdio_drv, SDIO_DRIVER_NAME);
+    if (ret != EOK) {
+        KPrintf("Sdio driver init error %d\n", ret);
+        return -ERROR;
+    }
+
+    ret = SdioDriverAttachToBus(SDIO_DRIVER_NAME, SDIO_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("Sdio driver attach error %d\n", ret);
+        return -ERROR;
+    }
+
+    sdio_dev.dev_done = &sdio_done;
+    ret = SdioDeviceRegister(&sdio_dev, SDIO_DEVICE_NAME);
+    if (ret != EOK) {
+        KPrintf("Sdio device register error %d\n", ret);
+        return -ERROR;
+    }
+
+    ret = SdioDeviceAttachToBus(SDIO_DEVICE_NAME, SDIO_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("Sdio device register error %d\n", ret);
+        return -ERROR;
+    }
+#endif
+
+#ifdef BSP_USING_USB
+    static struct UsbBus usb_bus;
+    static struct UsbDriver usb_drv;
+    static struct UsbHardwareDevice usb_dev;
+    
+    ret = UsbBusInit(&usb_bus, USB_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("USB bus init error %d\n", ret);
+        return -ERROR;
+    }
+
+    usb_drv.configure = &Ch376Configure;
+    ret = UsbDriverInit(&usb_drv, USB_DRIVER_NAME);
+    if (ret != EOK) {
+        KPrintf("USB driver init error %d\n", ret);
+        return -ERROR;
+    }
+    ret = UsbDriverAttachToBus(USB_DRIVER_NAME, USB_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("USB driver attach error %d\n", ret);
+        return -ERROR;
+    }
+
+    usb_dev.dev_done = &usb_done;
+    ret = USBDeviceRegister(&usb_dev, NONE, USB_DEVICE_NAME);
+    if (ret != EOK) {
+        KPrintf("USB device register error %d\n", ret);
+        return -ERROR;
+    }
+    ret = USBDeviceAttachToBus(USB_DEVICE_NAME, USB_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("USB device register error %d\n", ret);
+        return -ERROR;
+    }
+#endif
+    return ret;
+}

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch438/Kconfig

@@ -0,0 +1,136 @@
+
+if BSP_USING_CH438
+    config CH438_BUS_NAME
+        string
+        default "extuart"
+
+    config CH438_DRIVER_NAME
+        string
+        default "extuart_drv"
+
+    config CH438_DEVICE_NAME_0
+        string
+        default "extuart_dev0"
+
+    config CH438_DEVICE_NAME_1
+        string
+        default "extuart_dev1"
+
+    config CH438_DEVICE_NAME_2
+        string
+        default "extuart_dev2"
+
+    config CH438_DEVICE_NAME_3
+        string
+        default "extuart_dev3"
+
+    config CH438_DEVICE_NAME_4
+        string
+        default "extuart_dev4"
+
+    config CH438_DEVICE_NAME_5
+        string
+        default "extuart_dev5"
+
+    config CH438_DEVICE_NAME_6
+        string
+        default "extuart_dev6"
+
+    config CH438_DEVICE_NAME_7
+        string
+        default "extuart_dev7"
+
+    config BSP_CH438_ALE_PIN
+        int "ALE pin number for ch438"
+        default 23
+
+    config BSP_CH438_NWR_PIN
+        int "NWR pin number for ch438"
+        default 24
+
+    config BSP_CH438_NRD_PIN
+        int "NRD pin number for ch438"
+        default 25
+        
+    config BSP_CH438_D0_PIN
+        int "D0 pin number for ch438"
+        default 27
+        
+    config BSP_CH438_D1_PIN
+        int "D1 pin number for ch438"
+        default 28
+        
+    config BSP_CH438_D2_PIN
+        int "D2 pin number for ch438"
+        default 29
+        
+    config BSP_CH438_D3_PIN
+        int "D3 pin number for ch438"
+        default 30
+        
+    config BSP_CH438_D4_PIN
+        int "D4 pin number for ch438"
+        default 31
+        
+    config BSP_CH438_D5_PIN
+        int "D5 pin number for ch438"
+        default 32
+        
+    config BSP_CH438_D6_PIN
+        int "D6 pin number for ch438"
+        default 33
+        
+    config BSP_CH438_D7_PIN
+        int "D7 pin number for ch438"
+        default 34
+        
+    config BSP_CH438_INT_PIN
+        int "INT pin number for ch438"
+        default 35
+        
+    config BSP_485_dir
+        int "485 direction pin number for ch438"
+        default 18
+        
+
+    menuconfig BSP_USING_4G_OR_NB
+        bool "Select using the ec200t(4G) or bc28(NB-IOT)"
+        default y
+        if BSP_USING_4G_OR_NB
+            choice
+                prompt "Select using the ec200t(4G) or bc28(NB-IOT)"
+                default BSP_USING_4G
+                config BSP_USING_4G
+                    bool "Using ec200t(4G)"
+                config BSP_USING_NBIOT
+                    bool "Using bc26(NB-IOT)"
+            endchoice
+
+
+            if BSP_USING_4G
+                config BSP_4G_STATUS
+                    int "STATUS pin number for ec200t"
+                    default 21
+                config BSP_4G_POWERKEY
+                    int "POWERKEY pin number for ec200t"
+                    default 37
+            endif
+
+            if BSP_USING_NBIOT
+                config BSP_NB_RESET
+                    int "RESET pin number for bc28"
+                    default 21
+            endif
+        endif
+
+    menuconfig BSP_USING_WIFI_HFA21
+        bool "Using the hfa21(WIFI)"
+        default y
+        if BSP_USING_WIFI_HFA21
+            config BSP_WIFI_RST
+                int "RESET pin number for hfa21"
+                default 22
+        endif
+
+endif
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/ch438/Makefile

@@ -0,0 +1,4 @@
+SRC_FILES := connect_ch438.c
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/dma/Kconfig

@@ -0,0 +1 @@
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/dma/Makefile

@@ -0,0 +1,6 @@
+SRC_FILES := dmac.c
+
+
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/dma/dmac.c

@@ -0,0 +1,802 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file dmac.c
+* @brief add from Canaan K210 SDK
+*               https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#include <dmac.h>
+#include <fpioa.h>
+#include <plic.h>
+#include <stdint.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <sysctl.h>
+#include <utils.h>
+
+volatile dmac_t *const dmac = (dmac_t *)DMAC_BASE_ADDR;
+
+typedef struct _dmac_context
+{
+    dmac_channel_number_t dmac_channel;
+    plic_irq_callback_t callback;
+    void *ctx;
+} dmac_context_t;
+
+dmac_context_t dmac_context[6];
+
+static int is_memory(uintptr_t address)
+{
+    enum {
+        mem_len = 6 * 1024 * 1024,
+        mem_no_cache_len = 8 * 1024 * 1024,
+    };
+    return ((address >= 0x80000000) && (address < 0x80000000 + mem_len)) || ((address >= 0x40000000) && (address < 0x40000000 + mem_no_cache_len)) || (address == 0x50450040);
+}
+
+uint64_t dmac_read_id(void)
+{
+    return dmac->id;
+}
+
+uint64_t dmac_read_version(void)
+{
+    return dmac->compver;
+}
+
+uint64_t dmac_read_channel_id(dmac_channel_number_t channel_num)
+{
+    return dmac->channel[channel_num].axi_id;
+}
+
+static void dmac_enable(void)
+{
+    dmac_cfg_u_t  dmac_cfg;
+
+    dmac_cfg.data = readq(&dmac->cfg);
+    dmac_cfg.cfg.dmac_en = 1;
+    dmac_cfg.cfg.int_en = 1;
+    writeq(dmac_cfg.data, &dmac->cfg);
+}
+
+void dmac_disable(void)
+{
+    dmac_cfg_u_t  dmac_cfg;
+
+    dmac_cfg.data = readq(&dmac->cfg);
+    dmac_cfg.cfg.dmac_en = 0;
+    dmac_cfg.cfg.int_en = 0;
+    writeq(dmac_cfg.data, &dmac->cfg);
+}
+
+void src_transaction_complete_int_enable(dmac_channel_number_t channel_num)
+{
+    dmac_ch_intstatus_enable_u_t  ch_intstat;
+
+    ch_intstat.data = readq(&dmac->channel[channel_num].intstatus_en);
+    ch_intstat.ch_intstatus_enable.enable_src_transcomp_intstat = 1;
+
+    writeq(ch_intstat.data, &dmac->channel[channel_num].intstatus_en);
+}
+
+void dmac_channel_enable(dmac_channel_number_t channel_num)
+{
+    dmac_chen_u_t chen;
+
+    chen.data = readq(&dmac->chen);
+
+    switch (channel_num) {
+    case DMAC_CHANNEL0:
+        chen.dmac_chen.ch1_en = 1;
+        chen.dmac_chen.ch1_en_we = 1;
+        break;
+    case DMAC_CHANNEL1:
+        chen.dmac_chen.ch2_en = 1;
+        chen.dmac_chen.ch2_en_we = 1;
+        break;
+    case DMAC_CHANNEL2:
+        chen.dmac_chen.ch3_en = 1;
+        chen.dmac_chen.ch3_en_we = 1;
+        break;
+    case DMAC_CHANNEL3:
+        chen.dmac_chen.ch4_en = 1;
+        chen.dmac_chen.ch4_en_we = 1;
+        break;
+    case DMAC_CHANNEL4:
+        chen.dmac_chen.ch5_en = 1;
+        chen.dmac_chen.ch5_en_we = 1;
+        break;
+    case DMAC_CHANNEL5:
+        chen.dmac_chen.ch6_en = 1;
+        chen.dmac_chen.ch6_en_we = 1;
+        break;
+    default:
+        break;
+    }
+
+    writeq(chen.data, &dmac->chen);
+}
+
+void dmac_channel_disable(dmac_channel_number_t channel_num)
+{
+    dmac_chen_u_t chen;
+
+    chen.data = readq(&dmac->chen);
+
+    switch (channel_num)
+    {
+    case DMAC_CHANNEL0:
+        chen.dmac_chen.ch1_en = 0;
+        chen.dmac_chen.ch1_en_we = 1;
+        break;
+    case DMAC_CHANNEL1:
+        chen.dmac_chen.ch2_en = 0;
+        chen.dmac_chen.ch2_en_we = 1;
+        break;
+    case DMAC_CHANNEL2:
+        chen.dmac_chen.ch3_en = 0;
+        chen.dmac_chen.ch3_en_we = 1;
+        break;
+    case DMAC_CHANNEL3:
+        chen.dmac_chen.ch4_en = 0;
+        chen.dmac_chen.ch4_en_we = 1;
+        break;
+    case DMAC_CHANNEL4:
+        chen.dmac_chen.ch5_en = 0;
+        chen.dmac_chen.ch5_en_we = 1;
+        break;
+    case DMAC_CHANNEL5:
+        chen.dmac_chen.ch6_en = 0;
+        chen.dmac_chen.ch6_en_we = 1;
+        break;
+    default:
+        break;
+    }
+
+    writeq(chen.data, &dmac->chen);
+}
+
+int32_t dmac_check_channel_busy(dmac_channel_number_t channel_num)
+{
+    int32_t ret = 0;
+    dmac_chen_u_t chen_u;
+
+    chen_u.data = readq(&dmac->chen);
+    switch (channel_num) {
+    case DMAC_CHANNEL0:
+        if (chen_u.dmac_chen.ch1_en == 1)
+            ret = 1;
+        break;
+    case DMAC_CHANNEL1:
+        if (chen_u.dmac_chen.ch2_en == 1)
+            ret = 1;
+        break;
+    case DMAC_CHANNEL2:
+        if (chen_u.dmac_chen.ch3_en == 1)
+            ret = 1;
+        break;
+    case DMAC_CHANNEL3:
+        if (chen_u.dmac_chen.ch4_en == 1)
+            ret = 1;
+        break;
+    case DMAC_CHANNEL4:
+        if (chen_u.dmac_chen.ch5_en == 1)
+            ret = 1;
+        break;
+    case DMAC_CHANNEL5:
+        if (chen_u.dmac_chen.ch6_en == 1)
+            ret = 1;
+        break;
+    default:
+        break;
+    }
+
+    writeq(chen_u.data, &dmac->chen);
+
+    return ret;
+}
+
+int32_t dmac_set_list_master_select(dmac_channel_number_t channel_num,
+    dmac_src_dst_select_t sd_sel, dmac_master_number_t  mst_num)
+{
+    int32_t ret = 0;
+    uint64_t tmp = 0;
+    dmac_ch_ctl_u_t ctl;
+
+    ctl.data = readq(&dmac->channel[channel_num].ctl);
+    ret = dmac_check_channel_busy(channel_num);
+    if (ret == 0) {
+        if (sd_sel == DMAC_SRC || sd_sel == DMAC_SRC_DST)
+            ctl.ch_ctl.sms = mst_num;
+
+        if (sd_sel == DMAC_DST || sd_sel == DMAC_SRC_DST)
+            ctl.ch_ctl.dms = mst_num;
+        tmp |= *(uint64_t *)&dmac->channel[channel_num].ctl;
+        writeq(ctl.data, &dmac->channel[channel_num].ctl);
+    }
+
+    return ret;
+}
+
+void dmac_enable_common_interrupt_status(void)
+{
+    dmac_commonreg_intstatus_enable_u_t intstatus;
+
+    intstatus.data = readq(&dmac->com_intstatus_en);
+    intstatus.intstatus_enable.enable_slvif_dec_err_intstat = 1;
+    intstatus.intstatus_enable.enable_slvif_wr2ro_err_intstat = 1;
+    intstatus.intstatus_enable.enable_slvif_rd2wo_err_intstat = 1;
+    intstatus.intstatus_enable.enable_slvif_wronhold_err_intstat = 1;
+    intstatus.intstatus_enable.enable_slvif_undefinedreg_dec_err_intstat = 1;
+
+    writeq(intstatus.data, &dmac->com_intstatus_en);
+}
+
+void dmac_enable_common_interrupt_signal(void)
+{
+    dmac_commonreg_intsignal_enable_u_t intsignal;
+
+    intsignal.data = readq(&dmac->com_intsignal_en);
+    intsignal.intsignal_enable.enable_slvif_dec_err_intsignal = 1;
+    intsignal.intsignal_enable.enable_slvif_wr2ro_err_intsignal = 1;
+    intsignal.intsignal_enable.enable_slvif_rd2wo_err_intsignal = 1;
+    intsignal.intsignal_enable.enable_slvif_wronhold_err_intsignal = 1;
+    intsignal.intsignal_enable.enable_slvif_undefinedreg_dec_err_intsignal = 1;
+
+    writeq(intsignal.data, &dmac->com_intsignal_en);
+}
+
+static void dmac_enable_channel_interrupt(dmac_channel_number_t channel_num)
+{
+    writeq(0xffffffff, &dmac->channel[channel_num].intclear);
+    writeq(0x2, &dmac->channel[channel_num].intstatus_en);
+}
+
+void dmac_disable_channel_interrupt(dmac_channel_number_t channel_num)
+{
+    writeq(0, &dmac->channel[channel_num].intstatus_en);
+}
+
+static void dmac_chanel_interrupt_clear(dmac_channel_number_t channel_num)
+{
+    writeq(0xffffffff, &dmac->channel[channel_num].intclear);
+}
+
+int dmac_set_channel_config(dmac_channel_number_t channel_num,
+        dmac_channel_config_t *cfg_param)
+{
+    dmac_ch_ctl_u_t  ctl;
+    dmac_ch_cfg_u_t cfg;
+    dmac_ch_llp_u_t ch_llp;
+
+    if (cfg_param->ctl_sms > DMAC_MASTER2)
+        return -1;
+    if (cfg_param->ctl_dms > DMAC_MASTER2)
+        return -1;
+    if (cfg_param->ctl_src_msize > DMAC_MSIZE_256)
+        return -1;
+    if (cfg_param->ctl_drc_msize > DMAC_MSIZE_256)
+        return -1;
+
+    /**
+     * cfg register must configure before ts_block and
+     * sar dar register
+     */
+    cfg.data = readq(&dmac->channel[channel_num].cfg);
+
+    cfg.ch_cfg.hs_sel_src = cfg_param->cfg_hs_sel_src;
+    cfg.ch_cfg.hs_sel_dst = cfg_param->cfg_hs_sel_dst;
+    cfg.ch_cfg.src_hwhs_pol = cfg_param->cfg_src_hs_pol;
+    cfg.ch_cfg.dst_hwhs_pol  = cfg_param->cfg_dst_hs_pol;
+    cfg.ch_cfg.src_per = cfg_param->cfg_src_per;
+    cfg.ch_cfg.dst_per = cfg_param->cfg_dst_per;
+    cfg.ch_cfg.ch_prior = cfg_param->cfg_ch_prior;
+    cfg.ch_cfg.tt_fc = cfg_param->ctl_tt_fc;
+
+    cfg.ch_cfg.src_multblk_type = cfg_param->cfg_src_multblk_type;
+    cfg.ch_cfg.dst_multblk_type = cfg_param->cfg_dst_multblk_type;
+
+    writeq(cfg.data, &dmac->channel[channel_num].cfg);
+
+    ctl.data = readq(&dmac->channel[channel_num].ctl);
+    ctl.ch_ctl.sms = cfg_param->ctl_sms;
+    ctl.ch_ctl.dms = cfg_param->ctl_dms;
+    /* master select */
+    ctl.ch_ctl.sinc = cfg_param->ctl_sinc;
+    ctl.ch_ctl.dinc = cfg_param->ctl_dinc;
+    /* address incrememt */
+    ctl.ch_ctl.src_tr_width = cfg_param->ctl_src_tr_width;
+    ctl.ch_ctl.dst_tr_width  = cfg_param->ctl_dst_tr_width;
+    /* transfer width */
+    ctl.ch_ctl.src_msize = cfg_param->ctl_src_msize;
+    ctl.ch_ctl.dst_msize = cfg_param->ctl_drc_msize;
+    /* Burst transaction length */
+    ctl.ch_ctl.ioc_blktfr = cfg_param->ctl_ioc_blktfr;
+    /* interrupt on completion of block transfer */
+    /* 0x1 enable BLOCK_TFR_DONE_IntStat field */
+
+    writeq(cfg_param->ctl_block_ts, &dmac->channel[channel_num].block_ts);
+    /* the number of (blcok_ts +1) data of width SRC_TR_WIDTF to be */
+    /* transferred in a dma block transfer */
+
+    dmac->channel[channel_num].sar = cfg_param->sar;
+    dmac->channel[channel_num].dar = cfg_param->dar;
+
+    ch_llp.data = readq(&dmac->channel[channel_num].llp);
+    ch_llp.llp.loc = cfg_param->llp_loc;
+    ch_llp.llp.lms = cfg_param->llp_lms;
+    writeq(ch_llp.data, &dmac->channel[channel_num].llp);
+    writeq(ctl.data, &dmac->channel[channel_num].ctl);
+    readq(&dmac->channel[channel_num].swhssrc);
+
+    return 0;
+}
+
+int dmac_set_channel_param(dmac_channel_number_t channel_num,
+    const void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc,
+    dmac_burst_trans_length_t dmac_burst_size,
+    dmac_transfer_width_t dmac_trans_width,
+    uint32_t blockSize)
+{
+    dmac_ch_ctl_u_t  ctl;
+    dmac_ch_cfg_u_t cfg_u;
+
+    int mem_type_src = is_memory((uintptr_t)src), mem_type_dest = is_memory((uintptr_t)dest);
+    dmac_transfer_flow_t flow_control;
+    if (mem_type_src == 0 && mem_type_dest == 0)
+    {
+        flow_control = DMAC_PRF2PRF_DMA;
+    }else if (mem_type_src == 1 && mem_type_dest == 0)
+        flow_control = DMAC_MEM2PRF_DMA;
+    else if (mem_type_src == 0 && mem_type_dest == 1)
+        flow_control = DMAC_PRF2MEM_DMA;
+    else
+        flow_control = DMAC_MEM2MEM_DMA;
+
+    /**
+     * cfg register must configure before ts_block and
+     * sar dar register
+     */
+    cfg_u.data = readq(&dmac->channel[channel_num].cfg);
+
+    cfg_u.ch_cfg.tt_fc = flow_control;
+    cfg_u.ch_cfg.hs_sel_src = mem_type_src ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE;
+    cfg_u.ch_cfg.hs_sel_dst = mem_type_dest ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE;
+    cfg_u.ch_cfg.src_per = channel_num;
+    cfg_u.ch_cfg.dst_per = channel_num;
+    cfg_u.ch_cfg.src_multblk_type = 0;
+    cfg_u.ch_cfg.dst_multblk_type = 0;
+
+    writeq(cfg_u.data, &dmac->channel[channel_num].cfg);
+
+    dmac->channel[channel_num].sar = (uint64_t)src;
+    dmac->channel[channel_num].dar = (uint64_t)dest;
+
+    ctl.data = readq(&dmac->channel[channel_num].ctl);
+    ctl.ch_ctl.sms = DMAC_MASTER1;
+    ctl.ch_ctl.dms = DMAC_MASTER2;
+    /* master select */
+    ctl.ch_ctl.sinc = src_inc;
+    ctl.ch_ctl.dinc = dest_inc;
+    /* address incrememt */
+    ctl.ch_ctl.src_tr_width = dmac_trans_width;
+    ctl.ch_ctl.dst_tr_width  = dmac_trans_width;
+    /* transfer width */
+    ctl.ch_ctl.src_msize = dmac_burst_size;
+    ctl.ch_ctl.dst_msize = dmac_burst_size;
+
+    writeq(ctl.data, &dmac->channel[channel_num].ctl);
+
+    writeq(blockSize - 1, &dmac->channel[channel_num].block_ts);
+    /*the number of (blcok_ts +1) data of width SRC_TR_WIDTF to be */
+    /* transferred in a dma block transfer */
+    return 0;
+}
+
+int dmac_get_channel_config(dmac_channel_number_t channel_num,
+        dmac_channel_config_t *cfg_param)
+{
+    dmac_ch_ctl_u_t  ctl;
+    dmac_ch_cfg_u_t cfg;
+    dmac_ch_llp_u_t ch_llp;
+
+    if (cfg_param == 0)
+        return -1;
+    if (channel_num < DMAC_CHANNEL0 ||
+        channel_num > DMAC_CHANNEL3)
+        return -1;
+
+    ctl.data = readq(&dmac->channel[channel_num].ctl);
+
+    cfg_param->ctl_sms = ctl.ch_ctl.sms;
+    cfg_param->ctl_dms = ctl.ch_ctl.dms;
+    cfg_param->ctl_sinc = ctl.ch_ctl.sinc;
+    cfg_param->ctl_dinc = ctl.ch_ctl.dinc;
+    cfg_param->ctl_src_tr_width = ctl.ch_ctl.src_tr_width;
+    cfg_param->ctl_dst_tr_width = ctl.ch_ctl.dst_tr_width;
+    cfg_param->ctl_src_msize = ctl.ch_ctl.src_msize;
+    cfg_param->ctl_drc_msize = ctl.ch_ctl.dst_msize;
+    cfg_param->ctl_ioc_blktfr = ctl.ch_ctl.ioc_blktfr;
+
+    cfg.data = readq(&dmac->channel[channel_num].cfg);
+    cfg_param->cfg_hs_sel_src = cfg.ch_cfg.hs_sel_src;
+    cfg_param->cfg_hs_sel_dst = cfg.ch_cfg.hs_sel_dst;
+    cfg_param->cfg_src_hs_pol = cfg.ch_cfg.src_hwhs_pol;
+    cfg_param->cfg_dst_hs_pol =  cfg.ch_cfg.dst_hwhs_pol;
+    cfg_param->cfg_src_per = cfg.ch_cfg.src_per;
+    cfg_param->cfg_dst_per = cfg.ch_cfg.dst_per;
+    cfg_param->cfg_ch_prior = cfg.ch_cfg.ch_prior;
+    cfg_param->cfg_src_multblk_type = cfg.ch_cfg.src_multblk_type;
+    cfg_param->cfg_dst_multblk_type = cfg.ch_cfg.dst_multblk_type;
+
+    cfg_param->sar = dmac->channel[channel_num].sar;
+    cfg_param->dar = dmac->channel[channel_num].dar;
+
+    ch_llp.data = readq(&dmac->channel[channel_num].llp);
+    cfg_param->llp_loc = ch_llp.llp.loc;
+    cfg_param->llp_lms = ch_llp.llp.lms;
+
+    cfg_param->ctl_block_ts = readq(&dmac->channel[channel_num].block_ts);
+
+    return 0;
+}
+
+void dmac_set_address(dmac_channel_number_t channel_num, uint64_t src_addr,
+        uint64_t dst_addr)
+{
+    writeq(src_addr, &dmac->channel[channel_num].sar);
+    writeq(dst_addr, &dmac->channel[channel_num].dar);
+}
+
+void dmac_set_block_ts(dmac_channel_number_t channel_num,
+        uint32_t BlockSize)
+{
+    uint32_t block_ts;
+
+    block_ts = BlockSize & 0x3fffff;
+    writeq(block_ts, &dmac->channel[channel_num].block_ts);
+}
+
+void dmac_source_control(dmac_channel_number_t channel_num,
+        dmac_master_number_t master_select,
+        dmac_address_increment_t address_mode,
+        dmac_transfer_width_t tr_width,
+        dmac_burst_trans_length_t burst_length)
+{
+    dmac_ch_ctl_u_t ctl_u;
+
+    ctl_u.data = readq(&dmac->channel[channel_num].ctl);
+    ctl_u.ch_ctl.sms = master_select;
+    ctl_u.ch_ctl.sinc = address_mode;
+    ctl_u.ch_ctl.src_tr_width = tr_width;
+    ctl_u.ch_ctl.src_msize = burst_length;
+
+    writeq(ctl_u.data, &dmac->channel[channel_num].ctl);
+}
+
+void dmac_master_control(dmac_channel_number_t channel_num,
+        dmac_master_number_t master_select,
+        dmac_address_increment_t address_mode,
+        dmac_transfer_width_t tr_width,
+        dmac_burst_trans_length_t burst_length)
+{
+    dmac_ch_ctl_u_t ctl_u;
+
+    ctl_u.data = readq(&dmac->channel[channel_num].ctl);
+    ctl_u.ch_ctl.dms = master_select;
+    ctl_u.ch_ctl.dinc = address_mode;
+    ctl_u.ch_ctl.dst_tr_width = tr_width;
+    ctl_u.ch_ctl.dst_msize = burst_length;
+
+    writeq(ctl_u.data, &dmac->channel[channel_num].ctl);
+}
+
+void dmac_set_source_transfer_control(dmac_channel_number_t channel_num,
+                dmac_multiblk_transfer_type_t transfer_type,
+                dmac_sw_hw_hs_select_t handshak_select)
+{
+    dmac_ch_cfg_u_t cfg_u;
+
+    cfg_u.data = readq(&dmac->channel[channel_num].cfg);
+    cfg_u.ch_cfg.src_multblk_type = transfer_type;
+    cfg_u.ch_cfg.hs_sel_src = handshak_select;
+
+    writeq(cfg_u.data, &dmac->channel[channel_num].cfg);
+}
+
+void dmac_set_destination_transfer_control(dmac_channel_number_t channel_num,
+                dmac_multiblk_transfer_type_t transfer_type,
+                dmac_sw_hw_hs_select_t handshak_select)
+{
+    dmac_ch_cfg_u_t cfg_u;
+
+    cfg_u.data = readq(&dmac->channel[channel_num].cfg);
+    cfg_u.ch_cfg.dst_multblk_type = transfer_type;
+    cfg_u.ch_cfg.hs_sel_dst = handshak_select;
+
+    writeq(cfg_u.data, &dmac->channel[channel_num].cfg);
+}
+
+void dmac_set_flow_control(dmac_channel_number_t channel_num,
+            dmac_transfer_flow_t flow_control)
+{
+    dmac_ch_cfg_u_t cfg_u;
+
+    cfg_u.data = readq(&dmac->channel[channel_num].cfg);
+    cfg_u.ch_cfg.tt_fc = flow_control;
+
+    writeq(cfg_u.data, &dmac->channel[channel_num].cfg);
+}
+
+void dmac_set_linked_list_addr_point(dmac_channel_number_t channel_num,
+            uint64_t *addr)
+{
+    dmac_ch_llp_u_t llp_u;
+
+    llp_u.data = readq(&dmac->channel[channel_num].llp);
+    /* Cast pointer to uint64_t */
+    llp_u.llp.loc = (uint64_t)addr;
+    writeq(llp_u.data, &dmac->channel[channel_num].llp);
+}
+
+void DmacInit(void)
+{
+    uint64_t tmp;
+    dmac_commonreg_intclear_u_t intclear;
+    dmac_cfg_u_t dmac_cfg;
+    dmac_reset_u_t dmac_reset;
+
+    sysctl_clock_enable(SYSCTL_CLOCK_DMA);
+
+    dmac_reset.data = readq(&dmac->reset);
+    dmac_reset.reset.rst = 1;
+    writeq(dmac_reset.data, &dmac->reset);
+    while (dmac_reset.reset.rst)
+        dmac_reset.data = readq(&dmac->reset);
+
+    /*reset dmac */
+
+    intclear.data = readq(&dmac->com_intclear);
+    intclear.com_intclear.cear_slvif_dec_err_intstat = 1;
+    intclear.com_intclear.clear_slvif_wr2ro_err_intstat = 1;
+    intclear.com_intclear.clear_slvif_rd2wo_err_intstat = 1;
+    intclear.com_intclear.clear_slvif_wronhold_err_intstat = 1;
+    intclear.com_intclear.clear_slvif_undefinedreg_dec_err_intstat = 1;
+    writeq(intclear.data, &dmac->com_intclear);
+    /* clear common register interrupt */
+
+    dmac_cfg.data = readq(&dmac->cfg);
+    dmac_cfg.cfg.dmac_en = 0;
+    dmac_cfg.cfg.int_en = 0;
+    writeq(dmac_cfg.data, &dmac->cfg);
+    /* disable dmac and disable interrupt */
+
+    while (readq(&dmac->cfg))
+        ;
+    tmp = readq(&dmac->chen);
+    tmp &= ~0xf;
+    writeq(tmp, &dmac->chen);
+    /* disable all channel before configure */
+    dmac_enable();
+}
+
+static void list_add(struct list_head_t *new, struct list_head_t *prev,
+        struct list_head_t *next)
+{
+    next->prev = new;
+    new->next = next;
+    new->prev = prev;
+    prev->next = new;
+}
+
+void list_add_tail(struct list_head_t *new, struct list_head_t *head)
+{
+    list_add(new, head->prev, head);
+}
+
+void INIT_LIST_HEAD(struct list_head_t *list)
+{
+    list->next = list;
+    list->prev = list;
+}
+
+void dmac_link_list_item(dmac_channel_number_t channel_num,
+    uint8_t LLI_row_num, int8_t LLI_last_row,
+    dmac_lli_item_t *lli_item,
+    dmac_channel_config_t *cfg_param)
+{
+    dmac_ch_ctl_u_t ctl;
+    dmac_ch_llp_u_t  llp_u;
+
+    lli_item[LLI_row_num].sar = cfg_param->sar;
+    lli_item[LLI_row_num].dar = cfg_param->dar;
+
+    ctl.data = readq(&dmac->channel[channel_num].ctl);
+    ctl.ch_ctl.sms = cfg_param->ctl_sms;
+    ctl.ch_ctl.dms = cfg_param->ctl_dms;
+    ctl.ch_ctl.sinc = cfg_param->ctl_sinc;
+    ctl.ch_ctl.dinc = cfg_param->ctl_dinc;
+    ctl.ch_ctl.src_tr_width = cfg_param->ctl_src_tr_width;
+    ctl.ch_ctl.dst_tr_width = cfg_param->ctl_dst_tr_width;
+    ctl.ch_ctl.src_msize = cfg_param->ctl_src_msize;
+    ctl.ch_ctl.dst_msize = cfg_param->ctl_drc_msize;
+    ctl.ch_ctl.src_stat_en = cfg_param->ctl_src_stat_en;
+    ctl.ch_ctl.dst_stat_en = cfg_param->ctl_dst_stat_en;
+
+    if (LLI_last_row != LAST_ROW) {
+        ctl.ch_ctl.shadowreg_or_lli_valid = 1;
+        ctl.ch_ctl.shadowreg_or_lli_last = 0;
+    } else {
+        ctl.ch_ctl.shadowreg_or_lli_valid = 1;
+        ctl.ch_ctl.shadowreg_or_lli_last = 1;
+    }
+
+    lli_item[LLI_row_num].ctl = ctl.data;
+
+    lli_item[LLI_row_num].ch_block_ts = cfg_param->ctl_block_ts;
+    lli_item[LLI_row_num].sstat = 0;
+    lli_item[LLI_row_num].dstat = 0;
+
+    llp_u.data = readq(&dmac->channel[channel_num].llp);
+
+    if (LLI_last_row != LAST_ROW)
+        llp_u.llp.loc = ((uint64_t)&lli_item[LLI_row_num + 1]) >> 6;
+    else
+        llp_u.llp.loc = 0;
+
+    lli_item[LLI_row_num].llp = llp_u.data;
+}
+
+void dmac_update_shandow_register(dmac_channel_number_t channel_num,
+        int8_t last_block, dmac_channel_config_t *cfg_param)
+{
+    dmac_ch_ctl_u_t ctl_u;
+
+    do {
+        ctl_u.data = readq(&dmac->channel[channel_num].ctl);
+    } while (ctl_u.ch_ctl.shadowreg_or_lli_valid);
+
+    writeq(cfg_param->sar, &dmac->channel[channel_num].sar);
+    writeq(cfg_param->dar, &dmac->channel[channel_num].dar);
+    writeq(cfg_param->ctl_block_ts, &dmac->channel[channel_num].block_ts);
+
+    ctl_u.ch_ctl.sms = cfg_param->ctl_sms;
+    ctl_u.ch_ctl.dms = cfg_param->ctl_dms;
+    ctl_u.ch_ctl.sinc = cfg_param->ctl_sinc;
+    ctl_u.ch_ctl.dinc = cfg_param->ctl_dinc;
+    ctl_u.ch_ctl.src_tr_width = cfg_param->ctl_src_tr_width;
+    ctl_u.ch_ctl.dst_tr_width = cfg_param->ctl_dst_tr_width;
+    ctl_u.ch_ctl.src_msize = cfg_param->ctl_src_msize;
+    ctl_u.ch_ctl.dst_msize = cfg_param->ctl_drc_msize;
+    ctl_u.ch_ctl.src_stat_en = cfg_param->ctl_src_stat_en;
+    ctl_u.ch_ctl.dst_stat_en = cfg_param->ctl_dst_stat_en;
+    if (last_block != LAST_ROW)
+    {
+        ctl_u.ch_ctl.shadowreg_or_lli_valid = 1;
+        ctl_u.ch_ctl.shadowreg_or_lli_last = 0;
+    } else {
+        ctl_u.ch_ctl.shadowreg_or_lli_valid = 1;
+        ctl_u.ch_ctl.shadowreg_or_lli_last = 1;
+    }
+
+    writeq(ctl_u.data, &dmac->channel[channel_num].ctl);
+    writeq(0, &dmac->channel[channel_num].blk_tfr);
+}
+
+void dmac_set_shadow_invalid_flag(dmac_channel_number_t channel_num)
+{
+    dmac_ch_ctl_u_t ctl_u;
+
+    ctl_u.data = readq(&dmac->channel[channel_num].ctl);
+    ctl_u.ch_ctl.shadowreg_or_lli_valid = 1;
+    ctl_u.ch_ctl.shadowreg_or_lli_last = 0;
+    writeq(ctl_u.data, &dmac->channel[channel_num].ctl);
+}
+
+void dmac_set_single_mode(dmac_channel_number_t channel_num,
+                          const void *src, void *dest, dmac_address_increment_t src_inc,
+                          dmac_address_increment_t dest_inc,
+                          dmac_burst_trans_length_t dmac_burst_size,
+                          dmac_transfer_width_t dmac_trans_width,
+                          size_t BlockSize) {
+    dmac_chanel_interrupt_clear(channel_num);
+    dmac_channel_disable(channel_num);
+    dmac_wait_idle(channel_num);
+    dmac_set_channel_param(channel_num, src, dest, src_inc, dest_inc,
+                           dmac_burst_size, dmac_trans_width, BlockSize);
+    dmac_enable();
+    dmac_channel_enable(channel_num);
+}
+
+int dmac_is_done(dmac_channel_number_t channel_num)
+{
+    if(readq(&dmac->channel[channel_num].intstatus) & 0x2)
+        return 1;
+    else
+        return 0;
+}
+
+void dmac_wait_done(dmac_channel_number_t channel_num)
+{
+    dmac_wait_idle(channel_num);
+}
+
+int dmac_is_idle(dmac_channel_number_t channel_num)
+{
+    dmac_chen_u_t chen;
+    chen.data = readq(&dmac->chen);
+    if((chen.data >> channel_num) & 0x1UL)
+        return 0;
+    else
+        return 1;
+}
+
+void dmac_wait_idle(dmac_channel_number_t channel_num)
+{
+    while(!dmac_is_idle(channel_num));
+    dmac_chanel_interrupt_clear(channel_num); /* clear interrupt */
+}
+
+void dmac_set_src_dest_length(dmac_channel_number_t channel_num, const void *src, void *dest, size_t len)
+{
+    if(src != NULL)
+        dmac->channel[channel_num].sar = (uint64_t)src;
+    if(dest != NULL)
+        dmac->channel[channel_num].dar = (uint64_t)dest;
+    if(len > 0)
+        dmac_set_block_ts(channel_num, len - 1);
+    dmac_channel_enable(channel_num);
+}
+
+static int dmac_irq_callback(void *ctx)
+{
+    dmac_context_t *v_dmac_context = (dmac_context_t *)(ctx);
+    dmac_channel_number_t v_dmac_channel = v_dmac_context->dmac_channel;
+    dmac_chanel_interrupt_clear(v_dmac_channel);
+    if(v_dmac_context->callback != NULL)
+        v_dmac_context->callback(v_dmac_context->ctx);
+
+    return 0;
+}
+
+void dmac_irq_register(dmac_channel_number_t channel_num , plic_irq_callback_t dmac_callback, void *ctx, uint32_t priority)
+{
+    dmac_context[channel_num].dmac_channel = channel_num;
+    dmac_context[channel_num].callback = dmac_callback;
+    dmac_context[channel_num].ctx = ctx;
+    dmac_enable_channel_interrupt(channel_num);
+    plic_set_priority(IRQN_DMA0_INTERRUPT + channel_num, priority);
+    plic_irq_enable(IRQN_DMA0_INTERRUPT + channel_num);
+    plic_irq_register(IRQN_DMA0_INTERRUPT + channel_num, dmac_irq_callback, &dmac_context[channel_num]);
+}
+
+void __attribute__((weak, alias("dmac_irq_register"))) dmac_set_irq(dmac_channel_number_t channel_num , plic_irq_callback_t dmac_callback, void *ctx, uint32_t priority);
+
+void dmac_irq_unregister(dmac_channel_number_t channel_num)
+{
+    dmac_context[channel_num].callback = NULL;
+    dmac_context[channel_num].ctx = NULL;
+    dmac_disable_channel_interrupt(channel_num);
+    plic_irq_unregister(IRQN_DMA0_INTERRUPT + channel_num);
+}
+
+void __attribute__((weak, alias("dmac_irq_unregister"))) dmac_free_irq(dmac_channel_number_t channel_num);
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/gpio/Kconfig

@@ -0,0 +1,11 @@
+config PIN_BUS_NAME
+    string "pin bus name"
+    default "pin"
+
+config PIN_DRIVER_NAME
+    string "pin driver name"
+    default "pin_drv"
+
+config PIN_DEVICE_NAME
+    string "pin device name"
+    default "pin_dev"

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/gpio/Makefile

@@ -0,0 +1,8 @@
+SRC_FILES := connect_gpio.c drv_io_config.c fpioa.c gpio.c gpiohs.c utils.c
+
+
+
+
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/gpio/connect_gpio.c

@@ -0,0 +1,329 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-19     ZYH          first version
+ */
+
+/**
+* @file connect_gpio.c
+* @brief support gpio function using bus driver framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: connect_gpio.c
+Description: support  gpio configure and register to bus framework
+Others: take RT-Thread v4.0.2/bsp/k210/driver/drv_gpio.c for references
+                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: add bus driver framework support for gpio
+*************************************************/
+
+#include <connect_gpio.h>
+#include <drv_io_config.h>
+#include <fpioa.h>
+#include <gpiohs.h>
+#include <plic.h>
+#include <utils.h>
+
+#define FUNC_GPIOHS(n) (FUNC_GPIOHS0 + n)
+
+static int pin_alloc_table[FPIOA_NUM_IO];
+static uint32_t free_pin = 0;
+
+static int AllocPinChannel(x_base pin_index)
+{
+    if (free_pin == 31) {
+        SYS_ERR("no free gpiohs channel to alloc");
+        return -1;
+    }
+
+    if (pin_alloc_table[pin_index] != -1) {
+        SYS_WARN("already alloc gpiohs channel for pin %d", pin_index);
+        return pin_alloc_table[pin_index];
+    }
+
+    pin_alloc_table[pin_index] = free_pin;
+    free_pin++;
+
+    FpioaSetFunction(pin_index, FUNC_GPIOHS(pin_alloc_table[pin_index]));
+    return pin_alloc_table[pin_index];
+}
+
+static int GetPinChannel(x_base pin_index)
+{
+    return pin_alloc_table[pin_index];
+}
+
+static uint32 GpioConfigMode(int mode, uint8_t pin_channel)
+{
+    switch (mode)
+    {
+        case GPIO_CFG_OUTPUT:
+            gpiohs_set_drive_mode(pin_channel, GPIO_DM_OUTPUT);
+            break;
+        case GPIO_CFG_INPUT:
+            gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT);
+            break;
+        case GPIO_CFG_INPUT_PULLUP:
+            gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT_PULL_UP);
+            break;
+        case GPIO_CFG_INPUT_PULLDOWN:
+            gpiohs_set_drive_mode(pin_channel, GPIO_DM_INPUT_PULL_DOWN);
+            break;
+        case GPIO_CFG_OUTPUT_OD:
+            break;
+        default:
+            break;
+    }
+    return EOK;
+
+}
+
+static struct 
+{
+    void (*hdr) (void *args);
+    void *args;
+    GpioPinEdgeT edge;
+} IrqTable[32];
+
+static void pin_irq(int vector, void *param)
+{
+    int pin_channel = vector - IRQN_GPIOHS0_INTERRUPT;
+    if (IrqTable[pin_channel].edge &GPIO_PE_FALLING) {
+        set_gpio_bit(gpiohs->fall_ie.u32, pin_channel, 0);
+        set_gpio_bit(gpiohs->fall_ip.u32, pin_channel, 1);
+        set_gpio_bit(gpiohs->fall_ie.u32, pin_channel, 1);
+    }
+
+    if (IrqTable[pin_channel].edge &GPIO_PE_RISING) {
+        set_gpio_bit(gpiohs->rise_ie.u32, pin_channel, 0);
+        set_gpio_bit(gpiohs->rise_ip.u32, pin_channel, 1);
+        set_gpio_bit(gpiohs->rise_ie.u32, pin_channel, 1);
+    }
+
+    if (IrqTable[pin_channel].edge &GPIO_PE_LOW) {
+        set_gpio_bit(gpiohs->low_ie.u32, pin_channel, 0);
+        set_gpio_bit(gpiohs->low_ip.u32, pin_channel, 1);
+        set_gpio_bit(gpiohs->low_ie.u32, pin_channel, 1);
+    }
+
+    if (IrqTable[pin_channel].edge &GPIO_PE_HIGH) {
+        set_gpio_bit(gpiohs->high_ie.u32, pin_channel, 0);
+        set_gpio_bit(gpiohs->high_ip.u32, pin_channel, 1);
+        set_gpio_bit(gpiohs->high_ie.u32, pin_channel, 1);
+    }
+
+    if (IrqTable[pin_channel].hdr) {
+        IrqTable[pin_channel].hdr(IrqTable[pin_channel].args);
+    }
+}
+
+static uint32 GpioIrqRegister(int32 pin_channel, int32 mode, void (*hdr)(void *args), void *args)
+{
+    IrqTable[pin_channel].hdr = hdr;
+    IrqTable[pin_channel].args = args;
+    switch (mode)
+    {
+        case GPIO_IRQ_EDGE_RISING:
+            IrqTable[pin_channel].edge = GPIO_PE_RISING;
+            break;
+        case GPIO_IRQ_EDGE_FALLING:
+            IrqTable[pin_channel].edge = GPIO_PE_FALLING;
+            break;
+        case GPIO_IRQ_EDGE_BOTH:
+            IrqTable[pin_channel].edge = GPIO_PE_BOTH;
+            break;
+        case GPIO_IRQ_LEVEL_HIGH:
+            IrqTable[pin_channel].edge = GPIO_PE_LOW;
+            break;
+        case GPIO_IRQ_LEVEL_LOW:
+            IrqTable[pin_channel].edge = GPIO_PE_HIGH;
+            break;
+        default:
+            break;
+    }
+    gpiohs_set_pin_edge(pin_channel, IrqTable[pin_channel].edge);
+
+    isrManager.done->registerIrq(IRQN_GPIOHS0_INTERRUPT + pin_channel, pin_irq, NONE);
+ 
+    return EOK;
+}
+
+static uint32 GpioIrqFree(int32 pin_channel)
+{
+    IrqTable[pin_channel].hdr = NONE;
+    IrqTable[pin_channel].args = NONE;
+    return EOK;
+}
+
+static uint32 GpioIrqEnable(int32 pin_channel)
+{
+    isrManager.done->enableIrq(IRQN_GPIOHS0_INTERRUPT + pin_channel);
+    
+    return EOK;
+}
+
+static uint32 GpioIrqDisable(int32 pin_channel)
+{
+     isrManager.done->disableIrq(IRQN_GPIOHS0_INTERRUPT + pin_channel);
+     return EOK;
+}
+
+static uint32 PinConfigure(struct PinParam *param)
+{
+    NULL_PARAM_CHECK(param);
+    int ret = EOK;
+
+    int pin_channel = GetPinChannel(param->pin);
+    if (pin_channel == -1) {
+        pin_channel = AllocPinChannel(param->pin);
+        if (pin_channel == -1) {
+            return ERROR;
+        }
+    }
+
+    switch (param->cmd)
+    {
+        case GPIO_CONFIG_MODE:
+            GpioConfigMode(param->mode, pin_channel);
+            break;
+        case GPIO_IRQ_REGISTER:
+            ret = GpioIrqRegister(pin_channel,param->irq_set.irq_mode,param->irq_set.hdr,param->irq_set.args);
+            break;
+        case GPIO_IRQ_FREE:
+            ret = GpioIrqFree(pin_channel);
+            break;
+        case GPIO_IRQ_ENABLE:
+            ret = GpioIrqEnable(pin_channel);
+            break;
+        case GPIO_IRQ_DISABLE:
+            ret = GpioIrqDisable(pin_channel);
+            break;
+        default:
+            ret = EINVALED;
+            break;
+    }
+
+    return ret;
+}
+
+static uint32 GpioDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+    struct PinParam *param;
+
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_CFG:
+            param = (struct PinParam *)configure_info->private_data;
+            ret = PinConfigure(param);
+            break;
+        default:
+            break;
+    }
+
+    return ret;
+}
+
+uint32 PinWrite(void *dev, struct BusBlockWriteParam *write_param)
+{
+    NULL_PARAM_CHECK(write_param);
+    struct PinStat *pinstat = (struct PinStat *)write_param->buffer;
+
+    int pin_channel = GetPinChannel(pinstat->pin);
+    if (pin_channel == -1) {
+        SYS_ERR("pin %d not set mode", pinstat->pin);
+        return ERROR;
+    }
+
+    gpiohs_set_pin(pin_channel, pinstat->val == GPIO_HIGH ? GPIO_PV_HIGH : GPIO_PV_LOW);
+}
+
+uint32 PinRead(void *dev, struct BusBlockReadParam *read_param)
+{
+    NULL_PARAM_CHECK(dev);
+    NULL_PARAM_CHECK(read_param);
+    struct PinStat *pinstat = (struct PinStat *)read_param->buffer;
+
+    int pin_channel = GetPinChannel(pinstat->pin);
+    if (pin_channel == -1) {
+        SYS_ERR("pin %d not set mode", pinstat->pin);
+        return ERROR;
+    }
+
+    if (gpiohs_get_pin(pin_channel) == GPIO_PV_HIGH){
+        pinstat->val = GPIO_HIGH;
+        return GPIO_HIGH;
+    } else {
+        pinstat->val = GPIO_LOW;
+        return GPIO_LOW;
+    }
+}
+
+static const struct PinDevDone dev_done =
+{
+    .open  = NONE,
+    .close = NONE,
+    .write = PinWrite,
+    .read  = PinRead,
+};
+
+int HwGpioInit(void)
+{
+    x_err_t ret = EOK;
+
+    static struct PinBus pin;
+
+    memset(pin_alloc_table, -1, sizeof pin_alloc_table);
+    free_pin = GPIO_ALLOC_START;
+
+    ret = PinBusInit(&pin, PIN_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("gpio bus init error %d\n", ret);
+        return ERROR;
+    }
+
+    static struct PinDriver drv;
+    drv.configure = &GpioDrvConfigure;
+    
+    ret = PinDriverInit(&drv, PIN_DRIVER_NAME, NONE);
+    if (ret != EOK) {
+        KPrintf("pin driver init error %d\n", ret);
+        return ERROR;
+    }
+
+    ret = PinDriverAttachToBus(PIN_DRIVER_NAME, PIN_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("pin driver attach error %d\n", ret);
+        return ERROR;
+    }
+
+    static struct PinHardwareDevice dev;
+    dev.dev_done = &dev_done;
+
+    ret = PinDeviceRegister(&dev, NONE, PIN_DEVICE_NAME);
+    if (ret != EOK) {
+        KPrintf("pin device register error %d\n", ret);
+        return ERROR;
+    }
+
+    ret = PinDeviceAttachToBus(PIN_DEVICE_NAME, PIN_BUS_NAME);
+    if (ret != EOK) {
+        KPrintf("pin device register error %d\n", ret);
+        return ERROR;
+    }
+
+    return ret;
+}

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/gpio/drv_io_config.c

@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-19     ZYH          first version
+ */
+
+/**
+* @file drv_io_config.c
+* @brief support aiit-riscv64-board io configure
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: drv_io_config.c
+Description: support aiit-riscv64-board io configure
+Others: take RT-Thread v4.0.2/bsp/k210/driver/drv_io_config.c for references
+                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: support aiit-riscv64-board io configure
+*************************************************/
+
+#include <xizi.h>
+#include <fpioa.h>
+#include <drv_io_config.h>
+#include <sysctl.h>
+
+#define HS_GPIO(n) (FUNC_GPIOHS0 + n)
+
+#define IOCONFIG(pin,func)  {pin, func, #func}
+
+static struct io_config
+{
+    int io_num;
+    fpioa_function_t func;
+    const char * FuncName;
+} io_config[] = 
+{
+#ifdef BSP_USING_LCD
+    IOCONFIG(BSP_LCD_CS_PIN, FUNC_SPI0_SS0),                                        /* LCD CS PIN */
+    IOCONFIG(BSP_LCD_WR_PIN, FUNC_SPI0_SCLK),                                   /* LCD WR PIN */
+    IOCONFIG(BSP_LCD_DC_PIN, HS_GPIO(FPIOA_LCD_DC)),                   /* LCD DC PIN */
+    IOCONFIG(BSP_LCD_BL_PIN, HS_GPIO(FPIOA_LCD_BL)),                   /* LCD BackLight PIN */
+#endif
+
+#ifdef BSP_USING_CAMERA
+    IOCONFIG(BSP_CAMERA_SCCB_SDA_PIN, FUNC_SCCB_SDA),
+    IOCONFIG(BSP_CAMERA_SCCB_SCLK_PIN, FUNC_SCCB_SCLK),
+    IOCONFIG(BSP_CAMERA_CMOS_RST_PIN, FUNC_CMOS_RST),
+    IOCONFIG(BSP_CAMERA_CMOS_VSYNC_PIN, FUNC_CMOS_VSYNC),
+    IOCONFIG(BSP_CAMERA_CMOS_PWDN_PIN, FUNC_CMOS_PWDN),
+    IOCONFIG(BSP_CAMERA_CMOS_XCLK_PIN, FUNC_CMOS_XCLK),
+    IOCONFIG(BSP_CAMERA_CMOS_PCLK_PIN, FUNC_CMOS_PCLK),
+    IOCONFIG(BSP_CAMERA_CMOS_HREF_PIN, FUNC_CMOS_HREF),
+#endif
+
+#ifdef BSP_USING_SPI1
+    IOCONFIG(BSP_SPI1_CLK_PIN, FUNC_SPI1_SCLK),
+    IOCONFIG(BSP_SPI1_D0_PIN, FUNC_SPI1_D0),
+    IOCONFIG(BSP_SPI1_D1_PIN, FUNC_SPI1_D1),
+#ifdef BSP_USING_SPI1_AS_QSPI
+    IOCONFIG(BSP_SPI1_D2_PIN, FUNC_SPI1_D2),
+    IOCONFIG(BSP_SPI1_D3_PIN, FUNC_SPI1_D3),
+#endif
+#ifdef BSP_SPI1_USING_SS0
+    IOCONFIG(BSP_SPI1_SS0_PIN, HS_GPIO(SPI1_CS0_PIN)),
+#endif
+#ifdef BSP_SPI1_USING_SS1
+    IOCONFIG(BSP_SPI1_SS1_PIN, HS_GPIO(SPI1_CS1_PIN)),
+#endif
+#ifdef BSP_SPI1_USING_SS2
+    IOCONFIG(BSP_SPI1_SS2_PIN, HS_GPIO(SPI1_CS2_PIN)),
+#endif
+#ifdef BSP_SPI1_USING_SS3
+    IOCONFIG(BSP_SPI1_SS3_PIN, HS_GPIO(SPI1_CS3_PIN)),
+#endif
+#endif
+
+
+    IOCONFIG(BSP_UART2_TXD_PIN, FUNC_UART2_TX),      /* uart2.txd */
+    IOCONFIG(BSP_UART2_RXD_PIN, FUNC_UART2_RX),      /* uart2.rxd */
+   
+    IOCONFIG(15, FUNC_GPIO3),
+    IOCONFIG(17, FUNC_GPIO4),
+};
+
+static int PrintIoConfig()
+{
+    int i;
+    // KPrintf("IO Configuration Table\n");
+    // KPrintf("┌───────┬────────────────────────┐\n");
+    // KPrintf("│Pin    │Function                │\n");
+    // KPrintf("├───────┼────────────────────────┤\n");
+    // for(i = 0; i < sizeof io_config / sizeof io_config[0]; i++)
+    // {
+    //     KPrintf("│%-2d     │%-24.24s│\n", io_config[i].io_num, io_config[i].FuncName);
+    // }
+    // KPrintf("└───────┴────────────────────────┘\n");
+    KPrintf("IO Configuration Table\n");
+    KPrintf("----------------------------------\n");
+    KPrintf("|Pin    |Function                |\n");
+    KPrintf("|-------|------------------------|\n");
+    for(i = 0; i < sizeof io_config / sizeof io_config[0]; i++)
+    {
+        KPrintf("|%-2d     |%-24.24s|\n", io_config[i].io_num, io_config[i].FuncName);
+    }
+    KPrintf("---------------------------------\n");
+    return 0;
+}
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),
+                                                io,PrintIoConfig,print io config);
+
+int IoConfigInit(void)
+{
+    int count = sizeof(io_config) / sizeof(io_config[0]);
+    int i;
+    int ret = 0;
+
+    // sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V18);
+    // sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V18);
+    // sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V18);
+    sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V33);
+    sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V33);
+    sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V33);
+    sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V33);
+    sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V33);
+    sysctl_set_power_mode(SYSCTL_POWER_BANK5, SYSCTL_POWER_V33);
+    sysctl_set_power_mode(SYSCTL_POWER_BANK6, SYSCTL_POWER_V33);
+    sysctl_set_power_mode(SYSCTL_POWER_BANK7, SYSCTL_POWER_V33);
+    
+    for(i = 0; i < count; i++)
+    {
+        ret = FpioaSetFunction(io_config[i].io_num, io_config[i].func);
+        if(ret != 0)
+            return ret;
+    }
+
+#if defined(BSP_USING_CAMERA) || defined(BSP_USING_LCD)
+    sysctl_set_spi0_dvp_data(1);
+#endif
+
+    return ret;
+}
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/gpio/gpio.c

@@ -0,0 +1,89 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file gpio.c
+* @brief add from Canaan K210 SDK
+*               https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#include <fpioa.h>
+#include <gpio.h>
+#include <sysctl.h>
+#include <utils.h>
+#define GPIO_MAX_PINNO 8
+
+volatile gpio_t* const gpio = (volatile gpio_t*)GPIO_BASE_ADDR;
+
+int gpio_init(void)
+{
+    return sysctl_clock_enable(SYSCTL_CLOCK_GPIO);
+}
+
+void gpio_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode)
+{
+    configASSERT(pin < GPIO_MAX_PINNO);
+    int io_number = fpioa_get_io_by_function(FUNC_GPIO0 + pin);
+    configASSERT(io_number >= 0);
+
+    fpioa_pull_t pull;
+    uint32_t dir;
+
+    switch (mode)
+    {
+    case GPIO_DM_INPUT:
+        pull = FPIOA_PULL_NONE;
+        dir = 0;
+        break;
+    case GPIO_DM_INPUT_PULL_DOWN:
+        pull = FPIOA_PULL_DOWN;
+        dir = 0;
+        break;
+    case GPIO_DM_INPUT_PULL_UP:
+        pull = FPIOA_PULL_UP;
+        dir = 0;
+        break;
+    case GPIO_DM_OUTPUT:
+        pull = FPIOA_PULL_DOWN;
+        dir = 1;
+        break;
+    default:
+        configASSERT(!"GPIO drive mode is not supported.") break;
+    }
+
+    fpioa_set_io_pull(io_number, pull);
+    set_gpio_bit(gpio->direction.u32, pin, dir);
+}
+
+gpio_pin_value_t gpio_get_pin(uint8_t pin)
+{
+    configASSERT(pin < GPIO_MAX_PINNO);
+    uint32_t dir = get_gpio_bit(gpio->direction.u32, pin);
+    volatile uint32_t *reg = dir ? gpio->data_output.u32 : gpio->data_input.u32;
+    return get_gpio_bit(reg, pin);
+}
+
+void gpio_set_pin(uint8_t pin, gpio_pin_value_t value)
+{
+    configASSERT(pin < GPIO_MAX_PINNO);
+    uint32_t dir = get_gpio_bit(gpio->direction.u32, pin);
+    volatile uint32_t *reg = dir ? gpio->data_output.u32 : gpio->data_input.u32;
+    configASSERT(dir == 1);
+    set_gpio_bit(reg, pin, value);
+}
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/gpio/gpiohs.c

@@ -0,0 +1,228 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file gpiohs.c
+* @brief add from Canaan K210 SDK
+*               https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#include <fpioa.h>
+#include <gpiohs.h>
+#include <sysctl.h>
+#include <utils.h>
+#define GPIOHS_MAX_PINNO 32
+
+volatile gpiohs_t* const gpiohs = (volatile gpiohs_t*)GPIOHS_BASE_ADDR;
+
+typedef struct _gpiohs_pin_instance
+{
+    size_t pin;
+    GpioPinEdgeT edge;
+    void (*callback)();
+    plic_irq_callback_t gpiohs_callback;
+    void *context;
+} gpiohs_pin_instance_t;
+
+static gpiohs_pin_instance_t pin_instance[32];
+
+void gpiohs_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode)
+{
+    configASSERT(pin < GPIOHS_MAX_PINNO);
+    int io_number = fpioa_get_io_by_function(FUNC_GPIOHS0 + pin);
+    configASSERT(io_number >= 0);
+
+    fpioa_pull_t pull;
+    uint32_t dir;
+
+    switch (mode)
+    {
+    case GPIO_DM_INPUT:
+        pull = FPIOA_PULL_NONE;
+        dir = 0;
+        break;
+    case GPIO_DM_INPUT_PULL_DOWN:
+        pull = FPIOA_PULL_DOWN;
+        dir = 0;
+        break;
+    case GPIO_DM_INPUT_PULL_UP:
+        pull = FPIOA_PULL_UP;
+        dir = 0;
+        break;
+    case GPIO_DM_OUTPUT:
+        pull = FPIOA_PULL_DOWN;
+        dir = 1;
+        break;
+    default:
+        configASSERT(!"GPIO drive mode is not supported.") break;
+    }
+
+    fpioa_set_io_pull(io_number, pull);
+    volatile uint32_t *reg = dir ? gpiohs->output_en.u32 : gpiohs->input_en.u32;
+    volatile uint32_t *reg_d = !dir ? gpiohs->output_en.u32 : gpiohs->input_en.u32;
+    set_gpio_bit(reg_d, pin, 0);
+    set_gpio_bit(reg, pin, 1);
+}
+
+gpio_pin_value_t gpiohs_get_pin(uint8_t pin)
+{
+    configASSERT(pin < GPIOHS_MAX_PINNO);
+    return get_gpio_bit(gpiohs->input_val.u32, pin);
+}
+
+void gpiohs_set_pin(uint8_t pin, gpio_pin_value_t value)
+{
+    configASSERT(pin < GPIOHS_MAX_PINNO);
+    set_gpio_bit(gpiohs->output_val.u32, pin, value);
+}
+
+void gpiohs_set_pin_edge(uint8_t pin, GpioPinEdgeT edge)
+{
+    set_gpio_bit(gpiohs->rise_ie.u32, pin, 0);
+    set_gpio_bit(gpiohs->rise_ip.u32, pin, 1);
+
+    set_gpio_bit(gpiohs->fall_ie.u32, pin, 0);
+    set_gpio_bit(gpiohs->fall_ip.u32, pin, 1);
+
+    set_gpio_bit(gpiohs->low_ie.u32, pin, 0);
+    set_gpio_bit(gpiohs->low_ip.u32, pin, 1);
+
+    set_gpio_bit(gpiohs->high_ie.u32, pin, 0);
+    set_gpio_bit(gpiohs->high_ip.u32, pin, 1);
+
+    if(edge & GPIO_PE_FALLING)
+    {
+        set_gpio_bit(gpiohs->fall_ie.u32, pin, 1);
+    }
+    else
+    {
+        set_gpio_bit(gpiohs->fall_ie.u32, pin, 0);
+    }
+
+    if(edge & GPIO_PE_RISING)
+    {
+        set_gpio_bit(gpiohs->rise_ie.u32, pin, 1);
+    }
+    else
+    {
+        set_gpio_bit(gpiohs->rise_ie.u32, pin, 0);
+    }
+
+    if(edge & GPIO_PE_LOW)
+    {
+        set_gpio_bit(gpiohs->low_ie.u32, pin, 1);
+    }
+    else
+    {
+        set_gpio_bit(gpiohs->low_ie.u32, pin, 0);
+    }
+
+    if(edge & GPIO_PE_HIGH)
+    {
+        set_gpio_bit(gpiohs->high_ie.u32, pin, 1);
+    }
+    else
+    {
+        set_gpio_bit(gpiohs->high_ie.u32, pin, 0);
+    }
+
+    pin_instance[pin].edge = edge;
+}
+
+int gpiohs_pin_onchange_isr(void *userdata)
+{
+    gpiohs_pin_instance_t *ctx = (gpiohs_pin_instance_t *)userdata;
+    size_t pin = ctx->pin;
+
+    if(ctx->edge & GPIO_PE_FALLING)
+    {
+        set_gpio_bit(gpiohs->fall_ie.u32, pin, 0);
+        set_gpio_bit(gpiohs->fall_ip.u32, pin, 1);
+        set_gpio_bit(gpiohs->fall_ie.u32, pin, 1);
+    }
+
+    if(ctx->edge & GPIO_PE_RISING)
+    {
+        set_gpio_bit(gpiohs->rise_ie.u32, pin, 0);
+        set_gpio_bit(gpiohs->rise_ip.u32, pin, 1);
+        set_gpio_bit(gpiohs->rise_ie.u32, pin, 1);
+    }
+
+    if(ctx->edge & GPIO_PE_LOW)
+    {
+        set_gpio_bit(gpiohs->low_ie.u32, pin, 0);
+        set_gpio_bit(gpiohs->low_ip.u32, pin, 1);
+        set_gpio_bit(gpiohs->low_ie.u32, pin, 1);
+    }
+
+    if(ctx->edge & GPIO_PE_HIGH)
+    {
+        set_gpio_bit(gpiohs->high_ie.u32, pin, 0);
+        set_gpio_bit(gpiohs->high_ip.u32, pin, 1);
+        set_gpio_bit(gpiohs->high_ie.u32, pin, 1);
+    }
+
+    if (ctx->callback)
+        ctx->callback();
+    if(ctx->gpiohs_callback)
+        ctx->gpiohs_callback(ctx->context);
+
+    return 0;
+}
+
+void gpiohs_set_irq(uint8_t pin, uint32_t priority, void (*func)())
+{
+
+    pin_instance[pin].pin = pin;
+    pin_instance[pin].callback = func;
+
+    plic_set_priority(IRQN_GPIOHS0_INTERRUPT + pin, priority);
+    plic_irq_register(IRQN_GPIOHS0_INTERRUPT + pin, gpiohs_pin_onchange_isr, &(pin_instance[pin]));
+    plic_irq_enable(IRQN_GPIOHS0_INTERRUPT + pin);
+}
+
+void gpiohs_irq_register(uint8_t pin, uint32_t priority, plic_irq_callback_t callback, void *ctx)
+{
+    pin_instance[pin].pin = pin;
+    pin_instance[pin].gpiohs_callback = callback;
+    pin_instance[pin].context = ctx;
+
+    plic_set_priority(IRQN_GPIOHS0_INTERRUPT + pin, priority);
+    plic_irq_register(IRQN_GPIOHS0_INTERRUPT + pin, gpiohs_pin_onchange_isr, &(pin_instance[pin]));
+    plic_irq_enable(IRQN_GPIOHS0_INTERRUPT + pin);
+}
+
+void gpiohs_irq_unregister(uint8_t pin)
+{
+    pin_instance[pin] = (gpiohs_pin_instance_t){
+        .callback = NULL,
+        .gpiohs_callback = NULL,
+        .context = NULL,
+    };
+    set_gpio_bit(gpiohs->rise_ie.u32, pin, 0);
+    set_gpio_bit(gpiohs->fall_ie.u32, pin, 0);
+    set_gpio_bit(gpiohs->low_ie.u32, pin, 0);
+    set_gpio_bit(gpiohs->high_ie.u32, pin, 0);
+    plic_irq_unregister(IRQN_GPIOHS0_INTERRUPT + pin);
+}
+
+void gpiohs_irq_disable(size_t pin)
+{
+    plic_irq_disable(IRQN_GPIOHS0_INTERRUPT + pin);
+}
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/gpio/utils.c

@@ -0,0 +1,54 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file utils.c
+* @brief add from Canaan K210 SDK
+*               https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#include <encoding.h>
+#include <stddef.h>
+#include <utils.h>
+
+void set_bit(volatile uint32_t *bits, uint32_t mask, uint32_t value)
+{
+    uint32_t org = (*bits) & ~mask;
+    *bits = org | (value & mask);
+}
+
+void set_bit_offset(volatile uint32_t *bits, uint32_t mask, size_t offset, uint32_t value)
+{
+    set_bit(bits, mask << offset, value << offset);
+}
+
+void set_gpio_bit(volatile uint32_t *bits, size_t offset, uint32_t value)
+{
+    set_bit_offset(bits, 1, offset, value);
+}
+
+uint32_t get_bit(volatile uint32_t *bits, uint32_t mask, size_t offset)
+{
+    return ((*bits) & (mask << offset)) >> offset;
+}
+
+uint32_t get_gpio_bit(volatile uint32_t *bits, size_t offset)
+{
+    return get_bit(bits, 1, offset);
+}
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/i2c/Kconfig

@@ -0,0 +1,17 @@
+if BSP_USING_I2C
+    config BSP_I2C_SDA
+        int "SDA pin number for I2C"
+        default 15
+    config BSP_I2C_SCL
+        int "SCLK pin number for I2C"
+        default 17
+    config I2C_BUS_NAME_1
+        string "i2c bus 1 name"
+        default "i2c1"
+    config I2C_DRV_NAME_1
+        string "i2c bus 1 driver name"
+        default "i2c1_drv"
+    config I2C_1_DEVICE_NAME_0
+            string "i2c bus 1 device 0 name"
+            default "i2c1_dev0"     
+endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/i2c/Makefile

@@ -0,0 +1,6 @@
+SRC_FILES := hardware_i2c.c  connect_i2c.c
+
+
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/i2c/connect_i2c.c

@@ -0,0 +1,645 @@
+/*
+ * Copyright (c) 2020 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2012-04-25     weety         first version
+ */
+
+/**
+* @file connect_i2c.c
+* @brief support aiit-riscv64-board i2c function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: connect_i2c.c
+Description: support aiit-riscv64-board i2c configure and i2c bus register function
+Others: take RT-Thread v4.0.2/components/drivers/i2c/i2c-bit-ops.c for references
+                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support aiit-riscv64-board i2c bit configure, write and read
+2. support aiit-riscv64-board i2c bus device and driver register
+*************************************************/
+
+#include <board.h>
+#include <connect_i2c.h>
+#include <fpioa.h>
+#include <gpio_common.h>
+#include <gpio.h>
+#include <sleep.h>
+#include <sysctl.h>
+
+#ifndef BSP_USING_I2C1
+#define BSP_USING_I2C1
+#endif
+
+#define I2C_SDA_FUNC_GPIO 3
+#define I2C_SCL_FUNC_GPIO 4
+
+static I2cBusParam i2c_bus_param =
+{
+    I2C_SDA_FUNC_GPIO,
+    I2C_SCL_FUNC_GPIO,
+};
+
+#define SET_SDA(done, val)   done->SetSdaState(done->data, val)
+#define SET_SCL(done, val)   done->SetSclState(done->data, val)
+#define GET_SDA(done)          done->GetSdaState(done->data)
+#define GET_SCL(done)           done->GetSclState(done->data)
+#define SdaLow(done)             SET_SDA(done, 0)
+#define SdaHigh(done)            SET_SDA(done, 1)
+#define SclLow(done)               SET_SCL(done, 0)
+
+void I2cGpioInit(const I2cBusParam *bus_param)
+{
+    gpio_init ();
+    FpioaSetFunction(BSP_I2C_SDA , FUNC_GPIO3 );//RISC-V FPIOA CFG
+    FpioaSetFunction(BSP_I2C_SCL , FUNC_GPIO4 );//RISC-V FPIOA CFG
+    gpio_set_drive_mode(bus_param->i2c_sda_pin , GPIO_DM_OUTPUT );
+    gpio_set_drive_mode(bus_param->i2c_scl_pin, GPIO_DM_OUTPUT );
+    gpio_set_pin(bus_param->i2c_sda_pin , GPIO_PV_HIGH );
+    gpio_set_pin(bus_param->i2c_scl_pin , GPIO_PV_HIGH );    
+}
+
+static void SetSdaState(void *data, uint8 sda_state)
+{
+    I2cBusParam *bus_param = (I2cBusParam *)data;
+    if (sda_state) {
+       gpio_set_drive_mode(bus_param->i2c_sda_pin, GPIO_DM_OUTPUT );
+       gpio_set_pin(bus_param->i2c_sda_pin , GPIO_PV_HIGH );  
+    } else {
+       gpio_set_drive_mode(bus_param->i2c_sda_pin, GPIO_DM_OUTPUT );
+       gpio_set_pin(bus_param->i2c_sda_pin , GPIO_PV_LOW );  
+    }
+}
+
+static void SetSclState(void *data, uint8 scl_state)
+{
+    I2cBusParam *bus_param = (I2cBusParam *)data;
+    if (scl_state) {
+        gpio_set_drive_mode(bus_param->i2c_scl_pin, GPIO_DM_OUTPUT );
+        gpio_set_pin(bus_param->i2c_scl_pin , GPIO_PV_HIGH ); 
+    } else {
+        gpio_set_drive_mode(bus_param->i2c_scl_pin, GPIO_DM_OUTPUT );
+        gpio_set_pin(bus_param->i2c_scl_pin , GPIO_PV_LOW ); 
+    }
+}
+
+static uint8 GetSdaState(void *data)
+{
+    I2cBusParam *bus_param = (I2cBusParam *)data;
+    gpio_set_drive_mode (bus_param->i2c_sda_pin, GPIO_DM_INPUT_PULL_UP );  
+    return gpio_get_pin(bus_param->i2c_sda_pin);
+}
+
+static uint8 GetSclState(void *data)
+{
+    I2cBusParam *bus_param = (I2cBusParam *)data;
+    gpio_set_drive_mode (bus_param->i2c_scl_pin, GPIO_DM_INPUT_PULL_UP );
+    return gpio_get_pin(bus_param->i2c_scl_pin);
+}
+
+static const struct I2cHalDrvDone i2c_hal_drv_done =
+{
+    .data = (&i2c_bus_param),
+    .SetSdaState = SetSdaState,
+    .SetSclState = SetSclState,
+    .GetSdaState = GetSdaState,
+    .GetSclState = GetSclState,
+    .udelay = usleep,
+    .delay_us = 1,
+    .timeout = 100
+};
+
+static x_err_t I2cBusReset(const I2cBusParam *bus_param)
+{
+    int32 i = 0;
+    gpio_set_drive_mode(bus_param->i2c_sda_pin, GPIO_DM_INPUT_PULL_UP );   
+    if (GPIO_LOW == gpio_get_pin(bus_param->i2c_sda_pin)) {
+        while (i++ < 9)
+        {
+            gpio_set_drive_mode(bus_param->i2c_scl_pin, GPIO_DM_OUTPUT );
+            gpio_set_pin(bus_param->i2c_scl_pin , GPIO_PV_HIGH ); 
+            usleep(100);
+            gpio_set_pin(bus_param->i2c_scl_pin , GPIO_PV_LOW ); 
+            usleep(100);
+        }
+    }
+    gpio_set_drive_mode(bus_param->i2c_sda_pin, GPIO_DM_INPUT_PULL_UP );   
+    if (GPIO_LOW == gpio_get_pin(bus_param->i2c_sda_pin)) {
+        return -ERROR;
+    }
+    return EOK;
+}
+
+static __inline void I2cDelay(struct I2cHalDrvDone *done)
+{
+    done->udelay((done->delay_us + 1) >> 1);
+}
+
+static __inline void I2cDelay2(struct I2cHalDrvDone *done)
+{
+    done->udelay(done->delay_us);
+}
+
+static x_err_t SclHigh(struct I2cHalDrvDone *done)
+{
+    x_ticks_t start;
+
+    SET_SCL(done, 1);
+
+    if (!done->GetSclState)
+        goto done;
+
+    start = CurrentTicksGain();
+    while (!GET_SCL(done))
+    {
+        if ((CurrentTicksGain() - start) > done->timeout)
+            return -ETIMEOUT;
+        DelayKTask((done->timeout + 1) >> 1);
+    }
+
+done:
+    I2cDelay(done);
+
+    return EOK;
+}
+
+static void I2cStart(struct I2cHalDrvDone *done)
+{
+    SdaLow(done);
+    I2cDelay(done);
+    SclLow(done);
+}
+
+static void I2cRestart(struct I2cHalDrvDone *done)
+{
+    SdaHigh(done);
+    SclHigh(done);
+    I2cDelay(done);
+    SdaLow(done);
+    I2cDelay(done);
+    SclLow(done);
+}
+
+static void I2cStop(struct I2cHalDrvDone *done)
+{
+    SdaLow(done);
+    I2cDelay(done);
+    SclHigh(done);
+    I2cDelay(done);
+    SdaHigh(done);
+    I2cDelay2(done);
+}
+
+static __inline x_bool I2cWaitack(struct I2cHalDrvDone *done)
+{
+    x_bool ack;
+
+    SdaHigh(done);
+     GET_SDA(done);    
+    I2cDelay(done);
+
+    if (SclHigh(done) < 0) {
+        KPrintf("wait ack timeout");
+        return -ETIMEOUT;
+    }
+
+    ack = !GET_SDA(done);
+
+    SclLow(done);
+
+    return ack;
+}
+
+static int32 I2cWriteb(struct I2cBus *bus, uint8 data)
+{
+    int32 i;
+    uint8 bit;
+
+    struct I2cHalDrvDone *done = (struct I2cHalDrvDone *)bus->private_data;
+
+    for (i = 7; i >= 0; i--)
+    {
+        SclLow(done);
+        bit = (data >> i) & 1;
+        SET_SDA(done, bit);
+        I2cDelay(done);
+        if (SclHigh(done) < 0) {
+            KPrintf("I2cWriteb: 0x%02x, "
+                    "wait scl pin high timeout at bit %d",
+                    data, i);
+
+            return -ETIMEOUT;
+        }
+    }
+    SclLow(done);
+    I2cDelay(done);
+
+    return I2cWaitack(done);
+}
+
+static int32 I2cReadb(struct I2cBus *bus)
+{
+    uint8 i;
+    uint8 data = 0;
+    struct I2cHalDrvDone *done = (struct I2cHalDrvDone *)bus->private_data;
+
+    SdaHigh(done);
+    GET_SDA(done);
+    I2cDelay(done);
+    for (i = 0; i < 8; i++)
+    {
+        data <<= 1;
+
+        if (SclHigh(done) < 0) {
+            KPrintf("I2cReadb: wait scl pin high "
+                    "timeout at bit %d", 7 - i);
+
+            return -ETIMEOUT;
+        }
+
+        if (GET_SDA(done))
+            data |= 1;
+        SclLow(done);
+        I2cDelay2(done);
+    }
+
+    return data;
+}
+
+static x_size_t I2cSendBytes(struct I2cBus *bus, struct I2cDataStandard *msg)
+{
+    int32 ret;
+    x_size_t bytes = 0;
+    const uint8 *ptr = msg->buf;
+    int32 count = msg->len;
+    uint16 ignore_nack = msg->flags & I2C_IGNORE_NACK;
+
+    while (count > 0)
+    {
+        ret = I2cWriteb(bus, *ptr);
+
+        if ((ret > 0) || (ignore_nack && (ret == 0))) {
+            count --;
+            ptr ++;
+            bytes ++;
+        } else if (ret == 0) {
+            //KPrintf("send bytes: NACK.");
+
+            return 0;
+        } else {
+            KPrintf("send bytes: error %d", ret);
+
+            return ret;
+        }
+    }
+
+    return bytes;
+}
+
+static x_err_t I2cSendAckOrNack(struct I2cBus *bus, int ack)
+{
+    struct I2cHalDrvDone *done = (struct I2cHalDrvDone *)bus->private_data;
+
+    if (ack)
+        SET_SDA(done, 0);
+    I2cDelay(done);
+    if (SclHigh(done) < 0) {
+        KPrintf("ACK or NACK timeout.");
+
+        return -ETIMEOUT;
+    }
+    SclLow(done);
+
+    return EOK;
+}
+
+static x_size_t I2cRecvBytes(struct I2cBus *bus, struct I2cDataStandard *msg)
+{
+    int32 val;
+    int32 bytes = 0;
+    uint8 *ptr = msg->buf;
+    int32 count = msg->len;
+    const uint32 flags = msg->flags;
+
+    while (count > 0)
+    {
+        val = I2cReadb(bus);
+        if (val >= 0) {
+            *ptr = val;
+            bytes ++;
+        } else {
+            break;
+        }
+
+        ptr ++;
+        count --;
+
+        if (!(flags & I2C_NO_READ_ACK)) {
+            val = I2cSendAckOrNack(bus, count);
+            if (val < 0)
+                return val;
+        }
+    }
+
+    return bytes;
+}
+
+static int32 I2cSendAddress(struct I2cBus *bus, uint8 addr, int32 retries)
+{
+    struct I2cHalDrvDone *done = (struct I2cHalDrvDone *)bus->private_data;
+    int32 i;
+    x_err_t ret = 0;
+
+    for (i = 0; i <= retries; i++)
+    {
+        ret = I2cWriteb(bus, addr);
+        if (ret == 1 || i == retries)
+            break;
+        I2cStop(done);
+        I2cDelay2(done);
+        I2cStart(done);
+    }
+
+    return ret;
+}
+
+static x_err_t I2cBitSendAddress(struct I2cBus *bus, struct I2cDataStandard *msg)
+{
+    uint16 flags = msg->flags;
+    uint16 ignore_nack = msg->flags & I2C_IGNORE_NACK;
+    struct I2cHalDrvDone *done = (struct I2cHalDrvDone *)bus->private_data;
+
+    uint8 addr1, addr2;
+    int32 retries;
+    x_err_t ret;
+
+    retries = ignore_nack ? 0 : msg->retries;
+
+    if (flags & I2C_ADDR_10BIT) {
+        addr1 = 0xf0 | ((msg->addr >> 7) & 0x06);
+        addr2 = msg->addr & 0xff;
+
+        ret = I2cSendAddress(bus, addr1, retries);
+        if ((ret != 1) && !ignore_nack) {
+            KPrintf("NACK: sending first addr");
+
+            return -EPIO;
+        }
+
+        ret = I2cWriteb(bus, addr2);
+        if ((ret != 1) && !ignore_nack) {
+            //KPrintf("NACK: sending second addr");
+
+            return -EPIO;
+        }
+
+        if (flags & I2C_RD) {
+            I2cRestart(done);
+            addr1 |= 0x01;
+            ret = I2cSendAddress(bus, addr1, retries);
+            if ((ret != 1) && !ignore_nack) {
+
+                return -EPIO;
+            }
+        }
+    } else {
+        addr1 = msg->addr << 1;
+        if (flags & I2C_RD)
+            addr1 |= 1;
+        ret = I2cSendAddress(bus, addr1, retries);
+        if ((ret != 1) && !ignore_nack)
+            return -EPIO;
+    }
+
+    return EOK;
+}
+
+static uint32 I2cWriteData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStandard *msg)
+{
+    struct I2cBus *bus = (struct I2cBus *)i2c_dev->haldev.owner_bus;
+    bus->private_data = i2c_dev->haldev.owner_bus->private_data;
+    struct I2cHalDrvDone *done = (struct I2cHalDrvDone *)bus->private_data;
+    int32 ret;
+    int32 i = 0;
+    uint16 ignore_nack;
+
+    I2cStart(done);
+    while(NONE != msg)
+    {
+        ignore_nack = msg->flags & I2C_IGNORE_NACK;
+        if (!(msg->flags & I2C_NO_START)) {
+            if (i) {
+                I2cRestart(done);
+            }
+            ret = I2cBitSendAddress(bus, msg);
+            if ((ret != EOK) && !ignore_nack) {
+                goto out;
+            }
+        }
+
+        if (msg->flags & I2C_WR) {
+            ret = I2cSendBytes(bus, msg);
+            if (ret >= 1)
+                //KPrintf("write %d byte%s", ret, ret == 1 ? "" : "s");
+            if (ret < msg->len) {
+                if (ret >= 0)
+                    ret = -ERROR;
+                goto out;
+            }
+        }
+        msg = msg->next;
+        i++;
+    }
+    ret = i;
+
+out:
+    I2cStop(done);
+
+    return ret;
+}
+
+static uint32 I2cReadData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStandard *msg)
+{
+    struct I2cBus *bus = (struct I2cBus *)i2c_dev->haldev.owner_bus;
+    bus->private_data = i2c_dev->haldev.owner_bus->private_data;
+    struct I2cHalDrvDone *done = (struct I2cHalDrvDone *)bus->private_data;
+    int32 ret;
+    int32 i = 0;
+    uint16 ignore_nack;
+
+    I2cStart(done);
+    while (NONE != msg)
+    {
+        ignore_nack = msg->flags & I2C_IGNORE_NACK;
+        if (!(msg->flags & I2C_NO_START)) {
+            if (i) {
+                I2cRestart(done);
+            }
+            ret = I2cBitSendAddress(bus, msg);
+            if ((ret != EOK) && !ignore_nack) {
+                goto out;
+            }
+        }
+
+        if (msg->flags & I2C_RD) {
+            ret = I2cRecvBytes(bus, msg);
+            if (ret >= 1)
+                //KPrintf("read %d byte%s", ret, ret == 1 ? "" : "s");
+            if (ret < msg->len) {
+                if (ret >= 0)
+                    ret = -EPIO;
+                goto out;
+            }
+        }
+        msg = msg->next;
+        i++;
+    }
+    ret = i;
+
+out:
+    I2cStop(done);
+
+    return ret;
+}
+
+static uint32 I2cInit(struct I2cDriver *i2c_drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(i2c_drv);
+
+    struct I2cHardwareDevice *i2c_dev = (struct I2cHardwareDevice *)i2c_drv->driver.owner_bus->owner_haldev;
+
+    if (configure_info->private_data) {
+        i2c_dev->i2c_dev_addr = *((uint16 *)configure_info->private_data);
+        return EOK;
+    }
+    
+    KPrintf("I2cInit need set i2c dev addr\n");
+    return ERROR;
+}
+
+static uint32 I2cDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+    struct I2cDriver *i2c_drv = (struct I2cDriver *)drv;
+
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_INT:
+            ret = I2cInit(i2c_drv, configure_info);
+            break;
+        default:
+            break;
+    }
+
+    return ret;
+}
+
+/*manage the i2c device operations*/
+static const struct I2cDevDone i2c_dev_done =
+{
+    .dev_open = NONE,
+    .dev_close = NONE,
+    .dev_write = I2cWriteData,
+    .dev_read = I2cReadData,
+};
+
+/*Init i2c bus*/
+static int BoardI2cBusInit(struct I2cBus *i2c_bus, struct I2cDriver *i2c_driver)
+{
+    x_err_t ret = EOK;
+
+    /*Init the i2c bus */
+    i2c_bus->private_data = (void *)&i2c_hal_drv_done;
+    ret = I2cBusInit(i2c_bus, I2C_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("board_i2c_init I2cBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Init the i2c driver*/
+    i2c_driver->private_data = (void *)&i2c_hal_drv_done;
+    ret = I2cDriverInit(i2c_driver, I2C_DRV_NAME_1);
+    if (EOK != ret) {
+        KPrintf("board_i2c_init I2cDriverInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Attach the i2c driver to the i2c bus*/
+    ret = I2cDriverAttachToBus(I2C_DRV_NAME_1, I2C_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("board_i2c_init I2cDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    } 
+
+    return ret;
+}
+
+/*Attach the i2c device to the i2c bus*/
+static int BoardI2cDevBend(void)
+{
+    x_err_t ret = EOK;
+    static struct I2cHardwareDevice i2c_device0;
+    memset(&i2c_device0, 0, sizeof(struct I2cHardwareDevice));
+
+    i2c_device0.i2c_dev_done = &i2c_dev_done;
+
+    ret = I2cDeviceRegister(&i2c_device0, NONE, I2C_1_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("board_i2c_init I2cDeviceInit device %s error %d\n", I2C_1_DEVICE_NAME_0, ret);
+        return ERROR;
+    }  
+
+    ret = I2cDeviceAttachToBus(I2C_1_DEVICE_NAME_0, I2C_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("board_i2c_init I2cDeviceAttachToBus device %s error %d\n", I2C_1_DEVICE_NAME_0, ret);
+        return ERROR;
+    }  
+
+    return ret;
+}
+
+/*RISC-V 64 BOARD I2C INIT*/
+int HwI2cInit(void)
+{
+    x_err_t ret = EOK;
+    static struct I2cBus i2c_bus;
+    memset(&i2c_bus, 0, sizeof(struct I2cBus));
+
+    static struct I2cDriver i2c_driver;
+    memset(&i2c_driver, 0, sizeof(struct I2cDriver));
+
+#ifdef  BSP_USING_I2C1
+    I2cGpioInit(&i2c_bus_param);
+
+    i2c_driver.configure = I2cDrvConfigure;
+
+    ret = BoardI2cBusInit(&i2c_bus, &i2c_driver);
+    if (EOK != ret) {
+        KPrintf("board_i2c_Init error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardI2cDevBend();
+    if (EOK != ret) {
+        KPrintf("board_i2c_Init error ret %u\n", ret);
+        return ERROR;
+    }   
+
+    I2cBusReset(&i2c_bus_param);
+#endif
+
+    return ret;
+}

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/i2c/hardware_i2c.c

@@ -0,0 +1,371 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file hardware_i2c.c
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#include <bsp.h>
+#include <fpioa.h>
+#include <hardware_i2c.h>
+#include <platform.h>
+#include <stddef.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sysctl.h>
+#include <utils.h>
+
+typedef struct _i2c_slave_instance
+{
+    uint32_t i2c_num;
+    const i2c_slave_handler_t *slave_handler;
+} i2c_slave_instance_t;
+
+static i2c_slave_instance_t slave_instance[I2C_MAX_NUM];
+
+typedef struct _i2c_instance
+{
+    i2c_device_number_t i2c_num;
+    i2c_transfer_mode_t TransferMode;
+    dmac_channel_number_t dmac_channel;
+    plic_instance_t i2c_int_instance;
+    spinlock_t lock;
+} i2c_instance_t;
+
+static i2c_instance_t g_i2c_instance[3];
+
+volatile i2c_t* const i2c[3] =
+{
+    (volatile i2c_t*)I2C0_BASE_ADDR,
+    (volatile i2c_t*)I2C1_BASE_ADDR,
+    (volatile i2c_t*)I2C2_BASE_ADDR
+};
+
+static void i2c_clk_init(i2c_device_number_t i2c_num)
+{
+    configASSERT(i2c_num < I2C_MAX_NUM);
+    sysctl_clock_enable(SYSCTL_CLOCK_I2C0 + i2c_num);
+    sysctl_clock_set_threshold(SYSCTL_THRESHOLD_I2C0 + i2c_num, 3);
+}
+
+void i2c_init(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,
+              uint32_t i2c_clk)
+{
+    configASSERT(i2c_num < I2C_MAX_NUM);
+    configASSERT(address_width == 7 || address_width == 10);
+
+    volatile i2c_t *i2c_adapter = i2c[i2c_num];
+
+    i2c_clk_init(i2c_num);
+
+    uint32_t v_i2c_freq = SysctlClockGetFreq(SYSCTL_CLOCK_I2C0 + i2c_num);
+    uint16_t v_period_clk_cnt = v_i2c_freq / i2c_clk / 2;
+
+    if(v_period_clk_cnt == 0)
+        v_period_clk_cnt = 1;
+
+    i2c_adapter->enable = 0;
+    i2c_adapter->con = I2C_CON_MASTER_MODE | I2C_CON_SLAVE_DISABLE | I2C_CON_RESTART_EN |
+                       (address_width == 10 ? I2C_CON_10BITADDR_SLAVE : 0) | I2C_CON_SPEED(1);
+    i2c_adapter->ss_scl_hcnt = I2C_SS_SCL_HCNT_COUNT(v_period_clk_cnt);
+    i2c_adapter->ss_scl_lcnt = I2C_SS_SCL_LCNT_COUNT(v_period_clk_cnt);
+
+    i2c_adapter->tar = I2C_TAR_ADDRESS(slave_address);
+    i2c_adapter->intr_mask = 0;
+    i2c_adapter->dma_cr = 0x3;
+    i2c_adapter->dma_rdlr = 0;
+    i2c_adapter->dma_tdlr = 4;
+    i2c_adapter->enable = I2C_ENABLE_ENABLE;
+}
+
+static int i2c_slave_irq(void *userdata)
+{
+    i2c_slave_instance_t *instance = (i2c_slave_instance_t *)userdata;
+    volatile i2c_t *i2c_adapter = i2c[instance->i2c_num];
+    uint32_t status = i2c_adapter->intr_stat;
+    if (status & I2C_INTR_STAT_START_DET)
+    {
+        instance->slave_handler->on_event(I2C_EV_START);
+        readl(&i2c_adapter->clr_start_det);
+    }
+    if (status & I2C_INTR_STAT_STOP_DET)
+    {
+        instance->slave_handler->on_event(I2C_EV_STOP);
+        readl(&i2c_adapter->clr_stop_det);
+    }
+    if (status & I2C_INTR_STAT_RX_FULL)
+    {
+        instance->slave_handler->on_receive(i2c_adapter->data_cmd);
+    }
+    if (status & I2C_INTR_STAT_RD_REQ)
+    {
+        i2c_adapter->data_cmd = instance->slave_handler->on_transmit();
+        readl(&i2c_adapter->clr_rd_req);
+    }
+    return 0;
+}
+
+void i2c_init_as_slave(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,
+    const i2c_slave_handler_t *handler)
+{
+    configASSERT(address_width == 7 || address_width == 10);
+    volatile i2c_t *i2c_adapter = i2c[i2c_num];
+    slave_instance[i2c_num].i2c_num = i2c_num;
+    slave_instance[i2c_num].slave_handler = handler;
+
+    i2c_clk_init(i2c_num);
+    i2c_adapter->enable = 0;
+    i2c_adapter->con = (address_width == 10 ? I2C_CON_10BITADDR_SLAVE : 0) | I2C_CON_SPEED(1) | I2C_CON_STOP_DET_IFADDRESSED;
+    i2c_adapter->ss_scl_hcnt = I2C_SS_SCL_HCNT_COUNT(37);
+    i2c_adapter->ss_scl_lcnt = I2C_SS_SCL_LCNT_COUNT(40);
+    i2c_adapter->sar = I2C_SAR_ADDRESS(slave_address);
+    i2c_adapter->rx_tl = I2C_RX_TL_VALUE(0);
+    i2c_adapter->tx_tl = I2C_TX_TL_VALUE(0);
+    i2c_adapter->intr_mask = I2C_INTR_MASK_RX_FULL | I2C_INTR_MASK_START_DET | I2C_INTR_MASK_STOP_DET | I2C_INTR_MASK_RD_REQ;
+
+    plic_set_priority(IRQN_I2C0_INTERRUPT + i2c_num, 1);
+    plic_irq_register(IRQN_I2C0_INTERRUPT + i2c_num, i2c_slave_irq, slave_instance + i2c_num);
+    plic_irq_enable(IRQN_I2C0_INTERRUPT + i2c_num);
+
+    i2c_adapter->enable = I2C_ENABLE_ENABLE;
+}
+
+int i2c_send_data(i2c_device_number_t i2c_num, const uint8_t *SendBuf, size_t send_buf_len)
+{
+    configASSERT(i2c_num < I2C_MAX_NUM);
+    volatile i2c_t* i2c_adapter = i2c[i2c_num];
+    size_t fifo_len, index;
+    i2c_adapter->clr_tx_abrt = i2c_adapter->clr_tx_abrt;
+    while (send_buf_len)
+    {
+        fifo_len = 8 - i2c_adapter->txflr;
+        fifo_len = send_buf_len < fifo_len ? send_buf_len : fifo_len;
+        for (index = 0; index < fifo_len; index++)
+            i2c_adapter->data_cmd = I2C_DATA_CMD_DATA(*SendBuf++);
+        if (i2c_adapter->tx_abrt_source != 0)
+            return 1;
+        send_buf_len -= fifo_len;
+    }
+    while ((i2c_adapter->status & I2C_STATUS_ACTIVITY) || !(i2c_adapter->status & I2C_STATUS_TFE))
+        ;
+
+    if (i2c_adapter->tx_abrt_source != 0)
+        return 1;
+
+    return 0;
+}
+
+void i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t i2c_num, const uint8_t *SendBuf,
+                       size_t send_buf_len)
+{
+    configASSERT(i2c_num < I2C_MAX_NUM);
+    volatile i2c_t* i2c_adapter = i2c[i2c_num];
+    i2c_adapter->clr_tx_abrt = i2c_adapter->clr_tx_abrt;
+    uint32_t *buf = malloc(send_buf_len * sizeof(uint32_t));
+    int i;
+    for (i = 0; i < send_buf_len; i++)
+    {
+        buf[i] = SendBuf[i];
+    }
+
+    sysctl_dma_select((sysctl_dma_channel_t)dma_channel_num, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2);
+    dmac_set_single_mode(dma_channel_num, buf, (void *)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
+        DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, send_buf_len);
+
+    dmac_wait_done(dma_channel_num);
+    free((void *)buf);
+
+    while ((i2c_adapter->status & I2C_STATUS_ACTIVITY) || !(i2c_adapter->status & I2C_STATUS_TFE))
+    {
+        if (i2c_adapter->tx_abrt_source != 0)
+            return;
+    }
+}
+
+int i2c_recv_data(i2c_device_number_t i2c_num, const uint8_t *SendBuf, size_t send_buf_len, uint8_t *receive_buf,
+                  size_t receive_buf_len)
+{
+    configASSERT(i2c_num < I2C_MAX_NUM);
+
+    size_t fifo_len, index;
+    size_t rx_len = receive_buf_len;
+    volatile i2c_t* i2c_adapter = i2c[i2c_num];
+
+    while (send_buf_len)
+    {
+        fifo_len = 8 - i2c_adapter->txflr;
+        fifo_len = send_buf_len < fifo_len ? send_buf_len : fifo_len;
+        for (index = 0; index < fifo_len; index++)
+            i2c_adapter->data_cmd = I2C_DATA_CMD_DATA(*SendBuf++);
+        if (i2c_adapter->tx_abrt_source != 0)
+            return 1;
+        send_buf_len -= fifo_len;
+    }
+
+    while (receive_buf_len || rx_len)
+    {
+        fifo_len = i2c_adapter->rxflr;
+        fifo_len = rx_len < fifo_len ? rx_len : fifo_len;
+        for (index = 0; index < fifo_len; index++)
+            *receive_buf++ = (uint8_t)i2c_adapter->data_cmd;
+        rx_len -= fifo_len;
+        fifo_len = 8 - i2c_adapter->txflr;
+        fifo_len = receive_buf_len < fifo_len ? receive_buf_len : fifo_len;
+        for (index = 0; index < fifo_len; index++)
+            i2c_adapter->data_cmd = I2C_DATA_CMD_CMD;
+        if (i2c_adapter->tx_abrt_source != 0)
+            return 1;
+        receive_buf_len -= fifo_len;
+    }
+    return 0;
+}
+
+void i2c_recv_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num,
+                       i2c_device_number_t i2c_num, const uint8_t *SendBuf, size_t send_buf_len,
+                       uint8_t *receive_buf, size_t receive_buf_len)
+{
+    configASSERT(i2c_num < I2C_MAX_NUM);
+
+    volatile i2c_t* i2c_adapter = i2c[i2c_num];
+
+    uint32_t *write_cmd = malloc(sizeof(uint32_t) * (send_buf_len + receive_buf_len));
+    size_t i;
+    for(i = 0; i < send_buf_len; i++)
+        write_cmd[i] = *SendBuf++;
+    for (i = 0; i < receive_buf_len; i++)
+        write_cmd[i + send_buf_len] = I2C_DATA_CMD_CMD;
+
+    sysctl_dma_select((sysctl_dma_channel_t)dma_send_channel_num, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2);
+    sysctl_dma_select((sysctl_dma_channel_t)dma_receive_channel_num, SYSCTL_DMA_SELECT_I2C0_RX_REQ + i2c_num * 2);
+
+    dmac_set_single_mode(dma_receive_channel_num, (void *)(&i2c_adapter->data_cmd), write_cmd, DMAC_ADDR_NOCHANGE,
+         DMAC_ADDR_INCREMENT,DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, receive_buf_len);
+
+    dmac_set_single_mode(dma_send_channel_num, write_cmd, (void *)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT,
+         DMAC_ADDR_NOCHANGE,DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, receive_buf_len + send_buf_len);
+
+    dmac_wait_done(dma_send_channel_num);
+    dmac_wait_done(dma_receive_channel_num);
+
+    for (i = 0; i < receive_buf_len; i++)
+    {
+        receive_buf[i] = (uint8_t)write_cmd[i];
+    }
+
+    free(write_cmd);
+}
+
+static int i2c_dma_irq(void *ctx)
+{
+    i2c_instance_t *v_instance = (i2c_instance_t *)ctx;
+    volatile i2c_t* i2c_adapter = i2c[v_instance->i2c_num];
+    dmac_irq_unregister(v_instance->dmac_channel);
+    if(v_instance->TransferMode == I2C_SEND)
+    {
+        while ((i2c_adapter->status & I2C_STATUS_ACTIVITY) || !(i2c_adapter->status & I2C_STATUS_TFE))
+        {
+            if (i2c_adapter->tx_abrt_source != 0)
+            {
+                spinlock_unlock(&v_instance->lock);
+                return -1;
+            }
+        }
+    }
+    spinlock_unlock(&v_instance->lock);
+    if(v_instance->i2c_int_instance.callback)
+    {
+        v_instance->i2c_int_instance.callback(v_instance->i2c_int_instance.ctx);
+    }
+    return 0;
+}
+
+void i2c_handle_data_dma(i2c_device_number_t i2c_num, i2c_data_t data, plic_interrupt_t *cb)
+{
+    configASSERT(i2c_num < I2C_MAX_NUM);
+    configASSERT(data.tx_channel < DMAC_CHANNEL_MAX && data.rx_channel < DMAC_CHANNEL_MAX);
+
+    spinlock_lock(&g_i2c_instance[i2c_num].lock);
+    if(cb)
+    {
+        g_i2c_instance[i2c_num].i2c_int_instance.callback = cb->callback;
+        g_i2c_instance[i2c_num].i2c_int_instance.ctx = cb->ctx;
+    }
+
+    volatile i2c_t* i2c_adapter = i2c[i2c_num];
+    if(data.TransferMode == I2C_SEND)
+    {
+        configASSERT(data.tx_buf && data.tx_len);
+
+        i2c_adapter->clr_tx_abrt = i2c_adapter->clr_tx_abrt;
+        if(cb)
+        {
+            g_i2c_instance[i2c_num].dmac_channel = data.tx_channel;
+            g_i2c_instance[i2c_num].TransferMode = I2C_SEND;
+            dmac_irq_register(data.tx_channel, i2c_dma_irq, &g_i2c_instance[i2c_num], cb->priority);
+        }
+        sysctl_dma_select((sysctl_dma_channel_t)data.tx_channel, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2);
+        dmac_set_single_mode(data.tx_channel, data.tx_buf, (void *)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
+            DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, data.tx_len);
+        if(!cb)
+        {
+            dmac_wait_done(data.tx_channel);
+            while ((i2c_adapter->status & I2C_STATUS_ACTIVITY) || !(i2c_adapter->status & I2C_STATUS_TFE))
+            {
+                if (i2c_adapter->tx_abrt_source != 0)
+                    configASSERT(!"source abort");
+            }
+        }
+    }
+    else
+    {
+        configASSERT(data.rx_buf && data.rx_len);
+        if(data.tx_len)
+            configASSERT(data.tx_buf);
+        if(cb)
+        {
+            g_i2c_instance[i2c_num].dmac_channel = data.rx_channel;
+            g_i2c_instance[i2c_num].TransferMode = I2C_RECEIVE;
+            dmac_irq_register(data.rx_channel, i2c_dma_irq, &g_i2c_instance[i2c_num], cb->priority);
+        }
+        sysctl_dma_select((sysctl_dma_channel_t)data.rx_channel, SYSCTL_DMA_SELECT_I2C0_RX_REQ + i2c_num * 2);
+        dmac_set_single_mode(data.rx_channel, (void *)(&i2c_adapter->data_cmd), data.rx_buf, DMAC_ADDR_NOCHANGE,
+             DMAC_ADDR_INCREMENT,DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, data.rx_len);
+
+        sysctl_dma_select((sysctl_dma_channel_t)data.tx_channel, SYSCTL_DMA_SELECT_I2C0_TX_REQ + i2c_num * 2);
+        if(data.tx_len)
+        {
+            configASSERT(data.tx_buf);
+            dmac_set_single_mode(data.tx_channel, data.tx_buf, (void *)(&i2c_adapter->data_cmd), DMAC_ADDR_INCREMENT,
+                 DMAC_ADDR_NOCHANGE,DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, data.tx_len);
+            dmac_wait_done(data.tx_channel);
+        }
+        static uint32_t s_read_cmd = I2C_DATA_CMD_CMD;
+        dmac_set_single_mode(data.tx_channel, &s_read_cmd, (void *)(&i2c_adapter->data_cmd), DMAC_ADDR_NOCHANGE,
+                     DMAC_ADDR_NOCHANGE,DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, data.rx_len);
+
+        if(!cb)
+        {
+            dmac_wait_done(data.tx_channel);
+            dmac_wait_done(data.rx_channel);
+        }
+    }
+    if(!cb)
+        spinlock_unlock(&g_i2c_instance[i2c_num].lock);
+}

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/clint.h

@@ -0,0 +1,347 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/**
+ * @file
+ * @brief      The CLINT block holds memory-mapped control and status registers
+ *             associated with local interrupts for a Coreplex.
+ *
+ * @note       CLINT RAM Layout
+ *
+ * | Address   -| Description                     |
+ * |------------|---------------------------------|
+ * | 0x02000000 | msip for core 0                 |
+ * | 0x02000004 | msip for core 1                 |
+ * | ...        | ...                             |
+ * | 0x02003FF8 | msip for core 4094              |
+ * |            |                                 |
+ * | 0x02004000 | mtimecmp for core 0             |
+ * | 0x02004008 | mtimecmp for core 1             |
+ * | ...        | ...                             |
+ * | 0x0200BFF0 | mtimecmp For core 4094          |
+ * | 0x0200BFF8 | mtime                           |
+ * |            |                                 |
+ * | 0x0200C000 | Reserved                        |
+ * | ...        | ...                             |
+ * | 0x0200EFFC | Reserved                        |
+ */
+
+/**
+* @file clint.h
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef __CLINT_H__
+#define __CLINT_H__
+
+#include <platform.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* clang-format off */
+/* Register address offsets */
+#define CLINT_MSIP          (0x0000)
+#define CLINT_MSIP_SIZE     (0x4)
+#define CLINT_MTIMECMP      (0x4000)
+#define CLINT_MTIMECMP_SIZE (0x8)
+#define CLINT_MTIME         (0xBFF8)
+#define CLINT_MTIME_SIZE    (0x8)
+/* Max number of cores */
+#define CLINT_MAX_CORES     (4095)
+/* Real number of cores */
+#define CLINT_NUM_CORES     (2)
+/* Clock frequency division factor */
+#define CLINT_CLOCK_DIV     (50)
+/* clang-format on */
+
+/**
+ * @brief       MSIP Registers
+ *
+ *              Machine-mode software interrupts are generated by writing to a
+ *              per-core memory-mapped control register. The msip registers are
+ *              32-bit wide WARL registers, where the LSB is reflected in the
+ *              msip bit of the associated core’s mip register. Other bits in
+ *              the msip registers are hardwired to zero. The mapping supports
+ *              up to 4095 machine-mode cores.
+ */
+typedef struct _clint_msip
+{
+    uint32_t msip : 1;  /*!< Bit 0 is msip */
+    uint32_t zero : 31; /*!< Bits [32:1] is 0 */
+} __attribute__((packed, aligned(4))) clint_msip_t;
+
+/**
+ * @brief       Timer compare Registers Machine-mode timer interrupts are
+ *              generated by a real-time counter and a per-core comparator. The
+ *              mtime register is a 64-bit read-only register that contains the
+ *              current value of the real-time counter. Each mtimecmp register
+ *              holds its core’s time comparator. A timer interrupt is pending
+ *              whenever mtime is greater than or equal to the value in a
+ *              core’s mtimecmp register. The timer interrupt is reflected in
+ *              the mtip bit of the associated core’s mip register.
+ */
+typedef uint64_t clint_mtimecmp_t;
+
+/**
+ * @brief       Timer Registers
+ *
+ *              The mtime register has a 64-bit precision on all RV32, RV64,
+ *              and RV128 systems. Platforms provide a 64-bit memory-mapped
+ *              machine-mode timer compare register (mtimecmp), which causes a
+ *              timer interrupt to be posted when the mtime register contains a
+ *              value greater than or equal to the value in the mtimecmp
+ *              register. The interrupt remains posted until it is cleared by
+ *              writing the mtimecmp register. The interrupt will only be taken
+ *              if interrupts are enabled and the MTIE bit is set in the mie
+ *              register.
+ */
+typedef uint64_t clint_mtime_t;
+
+/**
+ * @brief       CLINT object
+ *
+ *              Coreplex-Local INTerrupts, which includes software interrupts,
+ *              local timer interrupts, and other interrupts routed directly to
+ *              a core.
+ */
+typedef struct _clint
+{
+    /* 0x0000 to 0x3FF8, MSIP Registers */
+    clint_msip_t msip[CLINT_MAX_CORES];
+    /* Resverd space, do not use */
+    uint32_t resv0;
+    /* 0x4000 to 0xBFF0, Timer Compare Registers */
+    clint_mtimecmp_t mtimecmp[CLINT_MAX_CORES];
+    /* 0xBFF8, Time Register */
+    clint_mtime_t mtime;
+} __attribute__((packed, aligned(4))) clint_t;
+
+/**
+ * @brief       Clint object instanse
+ */
+extern volatile clint_t* const clint;
+
+/**
+ * @brief       Definitions for the timer callbacks
+ */
+typedef int (*clint_timer_callback_t)(void *ctx);
+
+/**
+ * @brief       Definitions for local interprocessor interrupt callbacks
+ */
+typedef int (*clint_ipi_callback_t)(void *ctx);
+
+typedef struct _clint_timer_instance
+{
+    uint64_t interval;
+    uint64_t cycles;
+    uint64_t single_shot;
+    clint_timer_callback_t callback;
+    void *ctx;
+} clint_timer_instance_t;
+
+typedef struct _clint_ipi_instance
+{
+    clint_ipi_callback_t callback;
+    void *ctx;
+} clint_ipi_instance_t;
+
+/**
+ * @brief       Get the time form CLINT timer register
+ *
+ * @note        The CLINT must init to get right time
+ *
+ * @return      64bit Time
+ */
+uint64_t clint_get_time(void);
+
+/**
+ * @brief       Init the CLINT timer
+ *
+ * @note        MIP_MTIP will be clear after init. The MSTATUS_MIE must set by
+ *              user.
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int clint_timer_init(void);
+
+/**
+ * @brief       Stop the CLINT timer
+ *
+ * @note        MIP_MTIP will be clear after stop
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int clint_timer_stop(void);
+
+/**
+ * @brief       Start the CLINT timer
+ *
+ * @param[in]   interval        The interval with Millisecond(ms)
+ * @param[in]   single_shot     Single shot or repeat
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int clint_timer_start(uint64_t interval, int single_shot);
+
+/**
+ * @brief       Get the interval of timer
+ *
+ * @return      The interval with Millisecond(ms)
+ */
+uint64_t clint_timer_get_interval(void);
+
+/**
+ * @brief       Set the interval with Millisecond(ms)
+ *
+ * @param[in]   interval  The interval with Millisecond(ms)
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int clint_timer_set_interval(uint64_t interval);
+
+/**
+ * @brief      Get whether the timer is a single shot timer
+ *
+ * @return     result
+ *     - 0     It is a repeat timer
+ *     - 1     It is a single shot timer
+ */
+int clint_timer_get_single_shot(void);
+
+/**
+ * @brief       Set the timer working as a single shot timer or repeat timer
+ *
+ * @param[in]   single_shot  Single shot or repeat
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int clint_timer_set_single_shot(int single_shot);
+
+/**
+ * @brief       Set user callback function when timer is timeout
+ *
+ * @param[in]   callback        The callback function
+ * @param[in]   ctx             The context
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int clint_timer_register(clint_timer_callback_t callback, void *ctx);
+
+/**
+ * @brief       Deregister user callback function
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int clint_timer_unregister(void);
+
+/**
+ * @brief       Initialize local interprocessor interrupt
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int clint_ipi_init(void);
+
+/**
+ * @brief       Enable local interprocessor interrupt
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int clint_ipi_enable(void);
+
+/**
+ * @brief       Disable local interprocessor interrupt
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int clint_ipi_disable(void);
+
+/**
+ * @brief       Send local interprocessor interrupt to core by core id
+ *
+ * @param[in]   core_id  The core identifier
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int clint_ipi_send(size_t core_id);
+
+/**
+ * @brief       Clear local interprocessor interrupt
+ *
+ * @param[in]   core_id  The core identifier
+ *
+ * @return      result
+ *     - 1      An IPI was pending
+ *     - 0      Non IPI was pending
+ *     - -1     Fail
+ */
+int clint_ipi_clear(size_t core_id);
+
+/**
+ * @brief      Set user callback function when interprocessor interrupt
+ *
+ * @param[in]   callback        The callback function
+ * @param[in]   ctx             The context
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int clint_ipi_register(clint_ipi_callback_t callback, void *ctx);
+
+/**
+ * @brief       Deregister user callback function
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int clint_ipi_unregister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CLINT_H__ */
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_ch376.h

@@ -0,0 +1,36 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_ch376.h
+* @brief define aiit-riscv64-board ch376 function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_CH376_H
+#define CONNECT_CH376_H
+
+#include <device.h>
+
+struct HwCh376
+{
+    HardwareDevType dev;
+    x_size_t msg_len;
+    int sem;
+    KTaskDescriptorType task;
+};
+
+int HwCh376Init(void);
+
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_ch438.h

@@ -0,0 +1,259 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+ 
+/**
+* @file connect_ch438.h
+* @brief define aiit-riscv64-board ch438 function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_CH438_H
+#define CONNECT_CH438_H
+
+#include <device.h>
+
+#define BUFFSIZE	255
+
+/******************************************************************************************/
+
+/* CH438serial port0 register address */
+
+#define REG_RBR0_ADDR        0x00      /* serial port0receive buffer register address */
+#define REG_THR0_ADDR        0x00      /* serial port0send hold register address */
+#define REG_IER0_ADDR          0x01      /* serial port0interrupt enable register address */
+#define REG_IIR0_ADDR           0x02      /* serial port0interrupt identifies register address */
+#define REG_FCR0_ADDR        0x02      /* serial port0FIFO controls register address */
+#define REG_LCR0_ADDR        0x03      /* serial port0circuit control register address */
+#define REG_MCR0_ADDR       0x04      /* serial port0MODEM controls register address */
+#define REG_LSR0_ADDR         0x05      /* serial port0line status register address */
+#define REG_MSR0_ADDR       0x06      /* serial port0address of MODEM status register */
+#define REG_SCR0_ADDR        0x07      /* serial port0the user can define the register address */
+#define REG_DLL0_ADDR        0x00      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM0_ADDR       0x01      /* Baud rate divisor latch high 8-bit byte address */
+
+/* CH438serial port1 register address */
+
+#define REG_RBR1_ADDR       0x10      /* serial port1receive buffer register address */
+#define REG_THR1_ADDR       0x10      /* serial port1send hold register address */
+#define REG_IER1_ADDR         0x11      /* serial port1interrupt enable register address */
+#define REG_IIR1_ADDR          0x12      /* serial port1interrupt identifies register address */
+#define REG_FCR1_ADDR       0x12      /* serial port1FIFO controls register address */
+#define REG_LCR1_ADDR       0x13      /* serial port1circuit control register address */
+#define REG_MCR1_ADDR      0x14      /* serial port1MODEM controls register address */
+#define REG_LSR1_ADDR       0x15      /* serial port1line status register address */
+#define REG_MSR1_ADDR      0x16      /* serial port1address of MODEM status register */
+#define REG_SCR1_ADDR       0x17      /* serial port1the user can define the register address */
+#define REG_DLL1_ADDR       0x10      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM1_ADDR      0x11      /* Baud rate divisor latch high 8-bit byte address */
+
+
+/* CH438serial port2 register address */
+
+#define REG_RBR2_ADDR       0x20      /* serial port2receive buffer register address */
+#define REG_THR2_ADDR       0x20      /* serial port2send hold register address */
+#define REG_IER2_ADDR         0x21      /* serial port2interrupt enable register address */
+#define REG_IIR2_ADDR          0x22      /* serial port2interrupt identifies register address */
+#define REG_FCR2_ADDR       0x22      /* serial port2FIFO controls register address */
+#define REG_LCR2_ADDR       0x23      /* serial port2circuit control register address */
+#define REG_MCR2_ADDR      0x24      /* serial port2MODEM controls register address */
+#define REG_LSR2_ADDR       0x25      /* serial port2line status register address */
+#define REG_MSR2_ADDR      0x26      /* serial port2address of MODEM status register */
+#define REG_SCR2_ADDR       0x27      /* serial port2the user can define the register address */
+#define REG_DLL2_ADDR       0x20      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM2_ADDR      0x21      /* Baud rate divisor latch high 8-bit byte address */
+
+
+
+/* CH438serial port3 register address */
+
+#define REG_RBR3_ADDR       0x30      /* serial port3receive buffer register address */
+#define REG_THR3_ADDR       0x30      /* serial port3send hold register address */
+#define REG_IER3_ADDR         0x31      /* serial port3interrupt enable register address */
+#define REG_IIR3_ADDR          0x32      /* serial port3interrupt identifies register address */
+#define REG_FCR3_ADDR       0x32      /* serial port3FIFO controls register address */
+#define REG_LCR3_ADDR       0x33      /* serial port3circuit control register address */
+#define REG_MCR3_ADDR      0x34      /* serial port3MODEM controls register address */
+#define REG_LSR3_ADDR       0x35      /* serial port3line status register address */
+#define REG_MSR3_ADDR      0x36      /* serial port3address of MODEM status register */
+#define REG_SCR3_ADDR       0x37      /* serial port3the user can define the register address */
+#define REG_DLL3_ADDR       0x30      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM3_ADDR      0x31      /* Baud rate divisor latch high 8-bit byte address */
+
+
+/* CH438serial port4 register address */
+
+#define REG_RBR4_ADDR       0x08      /* serial port4receive buffer register address */
+#define REG_THR4_ADDR       0x08      /* serial port4send hold register address */
+#define REG_IER4_ADDR         0x09      /* serial port4interrupt enable register address */
+#define REG_IIR4_ADDR          0x0A      /* serial port4interrupt identifies register address */
+#define REG_FCR4_ADDR       0x0A      /* serial port4FIFO controls register address */
+#define REG_LCR4_ADDR       0x0B      /* serial port4circuit control register address */
+#define REG_MCR4_ADDR      0x0C      /* serial port4MODEM controls register address */
+#define REG_LSR4_ADDR       0x0D      /* serial port4line status register address */
+#define REG_MSR4_ADDR      0x0E      /* serial port4address of MODEM status register */
+#define REG_SCR4_ADDR       0x0F      /* serial port4the user can define the register address */
+#define REG_DLL4_ADDR       0x08      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM4_ADDR      0x09      /* Baud rate divisor latch high 8-bit byte address */
+
+
+
+/* CH438serial port5 register address */
+
+#define REG_RBR5_ADDR       0x18      /* serial port5receive buffer register address */
+#define REG_THR5_ADDR       0x18      /* serial port5send hold register address */
+#define REG_IER5_ADDR         0x19      /* serial port5interrupt enable register address */
+#define REG_IIR5_ADDR          0x1A      /* serial port5interrupt identifies register address */
+#define REG_FCR5_ADDR       0x1A      /* serial port5FIFO controls register address */
+#define REG_LCR5_ADDR       0x1B      /* serial port5circuit control register address */
+#define REG_MCR5_ADDR      0x1C      /* serial port5MODEM controls register address */
+#define REG_LSR5_ADDR       0x1D      /* serial port5line status register address */
+#define REG_MSR5_ADDR      0x1E      /* serial port5address of MODEM status register */
+#define REG_SCR5_ADDR       0x1F      /* serial port5the user can define the register address */
+#define REG_DLL5_ADDR       0x18      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM5_ADDR      0x19      /* Baud rate divisor latch high 8-bit byte address */
+
+
+/* CH438serial port6 register address */
+
+#define REG_RBR6_ADDR       0x28      /* serial port6receive buffer register address */
+#define REG_THR6_ADDR       0x28      /* serial port6send hold register address */
+#define REG_IER6_ADDR         0x29      /* serial port6interrupt enable register address */
+#define REG_IIR6_ADDR          0x2A      /* serial port6interrupt identifies register address */
+#define REG_FCR6_ADDR       0x2A      /* serial port6FIFO controls register address */
+#define REG_LCR6_ADDR       0x2B      /* serial port6circuit control register address */
+#define REG_MCR6_ADDR      0x2C      /* serial port6MODEM controls register address */
+#define REG_LSR6_ADDR       0x2D      /* serial port6line status register address */
+#define REG_MSR6_ADDR      0x2E      /* serial port6address of MODEM status register */
+#define REG_SCR6_ADDR       0x2F      /* serial port6the user can define the register address */
+#define REG_DLL6_ADDR       0x28      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM6_ADDR      0x29      /* Baud rate divisor latch high 8-bit byte address */
+
+
+/* CH438serial port7 register address */
+
+#define REG_RBR7_ADDR       0x38      /* serial port7receive buffer register address */
+#define REG_THR7_ADDR       0x38      /* serial port7send hold register address */
+#define REG_IER7_ADDR         0x39      /* serial port7interrupt enable register address */
+#define REG_IIR7_ADDR          0x3A      /* serial port7interrupt identifies register address */
+#define REG_FCR7_ADDR       0x3A      /* serial port7FIFO controls register address */
+#define REG_LCR7_ADDR       0x3B      /* serial port7circuit control register address */
+#define REG_MCR7_ADDR      0x3C      /* serial port7MODEM controls register address */
+#define REG_LSR7_ADDR       0x3D      /* serial port7line status register address */
+#define REG_MSR7_ADDR      0x3E      /* serial port7address of MODEM status register */
+#define REG_SCR7_ADDR       0x3F      /* serial port7the user can define the register address */
+#define REG_DLL7_ADDR       0x38      /* Baud rate divisor latch low 8-bit byte address */
+#define REG_DLM7_ADDR      0x39      /* Baud rate divisor latch high 8-bit byte address */
+
+
+#define REG_SSR_ADDR        0x4F       /* pecial status register address */
+
+
+/* IER register bit */
+
+#define BIT_IER_RESET                0x80      /* The bit is 1 soft reset serial port */
+#define BIT_IER_LOWPOWER    0x40      /* The bit is 1 close serial port internal reference clock */
+#define BIT_IER_SLP                     0x20      /* serial port0 is SLP, 1 close clock vibrator  */
+#define BIT_IER1_CK2X                0x20      /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */
+#define BIT_IER_IEMODEM         0x08      /* The bit is 1 allows MODEM input status to interrupt */
+#define BIT_IER_IELINES             0x04      /* The bit is 1 allow receiving line status to be interrupted */
+#define BIT_IER_IETHRE              0x02      /* The bit is 1 allows the send hold register to break in mid-air */
+#define BIT_IER_IERECV               0x01      /* The bit is 1 allows receiving data interrupts */
+
+/* IIR register bit */
+
+#define BIT_IIR_FIFOENS1    0x80
+#define BIT_IIR_FIFOENS0    0x40      /* The two is 1 said use FIFO */
+
+/* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted,
+1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */
+#define BIT_IIR_IID3        0x08
+#define BIT_IIR_IID2        0x04
+#define BIT_IIR_IID1        0x02
+#define BIT_IIR_NOINT  0x01
+
+/* FCR register bit */
+
+/* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */
+#define BIT_FCR_RECVTG1     0x80      /* Set the trigger point for FIFO interruption and automatic hardware flow control */
+#define BIT_FCR_RECVTG0     0x40      /* Set the trigger point for FIFO interruption and automatic hardware flow control */
+
+#define BIT_FCR_TFIFORST    0x04      /* The bit is 1 empty the data sent in FIFO */
+#define BIT_FCR_RFIFORST    0x02      /* The bit is 1 empty the data sent in FIFO */
+#define BIT_FCR_FIFOEN         0x01      /* The bit is 1 use FIFO, 0 disable FIFO */
+
+/* LCR register bit */
+
+#define BIT_LCR_DLAB              0x80      /* To access DLL, DLM, 0 to access RBR/THR/IER */
+#define BIT_LCR_BREAKEN     0x40      /* 1 forces a BREAK line interval*/
+
+/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */
+#define BIT_LCR_PARMODE1    0x20      /* Sets the parity bit format */
+#define BIT_LCR_PARMODE0    0x10      /* Sets the parity bit format */
+
+#define BIT_LCR_PAREN         0x08      /* A value of 1 allows you to generate and receive parity bits when sending */
+#define BIT_LCR_STOPBIT     0x04      /* If is 1, then two stop bits, is 0, a stop bit */
+
+/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */
+#define BIT_LCR_WORDSZ1     0x02      /* Set the word length length */
+#define BIT_LCR_WORDSZ0     0x01
+
+/* MCR register bit */
+
+#define BIT_MCR_AFE            0x20      /* For 1 allows automatic flow control of CTS and RTS hardware */
+#define BIT_MCR_LOOP        0x10      /* Is the test mode of 1 enabling internal loop */
+#define BIT_MCR_OUT2        0x08      /* 1 Allows an interrupt request for the serial port output  */
+#define BIT_MCR_OUT1        0x04      /* The MODEM control bit defined for the user */
+#define BIT_MCR_RTS            0x02      /* The bit is 1 RTS pin  output  effective  */
+#define BIT_MCR_DTR           0x01      /* The bit is 1 DTR pin  output  effective  */
+
+/* LSR register bit */
+
+#define BIT_LSR_RFIFOERR    0x80      /* 1 said There is at least one error in receiving FIFO */
+#define BIT_LSR_TEMT             0x40      /* 1 said THR and TSR are empty */
+#define BIT_LSR_THRE              0x20      /* 1 said THR is empty*/
+#define BIT_LSR_BREAKINT    0x10      /* The bit is 1 said the BREAK line interval was detected*/
+#define BIT_LSR_FRAMEERR   0x08      /* The bit is 1 said error reading data frame */
+#define BIT_LSR_PARERR         0x04      /* The bit is 1 said parity error */
+#define BIT_LSR_OVERR           0x02      /*  1 said receive FIFO buffer overflow */
+#define BIT_LSR_DATARDY       0x01      /* The bit is 1 said receive data received in FIFO */
+
+/* MSR register bit */
+
+#define BIT_MSR_DCD         0x80      /* The bit is 1 said DCD pin  effective  */
+#define BIT_MSR_RI              0x40      /* The bit is 1 said RI pin  effective  */
+#define BIT_MSR_DSR         0x20      /* The bit is 1 said DSR pin  effective  */
+#define BIT_MSR_CTS          0x10      /* The bit is 1 said CTS pin  effective  */
+#define BIT_MSR_DDCD      0x08      /* The bit is 1 said DCD pin The input state has changed */
+#define BIT_MSR_TERI        0x04      /* The bit is 1 said RI pin The input state has changed */
+#define BIT_MSR_DDSR      0x02      /* The bit is 1 said DSR pin The input state has changed */
+#define BIT_MSR_DCTS       0x01      /* The bit is 1 said CTS pin The input state has changed */
+
+/* Interrupt status code */
+
+#define INT_NOINT                          0x01      /* There is no interruption */
+#define INT_THR_EMPTY               0x02      /* THR empty interruption */
+#define INT_RCV_OVERTIME        0x0C      /* Receive timeout interrupt */
+#define INT_RCV_SUCCESS          0x04      /* Interrupts are available to receive data */
+#define INT_RCV_LINES                  0x06      /* Receiving line status interrupted */
+#define INT_MODEM_CHANGE    0x00      /* MODEM input changes interrupt */
+
+#define CH438_IIR_FIFOS_ENABLED 0xC0  /* use FIFO */
+
+
+#define Fpclk 1843200         /* Define the internal clock frequency  */
+
+void Set485Input(uint8 ch_no);
+void Set485Output(uint8 ch_no);
+
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_gpio.h

@@ -0,0 +1,36 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_gpio.h
+* @brief define aiit-riscv64-board gpio function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_GPIO_H
+#define CONNECT_GPIO_H
+
+#include <device.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int HwGpioInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_hwtimer.h

@@ -0,0 +1,37 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_hwtimer.h
+* @brief define aiit-riscv64-board hwtimer function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_HWTIMER_H
+#define CONNECT_HWTIMER_H
+
+#include <device.h>
+#include "hardware_hwtimer.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int HwTimerInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_i2c.h

@@ -0,0 +1,36 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_i2c.h
+* @brief define aiit-riscv64-board i2c function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_I2C_H
+#define CONNECT_I2C_H
+
+#include <device.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int HwI2cInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_lcd.h

@@ -0,0 +1,52 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file connect_lcd.h
+* @brief define aiit-riscv64-board lcd function
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: connect_lcd.h
+Description: define aiit-riscv64-board lcd function
+Others:  https://canaan-creative.com/developer
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. add aiit-riscv64-board lcd function
+*************************************************/
+
+#ifndef CONNECT_LCD_H
+#define CONNECT_LCD_H
+
+#include <device.h>
+#include "hardware_spi.h"
+#include <sysctl.h>
+
+#ifdef BSP_USING_TOUCH
+#include "connect_touch.h"
+#endif
+
+void DrvLcdClear(uint16_t color);
+void LcdDrawLine(uint16 x1, uint16 y1, uint16 x2, uint16 y2,uint16 color);							
+void LcdDrawRectangle(uint16 x1, uint16 y1, uint16 x2, uint16 y2,uint16 color);		   			
+void LcdDrawCircle(uint16 x0,uint16 y0,uint8 r,uint16 color);
+
+int HwLcdInit(void);
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_rtc.h

@@ -0,0 +1,36 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_rtc.h
+* @brief define aiit-riscv64-board rtc function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_RTC_H
+#define CONNECT_RTC_H
+
+#include <device.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int HwRtcInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_spi.h

@@ -0,0 +1,36 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_spi.h
+* @brief define aiit-riscv64-board spi function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_SPI_H
+#define CONNECT_SPI_H
+
+#include <device.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int HwSpiInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_spi_lora.h

@@ -0,0 +1,63 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_spi_lora.h
+* @brief define spi lora dev function and struct using bus driver framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-24
+*/
+
+#ifndef CONNECT_SPI_LORA_H
+#define CONNECT_SPI_LORA_H
+
+#include <bus.h>
+#include <connect_spi.h>
+#include <device.h>
+#include <radio.h>
+// #include <hardware_gpio.h>
+// #include <stm32f4xx.h>
+#include <spi_lora_sx12xx.h>
+#include <sx1276.h>
+#include <sx1276-Hal.h>
+#include <sx1276-LoRa.h>
+#include <sx1276-LoRaMisc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SPI_LORA_FREQUENCY 10000000
+#define SPI_LORA_BUFFER_SIZE 256
+
+typedef struct SpiLoraDevice *SpiLoraDeviceType;
+
+struct LoraDevDone
+{
+    uint32 (*open) (void *dev);
+    uint32 (*close) (void *dev);
+    uint32 (*write) (void *dev, struct BusBlockWriteParam *write_param);
+    uint32 (*read) (void *dev, struct BusBlockReadParam *read_param);
+};
+
+struct SpiLoraDevice
+{
+    struct SpiHardwareDevice *spi_dev;
+    struct SpiHardwareDevice lora_dev;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_touch.h

@@ -0,0 +1,66 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_touch.h
+* @brief define aiit-riscv64-board touch function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_TOUCH_H
+#define CONNECT_TOUCH_H
+
+#include <device.h>
+#include "fpioa.h"
+#include "gpio.h" 
+#include <sleep.h>
+
+#define TP_CLK    0
+#define TP_CS       1
+#define TP_MISO  2
+#define TP_PEN    3
+#define TP_MOSI  4
+
+#define TP_PRES_DOWN 0x80  
+#define TP_CATH_PRES   0x40  
+
+//touch screen control struct
+typedef struct
+{
+	unsigned short x; 	
+	unsigned short y;					
+	unsigned char sta;								
+	float xfac;					
+	float yfac;
+	short xoff;
+	short yoff;	   
+	unsigned char touchtype;
+}touch_device_info;
+
+extern touch_device_info tp_dev;	 	
+
+//save data struct
+typedef struct 
+{
+    int ty_xfac;
+	int ty_yfac;
+    short x_pos;
+    short y_pos;
+    unsigned char iic_touchtype;        
+	unsigned char iic_flag;              
+}TP_modify_save;
+
+int HwTouchBusInit(void);
+ 
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_uart.h

@@ -0,0 +1,40 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_uart.h
+* @brief define aiit-riscv64-board uart function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_UART_H
+#define CONNECT_UART_H
+
+#include <device.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define KERNEL_CONSOLE_BUS_NAME       SERIAL_BUS_NAME_0
+#define KERNEL_CONSOLE_DRV_NAME        SERIAL_DRV_NAME_0
+#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_0_DEVICE_NAME_0
+
+int HwUartInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/connect_wdt.h

@@ -0,0 +1,36 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_wdt.h
+* @brief define aiit-riscv64-board wdt function and struct
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef CONNECT_WDT_H
+#define CONNECT_WDT_H
+
+#include <device.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int HwWdtInit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/drv_io_config.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-19     ZYH          first version
+ */
+
+/**
+* @file drv_io_config.h
+* @brief define aiit-riscv64-board io configure
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: drv_io_config.h
+Description: define aiit-riscv64-board io configure
+Others: take RT-Thread v4.0.2/bsp/k210/driver/drv_io_config.h for references
+                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: add aiit-riscv64-board io configure define
+*************************************************/
+
+#ifndef __DRV_IO_CONFIG_H__
+#define __DRV_IO_CONFIG_H__
+
+enum HS_GPIO_CONFIG
+{
+#ifdef BSP_USING_LCD
+    LCD_DC_PIN = 0,     /* LCD DC PIN */
+#endif
+#ifdef BSP_SPI1_USING_SS0
+    SPI1_CS0_PIN,
+#endif
+#ifdef BSP_SPI1_USING_SS1
+    SPI1_CS1_PIN,
+#endif
+#ifdef BSP_SPI1_USING_SS2
+    SPI1_CS2_PIN,
+#endif
+#ifdef BSP_SPI1_USING_SS3
+    SPI1_CS3_PIN,
+#endif
+    GPIO_ALLOC_START /* index of gpio driver start */
+};
+
+extern int IoConfigInit(void);
+
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/dvp.h

@@ -0,0 +1,279 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file dvp.h
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef __DVP_H__
+#define __DVP_H__
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* clang-format off */
+/**
+ * @brief       DVP object
+ */
+typedef struct _dvp
+{
+    uint32_t dvp_cfg;
+    uint32_t r_addr;
+    uint32_t g_addr;
+    uint32_t b_addr;
+    uint32_t cmos_cfg;
+    uint32_t sccb_cfg;
+    uint32_t sccb_ctl;
+    uint32_t axi;
+    uint32_t sts;
+    uint32_t reverse;
+    uint32_t rgb_addr;
+} __attribute__((packed, aligned(4))) dvp_t;
+
+/* DVP Config Register */
+#define DVP_CFG_START_INT_ENABLE                0x00000001U
+#define DVP_CFG_FINISH_INT_ENABLE               0x00000002U
+#define DVP_CFG_AI_OUTPUT_ENABLE                0x00000004U
+#define DVP_CFG_DISPLAY_OUTPUT_ENABLE           0x00000008U
+#define DVP_CFG_AUTO_ENABLE                     0x00000010U
+#define DVP_CFG_BURST_SIZE_4BEATS               0x00000100U
+#define DVP_CFG_FORMAT_MASK                     0x00000600U
+#define DVP_CFG_RGB_FORMAT                      0x00000000U
+#define DVP_CFG_YUV_FORMAT                      0x00000200U
+#define DVP_CFG_Y_FORMAT                        0x00000600U
+#define DVP_CFG_HREF_BURST_NUM_MASK             0x000FF000U
+#define DVP_CFG_HREF_BURST_NUM(x)               ((x) << 12)
+#define DVP_CFG_LINE_NUM_MASK                   0x3FF00000U
+#define DVP_CFG_LINE_NUM(x)                     ((x) << 20)
+
+/* DVP CMOS Config Register */
+#define DVP_CMOS_CLK_DIV_MASK                   0x000000FFU
+#define DVP_CMOS_CLK_DIV(x)                     ((x) << 0)
+#define DVP_CMOS_CLK_ENABLE                     0x00000100U
+#define DVP_CMOS_RESET                          0x00010000U
+#define DVP_CMOS_POWER_DOWN                     0x01000000U
+
+/* DVP SCCB Config Register */
+#define DVP_SCCB_BYTE_NUM_MASK                  0x00000003U
+#define DVP_SCCB_BYTE_NUM_2                     0x00000001U
+#define DVP_SCCB_BYTE_NUM_3                     0x00000002U
+#define DVP_SCCB_BYTE_NUM_4                     0x00000003U
+#define DVP_SCCB_SCL_LCNT_MASK                  0x0000FF00U
+#define DVP_SCCB_SCL_LCNT(x)                    ((x) << 8)
+#define DVP_SCCB_SCL_HCNT_MASK                  0x00FF0000U
+#define DVP_SCCB_SCL_HCNT(x)                    ((x) << 16)
+#define DVP_SCCB_RDATA_BYTE(x)                  ((x) >> 24)
+
+/* DVP SCCB Control Register */
+#define DVP_SCCB_WRITE_DATA_ENABLE                   0x00000001U
+#define DVP_SCCB_DEVICE_ADDRESS(x)              ((x) << 0)
+#define DVP_SCCB_REG_ADDRESS(x)                 ((x) << 8)
+#define DVP_SCCB_WDATA_BYTE0(x)                 ((x) << 16)
+#define DVP_SCCB_WDATA_BYTE1(x)                 ((x) << 24)
+
+/* DVP AXI Register */
+#define DVP_AXI_GM_MLEN_MASK                    0x000000FFU
+#define DVP_AXI_GM_MLEN_1BYTE                   0x00000000U
+#define DVP_AXI_GM_MLEN_4BYTE                   0x00000003U
+
+/* DVP STS Register */
+#define DVP_STS_FRAME_START                     0x00000001U
+#define DVP_STS_FRAME_START_WE                  0x00000002U
+#define DVP_STS_FRAME_FINISH                    0x00000100U
+#define DVP_STS_FRAME_FINISH_WE                 0x00000200U
+#define DVP_STS_DVP_EN                          0x00010000U
+#define DVP_STS_DVP_EN_WE                       0x00020000U
+#define DVP_STS_SCCB_EN                         0x01000000U
+#define DVP_STS_SCCB_EN_WE                      0x02000000U
+/* clang-format on */
+
+typedef enum _dvp_output_mode
+{
+    DVP_OUTPUT_AI,
+    DVP_OUTPUT_DISPLAY,
+} dvp_output_mode_t;
+
+/**
+ * @brief       DVP object instance
+ */
+extern volatile dvp_t* const dvp;
+
+/**
+ * @brief       Initialize DVP
+ */
+void dvp_init(uint8_t reg_len);
+
+/**
+ * @brief       Set image format
+ *
+ * @param[in]   format      The image format
+ */
+void dvp_set_image_format(uint32_t format);
+
+/**
+ * @brief       Set image size
+ *
+ * @param[in]   width   The width  of image
+ * @param[in]   height  The height of image
+ */
+void dvp_set_image_size(uint32_t width, uint32_t height);
+
+/**
+ * @brief       Set the address of RGB for AI
+ *
+ * @param[in]   r_addr      The R address of RGB
+ * @param[in]   g_addr      The G address of RGB
+ * @param[in]   b_addr      The B address of RGB
+ */
+void dvp_set_ai_addr(uint32_t r_addr, uint32_t g_addr, uint32_t b_addr);
+
+/**
+ * @brief       Set the address of RGB for display
+ *
+ * @param[in]   r_addr      The R address of RGB
+ * @param[in]   g_addr      The G address of RGB
+ * @param[in]   b_addr      The B address of RGB
+ */
+void dvp_set_display_addr(uint32_t addr);
+
+/**
+ * @brief       The frame start transfer
+ */
+void dvp_start_frame(void);
+
+/**
+ * @brief       The DVP convert start
+ */
+void dvp_start_convert(void);
+
+/**
+ * @brief       The DVP convert finish
+ */
+void dvp_finish_convert(void);
+
+/**
+ * @brief       Get the image data
+ *
+ * @note        The image data stored in the address of RGB
+ */
+void dvp_get_image(void);
+
+/**
+ * @brief       Use SCCB write register
+ *
+ * @param[in]   DevAddr        The device address
+ * @param[in]   reg_addr        The register address
+ * @param[in]   reg_data        The register data
+ */
+void dvp_sccb_send_data(uint8_t DevAddr, uint16_t reg_addr, uint8_t reg_data);
+
+/**
+ * @brief       Use SCCB read register
+ *
+ * @param[in]   DevAddr        The device address
+ * @param[in]   reg_addr        The register address
+ *
+ * @return      The register value
+ */
+uint8_t dvp_sccb_receive_data(uint8_t DevAddr, uint16_t reg_addr);
+
+/**
+ * @brief       Enable dvp burst
+ */
+void dvp_enable_burst(void);
+
+/**
+ * @brief       Disable dvp burst
+ */
+void dvp_disable_burst(void);
+
+/**
+ * @brief       Enable or disable dvp interrupt
+ *
+ * @param[in]   interrupt       Dvp interrupt
+ * @param[in]   status          0:disable 1:enable
+ *
+ */
+void dvp_config_interrupt(uint32_t interrupt, uint8_t enable);
+
+/**
+ * @brief       Get dvp interrupt status
+ *
+ * @param[in]   interrupt       Dvp interrupt
+ *
+ *
+ * @return      Interrupt status
+ *     - 0      false
+ *     - 1      true
+ */
+int dvp_get_interrupt(uint32_t interrupt);
+
+/**
+ * @brief       Clear dvp interrupt status
+ *
+ * @param[in]   interrupt       Dvp interrupt
+ *
+ */
+void dvp_clear_interrupt(uint32_t interrupt);
+
+/**
+ * @brief       Enable dvp auto mode
+ */
+void dvp_enable_auto(void);
+
+/**
+ * @brief       Disable dvp auto mode
+ */
+void dvp_disable_auto(void);
+
+/**
+ * @brief       Dvp ouput data enable or not
+ *
+ * @param[in]   index       0:AI, 1:display
+ * @param[in]   enable      0:disable, 1:enable
+ *
+ */
+void dvp_set_output_enable(dvp_output_mode_t index, int enable);
+
+/**
+ * @brief       Set sccb clock rate
+ *
+ * @param[in]   clk_rate       Sccb clock rate
+ *
+ * @return      The real sccb clock rate
+ */
+uint32_t dvp_sccb_set_clk_rate(uint32_t clk_rate);
+
+/**
+ * @brief       Set xclk rate
+ *
+ * @param[in]   clk_rate       xclk rate
+ *
+ * @return      The real xclk rate
+ */
+uint32_t dvp_set_xclk_rate(uint32_t xclk_rate);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DVP_H__ */

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/font.h

@@ -0,0 +1,425 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file font.h
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef __FONT_H__
+#define __FONT_H__ 	   
+//ASCII char table
+//offset 32 
+//ASCII char : !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~
+//bytes of a single char : (size/8+((size%8)?1:0))*(size/2), size : (12/16/24/32...) code table size
+
+//12*12 ASCII code
+const unsigned char asc2_1206[95][12]={
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/
+{0x00,0x00,0x00,0x00,0x3F,0x40,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/
+{0x00,0x00,0x30,0x00,0x40,0x00,0x30,0x00,0x40,0x00,0x00,0x00},/*""",2*/
+{0x09,0x00,0x0B,0xC0,0x3D,0x00,0x0B,0xC0,0x3D,0x00,0x09,0x00},/*"#",3*/
+{0x18,0xC0,0x24,0x40,0x7F,0xE0,0x22,0x40,0x31,0x80,0x00,0x00},/*"$",4*/
+{0x18,0x00,0x24,0xC0,0x1B,0x00,0x0D,0x80,0x32,0x40,0x01,0x80},/*"%",5*/
+{0x03,0x80,0x1C,0x40,0x27,0x40,0x1C,0x80,0x07,0x40,0x00,0x40},/*"&",6*/
+{0x10,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x80,0x20,0x40,0x40,0x20},/*"(",8*/
+{0x00,0x00,0x40,0x20,0x20,0x40,0x1F,0x80,0x00,0x00,0x00,0x00},/*")",9*/
+{0x09,0x00,0x06,0x00,0x1F,0x80,0x06,0x00,0x09,0x00,0x00,0x00},/*"*",10*/
+{0x04,0x00,0x04,0x00,0x3F,0x80,0x04,0x00,0x04,0x00,0x00,0x00},/*"+",11*/
+{0x00,0x10,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/
+{0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x00,0x00},/*"-",13*/
+{0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/
+{0x00,0x20,0x01,0xC0,0x06,0x00,0x38,0x00,0x40,0x00,0x00,0x00},/*"/",15*/
+{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"0",16*/
+{0x00,0x00,0x10,0x40,0x3F,0xC0,0x00,0x40,0x00,0x00,0x00,0x00},/*"1",17*/
+{0x18,0xC0,0x21,0x40,0x22,0x40,0x24,0x40,0x18,0x40,0x00,0x00},/*"2",18*/
+{0x10,0x80,0x20,0x40,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"3",19*/
+{0x02,0x00,0x0D,0x00,0x11,0x00,0x3F,0xC0,0x01,0x40,0x00,0x00},/*"4",20*/
+{0x3C,0x80,0x24,0x40,0x24,0x40,0x24,0x40,0x23,0x80,0x00,0x00},/*"5",21*/
+{0x1F,0x80,0x24,0x40,0x24,0x40,0x34,0x40,0x03,0x80,0x00,0x00},/*"6",22*/
+{0x30,0x00,0x20,0x00,0x27,0xC0,0x38,0x00,0x20,0x00,0x00,0x00},/*"7",23*/
+{0x1B,0x80,0x24,0x40,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"8",24*/
+{0x1C,0x00,0x22,0xC0,0x22,0x40,0x22,0x40,0x1F,0x80,0x00,0x00},/*"9",25*/
+{0x00,0x00,0x00,0x00,0x08,0x40,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/
+{0x00,0x00,0x00,0x00,0x04,0x60,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/
+{0x00,0x00,0x04,0x00,0x0A,0x00,0x11,0x00,0x20,0x80,0x40,0x40},/*"<",28*/
+{0x09,0x00,0x09,0x00,0x09,0x00,0x09,0x00,0x09,0x00,0x00,0x00},/*"=",29*/
+{0x00,0x00,0x40,0x40,0x20,0x80,0x11,0x00,0x0A,0x00,0x04,0x00},/*">",30*/
+{0x18,0x00,0x20,0x00,0x23,0x40,0x24,0x00,0x18,0x00,0x00,0x00},/*"?",31*/
+{0x1F,0x80,0x20,0x40,0x27,0x40,0x29,0x40,0x1F,0x40,0x00,0x00},/*"@",32*/
+{0x00,0x40,0x07,0xC0,0x39,0x00,0x0F,0x00,0x01,0xC0,0x00,0x40},/*"A",33*/
+{0x20,0x40,0x3F,0xC0,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"B",34*/
+{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x30,0x80,0x00,0x00},/*"C",35*/
+{0x20,0x40,0x3F,0xC0,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"D",36*/
+{0x20,0x40,0x3F,0xC0,0x24,0x40,0x2E,0x40,0x30,0xC0,0x00,0x00},/*"E",37*/
+{0x20,0x40,0x3F,0xC0,0x24,0x40,0x2E,0x00,0x30,0x00,0x00,0x00},/*"F",38*/
+{0x0F,0x00,0x10,0x80,0x20,0x40,0x22,0x40,0x33,0x80,0x02,0x00},/*"G",39*/
+{0x20,0x40,0x3F,0xC0,0x04,0x00,0x04,0x00,0x3F,0xC0,0x20,0x40},/*"H",40*/
+{0x20,0x40,0x20,0x40,0x3F,0xC0,0x20,0x40,0x20,0x40,0x00,0x00},/*"I",41*/
+{0x00,0x60,0x20,0x20,0x20,0x20,0x3F,0xC0,0x20,0x00,0x20,0x00},/*"J",42*/
+{0x20,0x40,0x3F,0xC0,0x24,0x40,0x0B,0x00,0x30,0xC0,0x20,0x40},/*"K",43*/
+{0x20,0x40,0x3F,0xC0,0x20,0x40,0x00,0x40,0x00,0x40,0x00,0xC0},/*"L",44*/
+{0x3F,0xC0,0x3C,0x00,0x03,0xC0,0x3C,0x00,0x3F,0xC0,0x00,0x00},/*"M",45*/
+{0x20,0x40,0x3F,0xC0,0x0C,0x40,0x23,0x00,0x3F,0xC0,0x20,0x00},/*"N",46*/
+{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"O",47*/
+{0x20,0x40,0x3F,0xC0,0x24,0x40,0x24,0x00,0x18,0x00,0x00,0x00},/*"P",48*/
+{0x1F,0x80,0x21,0x40,0x21,0x40,0x20,0xE0,0x1F,0xA0,0x00,0x00},/*"Q",49*/
+{0x20,0x40,0x3F,0xC0,0x24,0x40,0x26,0x00,0x19,0xC0,0x00,0x40},/*"R",50*/
+{0x18,0xC0,0x24,0x40,0x24,0x40,0x22,0x40,0x31,0x80,0x00,0x00},/*"S",51*/
+{0x30,0x00,0x20,0x40,0x3F,0xC0,0x20,0x40,0x30,0x00,0x00,0x00},/*"T",52*/
+{0x20,0x00,0x3F,0x80,0x00,0x40,0x00,0x40,0x3F,0x80,0x20,0x00},/*"U",53*/
+{0x20,0x00,0x3E,0x00,0x01,0xC0,0x07,0x00,0x38,0x00,0x20,0x00},/*"V",54*/
+{0x38,0x00,0x07,0xC0,0x3C,0x00,0x07,0xC0,0x38,0x00,0x00,0x00},/*"W",55*/
+{0x20,0x40,0x39,0xC0,0x06,0x00,0x39,0xC0,0x20,0x40,0x00,0x00},/*"X",56*/
+{0x20,0x00,0x38,0x40,0x07,0xC0,0x38,0x40,0x20,0x00,0x00,0x00},/*"Y",57*/
+{0x30,0x40,0x21,0xC0,0x26,0x40,0x38,0x40,0x20,0xC0,0x00,0x00},/*"Z",58*/
+{0x00,0x00,0x00,0x00,0x7F,0xE0,0x40,0x20,0x40,0x20,0x00,0x00},/*"[",59*/
+{0x00,0x00,0x70,0x00,0x0C,0x00,0x03,0x80,0x00,0x40,0x00,0x00},/*"\",60*/
+{0x00,0x00,0x40,0x20,0x40,0x20,0x7F,0xE0,0x00,0x00,0x00,0x00},/*"]",61*/
+{0x00,0x00,0x20,0x00,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x00},/*"^",62*/
+{0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10},/*"_",63*/
+{0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/
+{0x00,0x00,0x02,0x80,0x05,0x40,0x05,0x40,0x03,0xC0,0x00,0x40},/*"a",65*/
+{0x20,0x00,0x3F,0xC0,0x04,0x40,0x04,0x40,0x03,0x80,0x00,0x00},/*"b",66*/
+{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x40,0x06,0x40,0x00,0x00},/*"c",67*/
+{0x00,0x00,0x03,0x80,0x04,0x40,0x24,0x40,0x3F,0xC0,0x00,0x40},/*"d",68*/
+{0x00,0x00,0x03,0x80,0x05,0x40,0x05,0x40,0x03,0x40,0x00,0x00},/*"e",69*/
+{0x00,0x00,0x04,0x40,0x1F,0xC0,0x24,0x40,0x24,0x40,0x20,0x00},/*"f",70*/
+{0x00,0x00,0x02,0xE0,0x05,0x50,0x05,0x50,0x06,0x50,0x04,0x20},/*"g",71*/
+{0x20,0x40,0x3F,0xC0,0x04,0x40,0x04,0x00,0x03,0xC0,0x00,0x40},/*"h",72*/
+{0x00,0x00,0x04,0x40,0x27,0xC0,0x00,0x40,0x00,0x00,0x00,0x00},/*"i",73*/
+{0x00,0x10,0x00,0x10,0x04,0x10,0x27,0xE0,0x00,0x00,0x00,0x00},/*"j",74*/
+{0x20,0x40,0x3F,0xC0,0x01,0x40,0x07,0x00,0x04,0xC0,0x04,0x40},/*"k",75*/
+{0x20,0x40,0x20,0x40,0x3F,0xC0,0x00,0x40,0x00,0x40,0x00,0x00},/*"l",76*/
+{0x07,0xC0,0x04,0x00,0x07,0xC0,0x04,0x00,0x03,0xC0,0x00,0x00},/*"m",77*/
+{0x04,0x40,0x07,0xC0,0x04,0x40,0x04,0x00,0x03,0xC0,0x00,0x40},/*"n",78*/
+{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x40,0x03,0x80,0x00,0x00},/*"o",79*/
+{0x04,0x10,0x07,0xF0,0x04,0x50,0x04,0x40,0x03,0x80,0x00,0x00},/*"p",80*/
+{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x50,0x07,0xF0,0x00,0x10},/*"q",81*/
+{0x04,0x40,0x07,0xC0,0x02,0x40,0x04,0x00,0x04,0x00,0x00,0x00},/*"r",82*/
+{0x00,0x00,0x06,0x40,0x05,0x40,0x05,0x40,0x04,0xC0,0x00,0x00},/*"s",83*/
+{0x00,0x00,0x04,0x00,0x1F,0x80,0x04,0x40,0x00,0x40,0x00,0x00},/*"t",84*/
+{0x04,0x00,0x07,0x80,0x00,0x40,0x04,0x40,0x07,0xC0,0x00,0x40},/*"u",85*/
+{0x04,0x00,0x07,0x00,0x04,0xC0,0x01,0x80,0x06,0x00,0x04,0x00},/*"v",86*/
+{0x06,0x00,0x01,0xC0,0x07,0x00,0x01,0xC0,0x06,0x00,0x00,0x00},/*"w",87*/
+{0x04,0x40,0x06,0xC0,0x01,0x00,0x06,0xC0,0x04,0x40,0x00,0x00},/*"x",88*/
+{0x04,0x10,0x07,0x10,0x04,0xE0,0x01,0x80,0x06,0x00,0x04,0x00},/*"y",89*/
+{0x00,0x00,0x04,0x40,0x05,0xC0,0x06,0x40,0x04,0x40,0x00,0x00},/*"z",90*/
+{0x00,0x00,0x00,0x00,0x04,0x00,0x7B,0xE0,0x40,0x20,0x00,0x00},/*"{",91*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0x00},/*"|",92*/
+{0x00,0x00,0x40,0x20,0x7B,0xE0,0x04,0x00,0x00,0x00,0x00,0x00},/*"}",93*/
+{0x40,0x00,0x80,0x00,0x40,0x00,0x20,0x00,0x20,0x00,0x40,0x00},/*"~",94*/
+};  
+//16*16 ASCII鐎涙顑侀梿鍡欏仯闂冿拷
+const unsigned char asc2_1608[95][16]={	
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xCC,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/
+{0x00,0x00,0x08,0x00,0x30,0x00,0x60,0x00,0x08,0x00,0x30,0x00,0x60,0x00,0x00,0x00},/*""",2*/
+{0x02,0x20,0x03,0xFC,0x1E,0x20,0x02,0x20,0x03,0xFC,0x1E,0x20,0x02,0x20,0x00,0x00},/*"#",3*/
+{0x00,0x00,0x0E,0x18,0x11,0x04,0x3F,0xFF,0x10,0x84,0x0C,0x78,0x00,0x00,0x00,0x00},/*"$",4*/
+{0x0F,0x00,0x10,0x84,0x0F,0x38,0x00,0xC0,0x07,0x78,0x18,0x84,0x00,0x78,0x00,0x00},/*"%",5*/
+{0x00,0x78,0x0F,0x84,0x10,0xC4,0x11,0x24,0x0E,0x98,0x00,0xE4,0x00,0x84,0x00,0x08},/*"&",6*/
+{0x08,0x00,0x68,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xE0,0x18,0x18,0x20,0x04,0x40,0x02,0x00,0x00},/*"(",8*/
+{0x00,0x00,0x40,0x02,0x20,0x04,0x18,0x18,0x07,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*")",9*/
+{0x02,0x40,0x02,0x40,0x01,0x80,0x0F,0xF0,0x01,0x80,0x02,0x40,0x02,0x40,0x00,0x00},/*"*",10*/
+{0x00,0x80,0x00,0x80,0x00,0x80,0x0F,0xF8,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x00},/*"+",11*/
+{0x00,0x01,0x00,0x0D,0x00,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/
+{0x00,0x00,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80},/*"-",13*/
+{0x00,0x00,0x00,0x0C,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/
+{0x00,0x00,0x00,0x06,0x00,0x18,0x00,0x60,0x01,0x80,0x06,0x00,0x18,0x00,0x20,0x00},/*"/",15*/
+{0x00,0x00,0x07,0xF0,0x08,0x08,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"0",16*/
+{0x00,0x00,0x08,0x04,0x08,0x04,0x1F,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"1",17*/
+{0x00,0x00,0x0E,0x0C,0x10,0x14,0x10,0x24,0x10,0x44,0x11,0x84,0x0E,0x0C,0x00,0x00},/*"2",18*/
+{0x00,0x00,0x0C,0x18,0x10,0x04,0x11,0x04,0x11,0x04,0x12,0x88,0x0C,0x70,0x00,0x00},/*"3",19*/
+{0x00,0x00,0x00,0xE0,0x03,0x20,0x04,0x24,0x08,0x24,0x1F,0xFC,0x00,0x24,0x00,0x00},/*"4",20*/
+{0x00,0x00,0x1F,0x98,0x10,0x84,0x11,0x04,0x11,0x04,0x10,0x88,0x10,0x70,0x00,0x00},/*"5",21*/
+{0x00,0x00,0x07,0xF0,0x08,0x88,0x11,0x04,0x11,0x04,0x18,0x88,0x00,0x70,0x00,0x00},/*"6",22*/
+{0x00,0x00,0x1C,0x00,0x10,0x00,0x10,0xFC,0x13,0x00,0x1C,0x00,0x10,0x00,0x00,0x00},/*"7",23*/
+{0x00,0x00,0x0E,0x38,0x11,0x44,0x10,0x84,0x10,0x84,0x11,0x44,0x0E,0x38,0x00,0x00},/*"8",24*/
+{0x00,0x00,0x07,0x00,0x08,0x8C,0x10,0x44,0x10,0x44,0x08,0x88,0x07,0xF0,0x00,0x00},/*"9",25*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x0C,0x03,0x0C,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/
+{0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/
+{0x00,0x00,0x00,0x80,0x01,0x40,0x02,0x20,0x04,0x10,0x08,0x08,0x10,0x04,0x00,0x00},/*"<",28*/
+{0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x00,0x00},/*"=",29*/
+{0x00,0x00,0x10,0x04,0x08,0x08,0x04,0x10,0x02,0x20,0x01,0x40,0x00,0x80,0x00,0x00},/*">",30*/
+{0x00,0x00,0x0E,0x00,0x12,0x00,0x10,0x0C,0x10,0x6C,0x10,0x80,0x0F,0x00,0x00,0x00},/*"?",31*/
+{0x03,0xE0,0x0C,0x18,0x13,0xE4,0x14,0x24,0x17,0xC4,0x08,0x28,0x07,0xD0,0x00,0x00},/*"@",32*/
+{0x00,0x04,0x00,0x3C,0x03,0xC4,0x1C,0x40,0x07,0x40,0x00,0xE4,0x00,0x1C,0x00,0x04},/*"A",33*/
+{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x04,0x11,0x04,0x0E,0x88,0x00,0x70,0x00,0x00},/*"B",34*/
+{0x03,0xE0,0x0C,0x18,0x10,0x04,0x10,0x04,0x10,0x04,0x10,0x08,0x1C,0x10,0x00,0x00},/*"C",35*/
+{0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"D",36*/
+{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x04,0x17,0xC4,0x10,0x04,0x08,0x18,0x00,0x00},/*"E",37*/
+{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x00,0x17,0xC0,0x10,0x00,0x08,0x00,0x00,0x00},/*"F",38*/
+{0x03,0xE0,0x0C,0x18,0x10,0x04,0x10,0x04,0x10,0x44,0x1C,0x78,0x00,0x40,0x00,0x00},/*"G",39*/
+{0x10,0x04,0x1F,0xFC,0x10,0x84,0x00,0x80,0x00,0x80,0x10,0x84,0x1F,0xFC,0x10,0x04},/*"H",40*/
+{0x00,0x00,0x10,0x04,0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x04,0x00,0x00,0x00,0x00},/*"I",41*/
+{0x00,0x03,0x00,0x01,0x10,0x01,0x10,0x01,0x1F,0xFE,0x10,0x00,0x10,0x00,0x00,0x00},/*"J",42*/
+{0x10,0x04,0x1F,0xFC,0x11,0x04,0x03,0x80,0x14,0x64,0x18,0x1C,0x10,0x04,0x00,0x00},/*"K",43*/
+{0x10,0x04,0x1F,0xFC,0x10,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x0C,0x00,0x00},/*"L",44*/
+{0x10,0x04,0x1F,0xFC,0x1F,0x00,0x00,0xFC,0x1F,0x00,0x1F,0xFC,0x10,0x04,0x00,0x00},/*"M",45*/
+{0x10,0x04,0x1F,0xFC,0x0C,0x04,0x03,0x00,0x00,0xE0,0x10,0x18,0x1F,0xFC,0x10,0x00},/*"N",46*/
+{0x07,0xF0,0x08,0x08,0x10,0x04,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"O",47*/
+{0x10,0x04,0x1F,0xFC,0x10,0x84,0x10,0x80,0x10,0x80,0x10,0x80,0x0F,0x00,0x00,0x00},/*"P",48*/
+{0x07,0xF0,0x08,0x18,0x10,0x24,0x10,0x24,0x10,0x1C,0x08,0x0A,0x07,0xF2,0x00,0x00},/*"Q",49*/
+{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x00,0x11,0xC0,0x11,0x30,0x0E,0x0C,0x00,0x04},/*"R",50*/
+{0x00,0x00,0x0E,0x1C,0x11,0x04,0x10,0x84,0x10,0x84,0x10,0x44,0x1C,0x38,0x00,0x00},/*"S",51*/
+{0x18,0x00,0x10,0x00,0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x00,0x18,0x00,0x00,0x00},/*"T",52*/
+{0x10,0x00,0x1F,0xF8,0x10,0x04,0x00,0x04,0x00,0x04,0x10,0x04,0x1F,0xF8,0x10,0x00},/*"U",53*/
+{0x10,0x00,0x1E,0x00,0x11,0xE0,0x00,0x1C,0x00,0x70,0x13,0x80,0x1C,0x00,0x10,0x00},/*"V",54*/
+{0x1F,0xC0,0x10,0x3C,0x00,0xE0,0x1F,0x00,0x00,0xE0,0x10,0x3C,0x1F,0xC0,0x00,0x00},/*"W",55*/
+{0x10,0x04,0x18,0x0C,0x16,0x34,0x01,0xC0,0x01,0xC0,0x16,0x34,0x18,0x0C,0x10,0x04},/*"X",56*/
+{0x10,0x00,0x1C,0x00,0x13,0x04,0x00,0xFC,0x13,0x04,0x1C,0x00,0x10,0x00,0x00,0x00},/*"Y",57*/
+{0x08,0x04,0x10,0x1C,0x10,0x64,0x10,0x84,0x13,0x04,0x1C,0x04,0x10,0x18,0x00,0x00},/*"Z",58*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFE,0x40,0x02,0x40,0x02,0x40,0x02,0x00,0x00},/*"[",59*/
+{0x00,0x00,0x30,0x00,0x0C,0x00,0x03,0x80,0x00,0x60,0x00,0x1C,0x00,0x03,0x00,0x00},/*"\",60*/
+{0x00,0x00,0x40,0x02,0x40,0x02,0x40,0x02,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00},/*"]",61*/
+{0x00,0x00,0x00,0x00,0x20,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x00,0x00},/*"^",62*/
+{0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01},/*"_",63*/
+{0x00,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/
+{0x00,0x00,0x00,0x98,0x01,0x24,0x01,0x44,0x01,0x44,0x01,0x44,0x00,0xFC,0x00,0x04},/*"a",65*/
+{0x10,0x00,0x1F,0xFC,0x00,0x88,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x70,0x00,0x00},/*"b",66*/
+{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x00},/*"c",67*/
+{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x11,0x08,0x1F,0xFC,0x00,0x04},/*"d",68*/
+{0x00,0x00,0x00,0xF8,0x01,0x44,0x01,0x44,0x01,0x44,0x01,0x44,0x00,0xC8,0x00,0x00},/*"e",69*/
+{0x00,0x00,0x01,0x04,0x01,0x04,0x0F,0xFC,0x11,0x04,0x11,0x04,0x11,0x00,0x18,0x00},/*"f",70*/
+{0x00,0x00,0x00,0xD6,0x01,0x29,0x01,0x29,0x01,0x29,0x01,0xC9,0x01,0x06,0x00,0x00},/*"g",71*/
+{0x10,0x04,0x1F,0xFC,0x00,0x84,0x01,0x00,0x01,0x00,0x01,0x04,0x00,0xFC,0x00,0x04},/*"h",72*/
+{0x00,0x00,0x01,0x04,0x19,0x04,0x19,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"i",73*/
+{0x00,0x00,0x00,0x03,0x00,0x01,0x01,0x01,0x19,0x01,0x19,0xFE,0x00,0x00,0x00,0x00},/*"j",74*/
+{0x10,0x04,0x1F,0xFC,0x00,0x24,0x00,0x40,0x01,0xB4,0x01,0x0C,0x01,0x04,0x00,0x00},/*"k",75*/
+{0x00,0x00,0x10,0x04,0x10,0x04,0x1F,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"l",76*/
+{0x01,0x04,0x01,0xFC,0x01,0x04,0x01,0x00,0x01,0xFC,0x01,0x04,0x01,0x00,0x00,0xFC},/*"m",77*/
+{0x01,0x04,0x01,0xFC,0x00,0x84,0x01,0x00,0x01,0x00,0x01,0x04,0x00,0xFC,0x00,0x04},/*"n",78*/
+{0x00,0x00,0x00,0xF8,0x01,0x04,0x01,0x04,0x01,0x04,0x01,0x04,0x00,0xF8,0x00,0x00},/*"o",79*/
+{0x01,0x01,0x01,0xFF,0x00,0x85,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x70,0x00,0x00},/*"p",80*/
+{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x01,0x05,0x01,0xFF,0x00,0x01},/*"q",81*/
+{0x01,0x04,0x01,0x04,0x01,0xFC,0x00,0x84,0x01,0x04,0x01,0x00,0x01,0x80,0x00,0x00},/*"r",82*/
+{0x00,0x00,0x00,0xCC,0x01,0x24,0x01,0x24,0x01,0x24,0x01,0x24,0x01,0x98,0x00,0x00},/*"s",83*/
+{0x00,0x00,0x01,0x00,0x01,0x00,0x07,0xF8,0x01,0x04,0x01,0x04,0x00,0x00,0x00,0x00},/*"t",84*/
+{0x01,0x00,0x01,0xF8,0x00,0x04,0x00,0x04,0x00,0x04,0x01,0x08,0x01,0xFC,0x00,0x04},/*"u",85*/
+{0x01,0x00,0x01,0x80,0x01,0x70,0x00,0x0C,0x00,0x10,0x01,0x60,0x01,0x80,0x01,0x00},/*"v",86*/
+{0x01,0xF0,0x01,0x0C,0x00,0x30,0x01,0xC0,0x00,0x30,0x01,0x0C,0x01,0xF0,0x01,0x00},/*"w",87*/
+{0x00,0x00,0x01,0x04,0x01,0x8C,0x00,0x74,0x01,0x70,0x01,0x8C,0x01,0x04,0x00,0x00},/*"x",88*/
+{0x01,0x01,0x01,0x81,0x01,0x71,0x00,0x0E,0x00,0x18,0x01,0x60,0x01,0x80,0x01,0x00},/*"y",89*/
+{0x00,0x00,0x01,0x84,0x01,0x0C,0x01,0x34,0x01,0x44,0x01,0x84,0x01,0x0C,0x00,0x00},/*"z",90*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x3E,0xFC,0x40,0x02,0x40,0x02},/*"{",91*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00},/*"|",92*/
+{0x00,0x00,0x40,0x02,0x40,0x02,0x3E,0xFC,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"}",93*/
+{0x00,0x00,0x60,0x00,0x80,0x00,0x80,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x20,0x00},/*"~",94*/
+};  
+//24*24 ASCII code
+const unsigned char asc2_2412[95][36]={	  
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x80,0x38,0x0F,0xFE,0x38,0x0F,0x80,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x06,0x00,0x00,0x0C,0x00,0x00,0x38,0x00,0x00,0x31,0x00,0x00,0x06,0x00,0x00,0x0C,0x00,0x00,0x38,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00},/*""",2*/
+{0x00,0x00,0x00,0x00,0x61,0x80,0x00,0x67,0xF8,0x07,0xF9,0x80,0x00,0x61,0x80,0x00,0x61,0x80,0x00,0x61,0x80,0x00,0x61,0x80,0x00,0x67,0xF8,0x07,0xF9,0x80,0x00,0x61,0x80,0x00,0x00,0x00},/*"#",3*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xC0,0xE0,0x03,0xE0,0xF0,0x06,0x30,0x08,0x04,0x18,0x08,0x1F,0xFF,0xFE,0x04,0x0E,0x08,0x07,0x87,0xF0,0x03,0x81,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*"$",4*/
+{0x01,0xF0,0x00,0x06,0x0C,0x00,0x04,0x04,0x08,0x06,0x0C,0x70,0x01,0xF9,0xC0,0x00,0x0E,0x00,0x00,0x3B,0xE0,0x00,0xEC,0x18,0x07,0x08,0x08,0x04,0x0C,0x18,0x00,0x03,0xE0,0x00,0x00,0x00},/*"%",5*/
+{0x00,0x01,0xE0,0x00,0x07,0xF0,0x03,0xF8,0x18,0x04,0x1C,0x08,0x04,0x17,0x08,0x07,0xE1,0xD0,0x03,0xC0,0xE0,0x00,0x23,0xB0,0x00,0x3C,0x08,0x00,0x20,0x08,0x00,0x00,0x10,0x00,0x00,0x00},/*"&",6*/
+{0x00,0x00,0x00,0x01,0x00,0x00,0x31,0x00,0x00,0x32,0x00,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x00,0x01,0xFF,0xC0,0x07,0x80,0xF0,0x0C,0x00,0x18,0x10,0x00,0x04,0x20,0x00,0x02,0x00,0x00,0x00},/*"(",8*/
+{0x00,0x00,0x00,0x20,0x00,0x02,0x10,0x00,0x04,0x0C,0x00,0x18,0x07,0x80,0xF0,0x01,0xFF,0xC0,0x00,0x7F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*")",9*/
+{0x00,0x00,0x00,0x00,0x42,0x00,0x00,0x66,0x00,0x00,0x66,0x00,0x00,0x3C,0x00,0x00,0x18,0x00,0x03,0xFF,0xC0,0x00,0x18,0x00,0x00,0x3C,0x00,0x00,0x66,0x00,0x00,0x66,0x00,0x00,0x42,0x00},/*"*",10*/
+{0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x01,0xFF,0xC0,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00},/*"+",11*/
+{0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x31,0x00,0x00,0x32,0x00,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/
+{0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00},/*"-",13*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x00,0x00,0x38,0x00,0x00,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/
+{0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x1C,0x00,0x00,0x70,0x00,0x01,0x80,0x00,0x0E,0x00,0x00,0x38,0x00,0x00,0xC0,0x00,0x07,0x00,0x00,0x1C,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00},/*"/",15*/
+{0x00,0x00,0x00,0x00,0x7F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x18,0x04,0x00,0x08,0x04,0x00,0x08,0x06,0x00,0x18,0x03,0x80,0x70,0x01,0xFF,0xE0,0x00,0x7F,0x80,0x00,0x00,0x00},/*"0",16*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x08,0x01,0x00,0x08,0x01,0x00,0x08,0x03,0xFF,0xF8,0x07,0xFF,0xF8,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"1",17*/
+{0x00,0x00,0x00,0x01,0xC0,0x38,0x02,0xC0,0x58,0x04,0x00,0x98,0x04,0x01,0x18,0x04,0x02,0x18,0x04,0x04,0x18,0x06,0x1C,0x18,0x03,0xF8,0x18,0x01,0xE0,0xF8,0x00,0x00,0x00,0x00,0x00,0x00},/*"2",18*/
+{0x00,0x00,0x00,0x01,0xC0,0xE0,0x03,0xC0,0xF0,0x04,0x00,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x06,0x18,0x08,0x03,0xF4,0x18,0x01,0xE7,0xF0,0x00,0x01,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*"3",19*/
+{0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x0D,0x00,0x00,0x11,0x00,0x00,0x61,0x00,0x00,0x81,0x08,0x03,0x01,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x01,0x08,0x00,0x01,0x08,0x00,0x00,0x00},/*"4",20*/
+{0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0xFC,0xD0,0x06,0x08,0x08,0x06,0x10,0x08,0x06,0x10,0x08,0x06,0x10,0x08,0x06,0x18,0x38,0x06,0x0F,0xF0,0x06,0x07,0xC0,0x00,0x00,0x00,0x00,0x00,0x00},/*"5",21*/
+{0x00,0x00,0x00,0x00,0x3F,0x80,0x01,0xFF,0xE0,0x03,0x84,0x30,0x02,0x08,0x18,0x04,0x10,0x08,0x04,0x10,0x08,0x04,0x10,0x08,0x07,0x18,0x10,0x03,0x0F,0xF0,0x00,0x07,0xC0,0x00,0x00,0x00},/*"6",22*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xC0,0x00,0x07,0x00,0x00,0x06,0x00,0x00,0x06,0x00,0xF8,0x06,0x07,0xF8,0x06,0x18,0x00,0x06,0xE0,0x00,0x07,0x00,0x00,0x06,0x00,0x00,0x00,0x00,0x00},/*"7",23*/
+{0x00,0x00,0x00,0x01,0xE1,0xE0,0x03,0xF7,0xF0,0x06,0x34,0x10,0x04,0x18,0x08,0x04,0x18,0x08,0x04,0x0C,0x08,0x04,0x0C,0x08,0x06,0x16,0x18,0x03,0xF3,0xF0,0x01,0xC1,0xE0,0x00,0x00,0x00},/*"8",24*/
+{0x00,0x00,0x00,0x00,0xF8,0x00,0x03,0xFC,0x30,0x03,0x06,0x38,0x04,0x02,0x08,0x04,0x02,0x08,0x04,0x02,0x08,0x04,0x04,0x10,0x03,0x08,0xF0,0x01,0xFF,0xC0,0x00,0x7F,0x00,0x00,0x00,0x00},/*"9",25*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x38,0x00,0x70,0x38,0x00,0x70,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x1A,0x00,0x30,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x14,0x00,0x00,0x22,0x00,0x00,0x41,0x00,0x00,0x80,0x80,0x01,0x00,0x40,0x02,0x00,0x20,0x04,0x00,0x10,0x08,0x00,0x08,0x00,0x00,0x00},/*"<",28*/
+{0x00,0x00,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x00,0x00},/*"=",29*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x08,0x04,0x00,0x10,0x02,0x00,0x20,0x01,0x00,0x40,0x00,0x80,0x80,0x00,0x41,0x00,0x00,0x22,0x00,0x00,0x14,0x00,0x00,0x08,0x00,0x00,0x00,0x00},/*">",30*/
+{0x00,0x00,0x00,0x03,0xC0,0x00,0x04,0xC0,0x00,0x04,0x00,0x00,0x08,0x00,0x38,0x08,0x0F,0x38,0x08,0x08,0x38,0x08,0x10,0x00,0x0C,0x30,0x00,0x07,0xE0,0x00,0x03,0xC0,0x00,0x00,0x00,0x00},/*"?",31*/
+{0x00,0x00,0x00,0x00,0x3F,0x80,0x00,0xFF,0xE0,0x03,0x80,0x70,0x02,0x0F,0x10,0x06,0x70,0x88,0x04,0xC0,0x88,0x04,0x83,0x08,0x04,0x7F,0x88,0x02,0xC0,0x90,0x03,0x01,0x20,0x00,0xFE,0x40},/*"@",32*/
+{0x00,0x00,0x08,0x00,0x00,0x18,0x00,0x01,0xF8,0x00,0x3E,0x08,0x01,0xC2,0x00,0x07,0x02,0x00,0x07,0xE2,0x00,0x00,0xFE,0x00,0x00,0x1F,0xC8,0x00,0x01,0xF8,0x00,0x00,0x38,0x00,0x00,0x08},/*"A",33*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x06,0x18,0x08,0x03,0xF4,0x18,0x01,0xE7,0xF0,0x00,0x01,0xE0,0x00,0x00,0x00},/*"B",34*/
+{0x00,0x00,0x00,0x00,0x3F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x02,0x00,0x18,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x10,0x06,0x00,0x20,0x07,0x80,0xC0,0x00,0x00,0x00},/*"C",35*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x18,0x02,0x00,0x10,0x03,0x80,0x70,0x01,0xFF,0xE0,0x00,0x7F,0x80,0x00,0x00,0x00},/*"D",36*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x3E,0x08,0x04,0x00,0x08,0x06,0x00,0x18,0x01,0x00,0x60,0x00,0x00,0x00},/*"E",37*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x00,0x04,0x08,0x00,0x04,0x08,0x00,0x04,0x3E,0x00,0x06,0x00,0x00,0x06,0x00,0x00,0x01,0x80,0x00,0x00,0x00,0x00},/*"F",38*/
+{0x00,0x00,0x00,0x00,0x3F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x18,0x04,0x00,0x08,0x04,0x02,0x08,0x04,0x02,0x08,0x02,0x03,0xF0,0x07,0x83,0xF0,0x00,0x02,0x00,0x00,0x02,0x00},/*"G",39*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x04,0x08,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08},/*"H",40*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"I",41*/
+{0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x07,0x00,0x00,0x01,0x04,0x00,0x01,0x04,0x00,0x01,0x04,0x00,0x03,0x07,0xFF,0xFE,0x07,0xFF,0xFC,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00},/*"J",42*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x0C,0x08,0x00,0x18,0x00,0x00,0x3E,0x00,0x04,0xC7,0x80,0x05,0x03,0xC8,0x06,0x00,0xF8,0x04,0x00,0x38,0x04,0x00,0x18,0x00,0x00,0x08},/*"K",43*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x18,0x00,0x00,0x60,0x00,0x00,0x00},/*"L",44*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0x80,0x08,0x07,0xFC,0x00,0x00,0x7F,0xC0,0x00,0x03,0xF8,0x00,0x07,0xC0,0x00,0x78,0x00,0x07,0x80,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08},/*"M",45*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0x00,0x08,0x03,0xC0,0x00,0x00,0xE0,0x00,0x00,0x38,0x00,0x00,0x1E,0x00,0x00,0x07,0x00,0x00,0x01,0xC0,0x04,0x00,0xF0,0x07,0xFF,0xF8,0x04,0x00,0x00},/*"N",46*/
+{0x00,0x00,0x00,0x00,0x7F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x18,0x04,0x00,0x08,0x04,0x00,0x08,0x06,0x00,0x18,0x03,0x00,0x30,0x01,0xFF,0xE0,0x00,0x7F,0x80,0x00,0x00,0x00},/*"O",47*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x04,0x08,0x04,0x04,0x00,0x04,0x04,0x00,0x04,0x04,0x00,0x04,0x04,0x00,0x06,0x0C,0x00,0x03,0xF8,0x00,0x01,0xF0,0x00,0x00,0x00,0x00},/*"P",48*/
+{0x00,0x00,0x00,0x00,0x7F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x88,0x04,0x00,0x88,0x04,0x00,0xC8,0x06,0x00,0x3C,0x03,0x00,0x3E,0x01,0xFF,0xE6,0x00,0x7F,0x84,0x00,0x00,0x00},/*"Q",49*/
+{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x00,0x04,0x0C,0x00,0x04,0x0F,0x00,0x04,0x0B,0xC0,0x06,0x10,0xF0,0x03,0xF0,0x38,0x01,0xE0,0x08,0x00,0x00,0x08},/*"R",50*/
+{0x00,0x00,0x00,0x01,0xE0,0xF8,0x03,0xF0,0x30,0x06,0x30,0x10,0x04,0x18,0x08,0x04,0x18,0x08,0x04,0x0C,0x08,0x04,0x0C,0x08,0x02,0x06,0x18,0x02,0x07,0xF0,0x07,0x81,0xE0,0x00,0x00,0x00},/*"S",51*/
+{0x01,0x80,0x00,0x06,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x04,0x00,0x00,0x04,0x00,0x00,0x06,0x00,0x00,0x01,0x80,0x00},/*"T",52*/
+{0x04,0x00,0x00,0x07,0xFF,0xE0,0x07,0xFF,0xF0,0x04,0x00,0x18,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x04,0x00,0x10,0x07,0xFF,0xE0,0x04,0x00,0x00},/*"U",53*/
+{0x04,0x00,0x00,0x06,0x00,0x00,0x07,0xE0,0x00,0x07,0xFE,0x00,0x04,0x1F,0xE0,0x00,0x01,0xF8,0x00,0x00,0x38,0x00,0x01,0xE0,0x04,0x3E,0x00,0x07,0xC0,0x00,0x06,0x00,0x00,0x04,0x00,0x00},/*"V",54*/
+{0x04,0x00,0x00,0x07,0xE0,0x00,0x07,0xFF,0xC0,0x04,0x1F,0xF8,0x00,0x07,0xC0,0x07,0xF8,0x00,0x07,0xFF,0x80,0x04,0x3F,0xF8,0x00,0x07,0xC0,0x04,0xF8,0x00,0x07,0x00,0x00,0x04,0x00,0x00},/*"W",55*/
+{0x00,0x00,0x00,0x04,0x00,0x08,0x06,0x00,0x18,0x07,0xC0,0x78,0x05,0xF1,0xC8,0x00,0x3E,0x00,0x00,0x1F,0x80,0x04,0x63,0xE8,0x07,0x80,0xF8,0x06,0x00,0x18,0x04,0x00,0x08,0x00,0x00,0x00},/*"X",56*/
+{0x04,0x00,0x00,0x06,0x00,0x00,0x07,0x80,0x00,0x07,0xE0,0x08,0x04,0x7C,0x08,0x00,0x1F,0xF8,0x00,0x07,0xF8,0x00,0x18,0x08,0x04,0xE0,0x08,0x07,0x00,0x00,0x06,0x00,0x00,0x04,0x00,0x00},/*"Y",57*/
+{0x00,0x00,0x00,0x01,0x00,0x08,0x06,0x00,0x38,0x04,0x00,0xF8,0x04,0x03,0xE8,0x04,0x0F,0x08,0x04,0x7C,0x08,0x05,0xF0,0x08,0x07,0xC0,0x08,0x07,0x00,0x18,0x04,0x00,0x60,0x00,0x00,0x00},/*"Z",58*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFE,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x00,0x00,0x00},/*"[",59*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x07,0x00,0x00,0x00,0xC0,0x00,0x00,0x38,0x00,0x00,0x06,0x00,0x00,0x01,0xC0,0x00,0x00,0x30,0x00,0x00,0x0E,0x00,0x00,0x01,0x00,0x00,0x00},/*"\",60*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x3F,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"]",61*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x10,0x00,0x00,0x30,0x00,0x00,0x20,0x00,0x00,0x30,0x00,0x00,0x10,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"^",62*/
+{0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01},/*"_",63*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x10,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/
+{0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x19,0xF8,0x00,0x1B,0x18,0x00,0x22,0x08,0x00,0x26,0x08,0x00,0x24,0x08,0x00,0x24,0x10,0x00,0x3F,0xF8,0x00,0x1F,0xF8,0x00,0x00,0x08,0x00,0x00,0x18},/*"a",65*/
+{0x00,0x00,0x00,0x04,0x00,0x00,0x07,0xFF,0xF8,0x0F,0xFF,0xF0,0x00,0x18,0x18,0x00,0x10,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x30,0x18,0x00,0x1F,0xF0,0x00,0x0F,0xC0,0x00,0x00,0x00},/*"b",66*/
+{0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x18,0x30,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x3C,0x08,0x00,0x1C,0x10,0x00,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00},/*"c",67*/
+{0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x38,0x18,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x04,0x10,0x10,0x07,0xFF,0xF8,0x0F,0xFF,0xF0,0x00,0x00,0x10,0x00,0x00,0x00},/*"d",68*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x12,0x30,0x00,0x22,0x18,0x00,0x22,0x08,0x00,0x22,0x08,0x00,0x32,0x08,0x00,0x1E,0x10,0x00,0x0E,0x20,0x00,0x00,0x00},/*"e",69*/
+{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x20,0x08,0x00,0x20,0x08,0x01,0xFF,0xF8,0x03,0xFF,0xF8,0x06,0x20,0x08,0x04,0x20,0x08,0x04,0x20,0x08,0x07,0x20,0x00,0x03,0x00,0x00,0x00,0x00,0x00},/*"f",70*/
+{0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x0E,0x6E,0x00,0x1F,0xF3,0x00,0x31,0xB1,0x00,0x20,0xB1,0x00,0x20,0xB1,0x00,0x31,0x91,0x00,0x1F,0x13,0x00,0x2E,0x1E,0x00,0x20,0x0E,0x00,0x30,0x00},/*"g",71*/
+{0x00,0x00,0x00,0x04,0x00,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x10,0x08,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x1F,0xF8,0x00,0x00,0x08,0x00,0x00,0x00},/*"h",72*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x06,0x3F,0xF8,0x06,0x3F,0xF8,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"i",73*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x03,0x00,0x20,0x01,0x00,0x20,0x01,0x00,0x20,0x03,0x06,0x3F,0xFE,0x06,0x3F,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"j",74*/
+{0x00,0x00,0x00,0x04,0x00,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x01,0x88,0x00,0x03,0x00,0x00,0x2F,0xC0,0x00,0x38,0xF8,0x00,0x20,0x38,0x00,0x20,0x08,0x00,0x00,0x08,0x00,0x00,0x00},/*"k",75*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"l",76*/
+{0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x10,0x08,0x00,0x20,0x00,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x10,0x08,0x00,0x20,0x00,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x00,0x08},/*"m",77*/
+{0x00,0x00,0x00,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x10,0x08,0x00,0x10,0x00,0x00,0x20,0x00,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x1F,0xF8,0x00,0x00,0x08,0x00,0x00,0x00},/*"n",78*/
+{0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x0F,0xF0,0x00,0x18,0x30,0x00,0x30,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x30,0x08,0x00,0x18,0x30,0x00,0x0F,0xF0,0x00,0x07,0xC0,0x00,0x00,0x00},/*"o",79*/
+{0x00,0x00,0x00,0x00,0x20,0x01,0x00,0x3F,0xFF,0x00,0x3F,0xFF,0x00,0x10,0x11,0x00,0x20,0x09,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x30,0x38,0x00,0x1F,0xF0,0x00,0x0F,0xC0,0x00,0x00,0x00},/*"p",80*/
+{0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x38,0x18,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x09,0x00,0x10,0x11,0x00,0x1F,0xFF,0x00,0x3F,0xFF,0x00,0x00,0x01,0x00,0x00,0x00},/*"q",81*/
+{0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x08,0x08,0x00,0x10,0x08,0x00,0x20,0x08,0x00,0x20,0x00,0x00,0x30,0x00,0x00,0x30,0x00,0x00,0x00,0x00},/*"r",82*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x78,0x00,0x1E,0x18,0x00,0x33,0x08,0x00,0x23,0x08,0x00,0x21,0x08,0x00,0x21,0x88,0x00,0x21,0x98,0x00,0x30,0xF0,0x00,0x38,0x60,0x00,0x00,0x00},/*"s",83*/
+{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0xFF,0xF0,0x03,0xFF,0xF8,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00,0x00},/*"t",84*/
+{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x3F,0xF0,0x00,0x7F,0xF8,0x00,0x00,0x18,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x20,0x10,0x00,0x3F,0xF8,0x00,0x7F,0xF0,0x00,0x00,0x10,0x00,0x00,0x00},/*"u",85*/
+{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x30,0x00,0x00,0x3C,0x00,0x00,0x3F,0x80,0x00,0x23,0xF0,0x00,0x00,0x78,0x00,0x00,0x70,0x00,0x23,0x80,0x00,0x3C,0x00,0x00,0x30,0x00,0x00,0x20,0x00},/*"v",86*/
+{0x00,0x20,0x00,0x00,0x3C,0x00,0x00,0x3F,0xE0,0x00,0x23,0xF8,0x00,0x00,0xE0,0x00,0x27,0x00,0x00,0x3E,0x00,0x00,0x3F,0xE0,0x00,0x21,0xF8,0x00,0x01,0xE0,0x00,0x3E,0x00,0x00,0x20,0x00},/*"w",87*/
+{0x00,0x00,0x00,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x38,0x38,0x00,0x3E,0x68,0x00,0x27,0x80,0x00,0x03,0xC8,0x00,0x2C,0xF8,0x00,0x38,0x38,0x00,0x20,0x18,0x00,0x20,0x08,0x00,0x00,0x00},/*"x",88*/
+{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x30,0x03,0x00,0x3C,0x01,0x00,0x3F,0x83,0x00,0x23,0xEC,0x00,0x00,0x70,0x00,0x23,0x80,0x00,0x3C,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"y",89*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x08,0x00,0x20,0x38,0x00,0x20,0xF8,0x00,0x23,0xE8,0x00,0x2F,0x88,0x00,0x3E,0x08,0x00,0x38,0x08,0x00,0x20,0x18,0x00,0x00,0x70,0x00,0x00,0x00},/*"z",90*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x14,0x00,0x1F,0xF7,0xFC,0x30,0x00,0x06,0x20,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00},/*"{",91*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"|",92*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x02,0x30,0x00,0x06,0x1F,0xF7,0xFC,0x00,0x14,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"}",93*/
+{0x00,0x00,0x00,0x18,0x00,0x00,0x60,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0x00,0x10,0x00,0x00,0x08,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x0C,0x00,0x00,0x10,0x00,0x00},/*"~",94*/
+};     
+
+//32*32 ASCII code
+const unsigned char asc2_3216[95][128]={
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xF0,0x00,0xC0,0x07,0xFF,0xE1,0xE0,0x07,0xF0,0x01,0xE0,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x01,0xC0,0x00,0x00,0x07,0x80,0x00,0x00,0x1F,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x1C,0x20,0x00,0x00,0x01,0xC0,0x00,0x00,0x07,0x80,0x00,0x00,0x1F,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*""",2*/
+{0x00,0x00,0x00,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0F,0xE0,0x00,0x1F,0xFC,0x00,0x03,0xF8,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0F,0xE0,0x00,0x1F,0xFC,0x00,0x03,0xF8,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x00,0x00,0x00},/*"#",3*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x80,0x00,0x78,0x07,0xC0,0x00,0xFC,0x06,0x40,0x01,0x0E,0x00,0x20,0x03,0x07,0x00,0x20,0x02,0x03,0x80,0x20,0x0F,0xFF,0xFF,0xFC,0x02,0x01,0xC0,0x20,0x02,0x00,0xE0,0x60,0x01,0x30,0x70,0x40,0x01,0xF0,0x3F,0x80,0x00,0xF0,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"$",4*/
+{0x00,0xFE,0x00,0x00,0x01,0xFF,0x00,0x00,0x03,0x01,0x80,0x00,0x02,0x00,0x80,0x60,0x03,0x01,0x81,0xC0,0x01,0xFF,0x07,0x00,0x00,0xFE,0x18,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0xBF,0x00,0x00,0x0C,0xFF,0xC0,0x00,0x71,0x80,0x60,0x01,0xC1,0x00,0x20,0x03,0x01,0x80,0x60,0x00,0x00,0xFF,0xC0,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00},/*"%",5*/
+{0x00,0x00,0x1F,0x00,0x00,0x00,0x7F,0xC0,0x00,0xFC,0xC0,0xC0,0x01,0xFF,0x80,0x60,0x03,0x03,0xE0,0x20,0x02,0x02,0x78,0x20,0x02,0x06,0x1E,0x20,0x03,0xFC,0x07,0x40,0x01,0xF0,0x03,0x80,0x00,0x01,0x03,0xC0,0x00,0x01,0x1C,0x60,0x00,0x01,0xE0,0x20,0x00,0x01,0x00,0x20,0x00,0x01,0x00,0x40,0x00,0x00,0x01,0x80,0x00,0x00,0x00,0x00},/*"&",6*/
+{0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x1C,0x60,0x00,0x00,0x1C,0x40,0x00,0x00,0x1F,0x80,0x00,0x00,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xF8,0x00,0x00,0x3F,0xFF,0x00,0x00,0x78,0x07,0xC0,0x01,0xC0,0x00,0xE0,0x03,0x00,0x00,0x30,0x04,0x00,0x00,0x08,0x08,0x00,0x00,0x04,0x10,0x00,0x00,0x02,0x00,0x00,0x00,0x00},/*"(",8*/
+{0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x02,0x08,0x00,0x00,0x04,0x04,0x00,0x00,0x08,0x03,0x00,0x00,0x30,0x01,0xC0,0x00,0xE0,0x00,0x78,0x07,0xC0,0x00,0x3F,0xFF,0x00,0x00,0x07,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*")",9*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x18,0x00,0x00,0x0E,0x38,0x00,0x00,0x0E,0x38,0x00,0x00,0x06,0x30,0x00,0x00,0x03,0x60,0x00,0x00,0x61,0x43,0x80,0x00,0xFF,0xFF,0x80,0x00,0x61,0x43,0x00,0x00,0x03,0x60,0x00,0x00,0x06,0x30,0x00,0x00,0x0E,0x38,0x00,0x00,0x0E,0x38,0x00,0x00,0x0C,0x18,0x00,0x00,0x00,0x00,0x00},/*"*",10*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x7F,0xFF,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00},/*"+",11*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0xE3,0x00,0x00,0x00,0xE2,0x00,0x00,0x00,0xFC,0x00,0x00,0x00,0x78,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00},/*"-",13*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x00,0x00,0x01,0xE0,0x00,0x00,0x01,0xE0,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x0E,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x0E,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x0E,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"/",15*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x7F,0xFF,0x00,0x00,0xF0,0x07,0x80,0x01,0x80,0x00,0xC0,0x03,0x00,0x00,0x60,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0x00,0x00,0x60,0x01,0x80,0x00,0xC0,0x00,0xE0,0x03,0x80,0x00,0x7F,0xFF,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x00,0x00},/*"0",16*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x20,0x00,0x80,0x00,0x20,0x00,0x80,0x00,0x20,0x00,0x80,0x00,0x60,0x01,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"1",17*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x00,0xE0,0x00,0x98,0x01,0x60,0x01,0x00,0x02,0x60,0x02,0x00,0x04,0x60,0x02,0x00,0x08,0x60,0x02,0x00,0x10,0x60,0x02,0x00,0x20,0x60,0x02,0x00,0x40,0x60,0x03,0x00,0x80,0x60,0x01,0x83,0x00,0x60,0x01,0xFE,0x00,0xE0,0x00,0x7C,0x07,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"2",18*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x80,0x01,0xF0,0x07,0xC0,0x01,0x00,0x00,0x40,0x02,0x00,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x03,0x03,0x80,0x20,0x01,0x86,0x80,0x40,0x01,0xFC,0xC0,0xC0,0x00,0x78,0x7F,0x80,0x00,0x00,0x1E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"3",19*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x48,0x00,0x00,0x01,0x88,0x00,0x00,0x06,0x08,0x00,0x00,0x0C,0x08,0x10,0x00,0x30,0x08,0x10,0x00,0x40,0x08,0x10,0x01,0xFF,0xFF,0xF0,0x03,0xFF,0xFF,0xF0,0x03,0xFF,0xFF,0xF0,0x00,0x00,0x08,0x10,0x00,0x00,0x08,0x10,0x00,0x00,0x08,0x10,0x00,0x00,0x00,0x00},/*"4",20*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x80,0x00,0x1F,0x86,0x40,0x03,0xE1,0x00,0x20,0x03,0x02,0x00,0x20,0x03,0x04,0x00,0x20,0x03,0x04,0x00,0x20,0x03,0x04,0x00,0x20,0x03,0x04,0x00,0x20,0x03,0x06,0x00,0x40,0x03,0x03,0x01,0xC0,0x03,0x01,0xFF,0x80,0x03,0x00,0x7E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"5",21*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xFC,0x00,0x00,0x3F,0xFF,0x00,0x00,0x70,0xC3,0x80,0x00,0x81,0x80,0xC0,0x01,0x01,0x00,0x60,0x03,0x02,0x00,0x20,0x02,0x02,0x00,0x20,0x02,0x02,0x00,0x20,0x02,0x02,0x00,0x20,0x02,0x03,0x00,0x40,0x01,0xC1,0x80,0xC0,0x00,0xC0,0xFF,0x80,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00},/*"6",22*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x00,0x03,0xC0,0x00,0x00,0x03,0x80,0x00,0x00,0x03,0x00,0x00,0x00,0x03,0x00,0x07,0xE0,0x03,0x00,0x3F,0xE0,0x03,0x01,0xC0,0x00,0x03,0x06,0x00,0x00,0x03,0x18,0x00,0x00,0x03,0x60,0x00,0x00,0x03,0x80,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"7",23*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x00,0x00,0x78,0x3F,0x80,0x00,0xFC,0x60,0xC0,0x01,0x8E,0xC0,0x40,0x03,0x07,0x80,0x20,0x02,0x03,0x00,0x20,0x02,0x01,0x80,0x20,0x02,0x01,0x80,0x20,0x02,0x01,0xC0,0x20,0x03,0x01,0xE0,0x40,0x01,0x86,0x70,0xC0,0x00,0xFC,0x3F,0x80,0x00,0x78,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"8",24*/
+{0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0xFF,0x81,0xC0,0x01,0xC0,0xC1,0xC0,0x01,0x00,0x60,0x20,0x02,0x00,0x20,0x20,0x02,0x00,0x20,0x20,0x02,0x00,0x20,0x20,0x02,0x00,0x20,0x60,0x02,0x00,0x40,0xC0,0x01,0x00,0xC1,0x80,0x00,0xC1,0x8F,0x00,0x00,0x7F,0xFE,0x00,0x00,0x1F,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"9",25*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0xC0,0x00,0x07,0x81,0xE0,0x00,0x07,0x81,0xE0,0x00,0x03,0x00,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x66,0x00,0x06,0x00,0x78,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x01,0xC0,0x00,0x00,0x03,0x60,0x00,0x00,0x06,0x30,0x00,0x00,0x0C,0x18,0x00,0x00,0x18,0x0C,0x00,0x00,0x30,0x06,0x00,0x00,0x60,0x03,0x00,0x00,0xC0,0x01,0x80,0x01,0x00,0x00,0x40,0x02,0x00,0x00,0x20,0x04,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"<",28*/
+{0x00,0x00,0x00,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x00,0x00,0x00},/*"=",29*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x10,0x02,0x00,0x00,0x20,0x01,0x00,0x00,0x40,0x00,0xC0,0x01,0x80,0x00,0x60,0x03,0x00,0x00,0x30,0x06,0x00,0x00,0x18,0x0C,0x00,0x00,0x0C,0x18,0x00,0x00,0x06,0x30,0x00,0x00,0x03,0x60,0x00,0x00,0x01,0xC0,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*">",30*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x00,0x00,0x01,0xF8,0x00,0x00,0x02,0x38,0x00,0x00,0x02,0x00,0x00,0x00,0x04,0x00,0x00,0xC0,0x04,0x00,0x79,0xE0,0x04,0x00,0x81,0xE0,0x04,0x01,0x00,0xC0,0x04,0x03,0x00,0x00,0x02,0x02,0x00,0x00,0x03,0x06,0x00,0x00,0x01,0xFC,0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00,0x00,0x00},/*"?",31*/
+{0x00,0x00,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x3F,0xFE,0x00,0x00,0x70,0x07,0x80,0x00,0xC0,0x00,0xC0,0x01,0x01,0xF8,0x40,0x03,0x07,0xFC,0x20,0x02,0x1E,0x04,0x20,0x02,0x30,0x08,0x20,0x02,0x20,0x30,0x20,0x02,0x3F,0xFC,0x20,0x01,0x3F,0x04,0x40,0x01,0x80,0x0C,0xC0,0x00,0xE0,0x31,0x80,0x00,0x1F,0xC2,0x00,0x00,0x00,0x00,0x00},/*"@",32*/
+{0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x60,0x00,0x00,0x03,0xE0,0x00,0x00,0x3E,0x20,0x00,0x03,0xE0,0x20,0x00,0x3E,0x20,0x00,0x03,0xE0,0x20,0x00,0x03,0x80,0x20,0x00,0x07,0xFC,0x20,0x00,0x00,0x3F,0xE0,0x00,0x00,0x03,0xFE,0x20,0x00,0x00,0x3F,0xE0,0x00,0x00,0x01,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"A",33*/
+{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x03,0x03,0x00,0x20,0x01,0x86,0x80,0x60,0x01,0xFC,0xC0,0xC0,0x00,0xF8,0x7F,0x80,0x00,0x00,0x1F,0x00,0x00,0x00,0x00,0x00},/*"B",34*/
+{0x00,0x00,0x00,0x00,0x00,0x07,0xF8,0x00,0x00,0x3F,0xFF,0x00,0x00,0x70,0x07,0x80,0x00,0xC0,0x00,0xC0,0x01,0x00,0x00,0x40,0x03,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x01,0x00,0x00,0x40,0x01,0x80,0x00,0xC0,0x03,0xC0,0x01,0x80,0x00,0x30,0x06,0x00,0x00,0x00,0x00,0x00},/*"C",35*/
+{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0x00,0x00,0x60,0x01,0x00,0x00,0x40,0x01,0x80,0x00,0xC0,0x00,0xF0,0x07,0x80,0x00,0x7F,0xFE,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x00,0x00},/*"D",36*/
+{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x03,0x80,0x20,0x02,0x0F,0xE0,0x20,0x03,0x00,0x00,0x60,0x03,0xC0,0x00,0xE0,0x00,0x60,0x03,0x00,0x00,0x00,0x00,0x00},/*"E",37*/
+{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x00,0x02,0x01,0x00,0x00,0x02,0x01,0x00,0x00,0x02,0x01,0x00,0x00,0x02,0x03,0x80,0x00,0x03,0x0F,0xE0,0x00,0x03,0x00,0x00,0x00,0x03,0xC0,0x00,0x00,0x00,0x60,0x00,0x00},/*"F",38*/
+{0x00,0x00,0x00,0x00,0x00,0x07,0xF8,0x00,0x00,0x3F,0xFE,0x00,0x00,0x70,0x07,0x80,0x01,0xC0,0x01,0xC0,0x01,0x00,0x00,0x40,0x03,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x01,0x00,0x20,0x20,0x01,0x00,0x20,0x40,0x03,0xC0,0x3F,0x80,0x00,0x30,0x3F,0x80,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00},/*"G",39*/
+{0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x80,0x20,0x02,0x00,0x80,0x20,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x02,0x00,0x80,0x20,0x02,0x00,0x80,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"H",40*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"I",41*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x0F,0x00,0x00,0x00,0x0F,0x00,0x00,0x00,0x01,0x02,0x00,0x00,0x01,0x02,0x00,0x00,0x01,0x02,0x00,0x00,0x03,0x02,0x00,0x00,0x06,0x03,0xFF,0xFF,0xFC,0x03,0xFF,0xFF,0xF8,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"J",42*/
+{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0xC0,0x20,0x02,0x01,0x00,0x20,0x00,0x07,0x80,0x00,0x00,0x0F,0xE0,0x00,0x00,0x30,0xF8,0x00,0x02,0x60,0x3E,0x20,0x03,0x80,0x0F,0x20,0x03,0x00,0x03,0xE0,0x02,0x00,0x00,0xE0,0x02,0x00,0x00,0x20,0x00,0x00,0x00,0x20},/*"K",43*/
+{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00},/*"L",44*/
+{0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xE0,0x00,0x20,0x03,0xFF,0x00,0x20,0x00,0x1F,0xF0,0x00,0x00,0x01,0xFF,0x80,0x00,0x00,0x0F,0xE0,0x00,0x00,0x1E,0x00,0x00,0x03,0xE0,0x00,0x00,0x3E,0x00,0x20,0x03,0xE0,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20},/*"M",45*/
+{0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0x80,0x00,0x20,0x03,0xF0,0x00,0x20,0x00,0xFC,0x00,0x00,0x00,0x1F,0x00,0x00,0x00,0x07,0xC0,0x00,0x00,0x01,0xF0,0x00,0x00,0x00,0x7C,0x00,0x02,0x00,0x1F,0x80,0x02,0x00,0x07,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"N",46*/
+{0x00,0x00,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x3F,0xFE,0x00,0x00,0xF0,0x07,0x80,0x01,0x80,0x00,0xC0,0x01,0x00,0x00,0x40,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x01,0x00,0x00,0x40,0x01,0x80,0x00,0xC0,0x00,0xF0,0x03,0x80,0x00,0x3F,0xFE,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x00,0x00},/*"O",47*/
+{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x80,0x20,0x02,0x00,0x80,0x20,0x02,0x00,0x80,0x00,0x02,0x00,0x80,0x00,0x02,0x00,0x80,0x00,0x02,0x00,0x80,0x00,0x03,0x01,0x80,0x00,0x01,0x83,0x00,0x00,0x00,0xFE,0x00,0x00,0x00,0x7C,0x00,0x00,0x00,0x00,0x00,0x00},/*"P",48*/
+{0x00,0x00,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x7F,0xFF,0x00,0x00,0xF0,0x03,0x80,0x01,0x80,0x01,0xC0,0x01,0x00,0x06,0x40,0x02,0x00,0x04,0x20,0x02,0x00,0x04,0x20,0x02,0x00,0x06,0x20,0x02,0x00,0x03,0xE0,0x01,0x00,0x00,0xF8,0x01,0x80,0x00,0x5C,0x00,0xE0,0x03,0x8C,0x00,0x3F,0xFF,0x0C,0x00,0x0F,0xFC,0x18,0x00,0x00,0x00,0x00},/*"Q",49*/
+{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x80,0x00,0x02,0x01,0xE0,0x00,0x02,0x01,0xFC,0x00,0x03,0x03,0x3F,0x80,0x01,0x86,0x07,0xE0,0x01,0xFC,0x00,0xE0,0x00,0xF8,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"R",50*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x06,0x00,0x00,0xFE,0x01,0xE0,0x01,0x86,0x00,0xC0,0x03,0x03,0x00,0x40,0x02,0x03,0x00,0x20,0x02,0x01,0x80,0x20,0x02,0x01,0x80,0x20,0x02,0x01,0xC0,0x20,0x02,0x00,0xC0,0x20,0x01,0x00,0xE0,0x60,0x01,0x80,0x70,0xC0,0x03,0xE0,0x3F,0x80,0x00,0x00,0x1F,0x00,0x00,0x00,0x00,0x00},/*"S",51*/
+{0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x03,0x80,0x00,0x00,0x03,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0x80,0x00,0x00,0x00,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*"T",52*/
+{0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0xFF,0xFF,0x00,0x03,0xFF,0xFF,0xC0,0x02,0x00,0x00,0x40,0x02,0x00,0x00,0x60,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x02,0x00,0x00,0x40,0x02,0x00,0x00,0x80,0x03,0xFF,0xFF,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"U",53*/
+{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0xC0,0x00,0x00,0x03,0xFC,0x00,0x00,0x02,0x3F,0xC0,0x00,0x00,0x03,0xF8,0x00,0x00,0x00,0x7F,0x80,0x00,0x00,0x07,0xE0,0x00,0x00,0x07,0x80,0x00,0x00,0x78,0x00,0x02,0x03,0xC0,0x00,0x02,0x3C,0x00,0x00,0x03,0xC0,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00},/*"V",54*/
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+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFF,0xFF,0xFC,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"[",59*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x03,0xC0,0x00,0x00,0x00,0x78,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x03,0xC0,0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x07,0x80,0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0x3C,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"\",60*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x1F,0xFF,0xFF,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"]",61*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x10,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"^",62*/
+{0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01},/*"_",63*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x00,0x10,0x00,0x00,0x00,0x10,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x00,0x01,0x8F,0xC0,0x00,0x03,0x8C,0x60,0x00,0x06,0x18,0x20,0x00,0x04,0x10,0x20,0x00,0x04,0x10,0x20,0x00,0x04,0x20,0x20,0x00,0x04,0x20,0x40,0x00,0x06,0x20,0x40,0x00,0x03,0xFF,0xC0,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x00},/*"a",65*/
+{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xC0,0x00,0x01,0x80,0xC0,0x00,0x02,0x00,0x60,0x00,0x02,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x40,0x00,0x03,0x00,0xC0,0x00,0x01,0xFF,0x80,0x00,0x00,0xFE,0x00,0x00,0x00,0x00,0x00},/*"b",66*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x01,0xFF,0x80,0x00,0x03,0x81,0xC0,0x00,0x02,0x00,0x40,0x00,0x06,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x03,0xC0,0x40,0x00,0x01,0xC0,0x80,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"c",67*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x01,0xFF,0x80,0x00,0x03,0x80,0xC0,0x00,0x06,0x00,0x60,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x02,0x04,0x00,0x40,0x02,0x02,0x00,0x80,0x03,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xC0,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00},/*"d",68*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x01,0xFF,0x80,0x00,0x03,0x11,0xC0,0x00,0x02,0x10,0x40,0x00,0x04,0x10,0x60,0x00,0x04,0x10,0x20,0x00,0x04,0x10,0x20,0x00,0x04,0x10,0x20,0x00,0x06,0x10,0x20,0x00,0x03,0x10,0x40,0x00,0x01,0xF0,0xC0,0x00,0x00,0x71,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"e",69*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x7F,0xFF,0xE0,0x01,0xFF,0xFF,0xE0,0x01,0x04,0x00,0x20,0x03,0x04,0x00,0x20,0x02,0x04,0x00,0x20,0x02,0x04,0x00,0x20,0x02,0x04,0x00,0x00,0x02,0x00,0x00,0x00,0x01,0xC0,0x00,0x00,0x01,0xC0,0x00,0x00},/*"f",70*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x00,0x00,0xE3,0x3E,0x00,0x03,0xFF,0xC2,0x00,0x02,0x0C,0xC3,0x00,0x04,0x04,0xC1,0x00,0x04,0x04,0xC1,0x00,0x04,0x04,0xC1,0x00,0x04,0x04,0xC1,0x00,0x06,0x0C,0xC1,0x00,0x03,0xF8,0xC3,0x00,0x05,0xF0,0x62,0x00,0x06,0x00,0x7E,0x00,0x06,0x00,0x3C,0x00,0x00,0x00,0x00},/*"g",71*/
+{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xE0,0x00,0x01,0x00,0x20,0x00,0x02,0x00,0x20,0x00,0x06,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x03,0xFF,0xE0,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20},/*"h",72*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x03,0x87,0xFF,0xE0,0x03,0x8F,0xFF,0xE0,0x03,0x80,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"i",73*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,0x04,0x00,0x03,0x00,0x04,0x00,0x06,0x03,0x87,0xFF,0xFC,0x03,0x8F,0xFF,0xF8,0x03,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"j",74*/
+{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xE0,0x00,0x00,0x08,0x20,0x00,0x00,0x10,0x20,0x00,0x00,0x30,0x00,0x00,0x00,0xFC,0x00,0x00,0x05,0x8E,0x00,0x00,0x07,0x07,0xA0,0x00,0x06,0x01,0xE0,0x00,0x04,0x00,0xE0,0x00,0x04,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"k",75*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"l",76*/
+{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x07,0xFF,0xE0,0x00,0x0F,0xFF,0xE0,0x00,0x02,0x00,0x20,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x07,0xFF,0xE0,0x00,0x03,0xFF,0xE0,0x00,0x02,0x00,0x20,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x07,0xFF,0xE0,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"m",77*/
+{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x07,0xFF,0xE0,0x00,0x0F,0xFF,0xE0,0x00,0x01,0x00,0x20,0x00,0x02,0x00,0x20,0x00,0x02,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x03,0xFF,0xE0,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20},/*"n",78*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0xFF,0x80,0x00,0x03,0x81,0xC0,0x00,0x02,0x00,0x40,0x00,0x06,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x02,0x00,0x40,0x00,0x03,0x81,0xC0,0x00,0x01,0xFF,0x80,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00},/*"o",79*/
+{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,0x07,0xFF,0xFF,0x00,0x0F,0xFF,0xFF,0x00,0x01,0x00,0xC1,0x00,0x02,0x00,0x41,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x40,0x00,0x03,0x01,0xC0,0x00,0x01,0xFF,0x80,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00},/*"p",80*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x01,0xFF,0x80,0x00,0x03,0x80,0xC0,0x00,0x02,0x00,0x60,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x02,0x00,0x41,0x00,0x03,0x00,0xC1,0x00,0x03,0xFF,0xFF,0x00,0x07,0xFF,0xFF,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01},/*"q",81*/
+{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x0F,0xFF,0xE0,0x00,0x0F,0xFF,0xE0,0x00,0x00,0xC0,0x20,0x00,0x01,0x00,0x20,0x00,0x02,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00},/*"r",82*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x00,0x01,0xC0,0xE0,0x00,0x03,0xE0,0x40,0x00,0x06,0x30,0x20,0x00,0x04,0x30,0x20,0x00,0x04,0x18,0x20,0x00,0x04,0x18,0x20,0x00,0x04,0x18,0x20,0x00,0x04,0x0C,0x20,0x00,0x02,0x0C,0x60,0x00,0x03,0x07,0xC0,0x00,0x07,0x83,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"s",83*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x1F,0xFF,0x80,0x00,0xFF,0xFF,0xC0,0x00,0x04,0x00,0x60,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x40,0x00,0x00,0x01,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"t",84*/
+{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x07,0xFF,0x80,0x00,0x0F,0xFF,0xC0,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x04,0x00,0x40,0x00,0x04,0x00,0x80,0x00,0x07,0xFF,0xE0,0x00,0x0F,0xFF,0xC0,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40},/*"u",85*/
+{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x07,0x80,0x00,0x00,0x07,0xF0,0x00,0x00,0x04,0xFE,0x00,0x00,0x04,0x1F,0xC0,0x00,0x00,0x03,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x1C,0x00,0x00,0x04,0x60,0x00,0x00,0x07,0x80,0x00,0x00,0x06,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"v",86*/
+{0x00,0x04,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x07,0xC0,0x00,0x00,0x07,0xFC,0x00,0x00,0x04,0x3F,0x80,0x00,0x00,0x03,0xE0,0x00,0x04,0x0F,0x80,0x00,0x06,0xF0,0x00,0x00,0x07,0xF0,0x00,0x00,0x07,0xFF,0x80,0x00,0x04,0x0F,0xE0,0x00,0x00,0x03,0x80,0x00,0x04,0x3C,0x00,0x00,0x07,0xC0,0x00,0x00,0x06,0x00,0x00,0x00,0x04,0x00,0x00},/*"w",87*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x60,0x00,0x07,0x00,0xE0,0x00,0x07,0x83,0x20,0x00,0x07,0xE6,0x00,0x00,0x04,0xF8,0x00,0x00,0x00,0x3C,0x00,0x00,0x04,0x5E,0x20,0x00,0x05,0x87,0xA0,0x00,0x06,0x01,0xE0,0x00,0x04,0x00,0x60,0x00,0x04,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"x",88*/
+{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x03,0x00,0x07,0x00,0x03,0x00,0x07,0xE0,0x01,0x00,0x04,0xF8,0x01,0x00,0x04,0x1F,0x02,0x00,0x00,0x07,0xFC,0x00,0x00,0x00,0xE0,0x00,0x00,0x07,0x00,0x00,0x04,0x38,0x00,0x00,0x07,0xC0,0x00,0x00,0x06,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00},/*"y",89*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x80,0x60,0x00,0x06,0x00,0xE0,0x00,0x04,0x03,0xE0,0x00,0x04,0x07,0xA0,0x00,0x04,0x0E,0x20,0x00,0x04,0x3C,0x20,0x00,0x04,0x70,0x20,0x00,0x05,0xE0,0x20,0x00,0x07,0x80,0x20,0x00,0x07,0x00,0x60,0x00,0x04,0x00,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"z",90*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x01,0x40,0x00,0x07,0xFE,0x3F,0xF8,0x08,0x00,0x00,0x04,0x10,0x00,0x00,0x02,0x10,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"{",91*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"|",92*/
+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x02,0x10,0x00,0x00,0x02,0x08,0x00,0x00,0x04,0x07,0xFE,0x3F,0xF8,0x00,0x01,0x40,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"}",93*/
+{0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"~",94*/
+};
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/gpio.h

@@ -0,0 +1,178 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file gpio.h
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+#include "gpio_common.h"
+#include <inttypes.h>
+#include <platform.h>
+#include <stddef.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief       Structure for accessing GPIO registers by individual bit
+ */
+typedef struct _gpio_bits
+{
+    uint32_t b0 : 1;
+    uint32_t b1 : 1;
+    uint32_t b2 : 1;
+    uint32_t b3 : 1;
+    uint32_t b4 : 1;
+    uint32_t b5 : 1;
+    uint32_t b6 : 1;
+    uint32_t b7 : 1;
+    uint32_t b8 : 1;
+    uint32_t b9 : 1;
+    uint32_t b10 : 1;
+    uint32_t b11 : 1;
+    uint32_t b12 : 1;
+    uint32_t b13 : 1;
+    uint32_t b14 : 1;
+    uint32_t b15 : 1;
+    uint32_t b16 : 1;
+    uint32_t b17 : 1;
+    uint32_t b18 : 1;
+    uint32_t b19 : 1;
+    uint32_t b20 : 1;
+    uint32_t b21 : 1;
+    uint32_t b22 : 1;
+    uint32_t b23 : 1;
+    uint32_t b24 : 1;
+    uint32_t b25 : 1;
+    uint32_t b26 : 1;
+    uint32_t b27 : 1;
+    uint32_t b28 : 1;
+    uint32_t b29 : 1;
+    uint32_t b30 : 1;
+    uint32_t b31 : 1;
+} __attribute__((packed, aligned(4))) gpio_bits_t;
+
+/**
+ * @brief       Structure of templates for accessing GPIO registers
+ */
+typedef union _gpio_access_tp
+{
+    /* 32x1 bit mode */
+    uint32_t u32[1];
+    /* 16x2 bit mode */
+    uint16_t u16[2];
+    /* 8x4 bit mode */
+    uint8_t u8[4];
+    /* 1 bit mode */
+    gpio_bits_t bits;
+} __attribute__((packed, aligned(4))) gpio_access_tp_t;
+
+/**
+ * @brief       The GPIO address map
+ */
+typedef struct _gpio
+{
+    /* Offset 0x00: Data (output) registers */
+    gpio_access_tp_t data_output;
+    /* Offset 0x04: Data direction registers */
+    gpio_access_tp_t direction;
+    /* Offset 0x08: Data source registers */
+    gpio_access_tp_t source;
+    /* Offset 0x10 - 0x2f: Unused registers, 9x4 bytes */
+    uint32_t unused_0[9];
+    /* Offset 0x30: Interrupt enable/disable registers */
+    gpio_access_tp_t interrupt_enable;
+    /* Offset 0x34: Interrupt mask registers */
+    gpio_access_tp_t interrupt_mask;
+    /* Offset 0x38: Interrupt level registers */
+    gpio_access_tp_t interrupt_level;
+    /* Offset 0x3c: Interrupt polarity registers */
+    gpio_access_tp_t interrupt_polarity;
+    /* Offset 0x40: Interrupt status registers */
+    gpio_access_tp_t interrupt_status;
+    /* Offset 0x44: Raw interrupt status registers */
+    gpio_access_tp_t interrupt_status_raw;
+    /* Offset 0x48: Interrupt debounce registers */
+    gpio_access_tp_t interrupt_debounce;
+    /* Offset 0x4c: Registers for clearing interrupts */
+    gpio_access_tp_t interrupt_clear;
+    /* Offset 0x50: External port (data input) registers */
+    gpio_access_tp_t data_input;
+    /* Offset 0x54 - 0x5f: Unused registers, 3x4 bytes */
+    uint32_t unused_1[3];
+    /* Offset 0x60: Sync level registers */
+    gpio_access_tp_t sync_level;
+    /* Offset 0x64: ID code */
+    gpio_access_tp_t id_code;
+    /* Offset 0x68: Interrupt both edge type */
+    gpio_access_tp_t interrupt_bothedge;
+
+} __attribute__((packed, aligned(4))) gpio_t;
+
+/**
+ * @brief       Bus GPIO object instance
+ */
+extern volatile gpio_t *const gpio;
+
+/**
+ * @brief       Gpio initialize
+ *
+ * @return      Result
+ *     - 0      Success
+ *     - Other Fail
+ */
+int gpio_init(void);
+
+/**
+ * @brief       Set Gpio drive mode
+ *
+ * @param[in]   pin         Gpio pin
+ * @param[in]   mode        Gpio pin drive mode
+ */
+void gpio_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode);
+
+/**
+ * @brief       Get Gpio pin value
+ *
+ * @param[in]   pin      Gpio pin
+ * @return      Pin value
+ *
+ *     - GPIO_PV_Low     Gpio pin low
+ *     - GPIO_PV_High    Gpio pin high
+ */
+gpio_pin_value_t gpio_get_pin(uint8_t pin);
+
+/**
+ * @brief       Set Gpio pin value
+ *
+ * @param[in]   pin         Gpio pin
+ * @param[in]   value       Gpio pin value
+ */
+void gpio_set_pin(uint8_t pin, gpio_pin_value_t value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIO_H__ */
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/gpio_common.h

@@ -0,0 +1,61 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file gpio_common.h
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef __GPIO_COMMON_H__
+#define __GPIO_COMMON_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum _gpio_drive_mode
+{
+    GPIO_DM_INPUT,
+    GPIO_DM_INPUT_PULL_DOWN,
+    GPIO_DM_INPUT_PULL_UP,
+    GPIO_DM_OUTPUT,
+} gpio_drive_mode_t;
+
+typedef enum _gpio_pin_edge
+{
+    GPIO_PE_NONE,
+    GPIO_PE_FALLING,
+    GPIO_PE_RISING,
+    GPIO_PE_BOTH,
+    GPIO_PE_LOW,
+    GPIO_PE_HIGH = 8,
+} GpioPinEdgeT;
+
+typedef enum _gpio_pin_value
+{
+    GPIO_PV_LOW,
+    GPIO_PV_HIGH
+} gpio_pin_value_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIO_COMMON_H__ */
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/gpiohs.h

@@ -0,0 +1,277 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file gpiohs.h
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef __GPIOHS_H__
+#define __GPIOHS_H__
+
+#include "gpio_common.h"
+#include <platform.h>
+#include "plic.h"
+#include <stddef.h>
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* clang-format off */
+/* Register address offsets */
+#define GPIOHS_INPUT_VAL  (0x00)
+#define GPIOHS_INPUT_EN   (0x04)
+#define GPIOHS_OUTPUT_EN  (0x08)
+#define GPIOHS_OUTPUT_VAL (0x0C)
+#define GPIOHS_PULLUP_EN  (0x10)
+#define GPIOHS_DRIVE      (0x14)
+#define GPIOHS_RISE_IE    (0x18)
+#define GPIOHS_RISE_IP    (0x1C)
+#define GPIOHS_FALL_IE    (0x20)
+#define GPIOHS_FALL_IP    (0x24)
+#define GPIOHS_HIGH_IE    (0x28)
+#define GPIOHS_HIGH_IP    (0x2C)
+#define GPIOHS_LOW_IE     (0x30)
+#define GPIOHS_LOW_IP     (0x34)
+#define GPIOHS_IOF_EN     (0x38)
+#define GPIOHS_IOF_SEL    (0x3C)
+#define GPIOHS_OUTPUT_XOR (0x40)
+/* clang-format on */
+
+/**
+ * @brief      GPIO bits raw object
+ */
+typedef struct _gpiohs_raw
+{
+    /* Address offset 0x00 */
+    uint32_t input_val;
+    /* Address offset 0x04 */
+    uint32_t input_en;
+    /* Address offset 0x08 */
+    uint32_t output_en;
+    /* Address offset 0x0c */
+    uint32_t output_val;
+    /* Address offset 0x10 */
+    uint32_t pullup_en;
+    /* Address offset 0x14 */
+    uint32_t drive;
+    /* Address offset 0x18 */
+    uint32_t rise_ie;
+    /* Address offset 0x1c */
+    uint32_t rise_ip;
+    /* Address offset 0x20 */
+    uint32_t fall_ie;
+    /* Address offset 0x24 */
+    uint32_t fall_ip;
+    /* Address offset 0x28 */
+    uint32_t high_ie;
+    /* Address offset 0x2c */
+    uint32_t high_ip;
+    /* Address offset 0x30 */
+    uint32_t low_ie;
+    /* Address offset 0x34 */
+    uint32_t low_ip;
+    /* Address offset 0x38 */
+    uint32_t iof_en;
+    /* Address offset 0x3c */
+    uint32_t iof_sel;
+    /* Address offset 0x40 */
+    uint32_t output_xor;
+} __attribute__((packed, aligned(4))) gpiohs_raw_t;
+
+/**
+ * @brief       GPIO bits object
+ */
+typedef struct _gpiohs_bits
+{
+    uint32_t b0 : 1;
+    uint32_t b1 : 1;
+    uint32_t b2 : 1;
+    uint32_t b3 : 1;
+    uint32_t b4 : 1;
+    uint32_t b5 : 1;
+    uint32_t b6 : 1;
+    uint32_t b7 : 1;
+    uint32_t b8 : 1;
+    uint32_t b9 : 1;
+    uint32_t b10 : 1;
+    uint32_t b11 : 1;
+    uint32_t b12 : 1;
+    uint32_t b13 : 1;
+    uint32_t b14 : 1;
+    uint32_t b15 : 1;
+    uint32_t b16 : 1;
+    uint32_t b17 : 1;
+    uint32_t b18 : 1;
+    uint32_t b19 : 1;
+    uint32_t b20 : 1;
+    uint32_t b21 : 1;
+    uint32_t b22 : 1;
+    uint32_t b23 : 1;
+    uint32_t b24 : 1;
+    uint32_t b25 : 1;
+    uint32_t b26 : 1;
+    uint32_t b27 : 1;
+    uint32_t b28 : 1;
+    uint32_t b29 : 1;
+    uint32_t b30 : 1;
+    uint32_t b31 : 1;
+} __attribute__((packed, aligned(4))) gpiohs_bits_t;
+
+/**
+ * @brief       GPIO bits multi access union
+ */
+typedef union _gpiohs_u32
+{
+    /* 32x1 bit mode */
+    uint32_t u32[1];
+    /* 16x2 bit mode */
+    uint16_t u16[2];
+    /* 8x4 bit mode */
+    uint8_t u8[4];
+    /* 1 bit mode */
+    gpiohs_bits_t bits;
+} __attribute__((packed, aligned(4))) gpiohs_u32_t;
+
+/**
+ * @brief      GPIO object
+ *
+ *             The GPIO controller is a peripheral device mapped in the
+ *             internal memory map, discoverable in the Configuration String.
+ *             It is responsible for low-level configuration of the actual
+ *             GPIO pads on the device (direction, pull up-enable, and drive
+ *             value), as well as selecting between various sources of the
+ *             controls for these signals. The GPIO controller allows seperate
+ *             configuration of each of N GPIO bits.
+ *
+ *             Once the interrupt is pending, it will remain set until a 1 is
+ *             written to the *_ip register at that bit.
+ */
+
+typedef struct _gpiohs
+{
+    /* Address offset 0x00, Input Values */
+    gpiohs_u32_t input_val;
+    /* Address offset 0x04, Input enable */
+    gpiohs_u32_t input_en;
+    /* Address offset 0x08, Output enable */
+    gpiohs_u32_t output_en;
+    /* Address offset 0x0c, Onput Values */
+    gpiohs_u32_t output_val;
+    /* Address offset 0x10, Internal Pull-Ups enable */
+    gpiohs_u32_t pullup_en;
+    /* Address offset 0x14, Drive Strength */
+    gpiohs_u32_t drive;
+    /* Address offset 0x18, Rise interrupt enable */
+    gpiohs_u32_t rise_ie;
+    /* Address offset 0x1c, Rise interrupt pending */
+    gpiohs_u32_t rise_ip;
+    /* Address offset 0x20, Fall interrupt enable */
+    gpiohs_u32_t fall_ie;
+    /* Address offset 0x24, Fall interrupt pending */
+    gpiohs_u32_t fall_ip;
+    /* Address offset 0x28, High interrupt enable */
+    gpiohs_u32_t high_ie;
+    /* Address offset 0x2c, High interrupt pending */
+    gpiohs_u32_t high_ip;
+    /* Address offset 0x30, Low interrupt enable */
+    gpiohs_u32_t low_ie;
+    /* Address offset 0x34, Low interrupt pending */
+    gpiohs_u32_t low_ip;
+    /* Address offset 0x38, HW I/O Function enable */
+    gpiohs_u32_t iof_en;
+    /* Address offset 0x3c, HW I/O Function select */
+    gpiohs_u32_t iof_sel;
+    /* Address offset 0x40, Output XOR (invert) */
+    gpiohs_u32_t output_xor;
+} __attribute__((packed, aligned(4))) gpiohs_t;
+
+/**
+ * @brief       GPIO High-speed object instanse
+ */
+extern volatile gpiohs_t *const gpiohs;
+
+/**
+ * @brief       Set Gpiohs drive mode
+ *
+ * @param[in]   pin         Gpiohs pin
+ * @param[in]   mode        Gpiohs pin drive mode
+ */
+void gpiohs_set_drive_mode(uint8_t pin, gpio_drive_mode_t mode);
+
+/**
+ * @brief       Get Gpiohs pin value
+ *
+ * @param[in]   pin     Gpiohs pin
+ * @return      Pin     value
+ *
+ *     - GPIO_PV_Low     Gpiohs pin low
+ *     - GPIO_PV_High    Gpiohs pin high
+ */
+gpio_pin_value_t gpiohs_get_pin(uint8_t pin);
+
+/**
+ * @brief      Set Gpiohs pin value
+ *
+ * @param[in]   pin      Gpiohs pin
+ * @param[in]   value    Gpiohs pin value
+ */
+void gpiohs_set_pin(uint8_t pin, gpio_pin_value_t value);
+
+/**
+ * @brief      Set Gpiohs pin edge for interrupt
+ *
+ * @param[in]   pin         Gpiohs pin
+ * @param[in]   edge        Gpiohs pin edge type
+ */
+void gpiohs_set_pin_edge(uint8_t pin, GpioPinEdgeT edge);
+
+/**
+ * @brief      Set Gpiohs pin interrupt
+ *
+ * @param[in]   pin             Gpiohs pin
+ * @param[in]   priority        Gpiohs pin interrupt priority
+ * @param[in]   func            Gpiohs pin interrupt service routine
+ */
+void gpiohs_set_irq(uint8_t pin, uint32_t priority, void(*func)());
+
+/**
+ * @brief      Set Gpiohs pin interrupt
+ *
+ * @param[in]   pin             Gpiohs pin
+ * @param[in]   priority        Gpiohs pin interrupt priority
+ * @param[in]   callback        Gpiohs pin interrupt service routine
+ * @param[in]   ctx             Gpiohs interrupt param
+ */
+void gpiohs_irq_register(uint8_t pin, uint32_t priority, plic_irq_callback_t callback, void *ctx);
+
+/**
+ * @brief      Unregister Gpiohs pin interrupt
+ *
+ * @param[in]   pin             Gpiohs pin
+ */
+void gpiohs_irq_unregister(uint8_t pin);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIOHS_H__ */
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/graphic.h

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+/**
+* @file graphic.h
+* @brief define aiit-riscv64-board lcd operation
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: graphic.h
+Description: define aiit-riscv64-board lcd operation
+Others: take RT-Thread v4.0.2/include/rtdef.h for references
+                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: add aiit-riscv64-board lcd configure and operation function
+*************************************************/
+
+#ifndef GRAPHIC_H
+#define GRAPIHC_H
+
+#include <xizi.h>
+
+#define GRAPHIC_CTRL_RECT_UPDATE                      0
+#define GRAPHIC_CTRL_POWERON                          1
+#define GRAPHIC_CTRL_POWEROFF                         2
+#define GRAPHIC_CTRL_GET_INFO                         3
+#define GRAPHIC_CTRL_SET_MODE                         4
+#define GRAPHIC_CTRL_GET_EXT                          5
+
+enum
+{
+    PIXEL_FORMAT_MONO = 0,
+    PIXEL_FORMAT_GRAY4,
+    PIXEL_FORMAT_GRAY16,
+    PIXEL_FORMAT_RGB332,
+    PIXEL_FORMAT_RGB444,
+    PIXEL_FORMAT_RGB565 ,
+    PIXEL_FORMAT_RGB565P,
+    PIXEL_FORMAT_BGR565 = PIXEL_FORMAT_RGB565P,
+    PIXEL_FORMAT_RGB666,
+    PIXEL_FORMAT_RGB888,
+    PIXEL_FORMAT_ARGB888,
+    PIXEL_FORMAT_ABGR888,
+    PIXEL_FORMAT_ARGB565,
+    PIXEL_FORMAT_ALPHA,
+    PIXEL_FORMAT_COLOR,
+};
+
+struct DeviceLcdInfo
+{
+    uint8 pixel_format;                           
+    uint8 bits_per_pixel;                       
+    uint16 reserved;                               
+
+    uint16 width;                                 
+    uint16 height;                                
+
+    uint8 *framebuffer;                            
+};
+
+struct DeviceRectInfo
+{
+    uint16 x;                                    
+    uint16 y;                                  
+    uint16 width;                              
+    uint16 height;                             
+};
+
+struct DeviceGraphicDone
+{
+    void (*set_pixel) (const char *pixel, int x, int y);
+    void (*get_pixel) (char *pixel, int x, int y);
+
+    void (*draw_hline) (const char *pixel, int x1, int x2, int y);
+    void (*draw_vline) (const char *pixel, int x, int y1, int y2);
+
+    void (*blit_line) (const char *pixel, int x, int y, x_size_t size);
+};
+
+#define GraphixDone(device) ((struct DeviceGraphicDone *)(device->UserData))
+
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/hardware_hwtimer.h

@@ -0,0 +1,171 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file hardware_hwtimer.h
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef __HARDWARE_HWTIMER_H__
+#define __HARDWARE_HWTIMER_H__
+
+#include <stdint.h>
+#include <stddef.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* clang-format off */
+typedef struct _timer_channel
+{
+    /* TIMER_N Load Count Register              (0x00+(N-1)*0x14) */
+    volatile uint32_t load_count;
+    /* TIMER_N Current Value Register           (0x04+(N-1)*0x14) */
+    volatile uint32_t current_value;
+    /* TIMER_N Control Register                 (0x08+(N-1)*0x14) */
+    volatile uint32_t control;
+    /* TIMER_N Interrupt Clear Register         (0x0c+(N-1)*0x14) */
+    volatile uint32_t eoi;
+    /* TIMER_N Interrupt Status Register        (0x10+(N-1)*0x14) */
+    volatile uint32_t intr_stat;
+} __attribute__((packed, aligned(4))) timer_channel_t;
+
+typedef struct _kendryte_timer
+{
+    /* TIMER_N Register                         (0x00-0x4c) */
+    volatile timer_channel_t channel[4];
+    /* reserverd                                (0x50-0x9c) */
+    volatile uint32_t resv1[20];
+    /* TIMER Interrupt Status Register          (0xa0) */
+    volatile uint32_t intr_stat;
+    /* TIMER Interrupt Clear Register           (0xa4) */
+    volatile uint32_t eoi;
+    /* TIMER Raw Interrupt Status Register      (0xa8) */
+    volatile uint32_t raw_intr_stat;
+    /* TIMER Component Version Register         (0xac) */
+    volatile uint32_t comp_version;
+    /* TIMER_N Load Count2 Register             (0xb0-0xbc) */
+    volatile uint32_t load_count2[4];
+} __attribute__((packed, aligned(4))) kendryte_timer_t;
+
+typedef enum _timer_deivce_number
+{
+    TIMER_DEVICE_0,
+    TIMER_DEVICE_1,
+    TIMER_DEVICE_2,
+    TIMER_DEVICE_MAX,
+} timer_device_number_t;
+
+typedef enum _timer_channel_number
+{
+    TIMER_CHANNEL_0,
+    TIMER_CHANNEL_1,
+    TIMER_CHANNEL_2,
+    TIMER_CHANNEL_3,
+    TIMER_CHANNEL_MAX,
+} timer_channel_number_t;
+
+/* TIMER Control Register */
+#define TIMER_CR_ENABLE             0x00000001
+#define TIMER_CR_MODE_MASK          0x00000002
+#define TIMER_CR_FREE_MODE          0x00000000
+#define TIMER_CR_USER_MODE          0x00000002
+#define TIMER_CR_INTERRUPT_MASK     0x00000004
+#define TIMER_CR_PWM_ENABLE         0x00000008
+/* clang-format on */
+
+extern volatile kendryte_timer_t *const timer[3];
+
+/**
+ * @brief       Definitions for the timer callbacks
+ */
+typedef int (*timer_callback_t)(void *ctx);
+
+/**
+ * @brief       Set timer timeout
+ *
+ * @param[in]   timer           timer
+ * @param[in]   channel         channel
+ * @param[in]   nanoseconds     timeout
+ *
+ * @return      the real timeout
+ */
+size_t timer_set_interval(timer_device_number_t timer_number, timer_channel_number_t channel, size_t nanoseconds);
+
+/**
+ * @brief       Init timer
+ *
+ * @param[in]   timer       timer
+ */
+void timer_init(timer_device_number_t timer_number);
+
+/**
+ * @brief       [DEPRECATED] Set timer timeout function
+ *
+ * @param[in]   timer           timer
+ * @param[in]   channel         channel
+ * @param[in]   func            timeout function
+ * @param[in]   priority        interrupt priority
+ *
+ */
+void timer_set_irq(timer_device_number_t timer_number, timer_channel_number_t channel, void(*func)(),  uint32_t priority);
+
+/**
+ * @brief      Register timer interrupt user callback function
+ *
+ * @param[in]  device       The timer device number
+ * @param[in]  channel      The channel
+ * @param[in]  is_one_shot  Indicates if single shot
+ * @param[in]  priority     The priority
+ * @param[in]  callback     The callback function
+ * @param[in]  ctx          The context
+ *
+ * @return     result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int timer_irq_register(timer_device_number_t device, timer_channel_number_t channel, int is_single_shot, uint32_t priority, timer_callback_t callback, void *ctx);
+
+/**
+ * @brief      Deregister timer interrupt user callback function
+ *
+ * @param[in]  device   The timer device number
+ * @param[in]  channel  The channel
+ *
+ * @return     result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int timer_irq_unregister(timer_device_number_t device, timer_channel_number_t channel);
+
+/**
+ * @brief       Enable timer
+ *
+ * @param[in]   timer       timer
+ * @param[in]   channel     channel
+ * @param[in]   enable      Enable or disable
+ *
+ */
+void timer_set_enable(timer_device_number_t timer_number, timer_channel_number_t channel, uint32_t enable);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIMER_H__ */

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/hardware_i2c.h

@@ -0,0 +1,482 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file hardware_i2c.h
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef __HARDWARE_I2C_H__
+#define __HARDWARE_I2C_H__
+
+#include "dmac.h"
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define I2C_MAX_NUM 3
+
+/* clang-format off */
+typedef struct _i2c
+{
+    /* I2C Control Register                                 (0x00) */
+    volatile uint32_t con;
+    /* I2C Target Address Register                          (0x04) */
+    volatile uint32_t tar;
+    /* I2C Slave Address Register                           (0x08) */
+    volatile uint32_t sar;
+    /* reserved                                             (0x0c) */
+    volatile uint32_t resv1;
+    /* I2C Data Buffer and Command Register                 (0x10) */
+    volatile uint32_t data_cmd;
+    /* I2C Standard Speed Clock SCL High Count Register     (0x14) */
+    volatile uint32_t ss_scl_hcnt;
+    /* I2C Standard Speed Clock SCL Low Count Register      (0x18) */
+    volatile uint32_t ss_scl_lcnt;
+    /* reserverd                                            (0x1c-0x28) */
+    volatile uint32_t resv2[4];
+    /* I2C Interrupt Status Register                        (0x2c) */
+    volatile uint32_t intr_stat;
+    /* I2C Interrupt Mask Register                          (0x30) */
+    volatile uint32_t intr_mask;
+    /* I2C Raw Interrupt Status Register                    (0x34) */
+    volatile uint32_t raw_intr_stat;
+    /* I2C Receive FIFO Threshold Register                  (0x38) */
+    volatile uint32_t rx_tl;
+    /* I2C Transmit FIFO Threshold Register                 (0x3c) */
+    volatile uint32_t tx_tl;
+    /* I2C Clear Combined and Individual Interrupt Register (0x40) */
+    volatile uint32_t clr_intr;
+    /* I2C Clear RX_UNDER Interrupt Register                (0x44) */
+    volatile uint32_t clr_rx_under;
+    /* I2C Clear RX_OVER Interrupt Register                 (0x48) */
+    volatile uint32_t clr_rx_over;
+    /* I2C Clear TX_OVER Interrupt Register                 (0x4c) */
+    volatile uint32_t clr_tx_over;
+    /* I2C Clear RD_REQ Interrupt Register                  (0x50) */
+    volatile uint32_t clr_rd_req;
+    /* I2C Clear TX_ABRT Interrupt Register                 (0x54) */
+    volatile uint32_t clr_tx_abrt;
+    /* I2C Clear RX_DONE Interrupt Register                 (0x58) */
+    volatile uint32_t clr_rx_done;
+    /* I2C Clear ACTIVITY Interrupt Register                (0x5c) */
+    volatile uint32_t clr_activity;
+    /* I2C Clear STOP_DET Interrupt Register                (0x60) */
+    volatile uint32_t clr_stop_det;
+    /* I2C Clear START_DET Interrupt Register               (0x64) */
+    volatile uint32_t clr_start_det;
+    /* I2C Clear GEN_CALL Interrupt Register                (0x68) */
+    volatile uint32_t clr_gen_call;
+    /* I2C Enable Register                                  (0x6c) */
+    volatile uint32_t enable;
+    /* I2C Status Register                                  (0x70) */
+    volatile uint32_t status;
+    /* I2C Transmit FIFO Level Register                     (0x74) */
+    volatile uint32_t txflr;
+    /* I2C Receive FIFO Level Register                      (0x78) */
+    volatile uint32_t rxflr;
+    /* I2C SDA Hold Time Length Register                    (0x7c) */
+    volatile uint32_t sda_hold;
+    /* I2C Transmit Abort Source Register                   (0x80) */
+    volatile uint32_t tx_abrt_source;
+    /* reserved                                             (0x84) */
+    volatile uint32_t resv3;
+    /* I2C DMA Control Register                             (0x88) */
+    volatile uint32_t dma_cr;
+    /* I2C DMA Transmit Data Level Register                 (0x8c) */
+    volatile uint32_t dma_tdlr;
+    /* I2C DMA Receive Data Level Register                  (0x90) */
+    volatile uint32_t dma_rdlr;
+    /* I2C SDA Setup Register                               (0x94) */
+    volatile uint32_t sda_setup;
+    /* I2C ACK General Call Register                        (0x98) */
+    volatile uint32_t general_call;
+    /* I2C Enable Status Register                           (0x9c) */
+    volatile uint32_t enable_status;
+    /* I2C SS, FS or FM+ spike suppression limit            (0xa0) */
+    volatile uint32_t fs_spklen;
+    /* reserved                                             (0xa4-0xf0) */
+    volatile uint32_t resv4[20];
+    /* I2C Component Parameter Register 1                   (0xf4) */
+    volatile uint32_t comp_param_1;
+    /* I2C Component Version Register                       (0xf8) */
+    volatile uint32_t comp_version;
+    /* I2C Component Type Register                          (0xfc) */
+    volatile uint32_t comp_type;
+} __attribute__((packed, aligned(4))) i2c_t;
+
+/* I2C Control Register*/
+#define I2C_CON_MASTER_MODE                     0x00000001U
+#define I2C_CON_SPEED_MASK                      0x00000006U
+#define I2C_CON_SPEED(x)                        ((x) << 1)
+#define I2C_CON_10BITADDR_SLAVE                 0x00000008U
+#define I2C_CON_RESTART_EN                      0x00000020U
+#define I2C_CON_SLAVE_DISABLE                   0x00000040U
+#define I2C_CON_STOP_DET_IFADDRESSED            0x00000080U
+#define I2C_CON_TX_EMPTY_CTRL                   0x00000100U
+
+/* I2C Target Address Register*/
+#define I2C_TAR_ADDRESS_MASK                    0x000003FFU
+#define I2C_TAR_ADDRESS(x)                      ((x) << 0)
+#define I2C_TAR_GC_OR_START                     0x00000400U
+#define I2C_TAR_SPECIAL                         0x00000800U
+#define I2C_TAR_10BITADDR_MASTER                0x00001000U
+
+/* I2C Slave Address Register*/
+#define I2C_SAR_ADDRESS_MASK                    0x000003FFU
+#define I2C_SAR_ADDRESS(x)                  ((x) << 0)
+
+/* I2C Rx/Tx Data Buffer and Command Register*/
+#define I2C_DATA_CMD_CMD                        0x00000100U
+#define I2C_DATA_CMD_DATA_MASK                  0x000000FFU
+#define I2C_DATA_CMD_DATA(x)                    ((x) << 0)
+
+/* Standard Speed I2C Clock SCL High Count Register*/
+#define I2C_SS_SCL_HCNT_COUNT_MASK              0x0000FFFFU
+#define I2C_SS_SCL_HCNT_COUNT(x)                ((x) << 0)
+
+/* Standard Speed I2C Clock SCL Low Count Register*/
+#define I2C_SS_SCL_LCNT_COUNT_MASK              0x0000FFFFU
+#define I2C_SS_SCL_LCNT_COUNT(x)                ((x) << 0)
+
+/* I2C Interrupt Status Register*/
+#define I2C_INTR_STAT_RX_UNDER                  0x00000001U
+#define I2C_INTR_STAT_RX_OVER                   0x00000002U
+#define I2C_INTR_STAT_RX_FULL                   0x00000004U
+#define I2C_INTR_STAT_TX_OVER                   0x00000008U
+#define I2C_INTR_STAT_TX_EMPTY                  0x00000010U
+#define I2C_INTR_STAT_RD_REQ                    0x00000020U
+#define I2C_INTR_STAT_TX_ABRT                   0x00000040U
+#define I2C_INTR_STAT_RX_DONE                   0x00000080U
+#define I2C_INTR_STAT_ACTIVITY                  0x00000100U
+#define I2C_INTR_STAT_STOP_DET                  0x00000200U
+#define I2C_INTR_STAT_START_DET                 0x00000400U
+#define I2C_INTR_STAT_GEN_CALL                  0x00000800U
+
+/* I2C Interrupt Mask Register*/
+#define I2C_INTR_MASK_RX_UNDER                  0x00000001U
+#define I2C_INTR_MASK_RX_OVER                   0x00000002U
+#define I2C_INTR_MASK_RX_FULL                   0x00000004U
+#define I2C_INTR_MASK_TX_OVER                   0x00000008U
+#define I2C_INTR_MASK_TX_EMPTY                  0x00000010U
+#define I2C_INTR_MASK_RD_REQ                    0x00000020U
+#define I2C_INTR_MASK_TX_ABRT                   0x00000040U
+#define I2C_INTR_MASK_RX_DONE                   0x00000080U
+#define I2C_INTR_MASK_ACTIVITY                  0x00000100U
+#define I2C_INTR_MASK_STOP_DET                  0x00000200U
+#define I2C_INTR_MASK_START_DET                 0x00000400U
+#define I2C_INTR_MASK_GEN_CALL                  0x00000800U
+
+/* I2C Raw Interrupt Status Register*/
+#define I2C_RAW_INTR_MASK_RX_UNDER              0x00000001U
+#define I2C_RAW_INTR_MASK_RX_OVER               0x00000002U
+#define I2C_RAW_INTR_MASK_RX_FULL               0x00000004U
+#define I2C_RAW_INTR_MASK_TX_OVER               0x00000008U
+#define I2C_RAW_INTR_MASK_TX_EMPTY              0x00000010U
+#define I2C_RAW_INTR_MASK_RD_REQ                0x00000020U
+#define I2C_RAW_INTR_MASK_TX_ABRT               0x00000040U
+#define I2C_RAW_INTR_MASK_RX_DONE               0x00000080U
+#define I2C_RAW_INTR_MASK_ACTIVITY              0x00000100U
+#define I2C_RAW_INTR_MASK_STOP_DET              0x00000200U
+#define I2C_RAW_INTR_MASK_START_DET             0x00000400U
+#define I2C_RAW_INTR_MASK_GEN_CALL              0x00000800U
+
+/* I2C Receive FIFO Threshold Register*/
+#define I2C_RX_TL_VALUE_MASK                    0x00000007U
+#define I2C_RX_TL_VALUE(x)                  ((x) << 0)
+
+/* I2C Transmit FIFO Threshold Register*/
+#define I2C_TX_TL_VALUE_MASK                    0x00000007U
+#define I2C_TX_TL_VALUE(x)                  ((x) << 0)
+
+/* Clear Combined and Individual Interrupt Register*/
+#define I2C_CLR_INTR_CLR                        0x00000001U
+
+/* Clear RX_UNDER Interrupt Register*/
+#define I2C_CLR_RX_UNDER_CLR                    0x00000001U
+
+/* Clear RX_OVER Interrupt Register*/
+#define I2C_CLR_RX_OVER_CLR                     0x00000001U
+
+/* Clear TX_OVER Interrupt Register*/
+#define I2C_CLR_TX_OVER_CLR                     0x00000001U
+
+/* Clear RD_REQ Interrupt Register*/
+#define I2C_CLR_RD_REQ_CLR                      0x00000001U
+
+/* Clear TX_ABRT Interrupt Register*/
+#define I2C_CLR_TX_ABRT_CLR                     0x00000001U
+
+/* Clear RX_DONE Interrupt Register*/
+#define I2C_CLR_RX_DONE_CLR                     0x00000001U
+
+/* Clear ACTIVITY Interrupt Register*/
+#define I2C_CLR_ACTIVITY_CLR                    0x00000001U
+
+/* Clear STOP_DET Interrupt Register*/
+#define I2C_CLR_STOP_DET_CLR                    0x00000001U
+
+/* Clear START_DET Interrupt Register*/
+#define I2C_CLR_START_DET_CLR                   0x00000001U
+
+/* Clear GEN_CALL Interrupt Register*/
+#define I2C_CLR_GEN_CALL_CLR                    0x00000001U
+
+/* I2C Enable Register*/
+#define I2C_ENABLE_ENABLE                       0x00000001U
+#define I2C_ENABLE_ABORT                        0x00000002U
+#define I2C_ENABLE_TX_CMD_BLOCK                 0x00000004U
+
+/* I2C Status Register*/
+#define I2C_STATUS_ACTIVITY                     0x00000001U
+#define I2C_STATUS_TFNF                         0x00000002U
+#define I2C_STATUS_TFE                          0x00000004U
+#define I2C_STATUS_RFNE                         0x00000008U
+#define I2C_STATUS_RFF                          0x00000010U
+#define I2C_STATUS_MST_ACTIVITY                 0x00000020U
+#define I2C_STATUS_SLV_ACTIVITY                 0x00000040U
+
+/* I2C Transmit FIFO Level Register*/
+#define I2C_TXFLR_VALUE_MASK                    0x00000007U
+#define I2C_TXFLR_VALUE(x)                      ((x) << 0)
+
+/* I2C Receive FIFO Level Register*/
+#define I2C_RXFLR_VALUE_MASK                    0x00000007U
+#define I2C_RXFLR_VALUE(x)                      ((x) << 0)
+
+/* I2C SDA Hold Time Length Register*/
+#define I2C_SDA_HOLD_TX_MASK                    0x0000FFFFU
+#define I2C_SDA_HOLD_TX(x)                      ((x) << 0)
+#define I2C_SDA_HOLD_RX_MASK                    0x00FF0000U
+#define I2C_SDA_HOLD_RX(x)                      ((x) << 16)
+
+/* I2C Transmit Abort Source Register*/
+#define I2C_TX_ABRT_SOURCE_7B_ADDR_NOACK        0x00000001U
+#define I2C_TX_ABRT_SOURCE_10B_ADDR1_NOACK      0x00000002U
+#define I2C_TX_ABRT_SOURCE_10B_ADDR2_NOACK      0x00000004U
+#define I2C_TX_ABRT_SOURCE_TXDATA_NOACK         0x00000008U
+#define I2C_TX_ABRT_SOURCE_GCALL_NOACK          0x00000010U
+#define I2C_TX_ABRT_SOURCE_GCALL_READ           0x00000020U
+#define I2C_TX_ABRT_SOURCE_HS_ACKDET            0x00000040U
+#define I2C_TX_ABRT_SOURCE_SBYTE_ACKDET         0x00000080U
+#define I2C_TX_ABRT_SOURCE_HS_NORSTRT           0x00000100U
+#define I2C_TX_ABRT_SOURCE_SBYTE_NORSTRT        0x00000200U
+#define I2C_TX_ABRT_SOURCE_10B_RD_NORSTRT       0x00000400U
+#define I2C_TX_ABRT_SOURCE_MASTER_DIS           0x00000800U
+#define I2C_TX_ABRT_SOURCE_MST_ARBLOST          0x00001000U
+#define I2C_TX_ABRT_SOURCE_SLVFLUSH_TXFIFO      0x00002000U
+#define I2C_TX_ABRT_SOURCE_SLV_ARBLOST          0x00004000U
+#define I2C_TX_ABRT_SOURCE_SLVRD_INTX           0x00008000U
+#define I2C_TX_ABRT_SOURCE_USER_ABRT            0x00010000U
+
+/* DMA Control Register*/
+#define I2C_DMA_CR_RDMAE                        0x00000001U
+#define I2C_DMA_CR_TDMAE                        0x00000002U
+
+/* DMA Transmit Data Level Register*/
+#define I2C_DMA_TDLR_VALUE_MASK                 0x00000007U
+#define I2C_DMA_TDLR_VALUE(x)                   ((x) << 0)
+
+/* DMA Receive Data Level Register*/
+#define I2C_DMA_RDLR_VALUE_MASK                 0x00000007U
+#define I2C_DMA_RDLR_VALUE(x)                   ((x) << 0)
+
+/* I2C SDA Setup Register*/
+#define I2C_SDA_SETUP_VALUE_MASK                0x000000FFU
+#define I2C_SDA_SETUP_VALUE(x)                  ((x) << 0)
+
+/* I2C ACK General Call Register*/
+#define I2C_ACK_GENERAL_CALL_ENABLE             0x00000001U
+
+/* I2C Enable Status Register*/
+#define I2C_ENABLE_STATUS_IC_ENABLE             0x00000001U
+#define I2C_ENABLE_STATUS_SLV_DIS_BUSY          0x00000002U
+#define I2C_ENABLE_STATUS_SLV_RX_DATA_LOST      0x00000004U
+
+/* I2C SS, FS or FM+ spike suppression limit*/
+#define I2C_FS_SPKLEN_VALUE_MASK                0x000000FFU
+#define I2C_FS_SPKLEN_VALUE(x)                  ((x) << 0)
+
+/* Component Parameter Register 1*/
+#define I2C_COMP_PARAM1_APB_DATA_WIDTH          0x00000003U
+#define I2C_COMP_PARAM1_MAX_SPEED_MODE          0x0000000CU
+#define I2C_COMP_PARAM1_HC_COUNT_VALUES         0x00000010U
+#define I2C_COMP_PARAM1_INTR_IO                 0x00000020U
+#define I2C_COMP_PARAM1_HAS_DMA                 0x00000040U
+#define I2C_COMP_PARAM1_ENCODED_PARAMS          0x00000080U
+#define I2C_COMP_PARAM1_RX_BUFFER_DEPTH         0x0000FF00U
+#define I2C_COMP_PARAM1_TX_BUFFER_DEPTH         0x00FF0000U
+
+/* I2C Component Version Register*/
+#define I2C_COMP_VERSION_VALUE                  0xFFFFFFFFU
+
+/* I2C Component Type Register*/
+#define I2C_COMP_TYPE_VALUE                     0xFFFFFFFFU
+/* clang-format on */
+
+extern volatile i2c_t *const i2c[3];
+
+typedef enum _i2c_device_number
+{
+    I2C_DEVICE_0,
+    I2C_DEVICE_1,
+    I2C_DEVICE_2,
+    I2C_DEVICE_MAX,
+} i2c_device_number_t;
+
+typedef enum _i2c_bus_speed_mode
+{
+    I2C_BS_STANDARD,
+    I2C_BS_FAST,
+    I2C_BS_HIGHSPEED
+} i2c_bus_speed_mode_t;
+
+typedef enum _i2c_event
+{
+    I2C_EV_START,
+    I2C_EV_RESTART,
+    I2C_EV_STOP
+} i2c_event_id_t;
+
+typedef struct _i2c_slave_handler
+{
+    void(*on_receive)(uint32_t data);
+    uint32_t(*on_transmit)();
+    void(*on_event)(i2c_event_id_t event);
+} i2c_slave_handler_t;
+
+typedef enum _i2c_transfer_mode
+{
+    I2C_SEND,
+    I2C_RECEIVE,
+} i2c_transfer_mode_t;
+
+typedef struct _i2c_data_t
+{
+    dmac_channel_number_t tx_channel;
+    dmac_channel_number_t rx_channel;
+    uint32_t *tx_buf;
+    size_t tx_len;
+    uint32_t *rx_buf;
+    size_t rx_len;
+    i2c_transfer_mode_t TransferMode;
+} i2c_data_t;
+
+/**
+ * @brief       Set i2c params
+ *
+ * @param[in]   i2c_num             i2c number
+ * @param[in]   slave_address       i2c slave device address
+ * @param[in]   address_width       address width 7bit or 10bit
+ * @param[in]   i2c_clk             i2c clk rate
+ */
+void i2c_init(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,
+              uint32_t i2c_clk);
+
+/**
+ * @brief       I2c send data
+ *
+ * @param[in]   i2c_num         i2c number
+ * @param[in]   SendBuf        send data
+ * @param[in]   send_buf_len    send data length
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int i2c_send_data(i2c_device_number_t i2c_num, const uint8_t *SendBuf, size_t send_buf_len);
+
+/**
+ * @brief       Init i2c as slave mode.
+ *
+ * @param[in]   i2c_num             i2c number
+ * @param[in]   slave_address       i2c slave device address
+ * @param[in]   address_width       address width 7bit or 10bit
+ * @param[in]   handler             Handle of i2c slave interrupt function.
+ */
+void i2c_init_as_slave(i2c_device_number_t i2c_num, uint32_t slave_address, uint32_t address_width,
+    const i2c_slave_handler_t *handler);
+
+/**
+ * @brief       I2c send data by dma
+ *
+ * @param[in]   dma_channel_num     dma channel
+ * @param[in]   i2c_num             i2c number
+ * @param[in]   SendBuf            send data
+ * @param[in]   send_buf_len        send data length
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+void i2c_send_data_dma(dmac_channel_number_t dma_channel_num, i2c_device_number_t i2c_num, const uint8_t *SendBuf,
+                       size_t send_buf_len);
+
+/**
+ * @brief       I2c receive data
+ *
+ * @param[in]   i2c_num             i2c number
+ * @param[in]   SendBuf            send data address
+ * @param[in]   send_buf_len        length of send buf
+ * @param[in]   receive_buf         receive buf address
+ * @param[in]   receive_buf_len     length of receive buf
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+*/
+int i2c_recv_data(i2c_device_number_t i2c_num, const uint8_t *SendBuf, size_t send_buf_len, uint8_t *receive_buf,
+                  size_t receive_buf_len);
+
+/**
+ * @brief       I2c receive data by dma
+ *
+ * @param[in]   dma_send_channel_num        send dma channel
+ * @param[in]   dma_receive_channel_num     receive dma channel
+ * @param[in]   i2c_num                     i2c number
+ * @param[in]   SendBuf                    send data address
+ * @param[in]   send_buf_len                length of send buf
+ * @param[in]   receive_buf                 receive buf address
+ * @param[in]   receive_buf_len             length of receive buf
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+*/
+void i2c_recv_data_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num,
+                       i2c_device_number_t i2c_num, const uint8_t *SendBuf, size_t send_buf_len,
+                       uint8_t *receive_buf, size_t receive_buf_len);
+/**
+ * @brief       I2c handle transfer data operations
+ *
+ * @param[in]   i2c_num             i2c number
+ * @param[in]   data                i2c data information
+ * @param[in]   cb                  i2c dma callback
+ *
+*/
+void i2c_handle_data_dma(i2c_device_number_t i2c_num, i2c_data_t data, plic_interrupt_t *cb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HARDWARE_I2C_H__ */

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/hardware_rtc.h

@@ -0,0 +1,448 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/**
+ * @file
+ * @brief      A real-time clock (RTC) is a computer clock that keeps track of
+ *             the current time.
+ */
+
+/**
+* @file hardware_rtc.h
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef __HARDWARE_RTC_H__
+#define __HARDWARE_RTC_H__
+
+#include <platform.h>
+#include <stdint.h>
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief      RTC timer mode
+ *
+ *             Timer mode selector
+ *             | Mode | Description            |
+ *             |------|------------------------|
+ *             | 0    | Timer pause            |
+ *             | 1    | Timer time running     |
+ *             | 2    | Timer time setting     |
+ */
+typedef enum _rtc_timer_mode_e
+{
+    /* 0: Timer pause */
+    RTC_TIMER_PAUSE,
+    /* 1: Timer time running */
+    RTC_TIMER_RUNNING,
+    /* 2: Timer time setting */
+    RTC_TIMER_SETTING,
+    /* Max count of this enum*/
+    RTC_TIMER_MAX
+} rtc_timer_mode_t;
+
+/*
+ * @brief      RTC tick interrupt mode
+ *
+ *             Tick interrupt mode selector
+ *             | Mode | Description            |
+ *             |------|------------------------|
+ *             | 0    | Interrupt every second |
+ *             | 1    | Interrupt every minute |
+ *             | 2    | Interrupt every hour   |
+ *             | 3    | Interrupt every day    |
+ */
+typedef enum _rtc_tick_interrupt_mode_e
+{
+    /* 0: Interrupt every second */
+    RTC_INT_SECOND,
+    /* 1: Interrupt every minute */
+    RTC_INT_MINUTE,
+    /* 2: Interrupt every hour */
+    RTC_INT_HOUR,
+    /* 3: Interrupt every day */
+    RTC_INT_DAY,
+    /* Max count of this enum*/
+    RTC_INT_MAX
+} rtc_tick_interrupt_mode_t;
+
+/**
+ * @brief      RTC mask structure
+ *
+ *             RTC mask structure for common use
+ */
+typedef struct _rtc_mask
+{
+    /* Reserved */
+    uint32_t resv : 1;
+    /* Second mask */
+    uint32_t second : 1;
+    /* Minute mask */
+    uint32_t minute : 1;
+    /* Hour mask */
+    uint32_t hour : 1;
+    /* Week mask */
+    uint32_t week : 1;
+    /* Day mask */
+    uint32_t day : 1;
+    /* Month mask */
+    uint32_t month : 1;
+    /* Year mask */
+    uint32_t year : 1;
+} __attribute__((packed, aligned(1))) rtc_mask_t;
+
+/**
+ * @brief       RTC register
+ *
+ * @note        RTC register table
+ *
+ * | Offset    | Name           | Description                         |
+ * |-----------|----------------|-------------------------------------|
+ * | 0x00      | date           | Timer date information              |
+ * | 0x04      | time           | Timer time information              |
+ * | 0x08      | alarm_date     | Alarm date information              |
+ * | 0x0c      | alarm_time     | Alarm time information              |
+ * | 0x10      | initial_count  | Timer counter initial value         |
+ * | 0x14      | current_count  | Timer counter current value         |
+ * | 0x18      | interrupt_ctrl | RTC interrupt settings              |
+ * | 0x1c      | register_ctrl  | RTC register settings               |
+ * | 0x20      | reserved0      | Reserved                            |
+ * | 0x24      | reserved1      | Reserved                            |
+ * | 0x28      | extended       | Timer extended information          |
+ *
+ */
+
+
+/**
+ * @brief       Timer date information
+ *
+ *              No. 0 Register (0x00)
+ */
+typedef struct _rtc_date
+{
+    /* Week. Range [0,6]. 0 is Sunday. */
+    uint32_t week : 3;
+    /* Reserved */
+    uint32_t resv0 : 5;
+    /* Day. Range [1,31] or [1,30] or [1,29] or [1,28] */
+    uint32_t day : 5;
+    /* Reserved */
+    uint32_t resv1 : 3;
+    /* Month. Range [1,12] */
+    uint32_t month : 4;
+    /* Year. Range [0,99] */
+    uint32_t year : 12;
+} __attribute__((packed, aligned(4))) rtc_date_t;
+
+/**
+ * @brief       Timer time information
+ *
+ *              No. 1 Register (0x04)
+ */
+typedef struct _rtc_time
+{
+    /* Reserved */
+    uint32_t resv0 : 10;
+    /* Second. Range [0,59] */
+    uint32_t second : 6;
+    /* Minute. Range [0,59] */
+    uint32_t minute : 6;
+    /* Reserved */
+    uint32_t resv1 : 2;
+    /* Hour. Range [0,23] */
+    uint32_t hour : 5;
+    /* Reserved */
+    uint32_t resv2 : 3;
+} __attribute__((packed, aligned(4))) rtc_time_t;
+
+/**
+ * @brief       Alarm date information
+ *
+ *              No. 2 Register (0x08)
+ */
+typedef struct _rtc_alarm_date
+{
+    /* Alarm Week. Range [0,6]. 0 is Sunday. */
+    uint32_t week : 3;
+    /* Reserved */
+    uint32_t resv0 : 5;
+    /* Alarm Day. Range [1,31] or [1,30] or [1,29] or [1,28] */
+    uint32_t day : 5;
+    /* Reserved */
+    uint32_t resv1 : 3;
+    /* Alarm Month. Range [1,12] */
+    uint32_t month : 4;
+    /* Alarm Year. Range [0,99] */
+    uint32_t year : 12;
+} __attribute__((packed, aligned(4))) rtc_alarm_date_t;
+
+/**
+ * @brief       Alarm time information
+ *
+ *              No. 3 Register (0x0c)
+ */
+typedef struct _rtc_alarm_time
+{
+    /* Reserved */
+    uint32_t resv0 : 10;
+    /* Alarm Second. Range [0,59] */
+    uint32_t second : 6;
+    /* Alarm Minute. Range [0,59] */
+    uint32_t minute : 6;
+    /* Reserved */
+    uint32_t resv1 : 2;
+    /* Alarm Hour. Range [0,23] */
+    uint32_t hour : 5;
+    /* Reserved */
+    uint32_t resv2 : 3;
+} __attribute__((packed, aligned(4))) rtc_alarm_time_t;
+
+/**
+ * @brief       Timer counter initial value
+ *
+ *              No. 4 Register (0x10)
+ */
+typedef struct _rtc_initial_count
+{
+    /* RTC counter initial value */
+    uint32_t count : 32;
+} __attribute__((packed, aligned(4))) rtc_initial_count_t;
+
+/**
+ * @brief       Timer counter current value
+ *
+ *              No. 5 Register (0x14)
+ */
+typedef struct _rtc_current_count
+{
+    /* RTC counter current value */
+    uint32_t count : 32;
+} __attribute__((packed, aligned(4))) rtc_current_count_t;
+
+/**
+ * @brief      RTC interrupt settings
+ *
+ *             No. 6 Register (0x18)
+ */
+typedef struct _rtc_interrupt_ctrl
+{
+    /* Reserved */
+    uint32_t tick_enable : 1;
+    /* Alarm interrupt enable */
+    uint32_t alarm_enable : 1;
+    /* Tick interrupt enable */
+    uint32_t tick_int_mode : 2;
+    /* Reserved */
+    uint32_t resv : 20;
+    /* Alarm compare mask for interrupt */
+    uint32_t alarm_compare_mask : 8;
+} __attribute__((packed, aligned(4))) rtc_interrupt_ctrl_t;
+
+/**
+ * @brief       RTC register settings
+ *
+ *              No. 7 Register (0x1c)
+ */
+typedef struct _rtc_register_ctrl
+{
+    /* RTC timer read enable */
+    uint32_t read_enable : 1;
+    /* RTC timer write enable */
+    uint32_t write_enable : 1;
+    /* Reserved */
+    uint32_t resv0 : 11;
+    /* RTC timer mask */
+    uint32_t TimerMask : 8;
+    /* RTC alarm mask */
+    uint32_t alarm_mask : 8;
+    /* RTC counter initial count value mask */
+    uint32_t initial_count_mask : 1;
+    /* RTC interrupt register mask */
+    uint32_t interrupt_register_mask : 1;
+    /* Reserved */
+    uint32_t resv1 : 1;
+} __attribute__((packed, aligned(4))) rtc_register_ctrl_t;
+
+/**
+ * @brief       Reserved
+ *
+ *              No. 8 Register (0x20)
+ */
+typedef struct _rtc_reserved0
+{
+    /* Reserved */
+    uint32_t resv : 32;
+} __attribute__((packed, aligned(4))) rtc_reserved0_t;
+
+/**
+ * @brief      Reserved
+ *
+ *             No. 9 Register (0x24)
+ */
+typedef struct _rtc_reserved1
+{
+    /* Reserved */
+    uint32_t resv : 32;
+} __attribute__((packed, aligned(4))) rtc_reserved1_t;
+
+/**
+ * @brief      Timer extended information
+ *
+ *             No. 10 Register (0x28)
+ */
+typedef struct _rtc_extended
+{
+    /* Century. Range [0,31] */
+    uint32_t century : 5;
+    /* Is leap year. 1 is leap year, 0 is not leap year */
+    uint32_t leap_year : 1;
+    /* Reserved */
+    uint32_t resv : 26;
+} __attribute__((packed, aligned(4))) rtc_extended_t;
+
+
+/**
+ * @brief       Real-time clock struct
+ *
+ *              A real-time clock (RTC) is a computer clock that keeps track of
+ *              the current time.
+ */
+typedef struct _rtc
+{
+    /* No. 0 (0x00): Timer date information */
+    rtc_date_t date;
+    /* No. 1 (0x04): Timer time information */
+    rtc_time_t time;
+    /* No. 2 (0x08): Alarm date information */
+    rtc_alarm_date_t alarm_date;
+    /* No. 3 (0x0c): Alarm time information */
+    rtc_alarm_time_t alarm_time;
+    /* No. 4 (0x10): Timer counter initial value */
+    rtc_initial_count_t initial_count;
+    /* No. 5 (0x14): Timer counter current value */
+    rtc_current_count_t current_count;
+    /* No. 6 (0x18): RTC interrupt settings */
+    rtc_interrupt_ctrl_t interrupt_ctrl;
+    /* No. 7 (0x1c): RTC register settings */
+    rtc_register_ctrl_t register_ctrl;
+    /* No. 8 (0x20): Reserved */
+    rtc_reserved0_t reserved0;
+    /* No. 9 (0x24): Reserved */
+    rtc_reserved1_t reserved1;
+    /* No. 10 (0x28): Timer extended information */
+    rtc_extended_t extended;
+} __attribute__((packed, aligned(4))) rtc_t;
+
+
+/**
+ * @brief       Real-time clock object
+ */
+extern volatile rtc_t *const rtc;
+extern volatile uint32_t *const rtc_base;
+
+/**
+ * @brief       Set date time to RTC
+ *
+ * @param[in]   year        The year
+ * @param[in]   month       The month
+ * @param[in]   day         The day
+ * @param[in]   hour        The hour
+ * @param[in]   minute      The minute
+ * @param[in]   second      The second
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int rtc_timer_set(int year, int month, int day, int hour, int minute, int second);
+
+/**
+ * @brief       Get date time from RTC
+ *
+ * @param       year        The year
+ * @param       month       The month
+ * @param       day         The day
+ * @param       hour        The hour
+ * @param       minute      The minute
+ * @param       second      The second
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int rtc_timer_get(int *year, int *month, int *day, int *hour, int *minute, int *second);
+
+/**
+ * @brief       Initialize RTC
+ *
+ * @return      Result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int rtc_init(void);
+
+/**
+ * @brief       Set RTC in protect mode or not
+ *
+ * @param       enable        Enable flag
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int rtc_protect_set(int enable);
+
+/**
+ * @brief       Set RTC timer mode
+ *
+ * @param       timer_mode        Timer mode
+ *
+ */
+void rtc_timer_set_mode(rtc_timer_mode_t timer_mode);
+
+/**
+ * @brief       Set RTC timer clock frequency
+ *
+ * @param       frequency        Frequency
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int rtc_timer_set_clock_frequency(unsigned int frequency);
+
+/**
+ * @brief       Set RTC timer clock count value
+ *
+ * @param       count        Count
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int rtc_timer_set_clock_count_value(unsigned int  count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRIVER_RTC_H */

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/hardware_spi.h

@@ -0,0 +1,494 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file hardware_spi.h
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef __HARDWARE_SPI_H__
+#define __HARDWARE_SPI_H__
+
+#include "dmac.h"
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* clang-format off */
+typedef struct _spi
+{
+    /* SPI Control Register 0                                    (0x00)*/
+    volatile uint32_t ctrlr0;
+    /* SPI Control Register 1                                    (0x04)*/
+    volatile uint32_t ctrlr1;
+    /* SPI Enable Register                                       (0x08)*/
+    volatile uint32_t ssienr;
+    /* SPI Microwire Control Register                            (0x0c)*/
+    volatile uint32_t mwcr;
+    /* SPI Slave Enable Register                                 (0x10)*/
+    volatile uint32_t ser;
+    /* SPI Baud Rate Select                                      (0x14)*/
+    volatile uint32_t baudr;
+    /* SPI Transmit FIFO Threshold Level                         (0x18)*/
+    volatile uint32_t txftlr;
+    /* SPI Receive FIFO Threshold Level                          (0x1c)*/
+    volatile uint32_t rxftlr;
+    /* SPI Transmit FIFO Level Register                          (0x20)*/
+    volatile uint32_t txflr;
+    /* SPI Receive FIFO Level Register                           (0x24)*/
+    volatile uint32_t rxflr;
+    /* SPI Status Register                                       (0x28)*/
+    volatile uint32_t sr;
+    /* SPI Interrupt Mask Register                               (0x2c)*/
+    volatile uint32_t imr;
+    /* SPI Interrupt Status Register                             (0x30)*/
+    volatile uint32_t isr;
+    /* SPI Raw Interrupt Status Register                         (0x34)*/
+    volatile uint32_t risr;
+    /* SPI Transmit FIFO Overflow Interrupt Clear Register       (0x38)*/
+    volatile uint32_t txoicr;
+    /* SPI Receive FIFO Overflow Interrupt Clear Register        (0x3c)*/
+    volatile uint32_t rxoicr;
+    /* SPI Receive FIFO Underflow Interrupt Clear Register       (0x40)*/
+    volatile uint32_t rxuicr;
+    /* SPI Multi-Master Interrupt Clear Register                 (0x44)*/
+    volatile uint32_t msticr;
+    /* SPI Interrupt Clear Register                              (0x48)*/
+    volatile uint32_t icr;
+    /* SPI DMA Control Register                                  (0x4c)*/
+    volatile uint32_t dmacr;
+    /* SPI DMA Transmit Data Level                               (0x50)*/
+    volatile uint32_t dmatdlr;
+    /* SPI DMA Receive Data Level                                (0x54)*/
+    volatile uint32_t dmardlr;
+    /* SPI Identification Register                               (0x58)*/
+    volatile uint32_t idr;
+    /* SPI DWC_ssi component version                             (0x5c)*/
+    volatile uint32_t ssic_version_id;
+    /* SPI Data Register 0-36                                    (0x60 -- 0xec)*/
+    volatile uint32_t dr[36];
+    /* SPI RX Sample Delay Register                              (0xf0)*/
+    volatile uint32_t rx_sample_delay;
+    /* SPI SPI Control Register                                  (0xf4)*/
+    volatile uint32_t spi_ctrlr0;
+    /* reserved                                                  (0xf8)*/
+    volatile uint32_t resv;
+    /* SPI XIP Mode bits                                         (0xfc)*/
+    volatile uint32_t xip_mode_bits;
+    /* SPI XIP INCR transfer opcode                              (0x100)*/
+    volatile uint32_t xip_incr_inst;
+    /* SPI XIP WRAP transfer opcode                              (0x104)*/
+    volatile uint32_t xip_wrap_inst;
+    /* SPI XIP Control Register                                  (0x108)*/
+    volatile uint32_t xip_ctrl;
+    /* SPI XIP Slave Enable Register                             (0x10c)*/
+    volatile uint32_t xip_ser;
+    /* SPI XIP Receive FIFO Overflow Interrupt Clear Register    (0x110)*/
+    volatile uint32_t xrxoicr;
+    /* SPI XIP time out register for continuous transfers        (0x114)*/
+    volatile uint32_t xip_cnt_time_out;
+    volatile uint32_t endian;
+} __attribute__((packed, aligned(4))) spi_t;
+/* clang-format on */
+
+typedef enum _spi_device_num
+{
+    SPI_DEVICE_0,
+    SPI_DEVICE_1,
+    SPI_DEVICE_2,
+    SPI_DEVICE_3,
+    SPI_DEVICE_MAX,
+} spi_device_num_t;
+
+typedef enum _spi_work_mode
+{
+    SPI_WORK_MODE_0,
+    SPI_WORK_MODE_1,
+    SPI_WORK_MODE_2,
+    SPI_WORK_MODE_3,
+} spi_work_mode_t;
+
+typedef enum _spi_frame_format
+{
+    SPI_FF_STANDARD,
+    SPI_FF_DUAL,
+    SPI_FF_QUAD,
+    SPI_FF_OCTAL
+} spi_frame_format_t;
+
+typedef enum _spi_instruction_address_trans_mode
+{
+    SPI_AITM_STANDARD,
+    SPI_AITM_ADDR_STANDARD,
+    SPI_AITM_AS_FRAME_FORMAT
+} spi_instruction_address_trans_mode_t;
+
+typedef enum _spi_transfer_mode
+{
+    SPI_TMOD_TRANS_RECV,
+    SPI_TMOD_TRANS,
+    SPI_TMOD_RECV,
+    SPI_TMOD_EEROM
+} spi_transfer_mode_t;
+
+
+typedef enum _spi_transfer_width
+{
+    SPI_TRANS_CHAR  = 0x1,
+    SPI_TRANS_SHORT = 0x2,
+    SPI_TRANS_INT   = 0x4,
+} spi_transfer_width_t;
+
+typedef enum _spi_chip_select
+{
+    SPI_CHIP_SELECT_0,
+    SPI_CHIP_SELECT_1,
+    SPI_CHIP_SELECT_2,
+    SPI_CHIP_SELECT_3,
+    SPI_CHIP_SELECT_MAX,
+} spi_chip_select_t;
+
+typedef enum
+{
+    WRITE_CONFIG,
+    READ_CONFIG,
+    WRITE_DATA_BYTE,
+    READ_DATA_BYTE,
+    WRITE_DATA_BLOCK,
+    READ_DATA_BLOCK,
+} spi_slave_command_e;
+
+typedef struct
+{
+    uint8_t cmd;
+    uint8_t err;
+    uint32_t addr;
+    uint32_t len;
+} spi_slave_command_t;
+
+typedef enum
+{
+    IDLE,
+    COMMAND,
+    TRANSFER,
+} spi_slave_status_e;
+
+typedef int (*spi_slave_receive_callback_t)(void *ctx);
+
+typedef struct _spi_slave_instance
+{
+    uint8_t int_pin;
+    uint8_t ready_pin;
+    dmac_channel_number_t dmac_channel;
+    uint8_t dfs;
+    uint8_t slv_oe;
+    uint8_t work_mode;
+    size_t data_bit_length;
+    volatile spi_slave_status_e status;
+    volatile spi_slave_command_t command;
+    volatile uint8_t *config_ptr;
+    uint32_t config_len;
+    spi_slave_receive_callback_t callback;
+} spi_slave_instance_t;
+
+typedef struct _spi_data_t
+{
+    dmac_channel_number_t tx_channel;
+    dmac_channel_number_t rx_channel;
+    uint32_t *tx_buf;
+    size_t tx_len;
+    uint32_t *rx_buf;
+    size_t rx_len;
+    spi_transfer_mode_t TransferMode;
+    bool fill_mode;
+} spi_data_t;
+
+extern volatile spi_t *const spi[4];
+
+/**
+ * @brief       Set spi configuration
+ *
+ * @param[in]   spi_num             Spi bus number
+ * @param[in]   mode                Spi mode
+ * @param[in]   frame_format        Spi frame format
+ * @param[in]   data_bit_length     Spi data bit length
+ * @param[in]   endian              0:little-endian 1:big-endian
+ *
+ * @return      Void
+ */
+void spi_init(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format,
+              size_t data_bit_length, uint32_t endian);
+
+/**
+ * @brief       Set multiline configuration
+ *
+ * @param[in]   spi_num                                 Spi bus number
+ * @param[in]   instruction_length                      Instruction length
+ * @param[in]   address_length                          Address length
+ * @param[in]   wait_cycles                             Wait cycles
+ * @param[in]   instruction_address_trans_mode          Spi transfer mode
+ *
+ */
+void spi_init_non_standard(spi_device_num_t spi_num, uint32_t instruction_length, uint32_t address_length,
+                           uint32_t wait_cycles, spi_instruction_address_trans_mode_t instruction_address_trans_mode);
+
+/**
+ * @brief       Spi send data
+ *
+ * @param[in]   spi_num         Spi bus number
+ * @param[in]   chip_select     Spi chip select
+ * @param[in]   CmdBuff        Spi command buffer point
+ * @param[in]   CmdLen         Spi command length
+ * @param[in]   tx_buff         Spi transmit buffer point
+ * @param[in]   tx_len          Spi transmit buffer length
+ *
+ * @return      Result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+void spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *CmdBuff,
+                            size_t CmdLen, const uint8_t *tx_buff, size_t tx_len);
+
+/**
+ * @brief       Spi receive data
+ *
+ * @param[in]   spi_num             Spi bus number
+ * @param[in]   chip_select         Spi chip select
+ * @param[in]   CmdBuff            Spi command buffer point
+ * @param[in]   CmdLen             Spi command length
+ * @param[in]   rx_buff             Spi receive buffer point
+ * @param[in]   rx_len              Spi receive buffer length
+ *
+ * @return      Result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+void spi_receive_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *CmdBuff,
+                               size_t CmdLen, uint8_t *rx_buff, size_t rx_len);
+
+/**
+ * @brief       Spi special receive data
+ *
+ * @param[in]   spi_num         Spi bus number
+ * @param[in]   chip_select     Spi chip select
+ * @param[in]   CmdBuff        Spi command buffer point
+ * @param[in]   CmdLen         Spi command length
+ * @param[in]   rx_buff         Spi receive buffer point
+ * @param[in]   rx_len          Spi receive buffer length
+ *
+ * @return      Result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+void spi_receive_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *CmdBuff,
+                               size_t CmdLen, uint8_t *rx_buff, size_t rx_len);
+
+/**
+ * @brief       Spi special send data
+ *
+ * @param[in]   spi_num         Spi bus number
+ * @param[in]   chip_select     Spi chip select
+ * @param[in]   CmdBuff        Spi command buffer point
+ * @param[in]   CmdLen         Spi command length
+ * @param[in]   tx_buff         Spi transmit buffer point
+ * @param[in]   tx_len          Spi transmit buffer length
+ *
+ * @return      Result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+void spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *CmdBuff,
+                            size_t CmdLen, const uint8_t *tx_buff, size_t tx_len);
+
+/**
+ * @brief       Spi send data by dma
+ *
+ * @param[in]   channel_num     Dmac channel number
+ * @param[in]   spi_num         Spi bus number
+ * @param[in]   chip_select     Spi chip select
+ * @param[in]   CmdBuff        Spi command buffer point
+ * @param[in]   CmdLen         Spi command length
+ * @param[in]   tx_buff         Spi transmit buffer point
+ * @param[in]   tx_len          Spi transmit buffer length
+ *
+ * @return      Result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+void spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num,
+                                spi_chip_select_t chip_select,
+                                const uint8_t *CmdBuff, size_t CmdLen, const uint8_t *tx_buff, size_t tx_len);
+
+/**
+ * @brief       Spi receive data by dma
+ *
+ * @param[in]   w_channel_num       Dmac write channel number
+ * @param[in]   r_channel_num       Dmac read channel number
+ * @param[in]   spi_num             Spi bus number
+ * @param[in]   chip_select         Spi chip select
+ * @param[in]   CmdBuff            Spi command buffer point
+ * @param[in]   CmdLen             Spi command length
+ * @param[in]   rx_buff             Spi receive buffer point
+ * @param[in]   rx_len              Spi receive buffer length
+ *
+ * @return      Result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+void spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num,
+                                   dmac_channel_number_t dma_receive_channel_num,
+                                   spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *CmdBuff,
+                                   size_t CmdLen, uint8_t *rx_buff, size_t rx_len);
+
+/**
+ * @brief       Spi special send data by dma
+ *
+ * @param[in]   channel_num     Dmac channel number
+ * @param[in]   spi_num         Spi bus number
+ * @param[in]   chip_select     Spi chip select
+ * @param[in]   CmdBuff        Spi command buffer point
+ * @param[in]   CmdLen         Spi command length
+ * @param[in]   tx_buff         Spi transmit buffer point
+ * @param[in]   tx_len          Spi transmit buffer length
+ *
+ * @return      Result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+void spi_send_data_multiple_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num,
+                                spi_chip_select_t chip_select,
+                                const uint32_t *CmdBuff, size_t CmdLen, const uint8_t *tx_buff, size_t tx_len);
+
+/**
+ * @brief       Spi special receive data by dma
+ *
+ * @param[in]   dma_send_channel_num        Dmac write channel number
+ * @param[in]   dma_receive_channel_num     Dmac read channel number
+ * @param[in]   spi_num                     Spi bus number
+ * @param[in]   chip_select                 Spi chip select
+ * @param[in]   CmdBuff                    Spi command buffer point
+ * @param[in]   CmdLen                     Spi command length
+ * @param[in]   rx_buff                     Spi receive buffer point
+ * @param[in]   rx_len                      Spi receive buffer length
+ *
+ * @return      Result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+void spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num,
+                                   dmac_channel_number_t dma_receive_channel_num,
+                                   spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *CmdBuff,
+                                   size_t CmdLen, uint8_t *rx_buff, size_t rx_len);
+
+/**
+ * @brief       Spi fill dma
+ *
+ * @param[in]   channel_num     Dmac channel number
+ * @param[in]   spi_num         Spi bus number
+ * @param[in]   chip_select     Spi chip select
+ * @param[in]   tx_buff        Spi command buffer point
+ * @param[in]   tx_len         Spi command length
+ *
+ * @return      Result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+void spi_fill_data_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select,
+                       const uint32_t *tx_buff, size_t tx_len);
+
+/**
+ * @brief       Spi normal send by dma
+ *
+ * @param[in]   channel_num     Dmac channel number
+ * @param[in]   spi_num         Spi bus number
+ * @param[in]   chip_select     Spi chip select
+ * @param[in]   tx_buff         Spi transmit buffer point
+ * @param[in]   tx_len          Spi transmit buffer length
+ * @param[in]   stw             Spi transfer width
+ *
+ * @return      Result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+void spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num,
+                              spi_chip_select_t chip_select,
+                              const void *tx_buff, size_t tx_len, spi_transfer_width_t spi_transfer_width);
+
+/**
+ * @brief       Spi normal send by dma
+ *
+ * @param[in]   spi_num         Spi bus number
+ * @param[in]   spi_clk         Spi clock rate
+ *
+ * @return      The real spi clock rate
+ */
+uint32_t spi_set_clk_rate(spi_device_num_t spi_num, uint32_t spi_clk);
+
+/**
+ * @brief       Spi full duplex send receive data by dma
+ *
+ * @param[in]   dma_send_channel_num          Dmac write channel number
+ * @param[in]   dma_receive_channel_num       Dmac read channel number
+ * @param[in]   spi_num                       Spi bus number
+ * @param[in]   chip_select                   Spi chip select
+ * @param[in]   tx_buf                        Spi send buffer
+ * @param[in]   tx_len                        Spi send buffer length
+ * @param[in]   rx_buf                        Spi receive buffer
+ * @param[in]   rx_len                        Spi receive buffer length
+ *
+ */
+void spi_dup_send_receive_data_dma(dmac_channel_number_t dma_send_channel_num,
+                               dmac_channel_number_t dma_receive_channel_num,
+                               spi_device_num_t spi_num, spi_chip_select_t chip_select,
+                               const uint8_t *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len);
+
+/**
+ * @brief       Set spi slave configuration
+ *
+ * @param[in]   int_pin             SPI master starts sending data interrupt.
+ * @param[in]   ready_pin           SPI slave ready.
+ * @param[in]   dmac_channel        Dmac channel number for block.
+ * @param[in]   data_bit_length     Spi data bit length
+ * @param[in]   data                SPI slave device data buffer.
+ * @param[in]   len                 The length of SPI slave device data buffer.
+ * @param[in]   callback            Callback of spi slave.
+ *
+ * @return      Void
+ */
+void spi_slave_config(uint8_t int_pin, uint8_t ready_pin, dmac_channel_number_t dmac_channel, size_t data_bit_length, uint8_t *data, uint32_t len, spi_slave_receive_callback_t callback);
+
+/**
+ * @brief       Spi handle transfer data operations
+ *
+ * @param[in]   spi_num         Spi bus number
+ * @param[in]   chip_select     Spi chip select
+ * @param[in]   data            Spi transfer data information
+ * @param[in]   cb              Spi DMA callback
+ *
+ */
+void spi_handle_data_dma(spi_device_num_t spi_num, spi_chip_select_t chip_select, spi_data_t data, plic_interrupt_t *cb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HARDWARE_SPI_H__ */

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/hardware_uart.h

@@ -0,0 +1,364 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief       Universal Asynchronous Receiver/Transmitter (UART)
+ *
+ *              The UART peripheral supports the following features:
+ *
+ *              - 8-N-1 and 8-N-2 formats: 8 data bits, no parity bit, 1 start
+ *                bit, 1 or 2 stop bits
+ *
+ *              - 8-entry transmit and receive FIFO buffers with programmable
+ *                watermark interrupts
+ *
+ *              - 16× Rx oversampling with 2/3 majority voting per bit
+ *
+ *              The UART peripheral does not support hardware flow control or
+ *              other modem control signals, or synchronous serial data
+ *              tranfesrs.
+ *
+ *
+ */
+
+/**
+* @file hardware_uart.h
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef __HARDWARE_UART_H__
+#define __HARDWARE_UART_H__
+
+#include "dmac.h"
+#include <platform.h>
+#include "plic.h"
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum _uart_dev
+{
+    UART_DEV1 = 0,
+    UART_DEV2,
+    UART_DEV3,
+} uart_dev_t;
+
+typedef struct _uart
+{
+    union
+    {
+        volatile uint32_t RBR;
+        volatile uint32_t DLL;
+        volatile uint32_t THR;
+    };
+
+    union
+    {
+        volatile uint32_t DLH;
+        volatile uint32_t IER;
+    };
+
+    union
+    {
+        volatile uint32_t FCR;
+        volatile uint32_t IIR;
+    };
+
+    volatile uint32_t LCR;
+    volatile uint32_t MCR;
+    volatile uint32_t LSR;
+    volatile uint32_t MSR;
+
+    volatile uint32_t SCR;
+    volatile uint32_t LPDLL;
+    volatile uint32_t LPDLH;
+
+    volatile uint32_t reserved1[2];
+
+    union
+    {
+        volatile uint32_t SRBR[16];
+        volatile uint32_t STHR[16];
+    };
+
+    volatile uint32_t FAR;
+    volatile uint32_t TFR;
+    volatile uint32_t RFW;
+    volatile uint32_t USR;
+    volatile uint32_t TFL;
+    volatile uint32_t RFL;
+    volatile uint32_t SRR;
+    volatile uint32_t SRTS;
+    volatile uint32_t SBCR;
+    volatile uint32_t SDMAM;
+    volatile uint32_t SFE;
+    volatile uint32_t SRT;
+    volatile uint32_t STET;
+    volatile uint32_t HTX;
+    volatile uint32_t DMASA;
+    volatile uint32_t TCR;
+    volatile uint32_t DE_EN;
+    volatile uint32_t RE_EN;
+    volatile uint32_t DET;
+    volatile uint32_t TAT;
+    volatile uint32_t DLF;
+    volatile uint32_t RAR;
+    volatile uint32_t TAR;
+    volatile uint32_t LCR_EXT;
+    volatile uint32_t reserved2[9];
+    volatile uint32_t CPR;
+    volatile uint32_t UCV;
+    volatile uint32_t CTR;
+} UartT;
+
+typedef enum _uart_device_number
+{
+    UART_DEVICE_1,
+    UART_DEVICE_2,
+    UART_DEVICE_3,
+    UART_DEVICE_MAX,
+} UartDeviceNumberT;
+
+typedef enum _uart_bitwidth
+{
+    UART_BITWIDTH_5BIT = 5,
+    UART_BITWIDTH_6BIT,
+    UART_BITWIDTH_7BIT,
+    UART_BITWIDTH_8BIT,
+} UartBitwidthPointer;
+
+typedef enum _uart_stopbit
+{
+    UART_STOP_1,
+    UART_STOP_1_5,
+    UART_STOP_2
+} UartStopbitT;
+
+typedef enum _uart_rede_sel
+{
+    DISABLE = 0,
+    ENABLE,
+} uart_rede_sel_t;
+
+typedef enum _uart_parity
+{
+    UART_PARITY_NONE,
+    UART_PARITY_ODD,
+    UART_PARITY_EVEN
+} UartParityT;
+
+typedef enum _uart_interrupt_mode
+{
+    UART_SEND = 1,
+    UART_RECEIVE = 2,
+} UartInterruptModeT;
+
+typedef enum _uart_send_trigger
+{
+    UART_SEND_FIFO_0,
+    UART_SEND_FIFO_2,
+    UART_SEND_FIFO_4,
+    UART_SEND_FIFO_8,
+} uart_send_trigger_t;
+
+typedef enum _uart_receive_trigger
+{
+    UART_RECEIVE_FIFO_1,
+    UART_RECEIVE_FIFO_4,
+    UART_RECEIVE_FIFO_8,
+    UART_RECEIVE_FIFO_14,
+} uart_receive_trigger_t;
+
+typedef struct _uart_data_t
+{
+    dmac_channel_number_t tx_channel;
+    dmac_channel_number_t rx_channel;
+    uint32_t *tx_buf;
+    size_t tx_len;
+    uint32_t *rx_buf;
+    size_t rx_len;
+    UartInterruptModeT TransferMode;
+} uart_data_t;
+
+/**
+ * @brief       Send data from uart
+ *
+ * @param[in]   channel     Uart index
+ * @param[in]   buffer      The data be transfer
+ * @param[in]   len         The data length
+ *
+ * @return      Transfer length
+ */
+int UartSendData(UartDeviceNumberT channel, const char *buffer, size_t BufLen);
+
+/**
+ * @brief       Read data from uart
+ *
+ * @param[in]   channel     Uart index
+ * @param[in]   buffer      The Data received
+ * @param[in]   len         Receive length
+ *
+ * @return      Receive length
+ */
+int UartReceiveData(UartDeviceNumberT channel, char *buffer, size_t BufLen);
+
+/**
+ * @brief       Init uart
+ *
+ * @param[in]   channel     Uart index
+ *
+ */
+void UartInit(UartDeviceNumberT channel);
+
+/**
+ * @brief       Set uart param
+ *
+ * @param[in]   channel         Uart index
+ * @param[in]   BaudRate       Baudrate
+ * @param[in]   DataWidth      Data width
+ * @param[in]   stopbit         Stop bit
+ * @param[in]   parity          Odd Even parity
+ *
+ */
+void uart_config(UartDeviceNumberT channel, uint32_t BaudRate, UartBitwidthPointer DataWidth, UartStopbitT stopbit, UartParityT parity);
+
+/**
+ * @brief       Set uart param
+ *
+ * @param[in]   channel         Uart index
+ * @param[in]   BaudRate       Baudrate
+ * @param[in]   DataWidth      Data width
+ * @param[in]   stopbit         Stop bit
+ * @param[in]   parity          Odd Even parity
+ *
+ */
+void uart_configure(UartDeviceNumberT channel, uint32_t BaudRate, UartBitwidthPointer DataWidth, UartStopbitT stopbit, UartParityT parity);
+
+/**
+ * @brief       Register uart interrupt
+ *
+ * @param[in]   channel             Uart index
+ * @param[in]   interrupt_mode      Interrupt Mode receive or send
+ * @param[in]   uart_callback       Call back
+ * @param[in]   ctx                 Param of call back
+ * @param[in]   priority            Interrupt priority
+ *
+ */
+void uart_irq_register(UartDeviceNumberT channel, UartInterruptModeT interrupt_mode, plic_irq_callback_t uart_callback, void *ctx, uint32_t priority);
+
+/**
+ * @brief       Deregister uart interrupt
+ *
+ * @param[in]   channel             Uart index
+ * @param[in]   interrupt_mode      Interrupt Mode receive or send
+ *
+ */
+void uart_irq_unregister(UartDeviceNumberT channel, UartInterruptModeT interrupt_mode);
+
+/**
+ * @brief       Set send interrupt threshold
+ *
+ * @param[in]   channel             Uart index
+ * @param[in]   trigger             Threshold of send interrupt
+ *
+ */
+void UartSetSendTrigger(UartDeviceNumberT channel, uart_send_trigger_t trigger);
+
+/**
+ * @brief       Set receive interrupt threshold
+ *
+ * @param[in]   channel             Uart index
+ * @param[in]   trigger             Threshold of receive interrupt
+ *
+ */
+void uart_set_receive_trigger(UartDeviceNumberT channel, uart_receive_trigger_t trigger);
+
+/**
+ * @brief       Send data by dma
+ *
+ * @param[in]   channel             Uart index
+ * @param[in]   dmac_channel        Dmac channel
+ * @param[in]   buffer              Send data
+ * @param[in]   BufLen             Data length
+ *
+ */
+void UartSendDataDma(UartDeviceNumberT uart_channel, dmac_channel_number_t dmac_channel, const uint8_t *buffer, size_t BufLen);
+
+/**
+ * @brief       Receive data by dma
+ *
+ * @param[in]   channel             Uart index
+ * @param[in]   dmac_channel        Dmac channel
+ * @param[in]   buffer              Receive data
+ * @param[in]   BufLen             Data length
+ *
+ */
+void UartReceiveDataDma(UartDeviceNumberT uart_channel, dmac_channel_number_t dmac_channel, uint8_t *buffer, size_t BufLen);
+
+
+/**
+ * @brief       Send data by dma
+ *
+ * @param[in]   uart_channel        Uart index
+ * @param[in]   dmac_channel        Dmac channel
+ * @param[in]   buffer              Send data
+ * @param[in]   BufLen             Data length
+ * @param[in]   uart_callback       Call back
+ * @param[in]   ctx                 Param of call back
+ * @param[in]   priority            Interrupt priority
+ *
+ */
+void UartSendDataDmaIrq(UartDeviceNumberT uart_channel, dmac_channel_number_t dmac_channel,
+                            const uint8_t *buffer, size_t BufLen, plic_irq_callback_t uart_callback,
+                            void *ctx, uint32_t priority);
+
+/**
+ * @brief       Receive data by dma
+ *
+ * @param[in]   uart_channel        Uart index
+ * @param[in]   dmac_channel        Dmac channel
+ * @param[in]   buffer              Receive data
+ * @param[in]   BufLen             Data length
+ * @param[in]   uart_callback       Call back
+ * @param[in]   ctx                 Param of call back
+ * @param[in]   priority            Interrupt priority
+ *
+ */
+void UartReceiveDataDmaIrq(UartDeviceNumberT uart_channel, dmac_channel_number_t dmac_channel,
+                               uint8_t *buffer, size_t BufLen, plic_irq_callback_t uart_callback,
+                               void *ctx, uint32_t priority);
+
+/**
+ * @brief       Uart handle transfer data operations
+ *
+ * @param[in]   uart_channel        Uart index
+ * @param[in]   data                Uart data information
+ * @param[in]   buffer              Uart DMA callback
+ *
+ */
+void uart_handle_data_dma(UartDeviceNumberT uart_channel ,uart_data_t data, plic_interrupt_t *cb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UART_H__ */

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/hardware_uarths.h

@@ -0,0 +1,302 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file
+ * @brief       Universal Asynchronous Receiver/Transmitter (UART)
+ *
+ *              The UART peripheral supports the following features:
+ *
+ *              - 8-N-1 and 8-N-2 formats: 8 data bits, no parity bit, 1 start
+ *                bit, 1 or 2 stop bits
+ *
+ *               - 8-entry transmit and receive FIFO buffers with programmable
+ *                watermark interrupts
+ *
+ *              - 16× Rx oversampling with 2/3 majority voting per bit
+ *
+ *              The UART peripheral does not support hardware flow control or
+ *              other modem control signals, or synchronous serial data
+ *              tranfesrs.
+ *
+ * @note        UART RAM Layout
+ *
+ * | Address   | Name     | Description                     |
+ * |-----------|----------|---------------------------------|
+ * | 0x000     | txdata   | Transmit data register          |
+ * | 0x004     | rxdata   | Receive data register           |
+ * | 0x008     | txctrl   | Transmit control register       |
+ * | 0x00C     | rxctrl   | Receive control register        |
+ * | 0x010     | ie       | UART interrupt enable           |
+ * | 0x014     | ip       | UART Interrupt pending          |
+ * | 0x018     | div      | Baud rate divisor               |
+ *
+ */
+
+/**
+* @file hardware_uarths.h
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef __HARDWARE_UARTHS_H__
+#define __HARDWARE_UARTHS_H__
+
+#include <platform.h>
+#include "plic.h"
+#include <stddef.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* clang-format off */
+/* Register address offsets */
+#define UARTHS_REG_TXFIFO (0x00)
+#define UARTHS_REG_RXFIFO (0x04)
+#define UARTHS_REG_TXCTRL (0x08)
+#define UARTHS_REG_RXCTRL (0x0c)
+#define UARTHS_REG_IE     (0x10)
+#define UARTHS_REG_IP     (0x14)
+#define UARTHS_REG_DIV    (0x18)
+
+/* TXCTRL register */
+#define UARTHS_TXEN       (0x01)
+#define UARTHS_TXWM(x)    (((x) & 0xffff) << 16)
+
+/* RXCTRL register */
+#define UARTHS_RXEN       (0x01)
+#define UARTHS_RXWM(x)    (((x) & 0xffff) << 16)
+
+/* IP register */
+#define UARTHS_IP_TXWM    (0x01)
+#define UARTHS_IP_RXWM    (0x02)
+/* clang-format on */
+
+typedef struct _uarths_txdata
+{
+    /* Bits [7:0] is data */
+    uint32_t data : 8;
+    /* Bits [30:8] is 0 */
+    uint32_t zero : 23;
+    /* Bit 31 is full status */
+    uint32_t full : 1;
+} __attribute__((packed, aligned(4))) uarths_txdata_t;
+
+typedef struct _uarths_rxdata
+{
+    /* Bits [7:0] is data */
+    uint32_t data : 8;
+    /* Bits [30:8] is 0 */
+    uint32_t zero : 23;
+    /* Bit 31 is empty status */
+    uint32_t empty : 1;
+} __attribute__((packed, aligned(4))) uarths_rxdata_t;
+
+typedef struct _uarths_txctrl
+{
+    /* Bit 0 is txen, controls whether the Tx channel is active. */
+    uint32_t txen : 1;
+    /* Bit 1 is nstop, 0 for one stop bit and 1 for two stop bits */
+    uint32_t nstop : 1;
+    /* Bits [15:2] is reserved */
+    uint32_t resv0 : 14;
+    /* Bits [18:16] is threshold of interrupt triggers */
+    uint32_t txcnt : 3;
+    /* Bits [31:19] is reserved */
+    uint32_t resv1 : 13;
+} __attribute__((packed, aligned(4))) uarths_txctrl_t;
+
+typedef struct _uarths_rxctrl
+{
+    /* Bit 0 is txen, controls whether the Tx channel is active. */
+    uint32_t rxen : 1;
+    /* Bits [15:1] is reserved */
+    uint32_t resv0 : 15;
+    /* Bits [18:16] is threshold of interrupt triggers */
+    uint32_t rxcnt : 3;
+    /* Bits [31:19] is reserved */
+    uint32_t resv1 : 13;
+} __attribute__((packed, aligned(4))) uarths_rxctrl_t;
+
+typedef struct _uarths_ip
+{
+    /* Bit 0 is txwm, raised less than txcnt */
+    uint32_t txwm : 1;
+    /* Bit 1 is txwm, raised greater than rxcnt */
+    uint32_t rxwm : 1;
+    /* Bits [31:2] is 0 */
+    uint32_t zero : 30;
+} __attribute__((packed, aligned(4))) uarths_ip_t;
+
+typedef struct _uarths_ie
+{
+    /* Bit 0 is txwm, raised less than txcnt */
+    uint32_t txwm : 1;
+    /* Bit 1 is txwm, raised greater than rxcnt */
+    uint32_t rxwm : 1;
+    /* Bits [31:2] is 0 */
+    uint32_t zero : 30;
+} __attribute__((packed, aligned(4))) uarths_ie_t;
+
+typedef struct _uarths_div
+{
+    /* Bits [31:2] is baud rate divisor register */
+    uint32_t div : 16;
+    /* Bits [31:16] is 0 */
+    uint32_t zero : 16;
+} __attribute__((packed, aligned(4))) uarths_div_t;
+
+typedef struct _uarths
+{
+    /* Address offset 0x00 */
+    uarths_txdata_t txdata;
+    /* Address offset 0x04 */
+    uarths_rxdata_t rxdata;
+    /* Address offset 0x08 */
+    uarths_txctrl_t txctrl;
+    /* Address offset 0x0c */
+    uarths_rxctrl_t rxctrl;
+    /* Address offset 0x10 */
+    uarths_ie_t ie;
+    /* Address offset 0x14 */
+    uarths_ip_t ip;
+    /* Address offset 0x18 */
+    uarths_div_t div;
+} __attribute__((packed, aligned(4))) UarthsT;
+
+typedef enum _uarths_interrupt_mode
+{
+    UARTHS_SEND = 1,
+    UARTHS_RECEIVE = 2,
+    UARTHS_SEND_RECEIVE = 3,
+} uarths_interrupt_mode_t;
+
+typedef enum _uarths_stopbit
+{
+    UARTHS_STOP_1,
+    UARTHS_STOP_2
+} uarths_stopbit_t;
+
+extern volatile UarthsT *const uarths;
+
+/**
+ * @brief       Initialization Core UART
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+void uarths_init(void);
+
+/**
+ * @brief       Put a char to UART
+ *
+ * @param[in]   c       The char to put
+ *
+ * @note        If c is '\n', a '\r' will be appended automatically
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int uarths_putchar(char c);
+
+/**
+ * @brief       Send a string to UART
+ *
+ * @param[in]   s       The string to send
+ *
+ * @note        The string must ending with '\0'
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int uarths_puts(const char *s);
+
+
+/**
+ * @brief       Get a byte from UART
+ *
+ * @return      byte as int type from UART
+ */
+int uarths_getc(void);
+
+/**
+ * @brief       Set uarths interrupt callback
+ *
+ * @param[in]    interrupt_mode       Interrupt mode recevice or send
+ * @param[in]    uarths_callback      Interrupt callback
+ * @param[in]    ctx                  Param of callback
+ * @param[in]    priority             Interrupt priority
+ *
+ */
+void uarths_set_irq(uarths_interrupt_mode_t interrupt_mode, plic_irq_callback_t uarths_callback, void *ctx, uint32_t priority);
+
+/**
+ * @brief       Uarths receive data
+ *
+ * @param[in]    buf          The data received
+ * @param[in]    BufLen      The length of data
+ *
+ * @return      Number of received data
+ */
+size_t uarths_receive_data(uint8_t *buf, size_t BufLen);
+
+/**
+ * @brief       Uarths receive data
+ *
+ * @param[in]    buf          The data sended
+ * @param[in]    BufLen      The length of data
+ *
+ * @return      Number of sended data
+ */
+size_t uarths_send_data(const uint8_t *buf, size_t BufLen);
+
+/**
+ * @brief       Get interrupt mode
+ *
+ * @return      Mode of interrupt
+ */
+uarths_interrupt_mode_t uarths_get_interrupt_mode(void);
+
+/**
+ * @brief       Set uarths baud rate and stopbit
+ *
+ * @param[in]    BaudRate        The baud rate
+ * @param[in]    stopbit          The stopbit of data
+ *
+ */
+void uarths_config(uint32_t BaudRate, uarths_stopbit_t stopbit);
+
+/**
+ * @brief       Set uart interrupt condition
+ *
+ * @param[in]    interrupt_mode         The interrupt mode
+ * @param[in]    cnt                    The count of tigger
+ *
+ */
+void uarths_set_interrupt_cnt(uarths_interrupt_mode_t interrupt_mode, uint8_t cnt);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UARTHS_H__ */

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/io.h

@@ -0,0 +1,60 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file io.h
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef __IO_H__
+#define __IO_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define readb(addr) (*(volatile uint8_t *)(addr))
+#define readw(addr) (*(volatile uint16_t *)(addr))
+#define readl(addr) (*(volatile uint32_t *)(addr))
+#define readq(addr) (*(volatile uint64_t *)(addr))
+
+#define writeb(v, addr)                                                        \
+    {                                                                      \
+        (*(volatile uint8_t *)(addr)) = (v);                           \
+    }
+#define writew(v, addr)                                                        \
+    {                                                                      \
+        (*(volatile uint16_t *)(addr)) = (v);                          \
+    }
+#define writel(v, addr)                                                        \
+    {                                                                      \
+        (*(volatile uint32_t *)(addr)) = (v);                          \
+    }
+#define writeq(v, addr)                                                        \
+    {                                                                      \
+        (*(volatile uint64_t *)(addr)) = (v);                          \
+    }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IO_H__ */

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/plic.h

@@ -0,0 +1,508 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/**
+ * @file
+ * @brief      The PLIC complies with the RISC-V Privileged Architecture
+ *             specification, and can support a maximum of 1023 external
+ *             interrupt sources targeting up to 15,872 core contexts.
+ *
+ * @note       PLIC RAM Layout
+ *
+ * | Address   | Description                     |
+ * |-----------|---------------------------------|
+ * |0x0C000000 | Reserved                        |
+ * |0x0C000004 | source 1 priority               |
+ * |0x0C000008 | source 2 priority               |
+ * |...        | ...                             |
+ * |0x0C000FFC | source 1023 priority            |
+ * |           |                                 |
+ * |0x0C001000 | Start of pending array          |
+ * |...        | (read-only)                     |
+ * |0x0C00107C | End of pending array            |
+ * |0x0C001080 | Reserved                        |
+ * |...        | ...                             |
+ * |0x0C001FFF | Reserved                        |
+ * |           |                                 |
+ * |0x0C002000 | target 0 enables                |
+ * |0x0C002080 | target 1 enables                |
+ * |...        | ...                             |
+ * |0x0C1F1F80 | target 15871 enables            |
+ * |0x0C1F2000 | Reserved                        |
+ * |...        | ...                             |
+ * |0x0C1FFFFC | Reserved                        |
+ * |           |                                 |
+ * |0x0C200000 | target 0 priority threshold     |
+ * |0x0C200004 | target 0 claim/complete         |
+ * |...        | ...                             |
+ * |0x0C201000 | target 1 priority threshold     |
+ * |0x0C201004 | target 1 claim/complete         |
+ * |...        | ...                             |
+ * |0x0FFFF000 | target 15871 priority threshold |
+ * |0x0FFFF004 | target 15871 claim/complete     |
+ *
+ */
+
+/**
+* @file plic.h
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef __PLIC_H__
+#define __PLIC_H__
+
+#include <encoding.h>
+#include <platform.h>
+#include <stdint.h>
+
+/* For c++ compatibility */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* clang-format off */
+/* IRQ number settings */
+#define PLIC_NUM_SOURCES    (IRQN_MAX - 1)
+#define PLIC_NUM_PRIORITIES (7)
+
+/* Real number of cores */
+#define PLIC_NUM_CORES      (2)
+/* clang-format on */
+
+/**
+ * @brief       PLIC External Interrupt Numbers
+ *
+ * @note        PLIC interrupt sources
+ *
+ * | Source | Name                     | Description                        |
+ * |--------|--------------------------|------------------------------------|
+ * | 0      | IRQN_NO_INTERRUPT        | The non-existent interrupt         |
+ * | 1      | IRQN_SPI0_INTERRUPT      | SPI0 interrupt                     |
+ * | 2      | IRQN_SPI1_INTERRUPT      | SPI1 interrupt                     |
+ * | 3      | IRQN_SPI_SLAVE_INTERRUPT | SPI_SLAVE interrupt                |
+ * | 4      | IRQN_SPI3_INTERRUPT      | SPI3 interrupt                     |
+ * | 5      | IRQN_I2S0_INTERRUPT      | I2S0 interrupt                     |
+ * | 6      | IRQN_I2S1_INTERRUPT      | I2S1 interrupt                     |
+ * | 7      | IRQN_I2S2_INTERRUPT      | I2S2 interrupt                     |
+ * | 8      | IRQN_I2C0_INTERRUPT      | I2C0 interrupt                     |
+ * | 9      | IRQN_I2C1_INTERRUPT      | I2C1 interrupt                     |
+ * | 10     | IRQN_I2C2_INTERRUPT      | I2C2 interrupt                     |
+ * | 11     | IRQN_UART1_INTERRUPT     | UART1 interrupt                    |
+ * | 12     | IRQN_UART2_INTERRUPT     | UART2 interrupt                    |
+ * | 13     | IRQN_UART3_INTERRUPT     | UART3 interrupt                    |
+ * | 14     | IRQN_TIMER0A_INTERRUPT   | TIMER0 channel 0 or 1 interrupt    |
+ * | 15     | IRQN_TIMER0B_INTERRUPT   | TIMER0 channel 2 or 3 interrupt    |
+ * | 16     | IRQN_TIMER1A_INTERRUPT   | TIMER1 channel 0 or 1 interrupt    |
+ * | 17     | IRQN_TIMER1B_INTERRUPT   | TIMER1 channel 2 or 3 interrupt    |
+ * | 18     | IRQN_TIMER2A_INTERRUPT   | TIMER2 channel 0 or 1 interrupt    |
+ * | 19     | IRQN_TIMER2B_INTERRUPT   | TIMER2 channel 2 or 3 interrupt    |
+ * | 20     | IRQN_RTC_INTERRUPT       | RTC tick and alarm interrupt       |
+ * | 21     | IRQN_WDT0_INTERRUPT      | Watching dog timer0 interrupt      |
+ * | 22     | IRQN_WDT1_INTERRUPT      | Watching dog timer1 interrupt      |
+ * | 23     | IRQN_APB_GPIO_INTERRUPT  | APB GPIO interrupt                 |
+ * | 24     | IRQN_DVP_INTERRUPT       | Digital video port interrupt       |
+ * | 25     | IRQN_AI_INTERRUPT        | AI accelerator interrupt           |
+ * | 26     | IRQN_FFT_INTERRUPT       | FFT accelerator interrupt          |
+ * | 27     | IRQN_DMA0_INTERRUPT      | DMA channel0 interrupt             |
+ * | 28     | IRQN_DMA1_INTERRUPT      | DMA channel1 interrupt             |
+ * | 29     | IRQN_DMA2_INTERRUPT      | DMA channel2 interrupt             |
+ * | 30     | IRQN_DMA3_INTERRUPT      | DMA channel3 interrupt             |
+ * | 31     | IRQN_DMA4_INTERRUPT      | DMA channel4 interrupt             |
+ * | 32     | IRQN_DMA5_INTERRUPT      | DMA channel5 interrupt             |
+ * | 33     | IRQN_UARTHS_INTERRUPT    | Hi-speed UART0 interrupt           |
+ * | 34     | IRQN_GPIOHS0_INTERRUPT   | Hi-speed GPIO0 interrupt           |
+ * | 35     | IRQN_GPIOHS1_INTERRUPT   | Hi-speed GPIO1 interrupt           |
+ * | 36     | IRQN_GPIOHS2_INTERRUPT   | Hi-speed GPIO2 interrupt           |
+ * | 37     | IRQN_GPIOHS3_INTERRUPT   | Hi-speed GPIO3 interrupt           |
+ * | 38     | IRQN_GPIOHS4_INTERRUPT   | Hi-speed GPIO4 interrupt           |
+ * | 39     | IRQN_GPIOHS5_INTERRUPT   | Hi-speed GPIO5 interrupt           |
+ * | 40     | IRQN_GPIOHS6_INTERRUPT   | Hi-speed GPIO6 interrupt           |
+ * | 41     | IRQN_GPIOHS7_INTERRUPT   | Hi-speed GPIO7 interrupt           |
+ * | 42     | IRQN_GPIOHS8_INTERRUPT   | Hi-speed GPIO8 interrupt           |
+ * | 43     | IRQN_GPIOHS9_INTERRUPT   | Hi-speed GPIO9 interrupt           |
+ * | 44     | IRQN_GPIOHS10_INTERRUPT  | Hi-speed GPIO10 interrupt          |
+ * | 45     | IRQN_GPIOHS11_INTERRUPT  | Hi-speed GPIO11 interrupt          |
+ * | 46     | IRQN_GPIOHS12_INTERRUPT  | Hi-speed GPIO12 interrupt          |
+ * | 47     | IRQN_GPIOHS13_INTERRUPT  | Hi-speed GPIO13 interrupt          |
+ * | 48     | IRQN_GPIOHS14_INTERRUPT  | Hi-speed GPIO14 interrupt          |
+ * | 49     | IRQN_GPIOHS15_INTERRUPT  | Hi-speed GPIO15 interrupt          |
+ * | 50     | IRQN_GPIOHS16_INTERRUPT  | Hi-speed GPIO16 interrupt          |
+ * | 51     | IRQN_GPIOHS17_INTERRUPT  | Hi-speed GPIO17 interrupt          |
+ * | 52     | IRQN_GPIOHS18_INTERRUPT  | Hi-speed GPIO18 interrupt          |
+ * | 53     | IRQN_GPIOHS19_INTERRUPT  | Hi-speed GPIO19 interrupt          |
+ * | 54     | IRQN_GPIOHS20_INTERRUPT  | Hi-speed GPIO20 interrupt          |
+ * | 55     | IRQN_GPIOHS21_INTERRUPT  | Hi-speed GPIO21 interrupt          |
+ * | 56     | IRQN_GPIOHS22_INTERRUPT  | Hi-speed GPIO22 interrupt          |
+ * | 57     | IRQN_GPIOHS23_INTERRUPT  | Hi-speed GPIO23 interrupt          |
+ * | 58     | IRQN_GPIOHS24_INTERRUPT  | Hi-speed GPIO24 interrupt          |
+ * | 59     | IRQN_GPIOHS25_INTERRUPT  | Hi-speed GPIO25 interrupt          |
+ * | 60     | IRQN_GPIOHS26_INTERRUPT  | Hi-speed GPIO26 interrupt          |
+ * | 61     | IRQN_GPIOHS27_INTERRUPT  | Hi-speed GPIO27 interrupt          |
+ * | 62     | IRQN_GPIOHS28_INTERRUPT  | Hi-speed GPIO28 interrupt          |
+ * | 63     | IRQN_GPIOHS29_INTERRUPT  | Hi-speed GPIO29 interrupt          |
+ * | 64     | IRQN_GPIOHS30_INTERRUPT  | Hi-speed GPIO30 interrupt          |
+ * | 65     | IRQN_GPIOHS31_INTERRUPT  | Hi-speed GPIO31 interrupt          |
+ *
+ */
+/* clang-format off */
+typedef enum _plic_irq
+{
+    IRQN_NO_INTERRUPT        = 0, /*!< The non-existent interrupt */
+    IRQN_SPI0_INTERRUPT      = 1, /*!< SPI0 interrupt */
+    IRQN_SPI1_INTERRUPT      = 2, /*!< SPI1 interrupt */
+    IRQN_SPI_SLAVE_INTERRUPT = 3, /*!< SPI_SLAVE interrupt */
+    IRQN_SPI3_INTERRUPT      = 4, /*!< SPI3 interrupt */
+    IRQN_I2S0_INTERRUPT      = 5, /*!< I2S0 interrupt */
+    IRQN_I2S1_INTERRUPT      = 6, /*!< I2S1 interrupt */
+    IRQN_I2S2_INTERRUPT      = 7, /*!< I2S2 interrupt */
+    IRQN_I2C0_INTERRUPT      = 8, /*!< I2C0 interrupt */
+    IRQN_I2C1_INTERRUPT      = 9, /*!< I2C1 interrupt */
+    IRQN_I2C2_INTERRUPT      = 10, /*!< I2C2 interrupt */
+    IRQN_UART1_INTERRUPT     = 11, /*!< UART1 interrupt */
+    IRQN_UART2_INTERRUPT     = 12, /*!< UART2 interrupt */
+    IRQN_UART3_INTERRUPT     = 13, /*!< UART3 interrupt */
+    IRQN_TIMER0A_INTERRUPT   = 14, /*!< TIMER0 channel 0 or 1 interrupt */
+    IRQN_TIMER0B_INTERRUPT   = 15, /*!< TIMER0 channel 2 or 3 interrupt */
+    IRQN_TIMER1A_INTERRUPT   = 16, /*!< TIMER1 channel 0 or 1 interrupt */
+    IRQN_TIMER1B_INTERRUPT   = 17, /*!< TIMER1 channel 2 or 3 interrupt */
+    IRQN_TIMER2A_INTERRUPT   = 18, /*!< TIMER2 channel 0 or 1 interrupt */
+    IRQN_TIMER2B_INTERRUPT   = 19, /*!< TIMER2 channel 2 or 3 interrupt */
+    IRQN_RTC_INTERRUPT       = 20, /*!< RTC tick and alarm interrupt */
+    IRQN_WDT0_INTERRUPT      = 21, /*!< Watching dog timer0 interrupt */
+    IRQN_WDT1_INTERRUPT      = 22, /*!< Watching dog timer1 interrupt */
+    IRQN_APB_GPIO_INTERRUPT  = 23, /*!< APB GPIO interrupt */
+    IRQN_DVP_INTERRUPT       = 24, /*!< Digital video port interrupt */
+    IRQN_AI_INTERRUPT        = 25, /*!< AI accelerator interrupt */
+    IRQN_FFT_INTERRUPT       = 26, /*!< FFT accelerator interrupt */
+    IRQN_DMA0_INTERRUPT      = 27, /*!< DMA channel0 interrupt */
+    IRQN_DMA1_INTERRUPT      = 28, /*!< DMA channel1 interrupt */
+    IRQN_DMA2_INTERRUPT      = 29, /*!< DMA channel2 interrupt */
+    IRQN_DMA3_INTERRUPT      = 30, /*!< DMA channel3 interrupt */
+    IRQN_DMA4_INTERRUPT      = 31, /*!< DMA channel4 interrupt */
+    IRQN_DMA5_INTERRUPT      = 32, /*!< DMA channel5 interrupt */
+    IRQN_UARTHS_INTERRUPT    = 33, /*!< Hi-speed UART0 interrupt */
+    IRQN_GPIOHS0_INTERRUPT   = 34, /*!< Hi-speed GPIO0 interrupt */
+    IRQN_GPIOHS1_INTERRUPT   = 35, /*!< Hi-speed GPIO1 interrupt */
+    IRQN_GPIOHS2_INTERRUPT   = 36, /*!< Hi-speed GPIO2 interrupt */
+    IRQN_GPIOHS3_INTERRUPT   = 37, /*!< Hi-speed GPIO3 interrupt */
+    IRQN_GPIOHS4_INTERRUPT   = 38, /*!< Hi-speed GPIO4 interrupt */
+    IRQN_GPIOHS5_INTERRUPT   = 39, /*!< Hi-speed GPIO5 interrupt */
+    IRQN_GPIOHS6_INTERRUPT   = 40, /*!< Hi-speed GPIO6 interrupt */
+    IRQN_GPIOHS7_INTERRUPT   = 41, /*!< Hi-speed GPIO7 interrupt */
+    IRQN_GPIOHS8_INTERRUPT   = 42, /*!< Hi-speed GPIO8 interrupt */
+    IRQN_GPIOHS9_INTERRUPT   = 43, /*!< Hi-speed GPIO9 interrupt */
+    IRQN_GPIOHS10_INTERRUPT  = 44, /*!< Hi-speed GPIO10 interrupt */
+    IRQN_GPIOHS11_INTERRUPT  = 45, /*!< Hi-speed GPIO11 interrupt */
+    IRQN_GPIOHS12_INTERRUPT  = 46, /*!< Hi-speed GPIO12 interrupt */
+    IRQN_GPIOHS13_INTERRUPT  = 47, /*!< Hi-speed GPIO13 interrupt */
+    IRQN_GPIOHS14_INTERRUPT  = 48, /*!< Hi-speed GPIO14 interrupt */
+    IRQN_GPIOHS15_INTERRUPT  = 49, /*!< Hi-speed GPIO15 interrupt */
+    IRQN_GPIOHS16_INTERRUPT  = 50, /*!< Hi-speed GPIO16 interrupt */
+    IRQN_GPIOHS17_INTERRUPT  = 51, /*!< Hi-speed GPIO17 interrupt */
+    IRQN_GPIOHS18_INTERRUPT  = 52, /*!< Hi-speed GPIO18 interrupt */
+    IRQN_GPIOHS19_INTERRUPT  = 53, /*!< Hi-speed GPIO19 interrupt */
+    IRQN_GPIOHS20_INTERRUPT  = 54, /*!< Hi-speed GPIO20 interrupt */
+    IRQN_GPIOHS21_INTERRUPT  = 55, /*!< Hi-speed GPIO21 interrupt */
+    IRQN_GPIOHS22_INTERRUPT  = 56, /*!< Hi-speed GPIO22 interrupt */
+    IRQN_GPIOHS23_INTERRUPT  = 57, /*!< Hi-speed GPIO23 interrupt */
+    IRQN_GPIOHS24_INTERRUPT  = 58, /*!< Hi-speed GPIO24 interrupt */
+    IRQN_GPIOHS25_INTERRUPT  = 59, /*!< Hi-speed GPIO25 interrupt */
+    IRQN_GPIOHS26_INTERRUPT  = 60, /*!< Hi-speed GPIO26 interrupt */
+    IRQN_GPIOHS27_INTERRUPT  = 61, /*!< Hi-speed GPIO27 interrupt */
+    IRQN_GPIOHS28_INTERRUPT  = 62, /*!< Hi-speed GPIO28 interrupt */
+    IRQN_GPIOHS29_INTERRUPT  = 63, /*!< Hi-speed GPIO29 interrupt */
+    IRQN_GPIOHS30_INTERRUPT  = 64, /*!< Hi-speed GPIO30 interrupt */
+    IRQN_GPIOHS31_INTERRUPT  = 65, /*!< Hi-speed GPIO31 interrupt */
+    IRQN_MAX
+} plic_irq_t;
+/* clang-format on */
+
+/**
+ * @brief      Interrupt Source Priorities
+ *
+ *             Each external interrupt source can be assigned a priority by
+ *             writing to its 32-bit memory-mapped priority register. The
+ *             number and value of supported priority levels can vary by
+ *             implementa- tion, with the simplest implementations having all
+ *             devices hardwired at priority 1, in which case, interrupts with
+ *             the lowest ID have the highest effective priority. The priority
+ *             registers are all WARL.
+ */
+typedef struct _plic_source_priorities
+{
+    /* 0x0C000000: Reserved, 0x0C000004-0x0C000FFC: 1-1023 priorities */
+    uint32_t priority[1024];
+} __attribute__((packed, aligned(4))) plic_source_priorities_t;
+
+/**
+ * @brief       Interrupt Pending Bits
+ *
+ *              The current status of the interrupt source pending bits in the
+ *              PLIC core can be read from the pending array, organized as 32
+ *              words of 32 bits. The pending bit for interrupt ID N is stored
+ *              in bit (N mod 32) of word (N/32). Bit 0 of word 0, which
+ *              represents the non-existent interrupt source 0, is always
+ *              hardwired to zero. The pending bits are read-only. A pending
+ *              bit in the PLIC core can be cleared by setting enable bits to
+ *              only enable the desired interrupt, then performing a claim. A
+ *              pending bit can be set by instructing the associated gateway to
+ *              send an interrupt service request.
+ */
+typedef struct _plic_pending_bits
+{
+    /* 0x0C001000-0x0C00107C: Bit 0 is zero, Bits 1-1023 is pending bits */
+    uint32_t u32[32];
+    /* 0x0C001080-0x0C001FFF: Reserved */
+    uint8_t resv[0xF80];
+} __attribute__((packed, aligned(4))) plic_pending_bits_t;
+
+/**
+ * @brief       Target Interrupt Enables
+ *
+ *              For each interrupt target, each device’s interrupt can be
+ *              enabled by setting the corresponding bit in that target’s
+ *              enables registers. The enables for a target are accessed as a
+ *              contiguous array of 32×32-bit words, packed the same way as the
+ *              pending bits. For each target, bit 0 of enable word 0
+ *              represents the non-existent interrupt ID 0 and is hardwired to
+ *              0. Unused interrupt IDs are also hardwired to zero. The enables
+ *              arrays for different targets are packed contiguously in the
+ *              address space. Only 32-bit word accesses are supported by the
+ *              enables array in RV32 systems. Implementations can trap on
+ *              accesses to enables for non-existent targets, but must allow
+ *              access to the full enables array for any extant target,
+ *              treating all non-existent interrupt source’s enables as
+ *              hardwired to zero.
+ */
+typedef struct _plic_target_enables
+{
+    /* 0x0C002000-0x0C1F1F80: target 0-15871 enables */
+    struct
+    {
+        uint32_t enable[32 * 2];/* Offset 0x00-0x7C: Bit 0 is zero, Bits 1-1023 is bits*/
+    } target[15872 / 2];
+
+    /* 0x0C1F2000-0x0C1FFFFC: Reserved, size 0xE000 */
+    uint8_t resv[0xE000];
+} __attribute__((packed, aligned(4))) plic_target_enables_t;
+
+/**
+ * @brief       PLIC Targets
+ *
+ *              Target Priority Thresholds The threshold for a pending
+ *              interrupt priority that can interrupt each target can be set in
+ *              the target’s threshold register. The threshold is a WARL field,
+ *              where different implementations can support different numbers
+ *              of thresholds. The simplest implementation has a threshold
+ *              hardwired to zero.
+ *
+ *              Target Claim Each target can perform a claim by reading the
+ *              claim/complete register, which returns the ID of the highest
+ *              priority pending interrupt or zero if there is no pending
+ *              interrupt for the target. A successful claim will also
+ *              atomically clear the corresponding pending bit on the interrupt
+ *              source. A target can perform a claim at any time, even if the
+ *              EIP is not set. The claim operation is not affected by the
+ *              setting of the target’s priority threshold register.
+ *
+ *              Target Completion A target signals it has completed running a
+ *              handler by writing the interrupt ID it received from the claim
+ *              to the claim/complete register. This is routed to the
+ *              corresponding interrupt gateway, which can now send another
+ *              interrupt request to the PLIC. The PLIC does not check whether
+ *              the completion ID is the same as the last claim ID for that
+ *              target. If the completion ID does not match an interrupt source
+ *              that is currently enabled for the target, the completion is
+ *              silently ignored.
+ */
+typedef struct _plic_target
+{
+    /* 0x0C200000-0x0FFFF004: target 0-15871 */
+    struct {
+        uint32_t priority_threshold;/* Offset 0x000 */
+        uint32_t claim_complete;    /* Offset 0x004 */
+        uint8_t resv[0x1FF8];        /* Offset 0x008, Size 0xFF8 */
+    } target[15872 / 2];
+} __attribute__((packed, aligned(4))) plic_target_t;
+
+/**
+ * @brief       Platform-Level Interrupt Controller
+ *
+ *              PLIC is Platform-Level Interrupt Controller. The PLIC complies
+ *              with the RISC-V Privileged Architecture specification, and can
+ *              support a maximum of 1023 external interrupt sources targeting
+ *              up to 15,872 core contexts.
+ */
+typedef struct _plic
+{
+    /* 0x0C000000-0x0C000FFC */
+    plic_source_priorities_t source_priorities;
+    /* 0x0C001000-0x0C001FFF */
+    const plic_pending_bits_t pending_bits;
+    /* 0x0C002000-0x0C1FFFFC */
+    plic_target_enables_t target_enables;
+    /* 0x0C200000-0x0FFFF004 */
+    plic_target_t targets;
+} __attribute__((packed, aligned(4))) plic_t;
+
+extern volatile plic_t *const plic;
+
+/**
+ * @brief       Definitions for the interrupt callbacks
+ */
+typedef int (*plic_irq_callback_t)(void *ctx);
+
+/**
+ * @brief       Definitions for IRQ table instance
+ */
+typedef struct _plic_instance_t
+{
+    plic_irq_callback_t callback;
+    void *ctx;
+} plic_instance_t;
+
+typedef struct _plic_callback_t
+{
+    plic_irq_callback_t callback;
+    void *ctx;
+    uint32_t priority;
+} plic_interrupt_t;
+
+/**
+ * @brief       Initialize PLIC external interrupt
+ *
+ * @note        This function will set MIP_MEIP. The MSTATUS_MIE must set by user.
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+void plic_init(void);
+
+/**
+ * @brief       Enable PLIC external interrupt
+ *
+ * @param[in]   irq_number      external interrupt number
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+
+int plic_irq_enable(plic_irq_t irq_number);
+
+/**
+ * @brief       Disable PLIC external interrupt
+ *
+ * @param[in]   irq_number  The external interrupt number
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int plic_irq_disable(plic_irq_t irq_number);
+
+/**
+ * @brief       Set IRQ priority
+ *
+ * @param[in]   irq_number      The external interrupt number
+ * @param[in]   priority        The priority of external interrupt number
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int plic_set_priority(plic_irq_t irq_number, uint32_t priority);
+
+/**
+ * @brief       Get IRQ priority
+ *
+ * @param[in]   irq_number          The external interrupt number
+ *
+ * @return      The priority of external interrupt number
+ */
+uint32_t plic_get_priority(plic_irq_t irq_number);
+
+/**
+ * @brief       Claim an IRQ
+ *
+ * @return      The current IRQ number
+ */
+uint32_t plic_irq_claim(void);
+
+/**
+ * @brief       Complete an IRQ
+ *
+ * @param[in]   source      The source IRQ number to complete
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+int plic_irq_complete(uint32_t source);
+
+/**
+ * @brief       Register user callback function by IRQ number
+ *
+ * @param[in]   irq             The irq
+ * @param[in]   callback        The callback
+ * @param       ctx             The context
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+void plic_irq_register(plic_irq_t irq, plic_irq_callback_t callback, void *ctx);
+
+/**
+ * @brief       Deegister user callback function by IRQ number
+ *
+ * @param[in]   irq     The irq
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+void plic_irq_deregister(plic_irq_t irq);
+
+/**
+ * @brief       Deegister user callback function by IRQ number
+ *
+ * @param[in]   irq     The irq
+ *
+ * @return      result
+ *     - 0      Success
+ *     - Other  Fail
+ */
+void plic_irq_unregister(plic_irq_t irq);
+
+/**
+ * @brief       Get IRQ table, Usage:
+ *              plic_instance_t (*plic_instance)[IRQN_MAX] = plic_get_instance();
+ *              ... plic_instance[x][y] ...;
+ *
+ * @return      the point of IRQ table
+ */
+plic_instance_t (*plic_get_instance(void))[IRQN_MAX];
+
+/* For c++ compatibility */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PLIC_H__ */

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/utils.h

@@ -0,0 +1,357 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file utils.h
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef __UTILS_H__
+#define __UTILS_H__
+
+#ifdef __cplusplus
+#include <cstdbool>
+#include <cstddef>
+#include <cstdint>
+#else /* __cplusplus */
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <stdio.h>
+#endif /* __cplusplus */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define KENDRYTE_MIN(a, b) ((a) > (b) ? (b) : (a))
+#define KENDRYTE_MAX(a, b) ((a) > (b) ? (a) : (b))
+
+#ifdef __ASSEMBLY__
+#define KENDRYTE_CAST(type, ptr) ptr
+#else /* __ASSEMBLY__ */
+/**
+ * @brief       Cast the pointer to specified pointer type.
+ *
+ * @param[in]   type        The pointer type to cast to
+ * @param[in]   ptr         The pointer to apply the type cast to
+ */
+#define KENDRYTE_CAST(type, ptr) ((type)(ptr))
+#endif /* __ASSEMBLY__ */
+
+/**
+ * @addtogroup      UTIL_RW_FUNC Memory Read/Write Utilities
+ *
+ * This section implements read and write functionality for various
+ * memory untis. The memory unit terms used for these functions are
+ * consistent with those used in the ARM Architecture Reference Manual
+ * ARMv7-A and ARMv7-R edition manual. The terms used for units of memory are:
+ *
+ *  Unit of Memory | Abbreviation | Size in Bits
+ * :---------------|:-------------|:------------:
+ *  Byte           | byte         |       8
+ *  Half Word      | hword        |      16
+ *  Word           | word         |      32
+ *  Double Word    | dword        |      64
+ *
+ */
+
+/**
+ * @brief       Write the 8 bit byte to the destination address in device memory.
+ *
+ * @param[in]   dest        Write destination pointer address
+ * @param[in]   src         8 bit data byte to write to memory
+ */
+#define kendryte_write_byte(dest, src) \
+    (*KENDRYTE_CAST(volatile uint8_t*, (dest)) = (src))
+
+/**
+ * @brief       Read and return the 8 bit byte from the source address in device memory.
+ *
+ * @param[in]   src     Read source pointer address
+ *
+ * @return      8 bit data byte value
+ */
+#define kendryte_read_byte(src) (*KENDRYTE_CAST(volatile uint8_t*, (src)))
+
+/**
+ * @brief       Write the 16 bit half word to the destination address in device memory.
+ *
+ * @param[in]   dest        Write destination pointer address
+ * @param[in]   src         16 bit data half word to write to memory
+ */
+#define kendryte_write_hword(dest, src) \
+    (*KENDRYTE_CAST(volatile uint16_t*, (dest)) = (src))
+
+/**
+ * @brief       Read and return the 16 bit half word from the source address in device
+ *
+ * @param[in]   src     Read source pointer address
+ *
+ * @return      16 bit data half word value
+ */
+#define kendryte_read_hword(src) (*KENDRYTE_CAST(volatile uint16_t*, (src)))
+
+/**
+ * @brief       Write the 32 bit word to the destination address in device memory.
+ *
+ * @param[in]   dest        Write destination pointer address
+ * @param[in]   src         32 bit data word to write to memory
+ */
+#define kendryte_write_word(dest, src) \
+    (*KENDRYTE_CAST(volatile uint32_t*, (dest)) = (src))
+
+/**
+ * @brief       Read and return the 32 bit word from the source address in device memory.
+ *
+ * @param[in]   src     Read source pointer address
+ *
+ * @return      32 bit data half word value
+ */
+#define kendryte_read_word(src) (*KENDRYTE_CAST(volatile uint32_t*, (src)))
+
+/**
+ * @brief       Write the 64 bit double word to the destination address in device memory.
+ *
+ * @param[in]   dest        Write destination pointer address
+ * @param[in]   src         64 bit data word to write to memory
+ */
+#define kendryte_write_dword(dest, src) \
+    (*KENDRYTE_CAST(volatile uint64_t*, (dest)) = (src))
+
+/**
+ * @brief       Read and return the 64 bit double word from the source address in device
+ *
+ * @param[in]   src     Read source pointer address
+ *
+ * @return      64 bit data half word value
+ */
+#define kendryte_read_dword(src) (*KENDRYTE_CAST(volatile uint64_t*, (src)))
+
+/**
+ * @brief       Set selected bits in the 8 bit byte at the destination address in device
+ *
+ * @param[in]   dest        Destination pointer address
+ * @param[in]   bits        Bits to set in destination byte
+ */
+#define kendryte_setbits_byte(dest, bits) \
+    (kendryte_write_byte(dest, kendryte_read_byte(dest) | (bits)))
+
+/**
+ * @brief       Clear selected bits in the 8 bit byte at the destination address in device
+ *
+ * @param[in]   dest        Destination pointer address
+ * @param[in]   bits        Bits to clear in destination byte
+ */
+#define kendryte_clrbits_byte(dest, bits) \
+    (kendryte_write_byte(dest, kendryte_read_byte(dest) & ~(bits)))
+
+/**
+ * @brief       Change or toggle selected bits in the 8 bit byte at the destination address
+ *
+ * @param[in]   dest        Destination pointer address
+ * @param[in]   bits        Bits to change in destination byte
+ */
+#define kendryte_xorbits_byte(dest, bits) \
+    (kendryte_write_byte(dest, kendryte_read_byte(dest) ^ (bits)))
+
+/**
+ * @brief       Replace selected bits in the 8 bit byte at the destination address in device
+ *
+ * @param[in]   dest        Destination pointer address
+ * @param[in]   msk         Bits to replace in destination byte
+ * @param[in]   src         Source bits to write to cleared bits in destination byte
+ */
+#define kendryte_replbits_byte(dest, msk, src) \
+    (kendryte_write_byte(dest, (kendryte_read_byte(dest) & ~(msk)) | ((src) & (msk))))
+
+/**
+ * @brief       Set selected bits in the 16 bit halfword at the destination address in
+ *
+ * @param[in]   dest        Destination pointer address
+ * @param[in]   bits        Bits to set in destination halfword
+ */
+#define kendryte_setbits_hword(dest, bits) \
+    (kendryte_write_hword(dest, kendryte_read_hword(dest) | (bits)))
+
+/**
+ * @brief       Clear selected bits in the 16 bit halfword at the destination address in
+ *
+ * @param[in]   dest        Destination pointer address
+ * @param[in]   bits        Bits to clear in destination halfword
+ */
+#define kendryte_clrbits_hword(dest, bits) \
+    (kendryte_write_hword(dest, kendryte_read_hword(dest) & ~(bits)))
+
+/**
+ * @brief       Change or toggle selected bits in the 16 bit halfword at the destination
+ *
+ * @param[in]   dest        Destination pointer address
+ * @param[in]   bits        Bits to change in destination halfword
+ */
+#define kendryte_xorbits_hword(dest, bits) \
+    (kendryte_write_hword(dest, kendryte_read_hword(dest) ^ (bits)))
+
+/**
+ * @brief       Replace selected bits in the 16 bit halfword at the destination address in
+ *
+ * @param[in]   dest        Destination pointer address
+ * @param[in]   msk         Bits to replace in destination byte
+ * @param[in]   src         Source bits to write to cleared bits in destination halfword
+ */
+#define kendryte_replbits_hword(dest, msk, src) \
+    (kendryte_write_hword(dest, (kendryte_read_hword(dest) & ~(msk)) | ((src) & (msk))))
+
+/**
+ * @brief       Set selected bits in the 32 bit word at the destination address in device
+ *
+ * @param[in]   dest        Destination pointer address
+ * @param[in]   bits        Bits to set in destination word
+ */
+#define kendryte_setbits_word(dest, bits) \
+    (kendryte_write_word(dest, kendryte_read_word(dest) | (bits)))
+
+/**
+ * @brief       Clear selected bits in the 32 bit word at the destination address in device
+ *
+ * @param[in]   dest        Destination pointer address
+ * @param[in]   bits        Bits to clear in destination word
+ */
+#define kendryte_clrbits_word(dest, bits) \
+    (kendryte_write_word(dest, kendryte_read_word(dest) & ~(bits)))
+
+/**
+ * @brief       Change or toggle selected bits in the 32 bit word at the destination address
+ *
+ * @param[in]   dest        Destination pointer address
+ * @param[in]   bits        Bits to change in destination word
+ */
+#define kendryte_xorbits_word(dest, bits) \
+    (kendryte_write_word(dest, kendryte_read_word(dest) ^ (bits)))
+
+/**
+ * @brief       Replace selected bits in the 32 bit word at the destination address in
+ *
+ * @param[in]   dest        Destination pointer address
+ * @param[in]   msk         Bits to replace in destination word
+ * @param[in]   src         Source bits to write to cleared bits in destination word
+ */
+#define kendryte_replbits_word(dest, msk, src) \
+    (kendryte_write_word(dest, (kendryte_read_word(dest) & ~(msk)) | ((src) & (msk))))
+
+/**
+ * @brief      Set selected bits in the 64 bit doubleword at the destination address in
+ *
+ * @param[in]   dest     Destination pointer address
+ * @param[in]   bits     Bits to set in destination doubleword
+ */
+#define kendryte_setbits_dword(dest, bits) \
+    (kendryte_write_dword(dest, kendryte_read_dword(dest) | (bits)))
+
+/**
+ * @brief       Clear selected bits in the 64 bit doubleword at the destination address in
+ *
+ * @param[in]   dest        Destination pointer address
+ * @param[in]   bits        Bits to clear in destination doubleword
+ */
+#define kendryte_clrbits_dword(dest, bits) \
+    (kendryte_write_dword(dest, kendryte_read_dword(dest) & ~(bits)))
+
+/**
+ * @brief       Change or toggle selected bits in the 64 bit doubleword at the destination
+ *
+ * @param[in]   dest        Destination pointer address
+ * @param[in]   bits        Bits to change in destination doubleword
+ */
+#define kendryte_xorbits_dword(dest, bits) \
+    (kendryte_write_dword(dest, kendryte_read_dword(dest) ^ (bits)))
+
+/**
+ * @brief       Replace selected bits in the 64 bit doubleword at the destination address in
+ *
+ * @param[in]   dest        Destination pointer address
+ * @param[in]   msk         its to replace in destination doubleword
+ * @param[in]   src         Source bits to write to cleared bits in destination word
+ */
+#define kendryte_replbits_dword(dest, msk, src) \
+    (kendryte_write_dword(dest, (kendryte_read_dword(dest) & ~(msk)) | ((src) & (msk))))
+
+#define configASSERT(x)                                 \
+    if ((x) == 0)                                       \
+    {                                                   \
+        printf("(%s:%d) %s\r\n", __FILE__, __LINE__, #x); \
+        for (;;)                                        \
+            ;                                           \
+    }
+
+/**
+ * @brief       Set value by mask
+ *
+ * @param[in]   bits        The one be set
+ * @param[in]   mask        mask value
+ * @param[in]   value       The value to set
+ */
+void set_bit(volatile uint32_t *bits, uint32_t mask, uint32_t value);
+
+/**
+ * @brief       Set value by mask
+ *
+ * @param[in]   bits        The one be set
+ * @param[in]   mask        Mask value
+ * @param[in]   offset      Mask's offset
+ * @param[in]   value       The value to set
+ */
+void set_bit_offset(volatile uint32_t *bits, uint32_t mask, size_t offset, uint32_t value);
+
+/**
+ * @brief       Set bit for gpio, only set one bit
+ *
+ * @param[in]   bits        The one be set
+ * @param[in]   idx         Offset value
+ * @param[in]   value       The value to set
+ */
+void set_gpio_bit(volatile uint32_t *bits, size_t idx, uint32_t value);
+
+/**
+ * @brief      Get bits value of mask
+ *
+ * @param[in]   bits        The source data
+ * @param[in]   mask        Mask value
+ * @param[in]   offset      Mask's offset
+ *
+ * @return      The bits value of mask
+ */
+uint32_t get_bit(volatile uint32_t *bits, uint32_t mask, size_t offset);
+
+/**
+ * @brief       Get a bit value by offset
+ *
+ * @param[in]   bits        The source data
+ * @param[in]   offset      Bit's offset
+ *
+ *
+ * @return      The bit value
+ */
+uint32_t get_gpio_bit(volatile uint32_t *bits, size_t offset);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _DRIVER_COMMON_H */
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/include/wdt.h

@@ -0,0 +1,180 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file wdt.h
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#ifndef __WDT_H__
+#define __WDT_H__
+
+#include <stdint.h>
+#include <stddef.h>
+#include <plic.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* clang-format off */
+typedef struct _wdt
+{
+    /* WDT Control Register                     (0x00) */
+    volatile uint32_t cr;
+    /* WDT Timeout Range Register               (0x04) */
+    volatile uint32_t torr;
+    /* WDT Current Counter Value Register       (0x08) */
+    volatile uint32_t ccvr;
+    /* WDT Counter Restart Register             (0x0c) */
+    volatile uint32_t crr;
+    /* WDT Interrupt Status Register            (0x10) */
+    volatile uint32_t stat;
+    /* WDT Interrupt Clear Register             (0x14) */
+    volatile uint32_t eoi;
+    /* reserverd                                (0x18) */
+    volatile uint32_t resv1;
+    /* WDT Protection level Register            (0x1c) */
+    volatile uint32_t prot_level;
+    /* reserved                                 (0x20-0xe0) */
+    volatile uint32_t resv4[49];
+    /* WDT Component Parameters Register 5      (0xe4) */
+    volatile uint32_t comp_param_5;
+    /* WDT Component Parameters Register 4      (0xe8) */
+    volatile uint32_t comp_param_4;
+    /* WDT Component Parameters Register 3      (0xec) */
+    volatile uint32_t comp_param_3;
+    /* WDT Component Parameters Register 2      (0xf0) */
+    volatile uint32_t comp_param_2;
+    /* WDT Component Parameters Register 1      (0xf4) */
+    volatile uint32_t comp_param_1;
+    /* WDT Component Version Register           (0xf8) */
+    volatile uint32_t comp_version;
+    /* WDT Component Type Register              (0xfc) */
+    volatile uint32_t comp_type;
+} __attribute__((packed, aligned(4))) wdt_t;
+
+typedef enum _wdt_device_number
+{
+    WDT_DEVICE_0,
+    WDT_DEVICE_1,
+    WDT_DEVICE_MAX,
+} wdt_device_number_t;
+
+
+#define WDT_RESET_ALL                                       0x00000000U
+#define WDT_RESET_CPU                                       0x00000001U
+
+/* WDT Control Register */
+#define WDT_CR_ENABLE                                       0x00000001U
+#define WDT_CR_RMOD_MASK                                    0x00000002U
+#define WDT_CR_RMOD_RESET                                   0x00000000U
+#define WDT_CR_RMOD_INTERRUPT                               0x00000002U
+#define WDT_CR_RPL_MASK                                     0x0000001CU
+#define WDT_CR_RPL(x)                                       ((x) << 2)
+/* WDT Timeout Range Register */
+#define WDT_TORR_TOP_MASK                                   0x000000FFU
+#define WDT_TORR_TOP(x)                                     ((x) << 4 | (x) << 0)
+/* WDT Current Counter Value Register */
+#define WDT_CCVR_MASK                                       0xFFFFFFFFU
+/* WDT Counter Restart Register */
+#define WDT_CRR_MASK                                        0x00000076U
+/* WDT Interrupt Status Register */
+#define WDT_STAT_MASK                                       0x00000001U
+/* WDT Interrupt Clear Register */
+#define WDT_EOI_MASK                                        0x00000001U
+/* WDT Protection level Register */
+#define WDT_PROT_LEVEL_MASK                                 0x00000007U
+/* WDT Component Parameter Register 5 */
+#define WDT_COMP_PARAM_5_CP_WDT_USER_TOP_MAX_MASK           0xFFFFFFFFU
+/* WDT Component Parameter Register 4 */
+#define WDT_COMP_PARAM_4_CP_WDT_USER_TOP_INIT_MAX_MASK      0xFFFFFFFFU
+/* WDT Component Parameter Register 3 */
+#define WDT_COMP_PARAM_3_CD_WDT_TOP_RST_MASK                0xFFFFFFFFU
+/* WDT Component Parameter Register 2 */
+#define WDT_COMP_PARAM_3_CP_WDT_CNT_RST_MASK                0xFFFFFFFFU
+/* WDT Component Parameter Register 1 */
+#define WDT_COMP_PARAM_1_WDT_ALWAYS_EN_MASK                 0x00000001U
+#define WDT_COMP_PARAM_1_WDT_DFLT_RMOD_MASK                 0x00000002U
+#define WDT_COMP_PARAM_1_WDT_DUAL_TOP_MASK                  0x00000004U
+#define WDT_COMP_PARAM_1_WDT_HC_RMOD_MASK                   0x00000008U
+#define WDT_COMP_PARAM_1_WDT_HC_RPL_MASK                    0x00000010U
+#define WDT_COMP_PARAM_1_WDT_HC_TOP_MASK                    0x00000020U
+#define WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_MASK               0x00000040U
+#define WDT_COMP_PARAM_1_WDT_PAUSE_MASK                     0x00000080U
+#define WDT_COMP_PARAM_1_APB_DATA_WIDTH_MASK                0x00000300U
+#define WDT_COMP_PARAM_1_WDT_DFLT_RPL_MASK                  0x00001C00U
+#define WDT_COMP_PARAM_1_WDT_DFLT_TOP_MASK                  0x000F0000U
+#define WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT_MASK             0x00F00000U
+#define WDT_COMP_PARAM_1_WDT_CNT_WIDTH_MASK                 0x1F000000U
+/* WDT Component Version Register */
+#define WDT_COMP_VERSION_MASK                               0xFFFFFFFFU
+/* WDT Component Type Register */
+#define WDT_COMP_TYPE_MASK                                  0xFFFFFFFFU
+/* clang-format on */
+
+/**
+ * @brief       Feed wdt
+ */
+void wdt_feed(wdt_device_number_t id);
+
+/**
+ * @brief       Start wdt
+ *
+ * @param[in]   id                  Wdt id 0 or 1
+ * @param[in]   time_out_ms         Wdt trigger time
+ * @param[in]   on_irq              Wdt interrupt callback
+ *
+ */
+void wdt_start(wdt_device_number_t id, uint64_t time_out_ms, plic_irq_callback_t on_irq);
+
+/**
+ * @brief       Start wdt
+ *
+ * @param[in]   id                 Wdt id 0 or 1
+ * @param[in]   time_out_ms        Wdt trigger time
+ * @param[in]   on_irq             Wdt interrupt callback
+ * @param[in]   ctx                Param of callback
+ *
+ * @return      Wdt time
+ *
+ */
+uint32_t wdt_init(wdt_device_number_t id, uint64_t time_out_ms, plic_irq_callback_t on_irq, void *ctx);
+
+/**
+ * @brief       Stop wdt
+ *
+ * @param[in]   id      Wdt id 0 or 1
+ *
+ */
+void wdt_stop(wdt_device_number_t id);
+
+/**
+ * @brief       Clear wdt interrupt
+ *
+ * @param[in]   id      Wdt id 0 or 1
+ *
+ */
+void wdt_clear_interrupt(wdt_device_number_t id);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __WDT_H__ */

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/lcd/Kconfig

@@ -0,0 +1,36 @@
+
+if BSP_USING_LCD
+    config LCD_BUS_NAME
+        string "lcd bus name"
+        default "lcd"
+    config LCD_DRV_NAME
+        string "lcd bus driver name"
+        default "lcd_drv"
+    config LCD_DEVICE_NAME
+            string "lcd bus device name"
+            default "lcd_dev"   
+    config BSP_LCD_CS_PIN
+        int "CS pin number of 8080 interface"
+        default 40
+    config BSP_LCD_WR_PIN
+        int "WR pin number of 8080 interface"
+        default 38
+    config BSP_LCD_DC_PIN
+        int "DC pin number of 8080 interface"
+        default 41
+    config FPIOA_LCD_DC
+        int "DC FPIOA number of 8080 interface"
+        default 2
+    config BSP_LCD_BL_PIN
+        int "BL pin number of 8080 interface"
+        default 47
+    config FPIOA_LCD_BL
+        int "BL FPIOA number of 8080 interface"
+        default 10
+    config BSP_LCD_X_MAX
+        int "LCD Height"
+        default 240
+    config BSP_LCD_Y_MAX
+        int "LCD Width"
+        default 320
+endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/lcd/Makefile

@@ -0,0 +1,4 @@
+SRC_FILES := connect_lcd.c
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/lcd/connect_lcd.c

@@ -0,0 +1,710 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file connect_lcd.c
+* @brief support aiit-riscv64-board lcd function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: connect_lcd.c
+Description: support aiit-riscv64-board lcd configure and lcd bus register function
+Others: https://canaan-creative.com/developer
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support aiit-riscv64-board lcd configure, write and read
+2. support aiit-riscv64-board lcd bus device and driver register
+*************************************************/
+
+#include <connect_lcd.h>
+#include <board.h>
+#include <drv_io_config.h>
+#include <font.h>
+#include <fpioa.h>
+#include <gpiohs.h>
+#include <graphic.h>
+
+#define NO_OPERATION                      0x00
+#define SOFTWARE_RESET                0x01
+#define READ_ID                                     0x04
+#define READ_STATUS                         0x09
+#define READ_POWER_MODE           0x0A
+#define READ_MADCTL                        0x0B
+#define READ_PIXEL_FORMAT          0x0C
+#define READ_IMAGE_FORMAT         0x0D
+#define READ_SIGNAL_MODE           0x0E
+#define READ_SELT_DIAG_RESULT 0x0F
+#define SLEEP_ON                                 0x10
+#define SLEEP_OFF                               0x11
+#define PARTIAL_DISPALY_ON          0x12
+#define NORMAL_DISPALY_ON          0x13
+#define INVERSION_DISPALY_OFF   0x20
+#define INVERSION_DISPALY_ON     0x21
+#define GAMMA_SET                              0x26
+#define DISPALY_OFF                             0x28
+#define DISPALY_ON                              0x29
+#define HORIZONTAL_ADDRESS_SET          0x2A
+#define VERTICAL_ADDRESS_SET                  0x2B
+#define MEMORY_WRITE                                    0x2C
+#define COLOR_SET                                              0x2D
+#define MEMORY_READ                                       0x2E
+#define PARTIAL_AREA                                        0x30
+#define VERTICAL_SCROL_DEFINE                 0x33
+#define TEAR_EFFECT_LINE_OFF                   0x34
+#define TEAR_EFFECT_LINE_ON                     0x35
+#define MEMORY_ACCESS_CTL                        0x36
+#define VERTICAL_SCROL_S_ADD                  0x37
+#define IDLE_MODE_OFF                                    0x38
+#define IDLE_MODE_ON                                      0x39
+#define PIXEL_FORMAT_SET                             0x3A
+#define WRITE_MEMORY_CONTINUE            0x3C
+#define READ_MEMORY_CONTINUE              0x3E
+#define SET_TEAR_SCANLINE                          0x44
+#define GET_SCANLINE                                       0x45
+#define WRITE_BRIGHTNESS                            0x51
+#define READ_BRIGHTNESS                              0x52
+#define WRITE_CTRL_DISPALY                         0x53
+#define READ_CTRL_DISPALY                           0x54
+#define WRITE_BRIGHTNESS_CTL                  0x55
+#define READ_BRIGHTNESS_CTL                    0x56
+#define WRITE_MIN_BRIGHTNESS                  0x5E
+#define READ_MIN_BRIGHTNESS                    0x5F
+#define READ_ID1                                                   0xDA
+#define READ_ID2                                                   0xDB
+#define READ_ID3                                                   0xDC
+#define RGB_IF_SIGNAL_CTL                            0xB0
+#define NORMAL_FRAME_CTL                           0xB1
+#define IDLE_FRAME_CTL                                   0xB2
+#define PARTIAL_FRAME_CTL                           0xB3
+#define INVERSION_CTL                                      0xB4
+#define BLANK_PORCH_CTL                              0xB5
+#define DISPALY_FUNCTION_CTL                    0xB6
+#define ENTRY_MODE_SET                                 0xB7
+#define BACKLIGHT_CTL1                                   0xB8
+#define BACKLIGHT_CTL2                                   0xB9
+#define BACKLIGHT_CTL3                                   0xBA
+#define BACKLIGHT_CTL4                                   0xBB
+#define BACKLIGHT_CTL5                                   0xBC
+#define BACKLIGHT_CTL7                                   0xBE
+#define BACKLIGHT_CTL8                                   0xBF
+#define POWER_CTL1                                            0xC0
+#define POWER_CTL2                                            0xC1
+#define VCOM_CTL1                                                0xC5
+#define VCOM_CTL2                                                0xC7
+#define NV_MEMORY_WRITE                              0xD0
+#define NV_MEMORY_PROTECT_KEY             0xD1
+#define NV_MEMORY_STATUS_READ             0xD2
+#define READ_ID4                                                    0xD3
+#define POSITIVE_GAMMA_CORRECT             0xE0
+#define NEGATIVE_GAMMA_CORRECT            0xE1
+#define DIGITAL_GAMMA_CTL1                         0xE2
+#define DIGITAL_GAMMA_CTL2                         0xE3
+#define INTERFACE_CTL                                       0xF6
+
+typedef enum _lcd_dir
+{
+    DIR_XY_RLUD = 0x00,
+    DIR_YX_RLUD = 0x20,
+    DIR_XY_LRUD = 0x40,
+    DIR_YX_LRUD = 0x60,
+    DIR_XY_RLDU = 0x80,
+    DIR_YX_RLDU = 0xA0,
+    DIR_XY_LRDU = 0xC0,
+    DIR_YX_LRDU = 0xE0,
+    DIR_XY_MASK = 0x20,
+    DIR_MASK = 0xE0,
+} lcd_dir_t;
+
+#define LCD_SPI_CHANNEL                 SPI_DEVICE_0
+#define LCD_SPI_CHIP_SELECT         SPI_CHIP_SELECT_0
+
+typedef struct Lcd8080Device
+{
+    struct LcdBus lcd_bus;
+    struct DeviceLcdInfo lcd_info;
+    int spi_channel;
+    int cs;
+    int dc_pin;
+    int dma_channel;
+} * Lcd8080DeviceType;
+
+Lcd8080DeviceType aiit_lcd ;
+
+static void DrvLcdCmd(uint8 cmd)
+{
+    gpiohs_set_pin(aiit_lcd->dc_pin, GPIO_PV_LOW);
+    spi_init(aiit_lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
+    spi_init_non_standard(aiit_lcd->spi_channel/*spi num*/, 8 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
+                          SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
+    spi_send_data_normal_dma(aiit_lcd->dma_channel, aiit_lcd->spi_channel, aiit_lcd->cs, &cmd, 1, SPI_TRANS_CHAR);
+}
+
+static void DrvLcdDataByte(uint8 *data_buf, uint32 length)
+{
+    gpiohs_set_pin(aiit_lcd->dc_pin, GPIO_PV_HIGH);
+    spi_init(aiit_lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
+    spi_init_non_standard(aiit_lcd->spi_channel, 8 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
+                          SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
+    spi_send_data_normal_dma(aiit_lcd->dma_channel, aiit_lcd->spi_channel, aiit_lcd->cs, data_buf, length, SPI_TRANS_CHAR);
+}
+
+static void DrvLcdDataHalfWord(uint16 *data_buf, uint32 length)
+{
+    gpiohs_set_pin(aiit_lcd->dc_pin, GPIO_PV_HIGH);
+    spi_init(aiit_lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 16, 0);
+    spi_init_non_standard(aiit_lcd->spi_channel, 16 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
+                          SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
+    spi_send_data_normal_dma(aiit_lcd->dma_channel, aiit_lcd->spi_channel, aiit_lcd->cs, data_buf, length, SPI_TRANS_SHORT);
+}
+
+static void DrvLcdDataWord(uint32 *data_buf, uint32 length)
+{
+    gpiohs_set_pin(aiit_lcd->dc_pin, GPIO_PV_HIGH);
+ /*spi  num      Polarity and phase mode   Multi-line mode    Data bit width    little endian  */
+    spi_init(aiit_lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0);
+
+/*  spi num      instrction length    address length     wait cycles    spi address trans mode*/
+    spi_init_non_standard(aiit_lcd->spi_channel, 0 , 32, 0 ,SPI_AITM_AS_FRAME_FORMAT );
+
+    /*dma  channel     spi num   chip_selete   tx_buff   tx_len    spi_trans_data_width */
+    spi_send_data_normal_dma(aiit_lcd->dma_channel, aiit_lcd->spi_channel, aiit_lcd->cs, data_buf, length, SPI_TRANS_INT);
+}
+
+static void DrvLcdHwInit(Lcd8080DeviceType lcd)
+{
+    gpiohs_set_drive_mode(lcd->dc_pin, GPIO_DM_OUTPUT);
+    gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
+    spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
+    spi_set_clk_rate(lcd->spi_channel, 25000000);
+}
+
+static void DrvLcdSetDirection(lcd_dir_t dir)
+{
+#if !BOARD_LICHEEDAN
+    dir |= 0x08;
+#endif
+    if (dir & DIR_XY_MASK) {
+        aiit_lcd->lcd_info.width = 320;
+        aiit_lcd->lcd_info.height = 240;
+    } else {
+        aiit_lcd->lcd_info.width = 240;
+        aiit_lcd->lcd_info.height = 320;
+    }
+
+    DrvLcdCmd(MEMORY_ACCESS_CTL);
+    DrvLcdDataByte((uint8 *)&dir, 1);
+}
+
+static void DrvLcdSetArea(uint16 x1, uint16 y1, uint16 x2, uint16 y2)
+{
+    uint8 data[4] = {0};
+
+    data[0] = (uint8)(x1 >> 8);
+    data[1] = (uint8)(x1);
+    data[2] = (uint8)(x2 >> 8);
+    data[3] = (uint8)(x2);
+    DrvLcdCmd(HORIZONTAL_ADDRESS_SET);
+    DrvLcdDataByte(data, 4);
+
+    data[0] = (uint8)(y1 >> 8);
+    data[1] = (uint8)(y1);
+    data[2] = (uint8)(y2 >> 8);
+    data[3] = (uint8)(y2);
+    DrvLcdCmd(VERTICAL_ADDRESS_SET);
+    DrvLcdDataByte(data, 4);
+
+    DrvLcdCmd(MEMORY_WRITE);
+}
+
+static void DrvLcdSetPixel(uint16_t x, uint16_t y, uint16_t color)
+{
+    DrvLcdSetArea(x, y, x, y);
+    DrvLcdDataHalfWord(&color, 1);
+}
+
+static void DrvLcdSetPixelDot(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2,void* color)
+{
+    uint32 size = 0;
+    size = (x2- x1 + 1)*(y2 - y1 + 1);
+    DrvLcdSetArea(x1, y1, x2, y2);
+    DrvLcdDataHalfWord(color, size);
+}
+
+void LcdShowChar(uint16 x,uint16 y,uint8 num,uint8 size,uint16 color,uint16 back_color)
+{  							  
+    uint8 temp,t1,t;
+	uint16 y0=y;
+	uint8 csize=(size/8+((size%8)?1:0))*(size/2);	
+ 	num=num-' ';
+	for (t = 0;t < csize;t ++) {   
+		if (size==12)
+            temp=asc2_1206[num][t]; 	 	     //1206
+		else if (size==16)
+            temp=asc2_1608[num][t];	//1608
+		else if (size==24)
+            temp=asc2_2412[num][t];	//2412
+		else if (size==32)
+            temp=asc2_3216[num][t];	//3216
+		else
+            return;				
+
+		for(t1 = 0;t1 < 8;t1 ++) {			    
+			if (temp&0x80)
+                DrvLcdSetPixel(x,y,color);
+            else
+                DrvLcdSetPixel(x,y,back_color);
+
+			temp<<=1;
+			y++;
+			if(y>=aiit_lcd->lcd_info.height)
+                return;	
+			if ((y-y0) == size) {
+				y=y0;
+				x++;
+				if(x>=aiit_lcd->lcd_info.width)
+                    return;	
+				break;
+			}
+		}  	 
+	}  	    	   	 	  
+}   
+
+void LcdShowString(uint16_t x,uint16_t y,uint16_t width,uint16_t height,uint8 size,uint8 *p,uint16_t color,uint16_t back_color)
+{         
+	uint16_t x0 = x;
+	width += x;
+	height += y;
+    while ((*p<='~')&&(*p>=' ')) {       
+        if (x>=width) {
+            x=x0;
+            y+=size;
+        }
+        if(y>=height)
+            break;
+        LcdShowChar(x,y,*p,size,color,back_color);
+        x += size/2;
+        p++;
+    }  
+}
+
+/*
+*   clear lcd by  color
+*   para     color
+*   return  none
+*/
+void DrvLcdClear(uint16 color)
+{
+    uint32 data = ((uint32)color << 16) | (uint32)color;
+
+    DrvLcdSetArea(0, 0, aiit_lcd->lcd_info.width - 1, aiit_lcd->lcd_info.height - 1);
+    gpiohs_set_pin(aiit_lcd->dc_pin, GPIO_PV_HIGH);
+    spi_init(aiit_lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0);
+    spi_init_non_standard(aiit_lcd->spi_channel,
+                                                          0                         /*instrction length*/, 
+                                                          32                       /*address length   */, 
+                                                          0                         /*wait cycles            */,
+                                                         SPI_AITM_AS_FRAME_FORMAT );
+    spi_fill_data_dma(aiit_lcd->dma_channel, aiit_lcd->spi_channel, aiit_lcd->cs, (const uint32_t *)&data, aiit_lcd->lcd_info.width * aiit_lcd->lcd_info.height / 2);
+}
+
+static void DrvLcdRectUpdate(uint16_t x1, uint16_t y1, uint16_t width, uint16_t height)
+{
+    static uint16 * rect_buffer = NONE;
+    if (!rect_buffer) {
+        rect_buffer = x_malloc(aiit_lcd->lcd_info.height * aiit_lcd->lcd_info.width * (aiit_lcd->lcd_info.bits_per_pixel / 8));
+        if (!rect_buffer) {
+            return;
+        }
+    }
+    if (x1 == 0 && y1 == 0 && width == aiit_lcd->lcd_info.width && height == aiit_lcd->lcd_info.height) {
+        DrvLcdSetArea(x1, y1, x1 + width - 1, y1 + height - 1);
+        DrvLcdDataWord((uint32 *)aiit_lcd->lcd_info.framebuffer, width * height / (aiit_lcd->lcd_info.bits_per_pixel / 8));
+    } else {
+        DrvLcdSetArea(x1, y1, x1 + width - 1, y1 + height - 1);
+        DrvLcdDataWord((uint32 *)rect_buffer, width * height / 2);
+    }
+}
+
+x_err_t DrvLcdInit(Lcd8080DeviceType dev)
+{
+    x_err_t ret = EOK;
+    aiit_lcd = (Lcd8080DeviceType)dev;
+    uint8 data = 0;
+
+    if (!aiit_lcd)
+    {
+        return -ERROR;
+    }
+    DrvLcdHwInit(aiit_lcd);
+    /* reset LCD */
+    DrvLcdCmd(SOFTWARE_RESET);
+    MdelayKTask(100);
+
+    /* Enter normal status */
+    DrvLcdCmd(SLEEP_OFF);
+    MdelayKTask(100);
+
+    /* pixel format rgb565 */
+    DrvLcdCmd(PIXEL_FORMAT_SET);
+    data = 0x55;
+    DrvLcdDataByte(&data, 1);
+
+    /* set direction */
+    DrvLcdSetDirection(DIR_YX_RLUD);
+
+    aiit_lcd->lcd_info.framebuffer = x_malloc(aiit_lcd->lcd_info.height * aiit_lcd->lcd_info.width * (aiit_lcd->lcd_info.bits_per_pixel / 8));
+    CHECK(aiit_lcd->lcd_info.framebuffer);
+
+    /*display on*/
+    DrvLcdCmd(DISPALY_ON);
+
+    return ret;
+}
+
+static uint32 drv_lcd_control(void* drv, struct BusConfigureInfo *configure_info)
+{
+    x_err_t ret = EOK;
+    struct LcdDriver *lcddrv = (struct LcdDriver *)drv;
+
+    struct DeviceRectInfo* rect_info;
+    NULL_PARAM_CHECK(drv);
+
+    switch (configure_info->configure_cmd)
+    {
+        case GRAPHIC_CTRL_RECT_UPDATE: 
+            rect_info = (struct DeviceRectInfo*)configure_info->private_data;
+            if(!rect_info)
+            {
+                SYS_ERR("GRAPHIC_CTRL_RECT_UPDATE error args");
+                return -ERROR;
+            }
+            DrvLcdRectUpdate(rect_info->x, rect_info->y, rect_info->width, rect_info->height);
+            break;
+
+        case GRAPHIC_CTRL_POWERON:
+            /* Todo: power on */
+            ret = -ENONESYS;
+            break;
+
+        case GRAPHIC_CTRL_POWEROFF:
+            /* Todo: power off */
+            ret = -ENONESYS;
+            break;
+
+        case GRAPHIC_CTRL_GET_INFO:
+            *(struct DeviceLcdInfo *)configure_info->private_data = aiit_lcd->lcd_info;
+            break;
+
+        case GRAPHIC_CTRL_SET_MODE:
+            ret = -ENONESYS;
+            break;
+        case GRAPHIC_CTRL_GET_EXT:
+            ret = -ENONESYS;
+            break;
+        default:
+            SYS_ERR("drv_lcd_control cmd: %d", configure_info->configure_cmd);
+            break;
+    }
+
+    return ret;
+}
+
+void ClearHandwriting (void)
+{
+    //clear  the lcd    
+    DrvLcdClear(WHITE);
+       
+    LcdShowString(10, 10, 100, 24, 24, "RST ", RED, WHITE);
+}
+
+#ifdef CONFIG_TOUCH
+void HandTest(unsigned short *x_pos, unsigned short *y_pos)
+{
+    float x1,y1;
+    TpReadXy(x_pos,y_pos);     //address
+    float  a = 12.1875,b = 16.25;
+    x1 = 320 -  (*x_pos)/a +10;
+    y1 = (* y_pos)/b;
+
+    if ((*x_pos> 500)&&(*y_pos<500)) {
+        ClearHandwriting();
+    } else {
+        DrvLcdSetPixel(x1,  y1,  RED);
+        DrvLcdSetPixel(x1+1,  y1,  RED);
+        DrvLcdSetPixel(x1-1,  y1,  RED);
+
+        DrvLcdSetPixel(x1,  y1+1,  RED);
+        DrvLcdSetPixel(x1,  y1-1,  RED);
+       
+       DrvLcdSetPixel(x1+1,  y1+1,  RED);
+       DrvLcdSetPixel(x1-1,  y1-1,  RED);
+
+       DrvLcdSetPixel(x1+1,  y1-1,  RED);
+       DrvLcdSetPixel(x1-1,  y1+1,  RED);
+    }
+}
+#endif
+
+static uint32 LcdWrite(void *dev, struct BusBlockWriteParam *write_param)
+{
+    if (write_param  == NONE) {
+         return  -ERROR;
+     }
+    LcdWriteParam * show = (LcdWriteParam *)write_param->buffer;
+    // KPrintf("DEBUG TYPE %d X1:%d X2:%d Y1:%d Y2:%d\n",show->type,show->pixel_info.x_startpos, show->pixel_info.x_endpos,show->pixel_info.y_startpos, show->pixel_info.y_endpos);
+    if(0 == show->type) //output string
+    {
+        LcdShowString(show->string_info.x_pos,show->string_info.y_pos,show->string_info.width,show->string_info.height,show->string_info.font_size,show->string_info.addr,show->string_info.font_color,show->string_info.back_color);
+        return  EOK;   
+    } 
+    else if(1 == show->type)   //output dot
+    {
+        // DrvLcdSetPixel(show->pixel_info.x_pos, show->pixel_info.y_pos, show->pixel_info.pixel_color);
+        DrvLcdSetPixelDot(show->pixel_info.x_startpos,show->pixel_info.y_startpos, show->pixel_info.x_endpos, show->pixel_info.y_endpos,show->pixel_info.pixel_color);
+        return  EOK;
+    } 
+    else 
+    {
+        return -ERROR;
+    }
+    // if (0==write_param->pos) {         //output string
+    //     LcdShowString(show->x_pos,show->y_pos,show->width,show->height,show->font_size,show->addr,show->font_color,show->back_color);
+    //     return  EOK;   
+    // } else if (1==write_param->pos) {  //output dot
+    //     DrvLcdSetPixel(show->x_pos, show->y_pos, show->font_color);
+    //     return  EOK;
+    // } else {
+    //     return -ERROR;
+    // }
+}
+
+uint32 DrvLcdClearDone(void * dev, struct BusConfigureInfo *configure_info)
+{
+    uint16 color =   0;
+    color =(uint16)(configure_info->configure_cmd |0x0000ffff );
+    DrvLcdClear( color);
+    return 0;
+}
+
+const struct LcdDevDone lcd_dev_done  = 
+{
+    .open = NONE,
+    .close = NONE,
+    .write = LcdWrite,
+    .read  = NONE
+};
+
+static int BoardLcdBusInit(struct LcdBus * lcd_bus, struct LcdDriver * lcd_driver,const char *bus_name, const char *drv_name)
+{
+    x_err_t ret = EOK;
+
+    /*Init the lcd bus */
+    ret = LcdBusInit( lcd_bus, bus_name);
+    if (EOK != ret) {
+        KPrintf("Board_lcd_init LcdBusInit error %d\n", ret);
+        return -ERROR;
+    }
+
+    /*Init the lcd driver*/
+    ret = LcdDriverInit( lcd_driver, drv_name);
+    if (EOK != ret) {
+        KPrintf("Board_LCD_init LcdDriverInit error %d\n", ret);
+        return -ERROR;
+    }
+
+    /*Attach the lcd driver to the lcd bus*/
+    ret = LcdDriverAttachToBus(drv_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("Board_LCD_init LcdDriverAttachToBus error %d\n", ret);
+        return -ERROR;
+    } 
+
+    return ret;
+}
+
+/*Attach the lcd device to the lcd bus*/
+static int BoardLcdDevBend(struct LcdHardwareDevice *lcd_device, void *param, const char *bus_name, const char *dev_name)
+{
+    x_err_t ret = EOK;
+
+    ret = LcdDeviceRegister(lcd_device, NONE, dev_name);
+    if (EOK != ret) {
+        KPrintf("Board_LCD_init LcdDeviceInit device %s error %d\n", dev_name, ret);
+        return -ERROR;
+    }  
+
+    ret = LcdDeviceAttachToBus(dev_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("Board_LCD_init LcdDeviceAttachToBus device %s error %d\n", dev_name, ret);
+        return -ERROR;
+    }  
+
+    return  ret;
+}
+
+int HwLcdInit(void)
+{
+    x_err_t ret = EOK;
+
+    static struct LcdDriver lcd_driver;
+    memset(&lcd_driver, 0, sizeof(struct LcdDriver));
+
+    Lcd8080DeviceType  lcd_dev = (Lcd8080DeviceType  )x_malloc(sizeof(  struct Lcd8080Device));
+    if (!lcd_dev) 
+    {
+        return -ERROR;
+    }
+
+    memset(lcd_dev, 0, sizeof(struct Lcd8080Device));
+
+    FpioaSetFunction(BSP_LCD_DC_PIN, FUNC_GPIOHS9);    //DC order/data
+    FpioaSetFunction(BSP_LCD_BL_PIN, FUNC_GPIOHS10);   //BL
+    FpioaSetFunction(BSP_LCD_CS_PIN, FUNC_SPI0_SS0);   //chip  select
+    FpioaSetFunction(BSP_LCD_WR_PIN, FUNC_SPI0_SCLK);  //clk
+
+    lcd_dev->cs                       = SPI_CHIP_SELECT_0;
+    lcd_dev->dc_pin                   =  9;  
+    lcd_dev->dma_channel              = DMAC_CHANNEL0;
+    lcd_dev->spi_channel              = SPI_DEVICE_0;
+    lcd_dev->lcd_info.bits_per_pixel  = 16;
+    lcd_dev->lcd_info.pixel_format    = PIXEL_FORMAT_BGR565;
+
+    sysctl_set_power_mode(SYSCTL_POWER_BANK6, SYSCTL_POWER_V18);
+    sysctl_set_power_mode(SYSCTL_POWER_BANK7, SYSCTL_POWER_V18);
+
+    sysctl_set_spi0_dvp_data(1); //open  the lcd  interface  with spi0
+
+    lcd_driver.configure = &drv_lcd_control;
+
+    ret = BoardLcdBusInit(&lcd_dev->lcd_bus, &lcd_driver, LCD_BUS_NAME, LCD_DRV_NAME);  //init  lcd bus
+    if (EOK != ret)
+    {
+        KPrintf("Board_lcd_Init error ret %u\n", ret);
+        x_free(lcd_dev);
+        return -ERROR;
+    }
+
+    static struct LcdHardwareDevice lcd_device;      
+    memset(&lcd_device, 0, sizeof(struct LcdHardwareDevice));
+
+    lcd_device.dev_done = &(lcd_dev_done);
+
+    ret = BoardLcdDevBend(&lcd_device, NONE, LCD_BUS_NAME, LCD_DEVICE_NAME);                             //init  lcd device
+    if (EOK != ret)
+    {
+        KPrintf("BoardLcdDevBend error ret %u\n", ret);
+        x_free(lcd_dev);
+        return -ERROR;
+    }
+
+    gpiohs_set_drive_mode(10, GPIO_DM_OUTPUT);
+    gpiohs_set_pin(10, GPIO_PV_HIGH);   
+
+    KPrintf("LCD driver inited ...\r\n");
+
+    DrvLcdInit(lcd_dev);
+
+    return ret;
+}
+
+//x1,y1:start
+//x2,y2:end  
+void LcdDrawLine(uint16 x1, uint16 y1, uint16 x2, uint16 y2,uint16 color)
+{
+	uint16 t; 
+	int xerr = 0, yerr = 0, delta_x, delta_y, distance; 
+	int incx,incy,uRow,uCol; 
+	delta_x = x2 - x1;  
+	delta_y = y2 - y1; 
+	uRow = x1; 
+	uCol = y1; 
+
+	if(delta_x>0)
+        incx = 1; 
+	else if(delta_x==0)
+        incx = 0;
+	else {
+        incx = -1;
+        delta_x = -delta_x;
+    } 
+
+	if(delta_y>0)
+        incy = 1; 
+	else if(delta_y==0)
+        incy = 0;
+	else {
+        incy= -1;
+        delta_y = -delta_y;
+    } 
+
+	if (delta_x>delta_y)
+        distance=delta_x; 
+	else 
+        distance=delta_y; 
+
+	for(t = 0;t <= distance+1;t ++ ) {  
+        DrvLcdSetPixel(uRow,uCol,color);
+		xerr += delta_x ; 
+		yerr += delta_y ; 
+		if (xerr>distance) { 
+			xerr-=distance; 
+			uRow+=incx; 
+		} 
+		if (yerr>distance) { 
+			yerr-=distance; 
+			uCol+=incy; 
+		} 
+	}  
+}    
+
+void LcdDrawRectangle(uint16 x1, uint16 y1, uint16 x2, uint16 y2,uint16 color)
+{
+	LcdDrawLine(x1,y1,x2,y1,color);
+	LcdDrawLine(x1,y1,x1,y2,color);
+	LcdDrawLine(x1,y2,x2,y2,color);
+	LcdDrawLine(x2,y1,x2,y2,color);
+}
+
+void LcdDrawCircle(uint16 x0,uint16 y0,uint8 r,uint16 color)
+{
+	int a,b;
+	int di;
+	a = 0;
+    b = r;	  
+	di = 3-(r<<1);            
+	while(a <= b) {
+		DrvLcdSetPixel(x0+a,y0-b,color);             //5
+ 		DrvLcdSetPixel(x0+b,y0-a,color);             //0           
+		DrvLcdSetPixel(x0+b,y0+a,color);             //4               
+		DrvLcdSetPixel(x0+a,y0+b,color);             //6 
+		DrvLcdSetPixel(x0-a,y0+b,color);             //1       
+ 		DrvLcdSetPixel(x0-b,y0+a,color);             
+		DrvLcdSetPixel(x0-a,y0-b,color);             //2             
+  		DrvLcdSetPixel(x0-b,y0-a,color);             //7     	         
+		a++;
+		//Bresenham     
+		if(di<0)
+            di += 4*a+6;	  
+		else {
+			di += 10+4*(a-b);   
+			b--;
+		} 						    
+	}
+}								  

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/plic/Kconfig

@@ -0,0 +1 @@
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/plic/Makefile

@@ -0,0 +1,5 @@
+SRC_FILES := drv_interrupt.c plic.c clint.c
+
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/plic/clint.c

@@ -0,0 +1,229 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file clint.c
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#include <clint.h>
+#include <encoding.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <sysctl.h>
+
+volatile clint_t* const clint = (volatile clint_t*)CLINT_BASE_ADDR;
+static clint_timer_instance_t clint_timer_instance[CLINT_NUM_CORES];
+static clint_ipi_instance_t clint_ipi_instance[CLINT_NUM_CORES];
+
+uint64_t clint_get_time(void)
+{
+    /* No difference on cores */
+    return clint->mtime;
+}
+
+int clint_timer_init(void)
+{
+    /* Read core id */
+    unsigned long core_id = current_coreid();
+    /* Clear the Machine-Timer bit in MIE */
+    CLEAR_CSR(mie, MIP_MTIP);
+    /* Fill core's instance with original data */
+
+    /* clang-format off */
+    clint_timer_instance[core_id] = (const clint_timer_instance_t)
+    {
+        .interval    = 0,
+        .cycles      = 0,
+        .single_shot = 0,
+        .callback    = NULL,
+        .ctx         = NULL,
+    };
+    /* clang-format on */
+
+    return 0;
+}
+
+int clint_timer_stop(void)
+{
+    /* Clear the Machine-Timer bit in MIE */
+    CLEAR_CSR(mie, MIP_MTIP);
+    return 0;
+}
+
+uint64_t clint_timer_get_freq(void)
+{
+    /* The clock is divided by CLINT_CLOCK_DIV */
+    return SysctlClockGetFreq(SYSCTL_CLOCK_CPU) / CLINT_CLOCK_DIV;
+}
+
+int clint_timer_start(uint64_t interval, int single_shot)
+{
+    /* Read core id */
+    unsigned long core_id = current_coreid();
+    /* Set timer interval */
+    if (clint_timer_set_interval(interval) != 0)
+        return -1;
+    /* Set timer single shot */
+    if (clint_timer_set_single_shot(single_shot) != 0)
+        return -1;
+    /* Check settings to prevent interval is 0 */
+    if (clint_timer_instance[core_id].interval == 0)
+        return -1;
+    /* Check settings to prevent cycles is 0 */
+    if (clint_timer_instance[core_id].cycles == 0)
+        return -1;
+    /* Add cycle interval to mtimecmp */
+    uint64_t now = clint->mtime;
+    uint64_t then = now + clint_timer_instance[core_id].cycles;
+    /* Set mtimecmp by core id */
+    clint->mtimecmp[core_id] = then;
+    /* Enable interrupts in general */
+    SET_CSR(mstatus, MSTATUS_MIE);
+    /* Enable the Machine-Timer bit in MIE */
+    SET_CSR(mie, MIP_MTIP);
+    return 0;
+}
+
+uint64_t clint_timer_get_interval(void)
+{
+    /* Read core id */
+    unsigned long core_id = current_coreid();
+    return clint_timer_instance[core_id].interval;
+}
+
+int clint_timer_set_interval(uint64_t interval)
+{
+    /* Read core id */
+    unsigned long core_id = current_coreid();
+    /* Check parameter */
+    if (interval == 0)
+        return -1;
+
+    /* Assign user interval with Millisecond(ms) */
+    clint_timer_instance[core_id].interval = interval;
+    /* Convert interval to cycles */
+    clint_timer_instance[core_id].cycles = interval * clint_timer_get_freq() / 1000ULL;
+    return 0;
+}
+
+int clint_timer_get_single_shot(void)
+{
+    /* Read core id */
+    unsigned long core_id = current_coreid();
+    /* Get single shot mode by core id */
+    return clint_timer_instance[core_id].single_shot;
+}
+
+int clint_timer_set_single_shot(int single_shot)
+{
+    /* Read core id */
+    unsigned long core_id = current_coreid();
+    /* Set single shot mode by core id */
+    clint_timer_instance[core_id].single_shot = single_shot;
+    return 0;
+}
+
+int clint_timer_register(clint_timer_callback_t callback, void *ctx)
+{
+    /* Read core id */
+    unsigned long core_id = current_coreid();
+    /* Set user callback function */
+    clint_timer_instance[core_id].callback = callback;
+    /* Assign user context */
+    clint_timer_instance[core_id].ctx = ctx;
+    return 0;
+}
+
+int clint_timer_unregister(void)
+{
+    /* Just assign NULL to user callback function and context */
+    return clint_timer_register(NULL, NULL);
+}
+
+int clint_ipi_init(void)
+{
+    /* Read core id */
+    unsigned long core_id = current_coreid();
+    /* Clear the Machine-Software bit in MIE */
+    CLEAR_CSR(mie, MIP_MSIP);
+    /* Fill core's instance with original data */
+    /* clang-format off */
+    clint_ipi_instance[core_id] = (const clint_ipi_instance_t){
+        .callback    = NULL,
+        .ctx         = NULL,
+    };
+    /* clang-format on */
+
+    return 0;
+}
+
+int clint_ipi_enable(void)
+{
+    /* Enable interrupts in general */
+    SET_CSR(mstatus, MSTATUS_MIE);
+    /* Set the Machine-Software bit in MIE */
+    SET_CSR(mie, MIP_MSIP);
+    return 0;
+}
+
+int clint_ipi_disable(void)
+{
+    /* Clear the Machine-Software bit in MIE */
+    CLEAR_CSR(mie, MIP_MSIP);
+    return 0;
+}
+
+int clint_ipi_send(size_t core_id)
+{
+    if (core_id >= CLINT_NUM_CORES)
+        return -1;
+    clint->msip[core_id].msip = 1;
+    return 0;
+}
+
+int clint_ipi_clear(size_t core_id)
+{
+    if (core_id >= CLINT_NUM_CORES)
+        return -1;
+    if (clint->msip[core_id].msip)
+    {
+        clint->msip[core_id].msip = 0;
+        return 1;
+    }
+    return 0;
+}
+
+int clint_ipi_register(clint_ipi_callback_t callback, void *ctx)
+{
+    /* Read core id */
+    unsigned long core_id = current_coreid();
+    /* Set user callback function */
+    clint_ipi_instance[core_id].callback = callback;
+    /* Assign user context */
+    clint_ipi_instance[core_id].ctx = ctx;
+    return 0;
+}
+
+int clint_ipi_unregister(void)
+{
+    /* Just assign NULL to user callback function and context */
+    return clint_ipi_register(NULL, NULL);
+}
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/plic/drv_interrupt.c

@@ -0,0 +1,41 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file drv_interrupt.c
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#include <plic.h>
+
+void PlicIrqHandle(plic_irq_t irq)
+{
+    plic_instance_t (*plic_instance)[IRQN_MAX] = plic_get_instance();
+    if (plic_instance[0][irq].callback)
+    {
+        plic_instance[0][irq].callback(
+            plic_instance[0][irq].ctx);
+    }
+    else if (plic_instance[1][irq].callback)
+    {
+        plic_instance[1][irq].callback(
+            plic_instance[1][irq].ctx);
+    }
+}
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/plic/plic.c

@@ -0,0 +1,219 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file plic.c
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#include <encoding.h>
+#include <plic.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <syscalls.h>
+#include <syslog.h>
+
+volatile plic_t* const plic = (volatile plic_t*)PLIC_BASE_ADDR;
+
+static plic_instance_t plic_instance[PLIC_NUM_CORES][IRQN_MAX];
+
+void plic_init(void)
+{
+    int i = 0;
+
+    /* Get current core id */
+    unsigned long core_id = current_coreid();
+
+    /* Disable all interrupts for the current core. */
+    for (i = 0; i < ((PLIC_NUM_SOURCES + 32u) / 32u); i++)
+        plic->target_enables.target[core_id].enable[i] = 0;
+
+    static uint8_t s_plic_priorities_init_flag = 0;
+    /* Set priorities to zero. */
+    if(s_plic_priorities_init_flag == 0)
+    {
+        for (i = 0; i < PLIC_NUM_SOURCES; i++)
+            plic->source_priorities.priority[i] = 0;
+        s_plic_priorities_init_flag = 1;
+    }
+
+    /* Set the threshold to zero. */
+    plic->targets.target[core_id].priority_threshold = 0;
+
+    /* Clear PLIC instance for every cores */
+    for (i = 0; i < IRQN_MAX; i++)
+    {
+        /* clang-format off */
+        plic_instance[core_id][i] = (const plic_instance_t){
+            .callback = NULL,
+            .ctx      = NULL,
+        };
+        /* clang-format on */
+    }
+
+    /*
+     * A successful claim will also atomically clear the corresponding
+     * pending bit on the interrupt source. A target can perform a claim
+     * at any time, even if the EIP is not set.
+     */
+    i = 0;
+    while (plic->targets.target[core_id].claim_complete > 0 && i < 100)
+    {
+        /* This loop will clear pending bit on the interrupt source */
+        i++;
+    }
+
+    /* Enable machine external interrupts. */
+    SET_CSR(mie, MIP_MEIP);
+}
+
+int plic_irq_enable(plic_irq_t irq_number)
+{
+    /* Check parameters */
+    if (PLIC_NUM_SOURCES < irq_number || 0 > irq_number)
+        return -1;
+    unsigned long core_id = current_coreid();
+    /* Get current enable bit array by IRQ number */
+    uint32_t current = plic->target_enables.target[core_id].enable[irq_number / 32];
+    /* Set enable bit in enable bit array */
+    current |= (uint32_t)1 << (irq_number % 32);
+    /* Write back the enable bit array */
+    plic->target_enables.target[core_id].enable[irq_number / 32] = current;
+    return 0;
+}
+
+int plic_irq_disable(plic_irq_t irq_number)
+{
+    /* Check parameters */
+    if (PLIC_NUM_SOURCES < irq_number || 0 > irq_number)
+        return -1;
+    unsigned long core_id = current_coreid();
+    /* Get current enable bit array by IRQ number */
+    uint32_t current = plic->target_enables.target[core_id].enable[irq_number / 32];
+    /* Clear enable bit in enable bit array */
+    current &= ~((uint32_t)1 << (irq_number % 32));
+    /* Write back the enable bit array */
+    plic->target_enables.target[core_id].enable[irq_number / 32] = current;
+    return 0;
+}
+
+int plic_set_priority(plic_irq_t irq_number, uint32_t priority)
+{
+    /* Check parameters */
+    if (PLIC_NUM_SOURCES < irq_number || 0 > irq_number)
+        return -1;
+    /* Set interrupt priority by IRQ number */
+    plic->source_priorities.priority[irq_number] = priority;
+    return 0;
+}
+
+uint32_t plic_get_priority(plic_irq_t irq_number)
+{
+    /* Check parameters */
+    if (PLIC_NUM_SOURCES < irq_number || 0 > irq_number)
+        return 0;
+    /* Get interrupt priority by IRQ number */
+    return plic->source_priorities.priority[irq_number];
+}
+
+uint32_t plic_irq_claim(void)
+{
+    unsigned long core_id = current_coreid();
+    /* Perform IRQ claim */
+    return plic->targets.target[core_id].claim_complete;
+}
+
+int plic_irq_complete(uint32_t source)
+{
+    unsigned long core_id = current_coreid();
+    /* Perform IRQ complete */
+    plic->targets.target[core_id].claim_complete = source;
+    return 0;
+}
+
+void plic_irq_register(plic_irq_t irq, plic_irq_callback_t callback, void *ctx)
+{
+    /* Read core id */
+    unsigned long core_id = current_coreid();
+    /* Set user callback function */
+    plic_instance[core_id][irq].callback = callback;
+    /* Assign user context */
+    plic_instance[core_id][irq].ctx = ctx;
+}
+
+void plic_irq_unregister(plic_irq_t irq)
+{
+    /* Just assign NULL to user callback function and context */
+    plic_irq_register(irq, NULL, NULL);
+}
+
+void __attribute__((weak, alias("plic_irq_unregister"))) plic_irq_deregister(plic_irq_t irq);
+
+plic_instance_t (*plic_get_instance(void))[IRQN_MAX]
+{
+    return plic_instance;
+}
+
+/*Entry Point for PLIC Interrupt Handler*/
+uintptr_t __attribute__((weak))
+HandleIrqMExt(uintptr_t cause, uintptr_t epc)
+{
+    /*
+     * After the highest-priority pending interrupt is claimed by a target
+     * and the corresponding IP bit is cleared, other lower-priority
+     * pending interrupts might then become visible to the target, and so
+     * the PLIC EIP bit might not be cleared after a claim. The interrupt
+     * handler can check the local meip/heip/seip/ueip bits before exiting
+     * the handler, to allow more efficient service of other interrupts
+     * without first restoring the interrupted context and taking another
+     * interrupt trap.
+     */
+    if (READ_CSR(mip) & MIP_MEIP)
+    {
+        /* Get current core id */
+        uint64_t core_id = current_coreid();
+        /* Get primitive interrupt enable flag */
+        uint64_t ie_flag = READ_CSR(mie);
+        /* Get current IRQ num */
+        uint32_t int_num = plic->targets.target[core_id].claim_complete;
+        /* Get primitive IRQ threshold */
+        uint32_t int_threshold = plic->targets.target[core_id].priority_threshold;
+        /* Set new IRQ threshold = current IRQ threshold */
+        plic->targets.target[core_id].priority_threshold = plic->source_priorities.priority[int_num];
+        /* Disable software interrupt and timer interrupt */
+        CLEAR_CSR(mie, MIP_MTIP | MIP_MSIP);
+        /* Enable global interrupt */
+        SET_CSR(mstatus, MSTATUS_MIE);
+        if (plic_instance[core_id][int_num].callback)
+            plic_instance[core_id][int_num].callback(
+                plic_instance[core_id][int_num].ctx);
+        /* Perform IRQ complete */
+        plic->targets.target[core_id].claim_complete = int_num;
+        /* Disable global interrupt */
+        CLEAR_CSR(mstatus, MSTATUS_MIE);
+        /* Set MPIE and MPP flag used to MRET instructions restore MIE flag */
+        SET_CSR(mstatus, MSTATUS_MPIE | MSTATUS_MPP);
+        /* Restore primitive interrupt enable flag */
+        WRITE_CSR(mie, ie_flag);
+        /* Restore primitive IRQ threshold */
+        plic->targets.target[core_id].priority_threshold = int_threshold;
+    }
+
+    return epc;
+}

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/rtc/Kconfig

@@ -0,0 +1,11 @@
+if BSP_USING_RTC
+    config RTC_BUS_NAME
+        string "rtc bus name"
+        default "rtc"
+    config RTC_DRV_NAME
+        string "rtc bus driver name"
+        default "rtc_drv"
+    config RTC_DEVICE_NAME
+            string "rtc bus device name"
+            default "rtc_dev"     
+endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/rtc/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := connect_rtc.c hardware_rtc.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/rtc/connect_rtc.c

@@ -0,0 +1,183 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_rtc.c
+* @brief support aiit-riscv64-board rtc function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#include <connect_rtc.h>
+#include <hardware_rtc.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <sysctl.h>
+#include <time.h>
+
+static int GetWeekDay(int year, int month, int day)
+{
+    /* Magic method to get weekday */
+    int weekday  = (day += month < 3 ? year-- : year - 2, 
+        23 * month / 9 + day + 4 + year / 4 - year / 100 + year / 400) % 7;
+    return weekday;
+}
+
+static uint32 RtcConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+
+    struct RtcDriver *rtc_drv = (struct RtcDriver *)drv;
+    struct RtcDrvConfigureParam *drv_param = (struct RtcDrvConfigureParam *)configure_info->private_data;
+
+    int cmd = drv_param->rtc_operation_cmd;
+    time_t *time = drv_param->time;
+
+    switch (cmd)
+    {
+        case OPER_RTC_GET_TIME:
+        {
+            struct tm ct;
+            int year,month,day,hour,minute,second;
+            memset(&ct,0,sizeof(struct tm));
+
+            rtc_timer_get(&year, &month, &day, &hour, &minute, &second);
+
+            ct.tm_year = year - 1900;
+            ct.tm_mon = month - 1;
+            ct.tm_mday = day;
+            ct.tm_wday = GetWeekDay(year, month, day);
+
+            ct.tm_hour = hour;
+            ct.tm_min = minute;
+            ct.tm_sec = second;
+
+            *time = mktime(&ct);
+        }
+        break;
+        case OPER_RTC_SET_TIME:
+        {
+            struct tm *ct;
+            struct tm tm_new;
+            x_base lock;
+
+            lock = CriticalAreaLock();
+            ct = localtime(time);
+            memcpy(&tm_new, ct, sizeof(struct tm));
+            CriticalAreaUnLock(lock);
+
+            sysctl_reset(SYSCTL_RESET_RTC);
+            sysctl_clock_enable(SYSCTL_CLOCK_RTC);
+            rtc_protect_set(0);
+            rtc_timer_set_clock_frequency(SysctlClockGetFreq(SYSCTL_CLOCK_IN0));
+            rtc_timer_set_clock_count_value(1);
+            rtc_timer_set_mode(RTC_TIMER_RUNNING);
+
+            if (rtc_timer_set(tm_new.tm_year+1900,tm_new.tm_mon+1,tm_new.tm_mday,
+                            tm_new.tm_hour,tm_new.tm_min,tm_new.tm_sec)==-1)
+                return ERROR;
+        }
+        break;
+    }
+    return EOK;
+}
+
+/*manage the rtc device operations*/
+static const struct RtcDevDone dev_done =
+{
+    .open = NONE,
+    .close = NONE,
+    .write = NONE,
+    .read = NONE,
+};
+
+static int BoardRtcBusInit(struct RtcBus *rtc_bus, struct RtcDriver *rtc_driver)
+{
+    x_err_t ret = EOK;
+
+    /*Init the rtc bus */
+    ret = RtcBusInit(rtc_bus, RTC_BUS_NAME);
+    if (EOK != ret) {
+        KPrintf("HwRtcInit RtcBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Init the rtc driver*/
+    ret = RtcDriverInit(rtc_driver, RTC_DRV_NAME);
+    if (EOK != ret) {
+        KPrintf("HwRtcInit RtcDriverInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Attach the rtc driver to the rtc bus*/
+    ret = RtcDriverAttachToBus(RTC_DRV_NAME, RTC_BUS_NAME);
+    if (EOK != ret) {
+        KPrintf("HwRtcInit RtcDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    } 
+
+    return ret;
+}
+
+/*Attach the rtc device to the rtc bus*/
+static int BoardRtcDevBend(void)
+{
+    x_err_t ret = EOK;
+
+    static struct RtcHardwareDevice rtc_device;
+    memset(&rtc_device, 0, sizeof(struct RtcHardwareDevice));
+
+    rtc_device.dev_done = &(dev_done);
+
+    ret = RtcDeviceRegister(&rtc_device, NONE, RTC_DEVICE_NAME);
+    if (EOK != ret) {
+        KPrintf("HwRtcInit RtcDeviceInit device %s error %d\n", RTC_DEVICE_NAME, ret);
+        return ERROR;
+    }  
+
+    ret = RtcDeviceAttachToBus(RTC_DEVICE_NAME, RTC_BUS_NAME);
+    if (EOK != ret) {
+        KPrintf("HwRtcInit RtcDeviceAttachToBus device %s error %d\n", RTC_DEVICE_NAME, ret);
+        return ERROR;
+    }  
+
+    return  ret;
+}
+
+int HwRtcInit(void)
+{
+    x_err_t ret = EOK;
+
+    static struct RtcBus rtc_bus;
+    memset(&rtc_bus, 0, sizeof(struct RtcBus));
+
+    static struct RtcDriver rtc_driver;
+    memset(&rtc_driver, 0, sizeof(struct RtcDriver));
+    
+    rtc_driver.configure = &(RtcConfigure);
+
+    ret = BoardRtcBusInit(&rtc_bus, &rtc_driver);
+    if (EOK != ret) {
+        KPrintf("HwRtcInit error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardRtcDevBend();
+    if (EOK != ret) {
+        KPrintf("HwRtcInit error ret %u\n", ret);
+    }
+    
+    rtc_init();
+
+    return ret;
+}

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/rtc/hardware_rtc.c

@@ -0,0 +1,597 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file hardware_rtc.c
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#include <encoding.h>
+#include <hardware_rtc.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <sysctl.h>
+#include <time.h>
+
+volatile rtc_t *const rtc = (volatile rtc_t *)RTC_BASE_ADDR;
+
+struct tm rtc_date_time;
+
+void rtc_timer_set_mode(rtc_timer_mode_t timer_mode)
+{
+    rtc_register_ctrl_t register_ctrl = rtc->register_ctrl;
+
+    switch (timer_mode)
+    {
+        case RTC_TIMER_PAUSE:
+            register_ctrl.read_enable = 0;
+            register_ctrl.write_enable = 0;
+            break;
+        case RTC_TIMER_RUNNING:
+            register_ctrl.read_enable = 1;
+            register_ctrl.write_enable = 0;
+            break;
+        case RTC_TIMER_SETTING:
+            register_ctrl.read_enable = 0;
+            register_ctrl.write_enable = 1;
+            break;
+        default:
+            register_ctrl.read_enable = 0;
+            register_ctrl.write_enable = 0;
+            break;
+    }
+    rtc->register_ctrl = register_ctrl;
+}
+
+rtc_timer_mode_t rtc_timer_get_mode(void)
+{
+    rtc_register_ctrl_t register_ctrl = rtc->register_ctrl;
+    rtc_timer_mode_t timer_mode = RTC_TIMER_PAUSE;
+
+    if ((!register_ctrl.read_enable) && (!register_ctrl.write_enable))
+    {
+        /* RTC_TIMER_PAUSE */
+        timer_mode = RTC_TIMER_PAUSE;
+    }
+    else if ((register_ctrl.read_enable) && (!register_ctrl.write_enable))
+    {
+        /* RTC_TIMER_RUNNING */
+        timer_mode = RTC_TIMER_RUNNING;
+    }
+    else if ((!register_ctrl.read_enable) && (register_ctrl.write_enable)) {
+        /* RTC_TIMER_SETTING */
+        timer_mode = RTC_TIMER_SETTING;
+    }
+    else
+    {
+        /* Something is error, reset timer mode */
+        rtc_timer_set_mode(timer_mode);
+    }
+
+    return timer_mode;
+}
+
+static inline int rtc_in_range(int value, int min, int max)
+{
+    return ((value >= min) && (value <= max));
+}
+
+int rtc_timer_set_tm(const struct tm *tm)
+{
+    rtc_date_t timer_date;
+    rtc_time_t timer_time;
+    rtc_extended_t timer_extended;
+
+    if (tm)
+    {
+        /*
+         * Range of tm->tm_sec could be [0,61]
+         *
+         * Range of tm->tm_sec allows for a positive leap second. Two
+         * leap seconds in the same minute are not allowed (the C90
+         * range 0..61 was a defect)
+         */
+        if (rtc_in_range(tm->tm_sec, 0, 59))
+            timer_time.second = tm->tm_sec;
+        else
+            return -1;
+
+        /* Range of tm->tm_min could be [0,59] */
+        if (rtc_in_range(tm->tm_min, 0, 59))
+            timer_time.minute = tm->tm_min;
+        else
+            return -1;
+
+        /* Range of tm->tm_hour could be [0, 23] */
+        if (rtc_in_range(tm->tm_hour, 0, 23))
+            timer_time.hour = tm->tm_hour;
+        else
+            return -1;
+
+        /* Range of tm->tm_mday could be [1, 31] */
+        if (rtc_in_range(tm->tm_mday, 1, 31))
+            timer_date.day = tm->tm_mday;
+        else
+            return -1;
+
+        /*
+         * Range of tm->tm_mon could be [0, 11]
+         * But in this RTC, date.month should be [1, 12]
+         */
+        if (rtc_in_range(tm->tm_mon, 0, 11))
+            timer_date.month = tm->tm_mon + 1;
+        else
+            return -1;
+
+        /*
+         * Range of tm->tm_year is the years since 1900
+         * But in this RTC, year is split into year and century
+         * In this RTC, century range is [0,31], year range is [0,99]
+         */
+        int human_year = tm->tm_year + 1900;
+        int rtc_year = human_year % 100;
+        int rtc_century = human_year / 100;
+
+        if (rtc_in_range(rtc_year, 0, 99) &&
+            rtc_in_range(rtc_century, 0, 31))
+        {
+            timer_date.year = rtc_year;
+            timer_extended.century = rtc_century;
+        }
+        else
+            return -1;
+
+        /* Range of tm->tm_wday could be [0, 6] */
+        if (rtc_in_range(tm->tm_wday, 0, 6))
+            timer_date.week = tm->tm_wday;
+        else
+            return -1;
+
+        /* Set RTC mode to timer setting mode */
+        rtc_timer_set_mode(RTC_TIMER_SETTING);
+        /* Write value to RTC */
+        rtc->date = timer_date;
+        rtc->time = timer_time;
+        rtc->extended = timer_extended;
+        /* Get CPU current freq */
+        unsigned long freq = SysctlClockGetFreq(SYSCTL_CLOCK_CPU);
+        /* Set threshold to 1/26000000 s */
+        freq = freq / 26000000;
+        /* Get current CPU cycle */
+        unsigned long start_cycle = read_cycle();
+        /* Wait for 1/26000000 s to sync data */
+        while (read_cycle() - start_cycle < freq)
+            continue;
+        /* Set RTC mode to timer running mode */
+        rtc_timer_set_mode(RTC_TIMER_RUNNING);
+    }
+
+    return 0;
+}
+
+int rtc_timer_set_alarm_tm(const struct tm *tm)
+{
+    rtc_alarm_date_t alarm_date;
+    rtc_alarm_time_t alarm_time;
+
+    if (tm) {
+        /*
+         * Range of tm->tm_sec could be [0,61]
+         *
+         * Range of tm->tm_sec allows for a positive leap second. Two
+         * leap seconds in the same minute are not allowed (the C90
+         * range 0..61 was a defect)
+         */
+        if (rtc_in_range(tm->tm_sec, 0, 59))
+            alarm_time.second = tm->tm_sec;
+        else
+            return -1;
+
+        /* Range of tm->tm_min could be [0,59] */
+        if (rtc_in_range(tm->tm_min, 0, 59))
+            alarm_time.minute = tm->tm_min;
+        else
+            return -1;
+
+        /* Range of tm->tm_hour could be [0, 23] */
+        if (rtc_in_range(tm->tm_hour, 0, 23))
+            alarm_time.hour = tm->tm_hour;
+        else
+            return -1;
+
+        /* Range of tm->tm_mday could be [1, 31] */
+        if (rtc_in_range(tm->tm_mday, 1, 31))
+            alarm_date.day = tm->tm_mday;
+        else
+            return -1;
+
+        /*
+         * Range of tm->tm_mon could be [0, 11]
+         * But in this RTC, date.month should be [1, 12]
+         */
+        if (rtc_in_range(tm->tm_mon, 0, 11))
+            alarm_date.month = tm->tm_mon + 1;
+        else
+            return -1;
+
+        /*
+         * Range of tm->tm_year is the years since 1900
+         * But in this RTC, year is split into year and century
+         * In this RTC, century range is [0,31], year range is [0,99]
+         */
+        int human_year = tm->tm_year + 1900;
+        int rtc_year = human_year % 100;
+        int rtc_century = human_year / 100;
+
+        if (rtc_in_range(rtc_year, 0, 99) &&
+            rtc_in_range(rtc_century, 0, 31))
+        {
+            alarm_date.year = rtc_year;
+        } else
+            return -1;
+
+        /* Range of tm->tm_wday could be [0, 6] */
+        if (rtc_in_range(tm->tm_wday, 0, 6))
+            alarm_date.week = tm->tm_wday;
+        else
+            return -1;
+
+        /* Write value to RTC */
+        rtc->alarm_date = alarm_date;
+        rtc->alarm_time = alarm_time;
+    }
+
+    return 0;
+}
+
+static int rtc_year_is_leap(int year)
+{
+    return (year % 4 == 0 && year % 100 != 0) || (year % 400 == 0);
+}
+
+static int rtc_get_yday(int year, int month, int day)
+{
+    static const int days[2][13] =
+    {
+        {0, 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334},
+        {0, 0, 31, 60, 91, 121, 152, 182, 213, 244, 274, 305, 335}
+    };
+    int leap = rtc_year_is_leap(year);
+
+    return days[leap][month] + day;
+}
+
+static int rtc_get_wday(int year, int month, int day)
+{
+    /* Magic method to get weekday */
+    int weekday  = (day += month < 3 ? year-- : year - 2, 23 * month / 9 + day + 4 + year / 4 - year / 100 + year / 400) % 7;
+    return weekday;
+}
+
+struct tm *rtc_timer_get_tm(void)
+{
+    if (rtc_timer_get_mode() != RTC_TIMER_RUNNING)
+        return NULL;
+
+    rtc_date_t timer_date = rtc->date;
+    rtc_time_t timer_time = rtc->time;
+    rtc_extended_t timer_extended = rtc->extended;
+
+    struct tm *tm = &rtc_date_time;
+
+    tm->tm_sec = timer_time.second % 60;
+    tm->tm_min = timer_time.minute % 60;
+    tm->tm_hour = timer_time.hour % 24;
+    tm->tm_mday = (timer_date.day - 1) % 31 + 1;
+    tm->tm_mon = (timer_date.month - 1)% 12;
+    tm->tm_year = (timer_date.year % 100) + (timer_extended.century * 100) - 1900;
+    tm->tm_wday = timer_date.week;
+    tm->tm_yday = rtc_get_yday(tm->tm_year + 1900, tm->tm_mon + 1, tm->tm_mday);
+    tm->tm_isdst = -1;
+
+    return tm;
+}
+
+struct tm *rtc_timer_get_alarm_tm(void)
+{
+    if (rtc_timer_get_mode() != RTC_TIMER_RUNNING)
+        return NULL;
+
+    rtc_alarm_date_t alarm_date = rtc->alarm_date;
+    rtc_alarm_time_t alarm_time = rtc->alarm_time;
+    rtc_extended_t timer_extended = rtc->extended;
+
+    struct tm *tm = &rtc_date_time;
+
+    tm->tm_sec = alarm_time.second % 60;
+    tm->tm_min = alarm_time.minute % 60;
+    tm->tm_hour = alarm_time.hour % 24;
+    tm->tm_mday = alarm_date.day % 31;
+    tm->tm_mon = (alarm_date.month % 12) - 1;
+    /* Alarm and Timer use same timer_extended.century */
+    tm->tm_year = (alarm_date.year % 100) + (timer_extended.century * 100) - 1900;
+    tm->tm_wday = alarm_date.week;
+    tm->tm_yday = rtc_get_yday(tm->tm_year + 1900, tm->tm_mon + 1, tm->tm_mday);
+    tm->tm_isdst = -1;
+
+    return tm;
+}
+
+int rtc_timer_set(int year, int month, int day, int hour, int minute, int second)
+{
+    struct tm date_time =
+    {
+        .tm_sec = second,
+        .tm_min = minute,
+        .tm_hour = hour,
+        .tm_mday = day,
+        .tm_mon = month - 1,
+        .tm_year = year - 1900,
+        .tm_wday = rtc_get_wday(year, month, day),
+        .tm_yday = rtc_get_yday(year, month, day),
+        .tm_isdst = -1,
+    };
+    return rtc_timer_set_tm(&date_time);
+}
+
+int rtc_timer_get(int *year, int *month, int *day, int *hour, int *minute, int *second)
+{
+    struct tm *tm = rtc_timer_get_tm();
+
+    if (tm)
+    {
+        if (year)
+            *year = tm->tm_year + 1900;
+        if (month)
+            *month = tm->tm_mon + 1;
+        if (day)
+            *day = tm->tm_mday;
+        if (hour)
+            *hour = tm->tm_hour;
+        if (minute)
+            *minute = tm->tm_min;
+        if (second)
+            *second = tm->tm_sec;
+    } else
+        return -1;
+
+    return 0;
+}
+
+int rtc_timer_set_alarm(int year, int month, int day, int hour, int minute, int second)
+{
+    struct tm date_time = {
+        .tm_sec = second,
+        .tm_min = minute,
+        .tm_hour = hour,
+        .tm_mday = day,
+        .tm_mon = month - 1,
+        .tm_year = year - 1900,
+        .tm_wday = rtc_get_wday(year, month, day),
+        .tm_yday = rtc_get_yday(year, month, day),
+        .tm_isdst = -1,
+    };
+
+    return rtc_timer_set_alarm_tm(&date_time);
+}
+
+int rtc_timer_get_alarm(int *year, int *month, int *day, int *hour, int *minute, int *second)
+{
+    struct tm *tm = rtc_timer_get_alarm_tm();
+
+    if (tm) {
+        if (year)
+            *year = tm->tm_year + 1900;
+        if (month)
+            *month = tm->tm_mon + 1;
+        if (day)
+            *day = tm->tm_mday;
+        if (hour)
+            *hour = tm->tm_hour;
+        if (minute)
+            *minute = tm->tm_min;
+        if (second)
+            *second = tm->tm_sec;
+    } else
+        return -1;
+
+    return 0;
+}
+
+int rtc_timer_set_clock_frequency(unsigned int frequency)
+{
+
+    rtc_initial_count_t initial_count;
+
+    initial_count.count = frequency;
+    rtc_timer_set_mode(RTC_TIMER_SETTING);
+    rtc->initial_count = initial_count;
+    rtc_timer_set_mode(RTC_TIMER_RUNNING);
+    return 0;
+}
+
+unsigned int rtc_timer_get_clock_frequency(void)
+{
+    return rtc->initial_count.count;
+}
+
+int rtc_timer_set_clock_count_value(unsigned int  count)
+{
+
+    rtc_current_count_t current_count;
+
+    current_count.count = count;
+    rtc_timer_set_mode(RTC_TIMER_SETTING);
+    rtc->current_count = current_count;
+    rtc_timer_set_mode(RTC_TIMER_RUNNING);
+    return 0;
+}
+
+unsigned int rtc_timer_get_clock_count_value(void)
+{
+    return rtc->current_count.count;
+}
+
+int rtc_tick_interrupt_set(int enable)
+{
+    rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl;
+    interrupt_ctrl.tick_enable = enable;
+    rtc_timer_set_mode(RTC_TIMER_SETTING);
+    rtc->interrupt_ctrl = interrupt_ctrl;
+    rtc_timer_set_mode(RTC_TIMER_RUNNING);
+    return 0;
+}
+
+int rtc_tick_interrupt_get(void)
+{
+    rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl;
+
+    return interrupt_ctrl.tick_enable;
+}
+
+int rtc_tick_interrupt_mode_set(rtc_tick_interrupt_mode_t mode)
+{
+    rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl;
+
+    interrupt_ctrl.tick_int_mode = mode;
+    rtc_timer_set_mode(RTC_TIMER_SETTING);
+    rtc->interrupt_ctrl = interrupt_ctrl;
+    rtc_timer_set_mode(RTC_TIMER_RUNNING);
+    return 0;
+}
+
+rtc_tick_interrupt_mode_t rtc_tick_interrupt_mode_get(void)
+{
+    rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl;
+
+    return interrupt_ctrl.tick_int_mode;
+}
+
+int rtc_alarm_interrupt_set(int enable)
+{
+    rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl;
+
+    interrupt_ctrl.alarm_enable = enable;
+    rtc->interrupt_ctrl = interrupt_ctrl;
+    return 0;
+}
+
+int rtc_alarm_interrupt_get(void)
+{
+    rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl;
+
+    return interrupt_ctrl.alarm_enable;
+}
+
+int rtc_alarm_interrupt_mask_set(rtc_mask_t mask)
+{
+    rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl;
+
+    interrupt_ctrl.alarm_compare_mask = *(uint8_t *)&mask;
+    rtc->interrupt_ctrl = interrupt_ctrl;
+    return 0;
+}
+
+rtc_mask_t rtc_alarm_interrupt_mask_get(void)
+{
+    rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl;
+
+    uint8_t compare_mask = interrupt_ctrl.alarm_compare_mask;
+
+    return *(rtc_mask_t *)&compare_mask;
+}
+
+int rtc_protect_set(int enable)
+{
+    rtc_register_ctrl_t register_ctrl = rtc->register_ctrl;
+
+    rtc_mask_t mask =
+    {
+        .second = 1,
+        /* Second mask */
+        .minute = 1,
+        /* Minute mask */
+        .hour = 1,
+        /* Hour mask */
+        .week = 1,
+        /* Week mask */
+        .day = 1,
+        /* Day mask */
+        .month = 1,
+        /* Month mask */
+        .year = 1,
+    };
+
+    rtc_mask_t unmask =
+    {
+        .second = 0,
+        /* Second mask */
+        .minute = 0,
+        /* Minute mask */
+        .hour = 0,
+        /* Hour mask */
+        .week = 0,
+        /* Week mask */
+        .day = 0,
+        /* Day mask */
+        .month = 0,
+        /* Month mask */
+        .year = 0,
+    };
+
+    if (enable)
+    {
+        /* Turn RTC in protect mode, no one can write time */
+        register_ctrl.TimerMask = *(uint8_t *)&unmask;
+        register_ctrl.alarm_mask = *(uint8_t *)&unmask;
+        register_ctrl.initial_count_mask = 0;
+        register_ctrl.interrupt_register_mask = 0;
+    }
+    else
+    {
+        /* Turn RTC in unprotect mode, everyone can write time */
+        register_ctrl.TimerMask = *(uint8_t *)&mask;
+        register_ctrl.alarm_mask = *(uint8_t *)&mask;
+        register_ctrl.initial_count_mask = 1;
+        register_ctrl.interrupt_register_mask = 1;
+    }
+    rtc_timer_set_mode(RTC_TIMER_SETTING);
+    rtc->register_ctrl = register_ctrl;
+    rtc_timer_set_mode(RTC_TIMER_RUNNING);
+    return 0;
+}
+
+int rtc_init(void)
+{
+    /* Reset RTC */
+    sysctl_reset(SYSCTL_RESET_RTC);
+    /* Enable RTC */
+    sysctl_clock_enable(SYSCTL_CLOCK_RTC);
+    /* Unprotect RTC */
+    rtc_protect_set(0);
+    /* Set RTC clock frequency */
+    rtc_timer_set_clock_frequency(
+        SysctlClockGetFreq(SYSCTL_CLOCK_IN0)
+    );
+    rtc_timer_set_clock_count_value(1);
+
+    /* Set RTC mode to timer running mode */
+    rtc_timer_set_mode(RTC_TIMER_RUNNING);
+    return 0;
+}

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/sleep.c

@@ -0,0 +1,49 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file sleep.c
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#include <sleep.h>
+#include <sysctl.h>
+
+int usleep(uint64_t usec)
+{
+    uint64_t cycle = read_cycle();
+    uint64_t nop_all = usec * SysctlClockGetFreq(SYSCTL_CLOCK_CPU) / 1000000UL;
+    while (1)
+    {
+        if(read_cycle() - cycle >= nop_all)
+            break;
+    }
+    return 0;
+}
+
+int msleep(uint64_t msec)
+{
+    return (unsigned int)usleep(msec * 1000);
+}
+
+unsigned int sleep(unsigned int seconds)
+{
+    return (unsigned int)msleep(seconds * 1000);
+}
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/Kconfig

@@ -0,0 +1,125 @@
+config BSP_USING_SPI1
+bool "Using spi1  "
+default y
+
+
+if BSP_USING_SPI1
+    config SPI_BUS_NAME_1
+        string "spi bus 1 name"
+        default "spi1"
+    config SPI_1_DRV_NAME
+        string "spi bus 1 driver name"
+        default "spi1_drv"    
+    config BSP_SPI1_CLK_PIN
+        int "spi1 clk pin number"
+        default 6
+    config BSP_SPI1_D0_PIN
+        int "spi1 d0 pin number"
+        default 8
+    config BSP_SPI1_D1_PIN
+        int "spi1 d1 pin number"
+        default 7
+    menuconfig BSP_SPI1_USING_SS0
+        bool "SPI1 Enable SS0"
+        default y
+    if BSP_SPI1_USING_SS0
+        config SPI_1_DEVICE_NAME_0
+            string "spi bus 1 device 0 name"
+            default "spi1_dev0"        
+        config BSP_SPI1_SS0_PIN
+            int "spi1 ss0 pin number"
+            default 9
+    menuconfig RESOURCES_SPI_LORA
+    bool "Using spi lora function"
+    default n
+        if RESOURCES_SPI_LORA
+        config SX12XX_DEVICE_NAME
+            string "SX1278 lora device name"
+            default "spi1_lora"
+        config SX12XX_DEVICE_RST_PIN
+            int
+            default 10
+
+        config SX12XX_DEVICE_DO0_PIN
+            int
+            default 10
+
+        config SX12XX_DEVICE_DO1_PIN
+            int
+            default 10
+
+        config SX12XX_DEVICE_DO2_PIN
+            int
+            default 10
+        
+        config SX12XX_DEVICE_DO3_PIN
+            int
+            default 10
+        
+        config SX12XX_DEVICE_DO4_PIN
+            int
+            default 10
+        
+        config SX12XX_DEVICE_DO5_PIN
+            int
+            default 10
+        endif
+    endif
+    menuconfig BSP_SPI1_USING_SS1
+        bool "SPI1 Enable SS1"
+        default y
+    if BSP_SPI1_USING_SS1
+        config SPI_1_DEVICE_NAME_1
+            string "spi bus 1 device 1 name"
+            default "spi1_dev1"             
+        config BSP_SPI1_SS1_PIN
+            int "spi1 ss1 pin number"
+            default 33
+    endif
+    menuconfig BSP_SPI1_USING_SS2
+        bool "SPI1 Enable SS2"
+        default n
+    if BSP_SPI1_USING_SS2
+        config SPI_1_DEVICE_NAME_2
+            string "spi bus 1 device 2 name"
+            default "spi1_dev2"              
+        config BSP_SPI1_SS2_PIN
+            int "spi1 ss2 pin number"
+            default 26
+    endif
+    menuconfig BSP_SPI1_USING_SS3
+        bool "SPI1 Enable SS3"
+        default n
+    if BSP_SPI1_USING_SS3
+        config SPI_1_DEVICE_NAME_3
+            string "spi bus 1 device 3 name"
+            default "spi1_dev3"               
+        config BSP_SPI1_SS3_PIN
+            int "spi1 ss3 pin number"
+            default 27
+    endif
+endif
+
+config BSP_USING_TP
+bool "Using LCD touch  "
+default n
+
+if BSP_USING_TP
+    config BSP_TP_SCK_PIN
+        int "TP SCK pin number"
+        default 42
+    config BSP_TP_NCS_PIN
+        int "TP NCS pin number"
+        default 43
+    config BSP_TP_MISO_PIN
+        int "TP MISO pin number"
+        default 44
+    config BSP_TP_IRQ_PIN
+        int "TP IRQ pin number"
+        default 45
+    config BSP_TP_MOSI_PIN
+        int "TP MOSI pin number"
+        default 46
+
+endif
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/Makefile

@@ -0,0 +1,9 @@
+SRC_FILES := connect_spi.c hardware_spi.c
+
+
+ifeq ($(CONFIG_RESOURCES_SPI_LORA),y)
+	SRC_DIR += third_party_spi_lora
+	SRC_FILES += connect_lora_spi.c
+endif
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/connect_lora_spi.c

@@ -0,0 +1,547 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_lora_spi.c
+* @brief support to register spi lora pointer and function
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-05-17
+*/
+
+#include <connect_spi_lora.h>
+
+static struct HardwareDev *g_spi_lora_dev;
+static BusType buspin;
+tRadioDriver *Radio = NONE;
+void SX1276InitIo(void)
+{
+    struct PinParam PinCfg;
+	struct PinStat PinStat;
+
+	struct BusConfigureInfo configure_info;
+	struct BusBlockWriteParam write_param;
+
+    write_param.buffer = (void *)&PinStat;
+    configure_info.configure_cmd = OPE_CFG;
+    configure_info.private_data = (void *)&PinCfg;
+
+    buspin = PinBusInitGet();  
+
+    PinCfg.cmd = GPIO_CONFIG_MODE;
+    PinCfg.pin = SX12XX_DEVICE_DO0_PIN;
+    PinCfg.mode = GPIO_CFG_INPUT;
+    BusDrvConfigure(buspin->owner_driver, &configure_info);
+
+    PinCfg.cmd = GPIO_CONFIG_MODE;
+    PinCfg.pin = SX12XX_DEVICE_DO1_PIN;
+    PinCfg.mode = GPIO_CFG_INPUT;
+    BusDrvConfigure(buspin->owner_driver, &configure_info);
+
+    PinCfg.cmd = GPIO_CONFIG_MODE;
+    PinCfg.pin = SX12XX_DEVICE_DO2_PIN;
+    PinCfg.mode = GPIO_CFG_INPUT;
+    BusDrvConfigure(buspin->owner_driver, &configure_info);
+}
+
+inline uint8_t SX1276ReadDio0(void)
+{
+    struct PinStat PinStat;
+
+    struct BusBlockReadParam read_param;
+    read_param.buffer = (void *)&PinStat;
+
+    PinStat.pin = SX12XX_DEVICE_DO0_PIN;
+    
+    return BusDevReadData(buspin->owner_haldev, &read_param);
+}
+
+inline uint8_t SX1276ReadDio1(void)
+{
+    struct PinStat PinStat;
+
+    struct BusBlockReadParam read_param;
+    read_param.buffer = (void *)&PinStat;
+
+    PinStat.pin = SX12XX_DEVICE_DO1_PIN;
+    
+    return BusDevReadData(buspin->owner_haldev, &read_param);
+}
+
+inline uint8_t SX1276ReadDio2(void)
+{
+    struct PinStat PinStat;
+
+    struct BusBlockReadParam read_param;
+    read_param.buffer = (void *)&PinStat;
+
+    PinStat.pin = SX12XX_DEVICE_DO2_PIN;
+    
+    return BusDevReadData(buspin->owner_haldev, &read_param);
+}
+
+inline uint8_t SX1276ReadDio3(void)
+{
+    struct PinStat PinStat;
+
+    struct BusBlockReadParam read_param;
+    read_param.buffer = (void *)&PinStat;
+
+    PinStat.pin = SX12XX_DEVICE_DO3_PIN;
+    
+    return BusDevReadData(buspin->owner_haldev, &read_param);
+}
+
+inline uint8_t SX1276ReadDio4(void)
+{
+    struct PinStat PinStat;
+
+    struct BusBlockReadParam read_param;
+    read_param.buffer = (void *)&PinStat;
+
+    PinStat.pin = SX12XX_DEVICE_DO4_PIN;
+    
+    return BusDevReadData(buspin->owner_haldev, &read_param);
+}
+
+inline uint8_t SX1276ReadDio5(void)
+{
+    struct PinStat PinStat;
+
+    struct BusBlockReadParam read_param;
+    read_param.buffer = (void *)&PinStat;
+
+    PinStat.pin = SX12XX_DEVICE_DO5_PIN;
+    
+    return BusDevReadData(buspin->owner_haldev, &read_param);
+}
+
+inline void SX1276WriteRxTx(uint8_t txEnable)
+{
+    return;
+}
+
+void SX1276SetReset(uint8_t state)
+{
+    struct PinParam PinCfg;
+	struct PinStat PinStat;
+
+	struct BusConfigureInfo configure_info;
+	struct BusBlockWriteParam write_param;
+
+    configure_info.configure_cmd = OPE_CFG;
+    configure_info.private_data = (void *)&PinCfg;
+    write_param.buffer = (void *)&PinStat;
+
+    if (state == RADIO_RESET_ON)
+    {
+        PinCfg.cmd = GPIO_CONFIG_MODE;
+        PinCfg.pin = SX12XX_DEVICE_RST_PIN;
+        PinCfg.mode = GPIO_CFG_OUTPUT;
+        BusDrvConfigure(buspin->owner_driver, &configure_info);
+
+        PinStat.val = GPIO_LOW;
+        PinStat.pin = SX12XX_DEVICE_RST_PIN;
+        BusDevWriteData(buspin->owner_haldev, &write_param);
+    }
+    else
+    {
+        PinCfg.cmd = GPIO_CONFIG_MODE;
+        PinCfg.pin = SX12XX_DEVICE_RST_PIN;
+        PinCfg.mode = GPIO_CFG_INPUT;
+        BusDrvConfigure(buspin->owner_driver, &configure_info);
+    }
+}
+
+void SX1276Write(uint8_t addr, uint8_t data)
+{
+    SX1276WriteBuffer(addr, &data, 1);
+}
+
+void SX1276Read(uint8_t addr, uint8_t *data)
+{
+    SX1276ReadBuffer(addr, data, 1);
+}
+
+void SX1276WriteBuffer(uint8_t addr, uint8_t *buffer, uint8_t size)
+{
+    struct BusBlockWriteParam write_param;
+    uint8 write_addr = addr | 0x80;
+
+    BusDevOpen(g_spi_lora_dev);
+
+    write_param.buffer = (void *)&write_addr;
+    write_param.size = 1;
+    BusDevWriteData(g_spi_lora_dev, &write_param);
+
+    write_param.buffer = (void *)buffer;
+    write_param.size = size;
+    BusDevWriteData(g_spi_lora_dev, &write_param);
+
+    BusDevClose(g_spi_lora_dev);
+}
+
+void SX1276ReadBuffer(uint8_t addr, uint8_t *buffer, uint8_t size)
+{
+    struct BusBlockWriteParam write_param;
+    struct BusBlockReadParam read_param;
+
+    uint8 write_addr = addr & 0x7F;
+
+    BusDevOpen(g_spi_lora_dev);
+
+    write_param.buffer = (void *)&write_addr;
+    write_param.size = 1;
+    BusDevWriteData(g_spi_lora_dev, &write_param);
+
+    read_param.buffer = (void *)buffer;
+    read_param.size = size;
+    BusDevReadData(g_spi_lora_dev, &read_param);
+
+    BusDevClose(g_spi_lora_dev);
+}
+
+void SX1276WriteFifo(uint8_t *buffer, uint8_t size)
+{
+    SX1276WriteBuffer(0, buffer, size);
+}
+
+void SX1276ReadFifo(uint8_t *buffer, uint8_t size)
+{
+    SX1276ReadBuffer(0, buffer, size);
+}
+
+uint8_t SX1276_Spi_Check()
+{
+    uint8_t test = 0;
+    KPrintf("SX1276_Spi_Check start\n");
+	tLoRaSettings settings;
+	SX1276Read(REG_LR_VERSION,&test);
+	KPrintf("version code of the chip is %x\n",test);
+	settings.RFFrequency = SX1276LoRaGetRFFrequency();
+	KPrintf("SX1278 Lora parameters are :\nRFFrequency is %d\n",settings.RFFrequency);
+	settings.Power = SX1276LoRaGetRFPower();
+	KPrintf("RFPower is %d\n",settings.Power);
+    settings.SignalBw = SX1276LoRaGetSignalBandwidth();	  
+	KPrintf("SignalBw is %d\n",settings.SignalBw);
+	settings.SpreadingFactor = SX1276LoRaGetSpreadingFactor();
+	KPrintf("SpreadingFactor is %d\n",settings.SpreadingFactor);
+    /*SPI confirm*/
+    SX1276Write(REG_LR_HOPPERIOD, 0x91);  
+    SX1276Read(REG_LR_HOPPERIOD, &test);
+    if (test != 0x91) {
+        return 0;
+    }		
+    return test;
+}
+
+/**
+ * This function supports to write data to the lora.
+ *
+ * @param dev lora dev descriptor
+ * @param write_param lora dev write datacfg param
+ */
+static uint32 SpiLoraWrite(void *dev, struct BusBlockWriteParam *write_param)
+{
+    NULL_PARAM_CHECK(dev);
+    NULL_PARAM_CHECK(write_param);
+
+    if (write_param->size > 256) {
+        KPrintf("SpiLoraWrite ERROR:The message is too long!\n");
+        return ERROR;
+    } else {
+        //Radio->SetTxPacket(write_param->buffer, write_param->size);    
+        //while(Radio->Process() != RF_TX_DONE);
+        SX1276SetTxPacket(write_param->buffer, write_param->size);    
+        while(SX1276Process() != RF_TX_DONE);
+        KPrintf("SpiLoraWrite success!\n");
+    }
+
+    return EOK;
+}
+
+/**
+ * This function supports to read data from the lora.
+ *
+ * @param dev lora dev descriptor
+ * @param read_param lora dev read datacfg param
+ */
+static uint32 SpiLoraRead(void *dev, struct BusBlockReadParam *read_param)
+{
+    NULL_PARAM_CHECK(dev);
+    NULL_PARAM_CHECK(read_param);
+
+    int read_times = 1000;
+    
+    //Radio->StartRx();
+    SX1276StartRx();
+    KPrintf("SpiLoraRead Ready!\n");
+
+    while (read_times) {
+        if (SX1276Process() != RF_RX_DONE) {
+            read_times --;
+            MdelayKTask(500);
+        } else {
+            break;
+        }
+    }
+
+    if (read_times > 0) {
+        SX1276GetRxPacket(read_param->buffer, (uint16 *)&read_param->read_length);
+    } else {
+        read_param->read_length = 0;
+    }
+    
+    //while(Radio->Process() != RF_RX_DONE);
+    //Radio->GetRxPacket(read_param->buffer, (uint16 *)&read_param->read_length);     
+    // while(SX1276Process() != RF_RX_DONE);
+    // SX1276GetRxPacket(read_param->buffer, (uint16 *)&read_param->read_length);
+
+    return read_param->read_length;
+}
+
+static uint32 SpiLoraOpen(void *dev)
+{
+    NULL_PARAM_CHECK(dev);
+
+    KPrintf("SpiLoraOpen start\n");
+
+    x_err_t ret = EOK;
+    static x_bool lora_init_status = RET_FALSE;
+
+    if (RET_TRUE == lora_init_status) {
+        return EOK;
+    }
+
+    struct HardwareDev *haldev = (struct HardwareDev *)dev;
+
+    struct SpiHardwareDevice *lora_dev = CONTAINER_OF(haldev, struct SpiHardwareDevice, haldev);
+    NULL_PARAM_CHECK(lora_dev);
+
+    SpiLoraDeviceType spi_lora_dev = CONTAINER_OF(lora_dev, struct SpiLoraDevice, lora_dev);    
+    NULL_PARAM_CHECK(spi_lora_dev);
+
+    struct Driver *spi_drv = spi_lora_dev->spi_dev->haldev.owner_bus->owner_driver;
+
+    struct BusConfigureInfo configure_info;
+    struct SpiMasterParam spi_master_param;
+    spi_master_param.spi_data_bit_width = 8;
+    spi_master_param.spi_work_mode = SPI_MODE_0 | SPI_MSB;
+    spi_master_param.spi_maxfrequency = SPI_LORA_FREQUENCY;
+    spi_master_param.spi_data_endian = 0;
+
+    configure_info.configure_cmd = OPE_CFG;
+    configure_info.private_data = (void *)&spi_master_param;
+    ret = BusDrvConfigure(spi_drv, &configure_info);
+    if (ret) {
+        KPrintf("spi drv OPE_CFG error drv %8p cfg %8p\n", spi_drv, &spi_master_param);
+        return ERROR;
+    }
+
+    configure_info.configure_cmd = OPE_INT;
+    ret = BusDrvConfigure(spi_drv, &configure_info);
+    if (ret) {
+        KPrintf("spi drv OPE_INT error drv %8p\n", spi_drv);
+        return ERROR;
+    }
+
+    SX1276Init();
+
+    if (0x91 != SX1276_Spi_Check()) {
+        KPrintf("LoRa check failed!\n!");
+    } else {
+        Radio = RadioDriverInit();
+        KPrintf("LoRa check ok!\nNote: The length of the message that can be sent in a single time is 256 characters\n");
+    }
+    
+    lora_init_status = RET_TRUE;
+
+    return ret;
+}
+
+static uint32 SpiLoraClose(void *dev)
+{
+    NULL_PARAM_CHECK(dev);
+
+    return EOK;
+}
+
+static const struct LoraDevDone lora_done =
+{
+    .open = SpiLoraOpen,
+    .close = SpiLoraClose,
+    .write = SpiLoraWrite,
+    .read = SpiLoraRead,
+};
+
+/**
+ * This function supports to init spi_lora_dev
+ *
+ * @param bus_name spi bus name
+ * @param dev_name spi dev name
+ * @param drv_name spi drv name
+ * @param flash_name flash dev name
+ */
+SpiLoraDeviceType SpiLoraInit(char *bus_name, char *dev_name, char *drv_name, char *lora_name)
+{
+    NULL_PARAM_CHECK(dev_name);
+    NULL_PARAM_CHECK(drv_name);
+    NULL_PARAM_CHECK(lora_name);
+    NULL_PARAM_CHECK(bus_name);
+
+    x_err_t ret;
+    static HardwareDevType haldev;
+
+    haldev = SpiDeviceFind(dev_name, TYPE_SPI_DEV);
+    if (NONE == haldev) {
+        KPrintf("SpiLoraInit find spi haldev %s error! \n", dev_name);
+        return NONE;
+    }
+
+    SpiLoraDeviceType spi_lora_dev = (SpiLoraDeviceType)malloc(sizeof(struct SpiLoraDevice));
+    if (NONE == spi_lora_dev) {
+        KPrintf("SpiLoraInit malloc spi_lora_dev failed\n");
+        free(spi_lora_dev);
+        return NONE;
+    }
+
+    memset(spi_lora_dev, 0, sizeof(struct SpiLoraDevice));
+
+    spi_lora_dev->spi_dev = CONTAINER_OF(haldev, struct SpiHardwareDevice, haldev);
+
+    spi_lora_dev->lora_dev.spi_dev_flag = RET_TRUE;
+    spi_lora_dev->lora_dev.haldev.dev_done = (struct HalDevDone *)&lora_done;
+
+    spi_lora_dev->spi_dev->haldev.owner_bus->owner_driver = SpiDriverFind(drv_name, TYPE_SPI_DRV);
+    if (NONE == spi_lora_dev->spi_dev->haldev.owner_bus->owner_driver) {
+        KPrintf("SpiLoraInit find spi driver %s error! \n", drv_name);
+        free(spi_lora_dev);
+        return NONE;
+    }
+
+    ret = SpiDeviceRegister(&spi_lora_dev->lora_dev, spi_lora_dev->spi_dev->haldev.private_data, lora_name);
+    if (EOK != ret) {
+        KPrintf("SpiLoraInit SpiDeviceRegister device %s error %d\n", lora_name, ret);
+        free(spi_lora_dev);   
+        return NONE;
+    }
+
+    ret = SpiDeviceAttachToBus(lora_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("SpiLoraInit SpiDeviceAttachToBus device %s error %d\n", lora_name, ret);
+        free(spi_lora_dev);
+        return NONE;
+    }
+
+    g_spi_lora_dev = &spi_lora_dev->spi_dev->haldev;
+
+    return spi_lora_dev;
+}
+
+/**
+ * This function supports to release spi_lora_dev
+ *
+ * @param spi_lora_dev spi lora descriptor
+ */
+uint32 SpiLoraRelease(SpiLoraDeviceType spi_lora_dev)
+{
+    NULL_PARAM_CHECK(spi_lora_dev);
+
+    x_err_t ret;
+
+    DeviceDeleteFromBus(spi_lora_dev->lora_dev.haldev.owner_bus, &spi_lora_dev->lora_dev.haldev);
+
+    free(spi_lora_dev);
+
+    return EOK;
+}
+
+int LoraSx12xxSpiDeviceInit(void)
+{
+#ifdef BSP_USING_SPI1
+
+    if (NONE == SpiLoraInit(SPI_BUS_NAME_1, SPI_1_DEVICE_NAME_0, SPI_1_DRV_NAME, SX12XX_DEVICE_NAME)) {
+        return ERROR;
+    }
+
+#endif
+
+    return EOK;
+}
+
+//#define LORA_TEST
+#ifdef LORA_TEST
+/*Just for lora test*/
+static struct Bus *bus;
+static struct HardwareDev *dev;
+static struct Driver *drv;
+
+void LoraOpen(void)
+{
+    x_err_t ret = EOK;
+
+    ret = LoraSx12xxSpiDeviceInit();
+    if (EOK != ret) {
+        KPrintf("LoraSx12xxSpiDeviceInit failed\n");
+        return;
+    }
+
+    bus = BusFind(SPI_BUS_NAME_1);
+    dev = BusFindDevice(bus, SX12XX_DEVICE_NAME);
+    drv = BusFindDriver(bus, SPI_1_DRV_NAME);
+
+    bus->match(drv, dev);
+ 
+    ret = SpiLoraOpen(dev);
+    if (EOK != ret) {
+        KPrintf("LoRa init failed\n");
+        return;
+    }
+
+    KPrintf("LoRa init succeed\n");
+
+    return;
+}
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
+                                                LoraOpen, LoraOpen,  open lora device and read parameters );
+
+static void LoraReceive(void)
+{
+    struct BusBlockReadParam read_param;
+    memset(&read_param, 0, sizeof(struct BusBlockReadParam));
+
+    read_param.buffer = malloc(SPI_LORA_BUFFER_SIZE);
+
+    SpiLoraRead(dev, &read_param);
+
+    free(read_param.buffer);
+}
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),
+LoraReceive, LoraReceive,  lora wait message );
+
+static void LoraSend(int argc, char *argv[])
+{
+    char Msg[SPI_LORA_BUFFER_SIZE] = {0};
+    struct BusBlockWriteParam write_param;
+    memset(&write_param, 0, sizeof(struct BusBlockWriteParam));
+
+    if (argc == 2) {
+        strncpy(Msg, argv[1], SPI_LORA_BUFFER_SIZE);
+        write_param.buffer = Msg;
+        write_param.size = strlen(Msg);
+
+        SpiLoraWrite(dev, &write_param);
+    }
+}
+SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN),
+LoraSend, LoraSend,  lora send message );
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/connect_spi.c

@@ -0,0 +1,475 @@
+/*
+ * Copyright (c) 2020 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-18     ZYH          first version
+ */
+
+/**
+* @file connect_spi.c
+* @brief support aiit-riscv64-board spi function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+/*************************************************
+File name: connect_spi.c
+Description: support aiit-riscv64-board spi configure and spi bus register function
+Others: take RT-Thread v4.0.2/bsp/k210/driver/drv_spi.c for references
+                https://github.com/RT-Thread/rt-thread/tree/v4.0.2
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. support aiit-riscv64-board spi configure, write and read
+2. support aiit-riscv64-board spi bus device and driver register
+*************************************************/
+
+#include <connect_spi.h>
+#include <dmac.h>
+#include <drv_io_config.h>
+#include <gpiohs.h>
+#include <hardware_spi.h>
+#include <string.h>
+#include <sysctl.h>
+#include <utils.h>
+
+#ifdef  BSP_SPI1_USING_SS0
+#define SPI_DEVICE_SLAVE_ID_0 0
+#endif
+
+#ifdef BSP_SPI1_USING_SS1
+#define SPI_DEVICE_SLAVE_ID_1 1
+#endif
+
+#ifdef BSP_SPI1_USING_SS2
+#define SPI_DEVICE_SLAVE_ID_2 2
+#endif
+
+#ifdef BSP_SPI1_USING_SS3
+#define SPI_DEVICE_SLAVE_ID_3 3
+#endif
+
+static volatile spi_t *const spi_instance[4] =
+{
+    (volatile spi_t *)SPI0_BASE_ADDR,
+    (volatile spi_t *)SPI1_BASE_ADDR,
+    (volatile spi_t *)SPI_SLAVE_BASE_ADDR,
+    (volatile spi_t *)SPI3_BASE_ADDR
+};
+
+void __spi_set_tmod(uint8_t spi_num, uint32_t tmod)
+{
+    CHECK(spi_num < SPI_DEVICE_MAX);
+    volatile spi_t *spi_handle = spi[spi_num];
+    uint8_t tmod_offset = 0;
+    switch(spi_num)
+    {
+        case 0:
+        case 1:
+        case 2:
+            tmod_offset = 8;
+            break;
+        case 3:
+        default:
+            tmod_offset = 10;
+            break;
+    }
+    set_bit(&spi_handle->ctrlr0, 3 << tmod_offset, tmod << tmod_offset);
+}
+
+/*Init the spi sdk intetface */
+static uint32 SpiSdkInit(struct SpiDriver *spi_drv)
+{
+    NULL_PARAM_CHECK(spi_drv);    
+    uint8 cs_gpio_pin, cs_select_id;
+    uint32 max_frequency;
+
+    SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_drv->driver.private_data);
+
+    cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;
+    cs_select_id = dev_param->spi_slave_param->spi_cs_select_id;
+
+    gpiohs_set_drive_mode(cs_select_id, GPIO_DM_OUTPUT);//Set the cs pin as output
+    gpiohs_set_pin(cs_gpio_pin, GPIO_PV_HIGH);//set the cs gpio high
+
+    spi_init(dev_param->spi_dma_param->spi_master_id, 
+                        dev_param->spi_master_param->spi_work_mode & SPI_MODE_3, 
+                        dev_param->spi_master_param->spi_frame_format, 
+                        dev_param->spi_master_param->spi_data_bit_width,
+                        dev_param->spi_master_param->spi_data_endian);
+
+    max_frequency = (dev_param->spi_master_param->spi_maxfrequency < SPI_MAX_CLOCK) ? dev_param->spi_master_param->spi_maxfrequency : SPI_MAX_CLOCK;
+
+    uint32 real_freq = spi_set_clk_rate(dev_param->spi_dma_param->spi_master_id, max_frequency);
+
+    return EOK;
+}
+
+static uint32 SpiSdkCfg(struct SpiDriver *spi_drv, struct SpiMasterParam *spi_param)
+{
+    NULL_PARAM_CHECK(spi_drv);
+    NULL_PARAM_CHECK(spi_param);  
+
+    SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_drv->driver.private_data);
+
+    dev_param->spi_master_param = spi_param;
+    dev_param->spi_master_param->spi_work_mode = dev_param->spi_master_param->spi_work_mode  & SPI_MODE_MASK;
+    dev_param->spi_master_param->spi_frame_format = SPI_FF_STANDARD;
+
+    return EOK;
+}
+
+/*Configure the spi device param, make sure struct (configure_info->private_data) = (SpiMasterParam)*/
+static uint32 SpiDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+    struct SpiDriver *spi_drv = (struct SpiDriver *)drv;
+    struct SpiMasterParam *spi_param;
+
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_INT:
+            ret = SpiSdkInit(spi_drv);
+            break;
+        case OPE_CFG:
+            spi_param = (struct SpiMasterParam *)configure_info->private_data;
+            ret = SpiSdkCfg(spi_drv, spi_param);
+            break;
+        default:
+            break;
+    }
+
+    return ret;
+}
+
+static uint32 SpiWriteData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg)
+{
+    SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_dev->haldev.private_data);
+
+    uint8 device_id = dev_param->spi_slave_param->spi_slave_id;
+    uint8 device_master_id = dev_param->spi_dma_param->spi_master_id;
+    uint8 cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;
+
+    while (NONE != spi_datacfg)
+    {
+        uint32_t * tx_buff = NONE;
+        int i;
+        x_ubase dummy = 0xFFFFFFFFU;
+
+        __spi_set_tmod(device_master_id, SPI_TMOD_TRANS_RECV);
+
+        if (spi_datacfg->spi_chip_select) {
+            gpiohs_set_pin(cs_gpio_pin, GPIO_PV_LOW);
+        }
+
+        if (spi_datacfg->length) {
+            spi_instance[device_master_id]->dmacr = 0x3;
+            spi_instance[device_master_id]->ssienr = 0x01;
+
+            sysctl_dma_select(dev_param->spi_dma_param->spi_dmac_txchannel, SYSCTL_DMA_SELECT_SSI0_TX_REQ + device_master_id * 2);
+            sysctl_dma_select(dev_param->spi_dma_param->spi_dmac_rxchannel, SYSCTL_DMA_SELECT_SSI0_RX_REQ + device_master_id* 2);
+            
+            dmac_set_single_mode(dev_param->spi_dma_param->spi_dmac_rxchannel, (void *)(&spi_instance[device_master_id]->dr[0]), &dummy, DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE,
+                DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, spi_datacfg->length);
+
+            if (!spi_datacfg->tx_buff) {
+                dmac_set_single_mode(dev_param->spi_dma_param->spi_dmac_txchannel, &dummy, (void *)(&spi_instance[device_master_id]->dr[0]), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE,
+                            DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, spi_datacfg->length);
+            } else {
+                tx_buff = x_malloc(spi_datacfg->length * 4);
+                if (!tx_buff) {
+                    goto transfer_done;
+                }
+                for (i = 0; i < spi_datacfg->length; i++) {
+                    tx_buff[i] = ((uint8_t *)spi_datacfg->tx_buff)[i];
+                }
+                dmac_set_single_mode(dev_param->spi_dma_param->spi_dmac_txchannel, tx_buff, (void *)(&spi_instance[device_master_id]->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
+                            DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, spi_datacfg->length);
+            }
+            
+            spi_instance[device_master_id]->ser = 1U << dev_param->spi_slave_param->spi_cs_select_id;
+            dmac_wait_done(dev_param->spi_dma_param->spi_dmac_txchannel);
+            dmac_wait_done(dev_param->spi_dma_param->spi_dmac_rxchannel);
+            spi_instance[device_master_id]->ser = 0x00;
+            spi_instance[device_master_id]->ssienr = 0x00;
+
+    transfer_done:
+            if (tx_buff) {
+                x_free(tx_buff);
+            }
+        }
+
+        if (spi_datacfg->spi_cs_release) {
+            gpiohs_set_pin(cs_gpio_pin, GPIO_PV_HIGH);
+        }
+
+        spi_datacfg = spi_datacfg->next;
+    }
+
+    return EOK;    
+}
+
+static uint32 SpiReadData(struct SpiHardwareDevice *spi_dev, struct SpiDataStandard *spi_datacfg)
+{
+    SpiDeviceParam *dev_param = (SpiDeviceParam *)(spi_dev->haldev.private_data);
+
+    uint32 spi_read_length = 0;;
+    uint8 device_id = dev_param->spi_slave_param->spi_slave_id;
+    uint8 device_master_id = dev_param->spi_dma_param->spi_master_id;
+    uint8 cs_gpio_pin = dev_param->spi_slave_param->spi_cs_gpio_pin;
+
+    while (NONE != spi_datacfg)
+    {
+        uint32_t * rx_buff = NONE;
+        int i;
+        x_ubase dummy = 0xFFFFFFFFU;
+
+        __spi_set_tmod(device_master_id, SPI_TMOD_TRANS_RECV);
+
+        if (spi_datacfg->spi_chip_select) {
+            gpiohs_set_pin(cs_gpio_pin, GPIO_PV_LOW);
+        }
+        if (spi_datacfg->length) {
+            spi_instance[device_master_id]->dmacr = 0x3;
+            spi_instance[device_master_id]->ssienr = 0x01;
+
+            sysctl_dma_select(dev_param->spi_dma_param->spi_dmac_txchannel, SYSCTL_DMA_SELECT_SSI0_TX_REQ + device_master_id * 2);
+            sysctl_dma_select(dev_param->spi_dma_param->spi_dmac_rxchannel, SYSCTL_DMA_SELECT_SSI0_RX_REQ + device_master_id* 2);
+
+            dmac_set_single_mode(dev_param->spi_dma_param->spi_dmac_txchannel, &dummy, (void *)(&spi_instance[device_master_id]->dr[0]), DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE,
+                DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, spi_datacfg->length);
+
+            if (!spi_datacfg->rx_buff) {
+                dmac_set_single_mode(dev_param->spi_dma_param->spi_dmac_rxchannel, (void *)(&spi_instance[device_master_id]->dr[0]), &dummy, DMAC_ADDR_NOCHANGE, DMAC_ADDR_NOCHANGE,
+                            DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, spi_datacfg->length);
+            } else {
+                rx_buff = x_calloc(spi_datacfg->length * 4, 1);
+                if(!rx_buff)
+                {
+                    goto transfer_done;
+                }
+                
+                dmac_set_single_mode(dev_param->spi_dma_param->spi_dmac_rxchannel, (void *)(&spi_instance[device_master_id]->dr[0]), rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
+                            DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, spi_datacfg->length);
+            }
+            
+            spi_instance[device_master_id]->ser = 1U << dev_param->spi_slave_param->spi_cs_select_id;
+            dmac_wait_done(dev_param->spi_dma_param->spi_dmac_txchannel);
+            dmac_wait_done(dev_param->spi_dma_param->spi_dmac_rxchannel);
+            spi_instance[device_master_id]->ser = 0x00;
+            spi_instance[device_master_id]->ssienr = 0x00;
+
+            if (spi_datacfg->rx_buff) {
+                for (i = 0; i < spi_datacfg->length; i++) {           
+                    ((uint8_t *)spi_datacfg->rx_buff)[i] = (uint8_t)rx_buff[i];
+                }
+            }
+
+    transfer_done:
+            if (rx_buff) {
+                x_free(rx_buff);
+            }
+        }
+
+        if (spi_datacfg->spi_cs_release) {
+            gpiohs_set_pin(cs_gpio_pin, GPIO_PV_HIGH);
+        }
+
+        spi_read_length += spi_datacfg->length;
+        spi_datacfg = spi_datacfg->next;
+    }
+
+    return spi_read_length;    
+}
+
+/*manage the spi device operations*/
+static const struct SpiDevDone spi_dev_done =
+{
+    .dev_open = NONE,
+    .dev_close = NONE,
+    .dev_write = SpiWriteData,
+    .dev_read = SpiReadData,
+};
+
+static int BoardSpiBusInit(struct SpiBus *spi_bus, struct SpiDriver *spi_driver)
+{
+    x_err_t ret = EOK;
+
+    /*Init the spi bus */
+    ret = SpiBusInit(spi_bus, SPI_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("Board_Spi_init SpiBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Init the spi driver*/
+    ret = SpiDriverInit(spi_driver, SPI_1_DRV_NAME);
+    if (EOK != ret) {
+        KPrintf("Board_Spi_init SpiDriverInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Attach the spi driver to the spi bus*/
+    ret = SpiDriverAttachToBus(SPI_1_DRV_NAME, SPI_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("Board_Spi_init SpiDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    } 
+
+    return ret;
+}
+
+/*Attach the spi device to the spi bus*/
+static int BoardSpiDevBend(struct SpiDmaParam *spi_initparam)
+{
+    x_err_t ret = EOK;
+
+#ifdef BSP_SPI1_USING_SS0
+    static struct SpiHardwareDevice spi_device0;
+    memset(&spi_device0, 0, sizeof(struct SpiHardwareDevice));
+
+    static struct SpiSlaveParam spi_slaveparam0;
+    memset(&spi_slaveparam0, 0, sizeof(struct SpiSlaveParam));
+
+    spi_slaveparam0.spi_slave_id = SPI_DEVICE_SLAVE_ID_0;
+    spi_slaveparam0.spi_cs_gpio_pin = SPI1_CS0_PIN;
+    spi_slaveparam0.spi_cs_select_id = SPI_CHIP_SELECT_0;
+
+    spi_device0.spi_param.spi_dma_param = spi_initparam;
+    spi_device0.spi_param.spi_slave_param = &spi_slaveparam0;
+
+    spi_device0.spi_dev_done = &(spi_dev_done);
+
+    ret = SpiDeviceRegister(&spi_device0, (void *)(&spi_device0.spi_param), SPI_1_DEVICE_NAME_0);
+    if (EOK != ret) {
+        KPrintf("Board_Spi_init SpiDeviceInit device %s error %d\n", SPI_1_DEVICE_NAME_0, ret);
+        return ERROR;
+    }  
+
+    ret = SpiDeviceAttachToBus(SPI_1_DEVICE_NAME_0, SPI_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("Board_Spi_init SpiDeviceAttachToBus device %s error %d\n", SPI_1_DEVICE_NAME_0, ret);
+        return ERROR;
+    }  
+#endif
+
+#ifdef BSP_SPI1_USING_SS1
+    static struct SpiHardwareDevice spi_device1;
+    memset(&spi_device1, 0, sizeof(struct SpiHardwareDevice));
+
+    static struct SpiSlaveParam spi_slaveparam1;
+    memset(&spi_slaveparam1, 0, sizeof(struct SpiSlaveParam));
+
+    spi_slaveparam1.spi_slave_id = SPI_DEVICE_SLAVE_ID_1;
+    spi_slaveparam1.spi_cs_gpio_pin = SPI1_CS1_PIN;
+    spi_slaveparam1.spi_cs_select_id = SPI_CHIP_SELECT_1;
+
+    spi_device1.spi_param.spi_dma_param = spi_initparam;
+    spi_device1.spi_param.spi_slave_param = &spi_slaveparam1;    
+    
+    spi_device1.spi_dev_done = &(spi_dev_done);
+
+    ret = SpiDeviceRegister(&spi_device1, (void *)(&spi_device1.spi_param), SPI_1_DEVICE_NAME_1);
+    if (EOK != ret) {
+        KPrintf("Board_Spi_init SpiDeviceInit device %s error %d\n", SPI_1_DEVICE_NAME_1, ret);
+        return ERROR;
+    } 
+
+    ret = SpiDeviceAttachToBus(SPI_1_DEVICE_NAME_1, SPI_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("Board_Spi_init SpiDeviceAttachToBus device %s error %d\n", SPI_1_DEVICE_NAME_1, ret);
+        return ERROR;
+    }  
+#endif
+
+#ifdef BSP_SPI1_USING_SS2
+    static struct SpiHardwareDevice spi_device2;
+    memset(&spi_device2, 0, sizeof(struct SpiHardwareDevice));
+
+    spi_initparam->spi_slave_id[SPI_DEVICE_SLAVE_ID_2] = SPI_DEVICE_SLAVE_ID_2;
+    spi_initparam->spi_cs_gpio_pin[SPI_DEVICE_SLAVE_ID_2] = SPI1_CS2_PIN;
+    spi_initparam->spi_cs_select_id[SPI_DEVICE_SLAVE_ID_2] = SPI_CHIP_SELECT_2;
+
+    spi_device2.spi_dev_done = &(spi_dev_done);
+
+    ret = SpiDeviceRegister(&spi_device2, (void *)(&spi_device2.spi_param), SPI_1_DEVICE_NAME_2);
+    if (EOK != ret) {
+        KPrintf("Board_Spi_init SpiDeviceInit device %s error %d\n", SPI_1_DEVICE_NAME_2, ret);
+        return ERROR;
+    } 
+
+    ret = SpiDeviceAttachToBus(SPI_1_DEVICE_NAME_2, SPI_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("Board_Spi_init SpiDeviceAttachToBus device %s error %d\n", SPI_1_DEVICE_NAME_2, ret);
+        return ERROR;
+    }  
+#endif
+
+#ifdef BSP_SPI1_USING_SS3
+    static struct SpiHardwareDevice spi_device3;
+    memset(&spi_device3, 0, sizeof(struct SpiHardwareDevice));
+
+    spi_initparam->spi_slave_id[SPI_DEVICE_SLAVE_ID_3] = SPI_DEVICE_SLAVE_ID_3;
+    spi_initparam->spi_cs_gpio_pin[SPI_DEVICE_SLAVE_ID_3] = SPI1_CS3_PIN;
+    spi_initparam->spi_cs_select_id[SPI_DEVICE_SLAVE_ID_3] = SPI_CHIP_SELECT_3;
+
+    spi_device3.spi_dev_done = &(spi_dev_done);
+
+    ret = SpiDeviceRegister(&spi_device3, (void *)(&spi_device3.spi_param), SPI_1_DEVICE_NAME_3);
+    if (EOK != ret) {
+        KPrintf("Board_Spi_init SpiDeviceInit device %s error %d\n", SPI_1_DEVICE_NAME_3, ret);
+        return ERROR;
+    } 
+
+    ret = SpiDeviceAttachToBus(SPI_1_DEVICE_NAME_3, SPI_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("Board_Spi_init SpiDeviceAttachToBus device %s error %d\n", SPI_1_DEVICE_NAME_3, ret);
+        return ERROR;
+    }  
+#endif
+    return  ret;
+}
+
+/*RISC-V 64 BOARD SPI INIT*/
+int HwSpiInit(void)
+{
+    x_err_t ret = EOK;
+    static struct SpiDmaParam spi_initparam;
+    memset(&spi_initparam, 0, sizeof(struct SpiDmaParam));
+
+#ifdef  BSP_USING_SPI1
+
+    static struct SpiBus spi_bus;
+    memset(&spi_bus, 0, sizeof(struct SpiBus));
+
+    static struct SpiDriver spi_driver;
+    memset(&spi_driver, 0, sizeof(struct SpiDriver));
+
+    spi_initparam.spi_master_id = SPI_DEVICE_1;
+    spi_initparam.spi_dmac_txchannel = DMAC_CHANNEL1;
+    spi_initparam.spi_dmac_rxchannel = DMAC_CHANNEL2;
+    
+    spi_driver.configure = &(SpiDrvConfigure);
+
+    ret = BoardSpiBusInit(&spi_bus, &spi_driver);
+    if (EOK != ret) {
+        KPrintf("Board_Spi_Init error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSpiDevBend(&spi_initparam);
+    if (EOK != ret) {
+        KPrintf("Board_Spi_Init error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+    return ret;
+}

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/Makefile

@@ -0,0 +1,7 @@
+SRC_DIR +=  src
+
+ifeq ($(ARCH), arm)
+	SRC_DIR += ports
+endif
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/inc/spi_lora_sx12xx.h

@@ -0,0 +1,95 @@
+/*
+ * Original Copyright (c) 2006-2018, RT-Thread Development Team
+ * Modified Copyright (c) 2020 AIIT XUOS Lab
+ * 
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+
+ * http://www.apache.org/licenses/LICENSE-2.0
+
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-02-25     XiaojieFan     the first version
+ */
+
+/* 
+ * Modified by:     AIIT XUOS Lab
+ * Modified date:   2020-09-01
+ * Description:     
+ */
+/*************************************************
+File name: spi_lora_sx12xx.h
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+
+#ifndef __SPI_LORA_SX12XX_H_
+#define __SPI_LORA_SX12XX_H_
+
+#include <xizi.h>
+#include <stdbool.h>
+
+/*!
+ * \brief Gets the SX1272 DIO0 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+uint8_t SX1276ReadDio0(void);
+
+/*!
+ * \brief Gets the SX1272 DIO1 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+uint8_t SX1276ReadDio1(void);
+
+/*!
+ * \brief Gets the SX1272 DIO2 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+uint8_t SX1276ReadDio2(void);
+
+/*!
+ * \brief Gets the SX1272 DIO3 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+uint8_t SX1276ReadDio3(void);
+
+/*!
+ * \brief Gets the SX1272 DIO4 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+uint8_t SX1276ReadDio4(void);
+
+/*!
+ * \brief Gets the SX1272 DIO5 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+uint8_t SX1276ReadDio5(void);
+
+void SX1276Write(uint8_t addr, uint8_t data);
+void SX1276Read(uint8_t addr, uint8_t *data);
+void SX1276WriteBuffer(uint8_t addr, uint8_t *buffer, uint8_t size);
+void SX1276ReadBuffer(uint8_t addr, uint8_t *buffer, uint8_t size);
+void SX1276WriteFifo(uint8_t *buffer, uint8_t size);
+void SX1276ReadFifo(uint8_t *buffer, uint8_t size);
+void SX1276SetReset(uint8_t state);
+uint8_t SX1276_Spi_Check(void);
+void SX1276WriteRxTx(uint8_t txEnable);
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/ports/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := sx12xx_device.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/ports/sx12xx_device.c

@@ -0,0 +1,38 @@
+/*
+ * Original Copyright (c) 2006-2018, RT-Thread Development Team
+ * Modified Copyright (c) 2020 AIIT XUOS Lab
+ * 
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+
+ * http://www.apache.org/licenses/LICENSE-2.0
+
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-02-20     XiaojieFan     the first version
+ */
+
+/*************************************************
+File name: sx12xx_device.c
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+#include "connect_spi.h"
+#include "board.h"
+// #include "gpio.h"
+#include "stm32f4xx.h"
+#include "hardware_gpio.h"
+
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/Makefile

@@ -0,0 +1,10 @@
+
+SRC_FILES += radio/radio.c \
+	radio/sx1276-Fsk.c \
+	radio/sx1276-FskMisc.c \
+	radio/sx1276-LoRa.c \
+	radio/sx1276-LoRaMisc.c \
+	radio/sx1276.c
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/radio/platform.h

@@ -0,0 +1,97 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       platform.h
+ * \brief        
+ *
+ * \version    1.0
+ * \date       Nov 21 2012
+ * \author     Miguel Luis
+ */
+/*************************************************
+File name: platform.h
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+#ifndef __PLATFORM_H__
+#define __PLATFORM_H__
+
+#ifndef __GNUC__
+#define inline
+#endif
+
+/*!
+ * Platform definition
+ */
+#define Bleeper                                     3
+#define SX1243ska                                   2
+#define SX12xxEiger                                 1
+#define SX12000DVK                                  0
+
+/*!
+ * Platform choice. Please uncoment the PLATFORM define and choose your platform
+ * or add/change the PLATFORM definition on the compiler Defines option
+ */
+#define PLATFORM                                    SX12xxEiger
+
+#if( PLATFORM == SX12xxEiger )
+/*!
+ * Radio choice. Please uncomment the wanted radio and comment the others
+ * or add/change wanted radio definition on the compiler Defines option
+ */
+//#define USE_SX1232_RADIO
+//#define USE_SX1272_RADIO
+#define USE_SX1276_RADIO
+//#define USE_SX1243_RADIO
+
+/*!
+ * Module choice. There are three existing module with the SX1276.
+ * Please set the connected module to the value 1 and set the others to 0
+ */
+#ifdef USE_SX1276_RADIO
+#define MODULE_SX1276RF1IAS                         0
+#define MODULE_SX1276RF1JAS                         0
+#define MODULE_SX1276RF1KAS                         1
+#endif
+
+    //#include "sx12xxEiger/sx12xxEiger.h"
+		#include "spi_lora_sx12xx.h"
+    #define USE_UART                                0
+
+#elif( PLATFORM == SX12000DVK )
+/*!
+ * Radio choice. Please uncomment the wanted radio and comment the others
+ * or add/change wanted radio definition on the compiler Defines option
+ */
+//#define USE_SX1232_RADIO
+#define USE_SX1272_RADIO
+//#define USE_SX1276_RADIO
+//#define USE_SX1243_RADIO
+
+    #include "sx1200dvk/sx1200dvk.h"
+
+#elif( PLATFORM == SX1243ska )
+
+#elif( PLATFORM == Bleeper )
+    #define USE_SX1272_RADIO
+    
+    #include "bleeper/bleeper.h"
+    #define USE_UART                                0
+
+#else
+    #error "Missing define: Platform (ie. SX12xxEiger)"
+#endif
+
+#endif // __PLATFORM_H__

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/radio/radio.c

@@ -0,0 +1,75 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       radio.c
+ * \brief      Generic radio driver ( radio abstraction )
+ *
+ * \version    2.0.0 
+ * \date       Nov 21 2012
+ * \author     Miguel Luis
+ *
+ * Last modified by Gregory Cristian on Apr 25 2013
+ */
+/*************************************************
+File name: radio.c
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+#include <stdint.h>
+#include "platform.h"
+#include "radio.h"
+
+#if defined( USE_SX1232_RADIO )
+    #include "sx1232.h"
+#elif defined( USE_SX1272_RADIO )
+    #include "sx1272.h"
+#elif defined( USE_SX1276_RADIO )
+    #include "sx1276.h"
+#else
+    #error "Missing define: USE_XXXXXX_RADIO (ie. USE_SX1272_RADIO)"
+#endif    
+
+tRadioDriver RadioDriver;
+
+tRadioDriver* RadioDriverInit( void )
+{
+#if defined( USE_SX1232_RADIO )
+    RadioDriver.Init = SX1232Init;
+    RadioDriver.Reset = SX1232Reset;
+    RadioDriver.StartRx = SX1232StartRx;
+    RadioDriver.GetRxPacket = SX1232GetRxPacket;
+    RadioDriver.SetTxPacket = SX1232SetTxPacket;
+    RadioDriver.Process = SX1232Process;
+#elif defined( USE_SX1272_RADIO )
+    RadioDriver.Init = SX1272Init;
+    RadioDriver.Reset = SX1272Reset;
+    RadioDriver.StartRx = SX1272StartRx;
+    RadioDriver.GetRxPacket = SX1272GetRxPacket;
+    RadioDriver.SetTxPacket = SX1272SetTxPacket;
+    RadioDriver.Process = SX1272Process;
+#elif defined( USE_SX1276_RADIO )
+    RadioDriver.Init = SX1276Init;
+    RadioDriver.Reset = SX1276Reset;
+    RadioDriver.StartRx = SX1276StartRx;
+    RadioDriver.GetRxPacket = SX1276GetRxPacket;
+    RadioDriver.SetTxPacket = SX1276SetTxPacket;
+    RadioDriver.Process = SX1276Process;
+    RadioDriver.ChannelEmpty = SX1276ChannelEmpty;
+#else
+    #error "Missing define: USE_XXXXXX_RADIO (ie. USE_SX1272_RADIO)"
+#endif    
+
+    return &RadioDriver;
+}

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/radio/radio.h

@@ -0,0 +1,77 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       radio.h
+ * \brief      Generic radio driver ( radio abstraction )
+ *
+ * \version    2.0.B2 
+ * \date       Nov 21 2012
+ * \author     Miguel Luis
+ *
+ * Last modified by Gregory Cristian on Apr 25 2013
+ */
+/*************************************************
+File name: radio.h
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+#ifndef __RADIO_H__
+#define __RADIO_H__
+
+/*!
+ * SX1272 and SX1276 General parameters definition
+ */
+#define LORA                                        1         // [0: OFF, 1: ON]
+
+/*!
+ * RF process function return codes
+ */
+typedef enum
+{
+    RF_IDLE,
+    RF_BUSY,
+    RF_RX_DONE,
+    RF_RX_TIMEOUT,
+    RF_TX_DONE,
+    RF_TX_TIMEOUT,
+    RF_LEN_ERROR,
+    RF_CHANNEL_EMPTY,
+    RF_CHANNEL_ACTIVITY_DETECTED,
+}tRFProcessReturnCodes;
+
+/*!
+ * Radio driver structure defining the different function pointers
+ */
+typedef struct sRadioDriver
+{
+    void ( *Init )( void );
+    void ( *Reset )( void );
+    void ( *StartRx )( void );
+    void ( *GetRxPacket )( void *buffer, uint16_t *size );
+    void ( *SetTxPacket )( const void *buffer, uint16_t size );
+    uint32_t ( *Process )( void );
+    uint32_t ( *ChannelEmpty )(void );
+}tRadioDriver;
+
+/*!
+ * \brief Initializes the RadioDriver structure with specific radio
+ *        functions.
+ *
+ * \retval radioDriver Pointer to the radio driver variable
+ */
+tRadioDriver* RadioDriverInit( void );
+
+#endif // __RADIO_H__

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276-Fsk.c

@@ -0,0 +1,616 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       sx1276.c
+ * \brief      SX1276 RF chip driver
+ *
+ * \version    2.0.0 
+ * \date       May 6 2013
+ * \author     Gregory Cristian
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276-Fsk.c
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+#include <string.h>
+#include <math.h>
+
+#include "platform.h"
+
+#if defined( USE_SX1276_RADIO )
+
+#include "radio.h"
+
+#include "sx1276-Hal.h"
+#include "sx1276.h"
+
+#include "sx1276-FskMisc.h"
+#include "sx1276-Fsk.h"
+
+// Default settings
+tFskSettings FskSettings = 
+{
+    870000000,      // RFFrequency
+    9600,           // Bitrate
+    50000,          // Fdev
+    20,             // Power
+    100000,         // RxBw
+    150000,         // RxBwAfc
+    true,           // CrcOn
+    true,           // AfcOn    
+    255             // PayloadLength (set payload size to the maximum for variable mode, else set the exact payload length)
+};
+
+/*!
+ * SX1276 FSK registers variable
+ */
+tSX1276* SX1276;
+
+/*!
+ * Local RF buffer for communication support
+ */
+static uint8_t RFBuffer[RF_BUFFER_SIZE];
+
+/*!
+ * Chunk size of data write in buffer 
+ */
+static uint8_t DataChunkSize = 32;
+
+
+/*!
+ * RF state machine variable
+ */
+static uint8_t RFState = RF_STATE_IDLE;
+
+/*!
+ * Rx management support variables
+ */
+
+/*!
+ * PacketTimeout holds the RF packet timeout
+ * SyncSize = [0..8]
+ * VariableSize = [0;1]
+ * AddressSize = [0;1]
+ * PayloadSize = [0..RF_BUFFER_SIZE]
+ * CrcSize = [0;2]
+ * PacketTimeout = ( ( 8 * ( VariableSize + AddressSize + PayloadSize + CrcSize ) / BR ) * 1000.0 ) + 1
+ * Computed timeout is in miliseconds
+ */
+static uint32_t PacketTimeout;
+
+/*!
+ * Preamble2SyncTimeout
+ * Preamble2SyncTimeout = ( ( 8 * ( PremableSize + SyncSize ) / RFBitrate ) * 1000.0 ) + 1
+ * Computed timeout is in miliseconds
+ */
+static uint32_t Preamble2SyncTimeout;
+
+static bool PreambleDetected = false;
+static bool SyncWordDetected = false;
+static bool PacketDetected = false;
+static uint16_t RxPacketSize = 0;
+static uint8_t RxBytesRead = 0;
+static uint8_t TxBytesSent = 0;
+static double RxPacketRssiValue;
+static uint32_t RxPacketAfcValue;
+static uint8_t RxGain = 1;
+static uint32_t RxTimeoutTimer = 0;
+static uint32_t Preamble2SyncTimer = 0;
+
+/*!
+ * Tx management support variables
+ */
+static uint16_t TxPacketSize = 0;
+static uint32_t TxTimeoutTimer = 0;
+
+void SX1276FskInit( void )
+{
+    RFState = RF_STATE_IDLE;
+
+    SX1276FskSetDefaults( );
+    
+    SX1276ReadBuffer( REG_OPMODE, SX1276Regs + 1, 0x70 - 1 );
+
+    // Set the device in FSK mode and Sleep Mode
+    SX1276->RegOpMode = RF_OPMODE_MODULATIONTYPE_FSK | RF_OPMODE_SLEEP;
+    SX1276Write( REG_OPMODE, SX1276->RegOpMode );
+
+    SX1276->RegPaRamp = RF_PARAMP_MODULATIONSHAPING_01;
+    SX1276Write( REG_PARAMP, SX1276->RegPaRamp );
+
+    SX1276->RegLna = RF_LNA_GAIN_G1;
+    SX1276Write( REG_LNA, SX1276->RegLna );
+
+    if( FskSettings.AfcOn == true )
+    {
+        SX1276->RegRxConfig = RF_RXCONFIG_RESTARTRXONCOLLISION_OFF | RF_RXCONFIG_AFCAUTO_ON |
+                              RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT;
+    }
+    else
+    {
+        SX1276->RegRxConfig = RF_RXCONFIG_RESTARTRXONCOLLISION_OFF | RF_RXCONFIG_AFCAUTO_OFF |
+                              RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT;
+    }
+
+    SX1276->RegPreambleLsb = 8;
+    
+    SX1276->RegPreambleDetect = RF_PREAMBLEDETECT_DETECTOR_ON | RF_PREAMBLEDETECT_DETECTORSIZE_2 |
+                                RF_PREAMBLEDETECT_DETECTORTOL_10;
+
+    SX1276->RegRssiThresh = 0xFF;
+
+    SX1276->RegSyncConfig = RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_ON | RF_SYNCCONFIG_PREAMBLEPOLARITY_AA |
+                            RF_SYNCCONFIG_SYNC_ON |
+                            RF_SYNCCONFIG_SYNCSIZE_4;
+
+    SX1276->RegSyncValue1 = 0x69;
+    SX1276->RegSyncValue2 = 0x81;
+    SX1276->RegSyncValue3 = 0x7E;
+    SX1276->RegSyncValue4 = 0x96;
+
+    SX1276->RegPacketConfig1 = RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE | RF_PACKETCONFIG1_DCFREE_OFF |
+                               ( FskSettings.CrcOn << 4 ) | RF_PACKETCONFIG1_CRCAUTOCLEAR_ON |
+                               RF_PACKETCONFIG1_ADDRSFILTERING_OFF | RF_PACKETCONFIG1_CRCWHITENINGTYPE_CCITT;
+    SX1276FskGetPacketCrcOn( ); // Update CrcOn on FskSettings
+
+    SX1276->RegPayloadLength = FskSettings.PayloadLength;
+
+    // we can now update the registers with our configuration
+    SX1276WriteBuffer( REG_OPMODE, SX1276Regs + 1, 0x70 - 1 );
+
+    // then we need to set the RF settings 
+    SX1276FskSetRFFrequency( FskSettings.RFFrequency );
+    SX1276FskSetBitrate( FskSettings.Bitrate );
+    SX1276FskSetFdev( FskSettings.Fdev );
+
+    SX1276FskSetDccBw( &SX1276->RegRxBw, 0, FskSettings.RxBw );
+    SX1276FskSetDccBw( &SX1276->RegAfcBw, 0, FskSettings.RxBwAfc );
+    SX1276FskSetRssiOffset( 0 );
+
+#if( ( MODULE_SX1276RF1IAS == 1 ) || ( MODULE_SX1276RF1KAS == 1 ) )
+    if( FskSettings.RFFrequency > 860000000 )
+    {
+        SX1276FskSetPAOutput( RF_PACONFIG_PASELECT_RFO );
+        SX1276FskSetPa20dBm( false );
+        FskSettings.Power = 14;
+        SX1276FskSetRFPower( FskSettings.Power );
+    }
+    else
+    {
+        SX1276FskSetPAOutput( RF_PACONFIG_PASELECT_PABOOST );
+        SX1276FskSetPa20dBm( true );
+        FskSettings.Power = 20;
+        SX1276FskSetRFPower( FskSettings.Power );
+    } 
+#elif( MODULE_SX1276RF1JAS == 1 )
+    if( FskSettings.RFFrequency > 860000000 )
+    {
+        SX1276FskSetPAOutput( RF_PACONFIG_PASELECT_PABOOST );
+        SX1276FskSetPa20dBm( true );
+        FskSettings.Power = 20;
+        SX1276FskSetRFPower( FskSettings.Power );
+    }
+    else
+    {
+        SX1276FskSetPAOutput( RF_PACONFIG_PASELECT_RFO );
+        SX1276FskSetPa20dBm( false );
+        FskSettings.Power = 14;
+        SX1276FskSetRFPower( FskSettings.Power );
+    } 
+#endif
+
+    SX1276FskSetOpMode( RF_OPMODE_STANDBY );
+
+    // Calibrate the HF
+    SX1276FskRxCalibrate( );
+}
+
+void SX1276FskSetDefaults( void )
+{
+    // REMARK: See SX1276 datasheet for modified default values.
+
+    SX1276Read( REG_VERSION, &SX1276->RegVersion );
+}
+
+void SX1276FskSetOpMode( uint8_t opMode )
+{
+    static uint8_t opModePrev = RF_OPMODE_STANDBY;
+    static bool antennaSwitchTxOnPrev = true;
+    bool antennaSwitchTxOn = false;
+
+    opModePrev = SX1276->RegOpMode & ~RF_OPMODE_MASK;
+
+    if( opMode != opModePrev )
+    {
+        if( opMode == RF_OPMODE_TRANSMITTER )
+        {
+            antennaSwitchTxOn = true;
+        }
+        else
+        {
+            antennaSwitchTxOn = false;
+        }
+        if( antennaSwitchTxOn != antennaSwitchTxOnPrev )
+        {
+            antennaSwitchTxOnPrev = antennaSwitchTxOn;
+            RXTX( antennaSwitchTxOn ); // Antenna switch control
+        }
+        SX1276->RegOpMode = ( SX1276->RegOpMode & RF_OPMODE_MASK ) | opMode;
+
+        SX1276Write( REG_OPMODE, SX1276->RegOpMode );        
+    }
+}
+
+uint8_t SX1276FskGetOpMode( void )
+{
+    SX1276Read( REG_OPMODE, &SX1276->RegOpMode );
+    
+    return SX1276->RegOpMode & ~RF_OPMODE_MASK;
+}
+
+int32_t SX1276FskReadFei( void )
+{
+    SX1276ReadBuffer( REG_FEIMSB, &SX1276->RegFeiMsb, 2 );                          // Reads the FEI value
+
+    return ( int32_t )( double )( ( ( uint16_t )SX1276->RegFeiMsb << 8 ) | ( uint16_t )SX1276->RegFeiLsb ) * ( double )FREQ_STEP;
+}
+
+int32_t SX1276FskReadAfc( void )
+{
+    SX1276ReadBuffer( REG_AFCMSB, &SX1276->RegAfcMsb, 2 );                            // Reads the AFC value
+    return ( int32_t )( double )( ( ( uint16_t )SX1276->RegAfcMsb << 8 ) | ( uint16_t )SX1276->RegAfcLsb ) * ( double )FREQ_STEP;
+}
+
+uint8_t SX1276FskReadRxGain( void )
+{
+    SX1276Read( REG_LNA, &SX1276->RegLna );
+    return( SX1276->RegLna >> 5 ) & 0x07;
+}
+
+double SX1276FskReadRssi( void )
+{
+    SX1276Read( REG_RSSIVALUE, &SX1276->RegRssiValue );                               // Reads the RSSI value
+
+    return -( double )( ( double )SX1276->RegRssiValue / 2.0 );
+}
+
+uint8_t SX1276FskGetPacketRxGain( void )
+{
+    return RxGain;
+}
+
+double SX1276FskGetPacketRssi( void )
+{
+    return RxPacketRssiValue;
+}
+
+uint32_t SX1276FskGetPacketAfc( void )
+{
+    return RxPacketAfcValue;
+}
+
+void SX1276FskStartRx( void )
+{
+    SX1276FskSetRFState( RF_STATE_RX_INIT );
+}
+
+void SX1276FskGetRxPacket( void *buffer, uint16_t *size )
+{
+    *size = RxPacketSize;
+    RxPacketSize = 0;
+    memcpy( ( void * )buffer, ( void * )RFBuffer, ( size_t )*size );
+}
+
+void SX1276FskSetTxPacket( const void *buffer, uint16_t size )
+{
+    TxPacketSize = size;
+    memcpy( ( void * )RFBuffer, buffer, ( size_t )TxPacketSize ); 
+
+    RFState = RF_STATE_TX_INIT;
+}
+
+// Remark: SX1276 must be fully initialized before calling this function
+uint16_t SX1276FskGetPacketPayloadSize( void )
+{
+    uint16_t syncSize;
+    uint16_t variableSize;
+    uint16_t addressSize;
+    uint16_t payloadSize;
+    uint16_t crcSize;
+
+    syncSize = ( SX1276->RegSyncConfig & 0x07 ) + 1;
+    variableSize = ( ( SX1276->RegPacketConfig1 & 0x80 ) == 0x80 ) ? 1 : 0;
+    addressSize = ( ( SX1276->RegPacketConfig1 & 0x06 ) != 0x00 ) ? 1 : 0;
+    payloadSize = SX1276->RegPayloadLength;
+    crcSize = ( ( SX1276->RegPacketConfig1 & 0x10 ) == 0x10 ) ? 2 : 0;
+    
+    return syncSize + variableSize + addressSize + payloadSize + crcSize;
+}
+
+// Remark: SX1276 must be fully initialized before calling this function
+uint16_t SX1276FskGetPacketHeaderSize( void )
+{
+    uint16_t preambleSize;
+    uint16_t syncSize;
+
+    preambleSize = ( ( uint16_t )SX1276->RegPreambleMsb << 8 ) | ( uint16_t )SX1276->RegPreambleLsb;
+    syncSize = ( SX1276->RegSyncConfig & 0x07 ) + 1;
+    
+    return preambleSize + syncSize;
+}
+
+uint8_t SX1276FskGetRFState( void )
+{
+    return RFState;
+}
+
+void SX1276FskSetRFState( uint8_t state )
+{
+    RFState = state;
+}
+
+uint32_t SX1276FskProcess( void )
+{
+    uint32_t result = RF_BUSY;
+
+    switch( RFState )
+    {
+    case RF_STATE_IDLE:
+        break;
+    // Rx management
+    case RF_STATE_RX_INIT:
+        // DIO mapping setup
+        if( ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_CRC_ON ) == RF_PACKETCONFIG1_CRC_ON )
+        {
+            //                           CrcOk,                   FifoLevel,               SyncAddr,               FifoEmpty
+            SX1276->RegDioMapping1 = RF_DIOMAPPING1_DIO0_01 | RF_DIOMAPPING1_DIO1_00 | RF_DIOMAPPING1_DIO2_11 | RF_DIOMAPPING1_DIO3_00;
+        }
+        else
+        {
+            //                           PayloadReady,            FifoLevel,               SyncAddr,               FifoEmpty
+            SX1276->RegDioMapping1 = RF_DIOMAPPING1_DIO0_00 | RF_DIOMAPPING1_DIO1_00 | RF_DIOMAPPING1_DIO2_11 | RF_DIOMAPPING1_DIO3_00;
+        }
+        //                          Preamble,                   Data
+        SX1276->RegDioMapping2 = RF_DIOMAPPING2_DIO4_11 | RF_DIOMAPPING2_DIO5_10 | RF_DIOMAPPING2_MAP_PREAMBLEDETECT;
+        SX1276WriteBuffer( REG_DIOMAPPING1, &SX1276->RegDioMapping1, 2 );
+
+        SX1276FskSetOpMode( RF_OPMODE_RECEIVER );
+    
+        memset( RFBuffer, 0, ( size_t )RF_BUFFER_SIZE );
+
+        PacketTimeout = ( uint16_t )( round( ( 8.0 * ( ( double )SX1276FskGetPacketPayloadSize( ) ) / ( double )FskSettings.Bitrate ) * 1000.0 ) + 1.0 );
+        PacketTimeout = PacketTimeout + ( PacketTimeout >> 1 ); // Set the Packet timeout as 1.5 times the full payload transmission time
+
+        Preamble2SyncTimeout = PacketTimeout;
+
+        Preamble2SyncTimer = RxTimeoutTimer = GET_TICK_COUNT( );
+
+        SX1276->RegFifoThresh = RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY | 0x20; // 32 bytes of data
+        SX1276Write( REG_FIFOTHRESH, SX1276->RegFifoThresh );
+
+        PreambleDetected = false;
+        SyncWordDetected = false;
+        PacketDetected = false;
+        RxBytesRead = 0;
+        RxPacketSize = 0;
+        RFState = RF_STATE_RX_SYNC;
+        break;
+    case RF_STATE_RX_SYNC:
+        if( ( DIO4 == 1 ) && ( PreambleDetected == false ) )// Preamble
+        {
+            PreambleDetected = true;
+            Preamble2SyncTimer = GET_TICK_COUNT( );
+        }
+        if( ( DIO2 == 1 ) && ( PreambleDetected == true ) && ( SyncWordDetected == false ) ) // SyncAddr
+        {
+            SyncWordDetected = true;
+        
+            RxPacketRssiValue = SX1276FskReadRssi( );
+
+            RxPacketAfcValue = SX1276FskReadAfc( );
+            RxGain = SX1276FskReadRxGain( );
+        
+            Preamble2SyncTimer = RxTimeoutTimer = GET_TICK_COUNT( );
+
+            RFState = RF_STATE_RX_RUNNING;
+        }
+
+        // Preamble 2 SyncAddr timeout
+        if( ( SyncWordDetected == false ) && ( PreambleDetected == true ) && ( ( GET_TICK_COUNT( ) - Preamble2SyncTimer ) > Preamble2SyncTimeout ) )
+        {
+            RFState = RF_STATE_RX_INIT;
+            SX1276Write( REG_RXCONFIG, SX1276->RegRxConfig | RF_RXCONFIG_RESTARTRXWITHPLLLOCK );
+        }
+        if( ( SyncWordDetected == false ) &&
+            ( PreambleDetected == false ) &&
+            ( PacketDetected == false ) &&
+            ( ( GET_TICK_COUNT( ) - RxTimeoutTimer ) > PacketTimeout ) )
+        {
+            RFState = RF_STATE_RX_TIMEOUT;
+        }
+        break;
+    case RF_STATE_RX_RUNNING:
+        if( RxPacketSize > RF_BUFFER_SIZE_MAX )
+        {
+            RFState = RF_STATE_RX_LEN_ERROR;
+            break;
+        }
+#if 1
+        if( DIO1 == 1 ) // FifoLevel
+        {
+            if( ( RxPacketSize == 0 ) && ( RxBytesRead == 0 ) ) // Read received packet size
+            {
+                if( ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) == RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE )
+                {
+                    SX1276ReadFifo( ( uint8_t* )&RxPacketSize, 1 );
+                }
+                else
+                {
+                    RxPacketSize = SX1276->RegPayloadLength;
+                }
+            }
+
+            if( ( RxPacketSize - RxBytesRead ) > ( SX1276->RegFifoThresh & 0x3F ) )
+            {
+                SX1276ReadFifo( ( RFBuffer + RxBytesRead ), ( SX1276->RegFifoThresh & 0x3F ) );
+                RxBytesRead += ( SX1276->RegFifoThresh & 0x3F );
+            }
+            else
+            {
+                SX1276ReadFifo( ( RFBuffer + RxBytesRead ), RxPacketSize - RxBytesRead );
+                RxBytesRead += ( RxPacketSize - RxBytesRead );
+            }
+        }
+#endif
+        if( DIO0 == 1 ) // PayloadReady/CrcOk
+        {
+            RxTimeoutTimer = GET_TICK_COUNT( );
+            if( ( RxPacketSize == 0 ) && ( RxBytesRead == 0 ) ) // Read received packet size
+            {
+                if( ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) == RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE )
+                {
+                    SX1276ReadFifo( ( uint8_t* )&RxPacketSize, 1 );
+                }
+                else
+                {
+                    RxPacketSize = SX1276->RegPayloadLength;
+                }
+                SX1276ReadFifo( RFBuffer + RxBytesRead, RxPacketSize - RxBytesRead );
+                RxBytesRead += ( RxPacketSize - RxBytesRead );
+                PacketDetected = true;
+                RFState = RF_STATE_RX_DONE;
+            }
+            else
+            {
+                SX1276ReadFifo( RFBuffer + RxBytesRead, RxPacketSize - RxBytesRead );
+                RxBytesRead += ( RxPacketSize - RxBytesRead );
+                PacketDetected = true;
+                RFState = RF_STATE_RX_DONE;
+            }
+        }
+        
+        // Packet timeout
+        if( ( PacketDetected == false ) && ( ( GET_TICK_COUNT( ) - RxTimeoutTimer ) > PacketTimeout ) )
+        {
+            RFState = RF_STATE_RX_TIMEOUT;
+        }
+        break;
+    case RF_STATE_RX_DONE:
+        RxBytesRead = 0;
+        RFState = RF_STATE_RX_INIT;
+        result = RF_RX_DONE;
+        break;
+    case RF_STATE_RX_TIMEOUT:
+        RxBytesRead = 0;
+        RxPacketSize = 0;
+        SX1276Write( REG_RXCONFIG, SX1276->RegRxConfig | RF_RXCONFIG_RESTARTRXWITHPLLLOCK );
+        RFState = RF_STATE_RX_INIT;
+        result = RF_RX_TIMEOUT;
+        break;
+    case RF_STATE_RX_LEN_ERROR:
+        RxBytesRead = 0;
+        RxPacketSize = 0;
+        SX1276Write( REG_RXCONFIG, SX1276->RegRxConfig | RF_RXCONFIG_RESTARTRXWITHPLLLOCK );
+        RFState = RF_STATE_RX_INIT;
+        result = RF_LEN_ERROR;
+        break;
+    // Tx management
+    case RF_STATE_TX_INIT:
+        // Packet DIO mapping setup
+        //                           PacketSent,               FifoLevel,              FifoFull,               TxReady
+        SX1276->RegDioMapping1 = RF_DIOMAPPING1_DIO0_00 | RF_DIOMAPPING1_DIO1_00 | RF_DIOMAPPING1_DIO2_00 | RF_DIOMAPPING1_DIO3_01;
+        //                           LowBat,                   Data
+        SX1276->RegDioMapping2 = RF_DIOMAPPING2_DIO4_00 | RF_DIOMAPPING2_DIO5_10;
+        SX1276WriteBuffer( REG_DIOMAPPING1, &SX1276->RegDioMapping1, 2 );
+
+        SX1276->RegFifoThresh = RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY | 0x18; // 24 bytes of data
+        SX1276Write( REG_FIFOTHRESH, SX1276->RegFifoThresh );
+
+        SX1276FskSetOpMode( RF_OPMODE_TRANSMITTER );
+        RFState = RF_STATE_TX_READY_WAIT;
+        TxBytesSent = 0;
+        break;
+    case RF_STATE_TX_READY_WAIT:
+        if( DIO3 == 1 )    // TxReady
+        {
+            if( ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) == RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE )
+            {
+                SX1276WriteFifo( ( uint8_t* )&TxPacketSize, 1 );
+            }
+            
+            if( ( TxPacketSize > 0 ) && ( TxPacketSize <= 64 ) )
+            {
+                DataChunkSize = TxPacketSize;
+            }
+            else
+            {
+                DataChunkSize = 32;
+            }
+            
+            SX1276WriteFifo( RFBuffer, DataChunkSize );
+            TxBytesSent += DataChunkSize;
+            TxTimeoutTimer = GET_TICK_COUNT( );
+            RFState = RF_STATE_TX_RUNNING;
+        }
+        break;
+
+    case RF_STATE_TX_RUNNING:
+        if( DIO1 == 0 )    // FifoLevel below thresold
+        {  
+            if( ( TxPacketSize - TxBytesSent ) > DataChunkSize )
+            {
+                SX1276WriteFifo( ( RFBuffer + TxBytesSent ), DataChunkSize );
+                TxBytesSent += DataChunkSize;
+            }
+            else 
+            {
+                // we write the last chunk of data
+                SX1276WriteFifo( RFBuffer + TxBytesSent, TxPacketSize - TxBytesSent );
+                TxBytesSent += TxPacketSize - TxBytesSent;
+            }
+        }
+
+        if( DIO0 == 1 ) // PacketSent
+        {
+            TxTimeoutTimer = GET_TICK_COUNT( );
+            RFState = RF_STATE_TX_DONE;
+            SX1276FskSetOpMode( RF_OPMODE_STANDBY );
+        }
+         
+        // Packet timeout
+        if( ( GET_TICK_COUNT( ) - TxTimeoutTimer ) > TICK_RATE_MS( 1000 ) )
+        {
+            RFState = RF_STATE_TX_TIMEOUT;
+        }
+        break;
+    case RF_STATE_TX_DONE:
+        RFState = RF_STATE_IDLE;
+        result = RF_TX_DONE;
+        break;
+    case RF_STATE_TX_TIMEOUT:
+        RFState = RF_STATE_IDLE;
+        result = RF_TX_TIMEOUT;
+        break;
+    default:
+        break;
+    }
+    return result;
+}
+
+#endif // USE_SX1276_RADIO

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276-FskMisc.c

@@ -0,0 +1,532 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       sx1276-FskMisc.c
+ * \brief      SX1276 RF chip high level functions driver
+ *
+ * \remark     Optional support functions.
+ *             These functions are defined only to easy the change of the
+ *             parameters.
+ *             For a final firmware the radio parameters will be known so
+ *             there is no need to support all possible parameters.
+ *             Removing these functions will greatly reduce the final firmware
+ *             size.
+ *
+ * \version    2.0.0 
+ * \date       May 6 2013
+ * \author     Gregory Cristian
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276-FskMisc.c
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+#include <math.h>
+
+#include "platform.h"
+
+#if defined( USE_SX1276_RADIO )
+
+#include "sx1276-Hal.h"
+#include "sx1276.h"
+
+#include "sx1276-Fsk.h"
+#include "sx1276-FskMisc.h"
+
+extern tFskSettings FskSettings;
+
+void SX1276FskSetRFFrequency( uint32_t freq )
+{
+    FskSettings.RFFrequency = freq;
+
+    freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
+    SX1276->RegFrfMsb = ( uint8_t )( ( freq >> 16 ) & 0xFF );
+    SX1276->RegFrfMid = ( uint8_t )( ( freq >> 8 ) & 0xFF );
+    SX1276->RegFrfLsb = ( uint8_t )( freq & 0xFF );
+    SX1276WriteBuffer( REG_FRFMSB, &SX1276->RegFrfMsb, 3 );
+}
+
+uint32_t SX1276FskGetRFFrequency( void )
+{
+    SX1276ReadBuffer( REG_FRFMSB, &SX1276->RegFrfMsb, 3 );
+    FskSettings.RFFrequency = ( ( uint32_t )SX1276->RegFrfMsb << 16 ) | ( ( uint32_t )SX1276->RegFrfMid << 8 ) | ( ( uint32_t )SX1276->RegFrfLsb );
+    FskSettings.RFFrequency = ( uint32_t )( ( double )FskSettings.RFFrequency * ( double )FREQ_STEP );
+
+    return FskSettings.RFFrequency;
+}
+
+void SX1276FskRxCalibrate( void )
+{
+    // the function RadioRxCalibrate is called just after the reset so all register are at their default values
+    uint8_t regPaConfigInitVal;
+    uint32_t initialFreq;
+
+    // save register values;
+    SX1276Read( REG_PACONFIG, &regPaConfigInitVal );
+    initialFreq = SX1276FskGetRFFrequency( );
+
+    // Cut the PA just in case
+    SX1276->RegPaConfig = 0x00; // RFO output, power = -1 dBm
+    SX1276Write( REG_PACONFIG, SX1276->RegPaConfig );
+
+    // Set Frequency in HF band
+    SX1276FskSetRFFrequency( 860000000 );
+
+    // Rx chain re-calibration workaround
+    SX1276Read( REG_IMAGECAL, &SX1276->RegImageCal );    
+    SX1276->RegImageCal = ( SX1276->RegImageCal & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START;
+    SX1276Write( REG_IMAGECAL, SX1276->RegImageCal );
+
+    SX1276Read( REG_IMAGECAL, &SX1276->RegImageCal );
+    // rx_cal_run goes low when calibration in finished
+    while( ( SX1276->RegImageCal & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
+    {
+        SX1276Read( REG_IMAGECAL, &SX1276->RegImageCal );
+    }
+
+    // reload saved values into the registers
+    SX1276->RegPaConfig = regPaConfigInitVal;
+    SX1276Write( REG_PACONFIG, SX1276->RegPaConfig );
+
+    SX1276FskSetRFFrequency( initialFreq );
+
+}
+
+void SX1276FskSetBitrate( uint32_t bitrate )
+{
+    FskSettings.Bitrate = bitrate;
+    
+    bitrate = ( uint16_t )( ( double )XTAL_FREQ / ( double )bitrate );
+    SX1276->RegBitrateMsb    = ( uint8_t )( bitrate >> 8 );
+    SX1276->RegBitrateLsb    = ( uint8_t )( bitrate & 0xFF );
+    SX1276WriteBuffer( REG_BITRATEMSB, &SX1276->RegBitrateMsb, 2 );    
+}
+
+uint32_t SX1276FskGetBitrate( void )
+{
+    SX1276ReadBuffer( REG_BITRATEMSB, &SX1276->RegBitrateMsb, 2 );
+    FskSettings.Bitrate = ( ( ( uint32_t )SX1276->RegBitrateMsb << 8 ) | ( ( uint32_t )SX1276->RegBitrateLsb ) );
+    FskSettings.Bitrate = ( uint16_t )( ( double )XTAL_FREQ / ( double )FskSettings.Bitrate );
+
+    return FskSettings.Bitrate;
+}
+
+void SX1276FskSetFdev( uint32_t fdev )
+{
+    FskSettings.Fdev = fdev;
+
+    SX1276Read( REG_FDEVMSB, &SX1276->RegFdevMsb ); 
+
+    fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
+    SX1276->RegFdevMsb    = ( ( SX1276->RegFdevMsb & RF_FDEVMSB_FDEV_MASK ) | ( ( ( uint8_t )( fdev >> 8 ) ) & ~RF_FDEVMSB_FDEV_MASK ) );
+    SX1276->RegFdevLsb    = ( uint8_t )( fdev & 0xFF );
+    SX1276WriteBuffer( REG_FDEVMSB, &SX1276->RegFdevMsb, 2 );    
+}
+
+uint32_t SX1276FskGetFdev( void )
+{
+    SX1276ReadBuffer( REG_FDEVMSB, &SX1276->RegFdevMsb, 2 );
+    FskSettings.Fdev = ( ( ( uint32_t )( ( SX1276->RegFdevMsb << 8 ) & ~RF_FDEVMSB_FDEV_MASK ) ) | ( ( uint32_t )SX1276->RegFdevLsb ) );
+    FskSettings.Fdev = ( uint16_t )( ( double )FskSettings.Fdev * ( double )FREQ_STEP );
+
+    return FskSettings.Fdev;
+}
+
+void SX1276FskSetRFPower( int8_t power )
+{
+    SX1276Read( REG_PACONFIG, &SX1276->RegPaConfig );
+    SX1276Read( REG_PADAC, &SX1276->RegPaDac );
+    
+    if( ( SX1276->RegPaConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
+    {
+        if( ( SX1276->RegPaDac & 0x87 ) == 0x87 )
+        {
+            if( power < 5 )
+            {
+                power = 5;
+            }
+            if( power > 20 )
+            {
+                power = 20;
+            }
+            SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
+            SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
+        }
+        else
+        {
+            if( power < 2 )
+            {
+                power = 2;
+            }
+            if( power > 17 )
+            {
+                power = 17;
+            }
+            SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
+            SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
+        }
+    }
+    else
+    {
+        if( power < -1 )
+        {
+            power = -1;
+        }
+        if( power > 14 )
+        {
+            power = 14;
+        }
+        SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
+        SX1276->RegPaConfig = ( SX1276->RegPaConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
+    }
+    SX1276Write( REG_PACONFIG, SX1276->RegPaConfig );
+    FskSettings.Power = power;
+}
+
+int8_t SX1276FskGetRFPower( void )
+{
+    SX1276Read( REG_PACONFIG, &SX1276->RegPaConfig );
+    SX1276Read( REG_PADAC, &SX1276->RegPaDac );
+
+    if( ( SX1276->RegPaConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
+    {
+        if( ( SX1276->RegPaDac & 0x07 ) == 0x07 )
+        {
+            FskSettings.Power = 5 + ( SX1276->RegPaConfig & ~RF_PACONFIG_OUTPUTPOWER_MASK );
+        }
+        else
+        {
+            FskSettings.Power = 2 + ( SX1276->RegPaConfig & ~RF_PACONFIG_OUTPUTPOWER_MASK );
+        }
+    }
+    else
+    {
+        FskSettings.Power = -1 + ( SX1276->RegPaConfig & ~RF_PACONFIG_OUTPUTPOWER_MASK );
+    }
+    return FskSettings.Power;
+}
+
+/*!
+ * \brief Computes the Rx bandwidth with the mantisse and exponent
+ *
+ * \param [IN] mantisse Mantisse of the bandwidth value
+ * \param [IN] exponent Exponent of the bandwidth value
+ * \retval bandwidth Computed bandwidth
+ */
+static uint32_t SX1276FskComputeRxBw( uint8_t mantisse, uint8_t exponent )
+{
+    // rxBw
+    if( ( SX1276->RegOpMode & RF_OPMODE_MODULATIONTYPE_FSK ) == RF_OPMODE_MODULATIONTYPE_FSK )
+    {
+        return ( uint32_t )( ( double )XTAL_FREQ / ( mantisse * ( double )pow( 2, exponent + 2 ) ) );
+    }
+    else
+    {
+        return ( uint32_t )( ( double )XTAL_FREQ / ( mantisse * ( double )pow( 2, exponent + 3 ) ) );
+    }
+}
+
+/*!
+ * \brief Computes the mantisse and exponent from the bandwitdh value
+ *
+ * \param [IN] rxBwValue Bandwidth value
+ * \param [OUT] mantisse Mantisse of the bandwidth value
+ * \param [OUT] exponent Exponent of the bandwidth value
+ */
+static void SX1276FskComputeRxBwMantExp( uint32_t rxBwValue, uint8_t* mantisse, uint8_t* exponent )
+{
+    uint8_t tmpExp = 0;
+    uint8_t tmpMant = 0;
+
+    double tmpRxBw = 0;
+    double rxBwMin = 10e6;
+
+    for( tmpExp = 0; tmpExp < 8; tmpExp++ )
+    {
+        for( tmpMant = 16; tmpMant <= 24; tmpMant += 4 )
+        {
+            if( ( SX1276->RegOpMode & RF_OPMODE_MODULATIONTYPE_FSK ) == RF_OPMODE_MODULATIONTYPE_FSK )
+            {
+                tmpRxBw = ( double )XTAL_FREQ / ( tmpMant * ( double )pow( 2, tmpExp + 2 ) );
+            }
+            else
+            {
+                tmpRxBw = ( double )XTAL_FREQ / ( tmpMant * ( double )pow( 2, tmpExp + 3 ) );
+            }
+            if( fabs( tmpRxBw - rxBwValue ) < rxBwMin )
+            {
+                rxBwMin = fabs( tmpRxBw - rxBwValue );
+                *mantisse = tmpMant;
+                *exponent = tmpExp;
+            }
+        }
+    }
+}
+
+void SX1276FskSetDccBw( uint8_t* reg, uint32_t dccValue, uint32_t rxBwValue )
+{
+    uint8_t mantisse = 0;
+    uint8_t exponent = 0;
+    
+    if( reg == &SX1276->RegRxBw )
+    {
+        *reg = ( uint8_t )dccValue & 0x60;
+    }
+    else
+    {
+        *reg = 0;
+    }
+
+    SX1276FskComputeRxBwMantExp( rxBwValue, &mantisse, &exponent );
+
+    switch( mantisse )
+    {
+        case 16:
+            *reg |= ( uint8_t )( 0x00 | ( exponent & 0x07 ) );
+            break;
+        case 20:
+            *reg |= ( uint8_t )( 0x08 | ( exponent & 0x07 ) );
+            break;
+        case 24:
+            *reg |= ( uint8_t )( 0x10 | ( exponent & 0x07 ) );
+            break;
+        default:
+            // Something went terribely wrong
+            break;
+    }
+
+    if( reg == &SX1276->RegRxBw )
+    {
+        SX1276Write( REG_RXBW, *reg );
+        FskSettings.RxBw = rxBwValue;
+    }
+    else
+    {
+        SX1276Write( REG_AFCBW, *reg );
+        FskSettings.RxBwAfc = rxBwValue;
+    }
+}
+
+uint32_t SX1276FskGetBw( uint8_t* reg )
+{
+    uint32_t rxBwValue = 0;
+    uint8_t mantisse = 0;
+    switch( ( *reg & 0x18 ) >> 3 )
+    {
+        case 0:
+            mantisse = 16;
+            break;
+        case 1:
+            mantisse = 20;
+            break;
+        case 2:
+            mantisse = 24;
+            break;
+        default:
+            break;
+    }
+    rxBwValue = SX1276FskComputeRxBw( mantisse, ( uint8_t )*reg & 0x07 );
+    if( reg == &SX1276->RegRxBw )
+    {
+        return FskSettings.RxBw = rxBwValue;
+    }
+    else
+    {
+        return FskSettings.RxBwAfc = rxBwValue;
+    }
+}
+
+void SX1276FskSetPacketCrcOn( bool enable )
+{
+    SX1276Read( REG_PACKETCONFIG1, &SX1276->RegPacketConfig1 );
+    SX1276->RegPacketConfig1 = ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_CRC_MASK ) | ( enable << 4 );
+    SX1276Write( REG_PACKETCONFIG1, SX1276->RegPacketConfig1 );
+    FskSettings.CrcOn = enable;
+}
+
+bool SX1276FskGetPacketCrcOn( void )
+{
+    SX1276Read( REG_PACKETCONFIG1, &SX1276->RegPacketConfig1 );
+    FskSettings.CrcOn = ( SX1276->RegPacketConfig1 & RF_PACKETCONFIG1_CRC_ON ) >> 4;
+    return FskSettings.CrcOn;
+}
+
+void SX1276FskSetAfcOn( bool enable )
+{
+    SX1276Read( REG_RXCONFIG, &SX1276->RegRxConfig );
+    SX1276->RegRxConfig = ( SX1276->RegRxConfig & RF_RXCONFIG_AFCAUTO_MASK ) | ( enable << 4 );
+    SX1276Write( REG_RXCONFIG, SX1276->RegRxConfig );
+    FskSettings.AfcOn = enable;
+}
+
+bool SX1276FskGetAfcOn( void )
+{
+    SX1276Read( REG_RXCONFIG, &SX1276->RegRxConfig );
+    FskSettings.AfcOn = ( SX1276->RegRxConfig & RF_RXCONFIG_AFCAUTO_ON ) >> 4;
+    return FskSettings.AfcOn;
+}
+
+void SX1276FskSetPayloadLength( uint8_t value )
+{
+    SX1276->RegPayloadLength = value;
+    SX1276Write( REG_PAYLOADLENGTH, SX1276->RegPayloadLength );
+    FskSettings.PayloadLength = value;
+}
+
+uint8_t SX1276FskGetPayloadLength( void )
+{
+    SX1276Read( REG_PAYLOADLENGTH, &SX1276->RegPayloadLength );
+    FskSettings.PayloadLength = SX1276->RegPayloadLength;
+    return FskSettings.PayloadLength;
+}
+
+void SX1276FskSetPa20dBm( bool enale )
+{
+    SX1276Read( REG_PADAC, &SX1276->RegPaDac );
+    SX1276Read( REG_PACONFIG, &SX1276->RegPaConfig );
+
+    if( ( SX1276->RegPaConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
+    {    
+        if( enale == true )
+        {
+            SX1276->RegPaDac = 0x87;
+        }
+    }
+    else
+    {
+        SX1276->RegPaDac = 0x84;
+    }
+    SX1276Write( REG_PADAC, SX1276->RegPaDac );
+}
+
+bool SX1276FskGetPa20dBm( void )
+{
+    SX1276Read( REG_PADAC, &SX1276->RegPaDac );
+    
+    return ( ( SX1276->RegPaDac & 0x07 ) == 0x07 ) ? true : false;
+}
+
+void SX1276FskSetPAOutput( uint8_t outputPin )
+{
+    SX1276Read( REG_PACONFIG, &SX1276->RegPaConfig );
+    SX1276->RegPaConfig = (SX1276->RegPaConfig & RF_PACONFIG_PASELECT_MASK ) | outputPin;
+    SX1276Write( REG_PACONFIG, SX1276->RegPaConfig );
+}
+
+uint8_t SX1276FskGetPAOutput( void )
+{
+    SX1276Read( REG_PACONFIG, &SX1276->RegPaConfig );
+    return SX1276->RegPaConfig & ~RF_PACONFIG_PASELECT_MASK;
+}
+
+
+void SX1276FskSetPaRamp( uint8_t value )
+{
+    SX1276Read( REG_PARAMP, &SX1276->RegPaRamp );
+    SX1276->RegPaRamp = ( SX1276->RegPaRamp & RF_PARAMP_MASK ) | ( value & ~RF_PARAMP_MASK );
+    SX1276Write( REG_PARAMP, SX1276->RegPaRamp );
+}
+
+uint8_t SX1276FskGetPaRamp( void )
+{
+    SX1276Read( REG_PARAMP, &SX1276->RegPaRamp );
+    return SX1276->RegPaRamp & ~RF_PARAMP_MASK;
+}
+
+void SX1276FskSetRssiOffset( int8_t offset )
+{
+    SX1276Read( REG_RSSICONFIG, &SX1276->RegRssiConfig );
+    if( offset < 0 )
+    {
+        offset = ( ~offset & 0x1F );
+        offset += 1;
+        offset = -offset;
+    }
+    SX1276->RegRssiConfig |= ( uint8_t )( ( offset & 0x1F ) << 3 );
+    SX1276Write( REG_RSSICONFIG, SX1276->RegRssiConfig );
+}
+
+int8_t SX1276FskGetRssiOffset( void )
+{
+    int8_t offset;
+		SX1276Read( REG_RSSICONFIG, &SX1276->RegRssiConfig );
+    offset = SX1276->RegRssiConfig >> 3;
+    if( ( offset & 0x10 ) == 0x10 )
+    {
+        offset = ( ~offset & 0x1F );
+        offset += 1;
+        offset = -offset;
+    }
+    return offset;
+}
+
+int8_t SX1276FskGetRawTemp( void )
+{
+    int8_t temp = 0;
+    uint8_t previousOpMode;
+    uint32_t startTick;
+    
+    // Enable Temperature reading
+    SX1276Read( REG_IMAGECAL, &SX1276->RegImageCal );
+    SX1276->RegImageCal = ( SX1276->RegImageCal & RF_IMAGECAL_TEMPMONITOR_MASK ) | RF_IMAGECAL_TEMPMONITOR_ON;
+    SX1276Write( REG_IMAGECAL, SX1276->RegImageCal );
+
+    // save current Op Mode
+    SX1276Read( REG_OPMODE, &SX1276->RegOpMode );
+    previousOpMode = SX1276->RegOpMode;
+
+    // put device in FSK RxSynth
+    SX1276->RegOpMode = RF_OPMODE_SYNTHESIZER_RX;
+    SX1276Write( REG_OPMODE, SX1276->RegOpMode );
+
+    // Wait 1ms
+    startTick = GET_TICK_COUNT( );
+    while( ( GET_TICK_COUNT( ) - startTick ) < TICK_RATE_MS( 1 ) );  
+
+    // Disable Temperature reading
+    SX1276Read( REG_IMAGECAL, &SX1276->RegImageCal );
+    SX1276->RegImageCal = ( SX1276->RegImageCal & RF_IMAGECAL_TEMPMONITOR_MASK ) | RF_IMAGECAL_TEMPMONITOR_OFF;
+    SX1276Write( REG_IMAGECAL, SX1276->RegImageCal );
+
+    // Read temperature
+    SX1276Read( REG_TEMP, &SX1276->RegTemp );
+    
+    temp = SX1276->RegTemp & 0x7F;
+    
+    if( ( SX1276->RegTemp & 0x80 ) == 0x80 )
+    {
+        temp *= -1;
+    }
+
+    // Reload previous Op Mode
+    SX1276Write( REG_OPMODE, previousOpMode );
+
+    return temp;
+}
+
+int8_t SX1276FskCalibreateTemp( int8_t actualTemp )
+{
+    return actualTemp - SX1276FskGetRawTemp( );
+}
+
+int8_t SX1276FskGetTemp( int8_t compensationFactor )
+{
+    return SX1276FskGetRawTemp( ) + compensationFactor;
+}
+
+#endif // USE_SX1276_RADIO

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276-FskMisc.h

@@ -0,0 +1,251 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       sx1276-FskMisc.h
+ * \brief      SX1276 RF chip high level functions driver
+ *
+ * \remark     Optional support functions.
+ *             These functions are defined only to easy the change of the
+ *             parameters.
+ *             For a final firmware the radio parameters will be known so
+ *             there is no need to support all possible parameters.
+ *             Removing these functions will greatly reduce the final firmware
+ *             size.
+ *
+ * \version    2.0.B2 
+ * \date       May 6 2013
+ * \author     Gregory Cristian
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276-FskMisc.h
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+#ifndef __SX1276_FSK_MISC_H__
+#define __SX1276_FSK_MISC_H__
+
+/*!
+ * \brief Writes the new RF frequency value
+ *
+ * \param [IN] freq New RF frequency value in [Hz]
+ */
+void SX1276FskSetRFFrequency( uint32_t freq );
+
+/*!
+ * \brief Reads the current RF frequency value
+ *
+ * \retval freq Current RF frequency value in [Hz]
+ */
+uint32_t SX1276FskGetRFFrequency( void );
+
+/*!
+ * \brief Calibrate RSSI and I/Q mismatch for HF 
+ *
+ * \retval none
+ */
+void SX1276FskRxCalibrate( void );
+
+/*!
+ * \brief Writes the new bitrate value
+ *
+ * \param [IN] bitrate New bitrate value in [bps]
+ */
+void SX1276FskSetBitrate( uint32_t bitrate );
+
+/*!
+ * \brief Reads the current bitrate value
+ *
+ * \retval bitrate Current bitrate value in [bps]
+ */
+uint32_t SX1276FskGetBitrate( void );
+
+/*!
+ * \brief Writes the new frequency deviation value
+ *
+ * \param [IN] fdev New frequency deviation value in [Hz]
+ */
+void SX1276FskSetFdev( uint32_t fdev );
+
+/*!
+ * \brief Reads the current frequency deviation value
+ *
+ * \retval fdev Current frequency deviation value in [Hz]
+ */
+uint32_t SX1276FskGetFdev( void );
+
+/*!
+ * \brief Writes the new RF output power value
+ *
+ * \param [IN] power New output power value in [dBm]
+ */
+void SX1276FskSetRFPower( int8_t power );
+
+/*!
+ * \brief Reads the current RF output power value
+ *
+ * \retval power Current output power value in [dBm]
+ */
+int8_t SX1276FskGetRFPower( void );
+
+/*!
+ * \brief Writes the DC offset canceller and Rx bandwidth values
+ *
+ * \remark For SX1276 there is no DCC setting. dccValue should be 0
+ *         ie: SX1276SetDccBw( &SX1276.RegRxBw, 0, 62500 );
+ *
+ * \param [IN] reg Register pointer to either SX1231.RegRxBw or SX1231.RegAfcBw
+ * \param [IN] dccValue New DC offset canceller value in [Hz] ( SX1231 only )
+ * \param [IN] rxBwValue New Rx bandwidth value in [Hz]
+ */
+void SX1276FskSetDccBw( uint8_t* reg, uint32_t dccValue, uint32_t rxBwValue );
+
+/*!
+ * \brief Reads the current bandwidth setting
+ *
+ * \param [IN] reg Register pointer to either SX1231.RegRxBw or SX1231.RegAfcBw
+ *
+ * \retval bandwidth Bandwidth value
+ */
+uint32_t SX1276FskGetBw( uint8_t* reg );
+
+/*!
+ * \brief Enables/Disables CRC
+ *
+ * \param [IN] enable CRC enable/disable
+ */
+void SX1276FskSetPacketCrcOn( bool enable );
+
+/*!
+ * \brief Reads the current CRC Enable/Disbale value
+ *
+ * \retval enable Current CRC Enable/Disbale value
+ */
+bool SX1276FskGetPacketCrcOn( void );
+
+/*!
+ * \brief Enables/Disables AFC
+ *
+ * \param [IN] enable AFC enable/disable
+ */
+void SX1276FskSetAfcOn( bool enable );
+
+/*!
+ * \brief Reads the current AFC Enable/Disbale value
+ *
+ * \retval enable Current AFC Enable/Disbale value
+ */
+bool SX1276FskGetAfcOn( void );
+
+/*!
+ * \brief Writes the new payload length value
+ *
+ * \param [IN] value New payload length value
+ */
+void SX1276FskSetPayloadLength( uint8_t value );
+
+/*!
+ * \brief Reads the current payload length value
+ *
+ * \retval value Current payload length value
+ */
+uint8_t SX1276FskGetPayloadLength( void );
+
+/*!
+ * \brief Enables/Disables the 20 dBm PA
+ *
+ * \param [IN] enable [true, false]
+ */
+void SX1276FskSetPa20dBm( bool enale );
+
+/*!
+ * \brief Gets the current 20 dBm PA status
+ *
+ * \retval enable [true, false]
+ */
+bool SX1276FskGetPa20dBm( void );
+
+/*!
+ * \brief Set the RF Output pin 
+ *
+ * \param [IN] RF_PACONFIG_PASELECT_PABOOST or RF_PACONFIG_PASELECT_RFO
+ */
+void SX1276FskSetPAOutput( uint8_t outputPin );
+
+/*!
+ * \brief Gets the used RF Ouptu pin
+ *
+ * \retval RF_PACONFIG_PASELECT_PABOOST or RF_PACONFIG_PASELECT_RFO
+ */
+uint8_t SX1276FskGetPAOutput( void );
+
+/*!
+ * \brief Writes the new PA rise/fall time of ramp up/down value
+ *
+ * \param [IN] value New PaRamp value
+ */
+void SX1276FskSetPaRamp( uint8_t value );
+
+/*!
+ * \brief Reads the current PA rise/fall time of ramp up/down value
+ *
+ * \retval value Current PaRamp value
+ */
+uint8_t SX1276FskGetPaRamp( void );
+
+/*!
+ * \brief Applies an offset to the RSSI. Compensates board components
+ *
+ * \param [IN] offset Offset to be applied (+/-)
+ */
+void SX1276FskSetRssiOffset( int8_t offset );
+
+/*!
+ * \brief Gets the current RSSI offset.
+ *
+ * \retval offset Current offset (+/-)
+ */
+int8_t SX1276FskGetRssiOffset( void );
+
+/*!
+ * \brief Writes the new value for the preamble size
+ *
+ * \param [IN] size New value of pramble size
+ */
+void SX1276FskSetPreambleSize( uint16_t size );
+
+/*!
+ * Reads the raw temperature
+ * \retval temperature New raw temperature reading in 2's complement format
+ */
+int8_t SX1276FskGetRawTemp( void );
+
+/*!
+ * Computes the temperature compensation factor
+ * \param [IN] actualTemp Actual temperature measured by an external device
+ * \retval compensationFactor Computed compensation factor
+ */
+int8_t SX1276FskCalibreateTemp( int8_t actualTemp );
+
+/*!
+ * Gets the actual compensated temperature
+ * \param [IN] compensationFactor Return value of the calibration function
+ * \retval New compensated temperature value
+ */
+int8_t SX1276FskGetTemp( int8_t compensationFactor );
+
+#endif //__SX1276_FSK_MISC_H__

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276-Hal.h

@@ -0,0 +1,170 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       sx1276-Hal.h
+ * \brief      SX1276 Hardware Abstraction Layer
+ *
+ * \version    2.0.B2 
+ * \date       Nov 21 2012
+ * \author     Miguel Luis
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276-Hal.h
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+#ifndef __SX1276_HAL_H__
+#define __SX1276_HAL_H__
+#include "platform.h"
+
+/*!
+ * DIO state read functions mapping
+ */
+#define DIO0                                        SX1276ReadDio0( )
+#define DIO1                                        SX1276ReadDio1( )
+#define DIO2                                        SX1276ReadDio2( )
+#define DIO3                                        SX1276ReadDio3( )
+#define DIO4                                        SX1276ReadDio4( )
+#define DIO5                                        SX1276ReadDio5( )
+
+// RXTX pin control see errata note
+#define RXTX( txEnable )                            SX1276WriteRxTx( txEnable );
+
+#define GET_TICK_COUNT( )                           CurrentTicksGain()
+#define TICK_RATE_MS( ms )                          ( ms )
+
+typedef enum
+{
+    RADIO_RESET_OFF,
+    RADIO_RESET_ON,
+}tRadioResetState;
+
+/*!
+ * \brief Initializes the radio interface I/Os
+ */
+void SX1276InitIo( void );
+
+/*!
+ * \brief Set the radio reset pin state
+ * 
+ * \param state New reset pin state
+ */
+void SX1276SetReset( uint8_t state );
+
+/*!
+ * \brief Writes the radio register at the specified address
+ *
+ * \param [IN]: addr Register address
+ * \param [IN]: data New register value
+ */
+void SX1276Write( uint8_t addr, uint8_t data );
+
+/*!
+ * \brief Reads the radio register at the specified address
+ *
+ * \param [IN]: addr Register address
+ * \param [OUT]: data Register value
+ */
+void SX1276Read( uint8_t addr, uint8_t *data );
+
+/*!
+ * \brief Writes multiple radio registers starting at address
+ *
+ * \param [IN] addr   First Radio register address
+ * \param [IN] buffer Buffer containing the new register's values
+ * \param [IN] size   Number of registers to be written
+ */
+void SX1276WriteBuffer( uint8_t addr, uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Reads multiple radio registers starting at address
+ *
+ * \param [IN] addr First Radio register address
+ * \param [OUT] buffer Buffer where to copy the registers data
+ * \param [IN] size Number of registers to be read
+ */
+void SX1276ReadBuffer( uint8_t addr, uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Writes the buffer contents to the radio FIFO
+ *
+ * \param [IN] buffer Buffer containing data to be put on the FIFO.
+ * \param [IN] size Number of bytes to be written to the FIFO
+ */
+void SX1276WriteFifo( uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Reads the contents of the radio FIFO
+ *
+ * \param [OUT] buffer Buffer where to copy the FIFO read data.
+ * \param [IN] size Number of bytes to be read from the FIFO
+ */
+void SX1276ReadFifo( uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Gets the SX1276 DIO0 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+inline uint8_t SX1276ReadDio0( void );
+
+/*!
+ * \brief Ge// USE_SX1276_RADIOts the SX1276 DIO1 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+inline uint8_t SX1276ReadDio1( void );
+
+/*!
+ * \brief Gets the SX1276 DIO2 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+inline uint8_t SX1276ReadDio2( void );
+
+/*!
+ * \brief Gets the SX1276 DIO3 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+inline uint8_t SX1276ReadDio3( void );
+
+/*!
+ * \brief Gets the SX1276 DIO4 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+inline uint8_t SX1276ReadDio4( void );
+
+/*!
+ * \brief Gets the SX1276 DIO5 hardware pin status
+ *
+ * \retval status Current hardware pin status [1, 0]
+ */
+inline uint8_t SX1276ReadDio5( void );
+
+/*!
+ * \brief Writes the external RxTx pin value
+ *
+ * \remark see errata note
+ *
+ * \param [IN] txEnable [1: Tx, 0: Rx]
+ */
+inline void SX1276WriteRxTx( uint8_t txEnable );
+
+#endif //__SX1276_HAL_H__

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276-LoRa.c

@@ -0,0 +1,801 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Original Copyright (C) SEMTECH S.A.
+ * Modified Copyright (C) 2020 AIIT XUOS Lab
+ */
+/*! 
+ * \file       sx1276-LoRa.c
+ * \brief      SX1276 RF chip driver mode LoRa
+ *
+ * \version    2.0.0 
+ * \date       Nov 21 2012
+ * \author     Miguel Luis
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276-LoRa.c
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+#include <string.h>
+
+#include "platform.h"
+
+#if defined( USE_SX1276_RADIO )
+#include "radio.h"
+#include "sx1276-Hal.h"
+#include "sx1276.h"
+#include "sx1276-LoRaMisc.h"
+#include "sx1276-LoRa.h"
+
+#define LoRa_FREQENCY                              433000000
+
+#define RSSI_OFFSET_LF                              -155.0
+#define RSSI_OFFSET_HF                              -150.0
+
+#define NOISE_ABSOLUTE_ZERO                         -174.0
+#define NOISE_FIGURE_LF                                4.0
+#define NOISE_FIGURE_HF                                6.0 
+
+volatile uint32 TickCounter = 0; 
+
+uint32 Tx_Time_Start,Tx_Time_End;   
+uint32 Rx_Time_Start,Rx_Time_End;
+//Signal bandwidth, used to calculate RSSI
+const double SignalBwLog[] =
+{
+    3.8927900303521316335038277369285,  // 7.8 kHz
+    4.0177301567005500940384239336392,  // 10.4 kHz
+    4.193820026016112828717566631653,   // 15.6 kHz
+    4.31875866931372901183597627752391, // 20.8 kHz
+    4.4948500216800940239313055263775,  // 31.2 kHz
+    4.6197891057238405255051280399961,  // 41.6 kHz
+    4.795880017344075219145044421102,   // 62.5 kHz
+    5.0969100130080564143587833158265,  // 125 kHz
+    5.397940008672037609572522210551,   // 250 kHz
+    5.6989700043360188047862611052755   // 500 kHz
+};
+
+//These values need testing
+const double RssiOffsetLF[] =
+{   
+    -155.0,
+    -155.0,
+    -155.0,
+    -155.0,
+    -155.0,
+    -155.0,
+    -155.0,
+    -155.0,
+    -155.0,
+    -155.0,
+};
+
+//These values need testing
+const double RssiOffsetHF[] =
+{  
+    -150.0,
+    -150.0,
+    -150.0,
+    -150.0,
+    -150.0,
+    -150.0,
+    -150.0,
+    -150.0,
+    -150.0,
+    -150.0,
+};
+
+/*!
+ * Frequency hopping frequencies table
+ */
+const int32_t HoppingFrequencies[] =
+{
+    916500000,
+    923500000,
+    906500000,
+    917500000,
+    917500000,
+    909000000,
+    903000000,
+    916000000,
+    912500000,
+    926000000,
+    925000000,
+    909500000,
+    913000000,
+    918500000,
+    918500000,
+    902500000,
+    911500000,
+    926500000,
+    902500000,
+    922000000,
+    924000000,
+    903500000,
+    913000000,
+    922000000,
+    926000000,
+    910000000,
+    920000000,
+    922500000,
+    911000000,
+    922000000,
+    909500000,
+    926000000,
+    922000000,
+    918000000,
+    925500000,
+    908000000,
+    917500000,
+    926500000,
+    908500000,
+    916000000,
+    905500000,
+    916000000,
+    903000000,
+    905000000,
+    915000000,
+    913000000,
+    907000000,
+    910000000,
+    926500000,
+    925500000,
+    911000000,
+};
+
+// Default settings
+tLoRaSettings LoRaSettings =
+{
+    LoRa_FREQENCY ,   // RFFrequency
+    20,               // Power
+    9,                // SignalBw [0: 125 kHz, 1: 250 kHz, 2: 500 kHz, 3: Reserved] 
+    12,                // SpreadingFactor [6: 64, 7: 128, 8: 256, 9: 512, 10: 1024, 11: 2048, 12: 4096  chips]
+    2,                // ErrorCoding [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+    true,             // CrcOn [0: OFF, 1: ON]
+    false,            // ImplicitHeaderOn [0: OFF, 1: ON]
+    0,                // RxSingleOn [0: Continuous, 1 Single]
+    0,                // FreqHopOn [0: OFF, 1: ON]
+    4,                // HopPeriod Hops every frequency hopping period symbols
+    1000,             // TxPacketTimeout
+    1000,             // RxPacketTimeout
+    128,              // PayloadLength (used for implicit header mode)
+};
+
+/*!
+ * SX1276 LoRa registers variable
+ */
+tSX1276LR* SX1276LR;
+
+/*!
+ * Local RF buffer for communication support
+ */
+static uint8_t RFBuffer[RF_BUFFER_SIZE];
+static uint8_t TFBuffer[RF_BUFFER_SIZE];
+
+/*!
+ * RF state machine variable
+ */
+static uint8_t RFLRState = RFLR_STATE_IDLE;
+
+/*!
+ * Rx management support variables
+ */
+static uint16_t RxPacketSize = 0;     
+static int8_t RxPacketSnrEstimate;    
+static double RxPacketRssiValue;      
+static uint8_t RxGain = 1;            
+static uint32_t RxTimeoutTimer = 0;  
+
+/*!
+ * PacketTimeout Stores the Rx window time value for packet reception
+ */ 
+static uint32_t PacketTimeout;  
+
+/*!
+ * Tx management support variables
+ */
+static uint16_t TxPacketSize = 0;     
+
+
+void SX1276LoRaInit( void )
+{
+	RFLRState = RFLR_STATE_IDLE;                                     
+
+	SX1276LoRaSetDefaults();                                         
+	
+    
+	SX1276ReadBuffer( REG_LR_OPMODE, SX1276Regs + 1, 0x70 - 1 );     
+    
+    
+    //SX1276LoRaSetOpMode( RFLR_OPMODE_SLEEP );
+	
+    SX1276LR->RegLna = RFLR_LNA_GAIN_G1;                             
+    SX1276WriteBuffer( REG_LR_OPMODE, SX1276Regs + 1, 0x70 - 1 );    
+	
+    // set the RF settings 
+    SX1276LoRaSetRFFrequency( LoRaSettings.RFFrequency );            
+    SX1276LoRaSetSpreadingFactor( LoRaSettings.SpreadingFactor );    
+    SX1276LoRaSetErrorCoding( LoRaSettings.ErrorCoding );            
+    SX1276LoRaSetPacketCrcOn( LoRaSettings.CrcOn );                  
+    SX1276LoRaSetSignalBandwidth( LoRaSettings.SignalBw );           
+    SX1276LoRaSetImplicitHeaderOn( LoRaSettings.ImplicitHeaderOn );  
+	
+    SX1276LoRaSetSymbTimeout(0x3FF);                                 
+    SX1276LoRaSetPayloadLength( LoRaSettings.PayloadLength );        
+    SX1276LoRaSetLowDatarateOptimize( true );                        
+
+    #if( ( MODULE_SX1276RF1IAS == 1 ) || ( MODULE_SX1276RF1KAS == 1 ) )
+        if( LoRaSettings.RFFrequency > 860000000 )                   
+        {
+            SX1276LoRaSetPAOutput( RFLR_PACONFIG_PASELECT_RFO );     
+            SX1276LoRaSetPa20dBm( false );                           
+            LoRaSettings.Power = 14;                                 
+            SX1276LoRaSetRFPower( LoRaSettings.Power );              
+        }
+        else                                                         
+        {
+			//SX1276Write( REG_LR_OCP, 0x3f );
+            SX1276LoRaSetPAOutput( RFLR_PACONFIG_PASELECT_PABOOST ); 
+            SX1276LoRaSetPa20dBm( true );                            
+            LoRaSettings.Power = 20;                                 
+            SX1276LoRaSetRFPower( LoRaSettings.Power );                     
+        } 
+    #elif( MODULE_SX1276RF1JAS == 1 )	
+		if( LoRaSettings.RFFrequency > 380000000 )                   
+		{
+			SX1276LoRaSetPAOutput( RFLR_PACONFIG_PASELECT_PABOOST ); 
+			SX1276LoRaSetPa20dBm( true );                            
+			LoRaSettings.Power = 20;                                 
+			SX1276LoRaSetRFPower( LoRaSettings.Power );                
+		}
+		else
+		{
+			SX1276LoRaSetPAOutput( RFLR_PACONFIG_PASELECT_RFO );
+			SX1276LoRaSetPa20dBm( false );
+			LoRaSettings.Power = 14;
+			SX1276LoRaSetRFPower( LoRaSettings.Power );
+		} 
+	#endif
+    SX1276LoRaSetOpMode( RFLR_OPMODE_STANDBY );	                      
+}
+
+
+void SX1276LoRaSetDefaults( void )
+{
+    // REMARK: See SX1276 datasheet for modified default values.
+
+    // Sets IF frequency selection manual
+    SX1276Read( REG_LR_VERSION, &SX1276LR->RegVersion );
+}
+
+
+
+void SX1276LoRaReset( void )
+{
+    uint32_t startTick;
+	
+	SX1276SetReset( RADIO_RESET_ON );
+    
+	// Wait 1ms
+    startTick = GET_TICK_COUNT( );                                    
+    while( ( GET_TICK_COUNT( ) - startTick ) < TICK_RATE_MS( 1 ) );    
+
+    SX1276SetReset( RADIO_RESET_OFF );
+    
+	// Wait 6ms
+    startTick = GET_TICK_COUNT( );                                    
+    while( ( GET_TICK_COUNT( ) - startTick ) < TICK_RATE_MS( 6 ) );    
+}
+
+void SX1276LoRaSetOpMode( uint8_t opMode )
+{
+    static uint8_t opModePrev = RFLR_OPMODE_STANDBY;
+    static bool antennaSwitchTxOnPrev = true;
+    bool antennaSwitchTxOn = false;                                  
+    opModePrev = SX1276LR->RegOpMode & ~RFLR_OPMODE_MASK;
+    if( opMode != opModePrev )                                       
+    {
+        if( opMode == RFLR_OPMODE_TRANSMITTER )                      
+		{
+			antennaSwitchTxOn = true;
+		}
+		else
+		{
+			antennaSwitchTxOn = false;
+		}
+		if( antennaSwitchTxOn != antennaSwitchTxOnPrev )
+		{
+			antennaSwitchTxOnPrev = antennaSwitchTxOn;	// Antenna switch control
+			RXTX( antennaSwitchTxOn );                                
+		}
+		SX1276LR->RegOpMode = ( SX1276LR->RegOpMode & RFLR_OPMODE_MASK ) | opMode;
+		
+		SX1276Write( REG_LR_OPMODE, SX1276LR->RegOpMode );        
+	}
+}
+
+
+uint8_t SX1276LoRaGetOpMode( void )                       
+{
+    SX1276Read( REG_LR_OPMODE, &SX1276LR->RegOpMode );
+    
+    return SX1276LR->RegOpMode & ~RFLR_OPMODE_MASK;
+}
+
+
+uint8_t SX1276LoRaReadRxGain( void )                    
+{
+	
+	SX1276Read( REG_LR_LNA, &SX1276LR->RegLna );
+	return( SX1276LR->RegLna >> 5 ) & 0x07;
+}
+
+
+double SX1276LoRaReadRssi( void )
+{  
+	// Reads the RSSI value
+    SX1276Read( REG_LR_RSSIVALUE, &SX1276LR->RegRssiValue );
+
+    if( LoRaSettings.RFFrequency < 860000000 )  
+    {
+        return RssiOffsetLF[LoRaSettings.SignalBw] + ( double )SX1276LR->RegRssiValue;
+    }
+    else
+    {
+        return RssiOffsetHF[LoRaSettings.SignalBw] + ( double )SX1276LR->RegRssiValue;
+    }
+}
+
+
+uint8_t SX1276LoRaGetPacketRxGain( void )
+{
+    return RxGain;
+}
+
+
+int8_t SX1276LoRaGetPacketSnr( void )
+{
+    return RxPacketSnrEstimate;
+}
+
+
+double SX1276LoRaGetPacketRssi( void )
+{
+    return RxPacketRssiValue;
+}
+
+
+void SX1276LoRaStartRx( void )
+{
+    SX1276LoRaSetRFState( RFLR_STATE_RX_INIT );
+}
+
+
+void SX1276LoRaGetRxPacket( void *buffer, uint16_t *size )
+{
+	*size = RxPacketSize;
+	RxPacketSize = 0;
+	memcpy( (void*)buffer, (void*)RFBuffer, (size_t)*size );
+}
+
+
+void SX1276LoRaSetTxPacket( const void *buffer, uint16_t size )
+{
+    if( LoRaSettings.FreqHopOn == false )    
+    {
+        TxPacketSize = size;
+    }
+    else
+    {
+        TxPacketSize = 255;
+    }
+    memcpy( ( void * )TFBuffer, buffer, ( size_t )TxPacketSize );  
+
+    RFLRState = RFLR_STATE_TX_INIT;                                
+}
+
+
+uint8_t SX1276LoRaGetRFState( void )
+{
+    return RFLRState;
+}
+
+
+void SX1276LoRaSetRFState( uint8_t state )
+{
+    RFLRState = state;
+}
+
+/*!
+ * \brief Process the LoRa modem Rx and Tx state machines depending on the
+ *        SX1276 operating mode.
+ *
+ * \retval rfState Current RF state [RF_IDLE, RF_BUSY, 
+ *                                   RF_RX_DONE, RF_RX_TIMEOUT,
+ *                                   RF_TX_DONE, RF_TX_TIMEOUT]
+ */
+uint32_t SX1276LoRaProcess( void )
+{
+    uint32_t result = RF_BUSY;
+    uint8_t regValue=0;
+    switch( RFLRState )
+    {
+		case RFLR_STATE_IDLE:                                                 
+             break;
+        case RFLR_STATE_RX_INIT:                                               
+			 SX1276LoRaSetOpMode(RFLR_OPMODE_STANDBY);                         
+		     
+		     SX1276LR->RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT          |    
+									   
+									     RFLR_IRQFLAGS_PAYLOADCRCERROR    |    
+									     RFLR_IRQFLAGS_VALIDHEADER        |
+									     RFLR_IRQFLAGS_TXDONE             |
+									     RFLR_IRQFLAGS_CADDONE            |
+                                         RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |    
+									     RFLR_IRQFLAGS_CADDETECTED;
+		     SX1276Write( REG_LR_IRQFLAGSMASK, SX1276LR->RegIrqFlagsMask );    
+
+		     if(LoRaSettings.FreqHopOn == true )                               
+		     {
+		         SX1276LR->RegHopPeriod = LoRaSettings.HopPeriod;              
+		       
+                 SX1276Read( REG_LR_HOPCHANNEL, &SX1276LR->RegHopChannel );    
+			     SX1276LoRaSetRFFrequency( HoppingFrequencies[SX1276LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] );
+		     }
+		     else    
+		     { 
+                 SX1276LR->RegHopPeriod = 255;
+		     } 
+		     
+		     SX1276Write( REG_LR_HOPPERIOD, SX1276LR->RegHopPeriod );  
+			
+		     
+                                    // RxDone     
+		     SX1276LR->RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_00;
+                                    // CadDetected   
+		     SX1276LR->RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_10 | RFLR_DIOMAPPING2_DIO5_00;
+		
+		     SX1276WriteBuffer( REG_LR_DIOMAPPING1, &SX1276LR->RegDioMapping1, 2 );
+			
+		     if( LoRaSettings.RxSingleOn == true )        // Rx single mode                       
+		     {
+			     SX1276LoRaSetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
+		     }
+	         else                        // Rx continuous mode                                        
+		     {
+			     SX1276LR->RegFifoAddrPtr = SX1276LR->RegFifoRxBaseAddr;
+			     
+			     SX1276Write( REG_LR_FIFOADDRPTR, SX1276LR->RegFifoAddrPtr );    
+			     SX1276LoRaSetOpMode( RFLR_OPMODE_RECEIVER );
+				 
+		     }   
+		     memset( RFBuffer, 0, ( size_t )RF_BUFFER_SIZE );                    
+             Rx_Time_Start=TickCounter;
+		     PacketTimeout = LoRaSettings.RxPacketTimeout;                       
+		     RxTimeoutTimer = GET_TICK_COUNT( );
+		     RFLRState = RFLR_STATE_RX_RUNNING;
+		     break;
+		case RFLR_STATE_RX_RUNNING:                                              
+			 SX1276Read(0x12,&regValue);                                         
+             //if( DIO0 == 1 )         // RxDone
+			 if(regValue & (1<<6))                                               
+             {
+				 
+		         RxTimeoutTimer = GET_TICK_COUNT( );
+                 if( LoRaSettings.FreqHopOn == true )                             
+                 { 
+				     SX1276Read( REG_LR_HOPCHANNEL, &SX1276LR->RegHopChannel );
+					 SX1276LoRaSetRFFrequency( HoppingFrequencies[SX1276LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] );
+				 }
+				 // Clear Irq
+				 SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE  );           
+				 RFLRState = RFLR_STATE_RX_DONE;
+			  }
+			  //if( DIO2 == 1 )         // FHSS Changed Channel
+			  if(regValue & (1<<1))                                               
+			  {
+			      RxTimeoutTimer = GET_TICK_COUNT( );
+			      if( LoRaSettings.FreqHopOn == true )
+				  {
+					  SX1276Read( REG_LR_HOPCHANNEL, &SX1276LR->RegHopChannel );
+					  SX1276LoRaSetRFFrequency( HoppingFrequencies[SX1276LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] );
+				  }
+					// Clear Irq
+				  SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); 
+				  //RxGain = SX1276LoRaReadRxGain( );
+			  }
+			  if( LoRaSettings.RxSingleOn == true )    // Rx single mode                             
+			  {
+			     if( ( GET_TICK_COUNT( ) - RxTimeoutTimer ) > PacketTimeout )       
+				 {
+				      RFLRState = RFLR_STATE_RX_TIMEOUT;                            
+				 }
+			 }
+             break;
+		case RFLR_STATE_RX_DONE:                                                    
+			                                                                        
+			 																		
+		     SX1276Read( REG_LR_IRQFLAGS, &SX1276LR->RegIrqFlags );
+			 if( ( SX1276LR->RegIrqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )   
+			 {      
+				 // Clear Irq
+				 SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );     
+				 if( LoRaSettings.RxSingleOn == true ) // Rx single mode                             
+				 {
+					RFLRState = RFLR_STATE_RX_INIT;                                
+				 }
+				 else
+				 { 
+					RFLRState = RFLR_STATE_RX_RUNNING;
+				 }
+				 break;
+		     }
+		     
+/*			 {
+				 uint8_t rxSnrEstimate;
+				 
+				 SX1276Read( REG_LR_PKTSNRVALUE, &rxSnrEstimate );                     
+				 if( rxSnrEstimate & 0x80 )  
+				 {
+
+					 RxPacketSnrEstimate = ( ( ~rxSnrEstimate + 1 ) & 0xFF ) >> 2;     
+					 RxPacketSnrEstimate = -RxPacketSnrEstimate;
+				 }
+				 else
+				 {
+					 RxPacketSnrEstimate = ( rxSnrEstimate & 0xFF ) >> 2;
+				 }
+			}        
+			if( LoRaSettings.RFFrequency < 860000000 ) 
+			{    
+				if( RxPacketSnrEstimate < 0 )          
+				{
+					
+					RxPacketRssiValue = NOISE_ABSOLUTE_ZERO + 10.0 * SignalBwLog[LoRaSettings.SignalBw] + NOISE_FIGURE_LF + ( double )RxPacketSnrEstimate;
+				}
+				else
+				{    
+					SX1276Read( REG_LR_PKTRSSIVALUE, &SX1276LR->RegPktRssiValue );
+					RxPacketRssiValue = RssiOffsetLF[LoRaSettings.SignalBw] + ( double )SX1276LR->RegPktRssiValue;
+				}
+			}
+			else                                        
+			{    
+				if( RxPacketSnrEstimate < 0 )
+				{
+					RxPacketRssiValue = NOISE_ABSOLUTE_ZERO + 10.0 * SignalBwLog[LoRaSettings.SignalBw] + NOISE_FIGURE_HF + ( double )RxPacketSnrEstimate;
+				}
+				else
+				{    
+					SX1276Read( REG_LR_PKTRSSIVALUE, &SX1276LR->RegPktRssiValue );
+					RxPacketRssiValue = RssiOffsetHF[LoRaSettings.SignalBw] + ( double )SX1276LR->RegPktRssiValue;
+				}
+			}*/
+			if( LoRaSettings.RxSingleOn == true )     // Rx single mode                                
+			{
+			    SX1276LR->RegFifoAddrPtr = SX1276LR->RegFifoRxBaseAddr;       
+				SX1276Write( REG_LR_FIFOADDRPTR, SX1276LR->RegFifoAddrPtr );          
+			    if( LoRaSettings.ImplicitHeaderOn == true )                           
+				{
+				    RxPacketSize = SX1276LR->RegPayloadLength;
+				    SX1276ReadFifo( RFBuffer, SX1276LR->RegPayloadLength );           
+				}
+				else	
+				{
+					
+				    SX1276Read( REG_LR_NBRXBYTES, &SX1276LR->RegNbRxBytes );
+					RxPacketSize = SX1276LR->RegNbRxBytes;
+				    SX1276ReadFifo( RFBuffer, SX1276LR->RegNbRxBytes );
+			     }
+			 }
+			 else     // Rx continuous mode                                                                
+			 {
+			     
+				 SX1276Read( REG_LR_FIFORXCURRENTADDR, &SX1276LR->RegFifoRxCurrentAddr );
+				 if( LoRaSettings.ImplicitHeaderOn == true )
+				 {
+					 RxPacketSize = SX1276LR->RegPayloadLength;
+					 SX1276LR->RegFifoAddrPtr = SX1276LR->RegFifoRxCurrentAddr;
+					 SX1276Write( REG_LR_FIFOADDRPTR, SX1276LR->RegFifoAddrPtr );
+				     SX1276ReadFifo( RFBuffer, SX1276LR->RegPayloadLength );
+				 }
+				 else
+				 {
+					 SX1276Read( REG_LR_NBRXBYTES, &SX1276LR->RegNbRxBytes );
+					 RxPacketSize = SX1276LR->RegNbRxBytes;
+					 SX1276LR->RegFifoAddrPtr = SX1276LR->RegFifoRxCurrentAddr;
+					 SX1276Write( REG_LR_FIFOADDRPTR, SX1276LR->RegFifoAddrPtr );
+					 SX1276ReadFifo( RFBuffer, SX1276LR->RegNbRxBytes );
+				 }
+			 }  
+			 if( LoRaSettings.RxSingleOn == true )   // Rx single mode                                  
+			 { 
+				 RFLRState = RFLR_STATE_RX_INIT;
+			 }
+			 else  // Rx continuous mode                                                                    
+			 { 
+				 RFLRState = RFLR_STATE_RX_RUNNING;
+			 }
+			 Rx_Time_End=TickCounter;
+			 result = RF_RX_DONE;
+			 break;
+		case RFLR_STATE_RX_TIMEOUT:                                                   
+		     RFLRState = RFLR_STATE_RX_INIT;                                          
+		     result = RF_RX_TIMEOUT;
+		     break;
+		case RFLR_STATE_TX_INIT:                                                      
+																					  
+		     Tx_Time_Start=TickCounter;
+			 SX1276LoRaSetOpMode( RFLR_OPMODE_STANDBY );                              
+			 if( LoRaSettings.FreqHopOn == true )                                     
+			 {
+				 SX1276LR->RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT          |
+											 RFLR_IRQFLAGS_RXDONE             |
+											 RFLR_IRQFLAGS_PAYLOADCRCERROR    |
+											 RFLR_IRQFLAGS_VALIDHEADER        |
+										   //RFLR_IRQFLAGS_TXDONE             |
+											 RFLR_IRQFLAGS_CADDONE            |
+										   //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+											 RFLR_IRQFLAGS_CADDETECTED;
+				 SX1276LR->RegHopPeriod = LoRaSettings.HopPeriod;
+				 SX1276Read( REG_LR_HOPCHANNEL, &SX1276LR->RegHopChannel );
+				 SX1276LoRaSetRFFrequency( HoppingFrequencies[SX1276LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] );
+			 }
+			 else
+			 {
+				 
+				 SX1276LR->RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT          |
+									         RFLR_IRQFLAGS_RXDONE             |
+											 RFLR_IRQFLAGS_PAYLOADCRCERROR    |
+											 RFLR_IRQFLAGS_VALIDHEADER        |
+										   //RFLR_IRQFLAGS_TXDONE             |
+											 RFLR_IRQFLAGS_CADDONE            |
+											 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+											 RFLR_IRQFLAGS_CADDETECTED;             
+				 SX1276LR->RegHopPeriod = 0;
+			 }
+			 SX1276Write( REG_LR_HOPPERIOD, SX1276LR->RegHopPeriod );                
+			 SX1276Write( REG_LR_IRQFLAGSMASK, SX1276LR->RegIrqFlagsMask );      
+			 // Initializes the payload size
+			 SX1276LR->RegPayloadLength = TxPacketSize;                              
+			 SX1276Write( REG_LR_PAYLOADLENGTH, SX1276LR->RegPayloadLength );
+			
+			 SX1276LR->RegFifoTxBaseAddr = 0x00;  // Full buffer used for Tx                                   
+			 SX1276Write( REG_LR_FIFOTXBASEADDR, SX1276LR->RegFifoTxBaseAddr );
+
+			 SX1276LR->RegFifoAddrPtr = SX1276LR->RegFifoTxBaseAddr;
+			 SX1276Write( REG_LR_FIFOADDRPTR, SX1276LR->RegFifoAddrPtr );
+			  // Write payload buffer to LORA modem
+			 SX1276WriteFifo( TFBuffer, SX1276LR->RegPayloadLength );                
+			 								// TxDone               RxTimeout                   FhssChangeChannel          ValidHeader         
+			 SX1276LR->RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_01;
+											// PllLock              Mode Ready
+			 SX1276LR->RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_01 | RFLR_DIOMAPPING2_DIO5_00;
+			
+			 SX1276WriteBuffer( REG_LR_DIOMAPPING1, &SX1276LR->RegDioMapping1, 2 );
+
+			 SX1276LoRaSetOpMode( RFLR_OPMODE_TRANSMITTER );
+
+			 RFLRState = RFLR_STATE_TX_RUNNING;
+			 break;
+		case RFLR_STATE_TX_RUNNING:                                            
+			 SX1276Read(0x12,&regValue);
+		     //if( DIO0 == 1 )    // TxDone
+			 if(regValue & (1<<3))
+			 {
+		         // Clear Irq
+				 SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );          
+				 RFLRState = RFLR_STATE_TX_DONE;   
+			 }	
+			 //if( DIO2 == 1 )   // FHSS Changed Channel
+			 if(regValue & (1<<3))
+			 {
+				 if( LoRaSettings.FreqHopOn == true )
+				 {
+					 SX1276Read( REG_LR_HOPCHANNEL, &SX1276LR->RegHopChannel );
+					 SX1276LoRaSetRFFrequency( HoppingFrequencies[SX1276LR->RegHopChannel & RFLR_HOPCHANNEL_CHANNEL_MASK] );
+				 }		
+				 // Clear Irq		
+				 SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL ); 
+			 }
+			 break;
+		case RFLR_STATE_TX_DONE:                                                
+             Tx_Time_End=TickCounter;			
+			 SX1276LoRaSetOpMode( RFLR_OPMODE_STANDBY );                         
+			 RFLRState = RFLR_STATE_IDLE;
+			 result = RF_TX_DONE;
+			 break;
+		case RFLR_STATE_CAD_INIT:
+		// optimize the power consumption by switching off the transmitter as soon as the packet has been sent                                               
+			 SX1276LoRaSetOpMode( RFLR_OPMODE_STANDBY );
+			 SX1276LR->RegIrqFlagsMask = RFLR_IRQFLAGS_RXTIMEOUT           |
+										 RFLR_IRQFLAGS_RXDONE              |
+										 RFLR_IRQFLAGS_PAYLOADCRCERROR     |
+										 RFLR_IRQFLAGS_VALIDHEADER         |
+										 RFLR_IRQFLAGS_TXDONE              |
+									     //RFLR_IRQFLAGS_CADDONE             |
+										 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL;
+									     //RFLR_IRQFLAGS_CADDETECTED;
+			 SX1276Write( REG_LR_IRQFLAGSMASK, SX1276LR->RegIrqFlagsMask );
+
+										 // RxDone                   RxTimeout                   FhssChangeChannel           CadDone
+			 SX1276LR->RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_00;
+										 // CAD Detected              ModeReady
+			 SX1276LR->RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_00 | RFLR_DIOMAPPING2_DIO5_00;
+			 SX1276WriteBuffer( REG_LR_DIOMAPPING1, &SX1276LR->RegDioMapping1, 2 );
+
+
+			 SX1276LoRaSetOpMode( RFLR_OPMODE_CAD );
+			 RFLRState = RFLR_STATE_CAD_RUNNING;
+
+			 break;
+		case RFLR_STATE_CAD_RUNNING:
+			 SX1276Read(0x12,&regValue);                                         
+			 int cad_done = regValue & (1<<2);
+			 int cad_detected = regValue & (1<<0);
+
+			 if( cad_done  ) //CAD Done interrupt
+			 { 
+				SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE  );
+				if( cad_detected  ) // CAD Detected interrupt
+				{
+					SX1276Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED  );
+					//CAD detected, we have a LoRa preamble
+					RFLRState = RFLR_STATE_RX_INIT;
+					result = RF_CHANNEL_ACTIVITY_DETECTED;
+                } 
+				else
+				{    
+					// The device goes in Standby Mode automatically    
+					RFLRState = RFLR_STATE_IDLE;
+					result = RF_CHANNEL_EMPTY;
+				}
+			 }   
+			 break;			
+        default:
+             break;
+    } 
+    return result;
+}
+
+uint32_t SX1276LoraChannelEmpty( void )
+{
+	uint32_t result = 0;
+	RFLRState = RFLR_STATE_CAD_INIT;
+	SX1276LoRaProcess();
+    while(RFLRState == RFLR_STATE_CAD_RUNNING)
+	{
+		//KPrintf("\nLora--SX1276LoRaProcess()");
+		result = SX1276LoRaProcess();
+	}
+
+	if(result == RF_CHANNEL_EMPTY)
+	{
+		KPrintf("\nLora--信道可用（RF_CHANNEL_EMPTY）\n");
+		return 0;
+	}
+	else if(result == RF_CHANNEL_ACTIVITY_DETECTED)
+	{
+		KPrintf("\nLora--信道正被占用（RF_CHANNEL_ACTIVITY_DETECTED）\n");
+		return 1;
+	}
+	else
+	{
+		return 2;
+	}
+}
+
+#endif // USE_SX1276_RADIO

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276-LoRa.h

@@ -0,0 +1,820 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Original Copyright (C) SEMTECH S.A.
+ * Modified Copyright (C) 2020 AIIT XUOS Lab
+ */
+/*! 
+ * \file       sx1276-LoRa.h
+ * \brief      SX1276 RF chip driver mode LoRa
+ *
+ * \version    2.0.0 
+ * \date       Nov 21 2012
+ * \author     Miguel Luis
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276-LoRa.h
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+#ifndef __SX1276_LORA_H__
+#define __SX1276_LORA_H__
+
+#include "stdint.h"
+#include "stdbool.h"
+
+
+//SX1276一些配置参数设置
+typedef struct sLoRaSettings
+{
+    uint32_t RFFrequency;			    //无线通信频率
+    int8_t Power;                       //功率
+    uint8_t SignalBw;                   //LORA 带宽[0: 7.8 kHz, 1: 10.4 kHz, 2: 15.6 kHz, 3: 20.8 kHz, 4: 31.2 kHz,
+                                        //5: 41.6 kHz, 6: 62.5 kHz, 7: 125 kHz, 8: 250 kHz, 9: 500 kHz, other: Reserved]  
+    uint8_t SpreadingFactor;            //扩频因子 LORA [6: 64, 7: 128, 8: 256, 9: 512, 10: 1024, 11: 2048, 12: 4096  chips]
+    uint8_t ErrorCoding;                //LORA 纠错码 [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+    bool CrcOn;                         //CRC效验开关 [0: OFF, 1: ON]
+    bool ImplicitHeaderOn;              //隐藏头部信息开关 [0: OFF, 1: ON]
+    bool RxSingleOn;                    //接收单次模式\连续模式配置[0: Continuous, 1 Single]
+    bool FreqHopOn;                     //跳频模式开关 [0: OFF, 1: ON]
+    uint8_t HopPeriod;                  //跳频之间的周期长度 Hops every frequency hopping period symbols
+    uint32_t TxPacketTimeout;           //最大发送时间
+    uint32_t RxPacketTimeout;           //最大接收时间
+    uint8_t PayloadLength;              //数据长度
+}tLoRaSettings;
+
+//RF数据包大小(模块配备了256Byte的RAM缓存，该缓存仅能通过LoRa模式访问)
+#define RF_BUFFER_SIZE_MAX                          256
+#define RF_BUFFER_SIZE                              256
+
+
+//LoRa的返回值
+typedef enum
+{
+    RFLR_STATE_IDLE,
+    RFLR_STATE_RX_INIT,
+    RFLR_STATE_RX_RUNNING,
+    RFLR_STATE_RX_DONE,
+    RFLR_STATE_RX_TIMEOUT,
+    RFLR_STATE_TX_INIT,
+    RFLR_STATE_TX_RUNNING,
+    RFLR_STATE_TX_DONE,
+    RFLR_STATE_TX_TIMEOUT,
+    RFLR_STATE_CAD_INIT,
+    RFLR_STATE_CAD_RUNNING,
+}tRFLRStates;
+
+
+//SX1276 definitions
+#define XTAL_FREQ                                   32000000
+#define FREQ_STEP                                   61.03515625
+
+/*LoRa模式寄存器映射*/
+//SX1276内部寄存器地址
+#define REG_LR_FIFO                                 0x00    //FIFO 数据输入/输出。当器件处于睡眠模式时，FIFO被清零，无法访问。
+
+//通用寄存器
+#define REG_LR_OPMODE                               0x01    //关于模式选择相关的寄存器  
+#define REG_LR_BANDSETTING                          0x04    
+#define REG_LR_FRFMSB                               0x06    //RF 载波频率最高有效位
+#define REG_LR_FRFMID                               0x07    //RF 载波频率中间有效位
+#define REG_LR_FRFLSB                               0x08    //RF 载波频率最低有效位
+
+//RF模块寄存器
+#define REG_LR_PACONFIG                             0x09    
+#define REG_LR_PARAMP                               0x0A    
+#define REG_LR_OCP                                  0x0B 
+#define REG_LR_LNA                                  0x0C 
+
+//LoRa页面寄存器
+#define REG_LR_FIFOADDRPTR                          0x0D 
+#define REG_LR_FIFOTXBASEADDR                       0x0E 
+#define REG_LR_FIFORXBASEADDR                       0x0F 
+#define REG_LR_FIFORXCURRENTADDR                    0x10 
+#define REG_LR_IRQFLAGSMASK                         0x11  //IAQ标志屏蔽 
+#define REG_LR_IRQFLAGS                             0x12 
+#define REG_LR_NBRXBYTES                            0x13 
+#define REG_LR_RXHEADERCNTVALUEMSB                  0x14 
+#define REG_LR_RXHEADERCNTVALUELSB                  0x15 
+#define REG_LR_RXPACKETCNTVALUEMSB                  0x16 
+#define REG_LR_RXPACKETCNTVALUELSB                  0x17 
+#define REG_LR_MODEMSTAT                            0x18 
+#define REG_LR_PKTSNRVALUE                          0x19 
+#define REG_LR_PKTRSSIVALUE                         0x1A 
+#define REG_LR_RSSIVALUE                            0x1B 
+#define REG_LR_HOPCHANNEL                           0x1C 
+#define REG_LR_MODEMCONFIG1                         0x1D 
+#define REG_LR_MODEMCONFIG2                         0x1E 
+#define REG_LR_SYMBTIMEOUTLSB                       0x1F 
+#define REG_LR_PREAMBLEMSB                          0x20 
+#define REG_LR_PREAMBLELSB                          0x21 
+#define REG_LR_PAYLOADLENGTH                        0x22 
+#define REG_LR_PAYLOADMAXLENGTH                     0x23 
+#define REG_LR_HOPPERIOD                            0x24 
+#define REG_LR_FIFORXBYTEADDR                       0x25
+#define REG_LR_MODEMCONFIG3                         0x26
+/*以上是LoRa模式寄存器映射*/
+
+//IO控制寄存器（关于DI00-DI05的映射设置）
+#define REG_LR_DIOMAPPING1                          0x40
+#define REG_LR_DIOMAPPING2                          0x41
+
+//版本寄存器
+#define REG_LR_VERSION                              0x42
+
+//附加寄存器
+#define REG_LR_PLLHOP                               0x44
+#define REG_LR_TCXO                                 0x4B
+#define REG_LR_PADAC                                0x4D
+#define REG_LR_FORMERTEMP                           0x5B
+#define REG_LR_BITRATEFRAC                          0x5D
+#define REG_LR_AGCREF                               0x61
+#define REG_LR_AGCTHRESH1                           0x62
+#define REG_LR_AGCTHRESH2                           0x63
+#define REG_LR_AGCTHRESH3                           0x64
+
+//与模式选择相关的宏定义 RegOpMode(寄存器地址0X01)
+#define RFLR_OPMODE_LONGRANGEMODE_MASK              0x7F 
+#define RFLR_OPMODE_LONGRANGEMODE_OFF               0x00 // Default
+#define RFLR_OPMODE_LONGRANGEMODE_ON                0x80 
+
+#define RFLR_OPMODE_ACCESSSHAREDREG_MASK            0xBF 
+#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE          0x40 
+#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE         0x00 // Default
+
+#define RFLR_OPMODE_FREQMODE_ACCESS_MASK            0xF7
+#define RFLR_OPMODE_FREQMODE_ACCESS_LF              0x08 // Default
+#define RFLR_OPMODE_FREQMODE_ACCESS_HF              0x00 
+
+#define RFLR_OPMODE_MASK                            0xF8 
+#define RFLR_OPMODE_SLEEP                           0x00 //睡眠模式
+#define RFLR_OPMODE_STANDBY                         0x01 //待机模式
+#define RFLR_OPMODE_SYNTHESIZER_TX                  0x02 //频率合成器转换至Tx频率
+#define RFLR_OPMODE_TRANSMITTER                     0x03 //发送模式
+#define RFLR_OPMODE_SYNTHESIZER_RX                  0x04 //频率合成器转换至Rx频率
+#define RFLR_OPMODE_RECEIVER                        0x05 //接收模式
+
+#define RFLR_OPMODE_RECEIVER_SINGLE                 0x06 //单次接收模式   
+#define RFLR_OPMODE_CAD                             0x07 //CAD模式 
+
+//与位带操作相关的宏定义
+#define RFLR_BANDSETTING_MASK                       0x3F 
+#define RFLR_BANDSETTING_AUTO                       0x00 // Default
+#define RFLR_BANDSETTING_DIV_BY_1                   0x40
+#define RFLR_BANDSETTING_DIV_BY_2                   0x80
+#define RFLR_BANDSETTING_DIV_BY_6                   0xC0
+
+//射频载波频率设置相关宏定义 RegFrf (MHz)(寄存器地址0x06，0x07,0x08)
+#define RFLR_FRFMSB_434_MHZ                         0x6C // Default
+#define RFLR_FRFMID_434_MHZ                         0x80 // Default
+#define RFLR_FRFLSB_434_MHZ                         0x00 // Default
+
+#define RFLR_FRFMSB_470_MHZ                         0x73 // Default
+#define RFLR_FRFMID_470_MHZ                         0xBB // Default
+#define RFLR_FRFLSB_470_MHZ                         0xBB // Default
+
+#define RFLR_FRFMSB_863_MHZ                         0xD7
+#define RFLR_FRFMID_863_MHZ                         0xC0
+#define RFLR_FRFLSB_863_MHZ                         0x00
+#define RFLR_FRFMSB_864_MHZ                         0xD8
+#define RFLR_FRFMID_864_MHZ                         0x00
+#define RFLR_FRFLSB_864_MHZ                         0x00
+#define RFLR_FRFMSB_865_MHZ                         0xD8
+#define RFLR_FRFMID_865_MHZ                         0x40
+#define RFLR_FRFLSB_865_MHZ                         0x00
+#define RFLR_FRFMSB_866_MHZ                         0xD8
+#define RFLR_FRFMID_866_MHZ                         0x80
+#define RFLR_FRFLSB_866_MHZ                         0x00
+#define RFLR_FRFMSB_867_MHZ                         0xD8
+#define RFLR_FRFMID_867_MHZ                         0xC0
+#define RFLR_FRFLSB_867_MHZ                         0x00
+#define RFLR_FRFMSB_868_MHZ                         0xD9
+#define RFLR_FRFMID_868_MHZ                         0x00
+#define RFLR_FRFLSB_868_MHZ                         0x00
+#define RFLR_FRFMSB_869_MHZ                         0xD9
+#define RFLR_FRFMID_869_MHZ                         0x40
+#define RFLR_FRFLSB_869_MHZ                         0x00
+#define RFLR_FRFMSB_870_MHZ                         0xD9
+#define RFLR_FRFMID_870_MHZ                         0x80
+#define RFLR_FRFLSB_870_MHZ                         0x00
+
+#define RFLR_FRFMSB_902_MHZ                         0xE1
+#define RFLR_FRFMID_902_MHZ                         0x80
+#define RFLR_FRFLSB_902_MHZ                         0x00
+#define RFLR_FRFMSB_903_MHZ                         0xE1
+#define RFLR_FRFMID_903_MHZ                         0xC0
+#define RFLR_FRFLSB_903_MHZ                         0x00
+#define RFLR_FRFMSB_904_MHZ                         0xE2
+#define RFLR_FRFMID_904_MHZ                         0x00
+#define RFLR_FRFLSB_904_MHZ                         0x00
+#define RFLR_FRFMSB_905_MHZ                         0xE2
+#define RFLR_FRFMID_905_MHZ                         0x40
+#define RFLR_FRFLSB_905_MHZ                         0x00
+#define RFLR_FRFMSB_906_MHZ                         0xE2
+#define RFLR_FRFMID_906_MHZ                         0x80
+#define RFLR_FRFLSB_906_MHZ                         0x00
+#define RFLR_FRFMSB_907_MHZ                         0xE2
+#define RFLR_FRFMID_907_MHZ                         0xC0
+#define RFLR_FRFLSB_907_MHZ                         0x00
+#define RFLR_FRFMSB_908_MHZ                         0xE3
+#define RFLR_FRFMID_908_MHZ                         0x00
+#define RFLR_FRFLSB_908_MHZ                         0x00
+#define RFLR_FRFMSB_909_MHZ                         0xE3
+#define RFLR_FRFMID_909_MHZ                         0x40
+#define RFLR_FRFLSB_909_MHZ                         0x00
+#define RFLR_FRFMSB_910_MHZ                         0xE3
+#define RFLR_FRFMID_910_MHZ                         0x80
+#define RFLR_FRFLSB_910_MHZ                         0x00
+#define RFLR_FRFMSB_911_MHZ                         0xE3
+#define RFLR_FRFMID_911_MHZ                         0xC0
+#define RFLR_FRFLSB_911_MHZ                         0x00
+#define RFLR_FRFMSB_912_MHZ                         0xE4
+#define RFLR_FRFMID_912_MHZ                         0x00
+#define RFLR_FRFLSB_912_MHZ                         0x00
+#define RFLR_FRFMSB_913_MHZ                         0xE4
+#define RFLR_FRFMID_913_MHZ                         0x40
+#define RFLR_FRFLSB_913_MHZ                         0x00
+#define RFLR_FRFMSB_914_MHZ                         0xE4
+#define RFLR_FRFMID_914_MHZ                         0x80
+#define RFLR_FRFLSB_914_MHZ                         0x00
+#define RFLR_FRFMSB_915_MHZ                         0xE4  // Default
+#define RFLR_FRFMID_915_MHZ                         0xC0  // Default
+#define RFLR_FRFLSB_915_MHZ                         0x00  // Default
+#define RFLR_FRFMSB_916_MHZ                         0xE5
+#define RFLR_FRFMID_916_MHZ                         0x00
+#define RFLR_FRFLSB_916_MHZ                         0x00
+#define RFLR_FRFMSB_917_MHZ                         0xE5
+#define RFLR_FRFMID_917_MHZ                         0x40
+#define RFLR_FRFLSB_917_MHZ                         0x00
+#define RFLR_FRFMSB_918_MHZ                         0xE5
+#define RFLR_FRFMID_918_MHZ                         0x80
+#define RFLR_FRFLSB_918_MHZ                         0x00
+#define RFLR_FRFMSB_919_MHZ                         0xE5
+#define RFLR_FRFMID_919_MHZ                         0xC0
+#define RFLR_FRFLSB_919_MHZ                         0x00
+#define RFLR_FRFMSB_920_MHZ                         0xE6
+#define RFLR_FRFMID_920_MHZ                         0x00
+#define RFLR_FRFLSB_920_MHZ                         0x00
+#define RFLR_FRFMSB_921_MHZ                         0xE6
+#define RFLR_FRFMID_921_MHZ                         0x40
+#define RFLR_FRFLSB_921_MHZ                         0x00
+#define RFLR_FRFMSB_922_MHZ                         0xE6
+#define RFLR_FRFMID_922_MHZ                         0x80
+#define RFLR_FRFLSB_922_MHZ                         0x00
+#define RFLR_FRFMSB_923_MHZ                         0xE6
+#define RFLR_FRFMID_923_MHZ                         0xC0
+#define RFLR_FRFLSB_923_MHZ                         0x00
+#define RFLR_FRFMSB_924_MHZ                         0xE7
+#define RFLR_FRFMID_924_MHZ                         0x00
+#define RFLR_FRFLSB_924_MHZ                         0x00
+#define RFLR_FRFMSB_925_MHZ                         0xE7
+#define RFLR_FRFMID_925_MHZ                         0x40
+#define RFLR_FRFLSB_925_MHZ                         0x00
+#define RFLR_FRFMSB_926_MHZ                         0xE7
+#define RFLR_FRFMID_926_MHZ                         0x80
+#define RFLR_FRFLSB_926_MHZ                         0x00
+#define RFLR_FRFMSB_927_MHZ                         0xE7
+#define RFLR_FRFMID_927_MHZ                         0xC0
+#define RFLR_FRFLSB_927_MHZ                         0x00
+#define RFLR_FRFMSB_928_MHZ                         0xE8
+#define RFLR_FRFMID_928_MHZ                         0x00
+#define RFLR_FRFLSB_928_MHZ                         0x00
+
+//PA（功率放大器） 选择和输出功率控制设置相关宏定义 RegPaConfig（寄存器地址0X09）
+#define RFLR_PACONFIG_PASELECT_MASK                 0x7F 
+#define RFLR_PACONFIG_PASELECT_PABOOST              0x80 
+#define RFLR_PACONFIG_PASELECT_RFO                  0x00 // Default
+
+#define RFLR_PACONFIG_MAX_POWER_MASK                0x8F
+
+#define RFLR_PACONFIG_OUTPUTPOWER_MASK              0xF0 
+ 
+//PA（功率放大器） 斜升/斜降时间和低相噪设置相关定义 RegPaRamp（寄存器地址0X0A）
+#define RFLR_PARAMP_TXBANDFORCE_MASK                0xEF 
+#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL            0x10 
+#define RFLR_PARAMP_TXBANDFORCE_AUTO                0x00 // Default
+
+#define RFLR_PARAMP_MASK                            0xF0 
+#define RFLR_PARAMP_3400_US                         0x00 
+#define RFLR_PARAMP_2000_US                         0x01 
+#define RFLR_PARAMP_1000_US                         0x02
+#define RFLR_PARAMP_0500_US                         0x03 
+#define RFLR_PARAMP_0250_US                         0x04 
+#define RFLR_PARAMP_0125_US                         0x05 
+#define RFLR_PARAMP_0100_US                         0x06 
+#define RFLR_PARAMP_0062_US                         0x07 
+#define RFLR_PARAMP_0050_US                         0x08 
+#define RFLR_PARAMP_0040_US                         0x09 // Default
+#define RFLR_PARAMP_0031_US                         0x0A 
+#define RFLR_PARAMP_0025_US                         0x0B 
+#define RFLR_PARAMP_0020_US                         0x0C 
+#define RFLR_PARAMP_0015_US                         0x0D 
+#define RFLR_PARAMP_0012_US                         0x0E 
+#define RFLR_PARAMP_0010_US                         0x0F 
+
+//过流保护控制设置相关宏定义 RegOcp（寄存器地址0X0B）
+#define RFLR_OCP_MASK                               0xDF 
+#define RFLR_OCP_ON                                 0x20 // Default
+#define RFLR_OCP_OFF                                0x00   
+
+#define RFLR_OCP_TRIM_MASK                          0xE0
+#define RFLR_OCP_TRIM_045_MA                        0x00
+#define RFLR_OCP_TRIM_050_MA                        0x01   
+#define RFLR_OCP_TRIM_055_MA                        0x02 
+#define RFLR_OCP_TRIM_060_MA                        0x03 
+#define RFLR_OCP_TRIM_065_MA                        0x04 
+#define RFLR_OCP_TRIM_070_MA                        0x05 
+#define RFLR_OCP_TRIM_075_MA                        0x06 
+#define RFLR_OCP_TRIM_080_MA                        0x07  
+#define RFLR_OCP_TRIM_085_MA                        0x08
+#define RFLR_OCP_TRIM_090_MA                        0x09 
+#define RFLR_OCP_TRIM_095_MA                        0x0A 
+#define RFLR_OCP_TRIM_100_MA                        0x0B  // Default
+#define RFLR_OCP_TRIM_105_MA                        0x0C 
+#define RFLR_OCP_TRIM_110_MA                        0x0D 
+#define RFLR_OCP_TRIM_115_MA                        0x0E 
+#define RFLR_OCP_TRIM_120_MA                        0x0F 
+#define RFLR_OCP_TRIM_130_MA                        0x10
+#define RFLR_OCP_TRIM_140_MA                        0x11   
+#define RFLR_OCP_TRIM_150_MA                        0x12 
+#define RFLR_OCP_TRIM_160_MA                        0x13 
+#define RFLR_OCP_TRIM_170_MA                        0x14 
+#define RFLR_OCP_TRIM_180_MA                        0x15 
+#define RFLR_OCP_TRIM_190_MA                        0x16 
+#define RFLR_OCP_TRIM_200_MA                        0x17  
+#define RFLR_OCP_TRIM_210_MA                        0x18
+#define RFLR_OCP_TRIM_220_MA                        0x19 
+#define RFLR_OCP_TRIM_230_MA                        0x1A 
+#define RFLR_OCP_TRIM_240_MA                        0x1B
+
+//LNA（低噪声放大器 ）设置相关宏定义 RegLna（寄存器地址0X0C）
+#define RFLR_LNA_GAIN_MASK                          0x1F 
+#define RFLR_LNA_GAIN_G1                            0x20 // Default
+#define RFLR_LNA_GAIN_G2                            0x40 
+#define RFLR_LNA_GAIN_G3                            0x60 
+#define RFLR_LNA_GAIN_G4                            0x80 
+#define RFLR_LNA_GAIN_G5                            0xA0 
+#define RFLR_LNA_GAIN_G6                            0xC0 
+
+#define RFLR_LNA_BOOST_LF_MASK                      0xE7 
+#define RFLR_LNA_BOOST_LF_DEFAULT                   0x00 // Default
+#define RFLR_LNA_BOOST_LF_GAIN                      0x08 
+#define RFLR_LNA_BOOST_LF_IP3                       0x10 
+#define RFLR_LNA_BOOST_LF_BOOST                     0x18 
+
+#define RFLR_LNA_RXBANDFORCE_MASK                   0xFB 
+#define RFLR_LNA_RXBANDFORCE_BAND_SEL               0x04
+#define RFLR_LNA_RXBANDFORCE_AUTO                   0x00 // Default
+
+#define RFLR_LNA_BOOST_HF_MASK                      0xFC 
+#define RFLR_LNA_BOOST_HF_OFF                       0x00 // Default
+#define RFLR_LNA_BOOST_HF_ON                        0x03 
+
+
+//FIFO 数据缓冲区中 SPI 接口地址指针（寄存器地址0X0D）
+#define RFLR_FIFOADDRPTR                            0x00 // Default
+
+//发送信息的起始位置
+#define RFLR_FIFOTXBASEADDR                         0x80 // Default
+
+//接收信息的起始位置
+#define RFLR_FIFORXBASEADDR                         0x00 // Default
+
+/*!
+ * RegFifoRxCurrentAddr (Read Only)
+ */
+
+//关于中断屏蔽相关的宏定义
+#define RFLR_IRQFLAGS_RXTIMEOUT_MASK                0x80 
+#define RFLR_IRQFLAGS_RXDONE_MASK                   0x40 
+#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK          0x20 
+#define RFLR_IRQFLAGS_VALIDHEADER_MASK              0x10 
+#define RFLR_IRQFLAGS_TXDONE_MASK                   0x08 
+#define RFLR_IRQFLAGS_CADDONE_MASK                  0x04 
+#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK       0x02 
+#define RFLR_IRQFLAGS_CADDETECTED_MASK              0x01 
+
+//关于中断打开相关的宏定义
+#define RFLR_IRQFLAGS_RXTIMEOUT                     0x80 
+#define RFLR_IRQFLAGS_RXDONE                        0x40 
+#define RFLR_IRQFLAGS_PAYLOADCRCERROR               0x20 
+#define RFLR_IRQFLAGS_VALIDHEADER                   0x10 
+#define RFLR_IRQFLAGS_TXDONE                        0x08 
+#define RFLR_IRQFLAGS_CADDONE                       0x04 
+#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL            0x02 
+#define RFLR_IRQFLAGS_CADDETECTED                   0x01 
+
+
+
+/*!
+ * RegFifoRxNbBytes (Read Only)    //
+ */
+
+ 
+ /*!
+ * RegRxHeaderCntValueMsb (Read Only)    //
+ */
+ 
+ 
+  /*!
+ * RegRxHeaderCntValueLsb (Read Only)    //
+ */
+ 
+ 
+/*!
+ * RegRxPacketCntValueMsb (Read Only)    //
+ */
+ 
+ 
+ /*!
+ * RegRxPacketCntValueLsb (Read Only)    //
+ */
+ 
+ 
+ /*!
+ * RegModemStat (Read Only)    //
+ */
+#define RFLR_MODEMSTAT_RX_CR_MASK                   0x1F 
+#define RFLR_MODEMSTAT_MODEM_STATUS_MASK            0xE0 
+ 
+/*!
+ * RegPktSnrValue (Read Only)    //
+ */
+
+ 
+ /*!
+ * RegPktRssiValue (Read Only)    //
+ */
+ 
+ 
+/*!
+ * RegRssiValue (Read Only)    //
+ */
+
+ 
+//与信号宽度，纠错编码率，是否显示报头有关宏定义（寄存器位置0X1D）
+#define RFLR_MODEMCONFIG1_BW_MASK                   0x0F 
+
+#define RFLR_MODEMCONFIG1_BW_7_81_KHZ               0x00 
+#define RFLR_MODEMCONFIG1_BW_10_41_KHZ              0x10 
+#define RFLR_MODEMCONFIG1_BW_15_62_KHZ              0x20 
+#define RFLR_MODEMCONFIG1_BW_20_83_KHZ              0x30 
+#define RFLR_MODEMCONFIG1_BW_31_25_KHZ              0x40 
+#define RFLR_MODEMCONFIG1_BW_41_66_KHZ              0x50 
+#define RFLR_MODEMCONFIG1_BW_62_50_KHZ              0x60 
+#define RFLR_MODEMCONFIG1_BW_125_KHZ                0x70 // Default
+#define RFLR_MODEMCONFIG1_BW_250_KHZ                0x80 
+#define RFLR_MODEMCONFIG1_BW_500_KHZ                0x90 
+                                                    
+#define RFLR_MODEMCONFIG1_CODINGRATE_MASK           0xF1 
+#define RFLR_MODEMCONFIG1_CODINGRATE_4_5            0x02
+#define RFLR_MODEMCONFIG1_CODINGRATE_4_6            0x04 // Default
+#define RFLR_MODEMCONFIG1_CODINGRATE_4_7            0x06 
+#define RFLR_MODEMCONFIG1_CODINGRATE_4_8            0x08 
+                                                    
+#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK       0xFE 
+#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON         0x01 
+#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF        0x00 // Default
+
+//与扩频因子，接收模式，发送CRC开启，RX超时相关宏定义
+#define RFLR_MODEMCONFIG2_SF_MASK                   0x0F 
+#define RFLR_MODEMCONFIG2_SF_6                      0x60 
+#define RFLR_MODEMCONFIG2_SF_7                      0x70 // Default
+#define RFLR_MODEMCONFIG2_SF_8                      0x80 
+#define RFLR_MODEMCONFIG2_SF_9                      0x90 
+#define RFLR_MODEMCONFIG2_SF_10                     0xA0 
+#define RFLR_MODEMCONFIG2_SF_11                     0xB0 
+#define RFLR_MODEMCONFIG2_SF_12                     0xC0 
+
+#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK     0xF7 
+#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON       0x08 
+#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF      0x00 
+
+#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK         0xFB 
+#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON           0x04 
+#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF          0x00 // Default
+ 
+#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK       0xFC 
+#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB            0x00 // Default
+                                                    
+                                                    
+/*!                                                 
+ * RegHopChannel (Read Only)                        
+ */                                                 
+#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK       0x7F 
+#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL               0x80 
+#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED            0x00 // Default
+                                                    
+#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_MASK          0xBF
+#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_ON            0x40
+#define RFLR_HOPCHANNEL_PAYLOAD_CRC16_OFF           0x00 // Default
+
+#define RFLR_HOPCHANNEL_CHANNEL_MASK                0x3F 
+
+
+/*!
+ * RegSymbTimeoutLsb
+ */
+#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT             0x64 // Default
+
+/*!
+ * RegPreambleLengthMsb
+ */
+#define RFLR_PREAMBLELENGTHMSB                      0x00 // Default
+
+/*!
+ * RegPreambleLengthLsb
+ */
+#define RFLR_PREAMBLELENGTHLSB                      0x08 // Default
+
+/*!
+ * RegPayloadLength
+ */
+#define RFLR_PAYLOADLENGTH                          0x0E // Default
+
+/*!
+ * RegPayloadMaxLength
+ */
+#define RFLR_PAYLOADMAXLENGTH                       0xFF // Default
+
+/*!
+ * RegHopPeriod
+ */
+#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD            0x00 // Default
+
+
+/*!
+ * RegDioMapping1
+ */
+#define RFLR_DIOMAPPING1_DIO0_MASK                  0x3F
+#define RFLR_DIOMAPPING1_DIO0_00                    0x00  // Default
+#define RFLR_DIOMAPPING1_DIO0_01                    0x40
+#define RFLR_DIOMAPPING1_DIO0_10                    0x80
+#define RFLR_DIOMAPPING1_DIO0_11                    0xC0
+
+#define RFLR_DIOMAPPING1_DIO1_MASK                  0xCF
+#define RFLR_DIOMAPPING1_DIO1_00                    0x00  // Default
+#define RFLR_DIOMAPPING1_DIO1_01                    0x10
+#define RFLR_DIOMAPPING1_DIO1_10                    0x20
+#define RFLR_DIOMAPPING1_DIO1_11                    0x30
+
+#define RFLR_DIOMAPPING1_DIO2_MASK                  0xF3
+#define RFLR_DIOMAPPING1_DIO2_00                    0x00  // Default
+#define RFLR_DIOMAPPING1_DIO2_01                    0x04
+#define RFLR_DIOMAPPING1_DIO2_10                    0x08
+#define RFLR_DIOMAPPING1_DIO2_11                    0x0C
+
+#define RFLR_DIOMAPPING1_DIO3_MASK                  0xFC
+#define RFLR_DIOMAPPING1_DIO3_00                    0x00  // Default
+#define RFLR_DIOMAPPING1_DIO3_01                    0x01
+#define RFLR_DIOMAPPING1_DIO3_10                    0x02
+#define RFLR_DIOMAPPING1_DIO3_11                    0x03
+
+/*!
+ * RegDioMapping2
+ */
+#define RFLR_DIOMAPPING2_DIO4_MASK                  0x3F
+#define RFLR_DIOMAPPING2_DIO4_00                    0x00  // Default
+#define RFLR_DIOMAPPING2_DIO4_01                    0x40
+#define RFLR_DIOMAPPING2_DIO4_10                    0x80
+#define RFLR_DIOMAPPING2_DIO4_11                    0xC0
+
+#define RFLR_DIOMAPPING2_DIO5_MASK                  0xCF
+#define RFLR_DIOMAPPING2_DIO5_00                    0x00  // Default
+#define RFLR_DIOMAPPING2_DIO5_01                    0x10
+#define RFLR_DIOMAPPING2_DIO5_10                    0x20
+#define RFLR_DIOMAPPING2_DIO5_11                    0x30
+
+#define RFLR_DIOMAPPING2_MAP_MASK                   0xFE
+#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT         0x01
+#define RFLR_DIOMAPPING2_MAP_RSSI                   0x00  // Default
+
+/*!
+ * RegVersion (Read Only)
+ */
+
+/*!
+ * RegAgcRef
+ */
+
+/*!
+ * RegAgcThresh1
+ */
+
+/*!
+ * RegAgcThresh2
+ */
+
+/*!
+ * RegAgcThresh3
+ */
+ 
+/*!
+ * RegFifoRxByteAddr (Read Only)
+ */
+ 
+/*!
+ * RegPllHop
+ */
+#define RFLR_PLLHOP_FASTHOP_MASK                    0x7F
+#define RFLR_PLLHOP_FASTHOP_ON                      0x80
+#define RFLR_PLLHOP_FASTHOP_OFF                     0x00 // Default
+
+/*!
+ * RegTcxo
+ */
+#define RFLR_TCXO_TCXOINPUT_MASK                    0xEF
+#define RFLR_TCXO_TCXOINPUT_ON                      0x10
+#define RFLR_TCXO_TCXOINPUT_OFF                     0x00  // Default
+
+/*!
+ * RegPaDac
+ */
+#define RFLR_PADAC_20DBM_MASK                       0xF8
+#define RFLR_PADAC_20DBM_ON                         0x07
+#define RFLR_PADAC_20DBM_OFF                        0x04  // Default
+
+/*!
+ * RegPll
+ */
+#define RFLR_PLL_BANDWIDTH_MASK                     0x3F
+#define RFLR_PLL_BANDWIDTH_75                       0x00
+#define RFLR_PLL_BANDWIDTH_150                      0x40
+#define RFLR_PLL_BANDWIDTH_225                      0x80
+#define RFLR_PLL_BANDWIDTH_300                      0xC0  // Default
+
+/*!
+ * RegPllLowPn
+ */
+#define RFLR_PLLLOWPN_BANDWIDTH_MASK                0x3F
+#define RFLR_PLLLOWPN_BANDWIDTH_75                  0x00
+#define RFLR_PLLLOWPN_BANDWIDTH_150                 0x40
+#define RFLR_PLLLOWPN_BANDWIDTH_225                 0x80
+#define RFLR_PLLLOWPN_BANDWIDTH_300                 0xC0  // Default
+
+/*!
+ * RegModemConfig3
+ */
+#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK  0xF7 
+#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON    0x08 
+#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF   0x00 // Default
+
+#define RFLR_MODEMCONFIG3_AGCAUTO_MASK              0xFB 
+#define RFLR_MODEMCONFIG3_AGCAUTO_ON                0x04 // Default 
+#define RFLR_MODEMCONFIG3_AGCAUTO_OFF               0x00 
+
+/*!
+ * RegFormerTemp
+ */
+
+typedef struct sSX1276LR
+{
+    uint8_t RegFifo;                                // 0x00 
+    // Common settings
+    uint8_t RegOpMode;                              // 0x01 
+    uint8_t RegRes02;                               // 0x02 
+    uint8_t RegRes03;                               // 0x03 
+    uint8_t RegBandSetting;                         // 0x04 
+    uint8_t RegRes05;                               // 0x05 
+    uint8_t RegFrfMsb;                              // 0x06 
+    uint8_t RegFrfMid;                              // 0x07 
+    uint8_t RegFrfLsb;                              // 0x08 
+    // Tx settings
+    uint8_t RegPaConfig;                            // 0x09 
+    uint8_t RegPaRamp;                              // 0x0A 
+    uint8_t RegOcp;                                 // 0x0B 
+    // Rx settings
+    uint8_t RegLna;                                 // 0x0C 
+    // LoRa registers
+    uint8_t RegFifoAddrPtr;                         // 0x0D 
+    uint8_t RegFifoTxBaseAddr;                      // 0x0E 
+    uint8_t RegFifoRxBaseAddr;                      // 0x0F 
+    uint8_t RegFifoRxCurrentAddr;                   // 0x10 
+    uint8_t RegIrqFlagsMask;                        // 0x11 
+    uint8_t RegIrqFlags;                            // 0x12 
+    uint8_t RegNbRxBytes;                           // 0x13 
+    uint8_t RegRxHeaderCntValueMsb;                 // 0x14 
+    uint8_t RegRxHeaderCntValueLsb;                 // 0x15 
+    uint8_t RegRxPacketCntValueMsb;                 // 0x16 
+    uint8_t RegRxPacketCntValueLsb;                 // 0x17 
+    uint8_t RegModemStat;                           // 0x18 
+    uint8_t RegPktSnrValue;                         // 0x19 
+    uint8_t RegPktRssiValue;                        // 0x1A 
+    uint8_t RegRssiValue;                           // 0x1B 
+    uint8_t RegHopChannel;                          // 0x1C 
+    uint8_t RegModemConfig1;                        // 0x1D 
+    uint8_t RegModemConfig2;                        // 0x1E 
+    uint8_t RegSymbTimeoutLsb;                      // 0x1F 
+    uint8_t RegPreambleMsb;                         // 0x20 
+    uint8_t RegPreambleLsb;                         // 0x21 
+    uint8_t RegPayloadLength;                       // 0x22 
+    uint8_t RegMaxPayloadLength;                    // 0x23 
+    uint8_t RegHopPeriod;                           // 0x24 跳频周期
+    uint8_t RegFifoRxByteAddr;                      // 0x25
+    uint8_t RegModemConfig3;                        // 0x26
+    uint8_t RegTestReserved27[0x30 - 0x27];         // 0x27-0x30
+    uint8_t RegTestReserved31;                      // 0x31
+    uint8_t RegTestReserved32[0x40 - 0x32];         // 0x32-0x40
+    // I/O settings                
+    uint8_t RegDioMapping1;                         // 0x40 
+    uint8_t RegDioMapping2;                         // 0x41 
+    // Version
+    uint8_t RegVersion;                             // 0x42
+    // Additional settings
+    uint8_t RegAgcRef;                              // 0x43
+    uint8_t RegAgcThresh1;                          // 0x44
+    uint8_t RegAgcThresh2;                          // 0x45
+    uint8_t RegAgcThresh3;                          // 0x46
+    // Test
+    uint8_t RegTestReserved47[0x4B - 0x47];         // 0x47-0x4A
+    // Additional settings
+    uint8_t RegPllHop;                              // 0x4B
+    uint8_t RegTestReserved4C;                      // 0x4C
+    uint8_t RegPaDac;                               // 0x4D
+    // Test
+    uint8_t RegTestReserved4E[0x58-0x4E];           // 0x4E-0x57
+    // Additional settings
+    uint8_t RegTcxo;                                // 0x58
+    // Test
+    uint8_t RegTestReserved59;                      // 0x59
+    // Test
+    uint8_t RegTestReserved5B;                      // 0x5B
+    // Additional settings
+    uint8_t RegPll;                                 // 0x5C
+    // Test
+    uint8_t RegTestReserved5D;                      // 0x5D
+    // Additional settings
+    uint8_t RegPllLowPn;                            // 0x5E
+    // Test
+    uint8_t RegTestReserved5F[0x6C - 0x5F];         // 0x5F-0x6B
+    // Additional settings
+    uint8_t RegFormerTemp;                          // 0x6C
+    // Test
+    uint8_t RegTestReserved6D[0x71 - 0x6D];         // 0x6D-0x70
+}tSX1276LR;
+
+extern tSX1276LR* SX1276LR;
+
+//初始化SX1276LoRa模式
+void SX1276LoRaInit( void );
+
+//读SX1276的版本号
+void SX1276LoRaSetDefaults( void );
+
+//启用/禁用LoRa模式
+void SX1276LoRaSetLoRaOn( bool enable );
+
+//设置SX1276操作模式
+void SX1276LoRaSetOpMode( uint8_t opMode );
+
+//获取SX1276操作模式
+uint8_t SX1276LoRaGetOpMode( void );
+
+//读取SX1276低噪声放大器（信号放大）的增益， 
+uint8_t SX1276LoRaReadRxGain( void );
+
+//读取lora模式下无线信号强度
+double SX1276LoRaReadRssi( void );
+
+//获取数据时的增益值
+uint8_t SX1276LoRaGetPacketRxGain( void );
+
+//获取数据时的信噪比值，信号和噪声的比值，信噪比越高，说明信号干扰越小。
+int8_t SX1276LoRaGetPacketSnr( void );
+
+//获取数据时的无线信号强度
+double SX1276LoRaGetPacketRssi( void );
+
+//开始接收
+void SX1276LoRaStartRx( void );
+
+//接收数据
+void SX1276LoRaGetRxPacket( void *buffer, uint16_t *size );
+
+//发送数据
+void SX1276LoRaSetTxPacket( const void *buffer, uint16_t size );
+
+//得到RFLRState状态
+uint8_t SX1276LoRaGetRFState( void );
+
+//设置RFLRState状态，RFLRState的值决定了下面的函数处理哪一步的代码
+void SX1276LoRaSetRFState( uint8_t state );
+
+//SX1276模块接发收数据的处理函数
+uint32_t SX1276LoRaProcess( void );
+
+uint32_t SX1276LoraChannelEmpty( void );
+
+#endif 

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276-LoRaMisc.c

@@ -0,0 +1,420 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       sx1276-LoRaMisc.c
+ * \brief      SX1276 RF chip high level functions driver
+ *
+ * \remark     Optional support functions.
+ *             These functions are defined only to easy the change of the
+ *             parameters.
+ *             For a final firmware the radio parameters will be known so
+ *             there is no need to support all possible parameters.
+ *             Removing these functions will greatly reduce the final firmware
+ *             size.
+ *
+ * \version    2.0.0 
+ * \date       May 6 2013
+ * \author     Gregory Cristian
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276-LoRaMisc.c
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+#include "platform.h"
+
+#if defined( USE_SX1276_RADIO )
+
+#include "sx1276-Hal.h"
+#include "sx1276.h"
+
+#include "sx1276-LoRa.h"
+#include "sx1276-LoRaMisc.h"
+
+/*!
+ * SX1276 definitions
+ */
+#define XTAL_FREQ                                   32000000
+#define FREQ_STEP                                   61.03515625
+
+extern tLoRaSettings LoRaSettings;
+
+void SX1276LoRaSetRFFrequency( uint32_t freq )
+{
+    LoRaSettings.RFFrequency = freq;
+
+    freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
+    SX1276LR->RegFrfMsb = ( uint8_t )( ( freq >> 16 ) & 0xFF );
+    SX1276LR->RegFrfMid = ( uint8_t )( ( freq >> 8 ) & 0xFF );
+    SX1276LR->RegFrfLsb = ( uint8_t )( freq & 0xFF );
+    SX1276WriteBuffer( REG_LR_FRFMSB, &SX1276LR->RegFrfMsb, 3 );
+}
+
+uint32_t SX1276LoRaGetRFFrequency( void )
+{
+    SX1276ReadBuffer( REG_LR_FRFMSB, &SX1276LR->RegFrfMsb, 3 );
+    LoRaSettings.RFFrequency = ( ( uint32_t )SX1276LR->RegFrfMsb << 16 ) | ( ( uint32_t )SX1276LR->RegFrfMid << 8 ) | ( ( uint32_t )SX1276LR->RegFrfLsb );
+    LoRaSettings.RFFrequency = ( uint32_t )( ( double )LoRaSettings.RFFrequency * ( double )FREQ_STEP );
+
+    return LoRaSettings.RFFrequency;
+}
+
+void SX1276LoRaSetRFPower( int8_t power )
+{
+    SX1276Read( REG_LR_PACONFIG, &SX1276LR->RegPaConfig );
+    SX1276Read( REG_LR_PADAC, &SX1276LR->RegPaDac );
+    
+    if( ( SX1276LR->RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) == RFLR_PACONFIG_PASELECT_PABOOST )
+    {
+        if( ( SX1276LR->RegPaDac & 0x87 ) == 0x87 )
+        {
+            if( power < 5 )
+            {
+                power = 5;
+            }
+            if( power > 20 )
+            {
+                power = 20;
+            }
+            SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70;
+            SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
+        }
+        else
+        {
+            if( power < 2 )
+            {
+                power = 2;
+            }
+            if( power > 17 )
+            {
+                power = 17;
+            }
+            SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70;
+            SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
+        }
+    }
+    else
+    {
+        if( power < -1 )
+        {
+            power = -1;
+        }
+        if( power > 14 )
+        {
+            power = 14;
+        }
+        SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_MAX_POWER_MASK ) | 0x70;
+        SX1276LR->RegPaConfig = ( SX1276LR->RegPaConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
+    }
+    SX1276Write( REG_LR_PACONFIG, SX1276LR->RegPaConfig );
+    LoRaSettings.Power = power;
+}
+
+int8_t SX1276LoRaGetRFPower( void )
+{
+    SX1276Read( REG_LR_PACONFIG, &SX1276LR->RegPaConfig );
+    SX1276Read( REG_LR_PADAC, &SX1276LR->RegPaDac );
+
+    if( ( SX1276LR->RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) == RFLR_PACONFIG_PASELECT_PABOOST )
+    {
+        if( ( SX1276LR->RegPaDac & 0x07 ) == 0x07 )
+        {
+            LoRaSettings.Power = 5 + ( SX1276LR->RegPaConfig & ~RFLR_PACONFIG_OUTPUTPOWER_MASK );
+        }
+        else
+        {
+            LoRaSettings.Power = 2 + ( SX1276LR->RegPaConfig & ~RFLR_PACONFIG_OUTPUTPOWER_MASK );
+        }
+    }
+    else
+    {
+        LoRaSettings.Power = -1 + ( SX1276LR->RegPaConfig & ~RFLR_PACONFIG_OUTPUTPOWER_MASK );
+    }
+    return LoRaSettings.Power;
+}
+
+void SX1276LoRaSetSignalBandwidth( uint8_t bw )
+{
+    SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 );
+    SX1276LR->RegModemConfig1 = ( SX1276LR->RegModemConfig1 & RFLR_MODEMCONFIG1_BW_MASK ) | ( bw << 4 );
+    SX1276Write( REG_LR_MODEMCONFIG1, SX1276LR->RegModemConfig1 );
+    LoRaSettings.SignalBw = bw;
+}
+
+uint8_t SX1276LoRaGetSignalBandwidth( void )
+{
+    SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 );
+    LoRaSettings.SignalBw = ( SX1276LR->RegModemConfig1 & ~RFLR_MODEMCONFIG1_BW_MASK ) >> 4;
+    return LoRaSettings.SignalBw;
+}
+
+void SX1276LoRaSetSpreadingFactor( uint8_t factor )
+{
+
+    if( factor > 12 )
+    {
+        factor = 12;
+    }
+    else if( factor < 6 )
+    {
+        factor = 6;
+    }
+
+    if( factor == 6 )
+    {
+        SX1276LoRaSetNbTrigPeaks( 5 );
+    }
+    else
+    {
+        SX1276LoRaSetNbTrigPeaks( 3 );
+    }
+
+    SX1276Read( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2 );    
+    SX1276LR->RegModemConfig2 = ( SX1276LR->RegModemConfig2 & RFLR_MODEMCONFIG2_SF_MASK ) | ( factor << 4 );
+    SX1276Write( REG_LR_MODEMCONFIG2, SX1276LR->RegModemConfig2 );    
+    LoRaSettings.SpreadingFactor = factor;
+}
+
+uint8_t SX1276LoRaGetSpreadingFactor( void )
+{
+    SX1276Read( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2 );   
+    LoRaSettings.SpreadingFactor = ( SX1276LR->RegModemConfig2 & ~RFLR_MODEMCONFIG2_SF_MASK ) >> 4;
+    return LoRaSettings.SpreadingFactor;
+}
+
+void SX1276LoRaSetErrorCoding( uint8_t value )
+{
+    SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 );
+    SX1276LR->RegModemConfig1 = ( SX1276LR->RegModemConfig1 & RFLR_MODEMCONFIG1_CODINGRATE_MASK ) | ( value << 1 );
+    SX1276Write( REG_LR_MODEMCONFIG1, SX1276LR->RegModemConfig1 );
+    LoRaSettings.ErrorCoding = value;
+}
+
+uint8_t SX1276LoRaGetErrorCoding( void )
+{
+    SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 );
+    LoRaSettings.ErrorCoding = ( SX1276LR->RegModemConfig1 & ~RFLR_MODEMCONFIG1_CODINGRATE_MASK ) >> 1;
+    return LoRaSettings.ErrorCoding;
+}
+
+void SX1276LoRaSetPacketCrcOn( bool enable )
+{
+    SX1276Read( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2 );
+    SX1276LR->RegModemConfig2 = ( SX1276LR->RegModemConfig2 & RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) | ( enable << 2 );
+    SX1276Write( REG_LR_MODEMCONFIG2, SX1276LR->RegModemConfig2 );
+    LoRaSettings.CrcOn = enable;
+}
+
+void SX1276LoRaSetPreambleLength( uint16_t value )
+{
+    SX1276ReadBuffer( REG_LR_PREAMBLEMSB, &SX1276LR->RegPreambleMsb, 2 );
+
+    SX1276LR->RegPreambleMsb = ( value >> 8 ) & 0x00FF;
+    SX1276LR->RegPreambleLsb = value & 0xFF;
+    SX1276WriteBuffer( REG_LR_PREAMBLEMSB, &SX1276LR->RegPreambleMsb, 2 );
+}
+
+uint16_t SX1276LoRaGetPreambleLength( void )
+{
+    SX1276ReadBuffer( REG_LR_PREAMBLEMSB, &SX1276LR->RegPreambleMsb, 2 );
+    return ( ( SX1276LR->RegPreambleMsb & 0x00FF ) << 8 ) | SX1276LR->RegPreambleLsb;
+}
+
+bool SX1276LoRaGetPacketCrcOn( void )
+{
+    SX1276Read( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2 );
+    LoRaSettings.CrcOn = ( SX1276LR->RegModemConfig2 & RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON ) >> 1;
+    return LoRaSettings.CrcOn;
+}
+
+void SX1276LoRaSetImplicitHeaderOn( bool enable )
+{
+    SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 );
+    SX1276LR->RegModemConfig1 = ( SX1276LR->RegModemConfig1 & RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) | ( enable );
+    SX1276Write( REG_LR_MODEMCONFIG1, SX1276LR->RegModemConfig1 );
+    LoRaSettings.ImplicitHeaderOn = enable;
+}
+
+bool SX1276LoRaGetImplicitHeaderOn( void )
+{
+    SX1276Read( REG_LR_MODEMCONFIG1, &SX1276LR->RegModemConfig1 );
+    LoRaSettings.ImplicitHeaderOn = ( SX1276LR->RegModemConfig1 & RFLR_MODEMCONFIG1_IMPLICITHEADER_ON );
+    return LoRaSettings.ImplicitHeaderOn;
+}
+
+void SX1276LoRaSetRxSingleOn( bool enable )
+{
+    LoRaSettings.RxSingleOn = enable;
+}
+
+bool SX1276LoRaGetRxSingleOn( void )
+{
+    return LoRaSettings.RxSingleOn;
+}
+
+void SX1276LoRaSetFreqHopOn( bool enable )
+{
+    LoRaSettings.FreqHopOn = enable;
+}
+
+bool SX1276LoRaGetFreqHopOn( void )
+{
+    return LoRaSettings.FreqHopOn;
+}
+
+void SX1276LoRaSetHopPeriod( uint8_t value )
+{
+    SX1276LR->RegHopPeriod = value;
+    SX1276Write( REG_LR_HOPPERIOD, SX1276LR->RegHopPeriod );
+    LoRaSettings.HopPeriod = value;
+}
+
+uint8_t SX1276LoRaGetHopPeriod( void )
+{
+    SX1276Read( REG_LR_HOPPERIOD, &SX1276LR->RegHopPeriod );
+    LoRaSettings.HopPeriod = SX1276LR->RegHopPeriod;
+    return LoRaSettings.HopPeriod;
+}
+
+void SX1276LoRaSetTxPacketTimeout( uint32_t value )
+{
+    LoRaSettings.TxPacketTimeout = value;
+}
+
+uint32_t SX1276LoRaGetTxPacketTimeout( void )
+{
+    return LoRaSettings.TxPacketTimeout;
+}
+
+void SX1276LoRaSetRxPacketTimeout( uint32_t value )
+{
+    LoRaSettings.RxPacketTimeout = value;
+}
+
+uint32_t SX1276LoRaGetRxPacketTimeout( void )
+{
+    return LoRaSettings.RxPacketTimeout;
+}
+
+void SX1276LoRaSetPayloadLength( uint8_t value )
+{
+    SX1276LR->RegPayloadLength = value;
+    SX1276Write( REG_LR_PAYLOADLENGTH, SX1276LR->RegPayloadLength );
+    LoRaSettings.PayloadLength = value;
+}
+
+uint8_t SX1276LoRaGetPayloadLength( void )
+{
+    SX1276Read( REG_LR_PAYLOADLENGTH, &SX1276LR->RegPayloadLength );
+    LoRaSettings.PayloadLength = SX1276LR->RegPayloadLength;
+    return LoRaSettings.PayloadLength;
+}
+
+void SX1276LoRaSetPa20dBm( bool enale )
+{
+    SX1276Read( REG_LR_PADAC, &SX1276LR->RegPaDac );
+    SX1276Read( REG_LR_PACONFIG, &SX1276LR->RegPaConfig );
+
+    if( ( SX1276LR->RegPaConfig & RFLR_PACONFIG_PASELECT_PABOOST ) == RFLR_PACONFIG_PASELECT_PABOOST )
+    {    
+        if( enale == true )
+        {
+            SX1276LR->RegPaDac = 0x87;
+        }
+    }
+    else
+    {
+        SX1276LR->RegPaDac = 0x84;
+    }
+    SX1276Write( REG_LR_PADAC, SX1276LR->RegPaDac );
+}
+
+bool SX1276LoRaGetPa20dBm( void )
+{
+    SX1276Read( REG_LR_PADAC, &SX1276LR->RegPaDac );
+    
+    return ( ( SX1276LR->RegPaDac & 0x07 ) == 0x07 ) ? true : false;
+}
+
+void SX1276LoRaSetPAOutput( uint8_t outputPin )
+{
+    SX1276Read( REG_LR_PACONFIG, &SX1276LR->RegPaConfig );
+    SX1276LR->RegPaConfig = (SX1276LR->RegPaConfig & RFLR_PACONFIG_PASELECT_MASK ) | outputPin;
+    SX1276Write( REG_LR_PACONFIG, SX1276LR->RegPaConfig );
+}
+
+uint8_t SX1276LoRaGetPAOutput( void )
+{
+    SX1276Read( REG_LR_PACONFIG, &SX1276LR->RegPaConfig );
+    return SX1276LR->RegPaConfig & ~RFLR_PACONFIG_PASELECT_MASK;
+}
+
+void SX1276LoRaSetPaRamp( uint8_t value )
+{
+    SX1276Read( REG_LR_PARAMP, &SX1276LR->RegPaRamp );
+    SX1276LR->RegPaRamp = ( SX1276LR->RegPaRamp & RFLR_PARAMP_MASK ) | ( value & ~RFLR_PARAMP_MASK );
+    SX1276Write( REG_LR_PARAMP, SX1276LR->RegPaRamp );
+}
+
+uint8_t SX1276LoRaGetPaRamp( void )
+{
+    SX1276Read( REG_LR_PARAMP, &SX1276LR->RegPaRamp );
+    return SX1276LR->RegPaRamp & ~RFLR_PARAMP_MASK;
+}
+
+void SX1276LoRaSetSymbTimeout( uint16_t value )
+{
+    SX1276ReadBuffer( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2, 2 );
+
+    SX1276LR->RegModemConfig2 = ( SX1276LR->RegModemConfig2 & RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) | ( ( value >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK );
+    SX1276LR->RegSymbTimeoutLsb = value & 0xFF;
+    SX1276WriteBuffer( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2, 2 );
+}
+
+uint16_t SX1276LoRaGetSymbTimeout( void )
+{
+    SX1276ReadBuffer( REG_LR_MODEMCONFIG2, &SX1276LR->RegModemConfig2, 2 );
+    return ( ( SX1276LR->RegModemConfig2 & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) << 8 ) | SX1276LR->RegSymbTimeoutLsb;
+}
+
+void SX1276LoRaSetLowDatarateOptimize( bool enable )
+{
+    SX1276Read( REG_LR_MODEMCONFIG3, &SX1276LR->RegModemConfig3 );
+    SX1276LR->RegModemConfig3 = ( SX1276LR->RegModemConfig3 & RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) | ( enable << 3 );
+    SX1276Write( REG_LR_MODEMCONFIG3, SX1276LR->RegModemConfig3 );
+}
+
+bool SX1276LoRaGetLowDatarateOptimize( void )
+{
+    SX1276Read( REG_LR_MODEMCONFIG3, &SX1276LR->RegModemConfig3 );
+    return ( ( SX1276LR->RegModemConfig3 & RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON ) >> 3 );
+}
+
+void SX1276LoRaSetNbTrigPeaks( uint8_t value )
+{
+    SX1276Read( 0x31, &SX1276LR->RegTestReserved31 );
+    SX1276LR->RegTestReserved31 = ( SX1276LR->RegTestReserved31 & 0xF8 ) | value;//数据包长度最高有效位 0x31 bit2 1 0
+    SX1276Write( 0x31, SX1276LR->RegTestReserved31 );
+}
+
+uint8_t SX1276LoRaGetNbTrigPeaks( void )
+{
+    SX1276Read( 0x31, &SX1276LR->RegTestReserved31 );
+    return ( SX1276LR->RegTestReserved31 & 0x07 );
+}
+
+#endif // USE_SX1276_RADIO

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276-LoRaMisc.h

@@ -0,0 +1,324 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       sx1276-LoRaMisc.h
+ * \brief      SX1276 RF chip high level functions driver
+ *
+ * \remark     Optional support functions.
+ *             These functions are defined only to easy the change of the
+ *             parameters.
+ *             For a final firmware the radio parameters will be known so
+ *             there is no need to support all possible parameters.
+ *             Removing these functions will greatly reduce the final firmware
+ *             size.
+ *
+ * \version    2.0.0 
+ * \date       May 6 2013
+ * \author     Gregory Cristian
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276-LoRaMisc.h
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+#ifndef __SX1276_LORA_MISC_H__
+#define __SX1276_LORA_MISC_H__
+#include "stdint.h"
+#include "stdbool.h"
+/*!
+ * \brief Writes the new RF frequency value
+ *
+ * \param [IN] freq New RF frequency value in [Hz]
+ */
+void SX1276LoRaSetRFFrequency( uint32_t freq );
+
+/*!
+ * \brief Reads the current RF frequency value
+ *
+ * \retval freq Current RF frequency value in [Hz]
+ */
+uint32_t SX1276LoRaGetRFFrequency( void );
+
+/*!
+ * \brief Writes the new RF output power value
+ *
+ * \param [IN] power New output power value in [dBm]
+ */
+void SX1276LoRaSetRFPower( int8_t power );
+
+/*!
+ * \brief Reads the current RF output power value
+ *
+ * \retval power Current output power value in [dBm]
+ */
+int8_t SX1276LoRaGetRFPower( void );
+
+/*!
+ * \brief Writes the new Signal Bandwidth value
+ *
+ * \remark This function sets the IF frequency according to the datasheet
+ *
+ * \param [IN] factor New Signal Bandwidth value [0: 125 kHz, 1: 250 kHz, 2: 500 kHz]
+ */
+void SX1276LoRaSetSignalBandwidth( uint8_t bw );
+
+/*!
+ * \brief Reads the current Signal Bandwidth value
+ *
+ * \retval factor Current Signal Bandwidth value [0: 125 kHz, 1: 250 kHz, 2: 500 kHz] 
+ */
+uint8_t SX1276LoRaGetSignalBandwidth( void );
+
+/*!
+ * \brief Writes the new Spreading Factor value
+ *
+ * \param [IN] factor New Spreading Factor value [7, 8, 9, 10, 11, 12]
+ */
+void SX1276LoRaSetSpreadingFactor( uint8_t factor );
+
+/*!
+ * \brief Reads the current Spreading Factor value
+ *
+ * \retval factor Current Spreading Factor value [7, 8, 9, 10, 11, 12] 
+ */
+uint8_t SX1276LoRaGetSpreadingFactor( void );
+
+/*!
+ * \brief Writes the new Error Coding value
+ *
+ * \param [IN] value New Error Coding value [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ */
+void SX1276LoRaSetErrorCoding( uint8_t value );
+
+/*!
+ * \brief Reads the current Error Coding value
+ *
+ * \retval value Current Error Coding value [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ */
+uint8_t SX1276LoRaGetErrorCoding( void );
+
+/*!
+ * \brief Enables/Disables the packet CRC generation
+ *
+ * \param [IN] enaable [true, false]
+ */
+void SX1276LoRaSetPacketCrcOn( bool enable );
+
+/*!
+ * \brief Reads the current packet CRC generation status
+ *
+ * \retval enable [true, false]
+ */
+bool SX1276LoRaGetPacketCrcOn( void );
+
+/*!
+ * \brief Enables/Disables the Implicit Header mode in LoRa
+ *
+ * \param [IN] enable [true, false]
+ */
+void SX1276LoRaSetImplicitHeaderOn( bool enable );
+
+/*!
+ * \brief Check if implicit header mode in LoRa in enabled or disabled
+ *
+ * \retval enable [true, false]
+ */
+bool SX1276LoRaGetImplicitHeaderOn( void );
+
+/*!
+ * \brief Enables/Disables Rx single instead of Rx continuous
+ *
+ * \param [IN] enable [true, false]
+ */
+void SX1276LoRaSetRxSingleOn( bool enable );
+
+/*!
+ * \brief Check if LoRa is in Rx Single mode
+ *
+ * \retval enable [true, false]
+ */
+bool SX1276LoRaGetRxSingleOn( void );
+
+/*!
+ * \brief Enables/Disables the frequency hopping 
+ *
+ * \param [IN] enable [true, false]
+ */
+ 
+void SX1276LoRaSetFreqHopOn( bool enable );
+
+/*!
+ * \brief Get the frequency hopping status 
+ *
+ * \param [IN] enable [true, false]
+ */
+bool SX1276LoRaGetFreqHopOn( void );
+
+/*!
+ * \brief Set symbol period between frequency hops
+ *
+ * \param [IN] value
+ */
+void SX1276LoRaSetHopPeriod( uint8_t value );
+
+/*!
+ * \brief Get symbol period between frequency hops
+ *
+ * \retval value symbol period between frequency hops
+ */
+uint8_t SX1276LoRaGetHopPeriod( void );
+
+/*!
+ * \brief Set timeout Tx packet (based on MCU timer, timeout between Tx Mode entry Tx Done IRQ)
+ *
+ * \param [IN] value timeout (ms)
+ */
+void SX1276LoRaSetTxPacketTimeout( uint32_t value );
+
+/*!
+ * \brief Get timeout between Tx packet (based on MCU timer, timeout between Tx Mode entry Tx Done IRQ)
+ *
+ * \retval value timeout (ms)
+ */
+uint32_t SX1276LoRaGetTxPacketTimeout( void );
+
+/*!
+ * \brief Set timeout Rx packet (based on MCU timer, timeout between Rx Mode entry and Rx Done IRQ)
+ *
+ * \param [IN] value timeout (ms)
+ */
+void SX1276LoRaSetRxPacketTimeout( uint32_t value );
+
+/*!
+ * \brief Get timeout Rx packet (based on MCU timer, timeout between Rx Mode entry and Rx Done IRQ)
+ *
+ * \retval value timeout (ms)
+ */
+uint32_t SX1276LoRaGetRxPacketTimeout( void );
+
+/*!
+ * \brief Set payload length
+ *
+ * \param [IN] value payload length
+ */
+void SX1276LoRaSetPayloadLength( uint8_t value );
+
+/*!
+ * \brief Get payload length
+ *
+ * \retval value payload length
+ */
+uint8_t SX1276LoRaGetPayloadLength( void );
+
+/*!
+ * \brief Enables/Disables the 20 dBm PA
+ *
+ * \param [IN] enable [true, false]
+ */
+void SX1276LoRaSetPa20dBm( bool enale );
+
+/*!
+ * \brief Gets the current 20 dBm PA status
+ *
+ * \retval enable [true, false]
+ */
+bool SX1276LoRaGetPa20dBm( void );
+
+/*!
+ * \brief Set the RF Output pin 
+ *
+ * \param [IN] RF_PACONFIG_PASELECT_PABOOST or RF_PACONFIG_PASELECT_RFO
+ */
+void SX1276LoRaSetPAOutput( uint8_t outputPin );
+
+/*!
+ * \brief Gets the used RF Ouptut pin
+ *
+ * \retval RF_PACONFIG_PASELECT_PABOOST or RF_PACONFIG_PASELECT_RFO
+ */
+uint8_t SX1276LoRaGetPAOutput( void );
+
+/*!
+ * \brief Writes the new PA rise/fall time of ramp up/down value
+ *
+ * \param [IN] value New PaRamp value
+ */
+void SX1276LoRaSetPaRamp( uint8_t value );
+
+/*!
+ * \brief Reads the current PA rise/fall time of ramp up/down value
+ *
+ * \retval freq Current PaRamp value
+ */
+uint8_t SX1276LoRaGetPaRamp( void );
+
+/*!
+ * \brief Set Symbol Timeout based on symbol length
+ *
+ * \param [IN] value number of symbol
+ */
+void SX1276LoRaSetSymbTimeout( uint16_t value );
+
+/*!
+ * \brief  Get Symbol Timeout based on symbol length
+ *
+ * \retval value number of symbol
+ */
+uint16_t SX1276LoRaGetSymbTimeout( void );
+
+/*!
+ * \brief  Configure the device to optimize low datarate transfers
+ *
+ * \param [IN] enable Enables/Disables the low datarate optimization
+ */
+void SX1276LoRaSetLowDatarateOptimize( bool enable );
+
+/*!
+ * \brief  Get the status of optimize low datarate transfers
+ *
+ * \retval LowDatarateOptimize enable or disable
+ */
+bool SX1276LoRaGetLowDatarateOptimize( void );
+
+/*!
+ * \brief Get the preamble length
+ *
+ * \retval value preamble length
+ */
+uint16_t SX1276LoRaGetPreambleLength( void );
+
+/*!
+ * \brief Set the preamble length
+ *
+ * \param [IN] value preamble length
+ */
+void SX1276LoRaSetPreambleLength( uint16_t value );
+
+/*!
+ * \brief Set the number or rolling preamble symbol needed for detection
+ *
+ * \param [IN] value number of preamble symbol
+ */
+void SX1276LoRaSetNbTrigPeaks( uint8_t value );
+
+/*!
+ * \brief Get the number or rolling preamble symbol needed for detection
+ *
+ * \retval value number of preamble symbol
+ */
+uint8_t SX1276LoRaGetNbTrigPeaks( void );
+#endif 

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276.c

@@ -0,0 +1,359 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       sx1276.c
+ * \brief      SX1276 RF chip high level functions driver
+ *
+ * \remark     Optional support functions.
+ *             These functions are defined only to easy the change of the
+ *             parameters.
+ *             For a final firmware the radio parameters will be known so
+ *             there is no need to support all possible parameters.
+ *             Removing these functions will greatly reduce the final firmware
+ *             size.
+ *
+ * \version    2.0.0 
+ * \date       May 6 2013
+ * \author     Gregory Cristian
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276.c
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+#include "platform.h"
+#include "radio.h"
+
+#if defined( USE_SX1276_RADIO )
+#include "sx1276.h"
+#include "sx1276-Hal.h"
+#include "sx1276-Fsk.h"
+#include "sx1276-LoRa.h"
+
+uint8_t SX1276Regs[0x70];        
+
+static bool LoRaOn = true;       
+static bool LoRaOnState = false; 
+
+void SX1276Init( void )
+{
+	uint8_t TempReg;
+	
+    SX1276=(tSX1276*)SX1276Regs;    
+    SX1276LR=(tSX1276LR*)SX1276Regs;
+
+    SX1276InitIo( );              
+
+    SX1276Reset( );                 
+
+	SX1276Read(0x06, &TempReg);
+
+	if(TempReg != 0x6C)
+	{
+		KPrintf("Hard SPI Err!\r\n");
+	}
+    
+    #if ( LORA == 0 )               
+		LoRaOn = false;
+		SX1276_SetLoRaOn( LoRaOn );
+		SX1276FskInit( );
+	#else
+		LoRaOn = true;               
+		SX1276_SetLoRaOn( LoRaOn );
+		SX1276LoRaInit( );       
+	#endif
+
+
+}
+
+
+
+void SX1276Reset( void )
+{
+
+
+	uint32_t startTick;  
+
+	SX1276SetReset( RADIO_RESET_ON );
+
+
+    
+    startTick = GET_TICK_COUNT( );   
+    while( ( GET_TICK_COUNT( ) - startTick ) < TICK_RATE_MS( 1 ) );
+
+
+    SX1276SetReset( RADIO_RESET_OFF );
+
+
+    
+    startTick = GET_TICK_COUNT( );   
+    while( ( GET_TICK_COUNT( ) - startTick ) < TICK_RATE_MS( 6 ) );    
+
+}
+
+
+void SX1276_SetLoRaOn( bool enable )
+{
+    if( LoRaOnState == enable )
+    {
+        return;
+    }
+    LoRaOnState = enable;
+    LoRaOn = enable;
+
+    if( LoRaOn == true )
+    {
+        SX1276LoRaSetOpMode( RFLR_OPMODE_SLEEP );   
+		
+
+        SX1276LR->RegOpMode = ( SX1276LR->RegOpMode & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON;
+        SX1276Write( REG_LR_OPMODE, SX1276LR->RegOpMode );
+        
+        SX1276LoRaSetOpMode( RFLR_OPMODE_STANDBY );  
+		
+
+                                        // RxDone               RxTimeout                   FhssChangeChannel           CadDone
+        SX1276LR->RegDioMapping1 = RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO1_00 | RFLR_DIOMAPPING1_DIO2_00 | RFLR_DIOMAPPING1_DIO3_00;
+                                        // CadDetected          ModeReady
+        SX1276LR->RegDioMapping2 = RFLR_DIOMAPPING2_DIO4_00 | RFLR_DIOMAPPING2_DIO5_00;
+        SX1276WriteBuffer( REG_LR_DIOMAPPING1, &SX1276LR->RegDioMapping1, 2 );
+        
+        SX1276ReadBuffer( REG_LR_OPMODE, SX1276Regs + 1, 0x70 - 1 );  
+    }
+    else      
+    {
+        SX1276LoRaSetOpMode( RFLR_OPMODE_SLEEP );
+        
+        SX1276LR->RegOpMode = ( SX1276LR->RegOpMode & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF;
+        SX1276Write( REG_LR_OPMODE, SX1276LR->RegOpMode );
+        
+        SX1276LoRaSetOpMode( RFLR_OPMODE_STANDBY );
+        
+        SX1276ReadBuffer( REG_OPMODE, SX1276Regs + 1, 0x70 - 1 );
+    }
+}
+
+
+bool SX1276_GetLoRaOn( void )
+{
+    return LoRaOn;
+}
+
+
+void SX1276SetOpMode( uint8_t opMode )
+{
+    if( LoRaOn == false )
+    {
+        SX1276FskSetOpMode( opMode );
+    }
+    else
+    {
+        SX1276LoRaSetOpMode( opMode );
+    }
+}
+
+
+uint8_t SX1276_GetOpMode( void )
+{
+    if( LoRaOn == false )
+    {
+        return SX1276FskGetOpMode( );
+    }
+    else
+    {
+        return SX1276LoRaGetOpMode( );
+    }
+}
+
+
+double SX1276ReadRssi( void )
+{
+    if( LoRaOn == false )
+    {
+        return SX1276FskReadRssi( );
+    }
+    else
+    {
+        return SX1276LoRaReadRssi( );
+    }
+}
+
+
+uint8_t SX1276_ReadRxGain( void )
+{
+    if( LoRaOn == false )
+    {
+        return SX1276FskReadRxGain( );
+    }
+    else
+    {
+        return SX1276LoRaReadRxGain( );
+    }
+}
+
+
+uint8_t SX1276_GetPacketRxGain( void )
+{
+    if( LoRaOn == false )
+    {
+        return SX1276FskGetPacketRxGain(  );
+    }
+    else
+    {
+        return SX1276LoRaGetPacketRxGain(  );
+    }
+}
+
+
+int8_t SX1276_GetPacketSnr( void )
+{
+    if( LoRaOn == false )
+    {
+         while( 1 )
+         {
+             // Useless in FSK mode
+             // Block program here
+         }
+    }
+    else
+    {
+        return SX1276LoRaGetPacketSnr(  );
+    }
+}
+
+
+double SX1276_GetPacketRssi( void )
+{
+    if( LoRaOn == false )
+    {
+        return SX1276FskGetPacketRssi(  );
+    }
+    else
+    {
+        return SX1276LoRaGetPacketRssi( );
+    }
+}
+
+uint32_t SX1276GetPacketAfc( void )
+{
+    if( LoRaOn == false )
+    {
+        return SX1276FskGetPacketAfc(  );
+    }
+    else
+    {
+         while( 1 )
+         {
+             // Useless in LoRa mode
+             // Block program here
+         }
+    }
+}
+
+
+void SX1276StartRx( void )
+{
+  if( LoRaOn == false )
+  {
+      SX1276FskSetRFState( RF_STATE_RX_INIT );
+  }
+  else
+  {
+      SX1276LoRaSetRFState( RFLR_STATE_RX_INIT );    
+  }
+}
+
+
+void SX1276GetRxPacket( void *buffer, uint16_t *size )
+{
+    if( LoRaOn == false )
+    {
+        SX1276FskGetRxPacket( buffer, size );
+    }
+    else
+    {
+        SX1276LoRaGetRxPacket( buffer, size );
+    }
+}
+
+
+void SX1276SetTxPacket( const void *buffer, uint16_t size )
+{
+    if( LoRaOn == false )
+    {
+        SX1276FskSetTxPacket( buffer, size );
+    }
+    else
+    {
+        SX1276LoRaSetTxPacket( buffer, size );
+    }
+}
+
+
+uint8_t SX1276GetRFState( void )
+{
+    if( LoRaOn == false )
+    {
+        return SX1276FskGetRFState( );
+    }
+    else
+    {
+        return SX1276LoRaGetRFState( );
+    }
+}
+
+
+void SX1276SetRFState( uint8_t state )
+{
+    if( LoRaOn == false )
+    {
+        SX1276FskSetRFState( state );
+    }
+    else
+    {
+        SX1276LoRaSetRFState( state );
+    }
+}
+
+
+uint32_t SX1276Process( void )
+{
+    if( LoRaOn == false )
+    {
+        return SX1276FskProcess( );
+    }
+    else
+    {
+        return SX1276LoRaProcess( );
+    }
+}
+
+
+uint32_t SX1276ChannelEmpty( void )
+{
+    if( LoRaOn == false )
+    {
+        return true;
+    }
+    else
+    {
+        SX1276LoraChannelEmpty();
+    }
+}
+
+#endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/spi/third_party_spi_lora/src/radio/sx1276.h

@@ -0,0 +1,93 @@
+/*
+ * THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND 
+ * (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
+ * CONSEQUENTLY, SEMTECH SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
+ * OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
+ * CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ * 
+ * Copyright (C) SEMTECH S.A.
+ */
+/*! 
+ * \file       sx1276.h
+ * \brief      SX1276 RF chip high level functions driver
+ *
+ * \remark     Optional support functions.
+ *             These functions are defined only to easy the change of the
+ *             parameters.
+ *             For a final firmware the radio parameters will be known so
+ *             there is no need to support all possible parameters.
+ *             Removing these functions will greatly reduce the final firmware
+ *             size.
+ *
+ * \version    2.0.0 
+ * \date       May 6 2013
+ * \author     Gregory Cristian
+ *
+ * Last modified by Miguel Luis on Jun 19 2013
+ */
+/*************************************************
+File name: sx1276.h
+Description: support aiit board configure and register function
+History: 
+1. Date: 2021-04-25
+Author: AIIT XUOS Lab
+Modification: 
+1. replace original macro and basic date type with AIIT XUOS Lab's own defination
+*************************************************/
+
+
+#ifndef __SX1276_H__
+#define __SX1276_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+extern uint8_t SX1276Regs[0x70];     						 //SX1276寄存器数组
+
+void SX1276Init( void );									 //初始化SX1276
+
+void SX1276Reset( void );									 //重置SX1276
+
+/*以下函数都没有被使用到，因为在sx1276-LoRa.h里面又定义了一系列与下面作用相同的函数*/
+void SX1276_SetLoRaOn( bool enable ); 						 //启用LoRa调制解调器或FSK调制解调器
+
+bool SX1276_GetLoRaOn( void );								 //获取LoRa调制解调器状态
+
+void SX1276SetOpMode( uint8_t opMode );  					 //设置SX1276操作模式
+
+uint8_t SX1276_GetOpMode( void );     						 //获取SX1276操作模式
+
+uint8_t SX1276_ReadRxGain( void );   						 //读取当前Rx增益设置
+
+double SX1276ReadRssi( void );       						 //读取无线信号强度
+
+uint8_t SX1276_GetPacketRxGain( void );                      //获取数据时的增益值
+
+int8_t SX1276_GetPacketSnr( void );							 //获取数据时的信噪比值，信号和噪声的比值，信噪比越高，说明信号干扰越小。
+
+double SX1276_GetPacketRssi( void );  					     //获取数据是的无线信号强度
+
+/*!
+ * \brief Gets the AFC value measured while receiving the packet
+ *
+ * \retval afcValue Current AFC value in [Hz]
+ */
+uint32_t SX1276GetPacketAfc( void );                          //此函数不知道作用
+
+
+void SX1276StartRx( void );                                   //开始接收
+
+void SX1276GetRxPacket( void *buffer, uint16_t *size );       //得到接收的数据
+
+void SX1276SetTxPacket( const void *buffer, uint16_t size );  //发送数据
+
+uint8_t SX1276GetRFState( void );       				      //得到RFLRState状态
+
+void SX1276SetRFState( uint8_t state );						  //设置RFLRState状态，RFLRState的值决定了下面的函数处理哪一步的代码
+
+uint32_t SX1276Process( void );         			          //SX1276模块接发收数据的处理函数
+
+uint32_t SX1276ChannelEmpty( void );
+
+#endif 

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/sys_clock/Kconfig

@@ -0,0 +1 @@
+

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/sys_clock/Makefile

@@ -0,0 +1,6 @@
+SRC_FILES := sysctl.c
+
+
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/timer/Kconfig

@@ -0,0 +1,19 @@
+if BSP_USING_HWTIMER
+    config HWTIMER_BUS_NAME_1
+    string "hwtimer bus name"
+    default "hwtim1"
+
+    menuconfig ENABLE_TIM1
+    bool "enable TIM1"
+    default y
+
+    if ENABLE_TIM1
+        config HWTIMER_1_DEVICE_NAME_1
+        string "TIM1 dev name"
+        default "hwtim1_dev1"
+
+        config HWTIMER_DRIVER_NAME_1
+        string "TIM1 drv name"
+        default "hwtim1_drv"
+    endif
+endif

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/timer/Makefile

@@ -0,0 +1,5 @@
+SRC_FILES := hardware_hwtimer.c connect_hwtimer.c
+
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/timer/connect_hwtimer.c

@@ -0,0 +1,153 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_hwtimer.c
+* @brief support aiit-riscv64-board hwtimer function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#include <board.h>
+#include <connect_hwtimer.h>
+#include <fpioa.h>
+#include <plic.h>
+#include <stdio.h>
+#include <sysctl.h>
+#include <syslog.h>
+
+static struct HwtimerCallBackInfo *ptim2_cb_info = NULL;
+
+int timer_callback(void *ctx) 
+{
+    if (ptim2_cb_info) {
+        if (ptim2_cb_info->timeout_callback) {
+            ptim2_cb_info->timeout_callback(ptim2_cb_info->param);
+        }
+    }
+    return 0;
+}
+
+uint32 HwtimerOpen(void *dev)
+{
+    struct HwtimerHardwareDevice *hwtimer_dev = dev;
+
+    ptim2_cb_info = &hwtimer_dev->hwtimer_param.cb_info;
+
+    plic_init();
+    sysctl_enable_irq();
+    timer_init(TIMER_DEVICE_1);
+
+    size_t real_time =  timer_set_interval(TIMER_DEVICE_1, TIMER_CHANNEL_1, hwtimer_dev->hwtimer_param.period_millisecond *1000);
+    KPrintf("timer_set_interval --  real_time : %ld\n", real_time);
+    timer_irq_register(TIMER_DEVICE_1, TIMER_CHANNEL_1, !hwtimer_dev->hwtimer_param.repeat, 1, timer_callback, NULL);
+
+    timer_set_enable(TIMER_DEVICE_1, TIMER_CHANNEL_1, 1);
+
+    return EOK;
+}
+
+uint32 HwtimerClose(void *dev)
+{
+    timer_set_enable(TIMER_DEVICE_1, TIMER_CHANNEL_1, 0);
+
+    return EOK;
+}
+
+/*manage the hwtimer device operations*/
+static const struct HwtimerDevDone dev_done =
+{
+    .open = HwtimerOpen,
+    .close = HwtimerClose,
+    .write = NONE,
+    .read = NONE,
+};
+
+/*Init hwtimer bus*/
+static int BoardHwtimerBusInit(struct HwtimerBus *hwtimer_bus, struct HwtimerDriver *hwtimer_driver)
+{
+    x_err_t ret = EOK;
+
+    /*Init the hwtimer bus */
+    ret = HwtimerBusInit(hwtimer_bus, HWTIMER_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("board_hwtimer_init HwtimerBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Init the hwtimer driver*/
+    hwtimer_driver->configure = NONE;
+    ret = HwtimerDriverInit(hwtimer_driver, HWTIMER_DRIVER_NAME_1);
+    if (EOK != ret) {
+        KPrintf("board_hwtimer_init HwtimerDriverInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Attach the hwtimer driver to the hwtimer bus*/
+    ret = HwtimerDriverAttachToBus(HWTIMER_DRIVER_NAME_1, HWTIMER_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("board_hwtimer_init USEDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    }
+
+    return ret;
+}
+
+/*Attach the hwtimer device to the hwtimer bus*/
+static int BoardHwtimerDevBend(void)
+{
+    x_err_t ret = EOK;
+    static struct HwtimerHardwareDevice hwtimer_device_0;
+    memset(&hwtimer_device_0, 0, sizeof(struct HwtimerHardwareDevice));
+
+    hwtimer_device_0.dev_done = &dev_done;
+
+    ret = HwtimerDeviceRegister(&hwtimer_device_0, NONE, HWTIMER_1_DEVICE_NAME_1);
+    if (EOK != ret) {
+        KPrintf("BoardHwtimerDevBend HwtimerDeviceRegister device %s error %d\n", HWTIMER_1_DEVICE_NAME_1, ret);
+        return ERROR;
+    }
+
+    ret = HwtimerDeviceAttachToBus(HWTIMER_1_DEVICE_NAME_1, HWTIMER_BUS_NAME_1);
+    if (EOK != ret) {
+        KPrintf("BoardHwtimerDevBend HwtimerDeviceAttachToBus device %s error %d\n", HWTIMER_1_DEVICE_NAME_1, ret);
+        return ERROR;
+    }
+
+    return ret;
+}
+
+/*K210 BOARD HWTIMER INIT*/
+int HwTimerInit(void)
+{
+    x_err_t ret = EOK;
+    static struct HwtimerBus hwtimer_bus;
+    memset(&hwtimer_bus, 0, sizeof(struct HwtimerBus));
+
+    static struct HwtimerDriver hwtimer_driver;
+    memset(&hwtimer_driver, 0, sizeof(struct HwtimerDriver));
+
+    ret = BoardHwtimerBusInit(&hwtimer_bus, &hwtimer_driver);
+    if (EOK != ret) {
+        KPrintf("board_hwtimer_Init error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardHwtimerDevBend();
+    if (EOK != ret) {
+        KPrintf("board_hwtimer_Init error ret %u\n", ret);
+        return ERROR;
+    }
+
+    return ret;
+}

Ubiquitous/XiZi/board/aiit-riscv64-board/third_party_driver/timer/hardware_hwtimer.c

@@ -0,0 +1,407 @@
+/* Copyright 2018 Canaan Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+* @file hardware_hwtimer.c
+* @brief add from Canaan k210 SDK
+*                https://canaan-creative.com/developer
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-25
+*/
+
+#include <hardware_hwtimer.h>
+#include <io.h>
+#include <plic.h>
+#include <stddef.h>
+#include <sysctl.h>
+#include <syslog.h>
+#include <xs_isr.h>
+#include <utils.h>
+
+/**
+ * @brief       Private definitions for the timer instance
+ */
+typedef struct timer_instance
+{
+    timer_callback_t callback;
+    void *ctx;
+    bool single_shot;
+} timer_instance_t;
+
+typedef void(*irq_manager_callback_t)(int irq, void* arg);
+
+volatile timer_instance_t timer_instance[TIMER_DEVICE_MAX][TIMER_CHANNEL_MAX];
+
+volatile kendryte_timer_t *const timer[3] =
+{
+    (volatile kendryte_timer_t *)TIMER0_BASE_ADDR,
+    (volatile kendryte_timer_t *)TIMER1_BASE_ADDR,
+    (volatile kendryte_timer_t *)TIMER2_BASE_ADDR
+};
+
+void timer_init(timer_device_number_t timer_number)
+{
+    for(size_t i = 0; i < TIMER_CHANNEL_MAX; i++)
+        timer_instance[timer_number][i] = (const timer_instance_t) {
+            .callback    = NULL,
+            .ctx         = NULL,
+            .single_shot = 0,
+        };
+
+    sysctl_clock_enable(SYSCTL_CLOCK_TIMER0 + timer_number);
+}
+
+void timer_set_clock_div(timer_device_number_t timer_number, uint32_t div)
+{
+    sysctl_clock_set_threshold(timer_number == 0 ? SYSCTL_THRESHOLD_TIMER0 :
+        timer_number == 1 ? SYSCTL_THRESHOLD_TIMER1 :
+        SYSCTL_THRESHOLD_TIMER2, div);
+}
+
+void timer_enable(timer_device_number_t timer_number, timer_channel_number_t channel)
+{
+    timer[timer_number]->channel[channel].control |= TIMER_CR_ENABLE;
+}
+
+void timer_disable(timer_device_number_t timer_number, timer_channel_number_t channel)
+{
+    timer[timer_number]->channel[channel].control &= (~TIMER_CR_ENABLE);
+}
+
+void timer_enable_pwm(timer_device_number_t timer_number, timer_channel_number_t channel)
+{
+    timer[timer_number]->channel[channel].control |= TIMER_CR_PWM_ENABLE;
+}
+
+void timer_disable_pwm(timer_device_number_t timer_number, timer_channel_number_t channel)
+{
+    timer[timer_number]->channel[channel].control &= (~TIMER_CR_PWM_ENABLE);
+}
+
+void timer_enable_interrupt(timer_device_number_t timer_number, timer_channel_number_t channel)
+{
+    timer[timer_number]->channel[channel].control &= (~TIMER_CR_INTERRUPT_MASK);
+}
+
+void timer_disable_interrupt(timer_device_number_t timer_number, timer_channel_number_t channel)
+{
+    timer[timer_number]->channel[channel].control |= TIMER_CR_INTERRUPT_MASK;
+}
+
+void timer_set_mode(timer_device_number_t timer_number, timer_channel_number_t channel, uint32_t mode)
+{
+    timer[timer_number]->channel[channel].control &= (~TIMER_CR_MODE_MASK);
+    timer[timer_number]->channel[channel].control |= mode;
+}
+
+void timer_set_reload(timer_device_number_t timer_number, timer_channel_number_t channel, uint32_t count)
+{
+    timer[timer_number]->channel[channel].load_count = count;
+}
+
+void timer_set_reload2(timer_device_number_t timer_number, timer_channel_number_t channel, uint32_t count)
+{
+    timer[timer_number]->load_count2[channel] = count;
+}
+
+uint32_t timer_get_count(timer_device_number_t timer_number, timer_channel_number_t channel)
+{
+    return timer[timer_number]->channel[channel].current_value;
+}
+
+uint32_t timer_get_reload(timer_device_number_t timer_number, timer_channel_number_t channel)
+{
+    return timer[timer_number]->channel[channel].load_count;
+}
+
+uint32_t timer_get_reload2(timer_device_number_t timer_number, timer_channel_number_t channel)
+{
+    return timer[timer_number]->load_count2[channel];
+}
+
+uint32_t timer_get_interrupt_status(timer_device_number_t timer_number)
+{
+    return timer[timer_number]->intr_stat;
+}
+
+uint32_t timer_get_raw_interrupt_status(timer_device_number_t timer_number)
+{
+    return timer[timer_number]->raw_intr_stat;
+}
+
+uint32_t timer_channel_get_interrupt_status(timer_device_number_t timer_number, timer_channel_number_t channel)
+{
+    return timer[timer_number]->channel[channel].intr_stat;
+}
+
+void timer_clear_interrupt(timer_device_number_t timer_number)
+{
+    timer[timer_number]->eoi = timer[timer_number]->eoi;
+}
+
+void timer_channel_clear_interrupt(timer_device_number_t timer_number, timer_channel_number_t channel)
+{
+    timer[timer_number]->channel[channel].eoi = timer[timer_number]->channel[channel].eoi;
+}
+
+void timer_set_enable(timer_device_number_t timer_number, timer_channel_number_t channel, uint32_t enable)
+{
+    if (enable)
+        timer[timer_number]->channel[channel].control = TIMER_CR_USER_MODE | TIMER_CR_ENABLE;
+    else
+        timer[timer_number]->channel[channel].control = TIMER_CR_INTERRUPT_MASK;
+}
+
+size_t timer_set_interval(timer_device_number_t timer_number, timer_channel_number_t channel, size_t useconds)
+{
+    uint32_t clk_freq = SysctlClockGetFreq(SYSCTL_CLOCK_TIMER0 + timer_number);
+
+    double min_step = 1e6 / clk_freq;
+    size_t value = (size_t)(useconds / min_step);
+    configASSERT(value > 0 && value < UINT32_MAX);
+    timer[timer_number]->channel[channel].load_count = (uint32_t)value;
+    return (size_t)(min_step * value);
+}
+
+typedef void(*timer_ontick)();
+timer_ontick time_irq[3][4] = { NULL };
+
+static int timer_isr(void *parm)
+{
+    uint32_t timer_number;
+    for (timer_number = 0; timer_number < 3; timer_number++)
+    {
+        if (parm == timer[timer_number])
+            break;
+    }
+
+    uint32_t channel = timer[timer_number]->intr_stat;
+    size_t i = 0;
+    for (i = 0; i < 4; i++)
+    {
+        if (channel & 1)
+        {
+            if (time_irq[timer_number][i])
+                (time_irq[timer_number][i])();
+            break;
+        }
+
+        channel >>= 1;
+    }
+
+    readl(&timer[timer_number]->eoi);
+    return 0;
+}
+
+void timer_set_irq(timer_device_number_t timer_number, timer_channel_number_t channel, void(*func)(), uint32_t priority)
+{
+    time_irq[timer_number][channel] = func;
+    if (channel < 2)
+    {
+        plic_set_priority(IRQN_TIMER0A_INTERRUPT + timer_number * 2, priority);
+        plic_irq_register(IRQN_TIMER0A_INTERRUPT + timer_number * 2, timer_isr, (void *)timer[timer_number]);
+        plic_irq_enable(IRQN_TIMER0A_INTERRUPT + timer_number * 2);
+    }
+    else
+    {
+        plic_set_priority(IRQN_TIMER0B_INTERRUPT + timer_number * 2, priority);
+        plic_irq_register(IRQN_TIMER0B_INTERRUPT + timer_number * 2, timer_isr, (void *)timer[timer_number]);
+        plic_irq_enable(IRQN_TIMER0B_INTERRUPT + timer_number * 2);
+    }
+}
+
+/**
+ * @brief             Get the timer irqn by device and channel object
+ *
+ * @note              Internal function, not public
+ * @param  device     The device
+ * @param  channel    The channel
+ * @return plic_irq_t IRQ number
+ */
+static plic_irq_t get_timer_irqn_by_device_and_channel(timer_device_number_t device, timer_channel_number_t channel)
+{
+    if (device < TIMER_DEVICE_MAX && channel < TIMER_CHANNEL_MAX) {
+        /*
+         * Select timer interrupt part
+         * Hierarchy of Timer interrupt to PLIC
+         *  +---------+       +-----------+
+         *  |        0+----+  |           |
+         *  |         |    +--+0A         |
+         *  |        1+----+  |           |
+         *  | TIMER0  |       |           |
+         *  |        2+----+  |           |
+         *  |         |    +--+0B         |
+         *  |        3+----+  |           |
+         *  +---------+       |           |
+         *                    |           |
+         *  +---------+       |           |
+         *  |        0+----+  |           |
+         *  |         |    +--+1A         |
+         *  |        1+----+  |           |
+         *  | TIMER1  |       |    PLIC   |
+         *  |        2+----+  |           |
+         *  |         |    +--+1B         |
+         *  |        3+----+  |           |
+         *  +---------+       |           |
+         *                    |           |
+         *  +---------+       |           |
+         *  |        0+----+  |           |
+         *  |         |    +--+2A         |
+         *  |        1+----+  |           |
+         *  | TIMER2  |       |           |
+         *  |        2+----+  |           |
+         *  |         |    +--+2B         |
+         *  |        3+----+  |           |
+         *  +---------+       +-----------+
+         *
+         */
+        if (channel < 2) {
+            /* It is part A interrupt, offset + 0 */
+            return IRQN_TIMER0A_INTERRUPT + device * 2;
+        }
+        else {
+            /* It is part B interrupt, offset + 1 */
+            return IRQN_TIMER0B_INTERRUPT + device * 2;
+        }
+    }
+    return IRQN_NO_INTERRUPT;
+}
+
+/**
+ * @brief         Process user callback function
+ *
+ * @note          Internal function, not public
+ * @param  device The timer device
+ * @param  ctx    The context
+ * @return int    The callback result
+ */
+static int timer_interrupt_handler(timer_device_number_t device, void *ctx)
+{
+    uint32_t channel_int_stat = timer[device]->intr_stat;
+
+    for (size_t i = 0; i < TIMER_CHANNEL_MAX; i++)
+    {
+        /* Check every bit for interrupt status */
+        if (channel_int_stat & 1)
+        {
+            if (timer_instance[device][i].callback) {
+                /* Process user callback function */
+                timer_instance[device][i].callback(timer_instance[device][i].ctx);
+                /* Check if this timer is a single shot timer */
+                if (timer_instance[device][i].single_shot) {
+                    /* Single shot timer, disable it */
+                    timer_set_enable(device, i, 0);
+                }
+            }
+            /* Clear timer interrupt flag for specific channel */
+            readl(&timer[device]->channel[i].eoi);
+        }
+        channel_int_stat >>= 1;
+    }
+
+    /*
+     * NOTE:
+     * Don't read timer[device]->eoi here, or you will lost some interrupt
+     * readl(&timer[device]->eoi);
+     */
+
+    return 0;
+}
+
+/**
+ * @brief             Callback function bus for timer interrupt
+ *
+ * @note              Internal function, not public
+ * @param  ctx        The context
+ * @return int        The callback result
+ */
+static void timer0_interrupt_callback(int irq, void *ctx)
+{
+    timer_interrupt_handler(TIMER_DEVICE_0, ctx);
+}
+
+/**
+ * @brief             Callback function bus for timer interrupt
+ *
+ * @note              Internal function, not public
+ * @param  ctx        The context
+ * @return int        The callback result
+ */
+static void timer1_interrupt_callback(int irq, void *ctx)
+{
+    timer_interrupt_handler(TIMER_DEVICE_1, ctx);
+}
+
+/**
+ * @brief             Callback function bus for timer interrupt
+ *
+ * @note              Internal function, not public
+ * @param  ctx        The context
+ * @return int        The callback result
+ */
+static void timer2_interrupt_callback(int irq, void *ctx)
+{
+    timer_interrupt_handler(TIMER_DEVICE_2, ctx);
+}
+
+int timer_irq_register(timer_device_number_t device, timer_channel_number_t channel, int is_single_shot, uint32_t priority, timer_callback_t callback, void *ctx)
+{
+    if (device < TIMER_DEVICE_MAX && channel < TIMER_CHANNEL_MAX) {
+        plic_irq_t irq_number = get_timer_irqn_by_device_and_channel(device, channel);
+        irq_manager_callback_t plic_irq_callback[TIMER_DEVICE_MAX] = {
+            timer0_interrupt_callback,
+            timer1_interrupt_callback,
+            timer2_interrupt_callback,
+        };
+
+        timer_instance[device][channel] = (const timer_instance_t) {
+            .callback    = callback,
+            .ctx         = ctx,
+            .single_shot = is_single_shot,
+        };
+
+        // plic_set_priority(irq_number, priority);
+        // plic_irq_register(irq_number, plic_irq_callback[device], (void *)&timer_instance[device]);
+        // plic_irq_enable(irq_number);
+
+        isrManager.done->registerIrq(irq_number, plic_irq_callback[device], NULL);
+        isrManager.done->enableIrq(irq_number);
+        return 0;
+    }
+    return -1;
+}
+
+int timer_irq_unregister(timer_device_number_t device, timer_channel_number_t channel)
+{
+    if (device < TIMER_DEVICE_MAX && channel < TIMER_CHANNEL_MAX) {
+        timer_instance[device][channel] = (const timer_instance_t) {
+            .callback    = NULL,
+            .ctx         = NULL,
+            .single_shot = 0,
+        };
+
+        /* Combine 0 and 1 to A interrupt, 2 and 3 to B interrupt */
+        if ((!(timer_instance[device][TIMER_CHANNEL_0].callback ||
+              timer_instance[device][TIMER_CHANNEL_1].callback)) ||
+            (!(timer_instance[device][TIMER_CHANNEL_2].callback ||
+              timer_instance[device][TIMER_CHANNEL_3].callback))) {
+            plic_irq_t irq_number = get_timer_irqn_by_device_and_channel(device, channel);
+            plic_irq_unregister(irq_number);
+        }
+        return 0;
+    }
+    return -1;
+}