OpenXX/xiuos
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Support XiZi_AIoT

Browse Source
This commit is contained in:
TXuian
2024-01-31 10:30:34 +08:00
parent f6cf46027d
commit 494312183b
351 changed files with 46408 additions and 450091 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/Makefile
+3
View File
@@ -0,0 +1,3 @@
SRC_FILES := ccm_pll.c clock.c gpt.c
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/ccm_pll.c
+331
View File
@@ -0,0 +1,331 @@
/*
* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "soc_memory_map.h"
#include <stdbool.h>
#include <stdint.h>
#include "regsccm.h"
#include "regsccmanalog.h"
#include "regsgpc.h"
#include "regsgpt.h"
#include "regsuart.h"
#include "ccm_pll.h"
////////////////////////////////////////////////////////////////////////////////
// Variables
////////////////////////////////////////////////////////////////////////////////
const uint32_t PLL1_OUTPUT = 792000000;
const uint32_t PLL2_OUTPUT[] = { 528000000, 396000000, 352000000, 198000000, 594000000 };
const uint32_t PLL3_OUTPUT[] = { 480000000, 720000000, 540000000, 508235294, 454736842 };
const uint32_t PLL4_OUTPUT = 650000000;
const uint32_t PLL5_OUTPUT = 650000000;
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
void ccm_init(void)
{
// ETHNET
HW_CCM_ANALOG_PLL_ENET_CLR(BM_CCM_ANALOG_PLL_ENET_POWERDOWN);
HW_CCM_ANALOG_PLL_ENET_SET(BM_CCM_ANALOG_PLL_ENET_ENABLE);
HW_CCM_ANALOG_PLL_ENET_CLR(BM_CCM_ANALOG_PLL_ENET_BYPASS);
#if !defined(CHIP_MX6SL)
HW_CCM_ANALOG_PLL_ENET.B.DIV_SELECT = 0x3;
#else
HW_CCM_ANALOG_PLL_ENET.B.DIV_SELECT = 0x1;
#endif
// Ungate clocks that are not enabled in a driver - need to be updated
HW_CCM_CCGR0_WR(0xffffffff);
HW_CCM_CCGR1_WR(0xFFCF0FFF); // EPIT, ESAI, GPT enabled by driver
HW_CCM_CCGR2_WR(0xFFFFF03F); // I2C enabled by driver
HW_CCM_CCGR3_WR(0xffffffff);
HW_CCM_CCGR4_WR(0x00FFFF03); // GPMI, Perfmon enabled by driver
HW_CCM_CCGR5_WR(0xF0FFFFCF); // UART, SATA enabled by driver
HW_CCM_CCGR6_WR(0xffffffff);
/*
* Keep default settings at reset.
* pre_periph_clk_sel is by default at 0, so the selected output
* of PLL2 is the main output at 528MHz.
* => by default, ahb_podf divides by 4 => AHB_CLK@132MHz.
* => by default, ipg_podf divides by 2 => IPG_CLK@66MHz.
*/
HW_CCM_CBCDR.U = BF_CCM_CBCDR_AHB_PODF(3)
#if !defined(CHIP_MX6SL)
| BF_CCM_CBCDR_AXI_PODF(1)
#endif
| BF_CCM_CBCDR_IPG_PODF(1);
/*
* UART clock tree: PLL3 (480MHz) div-by-6: 80MHz
* 80MHz uart_clk_podf (div-by-1) = 80MHz (UART module clock input)
*/
// writel(readl(CCM_CSCDR1) & 0x0000003F, CCM_CSCDR1);
// HW_CCM_CSCDR1.U =
/* Mask all interrupt sources that could wake up the processor when in
a low power mode. A source is individually masked/unmasked when the
interrupt is enabled/disabled by the GIC/interrupt driver. */
HW_GPC_IMR1_WR(0xFFFFFFFF);
HW_GPC_IMR2_WR(0xFFFFFFFF);
HW_GPC_IMR3_WR(0xFFFFFFFF);
HW_GPC_IMR4_WR(0xFFFFFFFF);
}
uint32_t get_main_clock(main_clocks_t clock)
{
uint32_t ret_val = 0;
uint32_t pre_periph_clk_sel = HW_CCM_CBCMR.B.PRE_PERIPH_CLK_SEL;
switch (clock) {
case CPU_CLK:
ret_val = PLL1_OUTPUT;
break;
#if !defined(CHIP_MX6SL)
case AXI_CLK:
ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AXI_PODF + 1);
break;
case MMDC_CH0_AXI_CLK:
ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.MMDC_CH0_AXI_PODF + 1);
break;
#endif
case AHB_CLK:
ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF + 1);
break;
case IPG_CLK:
ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF + 1) / (HW_CCM_CBCDR.B.IPG_PODF + 1);
break;
case IPG_PER_CLK:
ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF + 1) / (HW_CCM_CBCDR.B.IPG_PODF + 1) / (HW_CCM_CSCMR1.B.PERCLK_PODF + 1);
break;
#if !defined(CHIP_MX6SL)
case MMDC_CH1_AXI_CLK:
ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.MMDC_CH1_AXI_PODF + 1);
break;
#endif
default:
break;
}
return ret_val;
}
uint32_t get_peri_clock(peri_clocks_t clock)
{
uint32_t ret_val = 0;
switch (clock) {
case UART1_MODULE_CLK:
case UART2_MODULE_CLK:
case UART3_MODULE_CLK:
case UART4_MODULE_CLK:
// UART source clock is a fixed PLL3 / 6
ret_val = PLL3_OUTPUT[0] / 6 / (HW_CCM_CSCDR1.B.UART_CLK_PODF + 1);
break;
// eCSPI clock:
// PLL3(480) -> /8 -> CSCDR2[ECSPI_CLK_PODF]
case SPI_CLK:
ret_val = PLL3_OUTPUT[0] / 8 / (HW_CCM_CSCDR2.B.ECSPI_CLK_PODF + 1);
break;
#if !defined(CHIP_MX6SL)
case RAWNAND_CLK:
ret_val = PLL3_OUTPUT[0] / (HW_CCM_CS2CDR.B.ENFC_CLK_PRED + 1) / (HW_CCM_CS2CDR.B.ENFC_CLK_PODF + 1);
break;
case CAN_CLK:
// For i.mx6dq/sdl CAN source clock is a fixed PLL3 / 8
ret_val = PLL3_OUTPUT[0] / 8 / (HW_CCM_CSCMR2.B.CAN_CLK_PODF + 1);
break;
#endif
default:
break;
}
return ret_val;
}
/*!
* Set/unset clock gating for a peripheral.
* @param ccm_ccgrx Address of the clock gating register: CCM_CCGR1,...
* @param cgx_offset Offset of the clock gating field: CG(x).
* @param gating_mode Clock gating mode: CLOCK_ON or CLOCK_OFF.
*/
void ccm_ccgr_config(uint32_t ccm_ccgrx, uint32_t cgx_offset, uint32_t gating_mode)
{
if (gating_mode == CLOCK_ON) {
*(volatile uint32_t*)(ccm_ccgrx) |= cgx_offset;
} else {
*(volatile uint32_t*)(ccm_ccgrx) &= ~cgx_offset;
}
}
void clock_gating_config(uint32_t base_address, uint32_t gating_mode)
{
uint32_t ccm_ccgrx = 0;
uint32_t cgx_offset = 0;
switch (base_address) {
case REGS_UART1_BASE:
case REGS_UART2_BASE:
case REGS_UART3_BASE:
case REGS_UART4_BASE:
case REGS_UART5_BASE:
ccm_ccgrx = HW_CCM_CCGR5_ADDR;
cgx_offset = CG(13) | CG(12);
break;
/// @todo: Add necessary gating only when you need
/// Should refer to original SDK
case GPT_BASE_ADDR:
ccm_ccgrx = HW_CCM_CCGR1_ADDR;
cgx_offset = CG(10);
break;
default:
break;
}
// apply changes only if a valid address was found
if (ccm_ccgrx != 0) {
ccm_ccgr_config(ccm_ccgrx, cgx_offset, gating_mode);
}
}
void ccm_set_lpm_wakeup_source(uint32_t irq_id, bool doEnable)
{
uint32_t reg_offset = 0;
uint32_t bit_offset = 0;
uint32_t gpc_imr = 0;
// calculate the offset of the register handling that interrupt ID
// ID starts at 32, so for instance ID=89 is handled by IMR2 because
// the integer part of the division is reg_offset = 2
reg_offset = (irq_id / 32);
// and the rest of the previous division is used to calculate the bit
// offset in the register, so for ID=89 this is bit_offset = 25
bit_offset = irq_id - 32 * reg_offset;
// get the current value of the corresponding GPC_IMRx register
gpc_imr = *((volatile uint32_t*)(HW_GPC_IMR1_ADDR + (reg_offset - 1) * 4));
if (doEnable) {
// clear the corresponding bit to unmask the interrupt source
gpc_imr &= ~(1 << bit_offset);
// write the new mask
*((volatile uint32_t*)(HW_GPC_IMR1_ADDR + (reg_offset - 1) * 4)) = (gpc_imr);
} else {
// set the corresponding bit to mask the interrupt source
gpc_imr |= (1 << bit_offset);
// write the new mask
*((volatile uint32_t*)(HW_GPC_IMR1_ADDR + (reg_offset - 1) * 4)) = (gpc_imr);
}
}
void ccm_enter_low_power(lp_modes_t lp_mode)
{
uint32_t ccm_clpcr = 0;
// if MMDC channel 1 is not used, the handshake must be masked
// set disable core clock in wait - set disable oscillator in stop
ccm_clpcr =
#if !defined(CHIP_MX6SL)
BM_CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS |
#endif
BM_CCM_CLPCR_SBYOS | BM_CCM_CLPCR_ARM_CLK_DIS_ON_LPM | lp_mode;
if (lp_mode == STOP_MODE) {
// enable peripherals well-biased
ccm_clpcr |= BM_CCM_CLPCR_WB_PER_AT_LPM;
}
HW_CCM_CLPCR_WR(ccm_clpcr);
__asm(
// data synchronization barrier (caches, TLB maintenance, ...)
"dsb;"
// wait for interrupt instruction
"wfi;"
// instruction synchronization barrier (flush the pipe-line)
"isb;");
return;
}
#if !defined(CHIP_MX6SL)
/*!
* @brief Configure ipu 1 and 2 hsp clk to default 264MHz
*
* ipu_hsp_clk is derived from mmdc_ch0 divided by 2.
*/
void ipu_hsp_clk_config(void)
{
// clk_sel from mmdc_ch0, podf=1
HW_CCM_CSCDR3_WR(BF_CCM_CSCDR3_IPU1_HSP_CLK_SEL(0)
| BF_CCM_CSCDR3_IPU1_HSP_PODF(1)
#if CHIP_MX6DQ
| BF_CCM_CSCDR3_IPU2_HSP_CLK_SEL(0)
| BF_CCM_CSCDR3_IPU2_HSP_PODF(1)
#endif // CHIP_MX6DQ
);
}
// void gpu_clock_config(void)
// {
// HW_CCM_ANALOG_PLL_VIDEO_NUM_WR(0xFF0D6C3);
// HW_CCM_ANALOG_PLL_VIDEO_WR(BF_CCM_ANALOG_PLL_VIDEO_DIV_SELECT(2) | BF_CCM_ANALOG_PLL_VIDEO_ENABLE(1) | BF_CCM_ANALOG_PLL_VIDEO_BYPASS(1));
// while (!HW_CCM_ANALOG_PLL_VIDEO.B.LOCK)
// ; // waiting for PLL lock
// BF_CLR(CCM_ANALOG_PLL_VIDEO, BYPASS);
// // ldb_di0_clk select PLL5
// HW_CCM_CS2CDR.B.LDB_DI0_CLK_SEL = 0; // PLL5
// HW_IOMUXC_GPR3.B.LVDS1_MUX_CTL = 0; // LVDS1 source is IPU1 DI0 port
// HW_IOMUXC_GPR3.B.LVDS0_MUX_CTL = 2; // LVDS0 source is IPU2 DI0 port
// HW_CCM_CHSCCDR.B.IPU1_DI0_CLK_SEL = 3; // derive clock from ldb_di0_clk
// HW_CCM_CSCMR2_SET(BM_CCM_CSCMR2_LDB_DI0_IPU_DIV | BM_CCM_CSCMR2_LDB_DI1_IPU_DIV); // ldb_di0 divided by 3.5
// #if CHIP_MX6DQ
// HW_CCM_CSCDR2.B.IPU2_DI0_CLK_SEL = 3; // derive clock from ldb_di0_clk
// HW_CCM_CSCDR2.B.IPU2_DI1_CLK_SEL = 3; // derive clock from 352M PFD
// #endif // CHIP_MX6DQ
// }
#endif
////////////////////////////////////////////////////////////////////////////////
// End of file
////////////////////////////////////////////////////////////////////////////////
Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/clock.c
+78
View File
@@ -0,0 +1,78 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file clock.c
* @brief clock interfaces of hardkernel
* @version 3.0
* @author AIIT XUOS Lab
* @date 2023.08.25
*/
/*************************************************
File name: clock.c
Description: clock interfaces of hardkernel
Others:
History:
1. Date: 2023-08-28
Author: AIIT XUOS Lab
Modification:
1. first version
*************************************************/
#include <stdint.h>
#include "ccm_pll.h"
#include "gpt.h"
#include "timer.h"
#include "clock_common_op.h"
#include "irq_numbers.h"
static void _sys_clock_init()
{
uint32_t freq = get_main_clock(IPG_CLK);
gpt_init(CLKSRC_IPG_CLK, freq / 1000000, RESTART_MODE, WAIT_MODE_EN | STOP_MODE_EN);
gpt_set_compare_event(kGPTOutputCompare1, OUTPUT_CMP_DISABLE, 1000);
gpt_counter_enable(kGPTOutputCompare1);
}
static uint32_t _get_clock_int()
{
return IMX_INT_GPT;
}
static uint64_t _get_tick()
{
return 0;
}
static uint64_t _get_second()
{
return 0;
}
static void _clear_clock_intr()
{
gpt_get_compare_event(kGPTOutputCompare1);
}
static struct XiziClockDriver hardkernel_clock_driver = (struct XiziClockDriver) {
.sys_clock_init = _sys_clock_init,
.get_clock_int = _get_clock_int,
.get_tick = _get_tick,
.get_second = _get_second,
.clear_clock_intr = _clear_clock_intr,
};
struct XiziClockDriver* hardkernel_clock_init(struct TraceTag* hardkernel_tag)
{
hardkernel_clock_driver.sys_clock_init();
return &hardkernel_clock_driver;
}
Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/gpt.c
+211
View File
@@ -0,0 +1,211 @@
/*
* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!
* @file gpt.c
* @brief GPT driver source file.
*
* @ingroup diag_timer
*/
#include <stdint.h>
#include "soc_memory_map.h"
#include "ccm_pll.h"
#include "regsgpt.h"
#include "timer.h"
#include "gpt.h"
#include "trap_common.h"
////////////////////////////////////////////////////////////////////////////////
// Code
////////////////////////////////////////////////////////////////////////////////
static inline void gpt_clear_all_events(void)
{
HW_GPT_SR_WR(kGPTAllEvents);
}
uint32_t gpt_get_rollover_event(void)
{
// clear it if found set
if (HW_GPT_SR.B.ROV) {
HW_GPT_SR_WR(BM_GPT_SR_ROV);
return kGPTRollover;
}
// return the read value before the bit was cleared
return 0;
}
uint32_t gpt_get_capture_event(uint8_t flag, uint32_t* capture_val)
{
// get the capture status bit
flag &= kGPTInputCapture1 | kGPTInputCapture2;
uint32_t status_register = HW_GPT_SR_RD() & flag;
// Read the captured timer value.
if (capture_val) {
if (status_register == kGPTInputCapture1) {
*(uint32_t*)capture_val = HW_GPT_ICR1.B.CAPT;
} else if (status_register == kGPTInputCapture2) {
*(uint32_t*)capture_val = HW_GPT_ICR2.B.CAPT;
}
}
// Clear the flag.
HW_GPT_SR_WR(status_register);
// return the read value before the bit was cleared
return status_register;
}
void gpt_set_capture_event(uint8_t cap_input, uint8_t cap_input_mode)
{
// set the new input mode
switch (cap_input) {
case kGPTInputCapture1:
HW_GPT_CR.B.IM1 = cap_input_mode;
break;
case kGPTInputCapture2:
HW_GPT_CR.B.IM2 = cap_input_mode;
break;
}
}
uint32_t gpt_get_compare_event(uint8_t flag)
{
// get the active compare flags
flag &= kGPTOutputCompare1 | kGPTOutputCompare2 | kGPTOutputCompare3;
uint32_t status_register = HW_GPT_SR_RD() & flag;
// clear flags which are active
if (status_register) {
HW_GPT_SR_WR(status_register);
}
// return the read value before the flags were cleared
return status_register;
}
void gpt_set_compare_event(uint8_t cmp_output, uint8_t cmp_output_mode, uint32_t cmp_value)
{
// set the value to compare with
switch (cmp_output) {
case kGPTOutputCompare1:
BW_GPT_CR_OM1(cmp_output_mode);
HW_GPT_OCR1_WR(cmp_value);
break;
case kGPTOutputCompare2:
BW_GPT_CR_OM2(cmp_output_mode);
HW_GPT_OCR2_WR(cmp_value);
break;
case kGPTOutputCompare3:
BW_GPT_CR_OM3(cmp_output_mode);
HW_GPT_OCR3_WR(cmp_value);
break;
}
}
void gpt_counter_disable(void)
{
// disable the counter
HW_GPT_CR.B.EN = 0;
// ensure to leave the counter in a proper state by disabling the interrupt sources
HW_GPT_IR_WR(0);
// and by clearing possible remaining events
gpt_clear_all_events();
}
void gpt_counter_enable(uint32_t irq_mode)
{
// ensure to start the counter in a proper state by clearing possible remaining events
gpt_clear_all_events();
// enable the interrupts or clear the register for polling
HW_GPT_IR_WR(irq_mode & kGPTAllEvents);
// finally, enable the counter
HW_GPT_CR.B.EN = 1;
}
void gpt_init(uint32_t clock_src, uint32_t prescaler, uint32_t counter_mode, uint32_t low_power_mode)
{
uint32_t control_reg_tmp = 0;
// enable the source clocks to the GPT port
clock_gating_config(GPT_BASE_ADDR, CLOCK_ON);
// start with a known state by disabling and reseting the module
HW_GPT_CR_WR(BM_GPT_CR_SWR);
// wait for the reset to complete
while (HW_GPT_CR.B.SWR != 0)
;
// set the reference source clock for the counter
if (clock_src == CLKSRC_CKIL) {
// CKIL source is 0x4 for GPT but 0x3 for EPIT
clock_src++;
}
control_reg_tmp |= BF_GPT_CR_CLKSRC(clock_src);
// the prescaler can be changed at any time, and
// this affects the output clock immediately
HW_GPT_PR_WR(BF_GPT_PR_PRESCALER(prescaler - 1));
// set the counter mode
control_reg_tmp |= BF_GPT_CR_FRR(counter_mode);
// set behavior for low power mode
if (low_power_mode & WAIT_MODE_EN) {
control_reg_tmp |= BM_GPT_CR_WAITEN;
}
if (low_power_mode & STOP_MODE_EN) {
control_reg_tmp |= BM_GPT_CR_STOPEN;
}
// specify from where the counter starts to count when enabled
// this code makes it start from 0
control_reg_tmp |= BM_GPT_CR_ENMOD;
// finally write the control register
HW_GPT_CR_WR(control_reg_tmp);
}
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/ccm_pll.h
+150
View File
@@ -0,0 +1,150 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _CCM_PLL_H_
#define _CCM_PLL_H_
#include <stdbool.h>
#include <stdint.h>
//! @addtogroup diag_clocks
//! @{
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
#define CLK_SRC_32K 32768
//! @brief Create a clock gate bit mask value.
//! @param x 0..15, for CG0 to CG15
#define CG(x) (3 << (x * 2))
//! @brief Constants for CCM CCGR register fields.
enum _clock_gate_constants {
CLOCK_ON = 0x3, //!< Clock always on in both run and stop modes.
CLOCK_ON_RUN = 0x1, //!< Clock on only in run mode.
CLOCK_OFF = 0x0 //!< Clocked gated off.
};
//! @brief Low power mdoes.
typedef enum _lp_modes {
RUN_MODE,
WAIT_MODE,
STOP_MODE,
} lp_modes_t;
//! @brief Main clock sources.
typedef enum _main_clocks {
CPU_CLK,
AXI_CLK,
MMDC_CH0_AXI_CLK,
AHB_CLK,
IPG_CLK,
IPG_PER_CLK,
MMDC_CH1_AXI_CLK,
} main_clocks_t;
//! @brief Peripheral clocks.
typedef enum _peri_clocks {
UART1_MODULE_CLK,
UART2_MODULE_CLK,
UART3_MODULE_CLK,
UART4_MODULE_CLK,
SSI1_BAUD,
SSI2_BAUD,
CSI_BAUD,
MSTICK1_CLK,
MSTICK2_CLK,
RAWNAND_CLK,
USB_CLK,
VPU_CLK,
SPI_CLK,
CAN_CLK
} peri_clocks_t;
//! @brief Available PLLs.
typedef enum plls {
PLL1,
PLL2,
PLL3,
PLL4,
PLL5,
} plls_t;
extern const uint32_t PLL1_OUTPUT;
extern const uint32_t PLL2_OUTPUT[];
extern const uint32_t PLL3_OUTPUT[];
extern const uint32_t PLL4_OUTPUT;
extern const uint32_t PLL5_OUTPUT;
////////////////////////////////////////////////////////////////////////////////
// API
////////////////////////////////////////////////////////////////////////////////
#if defined(__cplusplus)
extern "C" {
#endif
//! @brief Set/unset clock gating for a peripheral.
//! @param base_address configure clock gating for that module from the base address.
//! @param gating_mode clock gating mode: CLOCK_ON or CLOCK_OFF.
void clock_gating_config(uint32_t base_address, uint32_t gating_mode);
//! @brief Returns the frequency of a clock in megahertz.
uint32_t get_main_clock(main_clocks_t clk);
//! @brief Returns the frequency of a clock in megahertz.
uint32_t get_peri_clock(peri_clocks_t clk);
//! @brief Inits clock sources.
void ccm_init(void);
//! @brief Prepare and enter in a low power mode.
//! @param lp_mode low power mode : WAIT_MODE or STOP_MODE.
void ccm_enter_low_power(lp_modes_t lp_mode);
//! @brief Mask/unmask an interrupt source that can wake up the processor when in a
//! low power mode.
//!
//! @param irq_id ID of the interrupt to mask/unmask.
//! @param doEnable Pass true to unmask the source ID.
void ccm_set_lpm_wakeup_source(uint32_t irq_id, bool doEnable);
#if defined(__cplusplus)
}
#endif
//! @}
#endif
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/gpt.h
+219
View File
@@ -0,0 +1,219 @@
/*
* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//! @addtogroup diag_gpt
//! @{
/*!
* @file gpt.h
* @brief GPT driver public interface.
*/
#ifndef __GPT_H__
#define __GPT_H__
#include <stdbool.h>
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//! @brief Possible events for the GPT.
//!
//! These constants are intended to be combined together to form a bitmask. Several
//! of the GPT driver APIs use such a bitmask. For instance, gpt_counter_enable()
//! accepts a bitmask that selects the events for which interrupts should be enabled.
//!
//! Note that the values of these enums happen to be the bitmasks for the respective
//! fields in the HW_GPT_SR and HW_GPT_IR registers, so a mask constructed from them
//! can be used directly with register values.
enum _gpt_events {
kGPTNoEvent = 0, //!< No events enabled.
kGPTRollover = 1 << 5, //!< Rollover event.
kGPTInputCapture1 = 1 << 3, //!< Input capture 1 event.
kGPTInputCapture2 = 1 << 4, //!< Input capture 2 event.
kGPTOutputCompare1 = 1 << 0, //!< Output compare 1 event.
kGPTOutputCompare2 = 1 << 1, //!< Output compare 2 event.
kGPTOutputCompare3 = 1 << 2, //!< Output compare 3 event.
//! Combined mask of all GPT events.
kGPTAllEvents = kGPTRollover | kGPTInputCapture1 | kGPTInputCapture2
| kGPTOutputCompare1 | kGPTOutputCompare2 | kGPTOutputCompare3
};
//! @brief GPT counter modes.
enum _gpt_counter_mode {
RESTART_MODE = 0,
FREE_RUN_MODE = 1
};
//! @brief Supported input capture modes.
enum _gpt_capture_modes {
INPUT_CAP_DISABLE = 0, //!< input capture event disabled
INPUT_CAP_RISING_EDGE = 1, //!< input capture event on a rising edge
INPUT_CAP_FALLING_EDGE = 2, //!< input capture event on a falling edge
INPUT_CAP_BOTH_EDGE = 3 //!< input capture event on a both edge
};
//! @brief Supported output modes.
enum _gpt_compare_modes {
OUTPUT_CMP_DISABLE = 0, //!< output disconnected from pad
OUTPUT_CMP_TOGGLE = 1, //!< output toggle mode
OUTPUT_CMP_CLEAR = 2, //!< output set low mode
OUTPUT_CMP_SET = 3, //!< output set high mode
OUTPUT_CMP_LOWPULSE = 4 //!< output set high mode
};
////////////////////////////////////////////////////////////////////////////////
// API
////////////////////////////////////////////////////////////////////////////////
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Initialize the GPT timer.
*
* @param clock_src Source clock of the counter: CLKSRC_OFF, CLKSRC_IPG_CLK,
* CLKSRC_PER_CLK, CLKSRC_CKIL, CLKSRC_CLKIN.
* @param prescaler Prescaler of the source clock from 1 to 4096.
* @param counter_mode Counter mode: FREE_RUN_MODE or RESTART_MODE.
* @param low_power_mode Low power during which the timer is enabled:
* WAIT_MODE_EN and/or STOP_MODE_EN.
*/
void gpt_init(uint32_t clock_src, uint32_t prescaler, uint32_t counter_mode, uint32_t low_power_mode);
/*!
* @brief Setup GPT interrupt.
*
* It enables or disables the related HW module interrupt, and attached the
* related sub-routine into the vector table.
*
* @param irq_subroutine the GPT interrupt interrupt routine.
* @param enableIt Pass true to enable the interrupt.
*/
void gpt_setup_interrupt(void (*irq_subroutine)(void), bool enableIt);
/*!
* @brief Enable the GPT module.
*
* Used typically when the gpt_init is done, and other interrupt related settings are ready.
*
* If a value of #kGPTNoEvent is passed for @a irq_mode, then no interrupts will be enabled.
* This effectively puts the timer into polling mode, where you must call gpt_get_x_event()
* to check for an event having occurred.
*
* @param irq_mode Mask of events to enable interrupts for, such as #kGPTRollover or
* #kGPTOutputCompare1. See the #_gpt_events enum for the complete list. Pass
* #kGPTNoEvent to prevent any interrupts from being enabled, which effectively puts
* the timer into polling mode.
*/
void gpt_counter_enable(uint32_t irq_mode);
/*!
* @brief Disable the counter.
*
* It saves power when not used.
*
*/
void gpt_counter_disable(void);
/*!
* @brief Get rollover event flag and clear it if set.
*
* This function can typically be used for polling method, but
* is also used to clear the status compare flag in IRQ mode.
*
* @return Either 0 of kGPTRollover.
*/
uint32_t gpt_get_rollover_event(void);
/*!
* @brief Get a captured value when an event occured, and clear the flag if set.
*
* Use this function to check for an input capture event having occurred, either in
* the event ISR or to check manually in polling mode. Pass the input channel to check
* in the @a flag parameter. If that channel fired, its captured timer value will be
* read and placed in @a capture_val (if not NULL). The event that fired will be cleared
* and its event mask returned as the return value from the function. If no event
* occurred, the function returns 0.
*
* @param flag Which channel to check, either #kGPTInputCapture1 or #kGPTInputCapture2.
* Only one channel may be specified.
* @param capture_val The capture register value is returned through this parameter if
* the specified event occurred. May be NULL if not required.
* @return Mask of input specified capture event that occurred, or 0 if no event occurred.
*/
uint32_t gpt_get_capture_event(uint8_t flag, uint32_t* capture_val);
/*!
* @brief Set the input capture mode.
*
* @param cap_input The input capture channel to configure, either #kGPTInputCapture1
* or #kGPTInputCapture2.
* @param cap_input_mode Capture input mode: #INPUT_CAP_DISABLE, #INPUT_CAP_BOTH_EDGE,
* #INPUT_CAP_FALLING_EDGE, #INPUT_CAP_RISING_EDGE.
*/
void gpt_set_capture_event(uint8_t cap_input, uint8_t cap_input_mode);
/*!
* @brief Get a compare event flag and clear it if set.
*
* This function can typically be used for polling method, but
* is also used to clear the status compare flag in IRQ mode.
*
* @param flag Checked compare event flag such GPTSR_OF1, GPTSR_OF2, GPTSR_OF3.
* @return The value of the compare event flag.
*/
uint32_t gpt_get_compare_event(uint8_t flag);
/*!
* @brief Set a compare event by programming the compare register and
* compare output mode.
*
* @param cmp_output The channel to configure. Must be one of #kGPTOutputCompare1,
* #kGPTOutputCompare2, or #kGPTOutputCompare3.
* @param cmp_output_mode Compare output mode: #OUTPUT_CMP_DISABLE, #OUTPUT_CMP_TOGGLE,
* #OUTPUT_CMP_CLEAR, #OUTPUT_CMP_SET, #OUTPUT_CMP_LOWPULSE.
* @param cmp_value Compare value for the compare register.
*/
void gpt_set_compare_event(uint8_t cmp_output, uint8_t cmp_output_mode, uint32_t cmp_value);
#if defined(__cplusplus)
}
#endif
//! @}
#endif //__GPT_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////
Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/regsccm.h
+8757
View File
File diff suppressed because it is too large Load Diff
Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/regsccmanalog.h
+3256
View File
File diff suppressed because it is too large Load Diff
Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/regsgpc.h
+737
View File
@@ -0,0 +1,737 @@
/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*
* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
*
* This file was generated automatically and any changes may be lost.
*/
#ifndef __HW_GPC_REGISTERS_H__
#define __HW_GPC_REGISTERS_H__
#include "regs.h"
/*
* i.MX6DQ GPC
*
* GPC
*
* Registers defined in this header file:
* - HW_GPC_CNTR - GPC Interface control register
* - HW_GPC_PGR - GPC Power Gating Register
* - HW_GPC_IMR1 - IRQ masking register 1
* - HW_GPC_IMR2 - IRQ masking register 2
* - HW_GPC_IMR3 - IRQ masking register 3
* - HW_GPC_IMR4 - IRQ masking register 4
* - HW_GPC_ISR1 - IRQ status resister 1
* - HW_GPC_ISR2 - IRQ status resister 2
* - HW_GPC_ISR3 - IRQ status resister 3
* - HW_GPC_ISR4 - IRQ status resister 4
*
* - hw_gpc_t - Struct containing all module registers.
*/
//! @name Module base addresses
//@{
#ifndef REGS_GPC_BASE
#define HW_GPC_INSTANCE_COUNT (1) //!< Number of instances of the GPC module.
#define REGS_GPC_BASE (0x020dc000) //!< Base address for GPC.
#endif
//@}
//-------------------------------------------------------------------------------------------
// HW_GPC_CNTR - GPC Interface control register
//-------------------------------------------------------------------------------------------
// #ifndef __LANGUAGE_ASM__
// /*!
// * @brief HW_GPC_CNTR - GPC Interface control register (RW)
// *
// * Reset value: 0x00100000
// */
// typedef union _hw_gpc_cntr
// {
// reg32_t U;
// struct _hw_gpc_cntr_bitfields
// {
// unsigned GPU_VPU_PDN_REQ : 1; //!< [0] GPU /VPU Power Down request.
// unsigned GPU_VPU_PUP_REQ : 1; //!< [1] GPU /VPU Power Up request.
// unsigned RESERVED2 : 14; //!< [15:2] Reserved.
// unsigned DVFS0CR : 1; //!< [16] DVFS0 (ARM) Change request (bit is read-only)
// unsigned RESERVED3 : 4; //!< [20:17] Reserved.
// unsigned GPCIRQM : 1; //!< [21] GPC interrupt/event masking
// unsigned RESERVED4 : 10; //!< [31:22] Reserved.
// } B;
// } hw_gpc_cntr_t;
// #endif
// /*!
// * @name Constants and macros for entire GPC_CNTR register
// */
// //@{
// #define HW_GPC_CNTR_ADDR (REGS_GPC_BASE + 0x0)
// #ifndef __LANGUAGE_ASM__
// #define HW_GPC_CNTR (*(volatile hw_gpc_cntr_t *) HW_GPC_CNTR_ADDR)
// #define HW_GPC_CNTR_RD() (HW_GPC_CNTR.U)
// #define HW_GPC_CNTR_WR(v) (HW_GPC_CNTR.U = (v))
// #define HW_GPC_CNTR_SET(v) (HW_GPC_CNTR_WR(HW_GPC_CNTR_RD() | (v)))
// #define HW_GPC_CNTR_CLR(v) (HW_GPC_CNTR_WR(HW_GPC_CNTR_RD() & ~(v)))
// #define HW_GPC_CNTR_TOG(v) (HW_GPC_CNTR_WR(HW_GPC_CNTR_RD() ^ (v)))
// #endif
// //@}
// /*
// * constants & macros for individual GPC_CNTR bitfields
// */
// /*! @name Register GPC_CNTR, field GPU_VPU_PDN_REQ[0] (RW)
// *
// * GPU /VPU Power Down request. Self-cleared bit. * Note: Power switch for GPU /VPU power domain is
// * controlled by ANALOG configuration, not GPU /VPU PGC signals
// *
// * Values:
// * - 0 - no request
// * - 1 - Request Power Down sequence to start for GPU /VPU
// */
// //@{
// #define BP_GPC_CNTR_GPU_VPU_PDN_REQ (0) //!< Bit position for GPC_CNTR_GPU_VPU_PDN_REQ.
// #define BM_GPC_CNTR_GPU_VPU_PDN_REQ (0x00000001) //!< Bit mask for GPC_CNTR_GPU_VPU_PDN_REQ.
// //! @brief Get value of GPC_CNTR_GPU_VPU_PDN_REQ from a register value.
// #define BG_GPC_CNTR_GPU_VPU_PDN_REQ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_CNTR_GPU_VPU_PDN_REQ) >> BP_GPC_CNTR_GPU_VPU_PDN_REQ)
// //! @brief Format value for bitfield GPC_CNTR_GPU_VPU_PDN_REQ.
// #define BF_GPC_CNTR_GPU_VPU_PDN_REQ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_CNTR_GPU_VPU_PDN_REQ) & BM_GPC_CNTR_GPU_VPU_PDN_REQ)
// #ifndef __LANGUAGE_ASM__
// //! @brief Set the GPU_VPU_PDN_REQ field to a new value.
// #define BW_GPC_CNTR_GPU_VPU_PDN_REQ(v) (HW_GPC_CNTR_WR((HW_GPC_CNTR_RD() & ~BM_GPC_CNTR_GPU_VPU_PDN_REQ) | BF_GPC_CNTR_GPU_VPU_PDN_REQ(v)))
// #endif
// //@}
// /*! @name Register GPC_CNTR, field GPU_VPU_PUP_REQ[1] (RW)
// *
// * GPU /VPU Power Up request. Self-cleared bit. * Note: Power switch for GPU /VPU power domain is
// * controlled by ANALOG configuration, not GPU /VPU PGC signals
// *
// * Values:
// * - 0 - no request
// * - 1 - Request Power Up sequence to start for GPU /VPU
// */
// //@{
// #define BP_GPC_CNTR_GPU_VPU_PUP_REQ (1) //!< Bit position for GPC_CNTR_GPU_VPU_PUP_REQ.
// #define BM_GPC_CNTR_GPU_VPU_PUP_REQ (0x00000002) //!< Bit mask for GPC_CNTR_GPU_VPU_PUP_REQ.
// //! @brief Get value of GPC_CNTR_GPU_VPU_PUP_REQ from a register value.
// #define BG_GPC_CNTR_GPU_VPU_PUP_REQ(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_CNTR_GPU_VPU_PUP_REQ) >> BP_GPC_CNTR_GPU_VPU_PUP_REQ)
// //! @brief Format value for bitfield GPC_CNTR_GPU_VPU_PUP_REQ.
// #define BF_GPC_CNTR_GPU_VPU_PUP_REQ(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_CNTR_GPU_VPU_PUP_REQ) & BM_GPC_CNTR_GPU_VPU_PUP_REQ)
// #ifndef __LANGUAGE_ASM__
// //! @brief Set the GPU_VPU_PUP_REQ field to a new value.
// #define BW_GPC_CNTR_GPU_VPU_PUP_REQ(v) (HW_GPC_CNTR_WR((HW_GPC_CNTR_RD() & ~BM_GPC_CNTR_GPU_VPU_PUP_REQ) | BF_GPC_CNTR_GPU_VPU_PUP_REQ(v)))
// #endif
// //@}
// /*! @name Register GPC_CNTR, field DVFS0CR[16] (RO)
// *
// * DVFS0 (ARM) Change request (bit is read-only)
// *
// * Values:
// * - 0 - DVFS0 has no request
// * - 1 - DVFS0 is requesting for frequency/voltage update
// */
// //@{
// #define BP_GPC_CNTR_DVFS0CR (16) //!< Bit position for GPC_CNTR_DVFS0CR.
// #define BM_GPC_CNTR_DVFS0CR (0x00010000) //!< Bit mask for GPC_CNTR_DVFS0CR.
// //! @brief Get value of GPC_CNTR_DVFS0CR from a register value.
// #define BG_GPC_CNTR_DVFS0CR(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_CNTR_DVFS0CR) >> BP_GPC_CNTR_DVFS0CR)
// //@}
// /*! @name Register GPC_CNTR, field GPCIRQM[21] (RW)
// *
// * GPC interrupt/event masking
// *
// * Values:
// * - 0 - not masked
// * - 1 - interrupt/event is masked
// */
// //@{
// #define BP_GPC_CNTR_GPCIRQM (21) //!< Bit position for GPC_CNTR_GPCIRQM.
// #define BM_GPC_CNTR_GPCIRQM (0x00200000) //!< Bit mask for GPC_CNTR_GPCIRQM.
// //! @brief Get value of GPC_CNTR_GPCIRQM from a register value.
// #define BG_GPC_CNTR_GPCIRQM(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_CNTR_GPCIRQM) >> BP_GPC_CNTR_GPCIRQM)
// //! @brief Format value for bitfield GPC_CNTR_GPCIRQM.
// #define BF_GPC_CNTR_GPCIRQM(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_CNTR_GPCIRQM) & BM_GPC_CNTR_GPCIRQM)
// #ifndef __LANGUAGE_ASM__
// //! @brief Set the GPCIRQM field to a new value.
// #define BW_GPC_CNTR_GPCIRQM(v) (HW_GPC_CNTR_WR((HW_GPC_CNTR_RD() & ~BM_GPC_CNTR_GPCIRQM) | BF_GPC_CNTR_GPCIRQM(v)))
// #endif
// //@}
// //-------------------------------------------------------------------------------------------
// // HW_GPC_PGR - GPC Power Gating Register
// //-------------------------------------------------------------------------------------------
// #ifndef __LANGUAGE_ASM__
// /*!
// * @brief HW_GPC_PGR - GPC Power Gating Register (RW)
// *
// * Reset value: 0x00000000
// */
// typedef union _hw_gpc_pgr
// {
// reg32_t U;
// struct _hw_gpc_pgr_bitfields
// {
// unsigned RESERVED0 : 29; //!< [28:0] Reserved
// unsigned DRCIC : 2; //!< [30:29] Debug ref cir in mux control
// unsigned RESERVED1 : 1; //!< [31] Reserved
// } B;
// } hw_gpc_pgr_t;
// #endif
// /*!
// * @name Constants and macros for entire GPC_PGR register
// */
// //@{
// #define HW_GPC_PGR_ADDR (REGS_GPC_BASE + 0x4)
// #ifndef __LANGUAGE_ASM__
// #define HW_GPC_PGR (*(volatile hw_gpc_pgr_t *) HW_GPC_PGR_ADDR)
// #define HW_GPC_PGR_RD() (HW_GPC_PGR.U)
// #define HW_GPC_PGR_WR(v) (HW_GPC_PGR.U = (v))
// #define HW_GPC_PGR_SET(v) (HW_GPC_PGR_WR(HW_GPC_PGR_RD() | (v)))
// #define HW_GPC_PGR_CLR(v) (HW_GPC_PGR_WR(HW_GPC_PGR_RD() & ~(v)))
// #define HW_GPC_PGR_TOG(v) (HW_GPC_PGR_WR(HW_GPC_PGR_RD() ^ (v)))
// #endif
// //@}
// /*
// * constants & macros for individual GPC_PGR bitfields
// */
// /*! @name Register GPC_PGR, field DRCIC[30:29] (RW)
// *
// * Debug ref cir in mux control
// *
// * Values:
// * - 00 - ccm_cosr_1_clk_in
// * - 01 - ccm_cosr_2_clk_in
// * - 10 - restricted
// * - 11 - restricted
// */
// //@{
// #define BP_GPC_PGR_DRCIC (29) //!< Bit position for GPC_PGR_DRCIC.
// #define BM_GPC_PGR_DRCIC (0x60000000) //!< Bit mask for GPC_PGR_DRCIC.
// //! @brief Get value of GPC_PGR_DRCIC from a register value.
// #define BG_GPC_PGR_DRCIC(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_PGR_DRCIC) >> BP_GPC_PGR_DRCIC)
// //! @brief Format value for bitfield GPC_PGR_DRCIC.
// #define BF_GPC_PGR_DRCIC(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_PGR_DRCIC) & BM_GPC_PGR_DRCIC)
// #ifndef __LANGUAGE_ASM__
// //! @brief Set the DRCIC field to a new value.
// #define BW_GPC_PGR_DRCIC(v) (HW_GPC_PGR_WR((HW_GPC_PGR_RD() & ~BM_GPC_PGR_DRCIC) | BF_GPC_PGR_DRCIC(v)))
// #endif
// //@}
// //-------------------------------------------------------------------------------------------
// // HW_GPC_IMR1 - IRQ masking register 1
// //-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPC_IMR1 - IRQ masking register 1 (RW)
*
* Reset value: 0x00000000
*
* IMR1 Register - masking of irq[63:32].
*/
typedef union _hw_gpc_imr1
{
reg32_t U;
struct _hw_gpc_imr1_bitfields
{
unsigned IMR1 : 32; //!< [31:0] IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked
} B;
} hw_gpc_imr1_t;
#endif
/*!
* @name Constants and macros for entire GPC_IMR1 register
*/
//@{
#define HW_GPC_IMR1_ADDR (REGS_GPC_BASE + 0x8)
#ifndef __LANGUAGE_ASM__
#define HW_GPC_IMR1 (*(volatile hw_gpc_imr1_t *) HW_GPC_IMR1_ADDR)
#define HW_GPC_IMR1_RD() (HW_GPC_IMR1.U)
#define HW_GPC_IMR1_WR(v) (HW_GPC_IMR1.U = (v))
#define HW_GPC_IMR1_SET(v) (HW_GPC_IMR1_WR(HW_GPC_IMR1_RD() | (v)))
#define HW_GPC_IMR1_CLR(v) (HW_GPC_IMR1_WR(HW_GPC_IMR1_RD() & ~(v)))
#define HW_GPC_IMR1_TOG(v) (HW_GPC_IMR1_WR(HW_GPC_IMR1_RD() ^ (v)))
#endif
//@}
// /*
// * constants & macros for individual GPC_IMR1 bitfields
// */
// /*! @name Register GPC_IMR1, field IMR1[31:0] (RW)
// *
// * IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked
// */
// //@{
// #define BP_GPC_IMR1_IMR1 (0) //!< Bit position for GPC_IMR1_IMR1.
// #define BM_GPC_IMR1_IMR1 (0xffffffff) //!< Bit mask for GPC_IMR1_IMR1.
// //! @brief Get value of GPC_IMR1_IMR1 from a register value.
// #define BG_GPC_IMR1_IMR1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_IMR1_IMR1) >> BP_GPC_IMR1_IMR1)
// //! @brief Format value for bitfield GPC_IMR1_IMR1.
// #define BF_GPC_IMR1_IMR1(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_IMR1_IMR1) & BM_GPC_IMR1_IMR1)
// #ifndef __LANGUAGE_ASM__
// //! @brief Set the IMR1 field to a new value.
// #define BW_GPC_IMR1_IMR1(v) (HW_GPC_IMR1_WR((HW_GPC_IMR1_RD() & ~BM_GPC_IMR1_IMR1) | BF_GPC_IMR1_IMR1(v)))
// #endif
// //@}
// //-------------------------------------------------------------------------------------------
// // HW_GPC_IMR2 - IRQ masking register 2
// //-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPC_IMR2 - IRQ masking register 2 (RW)
*
* Reset value: 0x00000000
*
* IMR2 Register - masking of irq[95:64].
*/
typedef union _hw_gpc_imr2
{
reg32_t U;
struct _hw_gpc_imr2_bitfields
{
unsigned IMR2 : 32; //!< [31:0] IRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked
} B;
} hw_gpc_imr2_t;
#endif
/*!
* @name Constants and macros for entire GPC_IMR2 register
*/
//@{
#define HW_GPC_IMR2_ADDR (REGS_GPC_BASE + 0xc)
#ifndef __LANGUAGE_ASM__
#define HW_GPC_IMR2 (*(volatile hw_gpc_imr2_t *) HW_GPC_IMR2_ADDR)
#define HW_GPC_IMR2_RD() (HW_GPC_IMR2.U)
#define HW_GPC_IMR2_WR(v) (HW_GPC_IMR2.U = (v))
#define HW_GPC_IMR2_SET(v) (HW_GPC_IMR2_WR(HW_GPC_IMR2_RD() | (v)))
#define HW_GPC_IMR2_CLR(v) (HW_GPC_IMR2_WR(HW_GPC_IMR2_RD() & ~(v)))
#define HW_GPC_IMR2_TOG(v) (HW_GPC_IMR2_WR(HW_GPC_IMR2_RD() ^ (v)))
#endif
//@}
// /*
// * constants & macros for individual GPC_IMR2 bitfields
// */
// /*! @name Register GPC_IMR2, field IMR2[31:0] (RW)
// *
// * IRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked
// */
// //@{
// #define BP_GPC_IMR2_IMR2 (0) //!< Bit position for GPC_IMR2_IMR2.
// #define BM_GPC_IMR2_IMR2 (0xffffffff) //!< Bit mask for GPC_IMR2_IMR2.
// //! @brief Get value of GPC_IMR2_IMR2 from a register value.
// #define BG_GPC_IMR2_IMR2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_IMR2_IMR2) >> BP_GPC_IMR2_IMR2)
// //! @brief Format value for bitfield GPC_IMR2_IMR2.
// #define BF_GPC_IMR2_IMR2(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_IMR2_IMR2) & BM_GPC_IMR2_IMR2)
// #ifndef __LANGUAGE_ASM__
// //! @brief Set the IMR2 field to a new value.
// #define BW_GPC_IMR2_IMR2(v) (HW_GPC_IMR2_WR((HW_GPC_IMR2_RD() & ~BM_GPC_IMR2_IMR2) | BF_GPC_IMR2_IMR2(v)))
// #endif
// //@}
// //-------------------------------------------------------------------------------------------
// // HW_GPC_IMR3 - IRQ masking register 3
// //-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPC_IMR3 - IRQ masking register 3 (RW)
*
* Reset value: 0x00000000
*
* IMR3 Register - masking of irq[127:96].
*/
typedef union _hw_gpc_imr3
{
reg32_t U;
struct _hw_gpc_imr3_bitfields
{
unsigned IMR3 : 32; //!< [31:0] IRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked
} B;
} hw_gpc_imr3_t;
#endif
/*!
* @name Constants and macros for entire GPC_IMR3 register
*/
//@{
#define HW_GPC_IMR3_ADDR (REGS_GPC_BASE + 0x10)
#ifndef __LANGUAGE_ASM__
#define HW_GPC_IMR3 (*(volatile hw_gpc_imr3_t *) HW_GPC_IMR3_ADDR)
#define HW_GPC_IMR3_RD() (HW_GPC_IMR3.U)
#define HW_GPC_IMR3_WR(v) (HW_GPC_IMR3.U = (v))
#define HW_GPC_IMR3_SET(v) (HW_GPC_IMR3_WR(HW_GPC_IMR3_RD() | (v)))
#define HW_GPC_IMR3_CLR(v) (HW_GPC_IMR3_WR(HW_GPC_IMR3_RD() & ~(v)))
#define HW_GPC_IMR3_TOG(v) (HW_GPC_IMR3_WR(HW_GPC_IMR3_RD() ^ (v)))
#endif
//@}
// /*
// * constants & macros for individual GPC_IMR3 bitfields
// */
// /*! @name Register GPC_IMR3, field IMR3[31:0] (RW)
// *
// * IRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked
// */
// //@{
// #define BP_GPC_IMR3_IMR3 (0) //!< Bit position for GPC_IMR3_IMR3.
// #define BM_GPC_IMR3_IMR3 (0xffffffff) //!< Bit mask for GPC_IMR3_IMR3.
// //! @brief Get value of GPC_IMR3_IMR3 from a register value.
// #define BG_GPC_IMR3_IMR3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_IMR3_IMR3) >> BP_GPC_IMR3_IMR3)
// //! @brief Format value for bitfield GPC_IMR3_IMR3.
// #define BF_GPC_IMR3_IMR3(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_IMR3_IMR3) & BM_GPC_IMR3_IMR3)
// #ifndef __LANGUAGE_ASM__
// //! @brief Set the IMR3 field to a new value.
// #define BW_GPC_IMR3_IMR3(v) (HW_GPC_IMR3_WR((HW_GPC_IMR3_RD() & ~BM_GPC_IMR3_IMR3) | BF_GPC_IMR3_IMR3(v)))
// #endif
// //@}
// //-------------------------------------------------------------------------------------------
// // HW_GPC_IMR4 - IRQ masking register 4
// //-------------------------------------------------------------------------------------------
#ifndef __LANGUAGE_ASM__
/*!
* @brief HW_GPC_IMR4 - IRQ masking register 4 (RW)
*
* Reset value: 0x00000000
*
* IMR4 Register - masking of irq[159:128].
*/
typedef union _hw_gpc_imr4
{
reg32_t U;
struct _hw_gpc_imr4_bitfields
{
unsigned IMR4 : 32; //!< [31:0] IRQ[159:128] masking bits: 1-irq masked, 0-irq is not masked
} B;
} hw_gpc_imr4_t;
#endif
/*!
* @name Constants and macros for entire GPC_IMR4 register
*/
//@{
#define HW_GPC_IMR4_ADDR (REGS_GPC_BASE + 0x14)
#ifndef __LANGUAGE_ASM__
#define HW_GPC_IMR4 (*(volatile hw_gpc_imr4_t *) HW_GPC_IMR4_ADDR)
#define HW_GPC_IMR4_RD() (HW_GPC_IMR4.U)
#define HW_GPC_IMR4_WR(v) (HW_GPC_IMR4.U = (v))
#define HW_GPC_IMR4_SET(v) (HW_GPC_IMR4_WR(HW_GPC_IMR4_RD() | (v)))
#define HW_GPC_IMR4_CLR(v) (HW_GPC_IMR4_WR(HW_GPC_IMR4_RD() & ~(v)))
#define HW_GPC_IMR4_TOG(v) (HW_GPC_IMR4_WR(HW_GPC_IMR4_RD() ^ (v)))
#endif
//@}
// /*
// * constants & macros for individual GPC_IMR4 bitfields
// */
// /*! @name Register GPC_IMR4, field IMR4[31:0] (RW)
// *
// * IRQ[159:128] masking bits: 1-irq masked, 0-irq is not masked
// */
// //@{
// #define BP_GPC_IMR4_IMR4 (0) //!< Bit position for GPC_IMR4_IMR4.
// #define BM_GPC_IMR4_IMR4 (0xffffffff) //!< Bit mask for GPC_IMR4_IMR4.
// //! @brief Get value of GPC_IMR4_IMR4 from a register value.
// #define BG_GPC_IMR4_IMR4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_IMR4_IMR4) >> BP_GPC_IMR4_IMR4)
// //! @brief Format value for bitfield GPC_IMR4_IMR4.
// #define BF_GPC_IMR4_IMR4(v) ((__REG_VALUE_TYPE((v), reg32_t) << BP_GPC_IMR4_IMR4) & BM_GPC_IMR4_IMR4)
// #ifndef __LANGUAGE_ASM__
// //! @brief Set the IMR4 field to a new value.
// #define BW_GPC_IMR4_IMR4(v) (HW_GPC_IMR4_WR((HW_GPC_IMR4_RD() & ~BM_GPC_IMR4_IMR4) | BF_GPC_IMR4_IMR4(v)))
// #endif
// //@}
// //-------------------------------------------------------------------------------------------
// // HW_GPC_ISR1 - IRQ status resister 1
// //-------------------------------------------------------------------------------------------
// #ifndef __LANGUAGE_ASM__
// /*!
// * @brief HW_GPC_ISR1 - IRQ status resister 1 (RO)
// *
// * Reset value: 0x00000000
// *
// * ISR1 Register - status of irq [63:32].
// */
// typedef union _hw_gpc_isr1
// {
// reg32_t U;
// struct _hw_gpc_isr1_bitfields
// {
// unsigned ISR1 : 32; //!< [31:0] IRQ[63:32] status, read only
// } B;
// } hw_gpc_isr1_t;
// #endif
// /*!
// * @name Constants and macros for entire GPC_ISR1 register
// */
// //@{
// #define HW_GPC_ISR1_ADDR (REGS_GPC_BASE + 0x18)
// #ifndef __LANGUAGE_ASM__
// #define HW_GPC_ISR1 (*(volatile hw_gpc_isr1_t *) HW_GPC_ISR1_ADDR)
// #define HW_GPC_ISR1_RD() (HW_GPC_ISR1.U)
// #endif
// //@}
// /*
// * constants & macros for individual GPC_ISR1 bitfields
// */
// /*! @name Register GPC_ISR1, field ISR1[31:0] (RO)
// *
// * IRQ[63:32] status, read only
// */
// //@{
// #define BP_GPC_ISR1_ISR1 (0) //!< Bit position for GPC_ISR1_ISR1.
// #define BM_GPC_ISR1_ISR1 (0xffffffff) //!< Bit mask for GPC_ISR1_ISR1.
// //! @brief Get value of GPC_ISR1_ISR1 from a register value.
// #define BG_GPC_ISR1_ISR1(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_ISR1_ISR1) >> BP_GPC_ISR1_ISR1)
// //@}
// //-------------------------------------------------------------------------------------------
// // HW_GPC_ISR2 - IRQ status resister 2
// //-------------------------------------------------------------------------------------------
// #ifndef __LANGUAGE_ASM__
// /*!
// * @brief HW_GPC_ISR2 - IRQ status resister 2 (RO)
// *
// * Reset value: 0x00000000
// *
// * ISR2 Register - status of irq [95:64].
// */
// typedef union _hw_gpc_isr2
// {
// reg32_t U;
// struct _hw_gpc_isr2_bitfields
// {
// unsigned ISR2 : 32; //!< [31:0] IRQ[95:64] status, read only
// } B;
// } hw_gpc_isr2_t;
// #endif
// /*!
// * @name Constants and macros for entire GPC_ISR2 register
// */
// //@{
// #define HW_GPC_ISR2_ADDR (REGS_GPC_BASE + 0x1c)
// #ifndef __LANGUAGE_ASM__
// #define HW_GPC_ISR2 (*(volatile hw_gpc_isr2_t *) HW_GPC_ISR2_ADDR)
// #define HW_GPC_ISR2_RD() (HW_GPC_ISR2.U)
// #endif
// //@}
// /*
// * constants & macros for individual GPC_ISR2 bitfields
// */
// /*! @name Register GPC_ISR2, field ISR2[31:0] (RO)
// *
// * IRQ[95:64] status, read only
// */
// //@{
// #define BP_GPC_ISR2_ISR2 (0) //!< Bit position for GPC_ISR2_ISR2.
// #define BM_GPC_ISR2_ISR2 (0xffffffff) //!< Bit mask for GPC_ISR2_ISR2.
// //! @brief Get value of GPC_ISR2_ISR2 from a register value.
// #define BG_GPC_ISR2_ISR2(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_ISR2_ISR2) >> BP_GPC_ISR2_ISR2)
// //@}
// //-------------------------------------------------------------------------------------------
// // HW_GPC_ISR3 - IRQ status resister 3
// //-------------------------------------------------------------------------------------------
// #ifndef __LANGUAGE_ASM__
// /*!
// * @brief HW_GPC_ISR3 - IRQ status resister 3 (RO)
// *
// * Reset value: 0x00000000
// *
// * ISR3 Register - status of irq [127:96].
// */
// typedef union _hw_gpc_isr3
// {
// reg32_t U;
// struct _hw_gpc_isr3_bitfields
// {
// unsigned ISR3 : 32; //!< [31:0] IRQ[127:96] status, read only
// } B;
// } hw_gpc_isr3_t;
// #endif
// /*!
// * @name Constants and macros for entire GPC_ISR3 register
// */
// //@{
// #define HW_GPC_ISR3_ADDR (REGS_GPC_BASE + 0x20)
// #ifndef __LANGUAGE_ASM__
// #define HW_GPC_ISR3 (*(volatile hw_gpc_isr3_t *) HW_GPC_ISR3_ADDR)
// #define HW_GPC_ISR3_RD() (HW_GPC_ISR3.U)
// #endif
// //@}
// /*
// * constants & macros for individual GPC_ISR3 bitfields
// */
// /*! @name Register GPC_ISR3, field ISR3[31:0] (RO)
// *
// * IRQ[127:96] status, read only
// */
// //@{
// #define BP_GPC_ISR3_ISR3 (0) //!< Bit position for GPC_ISR3_ISR3.
// #define BM_GPC_ISR3_ISR3 (0xffffffff) //!< Bit mask for GPC_ISR3_ISR3.
// //! @brief Get value of GPC_ISR3_ISR3 from a register value.
// #define BG_GPC_ISR3_ISR3(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_ISR3_ISR3) >> BP_GPC_ISR3_ISR3)
// //@}
// //-------------------------------------------------------------------------------------------
// // HW_GPC_ISR4 - IRQ status resister 4
// //-------------------------------------------------------------------------------------------
// #ifndef __LANGUAGE_ASM__
// /*!
// * @brief HW_GPC_ISR4 - IRQ status resister 4 (RO)
// *
// * Reset value: 0x00000000
// *
// * ISR4 Register - status of irq [159:128].
// */
// typedef union _hw_gpc_isr4
// {
// reg32_t U;
// struct _hw_gpc_isr4_bitfields
// {
// unsigned ISR4 : 32; //!< [31:0] IRQ[159:128] status, read only
// } B;
// } hw_gpc_isr4_t;
// #endif
// /*!
// * @name Constants and macros for entire GPC_ISR4 register
// */
// //@{
// #define HW_GPC_ISR4_ADDR (REGS_GPC_BASE + 0x24)
// #ifndef __LANGUAGE_ASM__
// #define HW_GPC_ISR4 (*(volatile hw_gpc_isr4_t *) HW_GPC_ISR4_ADDR)
// #define HW_GPC_ISR4_RD() (HW_GPC_ISR4.U)
// #endif
// //@}
// /*
// * constants & macros for individual GPC_ISR4 bitfields
// */
// /*! @name Register GPC_ISR4, field ISR4[31:0] (RO)
// *
// * IRQ[159:128] status, read only
// */
// //@{
// #define BP_GPC_ISR4_ISR4 (0) //!< Bit position for GPC_ISR4_ISR4.
// #define BM_GPC_ISR4_ISR4 (0xffffffff) //!< Bit mask for GPC_ISR4_ISR4.
// //! @brief Get value of GPC_ISR4_ISR4 from a register value.
// #define BG_GPC_ISR4_ISR4(r) ((__REG_VALUE_TYPE((r), reg32_t) & BM_GPC_ISR4_ISR4) >> BP_GPC_ISR4_ISR4)
// //@}
//-------------------------------------------------------------------------------------------
// hw_gpc_t - module struct
//-------------------------------------------------------------------------------------------
/*!
* @brief All GPC module registers.
*/
#ifndef __LANGUAGE_ASM__
#pragma pack(1)
// typedef struct _hw_gpc
// {
// volatile hw_gpc_cntr_t CNTR; //!< GPC Interface control register
// volatile hw_gpc_pgr_t PGR; //!< GPC Power Gating Register
// volatile hw_gpc_imr1_t IMR1; //!< IRQ masking register 1
// volatile hw_gpc_imr2_t IMR2; //!< IRQ masking register 2
// volatile hw_gpc_imr3_t IMR3; //!< IRQ masking register 3
// volatile hw_gpc_imr4_t IMR4; //!< IRQ masking register 4
// volatile hw_gpc_isr1_t ISR1; //!< IRQ status resister 1
// volatile hw_gpc_isr2_t ISR2; //!< IRQ status resister 2
// volatile hw_gpc_isr3_t ISR3; //!< IRQ status resister 3
// volatile hw_gpc_isr4_t ISR4; //!< IRQ status resister 4
// } hw_gpc_t;
// #pragma pack()
// //! @brief Macro to access all GPC registers.
// //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
// //! use the '&' operator, like <code>&HW_GPC</code>.
// #define HW_GPC (*(hw_gpc_t *) REGS_GPC_BASE)
#endif
#endif // __HW_GPC_REGISTERS_H__
// v18/121106/1.2.2
// EOF
Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/regsgpt.h
+1361
View File
File diff suppressed because it is too large Load Diff
Ubiquitous/XiZi_AIoT/hardkernel/clock/arm/armv7-a/cortex-a9/imx6q-sabrelite/include/timer.h
+109
View File
@@ -0,0 +1,109 @@
/*
* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//! @addtogroup diag_timer
//! @{
/*!
* @file timer.h
* @brief various defines used by the timer driver.
*/
#ifndef __TIMER_H__
#define __TIMER_H__
#include <stdint.h>
////////////////////////////////////////////////////////////////////////////////
// Constants
////////////////////////////////////////////////////////////////////////////////
//! @brief Options for low power mode support for the timers.
//!
//! These constants are bit masks that are or'd together to select in which low
//! power modes the timer will continue counting.
enum _timer_low_power_modes {
WAIT_MODE_EN = 1, //!< Timer is enabled in wait mode.
STOP_MODE_EN = 2 //!< Timer is enabled in stop mode.
};
//! @brief Available clock sources for the timers.
enum _timer_clock_sources {
CLKSRC_OFF = 0, //!< clock source is OFF
CLKSRC_IPG_CLK = 1, //!< clock source is peripheral clock
CLKSRC_PER_CLK = 2, //!< clock source is high-freq reference clock
CLKSRC_CLKIN = 3, //!< clock source is external from a CLKIN input
CLKSRC_CKIL = 3 //!< clock source is low-freq reference clock
};
//! @brief Do not enable interrupts.
#define POLLING_MODE 0
////////////////////////////////////////////////////////////////////////////////
// Externs
////////////////////////////////////////////////////////////////////////////////
extern uint32_t g_system_timer_port;
////////////////////////////////////////////////////////////////////////////////
// API
////////////////////////////////////////////////////////////////////////////////
#if defined(__cplusplus)
extern "C" {
#endif
//! @brief Delay for a given number of microseconds.
//!
//! system_time_init() must have been called before using this function.
//!
//! @param usecs Delay in microseconds.
void hal_delay_us(uint32_t usecs);
//! @brief Init system timer facilities.
//!
//! Inits the EPIT timer used for delay, and inits the microsecond counter.
void system_time_init(void);
//! @brief Return the current microsecond counter value.
//!
//! @return The number of microseconds elapsed since system_time_init()
//! was called. This value may roll over before reaching all ones.
uint64_t time_get_microseconds();
#if defined(__cplusplus)
}
#endif
//! @}
#endif // __TIMER_H__
////////////////////////////////////////////////////////////////////////////////
// EOF
////////////////////////////////////////////////////////////////////////////////