merge codes
This commit is contained in:
@@ -0,0 +1,12 @@
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if BSP_USING_I2C
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config I2C_BUS_NAME_1
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string "i2c bus 1 name"
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default "i2c1"
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config I2C_DRV_NAME_1
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string "i2c bus 1 driver name"
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default "i2c1_drv"
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config I2C_1_DEVICE_NAME_0
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string "i2c bus 1 device 0 name"
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default "i2c1_dev0"
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endif
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@@ -0,0 +1,3 @@
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SRC_FILES := connect_i2c.c connect_i2c_eeprom.c hardware_i2c.c fsl_lpi2c.c
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include $(KERNEL_ROOT)/compiler.mk
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@@ -0,0 +1,194 @@
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/*
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* Copyright (c) 2020 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2012-04-25 weety first version
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*/
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/**
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* @file connect_i2c.c
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* @brief support ok1052-c i2c function and register to bus framework
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2022-03-01
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*/
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/*************************************************
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File name: connect_i2c.c
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Description: support ok1052-c i2c configure and i2c bus register function
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Others: take RT-Thread v4.0.2/components/drivers/i2c/i2c-bit-ops.c for references
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https://github.com/RT-Thread/rt-thread/tree/v4.0.2
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History:
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1. Date: 2022-03-01
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Author: AIIT XUOS Lab
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Modification:
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1. support ok1052-c i2c bit configure, write and read
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2. support ok1052-c i2c bus device and driver register
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*************************************************/
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#include <board.h>
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#include "bus_serial.h"
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#include "connect_i2c.h"
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#include "fsl_lpi2c.h"
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#ifndef BSP_USING_I2C1
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#define BSP_USING_I2C1
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#endif
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static uint32 I2cWriteData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStandard *msg)
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{
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status_t ret;
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Stm32I2cType *param = (Stm32I2cType *)i2c_dev->haldev.private_data;
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ret = I2cHardwareWrite(param->base, param->slave_addr, param->sub_addr, msg->buf, msg->len);
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if(kStatus_Success == ret)
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return 1;
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return 0;
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}
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static uint32 I2cReadData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStandard *msg)
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{
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status_t ret;
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Stm32I2cType *param = (Stm32I2cType *)i2c_dev->haldev.private_data;
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ret = I2cHardwareRead(param->base, i2c_dev->i2c_dev_addr, param->sub_addr, msg->buf, msg->len);
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if(kStatus_Success == ret)
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return 1;
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return 0;
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}
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static uint32 I2cInit(struct I2cDriver *i2c_drv, struct BusConfigureInfo *configure_info)
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{
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NULL_PARAM_CHECK(i2c_drv);
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struct I2cHardwareDevice *i2c_dev = (struct I2cHardwareDevice *)i2c_drv->driver.owner_bus->owner_haldev;
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if (configure_info->private_data) {
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i2c_dev->i2c_dev_addr = *((uint16 *)configure_info->private_data);
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return EOK;
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}
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i2c_print("I2cInit need set i2c dev addr\n");
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return ERROR;
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}
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static uint32 I2cDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
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{
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NULL_PARAM_CHECK(drv);
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NULL_PARAM_CHECK(configure_info);
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x_err_t ret = EOK;
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struct I2cDriver *i2c_drv = (struct I2cDriver *)drv;
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switch (configure_info->configure_cmd)
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{
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case OPE_INT:
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ret = I2cInit(i2c_drv, configure_info);
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break;
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default:
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break;
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}
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return ret;
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}
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/*manage the i2c device operations*/
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static const struct I2cDevDone i2c_dev_done =
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{
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.dev_open = NONE,
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.dev_close = NONE,
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.dev_write = I2cWriteData,
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.dev_read = I2cReadData,
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};
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/*Init i2c bus*/
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static int BoardI2cBusInit(struct I2cBus *i2c_bus, struct I2cDriver *i2c_driver)
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{
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x_err_t ret = EOK;
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/*Init the i2c bus */
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i2c_bus->private_data = (void *)NULL;
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ret = I2cBusInit(i2c_bus, I2C_BUS_NAME_1);
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if (EOK != ret) {
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i2c_print("BoardI2cBusInit I2cBusInit error %d\n", ret);
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return ERROR;
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}
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/*Init the i2c driver*/
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i2c_driver->private_data = (void *)NULL;
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ret = I2cDriverInit(i2c_driver, I2C_DRV_NAME_1);
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if (EOK != ret) {
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i2c_print("BoardI2cBusInit I2cDriverInit error %d\n", ret);
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return ERROR;
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}
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/*Attach the i2c driver to the i2c bus*/
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ret = I2cDriverAttachToBus(I2C_DRV_NAME_1, I2C_BUS_NAME_1);
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if (EOK != ret) {
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i2c_print("BoardI2cBusInit I2cDriverAttachToBus error %d\n", ret);
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return ERROR;
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}
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return ret;
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}
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/*Attach the i2c device to the i2c bus*/
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static int BoardI2cDevBend(void)
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{
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x_err_t ret = EOK;
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static struct I2cHardwareDevice i2c_device0;
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memset(&i2c_device0, 0, sizeof(struct I2cHardwareDevice));
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i2c_device0.i2c_dev_done = &i2c_dev_done;
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ret = I2cDeviceRegister(&i2c_device0, NONE, I2C_1_DEVICE_NAME_0);
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if (EOK != ret) {
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i2c_print("BoardI2cDevBend I2cDeviceInit device %s error %d\n", I2C_1_DEVICE_NAME_0, ret);
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return ERROR;
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}
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ret = I2cDeviceAttachToBus(I2C_1_DEVICE_NAME_0, I2C_BUS_NAME_1);
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if (EOK != ret) {
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i2c_print("BoardI2cDevBend I2cDeviceAttachToBus device %s error %d\n", I2C_1_DEVICE_NAME_0, ret);
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return ERROR;
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}
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return ret;
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}
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/*BOARD I2C INIT*/
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int Stm32HwI2cInit(void)
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{
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static int init_flag = 0;
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x_err_t ret = EOK;
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if(init_flag)
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{
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return ret;
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}
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init_flag = 1;
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static struct I2cBus i2c_bus;
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memset(&i2c_bus, 0, sizeof(struct I2cBus));
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static struct I2cDriver i2c_driver;
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memset(&i2c_driver, 0, sizeof(struct I2cDriver));
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#ifdef BSP_USING_I2C1
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i2c_driver.configure = I2cDrvConfigure;
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ret = BoardI2cBusInit(&i2c_bus, &i2c_driver);
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if (EOK != ret) {
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i2c_print("board_i2c_Init error ret %u\n", ret);
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return ERROR;
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}
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ret = BoardI2cDevBend();
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if (EOK != ret) {
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i2c_print("board_i2c_Init error ret %u\n", ret);
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return ERROR;
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}
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#endif
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return ret;
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}
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@@ -0,0 +1,99 @@
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/*
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* The Clear BSD License
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file connect_i2c_eeprom.h
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* @brief ok1052-c eeprom relative codes
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2022-03-01
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*/
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#include "board.h"
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#include "connect_i2c.h"
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#include "fsl_lpi2c.h"
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#include "pin_mux.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define I2C_EEPROM_BASE LPI2C1
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#define I2C_EEPROM_ADDR (0xA0 >> 1)
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/*******************************************************************************
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* Code
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******************************************************************************/
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void I2cEEpromTestWrite(void)
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{
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uint8_t dat[8] = {0};
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if(I2cHardwareRead(I2C_EEPROM_BASE, I2C_EEPROM_ADDR, 0, dat, 8) == kStatus_Success)
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{
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i2c_print("Read from EEPROM %d %d %d %d %d %d %d %d\r\n",
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dat[0], dat[1], dat[2], dat[3], dat[4], dat[5], dat[6], dat[7]);
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}
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for(uint8_t i = 0; i < 8; i++)
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{
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dat[i] ++;
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}
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if(I2cHardwareWrite(I2C_EEPROM_BASE, I2C_EEPROM_ADDR, 0, dat, 8) == kStatus_Success)
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{
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i2c_print("Write to EEPROM %d %d %d %d %d %d %d %d\r\n",
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dat[0], dat[1], dat[2], dat[3], dat[4], dat[5], dat[6], dat[7]);
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}
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memset(dat, 0, 8);
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if(I2cHardwareRead(I2C_EEPROM_BASE, I2C_EEPROM_ADDR, 0, dat, 8) == kStatus_Success)
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{
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i2c_print("Read from EEPROM %d %d %d %d %d %d %d %d\r\n",
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dat[0], dat[1], dat[2], dat[3], dat[4], dat[5], dat[6], dat[7]);
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}
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}
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int I2cEEpromTest(void)
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{
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Stm32HwI2cInit();
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BOARD_InitI2C1Pins();
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I2cHardwareInit();
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I2cEEpromTestWrite();
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return 0;
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}
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SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)| SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN)| SHELL_CMD_PARAM_NUM(0),
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eeprom, I2cEEpromTest, test i2c eeprom);
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,94 @@
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/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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||||
* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
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||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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||||
*/
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/**
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* @file hardware_i2c.c
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* @brief ok1052-c i2c relative codes
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* @version 1.0
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* @author AIIT XUOS Lab
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* @date 2022-03-01
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*/
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#include "fsl_common.h"
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#include "fsl_lpi2c.h"
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#define I2C_BASE LPI2C1
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/* Select USB1 PLL (480 MHz) as master lpi2c clock source */
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#define LPI2C_CLOCK_SOURCE_SELECT (0U)
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/* Clock divider for master lpi2c clock source */
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#define LPI2C_CLOCK_SOURCE_DIVIDER (5U)
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#define I2C_CLOCK_FREQ ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER + 1U))
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#define I2C_BAUDRATE 100000U
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void I2cHardwareInit(void)
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{
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lpi2c_master_config_t masterConfig = {0};
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LPI2C_MasterGetDefaultConfig(&masterConfig);
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/* Change the default baudrate configuration */
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masterConfig.baudRate_Hz = I2C_BAUDRATE;
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/* Initialize the LPI2C master peripheral */
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LPI2C_MasterInit(I2C_BASE, &masterConfig, I2C_CLOCK_FREQ);
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}
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status_t I2cHardwareWrite(LPI2C_Type* base, uint16_t slave_addr, uint32_t subAdd, uint8_t* dataBuff, uint16_t dataLen)
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{
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lpi2c_master_transfer_t xfer;
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xfer.slaveAddress = slave_addr;
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xfer.direction = kLPI2C_Write;
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xfer.subaddress = subAdd;
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xfer.subaddressSize = 0x01;
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xfer.data = dataBuff;
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xfer.dataSize = dataLen;
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xfer.flags = kLPI2C_TransferDefaultFlag;
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return LPI2C_MasterTransferBlocking(base, &xfer);
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}
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status_t I2cHardwareRead(LPI2C_Type* base, uint16_t slave_addr, uint32_t subAdd, uint8_t* dataBuffer, uint16_t dataLen)
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{
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lpi2c_master_transfer_t masterXfer = {0};
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masterXfer.slaveAddress = slave_addr;
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masterXfer.direction = kLPI2C_Read;
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masterXfer.subaddress = subAdd;
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masterXfer.subaddressSize = 0x01;
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masterXfer.data = dataBuffer;
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masterXfer.dataSize = dataLen;
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masterXfer.flags = kLPI2C_TransferDefaultFlag;
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return LPI2C_MasterTransferBlocking(base, &masterXfer);
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}
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