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add semc driver and eth driver

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Wang_Weigen
2022-03-24 15:28:24 +08:00
parent 0340217e24
commit 1cf9939cb2
22 changed files with 8482 additions and 0 deletions
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Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/Kconfig
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config BSP_USING_EXTSRAM
bool "config semc extern sram"
default n
select MEM_EXTERN_SRAM
if BSP_USING_EXTSRAM
config EXTSRAM_MAX_NUM
int "config extsram chip num"
default 4
endif
Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/Makefile
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SRC_FILES := connect_semc.c fsl_semc.c semc_externsdram_test.c
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/connect_semc.c
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#include "fsl_semc.h"
#include "clock_config.h"
#include <xs_base.h>
#define EXAMPLE_SEMC SEMC
#define EXAMPLE_SEMC_START_ADDRESS (0x80000000U)
#define EXAMPLE_SEMC_CLK_FREQ CLOCK_GetFreq(kCLOCK_SemcClk)
#define SEMC_SRAM_SIZE (32 * 1024 * 1024)
status_t BOARD_InitSEMC(void)
{
semc_config_t config;
semc_sdram_config_t sdramconfig;
uint32_t clockFrq = EXAMPLE_SEMC_CLK_FREQ;
/* Initializes the MAC configure structure to zero. */
memset(&config, 0, sizeof(semc_config_t));
memset(&sdramconfig, 0, sizeof(semc_sdram_config_t));
/* Initialize SEMC. */
SEMC_GetDefaultConfig(&config);
config.dqsMode = kSEMC_Loopbackdqspad; /* For more accurate timing. */
SEMC_Init(SEMC, &config);
/* Configure SDRAM. */
sdramconfig.csxPinMux = kSEMC_MUXCSX0;
sdramconfig.address = 0x80000000;
sdramconfig.memsize_kbytes = 32 * 1024; /* 32MB = 32*1024*1KBytes*/
sdramconfig.portSize = kSEMC_PortSize16Bit;
sdramconfig.burstLen = kSEMC_Sdram_BurstLen8;
sdramconfig.columnAddrBitNum = kSEMC_SdramColunm_9bit;
sdramconfig.casLatency = kSEMC_LatencyThree;
sdramconfig.tPrecharge2Act_Ns = 18; /* Trp 18ns */
sdramconfig.tAct2ReadWrite_Ns = 18; /* Trcd 18ns */
sdramconfig.tRefreshRecovery_Ns = 67; /* Use the maximum of the (Trfc , Txsr). */
sdramconfig.tWriteRecovery_Ns = 12; /* 12ns */
sdramconfig.tCkeOff_Ns =
42; /* The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.*/
sdramconfig.tAct2Prechage_Ns = 42; /* Tras 42ns */
sdramconfig.tSelfRefRecovery_Ns = 67;
sdramconfig.tRefresh2Refresh_Ns = 60;
sdramconfig.tAct2Act_Ns = 60;
sdramconfig.tPrescalePeriod_Ns = 160 * (1000000000 / clockFrq);
sdramconfig.refreshPeriod_nsPerRow = 64 * 1000000 / 8192; /* 64ms/8192 */
sdramconfig.refreshUrgThreshold = sdramconfig.refreshPeriod_nsPerRow;
sdramconfig.refreshBurstLen = 1;
return SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdramconfig, clockFrq);
}
#ifdef BSP_USING_EXTSRAM
int ExtSramInit(void)
{
extern void ExtSramInitBoardMemory(void *start_phy_address, void *end_phy_address, uint8 extsram_idx);
ExtSramInitBoardMemory((void*)(EXAMPLE_SEMC_START_ADDRESS), (void*)((EXAMPLE_SEMC_START_ADDRESS + SEMC_SRAM_SIZE)), kSEMC_SDRAM_CS0);
return 0;
}
#endif
Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/fsl_semc.c
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Ubiquitous/XiZi/board/xidatong/third_party_driver/semc/semc_externsdram_test.c
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/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "board.h"
#define EXAMPLE_SEMC_START_ADDRESS (0x80000000U)
#define SEMC_EXAMPLE_DATALEN (0x1000U)
/*******************************************************************************
* Prototypes
******************************************************************************/
static void SEMC_SDRAMReadWrite32Bit(void);
static void SEMC_SDRAMReadWrite16Bit(void);
static void SEMC_SDRAMReadWrite8Bit(void);
/*******************************************************************************
* Variables
******************************************************************************/
uint32_t sdram_writeBuffer[SEMC_EXAMPLE_DATALEN];
uint32_t sdram_readBuffer[SEMC_EXAMPLE_DATALEN];
/*!
* @brief Main function
*/
int semc_externsram_test(void)
{
KPrintf("\r\n SEMC SDRAM Example Start!\r\n");
/* 32Bit data read and write. */
SEMC_SDRAMReadWrite32Bit();
/* 16Bit data read and write. */
SEMC_SDRAMReadWrite16Bit();
/* 8Bit data read and write. */
SEMC_SDRAMReadWrite8Bit();
KPrintf("\r\n SEMC SDRAM Example End.\r\n");
}
SHELL_EXPORT_CMD(SHELL_CMD_PERMISSION(0)|SHELL_CMD_TYPE(SHELL_TYPE_CMD_FUNC)|SHELL_CMD_PARAM_NUM(0),semc_externsram_test, semc_externsram_test, semc_externsram_test );
void SEMC_SDRAMReadWrite32Bit(void)
{
uint32_t index;
uint32_t datalen = SEMC_EXAMPLE_DATALEN;
uint32_t *sdram = (uint32_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */
int result = 0;
KPrintf("\r\n SEMC SDRAM Memory 32 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
/* Prepare data and write to SDRAM. */
for (index = 0; index < datalen; index++)
{
sdram_writeBuffer[index] = index;
sdram[index] = sdram_writeBuffer[index];
}
KPrintf("\r\n SEMC SDRAM Read 32 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
/* Read data from the SDRAM. */
for (index = 0; index < datalen; index++)
{
sdram_readBuffer[index] = sdram[index];
}
KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Start!\r\n");
/* Compare the two buffers. */
while (datalen--)
{
if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen])
{
result = -1;
break;
}
}
if (result < 0)
{
KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Failed!\r\n");
}
else
{
KPrintf("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Succeed!\r\n");
}
}
static void SEMC_SDRAMReadWrite16Bit(void)
{
uint32_t index;
uint32_t datalen = SEMC_EXAMPLE_DATALEN;
uint16_t *sdram = (uint16_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */
int result = 0;
KPrintf("\r\n SEMC SDRAM Memory 16 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
memset(sdram_writeBuffer, 0, sizeof(sdram_writeBuffer));
memset(sdram_readBuffer, 0, sizeof(sdram_readBuffer));
/* Prepare data and write to SDRAM. */
for (index = 0; index < datalen; index++)
{
sdram_writeBuffer[index] = index % 0xFFFF;
sdram[index] = sdram_writeBuffer[index];
}
KPrintf("\r\n SEMC SDRAM Read 16 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
/* Read data from the SDRAM. */
for (index = 0; index < datalen; index++)
{
sdram_readBuffer[index] = sdram[index];
}
KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Start!\r\n");
/* Compare the two buffers. */
while (datalen--)
{
if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen])
{
result = -1;
break;
}
}
if (result < 0)
{
KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Failed!\r\n");
}
else
{
KPrintf("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Succeed!\r\n");
}
}
static void SEMC_SDRAMReadWrite8Bit(void)
{
uint32_t index;
uint32_t datalen = SEMC_EXAMPLE_DATALEN;
uint8_t *sdram = (uint8_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */
int result = 0;
KPrintf("\r\n SEMC SDRAM Memory 8 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
memset(sdram_writeBuffer, 0, sizeof(sdram_writeBuffer));
memset(sdram_readBuffer, 0, sizeof(sdram_readBuffer));
/* Prepare data and write to SDRAM. */
for (index = 0; index < datalen; index++)
{
sdram_writeBuffer[index] = index % 0x100;
sdram[index] = sdram_writeBuffer[index];
}
KPrintf("\r\n SEMC SDRAM Read 8 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
/* Read data from the SDRAM. */
for (index = 0; index < datalen; index++)
{
sdram_readBuffer[index] = sdram[index];
}
KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Start!\r\n");
/* Compare the two buffers. */
while (datalen--)
{
if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen])
{
result = -1;
break;
}
}
if (result < 0)
{
KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Failed!\r\n");
}
else
{
KPrintf("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Succeed!\r\n");
}
}