1.feat support GPIO driver for ok1052-c and xidatong board;2.fix ok1052-c board H file description
This commit is contained in:
Liu_Weichao
@@ -13,9 +13,9 @@
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/**
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* @file connect_gpio.h
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* @brief define imxrt1052-board gpio function and struct
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* @version 1.0
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* @version 2.0
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* @author AIIT XUOS Lab
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* @date 2022-03-01
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* @date 2022-03-15
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*/
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#ifndef __CONNECT_GPIO_H_
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@@ -27,7 +27,9 @@
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extern "C" {
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#endif
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int Stm32HwGpioInit(void);
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#define IMXRT_GET_PIN(PORTx, PIN) (32 * (PORTx - 1) + (PIN & 31)) /* PORTx:1,2,3,4,5 */
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int Imxrt1052HwGpioInit(void);
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#ifdef __cplusplus
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}
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@@ -13,9 +13,9 @@
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/**
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* @file connect_sdio.h
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* @brief define imxrt1052-board sdio function and struct
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* @version 2.0
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* @version 2.0
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* @author AIIT XUOS Lab
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* @date 2022-01-24
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* @date 2022-03-15
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*/
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#ifndef CONNECT_SDIO_H
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@@ -32,7 +32,7 @@
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extern "C" {
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#endif
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int Imrt1052HwSdioInit(void);
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int Imxrt1052HwSdioInit(void);
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#ifdef __cplusplus
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}
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@@ -13,9 +13,9 @@
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/**
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* @file connect_uart.h
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* @brief define imxrt1052-board usart function and struct
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* @version 1.0
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* @version 2.0
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* @author AIIT XUOS Lab
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* @date 2021-05-28
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* @date 2022-03-15
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*/
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#ifndef CONNECT_UART_H
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@@ -33,7 +33,7 @@ extern "C" {
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#define KERNEL_CONSOLE_DRV_NAME SERIAL_DRV_NAME_1
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#define KERNEL_CONSOLE_DEVICE_NAME SERIAL_1_DEVICE_NAME_0
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int Imrt1052HwUartInit(void);
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int Imxrt1052HwUartInit(void);
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#ifdef __cplusplus
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}
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@@ -13,9 +13,9 @@
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/**
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* @file connect_usb.h
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* @brief define imxrt1052-board usb function and struct
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* @version 2.0
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* @version 2.0
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* @author AIIT XUOS Lab
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* @date 2022-02-09
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* @date 2022-03-15
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*/
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#ifndef CONNECT_USB_H
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@@ -44,7 +44,7 @@ extern "C" {
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#define USB_SINGLE_BLOCK_SIZE 512
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int Imrt1052HwUsbHostInit(void);
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int Imxrt1052HwUsbHostInit(void);
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#ifdef __cplusplus
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}
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@@ -9,9 +9,9 @@
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/**
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* @file fsl_cache.h
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* @brief cache drivers
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* @version 1.0
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* @version 2.0
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* @author AIIT XUOS Lab
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* @date 2021.11.11
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* @date 2022-03-15
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*/
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#ifndef _FSL_CACHE_H_
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@@ -8,9 +8,9 @@
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/**
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* @file fsl_clock.h
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* @brief clock drivers
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* @version 1.0
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* @version 2.0
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* @author AIIT XUOS Lab
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* @date 2021.11.11
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* @date 2022-03-15
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*/
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#ifndef _FSL_CLOCK_H_
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@@ -9,9 +9,9 @@
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/**
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* @file fsl_common.h
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* @brief common drivers header
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* @version 1.0
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* @version 2.0
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* @author AIIT XUOS Lab
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* @date 2021.11.11
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* @date 2022-03-15
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*/
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#ifndef _FSL_COMMON_H_
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@@ -1,213 +0,0 @@
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/*
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* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2018 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Debug console shall provide input and output functions to scan and print formatted data.
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* o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"
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* - [flags] :'-', '+', '#', ' ', '0'
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* - [width]: number (0,1...)
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* - [.precision]: number (0,1...)
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* - [length]: do not support
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* - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'
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* o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"
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* - [*]: is supported.
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* - [width]: number (0,1...)
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* - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')
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* - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'
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*/
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#ifndef _FSL_DEBUGCONSOLE_H_
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#define _FSL_DEBUGCONSOLE_H_
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#include "fsl_common.h"
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#include "serial_manager.h"
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/*!
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* @addtogroup debugconsole
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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extern serial_handle_t g_serialHandle; /*!< serial manager handle */
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/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */
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#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */
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#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */
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#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */
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/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support
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* to be redefined in project setting.
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*/
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#ifndef SDK_DEBUGCONSOLE
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#define SDK_DEBUGCONSOLE 1U
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#endif
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/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. */
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#ifndef SDK_DEBUGCONSOLE_UART
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/* mcux will handle this macro, not define it here */
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#if (!defined(__MCUXPRESSO))
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#define SDK_DEBUGCONSOLE_UART
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#endif
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#endif
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#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
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#include <stdio.h>
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#endif
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/*! @brief Definition to select redirect toolchain printf, scanf to uart or not.
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*
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* if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf.
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* if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf.
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* if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function.
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*/
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#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */
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#define PRINTF
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#define SCANF
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#define PUTCHAR
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#define GETCHAR
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#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */
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#define PRINTF DbgConsole_Printf
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#define SCANF DbgConsole_Scanf
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#define PUTCHAR DbgConsole_Putchar
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#define GETCHAR DbgConsole_Getchar
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#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \
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*/
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#define PRINTF printf
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#define SCANF scanf
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#define PUTCHAR putchar
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#define GETCHAR getchar
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#endif /* SDK_DEBUGCONSOLE */
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus */
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/*! @name Initialization*/
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/* @{ */
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/*!
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* @brief Initializes the peripheral used for debug messages.
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*
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* Call this function to enable debug log messages to be output via the specified peripheral
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* initialized by the serial manager module.
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* After this function has returned, stdout and stdin are connected to the selected peripheral.
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*
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* @param instance The instance of the module.
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* @param baudRate The desired baud rate in bits per second.
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* @param device Low level device type for the debug console, can be one of the following.
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* @arg kSerialPort_Uart,
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* @arg kSerialPort_UsbCdc
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* @arg kSerialPort_UsbCdcVirtual.
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* @param clkSrcFreq Frequency of peripheral source clock.
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*
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* @return Indicates whether initialization was successful or not.
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* @retval kStatus_Success Execution successfully
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*/
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status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq);
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/*!
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* @brief De-initializes the peripheral used for debug messages.
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*
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* Call this function to disable debug log messages to be output via the specified peripheral
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* initialized by the serial manager module.
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*
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* @return Indicates whether de-initialization was successful or not.
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*/
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status_t DbgConsole_Deinit(void);
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#if SDK_DEBUGCONSOLE
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/*!
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* @brief Writes formatted output to the standard output stream.
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*
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* Call this function to write a formatted output to the standard output stream.
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*
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* @param formatString Format control string.
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* @return Returns the number of characters printed or a negative value if an error occurs.
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*/
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int DbgConsole_Printf(const char *formatString, ...);
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/*!
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* @brief Writes a character to stdout.
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*
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* Call this function to write a character to stdout.
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*
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* @param ch Character to be written.
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* @return Returns the character written.
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*/
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int DbgConsole_Putchar(int ch);
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/*!
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* @brief Reads formatted data from the standard input stream.
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*
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* Call this function to read formatted data from the standard input stream.
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*
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* @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
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* other tasks will not be scheduled), the function cannot be used when the
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* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
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* And an error is returned when the function called in this case. The suggestion
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* is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
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*
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* @param formatString Format control string.
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* @return Returns the number of fields successfully converted and assigned.
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*/
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int DbgConsole_Scanf(char *formatString, ...);
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/*!
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* @brief Reads a character from standard input.
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*
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* Call this function to read a character from standard input.
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*
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* @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
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* other tasks will not be scheduled), the function cannot be used when the
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* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
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* And an error is returned when the function called in this case. The suggestion
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* is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
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*
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* @return Returns the character read.
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*/
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int DbgConsole_Getchar(void);
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/*!
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* @brief Debug console flush.
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*
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* Call this function to wait the tx buffer empty.
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* If interrupt transfer is using, make sure the global IRQ is enable before call this function
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* This function should be called when
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* 1, before enter power down mode
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* 2, log is required to print to terminal immediately
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* @return Indicates whether wait idle was successful or not.
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*/
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status_t DbgConsole_Flush(void);
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#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
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/*!
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* @brief Debug console try to get char
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* This function provides a API which will not block current task, if character is
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* available return it, otherwise return fail.
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* @param ch the address of char to receive
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* @return Indicates get char was successful or not.
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*/
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status_t DbgConsole_TryGetchar(char *ch);
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#endif
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#endif /* SDK_DEBUGCONSOLE */
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/*! @} */
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus */
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/*! @} */
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#endif /* _FSL_DEBUGCONSOLE_H_ */
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@@ -1,158 +0,0 @@
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/*
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* Copyright 2017 - 2019 NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_DEBUG_CONSOLE_CONF_H_
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#define _FSL_DEBUG_CONSOLE_CONF_H_
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/****************Debug console configuration********************/
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/*! @brief If Non-blocking mode is needed, please define it at project setting,
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* otherwise blocking mode is the default transfer mode.
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* Warning: If you want to use non-blocking transfer,please make sure the corresponding
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* IO interrupt is enable, otherwise there is no output.
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* And non-blocking is combine with buffer, no matter bare-metal or rtos.
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* Below shows how to configure in your project if you want to use non-blocking mode.
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* For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols".
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* For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define".
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* For ARMGCC, open CmakeLists.txt and add the following lines,
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* "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target.
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* "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target.
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* For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C
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* Complier->Preprocessor".
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*
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*/
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#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
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/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically
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* when
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* non-blocking transfer is using,
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* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
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* If it is configured too small, log maybe missed , because the log will not be
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* buffered if the buffer is full, and the print will return immediately with -1.
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* And this value should be multiple of 4 to meet memory alignment.
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*
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*/
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#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN
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#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U)
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#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */
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/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when
|
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* non-blocking transfer is using,
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* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
|
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* If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small.
|
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* And this value should be multiple of 4 to meet memory alignment.
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*
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*/
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#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN
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#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U)
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#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */
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/*!@ brief Whether enable the reliable TX function
|
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* If the macro is zero, the reliable TX function of the debug console is disabled.
|
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* When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full.
|
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*/
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#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE
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#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U)
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#endif /* DEBUG_CONSOLE_RX_ENABLE */
|
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|
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#else
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#define DEBUG_CONSOLE_TRANSFER_BLOCKING
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#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
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|
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/*!@ brief Whether enable the RX function
|
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* If the macro is zero, the receive function of the debug console is disabled.
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*/
|
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#ifndef DEBUG_CONSOLE_RX_ENABLE
|
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#define DEBUG_CONSOLE_RX_ENABLE (1U)
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#endif /* DEBUG_CONSOLE_RX_ENABLE */
|
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|
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/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log
|
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* length can not bigger than this value.
|
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* This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if
|
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* the buffer is too big and current task stack size not big enough.
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*/
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#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN
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#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U)
|
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#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */
|
||||
|
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/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log
|
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* length can not bigger than this value.
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* As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN.
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*/
|
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#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN
|
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#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U)
|
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#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */
|
||||
|
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/*! @brief Debug console synchronization
|
||||
* User should not change these macro for synchronization mode, but add the
|
||||
* corresponding synchronization mechanism per different software environment.
|
||||
* Such as, if another RTOS is used,
|
||||
* add:
|
||||
* #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3
|
||||
* in this configuration file and implement the synchronization in fsl.log.c.
|
||||
*/
|
||||
/*! @brief synchronization for baremetal software */
|
||||
#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0
|
||||
/*! @brief synchronization for freertos software */
|
||||
#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1
|
||||
|
||||
/*! @brief RTOS synchronization mechanism disable
|
||||
* If not defined, default is enable, to avoid multitask log print mess.
|
||||
* If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c
|
||||
* If synchronization is disabled, log maybe messed on terminal.
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION
|
||||
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
|
||||
#ifdef FSL_RTOS_FREE_RTOS
|
||||
#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS
|
||||
#else
|
||||
#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
|
||||
#endif /* FSL_RTOS_FREE_RTOS */
|
||||
#else
|
||||
#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
|
||||
#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
|
||||
#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */
|
||||
|
||||
/*! @brief echo function support
|
||||
* If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO
|
||||
* at your project setting.
|
||||
*/
|
||||
#ifndef DEBUG_CONSOLE_ENABLE_ECHO
|
||||
#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0
|
||||
#else
|
||||
#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1
|
||||
#endif /* DEBUG_CONSOLE_ENABLE_ECHO */
|
||||
|
||||
/*********************************************************************/
|
||||
|
||||
/***************Debug console other configuration*********************/
|
||||
/*! @brief Definition to printf the float number. */
|
||||
#ifndef PRINTF_FLOAT_ENABLE
|
||||
#define PRINTF_FLOAT_ENABLE 0U
|
||||
#endif /* PRINTF_FLOAT_ENABLE */
|
||||
|
||||
/*! @brief Definition to scanf the float number. */
|
||||
#ifndef SCANF_FLOAT_ENABLE
|
||||
#define SCANF_FLOAT_ENABLE 0U
|
||||
#endif /* SCANF_FLOAT_ENABLE */
|
||||
|
||||
/*! @brief Definition to support advanced format specifier for printf. */
|
||||
#ifndef PRINTF_ADVANCED_ENABLE
|
||||
#define PRINTF_ADVANCED_ENABLE 0U
|
||||
#endif /* PRINTF_ADVANCED_ENABLE */
|
||||
|
||||
/*! @brief Definition to support advanced format specifier for scanf. */
|
||||
#ifndef SCANF_ADVANCED_ENABLE
|
||||
#define SCANF_ADVANCED_ENABLE 0U
|
||||
#endif /* SCANF_ADVANCED_ENABLE */
|
||||
|
||||
/*! @brief Definition to select virtual com(USB CDC) as the debug console. */
|
||||
#ifndef BOARD_USE_VIRTUALCOM
|
||||
#define BOARD_USE_VIRTUALCOM 0U
|
||||
#endif
|
||||
/*******************************************************************/
|
||||
|
||||
#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */
|
||||
@@ -7,6 +7,14 @@
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file fsl_device_registers.h
|
||||
* @brief device register function
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-03-15
|
||||
*/
|
||||
|
||||
#ifndef __FSL_DEVICE_REGISTERS_H__
|
||||
#define __FSL_DEVICE_REGISTERS_H__
|
||||
|
||||
|
||||
@@ -9,9 +9,9 @@
|
||||
/**
|
||||
* @file fsl_enet.h
|
||||
* @brief ethernet drivers
|
||||
* @version 1.0
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021.11.11
|
||||
* @date 2022-03-15
|
||||
*/
|
||||
|
||||
#ifndef _FSL_ENET_H_
|
||||
|
||||
@@ -6,6 +6,14 @@
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file fsl_gpio.h
|
||||
* @brief gpio drivers
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-03-15
|
||||
*/
|
||||
|
||||
#ifndef _FSL_GPIO_H_
|
||||
#define _FSL_GPIO_H_
|
||||
|
||||
|
||||
@@ -9,9 +9,9 @@
|
||||
/**
|
||||
* @file fsl_iomuxc.h
|
||||
* @brief io mux drivers
|
||||
* @version 1.0
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021.11.11
|
||||
* @date 2022-03-15
|
||||
*/
|
||||
|
||||
#ifndef _FSL_IOMUXC_H_
|
||||
|
||||
@@ -7,12 +7,12 @@
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file fsl_lpi2c.h
|
||||
* @brief support imxrt1052-board i2c driver
|
||||
* @version 1.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-03-01
|
||||
*/
|
||||
* @file fsl_lpi2c.h
|
||||
* @brief support imxrt1052-board i2c driver
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-03-15
|
||||
*/
|
||||
|
||||
#ifndef _FSL_LPI2C_H_
|
||||
#define _FSL_LPI2C_H_
|
||||
|
||||
@@ -9,9 +9,9 @@
|
||||
/**
|
||||
* @file fsl_lpuart.h
|
||||
* @brief fsl uart drivers
|
||||
* @version 1.0
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2021.11.11
|
||||
* @date 2022-03-15
|
||||
*/
|
||||
|
||||
#ifndef _FSL_LPUART_H_
|
||||
|
||||
@@ -1,830 +0,0 @@
|
||||
/*
|
||||
* Copyright 2017-2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef _FSL_SEMC_H_
|
||||
#define _FSL_SEMC_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup semc
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief SEMC driver version 2.0.4. */
|
||||
#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief SEMC status. */
|
||||
enum _semc_status
|
||||
{
|
||||
kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0),
|
||||
kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1),
|
||||
kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2),
|
||||
kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3),
|
||||
kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4),
|
||||
kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5),
|
||||
kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6),
|
||||
kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7),
|
||||
kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8),
|
||||
kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9),
|
||||
kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10),
|
||||
kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11),
|
||||
};
|
||||
|
||||
/*! @brief SEMC memory device type. */
|
||||
typedef enum _semc_mem_type
|
||||
{
|
||||
kSEMC_MemType_SDRAM = 0, /*!< SDRAM */
|
||||
kSEMC_MemType_SRAM, /*!< SRAM */
|
||||
kSEMC_MemType_NOR, /*!< NOR */
|
||||
kSEMC_MemType_NAND, /*!< NAND */
|
||||
kSEMC_MemType_8080 /*!< 8080. */
|
||||
} semc_mem_type_t;
|
||||
|
||||
/*! @brief SEMC WAIT/RDY polarity. */
|
||||
typedef enum _semc_waitready_polarity
|
||||
{
|
||||
kSEMC_LowActive = 0, /*!< Low active. */
|
||||
kSEMC_HighActive, /*!< High active. */
|
||||
} semc_waitready_polarity_t;
|
||||
|
||||
/*! @brief SEMC SDRAM Chip selection . */
|
||||
typedef enum _semc_sdram_cs
|
||||
{
|
||||
kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */
|
||||
kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */
|
||||
kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */
|
||||
kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */
|
||||
} semc_sdram_cs_t;
|
||||
|
||||
/*! @brief SEMC NAND device type. */
|
||||
typedef enum _semc_nand_access_type
|
||||
{
|
||||
kSEMC_NAND_ACCESS_BY_AXI = 0,
|
||||
kSEMC_NAND_ACCESS_BY_IPCMD,
|
||||
} semc_nand_access_type_t;
|
||||
|
||||
/*! @brief SEMC interrupts . */
|
||||
typedef enum _semc_interrupt_enable
|
||||
{
|
||||
kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */
|
||||
kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */
|
||||
kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */
|
||||
kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */
|
||||
} semc_interrupt_enable_t;
|
||||
|
||||
/*! @brief SEMC IP command data size in bytes. */
|
||||
typedef enum _semc_ipcmd_datasize
|
||||
{
|
||||
kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */
|
||||
kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */
|
||||
kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */
|
||||
kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */
|
||||
} semc_ipcmd_datasize_t;
|
||||
|
||||
/*! @brief SEMC auto-refresh timing. */
|
||||
typedef enum _semc_refresh_time
|
||||
{
|
||||
kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */
|
||||
kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */
|
||||
kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */
|
||||
} semc_refresh_time_t;
|
||||
|
||||
/*! @brief CAS latency */
|
||||
typedef enum _semc_caslatency
|
||||
{
|
||||
kSEMC_LatencyOne = 1, /*!< Latency 1. */
|
||||
kSEMC_LatencyTwo, /*!< Latency 2. */
|
||||
kSEMC_LatencyThree, /*!< Latency 3. */
|
||||
} semc_caslatency_t;
|
||||
|
||||
/*! @brief SEMC sdram column address bit number. */
|
||||
typedef enum _semc_sdram_column_bit_num
|
||||
{
|
||||
kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */
|
||||
kSEMC_SdramColunm_11bit, /*!< 11 bit. */
|
||||
kSEMC_SdramColunm_10bit, /*!< 10 bit. */
|
||||
kSEMC_SdramColunm_9bit, /*!< 9 bit. */
|
||||
} semc_sdram_column_bit_num_t;
|
||||
|
||||
/*! @brief SEMC sdram burst length. */
|
||||
typedef enum _semc_sdram_burst_len
|
||||
{
|
||||
kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/
|
||||
kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/
|
||||
kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/
|
||||
kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/
|
||||
} sem_sdram_burst_len_t;
|
||||
|
||||
/*! @brief SEMC nand column address bit number. */
|
||||
typedef enum _semc_nand_column_bit_num
|
||||
{
|
||||
kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */
|
||||
kSEMC_NandColum_15bit, /*!< 15 bit. */
|
||||
kSEMC_NandColum_14bit, /*!< 14 bit. */
|
||||
kSEMC_NandColum_13bit, /*!< 13 bit. */
|
||||
kSEMC_NandColum_12bit, /*!< 12 bit. */
|
||||
kSEMC_NandColum_11bit, /*!< 11 bit. */
|
||||
kSEMC_NandColum_10bit, /*!< 10 bit. */
|
||||
kSEMC_NandColum_9bit, /*!< 9 bit. */
|
||||
} semc_nand_column_bit_num_t;
|
||||
|
||||
/*! @brief SEMC nand burst length. */
|
||||
typedef enum _semc_nand_burst_len
|
||||
{
|
||||
kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/
|
||||
kSEMC_Nand_BurstLen2, /*!< Burst length 2*/
|
||||
kSEMC_Nand_BurstLen4, /*!< Burst length 4*/
|
||||
kSEMC_Nand_BurstLen8, /*!< Burst length 8*/
|
||||
kSEMC_Nand_BurstLen16, /*!< Burst length 16*/
|
||||
kSEMC_Nand_BurstLen32, /*!< Burst length 32*/
|
||||
kSEMC_Nand_BurstLen64 /*!< Burst length 64*/
|
||||
} sem_nand_burst_len_t;
|
||||
|
||||
/*! @brief SEMC nor/sram column address bit number. */
|
||||
typedef enum _semc_norsram_column_bit_num
|
||||
{
|
||||
kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */
|
||||
kSEMC_NorColum_11bit, /*!< 11 bit. */
|
||||
kSEMC_NorColum_10bit, /*!< 10 bit. */
|
||||
kSEMC_NorColum_9bit, /*!< 9 bit. */
|
||||
kSEMC_NorColum_8bit, /*!< 8 bit. */
|
||||
kSEMC_NorColum_7bit, /*!< 7 bit. */
|
||||
kSEMC_NorColum_6bit, /*!< 6 bit. */
|
||||
kSEMC_NorColum_5bit, /*!< 5 bit. */
|
||||
kSEMC_NorColum_4bit, /*!< 4 bit. */
|
||||
kSEMC_NorColum_3bit, /*!< 3 bit. */
|
||||
kSEMC_NorColum_2bit /*!< 2 bit. */
|
||||
} semc_norsram_column_bit_num_t;
|
||||
|
||||
/*! @brief SEMC nor/sram burst length. */
|
||||
typedef enum _semc_norsram_burst_len
|
||||
{
|
||||
kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/
|
||||
kSEMC_Nor_BurstLen2, /*!< Burst length 2*/
|
||||
kSEMC_Nor_BurstLen4, /*!< Burst length 4*/
|
||||
kSEMC_Nor_BurstLen8, /*!< Burst length 8*/
|
||||
kSEMC_Nor_BurstLen16, /*!< Burst length 16*/
|
||||
kSEMC_Nor_BurstLen32, /*!< Burst length 32*/
|
||||
kSEMC_Nor_BurstLen64 /*!< Burst length 64*/
|
||||
} sem_norsram_burst_len_t;
|
||||
|
||||
/*! @brief SEMC dbi column address bit number. */
|
||||
typedef enum _semc_dbi_column_bit_num
|
||||
{
|
||||
kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */
|
||||
kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */
|
||||
kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */
|
||||
kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */
|
||||
kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */
|
||||
kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */
|
||||
kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */
|
||||
kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */
|
||||
kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */
|
||||
kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */
|
||||
kSEMC_Dbi_Colum_2bit /*!< 2 bit. */
|
||||
} semc_dbi_column_bit_num_t;
|
||||
|
||||
/*! @brief SEMC dbi burst length. */
|
||||
typedef enum _semc_dbi_burst_len
|
||||
{
|
||||
kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/
|
||||
kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/
|
||||
kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/
|
||||
kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/
|
||||
kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/
|
||||
kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/
|
||||
kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/
|
||||
} sem_dbi_burst_len_t;
|
||||
|
||||
/*! @brief SEMC IOMUXC. */
|
||||
typedef enum _semc_iomux_pin
|
||||
{
|
||||
kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */
|
||||
kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */
|
||||
kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/
|
||||
kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */
|
||||
kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
|
||||
kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
|
||||
} semc_iomux_pin;
|
||||
|
||||
/*! @brief SEMC NOR/PSRAM Address bit 27 A27. */
|
||||
typedef enum _semc_iomux_nora27_pin
|
||||
{
|
||||
kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */
|
||||
kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
|
||||
kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
|
||||
} semc_iomux_nora27_pin;
|
||||
|
||||
/*! @brief SEMC port size. */
|
||||
typedef enum _semc_port_size
|
||||
{
|
||||
kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */
|
||||
kSEMC_PortSize16Bit /*!< 16-Bit port size. */
|
||||
} smec_port_size_t;
|
||||
|
||||
/*! @brief SEMC address mode. */
|
||||
typedef enum _semc_addr_mode
|
||||
{
|
||||
kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */
|
||||
kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */
|
||||
kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */
|
||||
} semc_addr_mode_t;
|
||||
|
||||
/*! @brief SEMC DQS read strobe mode. */
|
||||
typedef enum _semc_dqs_mode
|
||||
{
|
||||
kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */
|
||||
kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */
|
||||
} semc_dqs_mode_t;
|
||||
|
||||
/*! @brief SEMC ADV signal active polarity. */
|
||||
typedef enum _semc_adv_polarity
|
||||
{
|
||||
kSEMC_AdvActiveLow = 0, /*!< Adv active low. */
|
||||
kSEMC_AdvActivehigh, /*!< Adv active low. */
|
||||
} semc_adv_polarity_t;
|
||||
|
||||
/*! @brief SEMC RDY signal active polarity. */
|
||||
typedef enum _semc_rdy_polarity
|
||||
{
|
||||
kSEMC_RdyActiveLow = 0, /*!< Adv active low. */
|
||||
kSEMC_RdyActivehigh, /*!< Adv active low. */
|
||||
} semc_rdy_polarity_t;
|
||||
|
||||
/*! @brief SEMC IP command for NAND: address mode. */
|
||||
typedef enum _semc_ipcmd_nand_addrmode
|
||||
{
|
||||
kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */
|
||||
kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */
|
||||
kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */
|
||||
kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */
|
||||
kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */
|
||||
kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */
|
||||
} semc_ipcmd_nand_addrmode_t;
|
||||
|
||||
/*! @brief SEMC IP command for NAND： command mode. */
|
||||
typedef enum _semc_ipcmd_nand_cmdmode
|
||||
{
|
||||
kSEMC_NANDCM_Command = 0x2U, /*!< command. */
|
||||
kSEMC_NANDCM_CommandHold, /*!< Command hold. */
|
||||
kSEMC_NANDCM_CommandAddress, /*!< Command address. */
|
||||
kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */
|
||||
kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */
|
||||
kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */
|
||||
kSEMC_NANDCM_CommandRead, /*!< Command read. */
|
||||
kSEMC_NANDCM_CommandWrite, /*!< Command write. */
|
||||
kSEMC_NANDCM_Read, /*!< Read. */
|
||||
kSEMC_NANDCM_Write /*!< Write. */
|
||||
} semc_ipcmd_nand_cmdmode_t;
|
||||
|
||||
/*! @brief SEMC NAND address option. */
|
||||
typedef enum _semc_nand_address_option
|
||||
{
|
||||
kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */
|
||||
kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */
|
||||
kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */
|
||||
kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */
|
||||
kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */
|
||||
kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */
|
||||
} semc_nand_address_option_t;
|
||||
|
||||
/*! @brief SEMC IP command for NOR. */
|
||||
typedef enum _semc_ipcmd_nor_dbi
|
||||
{
|
||||
kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */
|
||||
kSEMC_NORDBICM_Write /*!< NOR write. */
|
||||
} semc_ipcmd_nor_dbi_t;
|
||||
|
||||
/*! @brief SEMC IP command for SRAM. */
|
||||
typedef enum _semc_ipcmd_sram
|
||||
{
|
||||
kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */
|
||||
kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */
|
||||
kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */
|
||||
kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */
|
||||
} semc_ipcmd_sram_t;
|
||||
|
||||
/*! @brief SEMC IP command for SDARM. */
|
||||
typedef enum _semc_ipcmd_sdram
|
||||
{
|
||||
kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */
|
||||
kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */
|
||||
kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */
|
||||
kSEMC_SDRAMCM_Active, /*!< SDRAM active. */
|
||||
kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */
|
||||
kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */
|
||||
kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */
|
||||
kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */
|
||||
} semc_ipcmd_sdram_t;
|
||||
|
||||
/*! @brief SEMC SDRAM configuration structure.
|
||||
*
|
||||
* 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes
|
||||
* should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function.
|
||||
* Take refer to BR0~BR3 register in RM for details.
|
||||
* 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0,
|
||||
* it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0,
|
||||
* The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles.
|
||||
* idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are
|
||||
* similar to prescalePeriod_N16Cycle.
|
||||
*
|
||||
*/
|
||||
typedef struct _semc_sdram_config
|
||||
{
|
||||
semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */
|
||||
uint32_t address; /*!< The base address. */
|
||||
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
|
||||
smec_port_size_t portSize; /*!< Port size. */
|
||||
sem_sdram_burst_len_t burstLen; /*!< Burst length. */
|
||||
semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
|
||||
semc_caslatency_t casLatency; /*!< CAS latency. */
|
||||
uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */
|
||||
uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */
|
||||
uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */
|
||||
uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */
|
||||
uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */
|
||||
uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */
|
||||
uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */
|
||||
uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */
|
||||
uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */
|
||||
uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */
|
||||
uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */
|
||||
uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */
|
||||
uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */
|
||||
uint8_t refreshBurstLen; /*!< Refresh burst length. */
|
||||
} semc_sdram_config_t;
|
||||
|
||||
/*! @brief SEMC NAND device timing configuration structure. */
|
||||
typedef struct _semc_nand_timing_config
|
||||
{
|
||||
uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */
|
||||
uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */
|
||||
uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */
|
||||
uint8_t tWeLow_Ns; /*!< WE low time: tWP. */
|
||||
uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */
|
||||
uint8_t tReLow_Ns; /*!< RE low time: tRP. */
|
||||
uint8_t tReHigh_Ns; /*!< RE high time: tREH. */
|
||||
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */
|
||||
uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */
|
||||
uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */
|
||||
uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */
|
||||
uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */
|
||||
uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */
|
||||
} semc_nand_timing_config_t;
|
||||
|
||||
/*! @brief SEMC NAND configuration structure. */
|
||||
typedef struct _semc_nand_config
|
||||
{
|
||||
semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */
|
||||
uint32_t axiAddress; /*!< The base address for AXI nand. */
|
||||
uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */
|
||||
uint32_t ipgAddress; /*!< The base address for IPG nand . */
|
||||
uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */
|
||||
semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
|
||||
bool edoModeEnabled; /*!< EDO mode enabled. */
|
||||
semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
|
||||
semc_nand_address_option_t arrayAddrOption; /*!< Address option. */
|
||||
sem_nand_burst_len_t burstLen; /*!< Burst length. */
|
||||
smec_port_size_t portSize; /*!< Port size. */
|
||||
semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */
|
||||
} semc_nand_config_t;
|
||||
|
||||
/*! @brief SEMC NOR configuration structure. */
|
||||
typedef struct _semc_nor_config
|
||||
{
|
||||
semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
|
||||
semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
|
||||
uint32_t address; /*!< The base address. */
|
||||
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
|
||||
uint8_t addrPortWidth; /*!< The address port width. */
|
||||
semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
|
||||
semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */
|
||||
semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
|
||||
semc_addr_mode_t addrMode; /*!< Address mode. */
|
||||
sem_norsram_burst_len_t burstLen; /*!< Burst length. */
|
||||
smec_port_size_t portSize; /*!< Port size. */
|
||||
uint8_t tCeSetup_Ns; /*!< The CE setup time. */
|
||||
uint8_t tCeHold_Ns; /*!< The CE hold time. */
|
||||
uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
|
||||
uint8_t tAddrSetup_Ns; /*!< The address setup time. */
|
||||
uint8_t tAddrHold_Ns; /*!< The address hold time. */
|
||||
uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
|
||||
uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
|
||||
uint8_t tReLow_Ns; /*!< RE low time for async mode. */
|
||||
uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
|
||||
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
|
||||
uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
|
||||
#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME)
|
||||
uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME)
|
||||
uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
|
||||
#endif
|
||||
uint8_t latencyCount; /*!< Latency count for sync mode. */
|
||||
uint8_t readCycle; /*!< Read cycle time for sync mode. */
|
||||
} semc_nor_config_t;
|
||||
|
||||
/*! @brief SEMC SRAM configuration structure. */
|
||||
typedef struct _semc_sram_config
|
||||
{
|
||||
semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
|
||||
semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
|
||||
uint32_t address; /*!< The base address. */
|
||||
uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
|
||||
uint8_t addrPortWidth; /*!< The address port width. */
|
||||
semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */
|
||||
semc_addr_mode_t addrMode; /*!< Address mode. */
|
||||
sem_norsram_burst_len_t burstLen; /*!< Burst length. */
|
||||
smec_port_size_t portSize; /*!< Port size. */
|
||||
uint8_t tCeSetup_Ns; /*!< The CE setup time. */
|
||||
uint8_t tCeHold_Ns; /*!< The CE hold time. */
|
||||
uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
|
||||
uint8_t tAddrSetup_Ns; /*!< The address setup time. */
|
||||
uint8_t tAddrHold_Ns; /*!< The address hold time. */
|
||||
uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
|
||||
uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
|
||||
uint8_t tReLow_Ns; /*!< RE low time for async mode. */
|
||||
uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
|
||||
uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
|
||||
uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
|
||||
uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
|
||||
uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
|
||||
uint8_t latencyCount; /*!< Latency count for sync mode. */
|
||||
uint8_t readCycle; /*!< Read cycle time for sync mode. */
|
||||
} semc_sram_config_t;
|
||||
|
||||
/*! @brief SEMC DBI configuration structure. */
|
||||
typedef struct _semc_dbi_config
|
||||
{
|
||||
semc_iomux_pin csxPinMux; /*!< The CE# pin mux. */
|
||||
uint32_t address; /*!< The base address. */
|
||||
uint32_t memsize_kbytes; /*!< The memory size in unit of 4kbytes. */
|
||||
semc_dbi_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
|
||||
sem_dbi_burst_len_t burstLen; /*!< Burst length. */
|
||||
smec_port_size_t portSize; /*!< Port size. */
|
||||
uint8_t tCsxSetup_Ns; /*!< The CSX setup time. */
|
||||
uint8_t tCsxHold_Ns; /*!< The CSX hold time. */
|
||||
uint8_t tWexLow_Ns; /*!< WEX low time. */
|
||||
uint8_t tWexHigh_Ns; /*!< WEX high time. */
|
||||
uint8_t tRdxLow_Ns; /*!< RDX low time. */
|
||||
uint8_t tRdxHigh_Ns; /*!< RDX high time. */
|
||||
uint8_t tCsxInterval_Ns; /*!< Write data setup time.*/
|
||||
} semc_dbi_config_t;
|
||||
|
||||
/*! @brief SEMC AXI queue a weight setting structure. */
|
||||
typedef struct _semc_queuea_weight_struct
|
||||
{
|
||||
uint32_t qos : 4; /*!< weight of qos for queue 0 . */
|
||||
uint32_t aging : 4; /*!< weight of aging for queue 0.*/
|
||||
uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 0.*/
|
||||
uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 0 .*/
|
||||
} semc_queuea_weight_struct_t;
|
||||
|
||||
/*! @brief SEMC AXI queue a weight setting union. */
|
||||
typedef union _semc_queuea_weight
|
||||
{
|
||||
semc_queuea_weight_struct_t queueaConfig; /*!< Structure configuration for queueA. */
|
||||
uint32_t queueaValue; /*!< Configuration value for queueA which could directly write to the reg. */
|
||||
} semc_queuea_weight_t;
|
||||
|
||||
/*! @brief SEMC AXI queue b weight setting structure. */
|
||||
typedef struct _semc_queueb_weight_struct
|
||||
{
|
||||
uint32_t qos : 4; /*!< weight of qos for queue 1. */
|
||||
uint32_t aging : 4; /*!< weight of aging for queue 1.*/
|
||||
uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 1.*/
|
||||
uint32_t weightPagehit : 8; /*!< weight of page hit for queue 1 only .*/
|
||||
uint32_t bankRotation : 8; /*!< weight of bank rotation for queue 1 only .*/
|
||||
} semc_queueb_weight_struct_t;
|
||||
|
||||
/*! @brief SEMC AXI queue b weight setting union. */
|
||||
typedef union _semc_queueb_weight
|
||||
{
|
||||
semc_queueb_weight_struct_t queuebConfig; /*!< Structure configuration for queueB. */
|
||||
uint32_t queuebValue; /*!< Configuration value for queueB which could directly write to the reg. */
|
||||
} semc_queueb_weight_t;
|
||||
|
||||
/*! @brief SEMC AXI queue weight setting. */
|
||||
typedef struct _semc_axi_queueweight
|
||||
{
|
||||
semc_queuea_weight_t queueaWeight; /*!< Weight settings for queue a. */
|
||||
semc_queueb_weight_t queuebWeight; /*!< Weight settings for queue b. */
|
||||
} semc_axi_queueweight_t;
|
||||
|
||||
/*!
|
||||
* @brief SEMC configuration structure.
|
||||
*
|
||||
* busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is
|
||||
* 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024.
|
||||
* cmdTimeoutCycles: is used for command execution timeout cycles. it's
|
||||
* similar to the busTimeoutCycles.
|
||||
*/
|
||||
typedef struct _semc_config_t
|
||||
{
|
||||
semc_dqs_mode_t dqsMode; /*!< Dummy read strobe mode: use enum in "semc_dqs_mode_t". */
|
||||
uint8_t cmdTimeoutCycles; /*!< Command execution timeout cycles. */
|
||||
uint8_t busTimeoutCycles; /*!< Bus timeout cycles. */
|
||||
semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */
|
||||
} semc_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name SEMC Initialization and De-initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Gets the SEMC default basic configuration structure.
|
||||
*
|
||||
* The purpose of this API is to get the default SEMC
|
||||
* configure structure for SEMC_Init(). User may use the initialized
|
||||
* structure unchanged in SEMC_Init(), or modify some fields of the
|
||||
* structure before calling SEMC_Init().
|
||||
* Example:
|
||||
@code
|
||||
semc_config_t config;
|
||||
SEMC_GetDefaultConfig(&config);
|
||||
@endcode
|
||||
* @param config The SEMC configuration structure pointer.
|
||||
*/
|
||||
void SEMC_GetDefaultConfig(semc_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Initializes SEMC.
|
||||
* This function ungates the SEMC clock and initializes SEMC.
|
||||
* This function must be called before calling any other SEMC driver functions.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param configure The SEMC configuration structure pointer.
|
||||
*/
|
||||
void SEMC_Init(SEMC_Type *base, semc_config_t *configure);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the SEMC module and gates the clock.
|
||||
*
|
||||
* This function gates the SEMC clock. As a result, the SEMC module doesn't work after
|
||||
* calling this function, for some IDE, calling this API may cause the next downloading
|
||||
* operation failed. so, please call this API cautiously. Additional, users can
|
||||
* using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control
|
||||
* operation in drivers.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
*/
|
||||
void SEMC_Deinit(SEMC_Type *base);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name SEMC Configuration Operation For Each Memory Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Configures SDRAM controller in SEMC.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param cs The chip selection.
|
||||
* @param config The sdram configuration.
|
||||
* @param clkSrc_Hz The SEMC clock frequency.
|
||||
*/
|
||||
status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Configures NAND controller in SEMC.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param config The nand configuration.
|
||||
* @param clkSrc_Hz The SEMC clock frequency.
|
||||
*/
|
||||
status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Configures NOR controller in SEMC.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param config The nor configuration.
|
||||
* @param clkSrc_Hz The SEMC clock frequency.
|
||||
*/
|
||||
status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Configures SRAM controller in SEMC.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param config The sram configuration.
|
||||
* @param clkSrc_Hz The SEMC clock frequency.
|
||||
*/
|
||||
status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Configures DBI controller in SEMC.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param config The dbi configuration.
|
||||
* @param clkSrc_Hz The SEMC clock frequency.
|
||||
*/
|
||||
status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name SEMC Interrupt Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables the SEMC interrupt.
|
||||
*
|
||||
* This function enables the SEMC interrupts according to the provided mask. The mask
|
||||
* is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
|
||||
* For example, to enable the IP command done and error interrupt, do the following.
|
||||
* @code
|
||||
* SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
|
||||
* @endcode
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param mask SEMC interrupts to enable. This is a logical OR of the
|
||||
* enumeration :: semc_interrupt_enable_t.
|
||||
*/
|
||||
static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask)
|
||||
{
|
||||
base->INTEN |= mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables the SEMC interrupt.
|
||||
*
|
||||
* This function disables the SEMC interrupts according to the provided mask. The mask
|
||||
* is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
|
||||
* For example, to disable the IP command done and error interrupt, do the following.
|
||||
* @code
|
||||
* SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
|
||||
* @endcode
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param mask SEMC interrupts to disable. This is a logical OR of the
|
||||
* enumeration :: semc_interrupt_enable_t.
|
||||
*/
|
||||
static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask)
|
||||
{
|
||||
base->INTEN &= ~mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the SEMC status.
|
||||
*
|
||||
* This function gets the SEMC interrupts event status.
|
||||
* User can use the a logical OR of enumeration member as a mask.
|
||||
* See @ref semc_interrupt_enable_t.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @return status flag, use status flag in semc_interrupt_enable_t to get the related status.
|
||||
*/
|
||||
static inline bool SEMC_GetStatusFlag(SEMC_Type *base)
|
||||
{
|
||||
return base->INTR;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears the SEMC status flag state.
|
||||
*
|
||||
* The following status register flags can be cleared SEMC interrupt status.
|
||||
*
|
||||
* @param base SEMC base pointer
|
||||
* @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t.
|
||||
*/
|
||||
static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask)
|
||||
{
|
||||
base->INTR |= mask;
|
||||
}
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name SEMC Memory Access Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Check if SEMC is in idle.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @return True SEMC is in idle, false is not in idle.
|
||||
*/
|
||||
static inline bool SEMC_IsInIdle(SEMC_Type *base)
|
||||
{
|
||||
return (base->STS0 & SEMC_STS0_IDLE_MASK) ? true : false;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief SEMC IP command access.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param type SEMC memory type. refer to "semc_mem_type_t"
|
||||
* @param address SEMC device address.
|
||||
* @param command SEMC IP command.
|
||||
* For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command.
|
||||
* For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t".
|
||||
* For SRAM device, take refer to "semc_ipcmd_sram_t".
|
||||
* For SDRAM device, take refer to "semc_ipcmd_sdram_t".
|
||||
* @param write Data for write access.
|
||||
* @param read Data pointer for read data out.
|
||||
*/
|
||||
status_t SEMC_SendIPCommand(
|
||||
SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read);
|
||||
|
||||
/*!
|
||||
* @brief Build SEMC IP command for NAND.
|
||||
*
|
||||
* This function build SEMC NAND IP command. The command is build of user command code,
|
||||
* SEMC address mode and SEMC command mode.
|
||||
*
|
||||
* @param userCommand NAND device normal command.
|
||||
* @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t".
|
||||
* @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t".
|
||||
*/
|
||||
static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand,
|
||||
semc_ipcmd_nand_addrmode_t addrMode,
|
||||
semc_ipcmd_nand_cmdmode_t cmdMode)
|
||||
{
|
||||
return (uint16_t)((uint16_t)userCommand << 8) | (uint16_t)(addrMode << 4) | ((uint8_t)cmdMode & 0x0Fu);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Check if the NAND device is ready.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @return True NAND is ready, false NAND is not ready.
|
||||
*/
|
||||
static inline bool SEMC_IsNandReady(SEMC_Type *base)
|
||||
{
|
||||
return (base->STS0 & SEMC_STS0_NARDY_MASK) ? true : false;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief SEMC NAND device memory write through IP command.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param address SEMC NAND device address.
|
||||
* @param data Data for write access.
|
||||
* @param size_bytes Data length.
|
||||
*/
|
||||
status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
|
||||
|
||||
/*!
|
||||
* @brief SEMC NAND device memory read through IP command.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param address SEMC NAND device address.
|
||||
* @param data Data pointer for data read out.
|
||||
* @param size_bytes Data length.
|
||||
*/
|
||||
status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
|
||||
|
||||
/*!
|
||||
* @brief SEMC NOR device memory write through IP command.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param address SEMC NOR device address.
|
||||
* @param data Data for write access.
|
||||
* @param size_bytes Data length.
|
||||
*/
|
||||
status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
|
||||
|
||||
/*!
|
||||
* @brief SEMC NOR device memory read through IP command.
|
||||
*
|
||||
* @param base SEMC peripheral base address.
|
||||
* @param address SEMC NOR device address.
|
||||
* @param data Data pointer for data read out.
|
||||
* @param size_bytes Data length.
|
||||
*/
|
||||
status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_SEMC_H_*/
|
||||
@@ -5,6 +5,15 @@
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file fsl_usdhc.h
|
||||
* @brief fsl usdhc drivers
|
||||
* @version 2.0
|
||||
* @author AIIT XUOS Lab
|
||||
* @date 2022-03-15
|
||||
*/
|
||||
|
||||
#ifndef _FSL_USDHC_H_
|
||||
#define _FSL_USDHC_H_
|
||||
|
||||
|
||||
Reference in New Issue
Block a user